* [U-Boot] [PATCH 01/93] Add a simple script to remove boards
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 18:19 ` Adam Ford
2018-11-19 15:52 ` [U-Boot] [PATCH 02/93] dm: mmc: Use CONFIG_IS_ENABLED to check for BLK Simon Glass
` (96 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This script attempts to create a git commit which removes a single board.
It is quite fallible and everything it does needs checking. But it can
help speed up the process.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
tools/rmboard.py | 145 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 145 insertions(+)
create mode 100755 tools/rmboard.py
diff --git a/tools/rmboard.py b/tools/rmboard.py
new file mode 100755
index 00000000000..c6be434c9ed
--- /dev/null
+++ b/tools/rmboard.py
@@ -0,0 +1,145 @@
+#! /usr/bin/python
+
+'''
+Script to remove boards
+
+Usage:
+ rmboard.py <board_name>...
+
+A single commit is created for each board removed.
+
+Some boards may depend on files provided by another and this will cause
+problems.
+
+This script works by:
+ - Looking through the MAINTAINERS files which mention a board to find out
+ what files the board uses
+ - Looking through the Kconfig files which mention a board to find one that
+ needs to have material removed
+'''
+
+import glob
+import os
+import re
+import sys
+
+# Bring in the patman libraries
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '../patman'))
+
+import command
+
+def rm_kconfig_include(path):
+ """Remove a path from Kconfig files
+
+ This function finds the given path in a 'source' statement in a Kconfig
+ file and removes that line from the file. This is needed because the path
+ is going to be removed, so any reference to it will cause a problem with
+ Kconfig parsing.
+
+ The changes are made locally and then added to the git staging area.
+
+ Args:
+ path: Path to search for and remove
+ """
+ print 'path', path
+ cmd = ['git', 'grep', path]
+ stdout = command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
+ if not stdout:
+ return
+ fname = stdout.split(':')[0]
+
+ print "Fixing up '%s' to remove reference to '%s'" % (fname, path)
+ cmd = ['sed', '-i', '\|%s|d' % path, fname]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+ cmd = ['git', 'add', fname]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+def rm_board(board):
+ """Handle creating a commit which removes a single board
+
+ Args:
+ board: Board name to remove
+ """
+
+ # Find all MAINTAINERS and Kconfig files which mention the board
+ cmd = ['git', 'grep', '-l', board]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+ maintain = []
+ kconfig = []
+ for line in stdout.splitlines():
+ line = line.strip()
+ if 'MAINTAINERS' in line:
+ if line not in maintain:
+ maintain.append(line)
+ elif 'Kconfig' in line:
+ kconfig.append(line)
+ paths = []
+ cc = []
+ print 'maintain', maintain
+
+ # Look through the MAINTAINERS file to find things to remove
+ for fname in maintain:
+ with open(fname) as fd:
+ for line in fd:
+ line = line.strip()
+ fields = re.split('[ \t]', line, 1)
+ print fields
+ if len(fields) == 2:
+ if fields[0] == 'M:':
+ cc.append(fields[1])
+ elif fields[0] == 'F:':
+ paths.append(fields[1].strip())
+ print 'paths', paths
+
+ # Expannd any wildcards in the MAINTAINRERS file
+ real = []
+ for path in paths:
+ if path[-1] == '/':
+ path = path[:-1]
+ if '*' in path:
+ globbed = glob.glob(path)
+ print "Expanded '%s' to '%s'" % (path, globbed)
+ real += globbed
+ else:
+ real.append(path)
+ print 'real', real
+
+ # Search for Kconfig files in the resulting list. Remove any 'source' lines
+ # which referenced Kconfig files we want to remove
+ for path in real:
+ cmd = ['find', path]
+ stdout = (command.RunPipe([cmd], capture=True, raise_on_error=False).
+ stdout)
+ for fname in stdout.splitlines():
+ if fname.endswith('Kconfig'):
+ rm_kconfig_include(fname)
+
+ # Remove unwanted files
+ cmd = ['git', 'rm', '-r'] + real
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+ # Change the messages as needed
+ msg = '''arm: Remove %s board
+
+This board has not been converted to CONFIG_DM_BLK by the deadline.
+Remove it.
+
+''' % board
+ for name in cc:
+ msg += 'Patch-cc: %s\n' % name
+
+ # Create the commit
+ cmd = ['git', 'commit', '-s', '-m', msg]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+ print kconfig
+
+ # Check if the board is mentioned anywhere else. The user will need to deal
+ # with this
+ cmd = ['git', 'grep', '-il', board]
+ print command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
+ print ' '.join(cmd)
+
+for board in sys.argv[1:]:
+ rm_board(board)
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 01/93] Add a simple script to remove boards
2018-11-19 15:52 ` [U-Boot] [PATCH 01/93] Add a simple script to remove boards Simon Glass
@ 2018-11-19 18:19 ` Adam Ford
2018-11-26 22:24 ` Simon Glass
2018-11-27 0:08 ` Simon Glass
0 siblings, 2 replies; 211+ messages in thread
From: Adam Ford @ 2018-11-19 18:19 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 9:54 AM Simon Glass <sjg@chromium.org> wrote:
>
> This script attempts to create a git commit which removes a single board.
> It is quite fallible and everything it does needs checking. But it can
> help speed up the process.
>
This patch looks like it goes through the configs, finds boards and
blindly deletes them. What happens in the instance where multiple
defconfig files use the same include/configs file or C source? If one
of the defconfigs is missing something, does it then delete the
others? It seems like it should make sure that all variations don't
comply before blowing away the source and include/configs.
adam
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> tools/rmboard.py | 145 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 145 insertions(+)
> create mode 100755 tools/rmboard.py
>
> diff --git a/tools/rmboard.py b/tools/rmboard.py
> new file mode 100755
> index 00000000000..c6be434c9ed
> --- /dev/null
> +++ b/tools/rmboard.py
> @@ -0,0 +1,145 @@
> +#! /usr/bin/python
> +
> +'''
> +Script to remove boards
> +
> +Usage:
> + rmboard.py <board_name>...
> +
> +A single commit is created for each board removed.
> +
> +Some boards may depend on files provided by another and this will cause
> +problems.
> +
> +This script works by:
> + - Looking through the MAINTAINERS files which mention a board to find out
> + what files the board uses
> + - Looking through the Kconfig files which mention a board to find one that
> + needs to have material removed
> +'''
> +
> +import glob
> +import os
> +import re
> +import sys
> +
> +# Bring in the patman libraries
> +our_path = os.path.dirname(os.path.realpath(__file__))
> +sys.path.append(os.path.join(our_path, '../patman'))
> +
> +import command
> +
> +def rm_kconfig_include(path):
> + """Remove a path from Kconfig files
> +
> + This function finds the given path in a 'source' statement in a Kconfig
> + file and removes that line from the file. This is needed because the path
> + is going to be removed, so any reference to it will cause a problem with
> + Kconfig parsing.
> +
> + The changes are made locally and then added to the git staging area.
> +
> + Args:
> + path: Path to search for and remove
> + """
> + print 'path', path
> + cmd = ['git', 'grep', path]
> + stdout = command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
> + if not stdout:
> + return
> + fname = stdout.split(':')[0]
> +
> + print "Fixing up '%s' to remove reference to '%s'" % (fname, path)
> + cmd = ['sed', '-i', '\|%s|d' % path, fname]
> + stdout = command.RunPipe([cmd], capture=True).stdout
> +
> + cmd = ['git', 'add', fname]
> + stdout = command.RunPipe([cmd], capture=True).stdout
> +
> +def rm_board(board):
> + """Handle creating a commit which removes a single board
> +
> + Args:
> + board: Board name to remove
> + """
> +
> + # Find all MAINTAINERS and Kconfig files which mention the board
> + cmd = ['git', 'grep', '-l', board]
> + stdout = command.RunPipe([cmd], capture=True).stdout
> + maintain = []
> + kconfig = []
> + for line in stdout.splitlines():
> + line = line.strip()
> + if 'MAINTAINERS' in line:
> + if line not in maintain:
> + maintain.append(line)
> + elif 'Kconfig' in line:
> + kconfig.append(line)
> + paths = []
> + cc = []
> + print 'maintain', maintain
> +
> + # Look through the MAINTAINERS file to find things to remove
> + for fname in maintain:
> + with open(fname) as fd:
> + for line in fd:
> + line = line.strip()
> + fields = re.split('[ \t]', line, 1)
> + print fields
> + if len(fields) == 2:
> + if fields[0] == 'M:':
> + cc.append(fields[1])
> + elif fields[0] == 'F:':
> + paths.append(fields[1].strip())
> + print 'paths', paths
> +
> + # Expannd any wildcards in the MAINTAINRERS file
> + real = []
> + for path in paths:
> + if path[-1] == '/':
> + path = path[:-1]
> + if '*' in path:
> + globbed = glob.glob(path)
> + print "Expanded '%s' to '%s'" % (path, globbed)
> + real += globbed
> + else:
> + real.append(path)
> + print 'real', real
> +
> + # Search for Kconfig files in the resulting list. Remove any 'source' lines
> + # which referenced Kconfig files we want to remove
> + for path in real:
> + cmd = ['find', path]
> + stdout = (command.RunPipe([cmd], capture=True, raise_on_error=False).
> + stdout)
> + for fname in stdout.splitlines():
> + if fname.endswith('Kconfig'):
> + rm_kconfig_include(fname)
> +
> + # Remove unwanted files
> + cmd = ['git', 'rm', '-r'] + real
> + stdout = command.RunPipe([cmd], capture=True).stdout
> +
> + # Change the messages as needed
> + msg = '''arm: Remove %s board
> +
> +This board has not been converted to CONFIG_DM_BLK by the deadline.
> +Remove it.
> +
> +''' % board
> + for name in cc:
> + msg += 'Patch-cc: %s\n' % name
> +
> + # Create the commit
> + cmd = ['git', 'commit', '-s', '-m', msg]
> + stdout = command.RunPipe([cmd], capture=True).stdout
> + print kconfig
> +
> + # Check if the board is mentioned anywhere else. The user will need to deal
> + # with this
> + cmd = ['git', 'grep', '-il', board]
> + print command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
> + print ' '.join(cmd)
> +
> +for board in sys.argv[1:]:
> + rm_board(board)
> --
> 2.19.1.1215.g8438c0b245-goog
>
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 01/93] Add a simple script to remove boards
2018-11-19 18:19 ` Adam Ford
@ 2018-11-26 22:24 ` Simon Glass
2018-11-27 0:08 ` Simon Glass
1 sibling, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-26 22:24 UTC (permalink / raw)
To: u-boot
On Mon, 19 Nov 2018 at 11:19, Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Nov 19, 2018 at 9:54 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This script attempts to create a git commit which removes a single board.
> > It is quite fallible and everything it does needs checking. But it can
> > help speed up the process.
> >
>
> This patch looks like it goes through the configs, finds boards and
> blindly deletes them. What happens in the instance where multiple
> defconfig files use the same include/configs file or C source? If one
> of the defconfigs is missing something, does it then delete the
> others? It seems like it should make sure that all variations don't
> comply before blowing away the source and include/configs.
>
> adam
>
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > tools/rmboard.py | 145 +++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 145 insertions(+)
> > create mode 100755 tools/rmboard.py
> >
> > diff --git a/tools/rmboard.py b/tools/rmboard.py
> > new file mode 100755
> > index 00000000000..c6be434c9ed
> > --- /dev/null
> > +++ b/tools/rmboard.py
> > @@ -0,0 +1,145 @@
> > +#! /usr/bin/python
> > +
> > +'''
> > +Script to remove boards
> > +
> > +Usage:
> > + rmboard.py <board_name>...
> > +
> > +A single commit is created for each board removed.
> > +
> > +Some boards may depend on files provided by another and this will cause
> > +problems.
> > +
> > +This script works by:
> > + - Looking through the MAINTAINERS files which mention a board to find out
> > + what files the board uses
> > + - Looking through the Kconfig files which mention a board to find one that
> > + needs to have material removed
> > +'''
> > +
> > +import glob
> > +import os
> > +import re
> > +import sys
> > +
> > +# Bring in the patman libraries
> > +our_path = os.path.dirname(os.path.realpath(__file__))
> > +sys.path.append(os.path.join(our_path, '../patman'))
> > +
> > +import command
> > +
> > +def rm_kconfig_include(path):
> > + """Remove a path from Kconfig files
> > +
> > + This function finds the given path in a 'source' statement in a Kconfig
> > + file and removes that line from the file. This is needed because the path
> > + is going to be removed, so any reference to it will cause a problem with
> > + Kconfig parsing.
> > +
> > + The changes are made locally and then added to the git staging area.
> > +
> > + Args:
> > + path: Path to search for and remove
> > + """
> > + print 'path', path
> > + cmd = ['git', 'grep', path]
> > + stdout = command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
> > + if not stdout:
> > + return
> > + fname = stdout.split(':')[0]
> > +
> > + print "Fixing up '%s' to remove reference to '%s'" % (fname, path)
> > + cmd = ['sed', '-i', '\|%s|d' % path, fname]
> > + stdout = command.RunPipe([cmd], capture=True).stdout
> > +
> > + cmd = ['git', 'add', fname]
> > + stdout = command.RunPipe([cmd], capture=True).stdout
> > +
> > +def rm_board(board):
> > + """Handle creating a commit which removes a single board
> > +
> > + Args:
> > + board: Board name to remove
> > + """
> > +
> > + # Find all MAINTAINERS and Kconfig files which mention the board
> > + cmd = ['git', 'grep', '-l', board]
> > + stdout = command.RunPipe([cmd], capture=True).stdout
> > + maintain = []
> > + kconfig = []
> > + for line in stdout.splitlines():
> > + line = line.strip()
> > + if 'MAINTAINERS' in line:
> > + if line not in maintain:
> > + maintain.append(line)
> > + elif 'Kconfig' in line:
> > + kconfig.append(line)
> > + paths = []
> > + cc = []
> > + print 'maintain', maintain
> > +
> > + # Look through the MAINTAINERS file to find things to remove
> > + for fname in maintain:
> > + with open(fname) as fd:
> > + for line in fd:
> > + line = line.strip()
> > + fields = re.split('[ \t]', line, 1)
> > + print fields
> > + if len(fields) == 2:
> > + if fields[0] == 'M:':
> > + cc.append(fields[1])
> > + elif fields[0] == 'F:':
> > + paths.append(fields[1].strip())
> > + print 'paths', paths
> > +
> > + # Expannd any wildcards in the MAINTAINRERS file
> > + real = []
> > + for path in paths:
> > + if path[-1] == '/':
> > + path = path[:-1]
> > + if '*' in path:
> > + globbed = glob.glob(path)
> > + print "Expanded '%s' to '%s'" % (path, globbed)
> > + real += globbed
> > + else:
> > + real.append(path)
> > + print 'real', real
> > +
> > + # Search for Kconfig files in the resulting list. Remove any 'source' lines
> > + # which referenced Kconfig files we want to remove
> > + for path in real:
> > + cmd = ['find', path]
> > + stdout = (command.RunPipe([cmd], capture=True, raise_on_error=False).
> > + stdout)
> > + for fname in stdout.splitlines():
> > + if fname.endswith('Kconfig'):
> > + rm_kconfig_include(fname)
> > +
> > + # Remove unwanted files
> > + cmd = ['git', 'rm', '-r'] + real
> > + stdout = command.RunPipe([cmd], capture=True).stdout
> > +
> > + # Change the messages as needed
> > + msg = '''arm: Remove %s board
> > +
> > +This board has not been converted to CONFIG_DM_BLK by the deadline.
> > +Remove it.
> > +
> > +''' % board
> > + for name in cc:
> > + msg += 'Patch-cc: %s\n' % name
> > +
> > + # Create the commit
> > + cmd = ['git', 'commit', '-s', '-m', msg]
> > + stdout = command.RunPipe([cmd], capture=True).stdout
> > + print kconfig
> > +
> > + # Check if the board is mentioned anywhere else. The user will need to deal
> > + # with this
> > + cmd = ['git', 'grep', '-il', board]
> > + print command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
> > + print ' '.join(cmd)
> > +
> > +for board in sys.argv[1:]:
> > + rm_board(board)
> > --
> > 2.19.1.1215.g8438c0b245-goog
> >
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 01/93] Add a simple script to remove boards
2018-11-19 18:19 ` Adam Ford
2018-11-26 22:24 ` Simon Glass
@ 2018-11-27 0:08 ` Simon Glass
1 sibling, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-27 0:08 UTC (permalink / raw)
To: u-boot
Hi Adam,
On Mon, 19 Nov 2018 at 11:19, Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Nov 19, 2018 at 9:54 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This script attempts to create a git commit which removes a single board.
> > It is quite fallible and everything it does needs checking. But it can
> > help speed up the process.
> >
>
> This patch looks like it goes through the configs, finds boards and
> blindly deletes them. What happens in the instance where multiple
> defconfig files use the same include/configs file or C source? If one
> of the defconfigs is missing something, does it then delete the
> others? It seems like it should make sure that all variations don't
> comply before blowing away the source and include/configs.
Yes that is one of the failure modes :-) I am not sure how to do better. Regards
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 02/93] dm: mmc: Use CONFIG_IS_ENABLED to check for BLK
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 01/93] Add a simple script to remove boards Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 03/93] solidrun: Correct typo in MAINTAINERS Simon Glass
` (95 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This code can be used from SPL and SPL may have a different setting for
CONFIG_BLK that U-Boot proper. Use the correct macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
drivers/mmc/dw_mmc.c | 2 +-
drivers/mmc/mmc-uclass.c | 2 +-
drivers/mmc/mmc_write.c | 8 ++++----
include/dwmmc.h | 6 +++---
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7544b84ab61..cf86b125c6c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -544,7 +544,7 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
return mmc_bind(dev, mmc, cfg);
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index f73f07254be..34dfe13fe2c 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -379,7 +379,7 @@ U_BOOT_DRIVER(mmc_blk) = {
.ops = &mmc_blk_ops,
.probe = mmc_blk_probe,
};
-#endif /* CONFIG_BLK */
+#endif /* CONFIG_IS_ENABLED(BLK) */
U_BOOT_DRIVER(mmc) = {
.name = "mmc",
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index b8acc33c76d..c8c83c9188e 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -65,13 +65,13 @@ err_out:
return err;
}
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
#else
ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
#endif
{
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
int dev_num = block_dev->devnum;
@@ -183,7 +183,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
return blkcnt;
}
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
const void *src)
#else
@@ -191,7 +191,7 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
const void *src)
#endif
{
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
int dev_num = block_dev->devnum;
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 4ceda5e43c5..0cc155290da 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -182,7 +182,7 @@ struct dwmci_host {
* @freq: Frequency the host is trying to achieve
*/
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
-#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(BLK)
struct mmc_config cfg;
#endif
@@ -226,7 +226,7 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
return readb(host->ioaddr + reg);
}
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
/**
* dwmci_setup_cfg() - Set up the configuration for DWMMC
*
@@ -291,7 +291,7 @@ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
* @return 0 if OK, -ve on error
*/
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
-#endif /* !CONFIG_BLK */
+#endif /* CONFIG_IS_ENABLED(BLK) */
#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 03/93] solidrun: Correct typo in MAINTAINERS
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 01/93] Add a simple script to remove boards Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 02/93] dm: mmc: Use CONFIG_IS_ENABLED to check for BLK Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 04/93] arm: Remove s32v234evb board Simon Glass
` (94 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
The directory here is misspelled. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/solidrun/clearfog/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS
index 298e5011c79..6d0c3ef58bd 100644
--- a/board/solidrun/clearfog/MAINTAINERS
+++ b/board/solidrun/clearfog/MAINTAINERS
@@ -1,6 +1,6 @@
CLEARFOG BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
-F: board/soldrun/clearfog/
+F: board/solidrun/clearfog/
F: include/configs/clearfog.h
F: configs/clearfog_defconfig
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 04/93] arm: Remove s32v234evb board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (2 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 03/93] solidrun: Correct typo in MAINTAINERS Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 05/93] arm: Remove ls1043ardb_sdcard_SECURE_BOOT board Simon Glass
` (93 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
arch/arm/cpu/armv8/s32v234/Makefile | 6 -
arch/arm/cpu/armv8/s32v234/cpu.c | 98 -----
arch/arm/cpu/armv8/s32v234/cpu.h | 7 -
arch/arm/cpu/armv8/s32v234/generic.c | 349 ------------------
arch/arm/include/asm/arch-s32v234/clock.h | 33 --
arch/arm/include/asm/arch-s32v234/ddr.h | 156 --------
arch/arm/include/asm/arch-s32v234/imx-regs.h | 328 ----------------
arch/arm/include/asm/arch-s32v234/lpddr2.h | 74 ----
.../include/asm/arch-s32v234/mc_cgm_regs.h | 253 -------------
.../arm/include/asm/arch-s32v234/mc_me_regs.h | 198 ----------
.../include/asm/arch-s32v234/mc_rgm_regs.h | 30 --
arch/arm/include/asm/arch-s32v234/mmdc.h | 88 -----
arch/arm/include/asm/arch-s32v234/siul.h | 149 --------
board/freescale/s32v234evb/Kconfig | 23 --
board/freescale/s32v234evb/MAINTAINERS | 8 -
board/freescale/s32v234evb/Makefile | 9 -
board/freescale/s32v234evb/clock.c | 343 -----------------
board/freescale/s32v234evb/lpddr2.c | 136 -------
board/freescale/s32v234evb/s32v234evb.c | 182 ---------
board/freescale/s32v234evb/s32v234evb.cfg | 28 --
configs/s32v234evb_defconfig | 17 -
include/configs/s32v234evb.h | 190 ----------
23 files changed, 2706 deletions(-)
delete mode 100644 arch/arm/cpu/armv8/s32v234/Makefile
delete mode 100644 arch/arm/cpu/armv8/s32v234/cpu.c
delete mode 100644 arch/arm/cpu/armv8/s32v234/cpu.h
delete mode 100644 arch/arm/cpu/armv8/s32v234/generic.c
delete mode 100644 arch/arm/include/asm/arch-s32v234/clock.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/ddr.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/imx-regs.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/lpddr2.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_me_regs.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/mmdc.h
delete mode 100644 arch/arm/include/asm/arch-s32v234/siul.h
delete mode 100644 board/freescale/s32v234evb/Kconfig
delete mode 100644 board/freescale/s32v234evb/MAINTAINERS
delete mode 100644 board/freescale/s32v234evb/Makefile
delete mode 100644 board/freescale/s32v234evb/clock.c
delete mode 100644 board/freescale/s32v234evb/lpddr2.c
delete mode 100644 board/freescale/s32v234evb/s32v234evb.c
delete mode 100644 board/freescale/s32v234evb/s32v234evb.cfg
delete mode 100644 configs/s32v234evb_defconfig
delete mode 100644 include/configs/s32v234evb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f5d4d396838..11f2e0f826d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1519,7 +1519,6 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
-source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
diff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile
deleted file mode 100644
index 3bdb98d995e..00000000000
--- a/arch/arm/cpu/armv8/s32v234/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
-
-obj-y += generic.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
deleted file mode 100644
index 1fa6841eaf7..00000000000
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/armv8/mmu.h>
-#include <asm/io.h>
-#include <asm/arch/mc_me_regs.h>
-#include "cpu.h"
-
-u32 cpu_mask(void)
-{
- return readl(MC_ME_CS);
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
-#define S32V234_IRAM_BASE 0x3e800000UL
-#define S32V234_IRAM_SIZE 0x800000UL
-#define S32V234_DRAM_BASE1 0x80000000UL
-#define S32V234_DRAM_SIZE1 0x40000000UL
-#define S32V234_DRAM_BASE2 0xC0000000UL
-#define S32V234_DRAM_SIZE2 0x20000000UL
-#define S32V234_PERIPH_BASE 0x40000000UL
-#define S32V234_PERIPH_SIZE 0x40000000UL
-
-static struct mm_region s32v234_mem_map[] = {
- {
- .virt = S32V234_IRAM_BASE,
- .phys = S32V234_IRAM_BASE,
- .size = S32V234_IRAM_SIZE,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE
- }, {
- .virt = S32V234_DRAM_BASE1,
- .phys = S32V234_DRAM_BASE1,
- .size = S32V234_DRAM_SIZE1,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE
- }, {
- .virt = S32V234_PERIPH_BASE,
- .phys = S32V234_PERIPH_BASE,
- .size = S32V234_PERIPH_SIZE,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
- /* TODO: Do we need these? */
- /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
- }, {
- .virt = S32V234_DRAM_BASE2,
- .phys = S32V234_DRAM_BASE2,
- .size = S32V234_DRAM_SIZE2,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_OUTER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = s32v234_mem_map;
-
-#endif
-
-/*
- * Return the number of cores on this SOC.
- */
-int cpu_numcores(void)
-{
- int numcores;
- u32 mask;
-
- mask = cpu_mask();
- numcores = hweight32(cpu_mask());
-
- /* Verify if M4 is deactivated */
- if (mask & 0x1)
- numcores--;
-
- return numcores;
-}
-
-#if defined(CONFIG_ARCH_EARLY_INIT_R)
-int arch_early_init_r(void)
-{
- int rv;
- asm volatile ("dsb sy");
- rv = fsl_s32v234_wake_seconday_cores();
-
- if (rv)
- printf("Did not wake secondary cores\n");
-
- asm volatile ("sev");
- return 0;
-}
-#endif /* CONFIG_ARCH_EARLY_INIT_R */
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h
deleted file mode 100644
index 11c3a6b435e..00000000000
--- a/arch/arm/cpu/armv8/s32v234/cpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
- */
-
-u32 cpu_mask(void);
-int cpu_numcores(void);
diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c
deleted file mode 100644
index 273b88e9d33..00000000000
--- a/arch/arm/cpu/armv8/s32v234/generic.c
+++ /dev/null
@@ -1,349 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mc_cgm_regs.h>
-#include <asm/arch/mc_me_regs.h>
-#include <asm/arch/mc_rgm_regs.h>
-#include <netdev.h>
-#include <div64.h>
-#include <errno.h>
-
-u32 get_cpu_rev(void)
-{
- struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
- u32 cpu = readl(&mscmir->cpxtype);
-
- return cpu;
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
- u32 pllfd, u32 selected_output)
-{
- u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
- u32 plldv_rfdphi_div = 0, fout = 0;
- u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
-
- if (selected_output > DFS_MAXNUMBER) {
- return -1;
- }
-
- plldv_prediv =
- (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
- plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
-
- pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
-
- plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
-
- /* The formula for VCO is from TR manual, rev. D */
- vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
-
- if (selected_output != 0) {
- /* Determine the RFDPHI for PHI1 */
- plldv_rfdphi_div =
- (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
- PLLDIG_PLLDV_RFDPHI1_OFFSET;
- plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
- if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
- dfs_portn =
- readl(DFS_DVPORTn(pll, selected_output - 1));
- dfs_mfi =
- (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
- DFS_DVPORTn_MFI_OFFSET;
- dfs_mfn =
- (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
- DFS_DVPORTn_MFI_OFFSET;
- fout = vco / (dfs_mfi + (dfs_mfn / 256));
- } else {
- fout = vco / plldv_rfdphi_div;
- }
-
- } else {
- /* Determine the RFDPHI for PHI0 */
- plldv_rfdphi_div =
- (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
- PLLDIG_PLLDV_RFDPHI_OFFSET;
- fout = vco / plldv_rfdphi_div;
- }
-
- return fout;
-
-}
-
-/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
-static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
- u32 selected_output)
-{
- u32 plldv, pllfd;
-
- plldv = readl(PLLDIG_PLLDV(pll));
- pllfd = readl(PLLDIG_PLLFD(pll));
-
- return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
-}
-
-static u32 get_mcu_main_clk(void)
-{
- u32 coreclk_div;
- u32 sysclk_sel;
- u32 freq = 0;
-
- sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
- sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
-
- coreclk_div =
- readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
- coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
- coreclk_div += 1;
-
- switch (sysclk_sel) {
- case MC_CGM_SC_SEL_FIRC:
- freq = FIRC_CLK_FREQ;
- break;
- case MC_CGM_SC_SEL_XOSC:
- freq = XOSC_CLK_FREQ;
- break;
- case MC_CGM_SC_SEL_ARMPLL:
- /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
- freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
- break;
- case MC_CGM_SC_SEL_CLKDISABLE:
- printf("Sysclk is disabled\n");
- break;
- default:
- printf("unsupported system clock select\n");
- }
-
- return freq / coreclk_div;
-}
-
-static u32 get_sys_clk(u32 number)
-{
- u32 sysclk_div, sysclk_div_number;
- u32 sysclk_sel;
- u32 freq = 0;
-
- switch (number) {
- case 3:
- sysclk_div_number = 0;
- break;
- case 6:
- sysclk_div_number = 1;
- break;
- default:
- printf("unsupported system clock \n");
- return -1;
- }
- sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
- sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
-
- sysclk_div =
- readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
- MC_CGM_SC_DCn_PREDIV_MASK;
- sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
- sysclk_div += 1;
-
- switch (sysclk_sel) {
- case MC_CGM_SC_SEL_FIRC:
- freq = FIRC_CLK_FREQ;
- break;
- case MC_CGM_SC_SEL_XOSC:
- freq = XOSC_CLK_FREQ;
- break;
- case MC_CGM_SC_SEL_ARMPLL:
- /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
- freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
- break;
- case MC_CGM_SC_SEL_CLKDISABLE:
- printf("Sysclk is disabled\n");
- break;
- default:
- printf("unsupported system clock select\n");
- }
-
- return freq / sysclk_div;
-}
-
-static u32 get_peripherals_clk(void)
-{
- u32 aux5clk_div;
- u32 freq = 0;
-
- aux5clk_div =
- readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
- MC_CGM_ACn_DCm_PREDIV_MASK;
- aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
- aux5clk_div += 1;
-
- freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
-
- return freq / aux5clk_div;
-
-}
-
-static u32 get_uart_clk(void)
-{
- u32 auxclk3_div, auxclk3_sel, freq = 0;
-
- auxclk3_sel =
- readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
- auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
-
- auxclk3_div =
- readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
- MC_CGM_ACn_DCm_PREDIV_MASK;
- auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
- auxclk3_div += 1;
-
- switch (auxclk3_sel) {
- case MC_CGM_ACn_SEL_FIRC:
- freq = FIRC_CLK_FREQ;
- break;
- case MC_CGM_ACn_SEL_XOSC:
- freq = XOSC_CLK_FREQ;
- break;
- case MC_CGM_ACn_SEL_PERPLLDIVX:
- freq = get_peripherals_clk() / 3;
- break;
- case MC_CGM_ACn_SEL_SYSCLK:
- freq = get_sys_clk(6);
- break;
- default:
- printf("unsupported system clock select\n");
- }
-
- return freq / auxclk3_div;
-}
-
-static u32 get_fec_clk(void)
-{
- u32 aux2clk_div;
- u32 freq = 0;
-
- aux2clk_div =
- readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
- MC_CGM_ACn_DCm_PREDIV_MASK;
- aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
- aux2clk_div += 1;
-
- freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
-
- return freq / aux2clk_div;
-}
-
-static u32 get_usdhc_clk(void)
-{
- u32 aux15clk_div;
- u32 freq = 0;
-
- aux15clk_div =
- readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
- MC_CGM_ACn_DCm_PREDIV_MASK;
- aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
- aux15clk_div += 1;
-
- freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
-
- return freq / aux15clk_div;
-}
-
-static u32 get_i2c_clk(void)
-{
- return get_peripherals_clk();
-}
-
-/* return clocks in Hz */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_PERIPHERALS_CLK:
- return get_peripherals_clk();
- case MXC_UART_CLK:
- return get_uart_clk();
- case MXC_FEC_CLK:
- return get_fec_clk();
- case MXC_I2C_CLK:
- return get_i2c_clk();
- case MXC_USDHC_CLK:
- return get_usdhc_clk();
- default:
- break;
- }
- printf("Error: Unsupported function to read the frequency! \
- Please define it correctly!");
- return -1;
-}
-
-/* Not yet implemented - int soc_clk_dump(); */
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_reset_cause(void)
-{
- u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
-
- switch (cause) {
- case F_SWT4:
- return "WDOG";
- case F_JTAG:
- return "JTAG";
- case F_FCCU_SOFT:
- return "FCCU soft reaction";
- case F_FCCU_HARD:
- return "FCCU hard reaction";
- case F_SOFT_FUNC:
- return "Software Functional reset";
- case F_ST_DONE:
- return "Self Test done reset";
- case F_EXT_RST:
- return "External reset";
- default:
- return "unknown reset";
- }
-
-}
-
-#define SRC_SCR_SW_RST (1<<12)
-
-void reset_cpu(ulong addr)
-{
- printf("Feature not supported.\n");
-};
-
-int print_cpuinfo(void)
-{
- printf("CPU: Freescale Treerunner S32V234@%d MHz\n",
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- printf("Reset cause: %s\n", get_reset_cause());
-
- return 0;
-}
-#endif
-
-int cpu_eth_init(bd_t * bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
- rc = fecmxc_initialize(bis);
-#endif
-
- return rc;
-}
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC
- gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
-#endif
- return 0;
-}
diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h
deleted file mode 100644
index c60065444cc..00000000000
--- a/arch/arm/include/asm/arch-s32v234/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#include <common.h>
-
-enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_BUS_CLK,
- MXC_PERIPHERALS_CLK,
- MXC_UART_CLK,
- MXC_USDHC_CLK,
- MXC_FEC_CLK,
- MXC_I2C_CLK,
-};
-enum pll_type {
- ARM_PLL = 0,
- PERIPH_PLL,
- ENET_PLL,
- DDR_PLL,
- VIDEO_PLL,
-};
-
-unsigned int mxc_get_clock(enum mxc_clock clk);
-void clock_init(void);
-
-#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h
deleted file mode 100644
index 8c709af80d4..00000000000
--- a/arch/arm/include/asm/arch-s32v234/ddr.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
-#define __ARCH_ARM_MACH_S32V234_DDR_H__
-
-#define DDR0 0
-#define DDR1 1
-
-/* DDR offset in MSCR register */
-#define _DDR0_RESET 168
-#define _DDR0_CLK0 169
-#define _DDR0_CAS 170
-#define _DDR0_RAS 171
-#define _DDR0_WE_B 172
-#define _DDR0_CKE0 173
-#define _DDR0_CKE1 174
-#define _DDR0_CS_B0 175
-#define _DDR0_CS_B1 176
-#define _DDR0_BA0 177
-#define _DDR0_BA1 178
-#define _DDR0_BA2 179
-#define _DDR0_A0 180
-#define _DDR0_A1 181
-#define _DDR0_A2 182
-#define _DDR0_A3 183
-#define _DDR0_A4 184
-#define _DDR0_A5 185
-#define _DDR0_A6 186
-#define _DDR0_A7 187
-#define _DDR0_A8 188
-#define _DDR0_A9 189
-#define _DDR0_A10 190
-#define _DDR0_A11 191
-#define _DDR0_A12 192
-#define _DDR0_A13 193
-#define _DDR0_A14 194
-#define _DDR0_A15 195
-#define _DDR0_DM0 196
-#define _DDR0_DM1 197
-#define _DDR0_DM2 198
-#define _DDR0_DM3 199
-#define _DDR0_DQS0 200
-#define _DDR0_DQS1 201
-#define _DDR0_DQS2 202
-#define _DDR0_DQS3 203
-#define _DDR0_D0 204
-#define _DDR0_D1 205
-#define _DDR0_D2 206
-#define _DDR0_D3 207
-#define _DDR0_D4 208
-#define _DDR0_D5 209
-#define _DDR0_D6 210
-#define _DDR0_D7 211
-#define _DDR0_D8 212
-#define _DDR0_D9 213
-#define _DDR0_D10 214
-#define _DDR0_D11 215
-#define _DDR0_D12 216
-#define _DDR0_D13 217
-#define _DDR0_D14 218
-#define _DDR0_D15 219
-#define _DDR0_D16 220
-#define _DDR0_D17 221
-#define _DDR0_D18 222
-#define _DDR0_D19 223
-#define _DDR0_D20 224
-#define _DDR0_D21 225
-#define _DDR0_D22 226
-#define _DDR0_D23 227
-#define _DDR0_D24 228
-#define _DDR0_D25 229
-#define _DDR0_D26 230
-#define _DDR0_D27 231
-#define _DDR0_D28 232
-#define _DDR0_D29 233
-#define _DDR0_D30 234
-#define _DDR0_D31 235
-#define _DDR0_ODT0 236
-#define _DDR0_ODT1 237
-#define _DDR0_ZQ 238
-#define _DDR1_RESET 239
-#define _DDR1_CLK0 240
-#define _DDR1_CAS 241
-#define _DDR1_RAS 242
-#define _DDR1_WE_B 243
-#define _DDR1_CKE0 244
-#define _DDR1_CKE1 245
-#define _DDR1_CS_B0 246
-#define _DDR1_CS_B1 247
-#define _DDR1_BA0 248
-#define _DDR1_BA1 249
-#define _DDR1_BA2 250
-#define _DDR1_A0 251
-#define _DDR1_A1 252
-#define _DDR1_A2 253
-#define _DDR1_A3 254
-#define _DDR1_A4 255
-#define _DDR1_A5 256
-#define _DDR1_A6 257
-#define _DDR1_A7 258
-#define _DDR1_A8 259
-#define _DDR1_A9 260
-#define _DDR1_A10 261
-#define _DDR1_A11 262
-#define _DDR1_A12 263
-#define _DDR1_A13 264
-#define _DDR1_A14 265
-#define _DDR1_A15 266
-#define _DDR1_DM0 267
-#define _DDR1_DM1 268
-#define _DDR1_DM2 269
-#define _DDR1_DM3 270
-#define _DDR1_DQS0 271
-#define _DDR1_DQS1 272
-#define _DDR1_DQS2 273
-#define _DDR1_DQS3 274
-#define _DDR1_D0 275
-#define _DDR1_D1 276
-#define _DDR1_D2 277
-#define _DDR1_D3 278
-#define _DDR1_D4 279
-#define _DDR1_D5 280
-#define _DDR1_D6 281
-#define _DDR1_D7 282
-#define _DDR1_D8 283
-#define _DDR1_D9 284
-#define _DDR1_D10 285
-#define _DDR1_D11 286
-#define _DDR1_D12 287
-#define _DDR1_D13 288
-#define _DDR1_D14 289
-#define _DDR1_D15 290
-#define _DDR1_D16 291
-#define _DDR1_D17 292
-#define _DDR1_D18 293
-#define _DDR1_D19 294
-#define _DDR1_D20 295
-#define _DDR1_D21 296
-#define _DDR1_D22 297
-#define _DDR1_D23 298
-#define _DDR1_D24 299
-#define _DDR1_D25 300
-#define _DDR1_D26 301
-#define _DDR1_D27 302
-#define _DDR1_D28 303
-#define _DDR1_D29 304
-#define _DDR1_D30 305
-#define _DDR1_D31 306
-#define _DDR1_ODT0 307
-#define _DDR1_ODT1 308
-#define _DDR1_ZQ 309
-
-#endif
diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h
deleted file mode 100644
index 9a779cce965..00000000000
--- a/arch/arm/include/asm/arch-s32v234/imx-regs.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_IMX_REGS_H__
-#define __ASM_ARCH_IMX_REGS_H__
-
-#define ARCH_MXC
-
-#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
-#define IRAM_SIZE 0x00400000 /* 4MB */
-
-#define AIPS0_BASE_ADDR (0x40000000UL)
-#define AIPS1_BASE_ADDR (0x40080000UL)
-
-/* AIPS 0 */
-#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
-#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
-#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
-#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
-#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
-#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
-#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
-#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
-#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
-#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000)
-#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000)
-#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000)
-#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
-#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
-#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
-#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
-#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
-#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
-#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
-#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
-#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000)
-#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000)
-#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000)
-#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
-#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000)
-#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
-#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000)
-#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000)
-#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000)
-#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000)
-#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000)
-#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000)
-#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000)
-#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000)
-#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000)
-#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000)
-#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000)
-#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000)
-#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
-#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000)
-#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
-#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
-#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000)
-#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000)
-#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000)
-#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000)
-
-/* AIPS 1 */
-#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
-#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
-#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
-#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
-#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
-#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
-#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
-#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
-#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
-#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000)
-#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000)
-#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000)
-#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000)
-#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000)
-#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000)
-#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000)
-#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000)
-#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000)
-#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000)
-#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000)
-#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000)
-#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000)
-#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000)
-#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000)
-#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000)
-#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000)
-#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000)
-#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000)
-#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000)
-#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000)
-#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000)
-#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000)
-#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000)
-#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000)
-#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000)
-#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000)
-#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000)
-#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000)
-#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000)
-#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000)
-#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000)
-#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000)
-#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000)
-
-/* TODO Remove this after the IOMUX framework is implemented */
-#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
-
-/* MUX mode and PAD ctrl are in one register */
-#define CONFIG_IOMUX_SHARE_CONF_REG
-
-#define FEC_QUIRK_ENET_MAC
-#define I2C_QUIRK_REG
-
-/* MSCM interrupt router */
-#define MSCM_IRSPRC_CPn_EN 3
-#define MSCM_IRSPRC_NUM 176
-#define MSCM_CPXTYPE_RYPZ_MASK 0xFF
-#define MSCM_CPXTYPE_RYPZ_OFFSET 0
-#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00
-#define MSCM_CPXTYPE_PERS_OFFSET 8
-#define MSCM_CPXTYPE_PERS_A53 0x413533
-#define MSCM_CPXTYPE_PERS_CM4 0x434d34
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* System Reset Controller (SRC) */
-struct src {
- u32 bmr1;
- u32 bmr2;
- u32 gpr1_boot;
- u32 reserved_0x00C[61];
- u32 gpr1;
- u32 gpr2;
- u32 gpr3;
- u32 gpr4;
- u32 gpr5;
- u32 gpr6;
- u32 gpr7;
- u32 reserved_0x11C[1];
- u32 gpr9;
- u32 gpr10;
- u32 gpr11;
- u32 gpr12;
- u32 gpr13;
- u32 gpr14;
- u32 gpr15;
- u32 gpr16;
- u32 reserved_0x140[1];
- u32 gpr17;
- u32 gpr18;
- u32 gpr19;
- u32 gpr20;
- u32 gpr21;
- u32 gpr22;
- u32 gpr23;
- u32 gpr24;
- u32 gpr25;
- u32 gpr26;
- u32 gpr27;
- u32 reserved_0x16C[5];
- u32 pcie_config1;
- u32 ddr_self_ref_ctrl;
- u32 pcie_config0;
- u32 reserved_0x18C[4];
- u32 soc_misc_config2;
-};
-
-/* SRC registers definitions */
-
-/* SRC_GPR1 */
-#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
- (SRC_GPR1_PLL_OFFSET + (pll)) )
-#define SRC_GPR1_PLL_SOURCE_MASK (0x1)
-
-#define SRC_GPR1_PLL_OFFSET (27)
-#define SRC_GPR1_FIRC_CLK_SOURCE (0x0)
-#define SRC_GPR1_XOSC_CLK_SOURCE (0x1)
-
-/* Periodic Interrupt Timer (PIT) */
-struct pit_reg {
- u32 mcr;
- u32 recv0[55];
- u32 ltmr64h;
- u32 ltmr64l;
- u32 recv1[6];
- u32 ldval0;
- u32 cval0;
- u32 tctrl0;
- u32 tflg0;
- u32 ldval1;
- u32 cval1;
- u32 tctrl1;
- u32 tflg1;
- u32 ldval2;
- u32 cval2;
- u32 tctrl2;
- u32 tflg2;
- u32 ldval3;
- u32 cval3;
- u32 tctrl3;
- u32 tflg3;
- u32 ldval4;
- u32 cval4;
- u32 tctrl4;
- u32 tflg4;
- u32 ldval5;
- u32 cval5;
- u32 tctrl5;
- u32 tflg5;
-};
-
-/* Watchdog Timer (WDOG) */
-struct wdog_regs {
- u32 cr;
- u32 ir;
- u32 to;
- u32 wn;
- u32 sr;
- u32 co;
- u32 sk;
-};
-
-/* UART */
-struct linflex_fsl {
- u32 lincr1;
- u32 linier;
- u32 linsr;
- u32 linesr;
- u32 uartcr;
- u32 uartsr;
- u32 lintcsr;
- u32 linocr;
- u32 lintocr;
- u32 linfbrr;
- u32 linibrr;
- u32 lincfr;
- u32 lincr2;
- u32 bidr;
- u32 bdrl;
- u32 bdrm;
- u32 ifer;
- u32 ifmi;
- u32 ifmr;
- u32 ifcr0;
- u32 ifcr1;
- u32 ifcr2;
- u32 ifcr3;
- u32 ifcr4;
- u32 ifcr5;
- u32 ifcr6;
- u32 ifcr7;
- u32 ifcr8;
- u32 ifcr9;
- u32 ifcr10;
- u32 ifcr11;
- u32 ifcr12;
- u32 ifcr13;
- u32 ifcr14;
- u32 ifcr15;
- u32 gcr;
- u32 uartpto;
- u32 uartcto;
- u32 dmatxe;
- u32 dmarxe;
-};
-
-/* MSCM Interrupt Router */
-struct mscm_ir {
- u32 cpxtype; /* Processor x Type Register */
- u32 cpxnum; /* Processor x Number Register */
- u32 cpxmaster; /* Processor x Master Number Register */
- u32 cpxcount; /* Processor x Count Register */
- u32 cpxcfg0; /* Processor x Configuration 0 Register */
- u32 cpxcfg1; /* Processor x Configuration 1 Register */
- u32 cpxcfg2; /* Processor x Configuration 2 Register */
- u32 cpxcfg3; /* Processor x Configuration 3 Register */
- u32 cp0type; /* Processor 0 Type Register */
- u32 cp0num; /* Processor 0 Number Register */
- u32 cp0master; /* Processor 0 Master Number Register */
- u32 cp0count; /* Processor 0 Count Register */
- u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
- u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
- u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
- u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
- u32 cp1type; /* Processor 1 Type Register */
- u32 cp1num; /* Processor 1 Number Register */
- u32 cp1master; /* Processor 1 Master Number Register */
- u32 cp1count; /* Processor 1 Count Register */
- u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
- u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
- u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
- u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
- u32 reserved_0x060[232];
- u32 ocmdr0; /* On-Chip Memory Descriptor Register */
- u32 reserved_0x404[2];
- u32 ocmdr3; /* On-Chip Memory Descriptor Register */
- u32 reserved_0x410[28];
- u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
- u32 reserved_0x490[28];
- u32 cpce0; /* Core Parity Checking Enable Register 0 */
- u32 reserved_0x504[191];
- u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
- u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
- u32 reserved_0x808[6];
- u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
- u32 reserved_0x824[23];
- u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
- u32 reserved_0x9e0[136];
- u32 iahbbe0; /* Gasket Burst Enable Register */
- u32 reserved_0xc04[63];
- u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
- u32 reserved_0xd04[3];
- u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
- u32 reserved_0xd20[8];
- u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
- u32 reserved_0xd44[3];
- u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
-};
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h
deleted file mode 100644
index c5efee5b75d..00000000000
--- a/arch/arm/include/asm/arch-s32v234/lpddr2.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
-#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
-
-/* definitions for LPDDR2 PAD values */
-#define LPDDR2_CLK0_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
- SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \
- SIUL2_MSCR_DCYCLE_TRIM_NONE)
-#define LPDDR2_CKEn_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
- SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
-#define LPDDR2_CS_Bn_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
- SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
-#define LPDDR2_DMn_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
- SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
-#define LPDDR2_DQSn_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
- SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \
- SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
-#define LPDDR2_An_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
- SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
- SIUL2_MSCR_PUS_100K_UP)
-#define LPDDR2_Dn_PAD \
- (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \
- SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \
- SIUL2_MSCR_PUS_100K_UP)
-
-#define _MDCTL 0x03010000
-
-#define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */
-#define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
-#define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
-#define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
-#define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
-#define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
-#define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
-#define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
-#define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */
-#define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */
-#define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
-#define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
-#define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
-#define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */
-#define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */
-#define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */
-#define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */
-#define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */
-#define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */
-#define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
-#define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
-#define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */
-#define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */
-#define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */
-#define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
-#define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
-#define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */
-#define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */
-#define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */
-#define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */
-#define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */
-
-/* set I/O pads for DDR */
-void lpddr2_config_iomux(uint8_t module);
-void config_mmdc(uint8_t module);
-
-#endif
diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
deleted file mode 100644
index 957d48f9c03..00000000000
--- a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
-#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
-
-#ifndef __ASSEMBLY__
-
-/* MC_CGM registers definitions */
-/* MC_CGM_SC_SS */
-#define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) )
-#define MC_CGM_SC_SEL_FIRC (0x0)
-#define MC_CGM_SC_SEL_XOSC (0x1)
-#define MC_CGM_SC_SEL_ARMPLL (0x2)
-#define MC_CGM_SC_SEL_CLKDISABLE (0xF)
-
-/* MC_CGM_SC_DCn */
-#define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
-#define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
-#define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000)
-#define MC_CGM_SC_DCn_PREDIV_OFFSET (16)
-#define MC_CGM_SC_DCn_DE (1 << 31)
-#define MC_CGM_SC_SEL_MASK (0x0F000000)
-#define MC_CGM_SC_SEL_OFFSET (24)
-
-/* MC_CGM_ACn_DCm */
-#define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
-#define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
-
-/*
- * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
- * that the 5th bit is always ignored during writes if the current
- * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
- *
- * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
- *
- * This should be changed if any problems occur.
- */
-#define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000)
-#define MC_CGM_ACn_DCm_PREDIV_OFFSET (16)
-#define MC_CGM_ACn_DCm_DE (1 << 31)
-
-/*
- * MC_CGM_ACn_SC/MC_CGM_ACn_SS
- */
-#define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20))
-#define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20))
-#define MC_CGM_ACn_SEL_MASK (0x07000000)
-#define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
-#define MC_CGM_ACn_SEL_OFFSET (24)
-
-#define MC_CGM_ACn_SEL_FIRC (0x0)
-#define MC_CGM_ACn_SEL_XOSC (0x1)
-#define MC_CGM_ACn_SEL_ARMPLL (0x2)
-/*
- * According to the manual some PLL can be divided by X (X={1,3,5}):
- * PERPLLDIVX, VIDEOPLLDIVX.
- */
-#define MC_CGM_ACn_SEL_PERPLLDIVX (0x3)
-#define MC_CGM_ACn_SEL_ENETPLL (0x4)
-#define MC_CGM_ACn_SEL_DDRPLL (0x5)
-#define MC_CGM_ACn_SEL_EXTSRCPAD (0x7)
-#define MC_CGM_ACn_SEL_SYSCLK (0x8)
-#define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9)
-#define MC_CGM_ACn_SEL_PERCLK (0xA)
-
-/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
-#define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
-#define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div))
-#define PLLDIG_PLLDV_MFD_MASK (0x000000FF)
-
-/*
- * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
- * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
- */
-#define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
-#define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000)
-#define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F)
-#define PLLDIG_PLLDV_RFDPHI_OFFSET (16)
-
-#define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
-#define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000)
-#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F)
-#define PLLDIG_PLLDV_RFDPHI1_OFFSET (25)
-
-#define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
-#define PLLDIG_PLLDV_PREDIV_MASK (0x00007000)
-#define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7)
-#define PLLDIG_PLLDV_PREDIV_OFFSET (12)
-
-/* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */
-#define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
-#define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val))
-#define PLLDIG_PLLFD_MFN_MASK (0x00007FFF)
-#define PLLDIG_PLLFD_SMDEN (1 << 30)
-
-/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
-#define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
-#define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
-#define PLLDIG_PLLCAL1_NDAC1_OFFSET (24)
-#define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000)
-
-/* Digital Frequency Synthesizer (DFS) */
-/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
-#define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040)
-
-/* DFS DLL Program Register 1 */
-#define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
-
-#define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
-#define DFS_DLLPRG1_V2IGC_OFFSET (0)
-#define DFS_DLLPRG1_V2IGC_MASK (0x00000007)
-
-#define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
-#define DFS_DLLPRG1_LCKWT_OFFSET (4)
-#define DFS_DLLPRG1_LCKWT_MASK (0x00000030)
-
-#define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
-#define DFS_DLLPRG1_DACIN_OFFSET (6)
-#define DFS_DLLPRG1_DACIN_MASK (0x000001C0)
-
-#define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
-#define DFS_DLLPRG1_CALBYPEN_OFFSET (9)
-#define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200)
-
-#define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
-#define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10)
-#define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00)
-
-#define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
-#define DFS_DLLPRG1_CPICTRL_OFFSET (12)
-#define DFS_DLLPRG1_CPICTRL_MASK (0x00007000)
-
-/* DFS Control Register (DFS_CTRL) */
-#define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
-#define DFS_CTRL_DLL_LOLIE (1 << 0)
-#define DFS_CTRL_DLL_RESET (1 << 1)
-
-/* DFS Port Status Register (DFS_PORTSR) */
-#define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
-/* DFS Port Reset Register (DFS_PORTRESET) */
-#define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
-#define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
-#define DFS_PORTRESET_PORTRESET_MAXVAL (0xF)
-#define DFS_PORTRESET_PORTRESET_MASK (0x0000000F)
-#define DFS_PORTRESET_PORTRESET_OFFSET (0)
-
-/* DFS Divide Register Portn (DFS_DVPORTn) */
-#define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
-
-/*
- * The mathematical formula for fdfs_clockout is the following:
- * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
- */
-#define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
-#define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
-#define DFS_DVPORTn_MFI_MASK (0x0000FF00)
-#define DFS_DVPORTn_MFN_MASK (0x000000FF)
-#define DFS_DVPORTn_MFI_MAXVAL (0xFF)
-#define DFS_DVPORTn_MFN_MAXVAL (0xFF)
-#define DFS_DVPORTn_MFI_OFFSET (8)
-#define DFS_DVPORTn_MFN_OFFSET (0)
-#define DFS_MAXNUMBER (4)
-
-#define DFS_PARAMS_Nr (3)
-
-/* Frequencies are in Hz */
-#define FIRC_CLK_FREQ (48000000)
-#define XOSC_CLK_FREQ (40000000)
-
-#define PLL_MIN_FREQ (650000000)
-#define PLL_MAX_FREQ (1300000000)
-
-#define ARM_PLL_PHI0_FREQ (1000000000)
-#define ARM_PLL_PHI1_FREQ (1000000000)
-/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
-#define ARM_PLL_PHI1_DFS1_EN (1)
-#define ARM_PLL_PHI1_DFS1_MFI (3)
-#define ARM_PLL_PHI1_DFS1_MFN (194)
-/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
-#define ARM_PLL_PHI1_DFS2_EN (1)
-#define ARM_PLL_PHI1_DFS2_MFI (1)
-#define ARM_PLL_PHI1_DFS2_MFN (170)
-/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
-#define ARM_PLL_PHI1_DFS3_EN (1)
-#define ARM_PLL_PHI1_DFS3_MFI (1)
-#define ARM_PLL_PHI1_DFS3_MFN (170)
-#define ARM_PLL_PHI1_DFS_Nr (3)
-#define ARM_PLL_PLLDV_PREDIV (2)
-#define ARM_PLL_PLLDV_MFD (50)
-#define ARM_PLL_PLLDV_MFN (0)
-
-#define PERIPH_PLL_PHI0_FREQ (400000000)
-#define PERIPH_PLL_PHI1_FREQ (100000000)
-#define PERIPH_PLL_PHI1_DFS_Nr (0)
-#define PERIPH_PLL_PLLDV_PREDIV (1)
-#define PERIPH_PLL_PLLDV_MFD (30)
-#define PERIPH_PLL_PLLDV_MFN (0)
-
-#define ENET_PLL_PHI0_FREQ (500000000)
-#define ENET_PLL_PHI1_FREQ (1000000000)
-/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
-#define ENET_PLL_PHI1_DFS1_EN (1)
-#define ENET_PLL_PHI1_DFS1_MFI (2)
-#define ENET_PLL_PHI1_DFS1_MFN (219)
-/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
-#define ENET_PLL_PHI1_DFS2_EN (1)
-#define ENET_PLL_PHI1_DFS2_MFI (2)
-#define ENET_PLL_PHI1_DFS2_MFN (219)
-/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
-#define ENET_PLL_PHI1_DFS3_EN (1)
-#define ENET_PLL_PHI1_DFS3_MFI (3)
-#define ENET_PLL_PHI1_DFS3_MFN (32)
-/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
-#define ENET_PLL_PHI1_DFS4_EN (1)
-#define ENET_PLL_PHI1_DFS4_MFI (2)
-#define ENET_PLL_PHI1_DFS4_MFN (0)
-#define ENET_PLL_PHI1_DFS_Nr (4)
-#define ENET_PLL_PLLDV_PREDIV (2)
-#define ENET_PLL_PLLDV_MFD (50)
-#define ENET_PLL_PLLDV_MFN (0)
-
-#define DDR_PLL_PHI0_FREQ (533000000)
-#define DDR_PLL_PHI1_FREQ (1066000000)
-/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
-#define DDR_PLL_PHI1_DFS1_EN (1)
-#define DDR_PLL_PHI1_DFS1_MFI (2)
-#define DDR_PLL_PHI1_DFS1_MFN (33)
-/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
-#define DDR_PLL_PHI1_DFS2_EN (1)
-#define DDR_PLL_PHI1_DFS2_MFI (2)
-#define DDR_PLL_PHI1_DFS2_MFN (33)
-/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
-#define DDR_PLL_PHI1_DFS3_EN (1)
-#define DDR_PLL_PHI1_DFS3_MFI (3)
-#define DDR_PLL_PHI1_DFS3_MFN (11)
-#define DDR_PLL_PHI1_DFS_Nr (3)
-#define DDR_PLL_PLLDV_PREDIV (2)
-#define DDR_PLL_PLLDV_MFD (53)
-#define DDR_PLL_PLLDV_MFN (6144)
-
-#define VIDEO_PLL_PHI0_FREQ (600000000)
-#define VIDEO_PLL_PHI1_FREQ (0)
-#define VIDEO_PLL_PHI1_DFS_Nr (0)
-#define VIDEO_PLL_PLLDV_PREDIV (1)
-#define VIDEO_PLL_PLLDV_MFD (30)
-#define VIDEO_PLL_PLLDV_MFN (0)
-
-#endif
-
-#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
deleted file mode 100644
index 1671af4adb3..00000000000
--- a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
-#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
-
-#ifndef __ASSEMBLY__
-
-/* MC_ME registers definitions */
-
-/* MC_ME_GS */
-#define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000)
-
-#define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0)
-#define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0)
-#define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0)
-#define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0)
-#define MC_ME_GS_S_FIRC (1 << 4)
-#define MC_ME_GS_S_XOSC (1 << 5)
-#define MC_ME_GS_S_ARMPLL (1 << 6)
-#define MC_ME_GS_S_PERPLL (1 << 7)
-#define MC_ME_GS_S_ENETPLL (1 << 8)
-#define MC_ME_GS_S_DDRPLL (1 << 9)
-#define MC_ME_GS_S_VIDEOPLL (1 << 10)
-#define MC_ME_GS_S_MVR (1 << 20)
-#define MC_ME_GS_S_PDO (1 << 23)
-#define MC_ME_GS_S_MTRANS (1 << 27)
-#define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28)
-#define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28)
-#define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28)
-#define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28)
-
-/* MC_ME_MCTL */
-#define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004)
-
-#define MC_ME_MCTL_KEY (0x00005AF0)
-#define MC_ME_MCTL_INVERTEDKEY (0x0000A50F)
-#define MC_ME_MCTL_RESET (0x0 << 28)
-#define MC_ME_MCTL_TEST (0x1 << 28)
-#define MC_ME_MCTL_DRUN (0x3 << 28)
-#define MC_ME_MCTL_RUN0 (0x4 << 28)
-#define MC_ME_MCTL_RUN1 (0x5 << 28)
-#define MC_ME_MCTL_RUN2 (0x6 << 28)
-#define MC_ME_MCTL_RUN3 (0x7 << 28)
-
-/* MC_ME_ME */
-#define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008)
-
-#define MC_ME_ME_RESET_FUNC (1 << 0)
-#define MC_ME_ME_TEST (1 << 1)
-#define MC_ME_ME_DRUN (1 << 3)
-#define MC_ME_ME_RUN0 (1 << 4)
-#define MC_ME_ME_RUN1 (1 << 5)
-#define MC_ME_ME_RUN2 (1 << 6)
-#define MC_ME_ME_RUN3 (1 << 7)
-
-/* MC_ME_RUN_PCn */
-#define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
-
-#define MC_ME_RUN_PCn_RESET (1 << 0)
-#define MC_ME_RUN_PCn_TEST (1 << 1)
-#define MC_ME_RUN_PCn_DRUN (1 << 3)
-#define MC_ME_RUN_PCn_RUN0 (1 << 4)
-#define MC_ME_RUN_PCn_RUN1 (1 << 5)
-#define MC_ME_RUN_PCn_RUN2 (1 << 6)
-#define MC_ME_RUN_PCn_RUN3 (1 << 7)
-
-/*
- * MC_ME_RESET_MC/MC_ME_TEST_MC
- * MC_ME_DRUN_MC
- * MC_ME_RUNn_MC
- */
-#define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020)
-#define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024)
-#define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C)
-#define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
-
-#define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
-#define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F)
-#define MC_ME_RUNMODE_MC_FIRCON (1 << 4)
-#define MC_ME_RUNMODE_MC_XOSCON (1 << 5)
-#define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll)))
-#define MC_ME_RUNMODE_MC_MVRON (1 << 20)
-#define MC_ME_RUNMODE_MC_PDO (1 << 23)
-#define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28)
-#define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29)
-#define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30)
-
-/* MC_ME_DRUN_SEC_CC_I */
-#define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260)
-/* MC_ME_RUNn_SEC_CC_I */
-#define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12)
-#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3)
-
-/*
- * ME_PCTLn
- * Please note that these registers are 8 bits width, so
- * the operations over them should be done using 8 bits operations.
- */
-#define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK )
-#define MC_ME_PCTLn_RUNPCm_MASK (0x7)
-
-/* DEC200 Peripheral Control Register */
-#define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4)
-/* 2D-ACE Peripheral Control Register */
-#define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB)
-/* ENET Peripheral Control Register */
-#define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1)
-/* DMACHMUX0 Peripheral Control Register */
-#define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2)
-/* CSI0 Peripheral Control Register */
-#define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3)
-/* MMDC0 Peripheral Control Register */
-#define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5)
-/* FRAY Peripheral Control Register */
-#define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7)
-/* PIT0 Peripheral Control Register */
-#define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9)
-/* FlexTIMER0 Peripheral Control Register */
-#define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C)
-/* SARADC0 Peripheral Control Register */
-#define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E)
-/* LINFLEX0 Peripheral Control Register */
-#define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110)
-/* IIC0 Peripheral Control Register */
-#define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112)
-/* DSPI0 Peripheral Control Register */
-#define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114)
-/* CANFD0 Peripheral Control Register */
-#define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116)
-/* CRC0 Peripheral Control Register */
-#define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118)
-/* DSPI2 Peripheral Control Register */
-#define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A)
-/* SDHC Peripheral Control Register */
-#define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E)
-/* VIU0 Peripheral Control Register */
-#define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127)
-/* HPSMI Peripheral Control Register */
-#define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B)
-/* SIPI Peripheral Control Register */
-#define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137)
-/* LFAST Peripheral Control Register */
-#define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B)
-/* MMDC1 Peripheral Control Register */
-#define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161)
-/* DMACHMUX1 Peripheral Control Register */
-#define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162)
-/* CSI1 Peripheral Control Register */
-#define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163)
-/* QUADSPI0 Peripheral Control Register */
-#define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165)
-/* PIT1 Peripheral Control Register */
-#define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169)
-/* FlexTIMER1 Peripheral Control Register */
-#define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175)
-/* IIC2 Peripheral Control Register */
-#define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179)
-/* IIC1 Peripheral Control Register */
-#define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B)
-/* CANFD1 Peripheral Control Register */
-#define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D)
-/* LINFLEX1 Peripheral Control Register */
-#define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F)
-/* DSPI3 Peripheral Control Register */
-#define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181)
-/* DSPI1 Peripheral Control Register */
-#define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183)
-/* TSENS Peripheral Control Register */
-#define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D)
-/* CRC1 Peripheral Control Register */
-#define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F)
-/* VIU1 Peripheral Control Register */
-#define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193)
-/* JPEG Peripheral Control Register */
-#define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197)
-/* H264_DEC Peripheral Control Register */
-#define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B)
-/* H264_ENC Peripheral Control Register */
-#define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F)
-/* MBIST Peripheral Control Register */
-#define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9)
-
-/* Core status register */
-#define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0)
-
-#endif
-
-#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
deleted file mode 100644
index 34501b2189b..00000000000
--- a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
-#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
-
-#define MC_RGM_DES (MC_RGM_BASE_ADDR)
-#define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
-#define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
-#define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
-#define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
-#define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
-#define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
-#define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
-#define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
-#define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
-#define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
-
-/* function reset sources mask */
-#define F_SWT4 0x8000
-#define F_JTAG 0x400
-#define F_FCCU_SOFT 0x40
-#define F_FCCU_HARD 0x20
-#define F_SOFT_FUNC 0x8
-#define F_ST_DONE 0x4
-#define F_EXT_RST 0x1
-
-#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h
deleted file mode 100644
index 8d74ae02661..00000000000
--- a/arch/arm/include/asm/arch-s32v234/mmdc.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
-#define __ARCH_ARM_MACH_S32V234_MMDC_H__
-
-#define MMDC0 0
-#define MMDC1 1
-
-#define MMDC_MDCTL 0x0
-#define MMDC_MDPDC 0x4
-#define MMDC_MDOTC 0x8
-#define MMDC_MDCFG0 0xC
-#define MMDC_MDCFG1 0x10
-#define MMDC_MDCFG2 0x14
-#define MMDC_MDMISC 0x18
-#define MMDC_MDSCR 0x1C
-#define MMDC_MDREF 0x20
-#define MMDC_MDRWD 0x2C
-#define MMDC_MDOR 0x30
-#define MMDC_MDMRR 0x34
-#define MMDC_MDCFG3LP 0x38
-#define MMDC_MDMR4 0x3C
-#define MMDC_MDASP 0x40
-#define MMDC_MAARCR 0x400
-#define MMDC_MAPSR 0x404
-#define MMDC_MAEXIDR0 0x408
-#define MMDC_MAEXIDR1 0x40C
-#define MMDC_MADPCR0 0x410
-#define MMDC_MADPCR1 0x414
-#define MMDC_MADPSR0 0x418
-#define MMDC_MADPSR1 0x41C
-#define MMDC_MADPSR2 0x420
-#define MMDC_MADPSR3 0x424
-#define MMDC_MADPSR4 0x428
-#define MMDC_MADPSR5 0x42C
-#define MMDC_MASBS0 0x430
-#define MMDC_MASBS1 0x434
-#define MMDC_MAGENP 0x440
-#define MMDC_MPZQHWCTRL 0x800
-#define MMDC_MPWLGCR 0x808
-#define MMDC_MPWLDECTRL0 0x80C
-#define MMDC_MPWLDECTRL1 0x810
-#define MMDC_MPWLDLST 0x814
-#define MMDC_MPODTCTRL 0x818
-#define MMDC_MPRDDQBY0DL 0x81C
-#define MMDC_MPRDDQBY1DL 0x820
-#define MMDC_MPRDDQBY2DL 0x824
-#define MMDC_MPRDDQBY3DL 0x828
-#define MMDC_MPDGCTRL0 0x83C
-#define MMDC_MPDGCTRL1 0x840
-#define MMDC_MPDGDLST0 0x844
-#define MMDC_MPRDDLCTL 0x848
-#define MMDC_MPRDDLST 0x84C
-#define MMDC_MPWRDLCTL 0x850
-#define MMDC_MPWRDLST 0x854
-#define MMDC_MPZQLP2CTL 0x85C
-#define MMDC_MPRDDLHWCTL 0x860
-#define MMDC_MPWRDLHWCTL 0x864
-#define MMDC_MPRDDLHWST0 0x868
-#define MMDC_MPRDDLHWST1 0x86C
-#define MMDC_MPWRDLHWST1 0x870
-#define MMDC_MPWRDLHWST2 0x874
-#define MMDC_MPWLHWERR 0x878
-#define MMDC_MPDGHWST0 0x87C
-#define MMDC_MPDGHWST1 0x880
-#define MMDC_MPDGHWST2 0x884
-#define MMDC_MPDGHWST3 0x888
-#define MMDC_MPPDCMPR1 0x88C
-#define MMDC_MPPDCMPR2 0x890
-#define MMDC_MPSWDAR0 0x894
-#define MMDC_MPSWDRDR0 0x898
-#define MMDC_MPSWDRDR1 0x89C
-#define MMDC_MPSWDRDR2 0x8A0
-#define MMDC_MPSWDRDR3 0x8A4
-#define MMDC_MPSWDRDR4 0x8A8
-#define MMDC_MPSWDRDR5 0x8AC
-#define MMDC_MPSWDRDR6 0x8B0
-#define MMDC_MPSWDRDR7 0x8B4
-#define MMDC_MPMUR0 0x8B8
-#define MMDC_MPDCCR 0x8C0
-
-#define MMDC_MPMUR0_FRC_MSR (1 << 11)
-#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h
deleted file mode 100644
index 7572581054a..00000000000
--- a/arch/arm/include/asm/arch-s32v234/siul.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
-#define __ARCH_ARM_MACH_S32V234_SIUL_H__
-
-#include "ddr.h"
-
-#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
-#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
-#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
-#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
-#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
-#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
-#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
-#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
-
-#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
-#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i))
-
-#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
-
-/* SIUL2_MSCR specifications as stated in Reference Manual:
- * 0 - 359 Output Multiplexed Signal Configuration Registers
- * 512- 1023 Input Multiplexed Signal Configuration Registers */
-#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240)
-#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i))
-
-#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40)
-#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i))
-
-#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300)
-#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i))
-
-#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500)
-#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i))
-
-#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700)
-#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i))
-
-#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740)
-#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i))
-
-#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780)
-#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i))
-
-/* SIUL2_MSCR masks */
-#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000)
-#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30)
-#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30)
-#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30)
-#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30)
-
-#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000)
-#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29)
-#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29)
-
-#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000)
-#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27)
-#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27)
-
-#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000)
-#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24)
-#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24)
-#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24)
-#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24)
-#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24)
-#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24)
-#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24)
-
-#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000)
-#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22)
-#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22)
-#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22)
-
-#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000)
-#define SIUL2_MSCR_OBE_EN (1 << 21)
-
-#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000)
-#define SIUL2_MSCR_ODE_EN (1 << 20)
-
-#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000)
-#define SIUL2_MSCR_IBE_EN (1 << 19)
-
-#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000)
-#define SIUL2_MSCR_HYS_EN (1 << 18)
-
-#define SIUL2_MSCR_INV(v) ((v) & 0x00020000)
-#define SIUL2_MSCR_INV_EN (1 << 17)
-
-#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000)
-#define SIUL2_MSCR_PKE_EN (1 << 16)
-
-#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000)
-#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14)
-#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14)
-#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14)
-#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14)
-
-#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000)
-#define SIUL2_MSCR_PUE_EN (1 << 13)
-
-#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800)
-#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11)
-#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11)
-#define SIUL2_MSCR_PUS_100K_UP (2 << 11)
-#define SIUL2_MSCR_PUS_33K_UP (3 << 11)
-
-#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700)
-#define SIUL2_MSCR_DSE_240ohm (1 << 8)
-#define SIUL2_MSCR_DSE_120ohm (2 << 8)
-#define SIUL2_MSCR_DSE_80ohm (3 << 8)
-#define SIUL2_MSCR_DSE_60ohm (4 << 8)
-#define SIUL2_MSCR_DSE_48ohm (5 << 8)
-#define SIUL2_MSCR_DSE_40ohm (6 << 8)
-#define SIUL2_MSCR_DSE_34ohm (7 << 8)
-
-#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0)
-#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6)
-
-#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020)
-#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f)
-#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1)
-#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2)
-#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3)
-
-/* UART settings */
-#define SIUL2_UART0_TXD_PAD 12
-#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \
- SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
-
-#define SIUL2_UART0_MSCR_RXD_PAD 11
-#define SIUL2_UART0_IMCR_RXD_PAD 200
-
-#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
-#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2)
-
-/* uSDHC settings */
-#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \
- SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \
- SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
-#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
-#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
-#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
-#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
-
-#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */
diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig
deleted file mode 100644
index e71dfc4ab22..00000000000
--- a/board/freescale/s32v234evb/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if TARGET_S32V234EVB
-
-config SYS_CPU
- string
- default "armv8"
-
-config SYS_BOARD
- string
- default "s32v234evb"
-
-config SYS_VENDOR
- string
- default "freescale"
-
-config SYS_SOC
- string
- default "s32v234"
-
-config SYS_CONFIG_NAME
- string
- default "s32v234evb"
-
-endif
diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS
deleted file mode 100644
index 62b2e1b264f..00000000000
--- a/board/freescale/s32v234evb/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-S32V234 Evaluation BOARD
-M: Eddy Petrișor <eddy.petrisor@gmail.com>
-S: Maintained
-F: arch/arm/cpu/armv8/s32v234/
-F: arch/arm/include/asm/arch-s32v234/
-F: board/freescale/s32v234evb/
-F: include/configs/s32v234evb.h
-F: configs/s32v234evb_defconfig
diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile
deleted file mode 100644
index f6028e12776..00000000000
--- a/board/freescale/s32v234evb/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
-
-obj-y := clock.o
-obj-y += lpddr2.o
-obj-y += s32v234evb.o
-
-#########################################################################
diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c
deleted file mode 100644
index 21c619fa1ad..00000000000
--- a/board/freescale/s32v234evb/clock.c
+++ /dev/null
@@ -1,343 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mc_cgm_regs.h>
-#include <asm/arch/mc_me_regs.h>
-#include <asm/arch/clock.h>
-
-/*
- * Select the clock reference for required pll.
- * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
- * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
- */
-static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)
-{
- u32 clk_src;
- u32 pll_idx;
- volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR;
-
- /* select the pll clock source */
- switch (refclk_freq) {
- case FIRC_CLK_FREQ:
- clk_src = SRC_GPR1_FIRC_CLK_SOURCE;
- break;
- case XOSC_CLK_FREQ:
- clk_src = SRC_GPR1_XOSC_CLK_SOURCE;
- break;
- default:
- /* The clock frequency for the source clock is unknown */
- return -1;
- }
- /*
- * The hardware definition is not uniform, it has to calculate again
- * the recurrence formula.
- */
- switch (pll) {
- case PERIPH_PLL:
- pll_idx = 3;
- break;
- case ENET_PLL:
- pll_idx = 1;
- break;
- case DDR_PLL:
- pll_idx = 2;
- break;
- default:
- pll_idx = pll;
- }
-
- writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src),
- &src->gpr1);
-
- return 0;
-}
-
-static void entry_to_target_mode(u32 mode)
-{
- writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL);
- writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL);
- while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ;
-}
-
-/*
- * Program the pll according to the input parameters.
- * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
- * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
- * freq - expected output frequency for PHY0
- * freq1 - expected output frequency for PHY1
- * dfs_nr - number of DFS modules for current PLL
- * dfs - array with the activation dfs field, mfn and mfi
- * plldv_prediv - divider of clkfreq_ref
- * plldv_mfd - loop multiplication factor divider
- * pllfd_mfn - numerator loop multiplication factor divider
- * Please consult the PLLDIG chapter of platform manual
- * before to use this function.
- *)
- */
-static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1,
- u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv,
- u32 plldv_mfd, u32 pllfd_mfn)
-{
- u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco;
-
- /*
- * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter.
- */
- fvco =
- (refclk_freq / plldv_prediv) * (plldv_mfd +
- pllfd_mfn / (float)20480);
-
- /*
- * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult
- * the platform DataSheet in order to determine the allowed values.
- */
-
- if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) {
- return -1;
- }
-
- if (select_pll_source_clk(pll, refclk_freq) < 0) {
- return -1;
- }
-
- rfdphi = fvco / freq0;
-
- rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1;
-
- writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) |
- PLLDIG_PLLDV_RFDPHI_SET(rfdphi) |
- PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) |
- PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll));
-
- writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) |
- PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll));
-
- /* switch on the pll in current mode */
- writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll),
- MC_ME_RUNn_MC(0));
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-
- /* Only ARM_PLL, ENET_PLL and DDR_PLL */
- if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) {
- /* DFS clk enable programming */
- writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll));
-
- writel(DFS_DLLPRG1_CPICTRL_SET(0x5) |
- DFS_DLLPRG1_VSETTLCTRL_SET(0x1) |
- DFS_DLLPRG1_CALBYPEN_SET(0x0) |
- DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) |
- DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll));
-
- for (i = 0; i < dfs_nr; i++) {
- if (dfs[i][0]) {
- writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) |
- DFS_DVPORTn_MFN_SET(dfs[i][1]),
- DFS_DVPORTn(pll, i));
- dfs_on |= (dfs[i][0] << i);
- }
- }
-
- writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET,
- DFS_CTRL(pll));
- writel(readl(DFS_PORTRESET(pll)) &
- ~DFS_PORTRESET_PORTRESET_SET(dfs_on),
- DFS_PORTRESET(pll));
- while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ;
- }
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-
- return 0;
-
-}
-
-static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source)
-{
- /* select the clock source */
- writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac));
-}
-
-static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider)
-{
- /* set the divider */
- writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider),
- CGM_ACn_DCm(cgm_addr, ac, dc));
-}
-
-static void setup_sys_clocks(void)
-{
-
- /* set ARM PLL DFS 1 as SYSCLK */
- writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) |
- MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0));
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-
- /* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */
- writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK
- (0x2,
- MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) |
- MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
- MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET)
- | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
- MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET),
- MC_ME_RUNn_SEC_CC_I(0));
-
- /* setup the sys clock divider for CORE_CLK (1000MHz) */
- writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
- CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0));
-
- /* setup the sys clock divider for CORE2_CLK (500MHz) */
- writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
- CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1));
- /* setup the sys clock divider for SYS3_CLK (266 MHz) */
- writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
- CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0));
-
- /* setup the sys clock divider for SYS6_CLK (133 Mhz) */
- writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
- CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1));
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-
-}
-
-static void setup_aux_clocks(void)
-{
- /*
- * setup the aux clock divider for PERI_CLK
- * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)
- */
- aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX);
- aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4);
-
- /* setup the aux clock divider for LIN_CLK (40MHz) */
- aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX);
- aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1);
-
- /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */
- aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL);
- aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9);
-
- /* setup the aux clock divider for ENET_CLK (50MHz) */
- aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL);
- aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9);
-
- /* setup the aux clock divider for SDHC_CLK (50 MHz). */
- aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL);
- aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9);
-
- /* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */
- aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL);
- aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0);
- /* setup the aux clock divider for DDR4_CLK (133,25MHz) */
- aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3);
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-
-}
-
-static void enable_modules_clock(void)
-{
- /* PIT0 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58);
- /* PIT1 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170);
- /* LINFLEX0 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83);
- /* LINFLEX1 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188);
- /* ENET */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50);
- /* SDHC */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93);
- /* IIC0 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81);
- /* IIC1 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184);
- /* IIC2 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186);
- /* MMDC0 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54);
- /* MMDC1 */
- writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162);
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-}
-
-void clock_init(void)
-{
- unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
- {ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN,
- ARM_PLL_PHI1_DFS1_MFI},
- {ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN,
- ARM_PLL_PHI1_DFS2_MFI},
- {ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN,
- ARM_PLL_PHI1_DFS3_MFI}
- };
-
- unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
- {ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN,
- ENET_PLL_PHI1_DFS1_MFI},
- {ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN,
- ENET_PLL_PHI1_DFS2_MFI},
- {ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN,
- ENET_PLL_PHI1_DFS3_MFI},
- {ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN,
- ENET_PLL_PHI1_DFS4_MFI}
- };
-
- unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
- {DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN,
- DDR_PLL_PHI1_DFS1_MFI},
- {DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN,
- DDR_PLL_PHI1_DFS2_MFI},
- {DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN,
- DDR_PLL_PHI1_DFS3_MFI}
- };
-
- writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 |
- MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0));
-
- /* turn on FXOSC */
- writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON |
- MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1),
- MC_ME_RUNn_MC(0));
-
- entry_to_target_mode(MC_ME_MCTL_RUN0);
-
- program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ,
- ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs,
- ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN);
-
- setup_sys_clocks();
-
- program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ,
- PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL,
- PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD,
- PERIPH_PLL_PLLDV_MFN);
-
- program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ,
- ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs,
- ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD,
- ENET_PLL_PLLDV_MFN);
-
- program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ,
- DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs,
- DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN);
-
- program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ,
- VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL,
- VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD,
- VIDEO_PLL_PLLDV_MFN);
-
- setup_aux_clocks();
-
- enable_modules_clock();
-
-}
diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c
deleted file mode 100644
index b3775d3763e..00000000000
--- a/board/freescale/s32v234evb/lpddr2.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015, Freescale Semiconductor, Inc.
- */
-
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/siul.h>
-#include <asm/arch/lpddr2.h>
-#include <asm/arch/mmdc.h>
-
-volatile int mscr_offset_ck0;
-
-void lpddr2_config_iomux(uint8_t module)
-{
- int i;
-
- switch (module) {
- case DDR0:
- mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
- writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
-
- writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
- writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
-
- writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
- writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
-
- for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
- writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
-
- for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
- writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
-
- for (i = _DDR0_A0; i <= _DDR0_A9; i++)
- writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
-
- for (i = _DDR0_D0; i <= _DDR0_D31; i++)
- writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
- break;
- case DDR1:
- writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
-
- writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
- writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
-
- writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
- writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
-
- for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
- writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
-
- for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
- writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
-
- for (i = _DDR1_A0; i <= _DDR1_A9; i++)
- writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
-
- for (i = _DDR1_D0; i <= _DDR1_D31; i++)
- writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
- break;
- }
-}
-
-void config_mmdc(uint8_t module)
-{
- unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
-
- writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
-
- writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
- writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
- writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
- writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
- writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
- writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
- writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
- writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
-
- writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
-
- while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
- }
-
- writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
-
- /* Perform ZQ calibration */
- writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
- writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
- while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
- }
-
- /* Enable MMDC with CS0 */
- writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
-
- /* Complete the initialization sequence as defined by JEDEC */
- writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
- writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
- writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
- writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
-
- /* Set the amount of DRAM */
- /* Set DQS settings based on board type */
-
- switch (module) {
- case MMDC0:
- writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
- writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
- mmdc_addr + MMDC_MPRDDLCTL);
- writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
- mmdc_addr + MMDC_MPWRDLCTL);
- writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
- mmdc_addr + MMDC_MPDGCTRL0);
- writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
- mmdc_addr + MMDC_MPDGCTRL1);
- break;
- case MMDC1:
- writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
- writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
- mmdc_addr + MMDC_MPRDDLCTL);
- writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
- mmdc_addr + MMDC_MPWRDLCTL);
- writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
- mmdc_addr + MMDC_MPDGCTRL0);
- writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
- mmdc_addr + MMDC_MPDGCTRL1);
- break;
- }
-
- writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
- writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
- writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
- writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
- writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
-
-}
diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c
deleted file mode 100644
index 464be2b4e09..00000000000
--- a/board/freescale/s32v234evb/s32v234evb.c
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/siul.h>
-#include <asm/arch/lpddr2.h>
-#include <asm/arch/clock.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void setup_iomux_ddr(void)
-{
- lpddr2_config_iomux(DDR0);
- lpddr2_config_iomux(DDR1);
-
-}
-
-void ddr_phy_init(void)
-{
-}
-
-void ddr_ctrl_init(void)
-{
- config_mmdc(0);
- config_mmdc(1);
-}
-
-int dram_init(void)
-{
- setup_iomux_ddr();
-
- ddr_ctrl_init();
-
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
- return 0;
-}
-
-static void setup_iomux_uart(void)
-{
- /* Muxing for linflex */
- /* Replace the magic values after bringup */
-
- /* set TXD - MSCR[12] PA12 */
- writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
-
- /* set RXD - MSCR[11] - PA11 */
- writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
-
- /* set RXD - IMCR[200] - 200 */
- writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
-}
-
-static void setup_iomux_enet(void)
-{
-}
-
-static void setup_iomux_i2c(void)
-{
-}
-
-#ifdef CONFIG_SYS_USE_NAND
-void setup_iomux_nfc(void)
-{
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {USDHC_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* eSDHC1 is always present */
- return 1;
-}
-
-int board_mmc_init(bd_t * bis)
-{
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
-
- /* Set iomux PADS for USDHC */
-
- /* PK6 pad: uSDHC clk */
- writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
- writel(0x3, SIUL2_MSCRn(902));
-
- /* PK7 pad: uSDHC CMD */
- writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
- writel(0x3, SIUL2_MSCRn(901));
-
- /* PK8 pad: uSDHC DAT0 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
- writel(0x3, SIUL2_MSCRn(903));
-
- /* PK9 pad: uSDHC DAT1 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
- writel(0x3, SIUL2_MSCRn(904));
-
- /* PK10 pad: uSDHC DAT2 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
- writel(0x3, SIUL2_MSCRn(905));
-
- /* PK11 pad: uSDHC DAT3 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
- writel(0x3, SIUL2_MSCRn(906));
-
- /* PK15 pad: uSDHC DAT4 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
- writel(0x3, SIUL2_MSCRn(907));
-
- /* PL0 pad: uSDHC DAT5 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
- writel(0x3, SIUL2_MSCRn(908));
-
- /* PL1 pad: uSDHC DAT6 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
- writel(0x3, SIUL2_MSCRn(909));
-
- /* PL2 pad: uSDHC DAT7 */
- writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
- writel(0x3, SIUL2_MSCRn(910));
-
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
-static void mscm_init(void)
-{
- struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
- int i;
-
- for (i = 0; i < MSCM_IRSPRC_NUM; i++)
- writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- clock_init();
- mscm_init();
-
- setup_iomux_uart();
- setup_iomux_enet();
- setup_iomux_i2c();
-#ifdef CONFIG_SYS_USE_NAND
- setup_iomux_nfc();
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: s32v234evb\n");
-
- return 0;
-}
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg
deleted file mode 100644
index 526b7d177fe..00000000000
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
- */
-
-/*
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-#include <asm/mach-imx/imximage.cfg>
-
-/* image version */
-IMAGE_VERSION 2
-BOOT_FROM sd
-
-
-/*
- * Boot Device : one of qspi, sd:
- * qspi: flash_offset: 0x1000
- * sd/mmc: flash_offset: 0x1000
- */
-
-
-#ifdef CONFIG_SECURE_BOOT
-SECURE_BOOT
-#endif
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
deleted file mode 100644
index b18a63b325e..00000000000
--- a/configs/s32v234evb_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_S32V234EVB=y
-CONFIG_SYS_TEXT_BASE=0x3E800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyLF0 root=/dev/ram rw"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LINFLEXUART=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
deleted file mode 100644
index 216932046bc..00000000000
--- a/include/configs/s32v234evb.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Freescale S32V234 EVB board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_S32V234
-
-/* Config GIC */
-#define CONFIG_GICV2
-#define GICD_BASE 0x7D001000
-#define GICC_BASE 0x7D002000
-
-#define CONFIG_REMAKE_ELF
-#undef CONFIG_RUN_FROM_IRAM_ONLY
-
-#define CONFIG_RUN_FROM_DDR1
-#undef CONFIG_RUN_FROM_DDR0
-
-/* Run by default from DDR1 */
-#ifdef CONFIG_RUN_FROM_DDR0
-#define DDR_BASE_ADDR 0x80000000
-#else
-#define DDR_BASE_ADDR 0xC0000000
-#endif
-
-#define CONFIG_MACH_TYPE 4146
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* Config CACHE */
-#define CONFIG_CMD_CACHE
-
-#define CONFIG_SYS_FULL_VA
-
-/* Enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG
-
-/* SMP Spin Table Definitions */
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-
-/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */
-#define CONFIG_SYS_FSL_ERRATUM_A008585
-
-/* Size of malloc() pool */
-#ifdef CONFIG_RUN_FROM_IRAM_ONLY
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024)
-#else
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-#endif
-
-#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR
-
-#define CONFIG_DEBUG_UART_LINFLEXUART
-#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE
-
-/* Allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_UART_PORT (1)
-
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-#define CONFIG_CMD_MMC
-/* #define CONFIG_CMD_EXT2 EXT2 Support */
-
-#if 0
-
-/* Ethernet config */
-#define CONFIG_CMD_MII
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_FEC_MXC_PHYADDR 0
-#endif
-
-#if 0 /* Disable until the FLASH will be implemented */
-#define CONFIG_SYS_USE_NAND
-#endif
-
-#ifdef CONFIG_SYS_USE_NAND
-/* Nand Flash Configs */
-#define CONFIG_JFFS2_NAND
-#define MTD_NAND_FSL_NFC_SWECC 1
-#define CONFIG_NAND_FSL_NFC
-#define CONFIG_SYS_NAND_BASE 0x400E0000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_NAND_SELECT_DEVICE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-#endif
-
-#define CONFIG_LOADADDR 0xC307FFC0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "boot_scripts=boot.scr.uimg boot.scr\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "console=ttyLF0,115200\0" \
- "fdt_file=s32v234-evb.dtb\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_addr_r=0xC2000000\0" \
- "kernel_addr_r=0xC307FFC0\0" \
- "ramdisk_addr_r=0xC4000000\0" \
- "ramdisk=rootfs.uimg\0"\
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "update_sd_firmware_filename=u-boot.imx\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
- "jtagboot=echo Booting using jtag...; " \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
- "run loaduimage; run loadramdisk; run loadfdt;"\
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "boot_net_usb_start=true\0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 0) \
- func(DHCP, dhcp, na)
-
-#define CONFIG_BOOTCOMMAND \
- "run distro_bootcmd"
-
-#include <config_distro_bootcmd.h>
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT "=> "
-
-#define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR)
-#define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-#ifdef CONFIG_RUN_FROM_IRAM_ONLY
-#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR)
-#endif
-
-#if 0
-/* Configure PXE */
-#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
-#endif
-
-/* Physical memory map */
-/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
-#define PHYS_SDRAM (DDR_BASE_ADDR)
-#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 05/93] arm: Remove ls1043ardb_sdcard_SECURE_BOOT board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (3 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 04/93] arm: Remove s32v234evb board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 06/93] arm: Remove ls1046ardb_sdcard_SECURE_BOOT board Simon Glass
` (92 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/freescale/ls1043ardb/Kconfig | 41 ---
board/freescale/ls1043ardb/MAINTAINERS | 16 -
board/freescale/ls1043ardb/Makefile | 10 -
board/freescale/ls1043ardb/README | 54 ----
board/freescale/ls1043ardb/cpld.c | 173 -----------
board/freescale/ls1043ardb/cpld.h | 45 ---
board/freescale/ls1043ardb/ddr.c | 238 ---------------
board/freescale/ls1043ardb/ddr.h | 116 -------
board/freescale/ls1043ardb/eth.c | 76 -----
board/freescale/ls1043ardb/ls1043ardb.c | 221 --------------
board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 -
.../ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 -
.../ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 -
configs/ls1043ardb_SECURE_BOOT_defconfig | 51 ----
configs/ls1043ardb_defconfig | 49 ---
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 68 -----
configs/ls1043ardb_nand_defconfig | 66 ----
.../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 66 ----
configs/ls1043ardb_sdcard_defconfig | 64 ----
include/configs/ls1043ardb.h | 285 ------------------
21 files changed, 1668 deletions(-)
delete mode 100644 board/freescale/ls1043ardb/Kconfig
delete mode 100644 board/freescale/ls1043ardb/MAINTAINERS
delete mode 100644 board/freescale/ls1043ardb/Makefile
delete mode 100644 board/freescale/ls1043ardb/README
delete mode 100644 board/freescale/ls1043ardb/cpld.c
delete mode 100644 board/freescale/ls1043ardb/cpld.h
delete mode 100644 board/freescale/ls1043ardb/ddr.c
delete mode 100644 board/freescale/ls1043ardb/ddr.h
delete mode 100644 board/freescale/ls1043ardb/eth.c
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb.c
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_defconfig
delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_nand_defconfig
delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_sdcard_defconfig
delete mode 100644 include/configs/ls1043ardb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 11f2e0f826d..08d6db1cadf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1513,7 +1513,6 @@ source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
-source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
deleted file mode 100644
index 3d9e295c4e7..00000000000
--- a/board/freescale/ls1043ardb/Kconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-
-if TARGET_LS1043ARDB
-
-config SYS_BOARD
- default "ls1043ardb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls1043ardb"
-
-config SYS_HAS_ARMV8_SECURE_BASE
- bool "Enable secure address for PSCI image"
- depends on ARMV8_PSCI
- default n
- help
- PSCI image can be re-located to secure RAM.
- If enabled, please also define the value for ARMV8_SECURE_BASE,
- for LS1043ARDB, it could be some address in OCRAM.
-
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
deleted file mode 100644
index 88fe42e1e8a..00000000000
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ /dev/null
@@ -1,16 +0,0 @@
-LS1043A BOARD
-M: Mingkai Hu <mingkai.hu@nxp.com>
-S: Maintained
-F: board/freescale/ls1043ardb/
-F: board/freescale/ls1043ardb/ls1043ardb.c
-F: include/configs/ls1043ardb.h
-F: configs/ls1043ardb_defconfig
-F: configs/ls1043ardb_nand_defconfig
-F: configs/ls1043ardb_sdcard_defconfig
-
-LS1043A_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/ls1043ardb_SECURE_BOOT_defconfig
-F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
-F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
deleted file mode 100644
index 5309576c688..00000000000
--- a/board/freescale/ls1043ardb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2015 Freescale Semiconductor
-
-obj-y += ddr.o
-obj-y += ls1043ardb.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_NET) += eth.o
-obj-y += cpld.o
-endif
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
deleted file mode 100644
index 709ddbbef31..00000000000
--- a/board/freescale/ls1043ardb/README
+++ /dev/null
@@ -1,54 +0,0 @@
-Overview
---------
-The LS1043A Reference Design Board (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS1043A
-LayerScape Architecture processor. The LS1043ARDB provides SW development
-platform for the Freescale LS1043A processor series, with a complete
-debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
-
-LS1043A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
-SoC overview.
-
- LS1043ARDB board Overview
- -----------------------
- - SERDES Connections, 4 lanes supporting:
- - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
- standard PCIe card
- - QSGMII with x4 RJ45 connector
- - XFI with x1 RJ45 connector
- - DDR Controller
- - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
- -IFC/Local Bus
- - One 128MB NOR flash 16-bit data bus
- - One 512 MB NAND flash with ECC support
- - CPLD connection
- - USB 3.0
- - Two super speed USB 3.0 Type A ports
- - SDHC: connects directly to a full SD/MMC slot
- - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 4 I2C controllers
- - UART
- - Two 4-pin serial ports at up to 115.2 Kbit/s
- - Two DB9 D-Type connectors supporting one Serial port each
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-Start Address End Address Description Size
-0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
-0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
-0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
-0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
-0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
-0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
-0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
-
-Booting Options
----------------
-a) NOR boot
-b) NAND boot
-c) SD boot
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
deleted file mode 100644
index 00c70b1e49d..00000000000
--- a/board/freescale/ls1043ardb/cpld.c
+++ /dev/null
@@ -1,173 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * Freescale LS1043ARDB board-specific CPLD controlling supports.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/* Set the boot bank to the alternate bank */
-void cpld_set_altbank(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_NOR;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
- u8 reg7 = CPLD_READ(vbank);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
- CPLD_WRITE(vbank, reg7);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-/* Set the boot bank to the default bank */
-void cpld_set_defbank(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_NOR;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(vbank, 0);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_set_nand(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_NAND;
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_set_sd(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_SD;
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(system_rst, 1);
-}
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
- printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
- printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
- printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
- printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
- printf("vbank = %x\n", CPLD_READ(vbank));
- printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
- printf("uart_sel = %x\n", CPLD_READ(uart_sel));
- printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
- printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
- printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
- printf("status_led = %x\n", CPLD_READ(status_led));
- putc('\n');
-}
-#endif
-
-void cpld_rev_bit(unsigned char *value)
-{
- u8 rev_val, val;
- int i;
-
- val = *value;
- rev_val = val & 1;
- for (i = 1; i <= 7; i++) {
- val >>= 1;
- rev_val <<= 1;
- rev_val |= val & 1;
- }
-
- *value = rev_val;
-}
-
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else if (strcmp(argv[2], "nand") == 0)
- cpld_set_nand();
- else if (strcmp(argv[2], "sd") == 0)
- cpld_set_sd();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else {
- rc = cmd_usage(cmdtp);
- }
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset: reset to default bank\n"
- "cpld reset altbank: reset to alternate bank\n"
- "cpld reset nand: reset to boot from NAND flash\n"
- "cpld reset sd: reset to boot from SD card\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
-);
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
deleted file mode 100644
index 2e757b557f4..00000000000
--- a/board/freescale/ls1043ardb/cpld.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor
- */
-
-#ifndef __CPLD_H__
-#define __CPLD_H__
-
-/*
- * CPLD register set of LS1043ARDB board-specific.
- */
-struct cpld_data {
- u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
- u8 pcba_ver; /* 0x2 - PCBA Revision Register */
- u8 system_rst; /* 0x3 - system reset register */
- u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
- u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
- u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
- u8 vbank; /* 0x7 - Flash bank selection Control */
- u8 sysclk_sel; /* 0x8 - */
- u8 uart_sel; /* 0x9 - */
- u8 sd1refclk_sel; /* 0xA - */
- u8 tdmclk_mux_sel; /* 0xB - */
- u8 sdhc_spics_sel; /* 0xC - */
- u8 status_led; /* 0xD - */
- u8 global_rst; /* 0xE - */
-};
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-void cpld_rev_bit(unsigned char *value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \
- cpld_write(offsetof(struct cpld_data, reg), value)
-
-/* CPLD on IFC */
-#define CPLD_SW_MUX_BANK_SEL 0x40
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_SEL_ALTBANK 0x04
-#define CPLD_CFG_RCW_SRC_NOR 0x025
-#define CPLD_CFG_RCW_SRC_NAND 0x106
-#define CPLD_CFG_RCW_SRC_SD 0x040
-#endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
deleted file mode 100644
index 7bc0f568ffb..00000000000
--- a/board/freescale/ls1043ardb/ddr.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-#ifdef CONFIG_FSL_DEEP_SLEEP
-#include <fsl_sleep.h>
-#endif
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->cpo_override = pbsp->cpo_override;
- popts->write_data_delay =
- pbsp->write_data_delay;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for %lu MT/s\n",
- ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
-
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x46;
-
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-}
-
-/* DDR model number: MT40A512M8HX-093E */
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 2147483648u,
- .capacity = 2147483648u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .bank_addr_bits = 0,
- .bank_group_bits = 2,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 938,
- .tckmax_ps = 1500,
- .caslat_x = 0x000DFA00,
- .taa_ps = 13500,
- .trcd_ps = 13500,
- .trp_ps = 13500,
- .tras_ps = 33000,
- .trc_ps = 46500,
- .trfc1_ps = 260000,
- .trfc2_ps = 160000,
- .trfc4_ps = 110000,
- .tfaw_ps = 21000,
- .trrds_ps = 3700,
- .trrdl_ps = 5300,
- .tccdl_ps = 5355,
- .refresh_rate_ps = 7800000,
- .dq_mapping[0] = 0x0,
- .dq_mapping[1] = 0x0,
- .dq_mapping[2] = 0x0,
- .dq_mapping[3] = 0x0,
- .dq_mapping[4] = 0x0,
- .dq_mapping[5] = 0x0,
- .dq_mapping[6] = 0x0,
- .dq_mapping[7] = 0x0,
- .dq_mapping[8] = 0x0,
- .dq_mapping[9] = 0x0,
- .dq_mapping[10] = 0x0,
- .dq_mapping[11] = 0x0,
- .dq_mapping[12] = 0x0,
- .dq_mapping[13] = 0x0,
- .dq_mapping[14] = 0x0,
- .dq_mapping[15] = 0x0,
- .dq_mapping[16] = 0x0,
- .dq_mapping[17] = 0x0,
- .dq_mapping_ors = 0,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- static const char dimm_model[] = "Fixed DDR on board";
-
- if (((controller_number == 0) && (dimm_number == 0)) ||
- ((controller_number == 1) && (dimm_number == 0))) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#else
-
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs,
- fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- ddr_size = (phys_size_t)2048 * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- return ddr_size;
-}
-#endif
-
-int fsl_initdram(void)
-{
- phys_size_t dram_size;
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
- puts("Initializing DDR....\n");
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fsl_ddr_sdram_size();
-#endif
-#else
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
- puts("Initialzing DDR using fixed setting\n");
- dram_size = fixed_sdram();
-#else
- gd->ram_size = 0x80000000;
-
- return 0;
-#endif
-#endif
- erratum_a008850_post();
-
-#ifdef CONFIG_FSL_DEEP_SLEEP
- fsl_dp_ddr_restore();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
deleted file mode 100644
index 85ed920ca6d..00000000000
--- a/board/freescale/ls1043ardb/ddr.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-
-extern void erratum_a008850_post(void);
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo_override;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
- {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
- {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
-#endif
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
- .cs[0].bnds = 0x0000007F,
- .cs[1].bnds = 0,
- .cs[2].bnds = 0,
- .cs[3].bnds = 0,
- .cs[0].config = 0x80040322,
- .cs[0].config_2 = 0,
- .cs[1].config = 0,
- .cs[1].config_2 = 0,
- .cs[2].config = 0,
- .cs[3].config = 0,
- .timing_cfg_3 = 0x010C1000,
- .timing_cfg_0 = 0x91550018,
- .timing_cfg_1 = 0xBBB48C42,
- .timing_cfg_2 = 0x0048C111,
- .ddr_sdram_cfg = 0xC50C0008,
- .ddr_sdram_cfg_2 = 0x00401100,
- .ddr_sdram_cfg_3 = 0,
- .ddr_sdram_mode = 0x03010210,
- .ddr_sdram_mode_2 = 0,
- .ddr_sdram_mode_3 = 0x00010210,
- .ddr_sdram_mode_4 = 0,
- .ddr_sdram_mode_5 = 0x00010210,
- .ddr_sdram_mode_6 = 0,
- .ddr_sdram_mode_7 = 0x00010210,
- .ddr_sdram_mode_8 = 0,
- .ddr_sdram_mode_9 = 0x00000500,
- .ddr_sdram_mode_10 = 0x04000000,
- .ddr_sdram_mode_11 = 0x00000400,
- .ddr_sdram_mode_12 = 0x04000000,
- .ddr_sdram_mode_13 = 0x00000400,
- .ddr_sdram_mode_14 = 0x04000000,
- .ddr_sdram_mode_15 = 0x00000400,
- .ddr_sdram_mode_16 = 0x04000000,
- .ddr_sdram_interval = 0x18600618,
- .ddr_data_init = 0xDEADBEEF,
- .ddr_sdram_clk_cntl = 0x03000000,
- .ddr_init_addr = 0,
- .ddr_init_ext_addr = 0,
- .timing_cfg_4 = 0x00000002,
- .timing_cfg_5 = 0x03401400,
- .timing_cfg_6 = 0,
- .timing_cfg_7 = 0x13300000,
- .timing_cfg_8 = 0x02115600,
- .timing_cfg_9 = 0,
- .ddr_zq_cntl = 0x8A090705,
- .ddr_wrlvl_cntl = 0x8675F607,
- .ddr_wrlvl_cntl_2 = 0x07090800,
- .ddr_wrlvl_cntl_3 = 0,
- .ddr_sr_cntr = 0,
- .ddr_sdram_rcw_1 = 0,
- .ddr_sdram_rcw_2 = 0,
- .ddr_cdr1 = 0x80040000,
- .ddr_cdr2 = 0x0000A181,
- .dq_map_0 = 0,
- .dq_map_1 = 0,
- .dq_map_2 = 0,
- .dq_map_3 = 0,
- .debug[28] = 0x00700046,
-
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {1550, 1650, &ddr_cfg_regs_1600},
- {0, 0, NULL}
-};
-
-#endif
-#endif
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
deleted file mode 100644
index a8d0c1109b4..00000000000
--- a/board/freescale/ls1043ardb/eth.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- int i;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- /* QSGMII on lane B, MAC 1/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
-
- switch (srds_s1) {
- case 0x1455:
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
- srds_s1);
- break;
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
- fm_info_set_mdio(i, dev);
-
- /* XFI on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(FM1_10GEC1, dev);
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
deleted file mode 100644
index f31f0ec515d..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <fdt_support.h>
-#include <hwconfig.h>
-#include <ahci.h>
-#include <mmc.h>
-#include <scsi.h>
-#include <fm_eth.h>
-#include <fsl_esdhc.h>
-#include <fsl_ifc.h>
-#include <fsl_sec.h>
-#include "cpld.h"
-#ifdef CONFIG_U_QE
-#include <fsl_qe.h>
-#endif
-#include <asm/arch/ppa.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- fsl_lsch2_early_init_f();
-
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-
-int checkboard(void)
-{
- static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
-#ifndef CONFIG_SD_BOOT
- u8 cfg_rcw_src1, cfg_rcw_src2;
- u16 cfg_rcw_src;
-#endif
- u8 sd1refclk_sel;
-
- printf("Board: LS1043ARDB, boot from ");
-
-#ifdef CONFIG_SD_BOOT
- puts("SD\n");
-#else
- cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
- cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
- cpld_rev_bit(&cfg_rcw_src1);
- cfg_rcw_src = cfg_rcw_src1;
- cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
-
- if (cfg_rcw_src == 0x25)
- printf("vBank %d\n", CPLD_READ(vbank));
- else if (cfg_rcw_src == 0x106)
- puts("NAND\n");
- else
- printf("Invalid setting of SW4\n");
-#endif
-
- printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
- CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
-
- puts("SERDES Reference Clocks:\n");
- sd1refclk_sel = CPLD_READ(sd1refclk_sel);
- printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
-
- return 0;
-}
-
-int board_init(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
- erratum_a010315();
-#endif
-
-#ifdef CONFIG_FSL_IFC
- init_final_memctl_regs();
-#endif
-
-#ifdef CONFIG_SECURE_BOOT
- /* In case of Secure Boot, the IBR configures the SMMU
- * to allow only Secure transactions.
- * SMMU must be reset in bypass mode.
- * Set the ClientPD bit and Clear the USFCFG Bit
- */
- u32 val;
- val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_SCR0, val);
- val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_NSCR0, val);
-#endif
-
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
-#ifdef CONFIG_U_QE
- u_qe_init();
-#endif
- /* invert AQR105 IRQ pins polarity */
- out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
-
- return 0;
-}
-
-int config_board_mux(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- u32 usb_pwrfault;
-
- if (hwconfig("qe-hdlc")) {
- out_be32(&scfg->rcwpmuxcr0,
- (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
- printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
- in_be32(&scfg->rcwpmuxcr0));
- } else {
-#ifdef CONFIG_HAS_FSL_XHCI_USB
- out_be32(&scfg->rcwpmuxcr0, 0x3333);
- out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
- usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB3_SHIFT) |
- (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB2_SHIFT) |
- (SCFG_USBPWRFAULT_SHARED <<
- SCFG_USBPWRFAULT_USB1_SHIFT);
- out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
-#endif
- }
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
- config_board_mux();
- return 0;
-}
-#endif
-
-void fdt_del_qe(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,qe")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- /* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
- fdt_fixup_memory_banks(blob, base, size, 2);
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- fdt_fixup_icid(blob);
-
- /*
- * qe-hdlc and usb multi-use the pins,
- * when set hwconfig to qe-hdlc, delete usb node.
- */
- if (hwconfig("qe-hdlc"))
-#ifdef CONFIG_HAS_FSL_XHCI_USB
- fdt_del_node_and_alias(blob, "usb1");
-#endif
- /*
- * qe just support qe-uart and qe-hdlc,
- * if qe-uart and qe-hdlc are not set in hwconfig,
- * delete qe node.
- */
- if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
- fdt_del_qe(blob);
-
- return 0;
-}
-
-u8 flash_read8(void *addr)
-{
- return __raw_readb(addr + 1);
-}
-
-void flash_write16(u16 val, void *addr)
-{
- u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
-
- __raw_writew(shftval, addr);
-}
-
-u16 flash_read16(void *addr)
-{
- u16 val = __raw_readw(addr);
-
- return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
-}
-
-#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
deleted file mode 100644
index f072274f474..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#Configure Scratch register
-09570600 00000000
-09570604 10000000
-#Alt base register
-09570158 00001000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009e
-0957041c 0000009e
-09570420 0000009e
-#flush PBI data
-096100c0 000fffff
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
deleted file mode 100644
index d87058b7efe..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# serdes protocol
-08100010 0a000000 00000000 00000000
-14550002 80004012 e0106000 c1002000
-00000000 00000000 00000000 00038800
-00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
deleted file mode 100644
index e2ee34b7dfc..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-08100010 0a000000 00000000 00000000
-14550002 80004012 60040000 c1002000
-00000000 00000000 00000000 00038800
-00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
deleted file mode 100644
index 41df0b9fbfa..00000000000
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
deleted file mode 100644
index 7541fad3db4..00000000000
--- a/configs/ls1043ardb_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_FSL_LS_PPA=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
deleted file mode 100644
index 2879f45d564..00000000000
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
deleted file mode 100644
index 5a23e3cfff5..00000000000
--- a/configs/ls1043ardb_nand_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
deleted file mode 100644
index 3c196944568..00000000000
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
deleted file mode 100644
index 144e48b885b..00000000000
--- a/configs/ls1043ardb_sdcard_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
deleted file mode 100644
index 54e6eef417b..00000000000
--- a/include/configs/ls1043ardb.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor
- */
-
-#ifndef __LS1043ARDB_H__
-#define __LS1043ARDB_H__
-
-#include "ls1043a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-/* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-#ifndef CONFIG_SPL
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#define CONFIG_FSL_DDR_BIST
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
-#endif
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
-#define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
-#endif
-
-/*
- * NOR Flash Definitions
- */
-#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
- CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TAVDS(0x0) | \
- FTIM0_NOR_TEAHC(0xc))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
- FTIM1_NOR_TRAD_NOR(0xb) | \
- FTIM1_NOR_TSEQRAD_NOR(0x9))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x8) | \
- FTIM2_NOR_TWP(0x10))
-#define CONFIG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
-
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
-
-/*
- * NAND Flash Definitions
- */
-#ifndef SPL_NO_IFC
-#define CONFIG_NAND_FSL_IFC
-#endif
-
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_NAND \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x7) | \
- FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0xe) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
- FTIM2_NAND_TREH(0xa) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
-#endif
-
-/*
- * CPLD
- */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
-
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
- CSPR_PORT_SIZE_8 | \
- CSPR_MSEL_GPCM | \
- CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
- CSOR_NOR_NOR_MODE_AVD_NOR | \
- CSOR_NOR_TRHZ_80)
-
-/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
- FTIM0_GPCM_TEADC(0xf) | \
- FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
- FTIM2_GPCM_TCH(0xf) | \
- FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
-
-/* IFC Timing Params */
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
-
-/* EEPROM */
-#ifndef SPL_NO_EEPROM
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
-
-/*
- * Environment
- */
-#ifndef SPL_NO_ENV
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#endif
-
-/* FMan */
-#ifndef SPL_NO_FMAN
-#define AQR105_IRQ_MASK 0x40000000
-
-#ifdef CONFIG_NET
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-
-#define RGMII_PHY1_ADDR 0x1
-#define RGMII_PHY2_ADDR 0x2
-
-#define QSGMII_PORT1_PHY_ADDR 0x4
-#define QSGMII_PORT2_PHY_ADDR 0x5
-#define QSGMII_PORT3_PHY_ADDR 0x6
-#define QSGMII_PORT4_PHY_ADDR 0x7
-
-#define FM1_10GEC1_PHY_ADDR 0x1
-
-#define CONFIG_ETHPRIME "FM1@DTSEC3"
-#endif
-#endif
-
-/* SATA */
-#ifndef SPL_NO_SATA
-#ifndef CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT2
-#endif
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 2
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#define SCSI_VEND_ID 0x1b4b
-#define SCSI_DEV_ID 0x9170
-#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __LS1043ARDB_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 06/93] arm: Remove ls1046ardb_sdcard_SECURE_BOOT board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (4 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 05/93] arm: Remove ls1043ardb_sdcard_SECURE_BOOT board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 07/93] arm: Remove colibri_imx6_nospl board Simon Glass
` (91 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/freescale/ls1046ardb/Kconfig | 31 ---
board/freescale/ls1046ardb/MAINTAINERS | 20 --
board/freescale/ls1046ardb/Makefile | 10 -
board/freescale/ls1046ardb/README | 76 ------
board/freescale/ls1046ardb/cpld.c | 166 -------------
board/freescale/ls1046ardb/cpld.h | 49 ----
board/freescale/ls1046ardb/ddr.c | 119 ----------
board/freescale/ls1046ardb/ddr.h | 62 -----
board/freescale/ls1046ardb/eth.c | 127 ----------
board/freescale/ls1046ardb/ls1046ardb.c | 182 ---------------
board/freescale/ls1046ardb/ls1046ardb_pbi.cfg | 22 --
.../ls1046ardb/ls1046ardb_qspi_pbi.cfg | 26 ---
.../ls1046ardb/ls1046ardb_rcw_emmc.cfg | 7 -
.../ls1046ardb/ls1046ardb_rcw_qspi.cfg | 7 -
.../ls1046ardb/ls1046ardb_rcw_sd.cfg | 7 -
configs/ls1046ardb_emmc_defconfig | 63 -----
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 49 ----
configs/ls1046ardb_qspi_defconfig | 49 ----
configs/ls1046ardb_qspi_spl_defconfig | 66 ------
.../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 64 -----
configs/ls1046ardb_sdcard_defconfig | 62 -----
include/configs/ls1046ardb.h | 220 ------------------
23 files changed, 1485 deletions(-)
delete mode 100644 board/freescale/ls1046ardb/Kconfig
delete mode 100644 board/freescale/ls1046ardb/MAINTAINERS
delete mode 100644 board/freescale/ls1046ardb/Makefile
delete mode 100644 board/freescale/ls1046ardb/README
delete mode 100644 board/freescale/ls1046ardb/cpld.c
delete mode 100644 board/freescale/ls1046ardb/cpld.h
delete mode 100644 board/freescale/ls1046ardb/ddr.c
delete mode 100644 board/freescale/ls1046ardb/ddr.h
delete mode 100644 board/freescale/ls1046ardb/eth.c
delete mode 100644 board/freescale/ls1046ardb/ls1046ardb.c
delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
delete mode 100644 configs/ls1046ardb_emmc_defconfig
delete mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1046ardb_qspi_defconfig
delete mode 100644 configs/ls1046ardb_qspi_spl_defconfig
delete mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1046ardb_sdcard_defconfig
delete mode 100644 include/configs/ls1046ardb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 08d6db1cadf..54ec8243084 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1513,7 +1513,6 @@ source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
-source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
deleted file mode 100644
index 4c31e0e8857..00000000000
--- a/board/freescale/ls1046ardb/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-
-if TARGET_LS1046ARDB
-
-config SYS_BOARD
- default "ls1046ardb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls1046ardb"
-
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
-source "board/freescale/common/Kconfig"
-endif
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
deleted file mode 100644
index aac649a9428..00000000000
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-LS1046A BOARD
-M: Mingkai Hu <mingkai.hu@nxp.com>
-S: Maintained
-F: board/freescale/ls1046ardb/
-F: board/freescale/ls1046ardb/ls1046ardb.c
-F: include/configs/ls1046ardb.h
-F: configs/ls1046ardb_qspi_defconfig
-F: configs/ls1046ardb_qspi_spl_defconfig
-F: configs/ls1046ardb_sdcard_defconfig
-F: configs/ls1046ardb_emmc_defconfig
-
-LS1046A_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/ls1046ardb_SECURE_BOOT_defconfig
-F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
-F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile
deleted file mode 100644
index 1c13ed6b6f0..00000000000
--- a/board/freescale/ls1046ardb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2016 Freescale Semiconductor
-
-obj-y += ddr.o
-obj-y += ls1046ardb.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_NET) += eth.o
-obj-y += cpld.o
-endif
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
deleted file mode 100644
index a38c9d48300..00000000000
--- a/board/freescale/ls1046ardb/README
+++ /dev/null
@@ -1,76 +0,0 @@
-Overview
---------
-The LS1046A Reference Design Board (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS1046A
-LayerScape Architecture processor. The LS1046ARDB provides SW development
-platform for the Freescale LS1046A processor series, with a complete
-debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
-
-LS1046A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
-SoC overview.
-
- LS1046ARDB board Overview
- -----------------------
- - SERDES1 Connections, 4 lanes supporting:
- - Lane0: XFI with x1 RJ45 connector
- - Lane1: XFI Cage
- - Lane2: SGMII.5
- - Lane3: SGMII.6
- - SERDES2 Connections, 4 lanes supporting:
- - Lane0: PCIe1 with miniPCIe slot
- - Lane1: PCIe2 with PCIe x2 slot
- - Lane2: PCIe3 with PCIe x4 slot
- - Lane3: SATA
- - DDR Controller
- - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
- -IFC/Local Bus
- - One 512 MB NAND flash with ECC support
- - CPLD connection
- - USB 3.0
- - one Type A port, one Micro-AB port
- - SDHC: connects directly to a full SD/MMC slot
- - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 4 I2C controllers
- - UART
- - Two 4-pin serial ports at up to 115.2 Kbit/s
- - Two DB9 D-Type connectors supporting one Serial port each
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-Start Address End Address Description Size
-0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
-0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
-0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
-0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
-0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
-0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
-0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
-0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
-0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
-0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
-0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
-0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
-
-QSPI flash map:
-Start Address End Address Description Size
-0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
-0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
-0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
-0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
-0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
- + bootscript 3MB
-0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
-0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
-0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB
-0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
-
-Booting Options
----------------
-a) QSPI boot
-b) SD boot
-c) eMMC boot
diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c
deleted file mode 100644
index a65751986a1..00000000000
--- a/board/freescale/ls1046ardb/cpld.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor
- *
- * Freescale LS1046ARDB board-specific CPLD controlling supports.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/* Set the boot bank to the alternate bank */
-void cpld_set_altbank(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_QSPI;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
- u8 reg7 = CPLD_READ(vbank);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
- CPLD_WRITE(vbank, reg7);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-/* Set the boot bank to the default bank */
-void cpld_set_defbank(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_QSPI;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(vbank, 0);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_set_sd(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_SD;
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(®5);
-
- CPLD_WRITE(soft_mux_on, 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_select_core_volt(bool en_0v9)
-{
- u8 reg17 = en_0v9;
-
- CPLD_WRITE(vdd_en, 1);
- CPLD_WRITE(vdd_sel, reg17);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
- printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
- printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
- printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
- printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
- printf("vbank = %x\n", CPLD_READ(vbank));
- printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
- printf("uart_sel = %x\n", CPLD_READ(uart_sel));
- printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
- printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel));
- printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel));
- printf("status_led = %x\n", CPLD_READ(status_led));
- printf("sd_emmc = %x\n", CPLD_READ(sd_emmc));
- printf("vdd_en = %x\n", CPLD_READ(vdd_en));
- printf("vdd_sel = %x\n", CPLD_READ(vdd_sel));
- putc('\n');
-}
-#endif
-
-void cpld_rev_bit(unsigned char *value)
-{
- u8 rev_val, val;
- int i;
-
- val = *value;
- rev_val = val & 1;
- for (i = 1; i <= 7; i++) {
- val >>= 1;
- rev_val <<= 1;
- rev_val |= val & 1;
- }
-
- *value = rev_val;
-}
-
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else if (strcmp(argv[2], "sd") == 0)
- cpld_set_sd();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else {
- rc = cmd_usage(cmdtp);
- }
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset: reset to default bank\n"
- "cpld reset altbank: reset to alternate bank\n"
- "cpld reset sd: reset to boot from SD card\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
-);
diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h
deleted file mode 100644
index e87044f5c0d..00000000000
--- a/board/freescale/ls1046ardb/cpld.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor
- */
-
-#ifndef __CPLD_H__
-#define __CPLD_H__
-
-/*
- * CPLD register set of LS1046ARDB board-specific.
- * CPLD Revision: V2.1
- */
-struct cpld_data {
- u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
- u8 pcba_ver; /* 0x2 - PCBA Revision Register */
- u8 system_rst; /* 0x3 - system reset register */
- u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
- u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */
- u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */
- u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */
- u8 sysclk_sel; /* 0x8 - System clock POR Register */
- u8 uart_sel; /* 0x9 - UART1 Connection Control Register */
- u8 sd1refclk_sel; /* 0xA - */
- u8 rgmii_1588_sel; /* 0xB - */
- u8 reg_1588_clk_sel; /* 0xC - */
- u8 status_led; /* 0xD - */
- u8 global_rst; /* 0xE - */
- u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */
- u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */
- u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */
-};
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-void cpld_rev_bit(unsigned char *value);
-void cpld_select_core_volt(bool en_0v9);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \
- cpld_write(offsetof(struct cpld_data, reg), value)
-
-/* CPLD on IFC */
-#define CPLD_SW_MUX_BANK_SEL 0x40
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_SEL_ALTBANK 0x04
-#define CPLD_CFG_RCW_SRC_QSPI 0x044
-#define CPLD_CFG_RCW_SRC_SD 0x040
-#endif
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
deleted file mode 100644
index 82b1b1d9eaa..00000000000
--- a/board/freescale/ls1046ardb/ddr.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-#ifdef CONFIG_FSL_DEEP_SLEEP
-#include <fsl_sleep.h>
-#endif
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimms[0];
- else
- pbsp = udimms[0];
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for %lu MT/s\n",
- ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
-
- popts->data_bus_width = 0; /* 64-bit data bus */
- popts->bstopre = 0; /* enable auto precharge */
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x61;
-}
-
-int fsl_initdram(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- gd->ram_size = fsl_ddr_sdram_size();
-
- return 0;
-#else
- puts("Initializing DDR....using SPD\n");
-
- dram_size = fsl_ddr_sdram();
-#endif
-
- erratum_a008850_post();
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
deleted file mode 100644
index 3b4d44d4658..00000000000
--- a/board/freescale/ls1046ardb/ddr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-
-void erratum_a008850_post(void);
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,},
- {2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
- {2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
- {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,},
- {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
- {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
- {}
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-
-#endif
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
deleted file mode 100644
index 7dbfcac307b..00000000000
--- a/board/freescale/ls1046ardb/eth.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- int i;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- /* Set the two on-board SGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
-
- /* Set the on-board AQ PHY address */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-
- switch (srds_s1) {
- case 0x1133:
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
- srds_s1);
- break;
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
- fm_info_set_mdio(i, dev);
-
- /* XFI on lane A, MAC 9 */
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(FM1_10GEC1, dev);
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_FMAN_ENET
-int fdt_update_ethernet_dt(void *blob)
-{
- u32 srds_s1;
- int i, prop;
- int offset, nodeoff;
- const char *path;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- /* Cycle through all aliases */
- for (prop = 0; ; prop++) {
- const char *name;
-
- /* FDT might have been edited, recompute the offset */
- offset = fdt_first_property_offset(blob,
- fdt_path_offset(blob,
- "/aliases")
- );
- /* Select property number 'prop' */
- for (i = 0; i < prop; i++)
- offset = fdt_next_property_offset(blob, offset);
-
- if (offset < 0)
- break;
-
- path = fdt_getprop_by_offset(blob, offset, &name, NULL);
- nodeoff = fdt_path_offset(blob, path);
-
- switch (srds_s1) {
- case 0x1133:
- if (!strcmp(name, "ethernet0"))
- fdt_status_disabled(blob, nodeoff);
-
- if (!strcmp(name, "ethernet1"))
- fdt_status_disabled(blob, nodeoff);
- break;
- default:
- printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
- __func__, srds_s1);
- break;
- }
- }
-
- return 0;
-}
-#endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
deleted file mode 100644
index 0a73fe859d9..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ppa.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <hwconfig.h>
-#include <ahci.h>
-#include <mmc.h>
-#include <scsi.h>
-#include <fm_eth.h>
-#include <fsl_csu.h>
-#include <fsl_esdhc.h>
-#include <power/mc34vr500_pmic.h>
-#include "cpld.h"
-#include <fsl_sec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- fsl_lsch2_early_init_f();
-
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int checkboard(void)
-{
- static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
- u8 cfg_rcw_src1, cfg_rcw_src2;
- u16 cfg_rcw_src;
- u8 sd1refclk_sel;
-
- puts("Board: LS1046ARDB, boot from ");
-
- cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
- cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
- cpld_rev_bit(&cfg_rcw_src1);
- cfg_rcw_src = cfg_rcw_src1;
- cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
-
- if (cfg_rcw_src == 0x44)
- printf("QSPI vBank %d\n", CPLD_READ(vbank));
- else if (cfg_rcw_src == 0x40)
- puts("SD\n");
- else
- puts("Invalid setting of SW5\n");
-
- printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
- CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
-
- puts("SERDES Reference Clocks:\n");
- sd1refclk_sel = CPLD_READ(sd1refclk_sel);
- printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
-
- return 0;
-}
-
-int board_init(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-#ifdef CONFIG_SECURE_BOOT
- /*
- * In case of Secure Boot, the IBR configures the SMMU
- * to allow only Secure transactions.
- * SMMU must be reset in bypass mode.
- * Set the ClientPD bit and Clear the USFCFG Bit
- */
- u32 val;
- val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_SCR0, val);
- val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_NSCR0, val);
-#endif
-
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
- /* invert AQR105 IRQ pins polarity */
- out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
-
- return 0;
-}
-
-int board_setup_core_volt(u32 vdd)
-{
- bool en_0v9;
-
- en_0v9 = (vdd == 900) ? true : false;
- cpld_select_core_volt(en_0v9);
-
- return 0;
-}
-
-int get_serdes_volt(void)
-{
- return mc34vr500_get_sw_volt(SW4);
-}
-
-int set_serdes_volt(int svdd)
-{
- return mc34vr500_set_sw_volt(SW4, svdd);
-}
-
-int power_init_board(void)
-{
- int ret;
-
- ret = power_mc34vr500_init(0);
- if (ret)
- return ret;
-
- setup_chip_volt();
-
- return 0;
-}
-
-void config_board_mux(void)
-{
-#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- u32 usb_pwrfault;
-
- /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
- out_be32(&scfg->rcwpmuxcr0, 0x3300);
- out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
- usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB3_SHIFT) |
- (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB2_SHIFT) |
- (SCFG_USBPWRFAULT_SHARED <<
- SCFG_USBPWRFAULT_USB1_SHIFT);
- out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
-#endif
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- config_board_mux();
- return 0;
-}
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- /* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
- fdt_fixup_memory_banks(blob, base, size, 2);
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- fdt_fixup_icid(blob);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
deleted file mode 100644
index 5478217524d..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-#Configure Scratch register
-09570600 00000000
-09570604 10000000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009e
-0957041c 0000009e
-09570420 0000009e
-#Serdes SATA
-09eb1300 80104e20
-09eb08dc 00502880
-#PEX gen3 link
-09570158 00000300
-89400890 01048000
-89500890 01048000
-89600890 01048000
-#Alt base register
-09570158 00001000
-#flush PBI data
-096100c0 000fffff
diff --git a/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
deleted file mode 100644
index 735d46c9f9b..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#QSPI clk
-0957015c 40100000
-#Configure Scratch register
-09570600 00000000
-09570604 10000000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009e
-0957041c 0000009e
-09570420 0000009e
-#Serdes SATA
-09eb1300 80104e20
-09eb08dc 00502880
-#PEX gen3 link
-09570158 00000300
-89400890 01048000
-89500890 01048000
-89600890 01048000
-#Alt base register
-09570158 00001000
-#flush PBI data
-096100c0 000fffff
-#Change endianness
-09550000 000f400c
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
deleted file mode 100644
index ccedf87e849..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c150012 0e000000 00000000 00000000
-11335559 40000012 60040000 c1000000
-00000000 00000000 00000000 00238800
-20124000 00003000 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
deleted file mode 100644
index 7b9be0ad3f8..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c150010 0e000000 00000000 00000000
-11335559 40005012 40025000 c1000000
-00000000 00000000 00000000 00238800
-20124000 00003101 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
deleted file mode 100644
index d3b152282f2..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c150012 0e000000 00000000 00000000
-11335559 40005012 60040000 c1000000
-00000000 00000000 00000000 00238800
-20124000 00003101 00000096 00000001
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
deleted file mode 100644
index f7a35c7e194..00000000000
--- a/configs/ls1046ardb_emmc_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index 80f52807e12..00000000000
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
deleted file mode 100644
index e780acc446b..00000000000
--- a/configs/ls1046ardb_qspi_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
deleted file mode 100644
index f7cd33d8af5..00000000000
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_OS_BASE=0x40980000
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_ENV_IS_NOWHERE=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_SPL_GZIP=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
deleted file mode 100644
index 24a08b6e013..00000000000
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
deleted file mode 100644
index 61da6ae517b..00000000000
--- a/configs/ls1046ardb_sdcard_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
deleted file mode 100644
index dcb58540461..00000000000
--- a/include/configs/ls1046ardb.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor
- */
-
-#ifndef __LS1046ARDB_H__
-#define __LS1046ARDB_H__
-
-#include "ls1046a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-/* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_DDR_SPD
-#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
-#ifndef CONFIG_SPL
-#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
-#ifdef CONFIG_EMMC_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
-#endif
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
-#define CONFIG_SYS_FSL_PBL_PBI \
- board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
-#define CONFIG_SYS_UBOOT_BASE 0x40100000
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
-#endif
-
-#ifndef SPL_NO_IFC
-/* IFC */
-#define CONFIG_FSL_IFC
-/*
- * NAND Flash Definitions
- */
-#define CONFIG_NAND_FSL_IFC
-#endif
-
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_NAND \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
- | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x7) | \
- FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0xe) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
- FTIM2_NAND_TREH(0xa) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/*
- * CPLD
- */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
-
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
- CSPR_PORT_SIZE_8 | \
- CSPR_MSEL_GPCM | \
- CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
-
-/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
- FTIM2_GPCM_TCH(0xf) | \
- FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
-
-/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define I2C_RETIMER_ADDR 0x18
-
-/* PMIC */
-#define CONFIG_POWER
-#ifdef CONFIG_POWER
-#define CONFIG_POWER_I2C
-#endif
-
-/*
- * Environment
- */
-#ifndef SPL_NO_ENV
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#if defined(CONFIG_SD_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
-#endif
-
-#define AQR105_IRQ_MASK 0x80000000
-/* FMan */
-#ifndef SPL_NO_FMAN
-
-#ifdef CONFIG_NET
-#define CONFIG_PHY_REALTEK
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define RGMII_PHY1_ADDR 0x1
-#define RGMII_PHY2_ADDR 0x2
-
-#define SGMII_PHY1_ADDR 0x3
-#define SGMII_PHY2_ADDR 0x4
-
-#define FM1_10GEC1_PHY_ADDR 0x0
-
-#define FDT_SEQ_MACADDR_FROM_ENV
-
-#define CONFIG_ETHPRIME "FM1 at DTSEC3"
-#endif
-
-#endif
-
-/* QSPI device */
-#ifndef SPL_NO_QSPI
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE (1 << 26)
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-#endif
-
-#ifndef SPL_NO_MISC
-#undef CONFIG_BOOTCOMMAND
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#endif
-#endif
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __LS1046ARDB_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 07/93] arm: Remove colibri_imx6_nospl board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (5 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 06/93] arm: Remove ls1046ardb_sdcard_SECURE_BOOT board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 21:32 ` Marek Vasut
2018-11-19 15:52 ` [U-Boot] [PATCH 08/93] arm: Remove guruplug board Simon Glass
` (90 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
.../toradex/colibri_imx6/800mhz_2x64mx16.cfg | 58 -
.../toradex/colibri_imx6/800mhz_4x64mx16.cfg | 58 -
board/toradex/colibri_imx6/Kconfig | 44 -
board/toradex/colibri_imx6/MAINTAINERS | 8 -
board/toradex/colibri_imx6/Makefile | 5 -
board/toradex/colibri_imx6/clocks.cfg | 41 -
board/toradex/colibri_imx6/colibri_imx6.c | 1121 -----------------
board/toradex/colibri_imx6/colibri_imx6.cfg | 37 -
board/toradex/colibri_imx6/ddr-setup.cfg | 97 --
board/toradex/colibri_imx6/do_fuse.c | 97 --
board/toradex/colibri_imx6/pf0100.c | 212 ----
board/toradex/colibri_imx6/pf0100.h | 52 -
board/toradex/colibri_imx6/pf0100_otp.inc | 188 ---
configs/colibri_imx6_defconfig | 73 --
configs/colibri_imx6_nospl_defconfig | 61 -
include/configs/colibri_imx6.h | 251 ----
17 files changed, 2404 deletions(-)
delete mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
delete mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
delete mode 100644 board/toradex/colibri_imx6/Kconfig
delete mode 100644 board/toradex/colibri_imx6/MAINTAINERS
delete mode 100644 board/toradex/colibri_imx6/Makefile
delete mode 100644 board/toradex/colibri_imx6/clocks.cfg
delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.c
delete mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg
delete mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg
delete mode 100644 board/toradex/colibri_imx6/do_fuse.c
delete mode 100644 board/toradex/colibri_imx6/pf0100.c
delete mode 100644 board/toradex/colibri_imx6/pf0100.h
delete mode 100644 board/toradex/colibri_imx6/pf0100_otp.inc
delete mode 100644 configs/colibri_imx6_defconfig
delete mode 100644 configs/colibri_imx6_nospl_defconfig
delete mode 100644 include/configs/colibri_imx6.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 06c25bae362..fb25bc81e11 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -563,7 +563,6 @@ source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/apalis_imx6/Kconfig"
-source "board/toradex/colibri_imx6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
source "board/k+p/kp_imx6q_tpc/Kconfig"
source "board/udoo/Kconfig"
diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
deleted file mode 100644
index c9407143d23..00000000000
--- a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-/* DDR3 DATA BUS SIZE: 64BIT */
-/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
-/* DDR3 DATA BUS SIZE: 32BIT */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
deleted file mode 100644
index c319d2a7296..00000000000
--- a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
-/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-/* DDR3 DATA BUS SIZE: 64BIT */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
-/* DDR3 DATA BUS SIZE: 32BIT */
-/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig
deleted file mode 100644
index d2ad1ce2a03..00000000000
--- a/board/toradex/colibri_imx6/Kconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-if TARGET_COLIBRI_IMX6
-
-config SYS_BOARD
- default "colibri_imx6"
-
-config SYS_CONFIG_NAME
- default "colibri_imx6"
-
-config SYS_CPU
- default "armv7"
-
-config SYS_SOC
- default "mx6"
-
-config SYS_VENDOR
- default "toradex"
-
-config TDX_CFG_BLOCK
- default y
-
-config TDX_HAVE_MMC
- default y
-
-config TDX_CFG_BLOCK_DEV
- default "0"
-
-config TDX_CFG_BLOCK_PART
- default "1"
-
-# Toradex config block in eMMC, at the end of 1st "boot sector"
-config TDX_CFG_BLOCK_OFFSET
- default "-512"
-
-config TDX_CMD_IMX_MFGR
- bool "Enable factory testing commands for Toradex iMX 6 modules"
- help
- This adds the commands
- pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
- If executed on already fused modules it doesn't change any fuse setting.
- default y
-
-source "board/toradex/common/Kconfig"
-
-endif
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
deleted file mode 100644
index 1cc7ef2e71b..00000000000
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-Colibri iMX6
-M: Max Krummenacher <max.krummenacher@toradex.com>
-W: http://developer.toradex.com/software/linux/linux-software
-S: Maintained
-F: board/toradex/colibri_imx6/
-F: include/configs/colibri_imx6.h
-F: configs/colibri_imx6_defconfig
-F: configs/colibri_imx6_nospl_defconfig
diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile
deleted file mode 100644
index c81bc2d741c..00000000000
--- a/board/toradex/colibri_imx6/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2012-2014 Toradex, Inc.
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := colibri_imx6.o do_fuse.o
-obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4fa380..00000000000
--- a/board/toradex/colibri_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
deleted file mode 100644
index 68c0c02a8ac..00000000000
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ /dev/null
@@ -1,1121 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
- * copied from nitrogen6x
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/bootm.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <asm/io.h>
-#include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <input.h>
-#include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <netdev.h>
-
-#include "../common/tdx-cfg-block.h"
-#ifdef CONFIG_TDX_CMD_IMX_MFGR
-#include "pf0100.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
-
-#define NO_PULLUP ( \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
-
-#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
-
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
- /* use the DDR controllers configured size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- (ulong)imx_ddr_size());
-
- return 0;
-}
-
-/* Colibri UARTA */
-iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Colibri I2C */
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-/* Colibri local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
- .gp = IMX_GPIO_NR(3, 16)
- }
-};
-
-/* Apalis MMC */
-iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-# define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
-};
-
-/* eMMC */
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
-iomux_v3_cfg_t const gpio_pads[] = {
- /* ADDRESS[17:18] [25] used as GPIO */
- MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* ADDRESS[19:24] used as GPIO */
- MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* DATA[16:29] [31] used as GPIO */
- MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* DQM[0:3] used as GPIO */
- MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* RDY used as GPIO */
- MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* ADDRESS[16] DATA[30] used as GPIO */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN),
- MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* CSI pins used as GPIO */
- MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN),
- MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* GPIO */
- MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* USBH_OC */
- MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* USBC_ID */
- MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* USBC_DET */
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
-};
-
-static void setup_iomux_gpio(void)
-{
- imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
-}
-
-iomux_v3_cfg_t const usb_pads[] = {
- /* USB_PE */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
-};
-
-/*
- * UARTs are used in DTE mode, switch the mode on all UARTs before
- * any pinmuxing connects a (DCE) output to a transceiver output.
- */
-#define UFCR 0x90 /* FIFO Control Register */
-#define UFCR_DCEDTE (1<<6) /* DCE=0 */
-
-static void setup_dtemode_uart(void)
-{
- setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
- setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
- setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
-}
-
-static void setup_iomux_uart(void)
-{
- setup_dtemode_uart();
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
-{
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- /* control OTG power */
- /* No special PE for USBC, always on when ID pin signals
- host mode */
- break;
- case 1:
- /* Control MXM USBH */
- /* Set MXM USBH power enable, '0' means on */
- gpio_direction_output(GPIO_USBH_EN, !on);
- mdelay(100);
- break;
- default:
- break;
- }
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-/* use the following sequence: eMMC, MMC */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
- {USDHC3_BASE_ADDR},
- {USDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = true; /* default: assume inserted */
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- gpio_direction_input(GPIO_MMC_CD);
- ret = !gpio_get_value(GPIO_MMC_CD);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- s32 status = 0;
- u32 index = 0;
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- usdhc_cfg[0].max_bus_width = 8;
- usdhc_cfg[1].max_bus_width = 4;
-
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- break;
- default:
- printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
- }
-
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- }
-
- return status;
-#else
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x2 SD2
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- default:
- puts("MMC boot device not available");
- }
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-#endif
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- /* provide the PHY clock from the i.MX 6 */
- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
- return ret;
- /* set gpr1[ENET_CLK_SEL] */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return 0;
- /* scan PHY 1..7 */
- phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
- if (!phydev) {
- free(bus);
- puts("no PHY found\n");
- return 0;
- }
- phy_reset(phydev);
- printf("using PHY at %d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- free(phydev);
- free(bus);
- }
-#endif
- return 0;
-}
-
-static iomux_v3_cfg_t const pwr_intb_pads[] = {
- /*
- * the bootrom sets the iomux to vselect, potentially connecting
- * two outputs. Set this back to GPIO
- */
- MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static iomux_v3_cfg_t const backlight_pads[] = {
- /* Backlight On */
- MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
- /* Backlight PWM, used as GPIO in U-Boot */
- MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
- MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
-};
-
-static iomux_v3_cfg_t const rgb_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
-};
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-static void enable_rgb(struct display_info_t const *dev)
-{
- imx_iomux_v3_setup_multiple_pads(
- rgb_pads,
- ARRAY_SIZE(rgb_pads));
- gpio_direction_output(RGB_BACKLIGHT_GP, 1);
- gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
-}
-
-static int detect_default(struct display_info_t const *dev)
-{
- (void) dev;
- return 1;
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = detect_default,
- .enable = enable_rgb,
- .mode = {
- .name = "vga-rgb",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 33000,
- .left_margin = 48,
- .right_margin = 16,
- .upper_margin = 31,
- .lower_margin = 11,
- .hsync_len = 96,
- .vsync_len = 2,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .enable = enable_rgb,
- .mode = {
- .name = "wvga-rgb",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 25000,
- .left_margin = 40,
- .right_margin = 88,
- .upper_margin = 33,
- .lower_margin = 10,
- .hsync_len = 128,
- .vsync_len = 2,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
- imx_setup_hdmi();
- /* Turn on LDB0,IPU,IPU DI0 clocks */
- reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* set LDB0, LDB1 clk select to 011/011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
- |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
- |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
- |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-
- /* backlight unconditionally on for now */
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
- /* use 0 for EDT 7", use 1 for LG fullHD panel */
- gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
- gpio_direction_output(RGB_BACKLIGHT_GP, 1);
-}
-#endif /* defined(CONFIG_VIDEO_IPUV3) */
-
-int board_early_init_f(void)
-{
- imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
- ARRAY_SIZE(pwr_intb_pads));
- setup_iomux_uart();
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
-
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
-#endif
-
-#ifdef CONFIG_TDX_CMD_IMX_MFGR
- (void) pmic_init();
-#endif
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
-
- setup_iomux_gpio();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#if defined(CONFIG_REVISION_TAG) && \
- defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
- char env_str[256];
- u32 rev;
-
- rev = get_board_rev();
- snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
- env_set("board_rev", env_str);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
- return 0;
-}
-#endif
-
-int checkboard(void)
-{
- char it[] = " IT";
- int minc, maxc;
-
- switch (get_cpu_temp_grade(&minc, &maxc)) {
- case TEMP_AUTOMOTIVE:
- case TEMP_INDUSTRIAL:
- break;
- case TEMP_EXTCOMMERCIAL:
- default:
- it[0] = 0;
- };
- printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
- is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
- (gd->ram_size == 0x20000000) ? "512" : "256", it);
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- return ft_common_board_setup(blob, bd);
-}
-#endif
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_LDO_BYPASS_CHECK
-/* TODO, use external pmic, for now always ldo_enable */
-void ldo_mode_set(int ldo_bypass)
-{
- return;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#include <linux/libfdt.h>
-#include "asm/arch/mx6dl-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-static int mx6s_dcd_table[] = {
-/* ddr-setup.cfg */
-
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-/* TODO: check what the RALAT field does */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-
-/* 800mhz_2x64mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x0002002D,
-MX6_MMDC_P0_MDCFG0, 0x2C305503,
-MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x00301023,
-MX6_MMDC_P0_MDOTC, 0x00333030,
-MX6_MMDC_P0_MDPDC, 0x0002556D,
-/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
-MX6_MMDC_P0_MDASP, 0x00000017,
-/* DDR3 DATA BUS SIZE: 64BIT */
-/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
-/* DDR3 DATA BUS SIZE: 32BIT */
-MX6_MMDC_P0_MDCTL, 0x82190000,
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* MX6_MMDC_P0_MDSCR, 0x04408032, */
-MX6_MMDC_P0_MDSCR, 0x04008032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00048031,
-MX6_MMDC_P0_MDSCR, 0x13208030,
-/* ZQ calibration */
-MX6_MMDC_P0_MDSCR, 0x04008040,
-
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00005800,
-
-MX6_MMDC_P0_MPODTCTRL, 0x00000000,
-MX6_MMDC_P1_MPODTCTRL, 0x00000000,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
-MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
-MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
-MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
-MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
-MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
-MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
-MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-static int mx6dl_dcd_table[] = {
-/* ddr-setup.cfg */
-
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-/* TODO: check what the RALAT field does */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-
-/* 800mhz_2x64mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x0002002D,
-MX6_MMDC_P0_MDCFG0, 0x2C305503,
-MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x00301023,
-MX6_MMDC_P0_MDOTC, 0x00333030,
-MX6_MMDC_P0_MDPDC, 0x0002556D,
-/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
-MX6_MMDC_P0_MDASP, 0x00000017,
-/* DDR3 DATA BUS SIZE: 64BIT */
-MX6_MMDC_P0_MDCTL, 0x821A0000,
-/* DDR3 DATA BUS SIZE: 32BIT */
-/* MX6_MMDC_P0_MDCTL, 0x82190000, */
-
-/* Write commands to DDR */
-/* Load Mode Registers */
-/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
-/* MX6_MMDC_P0_MDSCR, 0x04408032, */
-MX6_MMDC_P0_MDSCR, 0x04008032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00048031,
-MX6_MMDC_P0_MDSCR, 0x13208030,
-/* ZQ calibration */
-MX6_MMDC_P0_MDSCR, 0x04008040,
-
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00005800,
-
-MX6_MMDC_P0_MPODTCTRL, 0x00000000,
-MX6_MMDC_P1_MPODTCTRL, 0x00000000,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
-MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
-MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
-MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
-MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
-MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
-MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
-MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFFFF3, &ccm->CCGR2);
- writel(0x3FF0300F, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000F3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
- writel(0x000000FB, &ccm->ccosr);
-}
-
-static void ddr_init(int *table, int size)
-{
- int i;
-
- for (i = 0; i < size / 2 ; i++)
- writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
- int minc, maxc;
-
- switch (get_cpu_temp_grade(&minc, &maxc)) {
- case TEMP_COMMERCIAL:
- case TEMP_EXTCOMMERCIAL:
- if (is_cpu_type(MXC_CPU_MX6DL)) {
- puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
- ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
- } else {
- puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
- ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
- }
- break;
- case TEMP_INDUSTRIAL:
- case TEMP_AUTOMOTIVE:
- default:
- if (is_cpu_type(MXC_CPU_MX6DL)) {
- ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
- } else {
- puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
- ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
- }
- break;
- };
- udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* Make sure we use dte mode */
- setup_dtemode_uart();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-
-void reset_cpu(ulong addr)
-{
-}
-
-#endif
-
-static struct mxc_serial_platdata mxc_serial_plat = {
- .reg = (struct mxc_uart *)UART1_BASE,
- .use_dte = true,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
- .name = "serial_mxc",
- .platdata = &mxc_serial_plat,
-};
diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg
deleted file mode 100644
index 517c5eb1072..00000000000
--- a/board/toradex/colibri_imx6/colibri_imx6.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014 Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-
-#if CONFIG_DDR_MB == 256
-#include "800mhz_2x64mx16.cfg"
-#elif CONFIG_DDR_MB == 512
-#include "800mhz_4x64mx16.cfg"
-#else
-#error "unknown DDR size"
-#endif
-
-#include "clocks.cfg"
diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg
deleted file mode 100644
index a943fd228c4..00000000000
--- a/board/toradex/colibri_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
- * memory bus width: 64 bits x16/x32/x64
- * MX6DL ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 64 bits x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 32 bits x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-/* TODO: check what the RALAT field does */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c
deleted file mode 100644
index e6793e366a3..00000000000
--- a/board/toradex/colibri_imx6/do_fuse.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for i.MX OTP fusing during module production
-*/
-
-#include <common.h>
-#ifndef CONFIG_SPL_BUILD
-#include <console.h>
-#include <fuse.h>
-
-static int mfgr_fuse(void)
-{
- unsigned val, val6;
-
- fuse_sense(0, 5, &val);
- printf("Fuse 0, 5: %8x\n", val);
- fuse_sense(0, 6, &val6);
- printf("Fuse 0, 6: %8x\n", val6);
- fuse_sense(4, 3, &val);
- printf("Fuse 4, 3: %8x\n", val);
- fuse_sense(4, 2, &val);
- printf("Fuse 4, 2: %8x\n", val);
- if (val6 & 0x10) {
- puts("BT_FUSE_SEL already fused, will do nothing\n");
- return CMD_RET_FAILURE;
- }
- /* boot cfg */
- fuse_prog(0, 5, 0x00005072);
- /* BT_FUSE_SEL */
- fuse_prog(0, 6, 0x00000010);
- return CMD_RET_SUCCESS;
-}
-
-int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int ret;
- puts("Fusing...\n");
- ret = mfgr_fuse();
- if (ret == CMD_RET_SUCCESS)
- puts("done.\n");
- else
- puts("failed.\n");
- return ret;
-}
-
-int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned val;
- int ret;
- int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
-
- /* can be used in scripts for command availability check */
- if (argc >= 1 && !strcmp(argv[1], "-n"))
- return CMD_RET_SUCCESS;
-
- /* boot cfg */
- fuse_sense(0, 5, &val);
- printf("Fuse 0, 5: %8x\n", val);
- if (val & 0x10) {
- puts("Fast boot mode already fused, no need to fuse\n");
- return CMD_RET_SUCCESS;
- }
- if (!confirmed) {
- puts("Warning: Programming fuses is an irreversible operation!\n"
- " Updating to fast boot mode prevents easy\n"
- " downgrading to previous BSP versions.\n"
- "\nReally perform this fuse programming? <y/N>\n");
- if (!confirm_yesno())
- return CMD_RET_FAILURE;
- }
- puts("Fusing fast boot mode...\n");
- ret = fuse_prog(0, 5, 0x00005072);
- if (ret == CMD_RET_SUCCESS)
- puts("done.\n");
- else
- puts("failed.\n");
- return ret;
-}
-
-U_BOOT_CMD(
- mfgr_fuse, 1, 0, do_mfgr_fuse,
- "OTP fusing during module production",
- ""
-);
-
-U_BOOT_CMD(
- updt_fuse, 2, 0, do_updt_fuse,
- "OTP fusing during module update",
- "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
-);
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
deleted file mode 100644
index fa63865670f..00000000000
--- a/board/toradex/colibri_imx6/pf0100.c
+++ /dev/null
@@ -1,212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for Freescale PMIC PF0100
-*/
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-
-#include "pf0100_otp.inc"
-#include "pf0100.h"
-
-/* define for PMIC register dump */
-/*#define DEBUG */
-
-/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
-static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
- MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
-};
-
-unsigned pmic_init(void)
-{
- unsigned programmed = 0;
- uchar bus = 1;
- uchar devid, revid, val;
-
- puts("PMIC: ");
- if (!((0 == i2c_set_bus_num(bus)) &&
- (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
- puts("i2c bus failed\n");
- return 0;
- }
- /* get device ident */
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
- puts("i2c pmic devid read failed\n");
- return 0;
- }
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
- puts("i2c pmic revid read failed\n");
- return 0;
- }
- printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
-
-#ifdef DEBUG
- {
- unsigned i, j;
-
- for (i = 0; i < 16; i++)
- printf("\t%x", i);
- for (j = 0; j < 0x80; ) {
- printf("\n%2x", j);
- for (i = 0; i < 16; i++) {
- i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
- printf("\t%2x", val);
- }
- j += 0x10;
- }
- printf("\nEXT Page 1");
-
- val = PFUZE100_PAGE_REGISTER_PAGE1;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
- &val, 1)) {
- puts("i2c write failed\n");
- return 0;
- }
-
- for (j = 0x80; j < 0x100; ) {
- printf("\n%2x", j);
- for (i = 0; i < 16; i++) {
- i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
- printf("\t%2x", val);
- }
- j += 0x10;
- }
- printf("\nEXT Page 2");
-
- val = PFUZE100_PAGE_REGISTER_PAGE2;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
- &val, 1)) {
- puts("i2c write failed\n");
- return 0;
- }
-
- for (j = 0x80; j < 0x100; ) {
- printf("\n%2x", j);
- for (i = 0; i < 16; i++) {
- i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
- printf("\t%2x", val);
- }
- j += 0x10;
- }
- printf("\n");
- }
-#endif
- /* get device programmed state */
- val = PFUZE100_PAGE_REGISTER_PAGE1;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
- puts("i2c write failed\n");
- return 0;
- }
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
- puts("i2c fuse_por read failed\n");
- return 0;
- }
- if (val & PFUZE100_FUSE_POR_M)
- programmed++;
-
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
- puts("i2c fuse_por read failed\n");
- return programmed;
- }
- if (val & PFUZE100_FUSE_POR_M)
- programmed++;
-
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
- puts("i2c fuse_por read failed\n");
- return programmed;
- }
- if (val & PFUZE100_FUSE_POR_M)
- programmed++;
-
- switch (programmed) {
- case 0:
- printf("PMIC: not programmed\n");
- break;
- case 3:
- printf("PMIC: programmed\n");
- break;
- default:
- printf("PMIC: undefined programming state\n");
- break;
- }
-
- return programmed;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static int pf0100_prog(void)
-{
- unsigned char bus = 1;
- unsigned char val;
- unsigned int i;
-
- if (pmic_init() == 3) {
- puts("PMIC already programmed, exiting\n");
- return CMD_RET_FAILURE;
- }
- /* set up gpio to manipulate vprog, initially off */
- imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
- ARRAY_SIZE(pmic_prog_pads));
- gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
-
- if (!((0 == i2c_set_bus_num(bus)) &&
- (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
- puts("i2c bus failed\n");
- return CMD_RET_FAILURE;
- }
-
- for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
- switch (pmic_otp_prog[i].cmd) {
- case pmic_i2c:
- val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
- if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
- 1, &val, 1)) {
- printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
- pmic_otp_prog[i].reg, val);
- return CMD_RET_FAILURE;
- }
- break;
- case pmic_delay:
- udelay(pmic_otp_prog[i].value * 1000);
- break;
- case pmic_vpgm:
- gpio_direction_output(PMIC_PROG_VOLTAGE,
- pmic_otp_prog[i].value);
- break;
- case pmic_pwr:
- /* TODO */
- break;
- }
- }
- return CMD_RET_SUCCESS;
-}
-
-static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int ret;
- puts("Programming PMIC OTP...");
- ret = pf0100_prog();
- if (ret == CMD_RET_SUCCESS)
- puts("done.\n");
- else
- puts("failed.\n");
- return ret;
-}
-
-U_BOOT_CMD(
- pf0100_otp_prog, 1, 0, do_pf0100_prog,
- "Program the OTP fuses on the PMIC PF0100",
- ""
-);
-#endif
diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h
deleted file mode 100644
index c0efb79bbc9..00000000000
--- a/board/toradex/colibri_imx6/pf0100.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for Freescale PMIC PF0100
-*/
-
-#ifndef PF0100_H_
-#define PF0100_H_
-
-/* 7-bit I2C bus slave address */
-#define PFUZE100_I2C_ADDR (0x08)
-/* Register Addresses */
-#define PFUZE100_DEVICEID (0x0)
-#define PFUZE100_REVID (0x3)
-#define PFUZE100_SW1AMODE (0x23)
-#define PFUZE100_SW1ACON 36
-#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
-#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
-#define PFUZE100_SW1CCON 49
-#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
-#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
-#define PFUZE100_SW1AVOL 32
-#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
-#define PFUZE100_SW1CVOL 46
-#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
-#define PFUZE100_VGEN1CTL (0x6c)
-#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
-#define PFUZE100_SWBSTCTL (0x66)
-/* Always ON, Auto Switching Mode, 5.0V */
-#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
-
-/* chooses the extended page (registers 0x80..0xff) */
-#define PFUZE100_PAGE_REGISTER 0x7f
-#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
-#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
-#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
-
-/* extended page 1 */
-#define PFUZE100_FUSE_POR1 0xe4
-#define PFUZE100_FUSE_POR2 0xe5
-#define PFUZE100_FUSE_POR3 0xe6
-#define PFUZE100_FUSE_POR_M (0x1 << 1)
-
-
-/* output some informational messages, return the number FUSE_POR=1 */
-/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
-unsigned pmic_init(void);
-
-#endif /* PF0100_H_ */
diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc
deleted file mode 100644
index ce29b95ae2a..00000000000
--- a/board/toradex/colibri_imx6/pf0100_otp.inc
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-// Register Output for PF0100 programmer
-// Customer: Toradex AG
-// Program: Colibri iMX6
-// Sample marking:
-// Date: 24.07.2015
-// Time: 10:52:58
-// Generated from Spreadsheet Revision: P1.8
-
-/* sed commands to get from programmer script to struct */
-/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
- sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
- sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
-
-enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
-struct pmic_otp_prog_t{
- unsigned char cmd;
- unsigned char reg;
- unsigned short value;
-};
-
-struct pmic_otp_prog_t pmic_otp_prog[] = {
-{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
-{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
-{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
-{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
-{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
-{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
-{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
-{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
-{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
-{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
-{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
-{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
-{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
-{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
-{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
-{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
-{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
-{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123
-{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
-{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
-{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
-{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
-{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
-{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
-{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
-{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
-{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
-{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
-{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
-{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
-
-#if 0 /* TBB mode */
-{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
-{pmic_delay, 0, 10},
-#else
-// Write OTP
-{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
-{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
-{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
-{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
-{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
-{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
-{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
-{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
-//VPGM:DOWN:n
-//VPGM:UP:n
-{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
-//-----------------------------------------------------------------------------------
-// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
-//-----------------------------------------------------------------------------------
-// BANK 1
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 2
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 3
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 4
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 5
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 6
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 7
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 8
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 9
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 10
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
-{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
-{pmic_i2c, 0xD0, 0x00}, // Clear
-{pmic_i2c, 0xD1, 0x00}, // Clear
-{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
-{pmic_delay, 0, 500},
-{pmic_pwr, 0, 1},
-#endif
-};
\ No newline at end of file
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
deleted file mode 100644
index d86c0872b4f..00000000000
--- a/configs/colibri_imx6_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_COLIBRI_IMX6=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Colibri iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig
deleted file mode 100644
index 2ed42b54cc2..00000000000
--- a/configs/colibri_imx6_nospl_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_COLIBRI_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Colibri iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
deleted file mode 100644
index 7eb87cada6f..00000000000
--- a/include/configs/colibri_imx6.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2015 Toradex, Inc.
- *
- * Configuration settings for the Toradex Colibri iMX6
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#undef CONFIG_DISPLAY_BOARDINFO
-
-#include <asm/arch/imx-regs.h>
-#include <asm/mach-imx/gpio.h>
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
-/* MMC Configs */
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-/* Network */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 16352
-#define CONFIG_TFTP_TSIZE
-
-/* USB Configs */
-/* Host */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-/* Client */
-#define CONFIG_USBD_HS
-
-#define CONFIG_USB_GADGET_MASS_STORAGE
-/* USB DFU */
-#define CONFIG_DFU_MMC
-
-/* Miscellaneous commands */
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition */
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FLASH
-
-#undef CONFIG_IPADDR
-#define CONFIG_IPADDR 192.168.10.2
-#define CONFIG_NETMASK 255.255.255.0
-#undef CONFIG_SERVERIP
-#define CONFIG_SERVERIP 192.168.10.1
-
-#define CONFIG_LOADADDR 0x12000000
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
-#else
-#define CONFIG_DRIVE_MMC
-#endif
-
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC
-
-#define DFU_ALT_EMMC_INFO \
- "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "uImage fat 0 1;" \
- "imx6q-colibri-eval-v3.dtb fat 0 1;" \
- "imx6q-colibri-cam-eval-v3.dtb fat 0 1"
-
-#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
- "rootwait\0" \
- "emmcboot=run setup; " \
- "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
- "${vidargs}; echo Booting from internal eMMC chip...; " \
- "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} ${dtbparam}\0" \
- "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0x10000000\0" \
- "fdt_addr_r=0x12000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x11000000\0" \
- "ramdisk_addr_r=0x12100000\0"
-
-#define NFS_BOOTCMD \
- "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
- "nfsboot=run setup; " \
- "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
- "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
- "run nfsdtbload; dhcp ${kernel_addr_r} " \
- "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
- "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
- "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define SD_BOOTCMD \
- "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
- "rootwait\0" \
- "sdboot=run setup; " \
- "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
- "${vidargs}; echo Booting from SD card; " \
- "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} ${dtbparam}\0" \
- "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define USB_BOOTCMD \
- "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
- "rootwait\0" \
- "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
- "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} ${dtbparam}\0" \
- "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
- "run nfsboot ; echo ; echo nfsboot failed ; " \
- "usb start ;" \
- "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
- "boot_file=uImage\0" \
- "console=ttymxc0\0" \
- "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
- "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
- EMMC_BOOTCMD \
- "fdt_file=" FDT_FILE "\0" \
- "fdt_fixup=;\0" \
- MEM_LAYOUT_ENV_SETTINGS \
- NFS_BOOTCMD \
- SD_BOOTCMD \
- "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
- "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
- "flash_eth.img && source ${loadaddr}\0" \
- "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
- "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
- "source ${loadaddr}\0" \
- "setup=setenv setupargs fec_mac=${ethaddr} " \
- "consoleblank=0 no_console_suspend=1 console=tty1 " \
- "console=${console},${baudrate}n8\0 " \
- "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
- "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
- "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
- "source ${loadaddr}\0" \
- "splashpos=m,m\0" \
- "vidargs=video=mxcfb0:dev=lcd,640x480M at 60,if=RGB666 " \
- "video=mxcfb1:off fbmem=8M\0 "
-
-/* Miscellaneous configurable options */
-#undef CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_CBSIZE 1024
-#undef CONFIG_SYS_MAXARGS
-#define CONFIG_SYS_MAXARGS 48
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
- CONFIG_TDX_CFG_BLOCK_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 1
-#endif
-
-#define CONFIG_OF_SYSTEM_SETUP
-
-#define CONFIG_CMD_TIME
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 08/93] arm: Remove guruplug board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (6 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 07/93] arm: Remove colibri_imx6_nospl board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 09/93] arm: Remove sniper board Simon Glass
` (89 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/Marvell/guruplug/Kconfig | 12 ---
board/Marvell/guruplug/MAINTAINERS | 6 --
board/Marvell/guruplug/Makefile | 7 --
board/Marvell/guruplug/guruplug.c | 138 --------------------------
board/Marvell/guruplug/guruplug.h | 22 -----
board/Marvell/guruplug/kwbimage.cfg | 144 ----------------------------
configs/guruplug_defconfig | 43 ---------
include/configs/guruplug.h | 82 ----------------
9 files changed, 455 deletions(-)
delete mode 100644 board/Marvell/guruplug/Kconfig
delete mode 100644 board/Marvell/guruplug/MAINTAINERS
delete mode 100644 board/Marvell/guruplug/Makefile
delete mode 100644 board/Marvell/guruplug/guruplug.c
delete mode 100644 board/Marvell/guruplug/guruplug.h
delete mode 100644 board/Marvell/guruplug/kwbimage.cfg
delete mode 100644 configs/guruplug_defconfig
delete mode 100644 include/configs/guruplug.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 3b860c4f55f..00ed62591ea 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -73,7 +73,6 @@ config SYS_SOC
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Synology/ds109/Kconfig"
-source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
diff --git a/board/Marvell/guruplug/Kconfig b/board/Marvell/guruplug/Kconfig
deleted file mode 100644
index 529e6e3b4ba..00000000000
--- a/board/Marvell/guruplug/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_GURUPLUG
-
-config SYS_BOARD
- default "guruplug"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "guruplug"
-
-endif
diff --git a/board/Marvell/guruplug/MAINTAINERS b/board/Marvell/guruplug/MAINTAINERS
deleted file mode 100644
index b5d07348316..00000000000
--- a/board/Marvell/guruplug/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GURUPLUG BOARD
-M: Siddarth Gore <gores@marvell.com>
-S: Maintained
-F: board/Marvell/guruplug/
-F: include/configs/guruplug.h
-F: configs/guruplug_defconfig
diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile
deleted file mode 100644
index b0dfc0cd6d9..00000000000
--- a/board/Marvell/guruplug/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-
-obj-y := guruplug.o
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
deleted file mode 100644
index 466f85eb081..00000000000
--- a/board/Marvell/guruplug/guruplug.c
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "guruplug.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
- GURUPLUG_OE_VAL_HIGH,
- GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* GPIO_RST */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GE1_8,
- MPP29_GE1_9,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GE1_14,
- MPP35_GE1_15,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_TDM_SPI_SCK,
- MPP41_TDM_SPI_MISO,
- MPP42_TDM_SPI_MOSI,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO, /* M_RLED */
- MPP47_GPIO, /* M_GLED */
- MPP48_GPIO, /* B_RLED */
- MPP49_GPIO, /* B_GLED */
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void mv_phy_88e1121_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
- reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
- miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1121 Initialized on %s\n", name);
-}
-
-void reset_phy(void)
-{
- /* configure and initialize both PHY's */
- mv_phy_88e1121_init("egiga0");
- mv_phy_88e1121_init("egiga1");
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/guruplug/guruplug.h b/board/Marvell/guruplug/guruplug.h
deleted file mode 100644
index a7023668132..00000000000
--- a/board/Marvell/guruplug/guruplug.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#ifndef __GURUPLUG_H
-#define __GURUPLUG_H
-
-#define GURUPLUG_OE_LOW (~(0))
-#define GURUPLUG_OE_HIGH (~(0))
-#define GURUPLUG_OE_VAL_LOW 0
-#define GURUPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
-
-/* PHY related */
-#define MV88E1121_MAC_CTRL2_REG 21
-#define MV88E1121_PGADR_REG 22
-#define MV88E1121_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1121_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __GURUPLUG_H */
diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg
deleted file mode 100644
index 8a0d752c91c..00000000000
--- a/board/Marvell/guruplug/kwbimage.cfg
+++ /dev/null
@@ -1,144 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0/1 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b9b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 01, Cs0width=x8
-# bit3-2: 10, Cs0size=1Gb
-# bit5-4: 01, Cs1width=x8
-# bit7-6: 10, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
deleted file mode 100644
index 9998e48ab9c..00000000000
--- a/configs/guruplug_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_GURUPLUG=y
-CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),- at 1M(root)"
-CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
deleted file mode 100644
index 739ab320f63..00000000000
--- a/include/configs/guruplug.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009-2014
- * Gerald Kerma <dreagle@doukki.net>
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#ifndef _CONFIG_GURUPLUG_H
-#define _CONFIG_GURUPLUG_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-
-/*
- * Standard filesystems
- */
-#define CONFIG_BZIP2
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-plug-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
- "ubi part root; " \
- "ubifsmount ubi:rootfs; " \
- "ubifsload 0x800000 ${kernel}; " \
- "ubifsload 0x700000 ${fdt}; " \
- "ubifsumount; " \
- "fdt addr 0x700000; fdt resize; fdt chosen; " \
- "bootz 0x800000 - 0x700000"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=console=ttyS0,115200\0" \
- "mtdids=nand0=orion_nand\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "kernel=/boot/zImage\0" \
- "fdt=/boot/guruplug-server-plus.dtb\0" \
- "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#endif /* _CONFIG_GURUPLUG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 09/93] arm: Remove sniper board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (7 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 08/93] arm: Remove guruplug board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 10/93] arm: Remove omap3_zoom1 board Simon Glass
` (88 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/lg/sniper/Kconfig | 12 -
board/lg/sniper/MAINTAINERS | 6 -
board/lg/sniper/Makefile | 7 -
board/lg/sniper/sniper.c | 189 ----------------
board/lg/sniper/sniper.h | 364 ------------------------------
configs/sniper_defconfig | 40 ----
include/configs/sniper.h | 154 -------------
8 files changed, 773 deletions(-)
delete mode 100644 board/lg/sniper/Kconfig
delete mode 100644 board/lg/sniper/MAINTAINERS
delete mode 100644 board/lg/sniper/Makefile
delete mode 100644 board/lg/sniper/sniper.c
delete mode 100644 board/lg/sniper/sniper.h
delete mode 100644 configs/sniper_defconfig
delete mode 100644 include/configs/sniper.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index e0d02fb4e59..b5f6061a17a 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -213,6 +213,5 @@ source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
source "board/quipos/cairo/Kconfig"
-source "board/lg/sniper/Kconfig"
endif
diff --git a/board/lg/sniper/Kconfig b/board/lg/sniper/Kconfig
deleted file mode 100644
index 3f18d2120db..00000000000
--- a/board/lg/sniper/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SNIPER
-
-config SYS_BOARD
- default "sniper"
-
-config SYS_VENDOR
- default "lg"
-
-config SYS_CONFIG_NAME
- default "sniper"
-
-endif
diff --git a/board/lg/sniper/MAINTAINERS b/board/lg/sniper/MAINTAINERS
deleted file mode 100644
index 7226b092cdd..00000000000
--- a/board/lg/sniper/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SNIPER BOARD
-M: Paul Kocialkowski <contact@paulk.fr>
-S: Maintained
-F: board/lg/sniper/
-F: include/configs/sniper.h
-F: configs/sniper_defconfig
diff --git a/board/lg/sniper/Makefile b/board/lg/sniper/Makefile
deleted file mode 100644
index 549dcca4e50..00000000000
--- a/board/lg/sniper/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# LG Optimus Black codename sniper board
-#
-# Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
-
-obj-y := sniper.o
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
deleted file mode 100644
index a7de4c21674..00000000000
--- a/board/lg/sniper/sniper.c
+++ /dev/null
@@ -1,189 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * LG Optimus Black codename sniper board
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- */
-
-#include <config.h>
-#include <common.h>
-#include <dm.h>
-#include <linux/ctype.h>
-#include <linux/usb/musb.h>
-#include <asm/omap_musb.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include "sniper.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
- .mtype = DDR_STACKED,
- .board_string = "sniper",
- .nand_string = "MMC"
-};
-
-static const struct ns16550_platdata serial_omap_platdata = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(sniper_serial) = {
- .name = "ns16550_serial",
- .platdata = &serial_omap_platdata
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_platform_data = {
- .mode = MUSB_PERIPHERAL,
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-
-void set_muxconf_regs(void)
-{
- MUX_SNIPER();
-}
-
-#ifdef CONFIG_SPL_BUILD
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- timings->mr = MICRON_V_MR_165;
-}
-#endif
-
-int board_init(void)
-{
- /* GPMC init */
- gpmc_init();
-
- /* MACH number */
- gd->bd->bi_arch_number = 3000;
-
- /* ATAGs location */
- gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- unsigned char keypad_matrix[64] = { 0 };
- char reboot_mode[2] = { 0 };
- unsigned char keys[3];
- unsigned char data = 0;
- int rc;
-
- /* Power button reset init */
-
- twl4030_power_reset_init();
-
- /* Keypad */
-
- twl4030_keypad_scan((unsigned char *)&keypad_matrix);
-
- keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0);
- keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1);
- keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2);
-
- /* Reboot mode */
-
- rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
-
- if (keys[0])
- reboot_mode[0] = 'r';
- else if (keys[1])
- reboot_mode[0] = 'b';
-
- if (rc < 0 || reboot_mode[0] == 'o') {
- /*
- * When not rebooting, valid power on reasons are either the
- * power button, charger plug or USB plug.
- */
-
- data |= twl4030_input_power_button();
- data |= twl4030_input_charger();
- data |= twl4030_input_usb();
-
- if (!data)
- twl4030_power_off();
- }
-
- if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
- if (!env_get("reboot-mode"))
- env_set("reboot-mode", (char *)reboot_mode);
- }
-
- omap_reboot_mode_clear();
-
- /* Serial number */
-
- omap_die_id_serial();
-
- /* MUSB */
-
- musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
-
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- /* Sold devices are expected to be at least revision F. */
- return 6;
-}
-
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- omap_die_id_get_board_serial(serialnr);
-}
-
-void reset_misc(void)
-{
- char reboot_mode[2] = { 0 };
-
- /*
- * Valid resets must contain the reboot mode magic, but we must not
- * override it when set previously (e.g. reboot to bootloader).
- */
-
- omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
- omap_reboot_mode_store(reboot_mode);
-}
-
-int fastboot_set_reboot_flag(void)
-{
- return omap_reboot_mode_store("b");
-}
-
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(1, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(1);
-}
diff --git a/board/lg/sniper/sniper.h b/board/lg/sniper/sniper.h
deleted file mode 100644
index db71ad86d88..00000000000
--- a/board/lg/sniper/sniper.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LG Optimus Black codename sniper board
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- */
-
-#ifndef _SNIPER_H_
-#define _SNIPER_H_
-
-#include <asm/arch/mux.h>
-
-#define MUX_SNIPER() \
- /* SDRC */ \
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* sdrc_d6 */\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* sdrc_d7 */\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* sdrc_d8 */\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* sdrc_d9 */\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* sdrc_d10 */\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* sdrc_d11 */\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* sdrc_d12 */\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* sdrc_d13 */\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* sdrc_d14 */\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* sdrc_d15 */\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* sdrc_d16 */\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* sdrc_d17 */\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* sdrc_d18 */\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* sdrc_d19 */\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* sdrc_d20 */\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* sdrc_d21 */\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* sdrc_d22 */\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* sdrc_d23 */\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* sdrc_d24 */\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* sdrc_d25 */\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* sdrc_d26 */\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* sdrc_d27 */\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* sdrc_d28 */\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* sdrc_d29 */\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* sdrc_d30 */\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* sdrc_d31 */\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* sdrc_clk */\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* sdrc_dqs0 */\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* sdrc_dqs1 */\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* sdrc_dqs2 */\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* sdrc_dqs3 */ \
- /* GPMC */ \
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \
- MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\
- MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\
- MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\
- MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\
- MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\
- MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* gpmc_d0 */ \
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* gpmc_d1 */ \
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* gpmc_d2 */ \
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* gpmc_d3 */ \
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* gpmc_d4 */ \
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* gpmc_d5 */ \
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* gpmc_d6 */ \
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* gpmc_d7 */ \
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* gpmc_d8 */ \
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* gpmc_d9 */ \
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* gpmc_d10 */ \
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* gpmc_d11 */ \
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* gpmc_d12 */ \
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* gpmc_d13 */ \
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* gpmc_d14 */ \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* gpio_52 */ \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* gpio_53 */ \
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* gpio_54 */ \
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* gpio_55 */ \
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* gpio_56 */ \
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* gpio_57 */ \
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* gpio_58 */ \
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* gpio_60 */ \
- MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* gpio_61 */ \
- MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* gpio_62 */ \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* gpio_63 */ \
- MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* gpio_64 */ \
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* gpio_65 */ \
- /* DSS */ \
- MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \
- MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* gpio_87 */ \
- MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* safe_mode */ \
- /* CAM */ \
- MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* cam_hs */ \
- MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* cam_vs */ \
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* cam_xclka */ \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* cam_pclk */ \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* gpio_98 */ \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* csi2_dx2 */ \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* csi2_dy2 */ \
- MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* gpio_101 */ \
- MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* cam_d4 */ \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* cam_d5 */ \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* cam_d6 */ \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* cam_d7 */ \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* cam_d8 */ \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* cam_d9 */ \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* cam_d10 */ \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* cam_d11 */ \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* cam_xclkb */ \
- MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* gpio_167 */ \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- /* CSI2 */ \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* csi2_dx0 */ \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* csi2_dy0 */ \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* csi2_dx1 */ \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* csi2_dy1 */ \
- /* MCBSP2 */ \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* mcbsp2_fsx */ \
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp2_clkx */ \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* mcbsp2_dr */ \
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* mcbsp2_dx */ \
- /* MMC1 */ \
- MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* mmc1_clk */ \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* mmc1_cmd */ \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* mmc1_dat0 */ \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* mmc1_dat1 */ \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* mmc1_dat2 */ \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* mmc1_dat3 */ \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- /* MMC2 */ \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* mmc2_clk */ \
- MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* mmc2_cmd */ \
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* mmc2_dat0 */ \
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* mmc2_dat1 */ \
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* mmc2_dat2 */ \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* mmc2_dat3 */ \
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* mmc2_dat4 */ \
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* mmc2_dat5 */ \
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* mmc2_dat6 */ \
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* mmc2_dat7 */ \
- /* MCBSP3 */ \
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* mcbsp3_dx */ \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* mcbsp3_dr */ \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp3_clkx */ \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* mcbsp3_fsx */ \
- /* UART2 */ \
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* uart2_cts */ \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* uart2_rts */ \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* uart2_tx */ \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* uart2_rx */ \
- /* UART1 */ \
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* uart1_tx */ \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* uart1_rts */ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* uart1_cts */ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* uart1_rx */ \
- /* MCBSP4 */ \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_152 */ \
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* gpio_153 */ \
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* gpio_154 */ \
- MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* gpio_155 */ \
- /* MCBSP1 */ \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* mcbsp1_clkr */ \
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* mcbsp1_fsr */ \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* mcbsp1_dx */ \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* mcbsp1_dr */ \
- MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* gpio_161 */ \
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_162 */ \
- /* UART3 */ \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* gpio_163 */ \
- MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* uart3_rx_irrx */ \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* uart3_tx_irtx */ \
- /* HSUSB0 */ \
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* hsusb0_clk */\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* hsusb0_stp */\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* hsusb0_dir */\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* hsusb0_nxt */\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* hsusb0_data0 */\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* hsusb0_data1 */\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* hsusb0_data2 */\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* hsusb0_data3 */\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* hsusb0_data4 */\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* hsusb0_data5 */\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* hsusb0_data6 */\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* hsusb0_data7 */ \
- /* I2C1 */ \
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* i2c1_scl */ \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* i2c1_sda */ \
- /* I2C2 */ \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* i2c2_scl */ \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* i2c2_sda */ \
- /* I2C3 */ \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* i2c3_scl */ \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* i2c3_sda */ \
- /* I2C4 */ \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* i2c4_scl */ \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* i2c4_sda */ \
- /* HDQ */ \
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* gpio_170 */ \
- /* MCSPI1 */ \
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* gpio_175 */ \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* gpio_176 */ \
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* gpio_177 */ \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* mcspi2_clk */ \
- MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* mcspi2_simo */ \
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* mcspi2_somi */ \
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* gpio_181 */ \
- MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* gpio_182 */ \
- /* SYS */ \
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* sys_32k */ \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* sys_clkreq */ \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* sys_nirq */ \
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* safe_mode */ \
- MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* sys_off_mode */ \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* gpio_10 */ \
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* safe_mode */ \
- /* JTAG */ \
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* jtag_ntrst */ \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* jtag_tck */ \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* jtag_tms */ \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* jtag_tdi */ \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* jtag_emu0 */ \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* jtag_emu1 */ \
- /* ETK */ \
- MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_clk */ \
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* sdmmc3_cmd */ \
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* gpio_14 */ \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* gpio_15 */ \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* gpio_16 */ \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat3 */ \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat0 */ \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat1 */ \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat2 */ \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* gpio_21 */ \
- MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* gpio_22 */ \
- MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* gpio_23 */ \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* gpio_24 */ \
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* gpio_25 */ \
- MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* gpio_26 */ \
- MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* gpio_27 */ \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* gpio_28 */ \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* gpio_29 */ \
- /* D2D */ \
- MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* d2d_mcad0 */ \
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* d2d_mcad1 */ \
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* d2d_mcad2 */ \
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* d2d_mcad3 */ \
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* d2d_mcad4 */ \
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* d2d_mcad5 */ \
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* d2d_mcad6 */ \
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* d2d_mcad7 */ \
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* d2d_mcad8 */ \
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* d2d_mcad9 */ \
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* d2d_mcad10 */ \
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* d2d_mcad11 */ \
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* d2d_mcad12 */ \
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* d2d_mcad13 */ \
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* d2d_mcad14 */ \
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* d2d_mcad15 */ \
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* d2d_mcad16 */ \
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* d2d_mcad17 */ \
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* d2d_mcad18 */ \
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* d2d_mcad19 */ \
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* d2d_mcad20 */ \
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* d2d_mcad21 */ \
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* d2d_mcad22 */ \
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* d2d_mcad23 */ \
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* d2d_mcad24 */ \
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* d2d_mcad25 */ \
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* d2d_mcad26 */ \
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* d2d_mcad27 */ \
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* d2d_mcad28 */ \
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* d2d_mcad29 */ \
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* d2d_mcad30 */ \
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* d2d_mcad31 */ \
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* d2d_mcad32 */ \
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* d2d_mcad33 */ \
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* d2d_mcad34 */ \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* d2d_mcad35 */ \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* d2d_mcad36 */ \
- MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* d2d_clk26mi */ \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* d2d_nrespwron */ \
- MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* d2d_nreswarm */ \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* d2d_arm9nirq */ \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* d2d_uma2p6fiq */ \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* d2d_spint */ \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* d2d_frint */ \
- MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* d2d_dmareq0 */ \
- MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* d2d_dmareq1 */ \
- MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* d2d_dmareq2 */ \
- MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* d2d_dmareq3 */ \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* d2d_n3gtrst */ \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* d2d_n3gtdi */ \
- MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* d2d_n3gtdo */ \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* d2d_n3gtms */ \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* d2d_n3gtck */ \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* d2d_n3grtck */ \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* d2d_mstdby */ \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* d2d_swakeup */ \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* d2d_idlereq */ \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* d2d_idleack */ \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* d2d_mwrite */ \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* d2d_swrite */ \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* d2d_mread */ \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* d2d_sread */ \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_mbusflag */ \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_sbusflag */ \
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* sdrc_cke0 */ \
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* sdrc_cke1 */ \
- MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* safe_mode */ \
- MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* gpio_126 */ \
- MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* gpio_128 */ \
- MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* gpio_129 */
-
-#endif
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
deleted file mode 100644
index b7ded7686bb..00000000000
--- a/configs/sniper_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TARGET_SNIPER=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
-# CONFIG_SPL_EXT_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SYS_PROMPT="sniper # "
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_SYS_OMAP24_I2C_SPEED=400000
-CONFIG_TWL4030_INPUT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_CONS_INDEX=3
-CONFIG_USB=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
deleted file mode 100644
index aa78684b02f..00000000000
--- a/include/configs/sniper.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LG Optimus Black codename sniper config
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-/*
- * CPU
- */
-
-#define CONFIG_ARM_ARCH_CP15_ERRATA
-
-/*
- * Board
- */
-
-/*
- * Clocks
- */
-
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2
-
-#define V_NS16550_CLK 48000000
-#define V_OSCK 26000000
-#define V_SCLK (V_OSCK >> 1)
-
-/*
- * DRAM
- */
-
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*
- * Memory
- */
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
-
-/*
- * I2C
- */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_I2C_MULTI_BUS
-
-/*
- * Input
- */
-
-/*
- * SPL
- */
-
-#define CONFIG_SPL_TEXT_BASE 0x40200000
-#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
- CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024)
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SYS_CBSIZE 512
-
-/*
- * Serial
- */
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#endif
-
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
- 115200 }
-
-/*
- * Environment
- */
-
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0x82000000\0" \
- "loadaddr=0x82000000\0" \
- "fdt_addr_r=0x88000000\0" \
- "fdtaddr=0x88000000\0" \
- "ramdisk_addr_r=0x88080000\0" \
- "pxefile_addr_r=0x80100000\0" \
- "scriptaddr=0x80000000\0" \
- "bootm_size=0x10000000\0" \
- "boot_mmc_dev=0\0" \
- "kernel_mmc_part=3\0" \
- "recovery_mmc_part=4\0" \
- "fdtfile=omap3-sniper.dtb\0" \
- "bootfile=/boot/extlinux/extlinux.conf\0" \
- "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
-
-/*
- * ATAGs
- */
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/*
- * Boot
- */
-
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
-#define CONFIG_BOOTCOMMAND \
- "setenv boot_mmc_part ${kernel_mmc_part}; " \
- "if test reboot-${reboot-mode} = reboot-r; then " \
- "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \
- "if test reboot-${reboot-mode} = reboot-b; then " \
- "echo fastboot; fastboot 0; fi; " \
- "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
- "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
- "mmc dev ${boot_mmc_dev}; " \
- "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
- "bootm ${kernel_addr_r};"
-
-/*
- * Defaults
- */
-
-#include <config_defaults.h>
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 10/93] arm: Remove omap3_zoom1 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (8 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 09/93] arm: Remove sniper board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 11/93] arm: Remove sksimx6 board Simon Glass
` (87 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/logicpd/zoom1/Kconfig | 12 ---
board/logicpd/zoom1/MAINTAINERS | 6 --
board/logicpd/zoom1/Makefile | 6 --
board/logicpd/zoom1/config.mk | 14 ---
board/logicpd/zoom1/zoom1.c | 146 ------------------------------
board/logicpd/zoom1/zoom1.h | 122 -------------------------
configs/omap3_zoom1_defconfig | 39 --------
include/configs/omap3_zoom1.h | 138 ----------------------------
9 files changed, 484 deletions(-)
delete mode 100644 board/logicpd/zoom1/Kconfig
delete mode 100644 board/logicpd/zoom1/MAINTAINERS
delete mode 100644 board/logicpd/zoom1/Makefile
delete mode 100644 board/logicpd/zoom1/config.mk
delete mode 100644 board/logicpd/zoom1/zoom1.c
delete mode 100644 board/logicpd/zoom1/zoom1.h
delete mode 100644 configs/omap3_zoom1_defconfig
delete mode 100644 include/configs/omap3_zoom1.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index b5f6061a17a..04b6ffe574a 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -202,7 +202,6 @@ source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig"
-source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
diff --git a/board/logicpd/zoom1/Kconfig b/board/logicpd/zoom1/Kconfig
deleted file mode 100644
index d76cb663f72..00000000000
--- a/board/logicpd/zoom1/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_ZOOM1
-
-config SYS_BOARD
- default "zoom1"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_CONFIG_NAME
- default "omap3_zoom1"
-
-endif
diff --git a/board/logicpd/zoom1/MAINTAINERS b/board/logicpd/zoom1/MAINTAINERS
deleted file mode 100644
index 338b965debd..00000000000
--- a/board/logicpd/zoom1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ZOOM1 BOARD
-M: Nishanth Menon <nm@ti.com>
-S: Maintained
-F: board/logicpd/zoom1/
-F: include/configs/omap3_zoom1.h
-F: configs/omap3_zoom1_defconfig
diff --git a/board/logicpd/zoom1/Makefile b/board/logicpd/zoom1/Makefile
deleted file mode 100644
index e73b42e7027..00000000000
--- a/board/logicpd/zoom1/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := zoom1.o
diff --git a/board/logicpd/zoom1/config.mk b/board/logicpd/zoom1/config.mk
deleted file mode 100644
index a8e4f52e7bf..00000000000
--- a/board/logicpd/zoom1/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006-2008
-# Texas Instruments, <www.ti.com>
-#
-# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
deleted file mode 100644
index 5e32077d649..00000000000
--- a/board/logicpd/zoom1/zoom1.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Nishanth Menon <nm@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- */
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <ns16550.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <linux/mtd/omap_gpmc.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "zoom1.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * gpmc_cfg is initialized by gpmc_init and we use it here.
- * GPMC definitions for Ethenet Controller LAN9211
- */
-static const u32 gpmc_lab_enet[] = {
- ZOOM1_ENET_GPMC_CONF1,
- ZOOM1_ENET_GPMC_CONF2,
- ZOOM1_ENET_GPMC_CONF3,
- ZOOM1_ENET_GPMC_CONF4,
- ZOOM1_ENET_GPMC_CONF5,
- ZOOM1_ENET_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-static const struct ns16550_platdata zoom1_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(zoom1_uart) = {
- "ns16550_serial",
- &zoom1_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* CS1 is Ethernet LAN9211 */
- enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
- DEBUG_BASE, GPMC_SIZE_16M);
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure zoom board specific configurations
- */
-int misc_init_r(void)
-{
- twl4030_power_init();
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
- omap_die_id_display();
-
- /*
- * Board Reset
- * The board is reset by holding the red button on the
- * top right front face for eight seconds.
- */
- twl4030_power_reset_init();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- /* platform specific muxes */
- MUX_ZOOM1_MDK();
-}
-
-#ifdef CONFIG_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_SMC911X
-#define STR_ENV_ETHADDR "ethaddr"
-
- struct eth_device *dev;
- uchar eth_addr[6];
-
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
- dev = eth_get_dev_by_index(0);
- if (dev) {
- eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
- } else {
- printf("zoom1: Couldn't get eth device\n");
- rc = -1;
- }
- }
-#endif
-
- return rc;
-}
-#endif
diff --git a/board/logicpd/zoom1/zoom1.h b/board/logicpd/zoom1/zoom1.h
deleted file mode 100644
index 63847616cfd..00000000000
--- a/board/logicpd/zoom1/zoom1.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Texas Instruments
- * Nishanth Menon <nm@ti.com>
- *
- * Derived from: board/omap3/beagle/beagle.h
- * Dirk Behme <dirk.behme@gmail.com>
- */
-#ifndef _BOARD_ZOOM1_H_
-#define _BOARD_ZOOM1_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 Zoom MDK Rev 1",
- "NAND",
-};
-
-#define ZOOM1_ENET_GPMC_CONF1 0x00611000
-#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
-#define ZOOM1_ENET_GPMC_CONF3 0x00080803
-#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
-#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
-#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_ZOOM1_MDK() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
-
-#endif /* _BOARD_ZOOM_H_ */
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
deleted file mode 100644
index 325c0020cab..00000000000
--- a/configs/omap3_zoom1_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_ZOOM1=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x08000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_UDC=y
-CONFIG_USB_OMAP3=y
-CONFIG_TWL4030_USB=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
deleted file mode 100644
index 0a02ecdc149..00000000000
--- a/include/configs/omap3_zoom1.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- * Nishanth Menon <nm@ti.com>
- *
- * Configuration settings for the TI OMAP3430 Zoom MDK board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-#include <configs/ti_omap3_common.h>
-
-/* Remove SPL boot option - we do not support that on LDP yet */
-
-/* Generic NAND definition conflicts with debug_base */
-#undef CONFIG_SYS_NAND_BASE
-
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
-/*
- * Hardware drivers
- */
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
-
-#if defined(CONFIG_CMD_NAND)
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-#endif
-
-/*
- * TWL4030
- */
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
-
-/* Environment information */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "fdtaddr=0x80f80000\0" \
- "bootfile=uImage\0" \
- "fdtfile=omap3-ldp.dtb\0" \
- "bootdir=/\0" \
- "bootpart=0:1\0" \
- "usbtty=cdc_acm\0" \
- "console=ttyO2,115200n8\0" \
- "mmcdev=0\0" \
- "videomode=1024x768 at 60,vxres=1024,vyres=768\0" \
- "videospec=omapfb:vram:2M,vram:4M\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "video=${videospec},mode:${videomode} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "video=${videospec},mode:${videomode} " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "mmczboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else if run loadzimage; then " \
- "run mmczboot; " \
- "else run nandboot; " \
- "fi; fi;" \
- "fi; " \
- "else run nandboot; fi"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \
- 0x01F00000) /* 31MB */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#endif
-
-/* Monitor@start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 11/93] arm: Remove sksimx6 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (9 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 10/93] arm: Remove omap3_zoom1 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 12/93] arm: Remove tbs2910 board Simon Glass
` (86 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/sks-kinkel/sksimx6/Kconfig | 11 -
board/sks-kinkel/sksimx6/MAINTAINERS | 6 -
board/sks-kinkel/sksimx6/Makefile | 2 -
board/sks-kinkel/sksimx6/sksimx6.c | 425 ---------------------------
configs/sksimx6_defconfig | 42 ---
include/configs/sksimx6.h | 96 ------
7 files changed, 583 deletions(-)
delete mode 100644 board/sks-kinkel/sksimx6/Kconfig
delete mode 100644 board/sks-kinkel/sksimx6/MAINTAINERS
delete mode 100644 board/sks-kinkel/sksimx6/Makefile
delete mode 100644 board/sks-kinkel/sksimx6/sksimx6.c
delete mode 100644 configs/sksimx6_defconfig
delete mode 100644 include/configs/sksimx6.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index fb25bc81e11..9ed827067b1 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -557,7 +557,6 @@ source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
-source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
diff --git a/board/sks-kinkel/sksimx6/Kconfig b/board/sks-kinkel/sksimx6/Kconfig
deleted file mode 100644
index 3efdf9d8b2a..00000000000
--- a/board/sks-kinkel/sksimx6/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_SKSIMX6
-
-config SYS_BOARD
- default "sksimx6"
-
-config SYS_VENDOR
- default "sks-kinkel"
-
-config SYS_CONFIG_NAME
- default "sksimx6"
-endif
diff --git a/board/sks-kinkel/sksimx6/MAINTAINERS b/board/sks-kinkel/sksimx6/MAINTAINERS
deleted file mode 100644
index c1527bfa5f3..00000000000
--- a/board/sks-kinkel/sksimx6/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SKS-Kinkel sksimx6
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/sks-kinkel/sksimx6/
-F: include/configs/sksimx6.h
-F: configs/sksimx6_defconfig
diff --git a/board/sks-kinkel/sksimx6/Makefile b/board/sks-kinkel/sksimx6/Makefile
deleted file mode 100644
index 1828fadd4e8..00000000000
--- a/board/sks-kinkel/sksimx6/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-#
-obj-y := sksimx6.o
diff --git a/board/sks-kinkel/sksimx6/sksimx6.c b/board/sks-kinkel/sksimx6/sksimx6.c
deleted file mode 100644
index f6e3d4d12e0..00000000000
--- a/board/sks-kinkel/sksimx6/sksimx6.c
+++ /dev/null
@@ -1,425 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <micrel.h>
-
-#include <common.h>
-#include <malloc.h>
-#include <fuse.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const gpios_pads[] = {
- IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-iomux_v3_cfg_t const enet_pads1[] = {
- /* pin 35 - 1 (PHY_AD2) on reset */
- IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 32 - 1 - (MODE0) all */
- IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 31 - 1 - (MODE1) all */
- IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 28 - 1 - (MODE2) all */
- IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 27 - 1 - (MODE3) all */
- IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 42 PHY nRST */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
-
- /* min rx data delay */
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- /* min tx data delay */
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- /* max rx/tx clock delay, min rx/tx control */
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-
-#define ENET_NRST IMX_GPIO_NR(1, 25)
-
-void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
-}
-
-int board_eth_init(bd_t *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
- /* scan phy */
- phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
- PHY_INTERFACE_MODE_RGMII);
-
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret)
- goto free_phydev;
-
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
-int board_early_init_f(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* Take in reset the ATMega processor */
- SETUP_IOMUX_PADS(gpios_pads);
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR, 0},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- if (cfg->esdhc_base == USDHC2_BASE_ADDR)
- ret = 1;
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- SETUP_IOMUX_PADS(usdhc2_pads);
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[0].max_bus_width = 4;
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev \n");
- return ret;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD)
-#include <asm/arch/mx6-ddr.h>
-
-/*
- * Driving strength:
- * 0x30 == 40 Ohm
- * 0x28 == 48 Ohm
- */
-#define IMX6SDL_DRIVE_STRENGTH 0x230
-
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
- /* quad = 1066, duallite = 800 */
- .mem_speed = 1066,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 0,
-};
-
-static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0043004E,
- .p0_mpwldectrl1 = 0x003D003F,
- .p1_mpwldectrl0 = 0x00230021,
- .p1_mpwldectrl1 = 0x0028003E,
- .p0_mpdgctrl0 = 0x42580250,
- .p0_mpdgctrl1 = 0x0238023C,
- .p1_mpdgctrl0 = 0x422C0238,
- .p1_mpdgctrl1 = 0x02180228,
- .p0_mprddlctl = 0x44464A46,
- .p1_mprddlctl = 0x44464A42,
- .p0_mpwrdlctl = 0x36343236,
- .p1_mpwrdlctl = 0x36343230,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_qdl = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 1,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* set the default clock gate to save power */
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
- if (is_cpu_type(MXC_CPU_MX6DL)) {
- mt41k128m16jt_125.mem_speed = 800;
- mem_qdl.rtt_nom = 1;
- mem_qdl.rtt_wr = 1;
-
- mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
- } else {
- printf("Wrong CPU for this board\n");
- return;
- }
-
- udelay(100);
-
-#ifdef CONFIG_MX6_DDRCAL
-
- /* Perform DDR DRAM calibration */
- mmdc_do_write_level_calibration(&mem_qdl);
- mmdc_do_dqs_calibration(&mem_qdl);
-#endif
-}
-
-static void check_bootcfg(void)
-{
- u32 val5, val6;
-
- fuse_sense(0, 5, &val5);
- fuse_sense(0, 6, &val6);
- /* Check if boot from MMC */
- if (val6 & 0x10) {
- puts("BT_FUSE_SEL already fused, will do nothing\n");
- return;
- }
- fuse_prog(0, 5, 0x00000840);
- /* BT_FUSE_SEL */
- fuse_prog(0, 6, 0x00000010);
-
- do_reset(NULL, 0, 0, NULL);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- gpr_init();
-
- /* iomux */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Set fuses for new boards and reboot if not set */
- check_bootcfg();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
deleted file mode 100644
index bd9cc735a88..00000000000
--- a/configs/sksimx6_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_SKSIMX6=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
-CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SILENT_U_BOOT_ONLY=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h
deleted file mode 100644
index 4f7ec2d7e99..00000000000
--- a/include/configs/sksimx6.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- */
-
-
-#ifndef __SKSIMX6_CONFIG_H
-#define __SKSIMX6_CONFIG_H
-
-#include "mx6_common.h"
-#include "imx6_spl.h"
-
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
-/* Serial */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
-/* Ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0x01
-
-#define CONFIG_PHY_MICREL_KSZ9021
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C2
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* Filesystem support */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/* Default environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
- "bootcmd=run mmcboot\0" \
- "bootfile=uImage\0" \
- "bootimage=uImage\0" \
- "console=ttymxc0\0" \
- "fdt_addr_r=0x18000000\0" \
- "fdt_file=imx6dl-sks-cts.dtb\0" \
- "fdt_high=0xffffffff\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "miscargs=quiet\0" \
- "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
- "mmcboot=if run mmcload;then " \
- "run mmcargs addcons addmisc;" \
- "bootm;fi\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1\0" \
- "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
- "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
- "run nfsargs addip addcons addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs " \
- "nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 12/93] arm: Remove tbs2910 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (10 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 11/93] arm: Remove sksimx6 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 13/93] arm: Remove theadorable_debug board Simon Glass
` (85 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/tbs/tbs2910/Kconfig | 18 --
board/tbs/tbs2910/MAINTAINERS | 6 -
board/tbs/tbs2910/Makefile | 5 -
board/tbs/tbs2910/tbs2910.c | 454 ----------------------------------
board/tbs/tbs2910/tbs2910.cfg | 114 ---------
configs/tbs2910_defconfig | 58 -----
include/configs/tbs2910.h | 158 ------------
8 files changed, 814 deletions(-)
delete mode 100644 board/tbs/tbs2910/Kconfig
delete mode 100644 board/tbs/tbs2910/MAINTAINERS
delete mode 100644 board/tbs/tbs2910/Makefile
delete mode 100644 board/tbs/tbs2910/tbs2910.c
delete mode 100644 board/tbs/tbs2910/tbs2910.cfg
delete mode 100644 configs/tbs2910_defconfig
delete mode 100644 include/configs/tbs2910.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 9ed827067b1..2b96c55b61b 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -559,7 +559,6 @@ source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
-source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/apalis_imx6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig
deleted file mode 100644
index 2e5e1d492a5..00000000000
--- a/board/tbs/tbs2910/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if TARGET_TBS2910
-
-config SYS_BOARD
- default "tbs2910"
-
-config SYS_VENDOR
- default "tbs"
-
-config SYS_CONFIG_NAME
- default "tbs2910"
-
-config MX6Q
- default y
-
-config IMX_CONFIG
- default "board/tbs/tbs2910/tbs2910.cfg"
-
-endif
diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS
deleted file mode 100644
index bf176553d24..00000000000
--- a/board/tbs/tbs2910/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TBS2910 BOARD
-M: Soeren Moch <smoch@web.de>
-S: Maintained
-F: board/tbs/tbs2910/
-F: configs/tbs2910_defconfig
-F: include/configs/tbs2910.h
diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile
deleted file mode 100644
index 78f4a3eecd4..00000000000
--- a/board/tbs/tbs2910/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2014 Soeren Moch <smoch@web.de>
-
-obj-y := tbs2910.o
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
deleted file mode 100644
index ecb45f208d0..00000000000
--- a/board/tbs/tbs2910/tbs2910.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Soeren Moch <smoch@web.de>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#ifdef CONFIG_SYS_I2C
-/* I2C1, SGTL5000 */
-static struct i2c_pads_info i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-/* I2C2 HDMI */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* I2C3, CON11, DS1307, PCIe_SMB */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-#endif /* CONFIG_SYS_I2C */
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* AR8035 PHY Reset */
- MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const pcie_pads[] = {
- /* W_DISABLE# */
- MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
- /* PERST# */
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int dram_init(void)
-{
- gd->ram_size = 2048ul * 1024 * 1024;
- return 0;
-}
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
- /* Reset AR8035 PHY */
- gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
- udelay(500);
- gpio_set_value(IMX_GPIO_NR(1, 25), 1);
-}
-
-static void setup_pcie(void)
-{
- imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
-}
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- /*
- * (U-Boot device node) (Physical Port)
- * mmc0 SD2
- * mmc1 SD3
- * mmc2 eMMC
- */
- int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- gpio_direction_input(USDHC3_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
- return 0;
-}
-
-/* set environment device to boot device when booting from SD */
-int board_mmc_get_env_dev(int devno)
-{
- return devno - 1;
-}
-
-int board_mmc_get_env_part(int devno)
-{
- return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
-}
-#endif /* CONFIG_FSL_ESDHC */
-
-#ifdef CONFIG_VIDEO_IPUV3
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- /* 1024x768@60Hz (VESA)*/
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15384,
- .left_margin = 160,
- .right_margin = 24,
- .upper_margin = 29,
- .lower_margin = 3,
- .hsync_len = 136,
- .vsync_len = 6,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- s32 timeout = 100000;
-
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
- reg = readl(&ccm->analog_pll_video);
- reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
- writel(reg, &ccm->analog_pll_video);
-
- reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
- reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
- writel(reg, &ccm->analog_pll_video);
-
- writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
- writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
-
- reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
- writel(reg, &ccm->analog_pll_video);
-
- while (timeout--)
- if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
- break;
- if (timeout < 0)
- printf("Warning: video pll lock timeout!\n");
-
- reg = readl(&ccm->analog_pll_video);
- reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
- reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
- writel(reg, &ccm->analog_pll_video);
-
- /* gate ipu1_di0_clk */
- reg = readl(&ccm->CCGR3);
- reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &ccm->CCGR3);
-
- /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
- reg = readl(&ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
- MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
- MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
- reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
- (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
- (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &ccm->chsccdr);
-
- /* enable ipu1_di0_clk */
- reg = readl(&ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &ccm->CCGR3);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-static int ar8035_phy_fixup(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- ar8035_phy_fixup(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
- setup_pcie();
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_VIDEO_IPUV3
- setup_display();
-#endif
-#ifdef CONFIG_SYS_I2C
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
-#ifdef CONFIG_DWC_AHSATA
- setup_sata();
-#endif
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-#ifdef CONFIG_USB_EHCI_MX6
- imx_iomux_v3_setup_multiple_pads(
- usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
-#endif
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: TBS2910 Matrix ARM mini PC\n");
- return 0;
-}
diff --git a/board/tbs/tbs2910/tbs2910.cfg b/board/tbs/tbs2910/tbs2910.cfg
deleted file mode 100644
index 3ca807b3157..00000000000
--- a/board/tbs/tbs2910/tbs2910.cfg
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Soeren Moch <smoch@web.de>
- */
-
-#define __ASSEMBLY__
-#include "asm/arch/crm_regs.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/mx6-ddr.h"
-
-/* image version 2 for imx6 */
-IMAGE_VERSION 2
-BOOT_FROM sd
-
-/* set the default clock gates to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
-DATA 4, CCM_CCOSR, 0x000000fb
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x77177717
-DATA 4, MX6_IOMUXC_GPR7, 0x77177717
-
-
-/*
- * DDR3/DDR3L settings
- * use default 40 Ohm pad drive strength, no odt
- * 4x256Mx16 DDR3L-1066 7-7-7
- */
-
-/* disable dq pullup */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-/* disable dqs pullup */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-/* set ddr input mode for dq signals */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* set ddr input mode for dqs signals */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* set pad calibration type to DDR3 */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-/* dqs write delay */
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
-/* dqs read delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-/* dqs read gating control */
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
-/* start delay line calibration */
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
-/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
-/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
-DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
-/* ODT timing */
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-/* read odt settings, 120 Ohm */
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
-/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
-/* 2GiByte RAM at cs0 */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-/* load mode registers of external ddr chips */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-/* externel chip ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-/* configure and start refreshes, 8 refresh commands at 32 kHz */
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-/* set automatic self refresh */
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
-/* controller configuration finished */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
deleted file mode 100644
index 55cd9bd998f..00000000000
--- a/configs/tbs2910_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_TBS2910=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x7c000000
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Matrix U-Boot> "
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="TBS"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
deleted file mode 100644
index a60223c6235..00000000000
--- a/include/configs/tbs2910.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Soeren Moch <smoch@web.de>
- *
- * Configuration settings for the TBS2910 MatrixARM board.
- */
-
-#ifndef __TBS2910_CONFIG_H
-#define __TBS2910_CONFIG_H
-
-#include "mx6_common.h"
-
-/* General configuration */
-
-#define CONFIG_MACH_TYPE 3980
-
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_IMX_THERMAL
-
-/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
-
-#define CONFIG_SYS_BOOTMAPSZ 0x10000000
-
-/* Serial console */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
-
-/* Filesystems / image support */
-
-/* MMC */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-/* Ethernet */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 4
-#define CONFIG_PHY_ATHEROS
-
-/* Framebuffer */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-#endif
-
-/* PCI */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
-#endif
-
-/* SATA */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#ifdef CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USBD_HS
-#endif /* CONFIG_CMD_USB_MASS_STORAGE */
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT \
- "usb start; " \
- "if hdmidet; then " \
- "run set_con_hdmi; " \
- "else " \
- "run set_con_serial; " \
- "fi;"
-#endif /* CONFIG_USB_KEYBOARD */
-#endif /* CONFIG_CMD_USB */
-
-/* RTC */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1307
-#define CONFIG_SYS_RTC_BUS_NUM 2
-#endif
-
-/* I2C */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_I2C_EDID
-#endif
-
-/* Environment organization */
-#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
-#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
-#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_OFFSET (384 * 1024)
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
- "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M at 60 " \
- "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
- "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
- "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
- "${bootargs_mmc3}\0" \
- "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
- "rdinit=/sbin/init enable_wait_mode=off\0" \
- "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
- "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
- "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
- "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
- "run bootargs_upd; " \
- "bootm 0x10800000 0x10d00000\0" \
- "console=ttymxc0\0" \
- "fan=gpio set 92\0" \
- "set_con_serial=setenv stdout serial; " \
- "setenv stderr serial;\0" \
- "set_con_hdmi=setenv stdout serial,vga; " \
- "setenv stderr serial,vga;\0" \
- "stderr=serial,vga;\0" \
- "stdin=serial,usbkbd;\0" \
- "stdout=serial,vga;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; " \
- "if run bootcmd_up1; then " \
- "run bootcmd_up2; " \
- "else " \
- "run bootcmd_mmc; " \
- "fi"
-
-#endif /* __TBS2910_CONFIG_H * */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 13/93] arm: Remove theadorable_debug board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (11 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 12/93] arm: Remove tbs2910 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 14/93] arm: Remove devkit3250 board Simon Glass
` (84 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/theadorable/MAINTAINERS | 6 -
board/theadorable/Makefile | 6 -
board/theadorable/fpga.c | 178 ---------------
board/theadorable/theadorable.c | 336 ----------------------------
board/theadorable/theadorable.h | 11 -
configs/theadorable_debug_defconfig | 74 ------
include/configs/theadorable.h | 125 -----------
7 files changed, 736 deletions(-)
delete mode 100644 board/theadorable/MAINTAINERS
delete mode 100644 board/theadorable/Makefile
delete mode 100644 board/theadorable/fpga.c
delete mode 100644 board/theadorable/theadorable.c
delete mode 100644 board/theadorable/theadorable.h
delete mode 100644 configs/theadorable_debug_defconfig
delete mode 100644 include/configs/theadorable.h
diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS
deleted file mode 100644
index 1e8df93d379..00000000000
--- a/board/theadorable/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-THEADORABLE BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/theadorable/
-F: include/configs/theadorable.h
-F: configs/theadorable_debug_defconfig
diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile
deleted file mode 100644
index b85faa676d7..00000000000
--- a/board/theadorable/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
-
-obj-y := theadorable.o
-obj-y += fpga.o
diff --git a/board/theadorable/fpga.c b/board/theadorable/fpga.c
deleted file mode 100644
index 4f8bf5e778f..00000000000
--- a/board/theadorable/fpga.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <altera.h>
-#include <errno.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-mvebu/spi.h>
-#include "theadorable.h"
-
-/*
- * FPGA programming support
- */
-static int fpga_pre_fn(int cookie)
-{
- int gpio_config = COOKIE2CONFIG(cookie);
- int gpio_done = COOKIE2DONE(cookie);
- int ret;
-
- debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n",
- __func__, __LINE__, cookie, gpio_config, gpio_done);
-
- /* Configure config pin */
- /* Set to output */
- ret = gpio_request(gpio_config, "CONFIG");
- if (ret < 0)
- return ret;
- gpio_direction_output(gpio_config, 1);
-
- /* Configure done pin */
- /* Set to input */
- ret = gpio_request(gpio_done, "DONE");
- if (ret < 0)
- return ret;
-
- gpio_direction_input(gpio_done);
-
- return 0;
-}
-
-static int fpga_config_fn(int assert, int flush, int cookie)
-{
- int gpio_config = COOKIE2CONFIG(cookie);
-
- debug("%s (%d): cookie=%08x gpio_config=%d\n",
- __func__, __LINE__, cookie, gpio_config);
-
- if (assert)
- gpio_set_value(gpio_config, 1);
- else
- gpio_set_value(gpio_config, 0);
-
- return 0;
-}
-
-static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
-{
- int spi_bus = COOKIE2SPI_BUS(cookie);
- int spi_dev = COOKIE2SPI_DEV(cookie);
- struct kwspi_registers *reg;
- u32 control_reg;
- u32 config_reg;
- void *dst;
-
- /*
- * Write data to FPGA attached to SPI bus via SPI direct write.
- * This results in the fastest and easiest way to program the
- * bitstream into the FPGA.
- */
- debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n",
- __func__, __LINE__, cookie, spi_bus, spi_dev);
-
- if (spi_bus == 0) {
- reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600);
- dst = (void *)SPI_BUS0_DEV1_BASE;
- } else {
- reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680);
- dst = (void *)SPI_BUS1_DEV2_BASE;
- }
-
- /* Configure SPI controller for direct access mode */
- control_reg = readl(®->ctrl);
- config_reg = readl(®->cfg);
- writel(0x00000214, ®->cfg); /* 27MHz clock */
- writel(0x00000000, ®->dw_cfg); /* don't de-asset CS */
- writel(KWSPI_CSN_ACT, ®->ctrl); /* activate CS */
-
- /* Copy data to the SPI direct mapped window */
- memcpy(dst, buf, len);
-
- /* Restore original register values */
- writel(control_reg, ®->ctrl);
- writel(config_reg, ®->cfg);
-
- return 0;
-}
-
-/* Returns the state of CONF_DONE Pin */
-static int fpga_done_fn(int cookie)
-{
- int gpio_done = COOKIE2DONE(cookie);
- unsigned long ts;
-
- debug("%s (%d): cookie=%08x gpio_done=%d\n",
- __func__, __LINE__, cookie, gpio_done);
-
- ts = get_timer(0);
- do {
- if (gpio_get_value(gpio_done))
- return 0;
- } while (get_timer(ts) < 1000);
-
- /* timeout so return error */
- return -ENODEV;
-}
-
-static altera_board_specific_func stratixv_fns = {
- .pre = fpga_pre_fn,
- .config = fpga_config_fn,
- .write = fpga_write_fn,
- .done = fpga_done_fn,
-};
-
-static Altera_desc altera_fpga[] = {
- {
- /* Family */
- Altera_StratixV,
- /* Interface type */
- passive_serial,
- /* No limitation as additional data will be ignored */
- -1,
- /* Device function table */
- (void *)&stratixv_fns,
- /* Base interface address specified in driver */
- NULL,
- /* Cookie implementation */
- /*
- * In this 32bit word the following information is coded:
- * Bit 31 ... Bit 0
- * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
- */
- FPGA_COOKIE(0, 1, 26, 7)
- },
- {
- /* Family */
- Altera_StratixV,
- /* Interface type */
- passive_serial,
- /* No limitation as additional data will be ignored */
- -1,
- /* Device function table */
- (void *)&stratixv_fns,
- /* Base interface address specified in driver */
- NULL,
- /* Cookie implementation */
- /*
- * In this 32bit word the following information is coded:
- * Bit 31 ... Bit 0
- * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
- */
- FPGA_COOKIE(1, 2, 29, 9)
- },
-};
-
-/* Add device descriptor to FPGA device table */
-void board_fpga_add(void)
-{
- int i;
-
- fpga_init();
- for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
- fpga_add(fpga_altera, &altera_fpga[i]);
-}
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
deleted file mode 100644
index b59589ae829..00000000000
--- a/board/theadorable/theadorable.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <pci.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <linux/crc8.h>
-#include <linux/mbus.h>
-#ifdef CONFIG_NET
-#include <netdev.h>
-#endif
-#include "theadorable.h"
-
-#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
-#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
-#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
- (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
-
-#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
-#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
-#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
-
-#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
-#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
-#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
-
-#define GPIO_USB0_PWR_ON 18
-#define GPIO_USB1_PWR_ON 19
-
-#define PEX_SWITCH_NOT_FOUNT_LIMIT 3
-
-#define STM_I2C_BUS 1
-#define STM_I2C_ADDR 0x27
-#define REBOOT_DELAY 1000 /* reboot-delay in ms */
-
-/* DDR3 static configuration */
-static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
- {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
- {0x00001404, 0x30000800}, /* Dunit Control Low Register */
- {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
- {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
- {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
- {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
- {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
- {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
- {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
-
- {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
- {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
- {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
- {0x000014A8, 0x00000101}, /* AXI Control Register */
-
- /*
- * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
- * training sequence
- */
- {0x000200e8, 0x3fff0e01},
- {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
-
- {0x0001504, 0x7fffffe1}, /* CS0 Size */
- {0x000150C, 0x00000000}, /* CS1 Size */
- {0x0001514, 0x00000000}, /* CS2 Size */
- {0x000151C, 0x00000000}, /* CS3 Size */
-
- {0x00020220, 0x00000007}, /* Reserved */
-
- {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
- {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
-
- {0x000015D0, 0x00000650}, /* MR0 */
- {0x000015D4, 0x00000044}, /* MR1 */
- {0x000015D8, 0x00000010}, /* MR2 */
- {0x000015DC, 0x00000000}, /* MR3 */
- {0x000015E0, 0x00000001},
- {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
- {0x000015EC, 0xf800a225}, /* DDR PHY */
-
- /* Recommended Settings from Marvell for 4 x 16 bit devices: */
- {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
- {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
-
- {0x0, 0x0}
-};
-
-static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
- {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
-};
-
-extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
-
-/*
- * Lane0 - PCIE0.0 X1 (to WIFI Module)
- * Lane5 - SATA0
- * Lane6 - SATA1
- * Lane7 - SGMII0 (to Ethernet Phy)
- * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
- * all other lanes are disabled
- */
-MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
- { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
- { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
- PEX_BUS_DISABLED },
- 0x0060, serdes_change_m_phy
- },
-};
-
-/*
- * Define a board-specific detection pulse-width array for the SerDes PCIe
- * interfaces. If not defined in the board code, the default of currently 2
- * is used. Values from 0...3 are possible (2 bits).
- */
-u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
-
-MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
-{
- /* Only one mode supported for this board */
- return &board_ddr_modes[0];
-}
-
-MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
-{
- return &theadorable_serdes_cfg[0];
-}
-
-u8 board_sat_r_get(u8 dev_num, u8 reg)
-{
- /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
- return 0x01;
-}
-
-int board_early_init_f(void)
-{
- /* Configure MPP */
- writel(0x00000000, MVEBU_MPP_BASE + 0x00);
- writel(0x03300000, MVEBU_MPP_BASE + 0x04);
- writel(0x00000033, MVEBU_MPP_BASE + 0x08);
- writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
- writel(0x11110000, MVEBU_MPP_BASE + 0x10);
- writel(0x00221100, MVEBU_MPP_BASE + 0x14);
- writel(0x00000000, MVEBU_MPP_BASE + 0x18);
- writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
- writel(0x00000000, MVEBU_MPP_BASE + 0x20);
-
- /* Configure GPIO */
- writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
- writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
- writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
- writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
- writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
- writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
-
- return 0;
-}
-
-int board_init(void)
-{
- int ret;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- /*
- * Map SPI devices via MBUS so that they can be accessed via
- * the SPI direct access mode
- */
- mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
- CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
- mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
- CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
-
- /*
- * Set RX Channel Control 0 Register:
- * Tests have shown, that setting the LPF_COEF from 0 (1/8)
- * to 3 (1/1) results in a more stable USB connection.
- */
- setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
- setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
- setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
-
- /* Toggle USB power */
- ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
- if (ret < 0)
- return ret;
- gpio_direction_output(GPIO_USB0_PWR_ON, 0);
- ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
- if (ret < 0)
- return ret;
- gpio_direction_output(GPIO_USB1_PWR_ON, 0);
- mdelay(1);
- gpio_set_value(GPIO_USB0_PWR_ON, 1);
- gpio_set_value(GPIO_USB1_PWR_ON, 1);
-
- return 0;
-}
-
-int checkboard(void)
-{
- board_fpga_add();
-
- return 0;
-}
-
-#ifdef CONFIG_NET
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in controller(s) come first */
- return pci_eth_init(bis);
-}
-#endif
-
-int board_video_init(void)
-{
- struct mvebu_lcd_info lcd_info;
-
- /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
- lcd_info.fb_base = gd->ram_size;
- lcd_info.x_res = 240;
- lcd_info.x_fp = 1;
- lcd_info.x_bp = 45;
- lcd_info.y_res = 320;
- lcd_info.y_fp = 1;
- lcd_info.y_bp = 3;
-
- return mvebu_lcd_register_init(&lcd_info);
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- pci_dev_t bdf;
- ulong bootcount;
-
- /*
- * Check if the PEX switch is detected (somtimes its not available
- * on the PCIe bus). In this case, try to recover by issuing a
- * soft-reset or even a power-cycle, depending on the bootcounter
- * value.
- */
- bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
- if (bdf == -1) {
- u8 i2c_buf[8];
- int ret;
-
- /* PEX switch not found! */
- bootcount = bootcount_load();
- printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
- bootcount);
- if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
- printf("Issuing power-switch via uC!\n");
-
- printf("Issuing power-switch via uC!\n");
- i2c_set_bus_num(STM_I2C_BUS);
- i2c_buf[0] = STM_I2C_ADDR << 1;
- i2c_buf[1] = 0xc5; /* cmd */
- i2c_buf[2] = 0x01; /* enable */
- /* Delay before reboot */
- i2c_buf[3] = REBOOT_DELAY & 0x00ff;
- i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
- /* Delay before shutdown */
- i2c_buf[5] = 0x00;
- i2c_buf[6] = 0x00;
- i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
-
- ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
- if (ret) {
- printf("I2C write error (ret=%d)\n", ret);
- printf("Issuing soft-reset...\n");
- /* default handling: SOFT reset */
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Wait for power-cycle to occur... */
- printf("Waiting for power-cycle via uC...\n");
- while (1)
- ;
- } else {
- printf("Issuing soft-reset...\n");
- /* default handling: SOFT reset */
- do_reset(NULL, 0, 0, NULL);
- }
- }
-
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
-int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pci_dev_t bdf;
- u16 ven_id, dev_id;
-
- if (argc != 3)
- return cmd_usage(cmdtp);
-
- ven_id = simple_strtoul(argv[1], NULL, 16);
- dev_id = simple_strtoul(argv[2], NULL, 16);
-
- printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
- ven_id, dev_id);
-
- /*
- * Check if the PCIe device is detected (somtimes its not available
- * on the PCIe bus)
- */
- bdf = pci_find_device(ven_id, dev_id, 0);
- if (bdf == -1) {
- /* PCIe device not found! */
- printf("Failed to find PCIe device\n");
- } else {
- /* PCIe device found! */
- printf("PCIe device found, resetting board...\n");
-
- /* default handling: SOFT reset */
- do_reset(NULL, 0, 0, NULL);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- pcie, 3, 0, do_pcie_test,
- "Test for presence of a PCIe device",
- "<VendorID> <DeviceID>"
-);
-#endif
diff --git a/board/theadorable/theadorable.h b/board/theadorable/theadorable.h
deleted file mode 100644
index d3c959de984..00000000000
--- a/board/theadorable/theadorable.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
- */
-
-/* Base addresses for the SPI direct access mode */
-#define SPI_BUS0_DEV1_BASE 0xe0000000
-#define SPI_BUS0_DEV1_SIZE (1 << 20)
-#define SPI_BUS1_DEV2_BASE (SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE)
-
-void board_fpga_add(void);
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
deleted file mode 100644
index 9e99618998c..00000000000
--- a/configs/theadorable_debug_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_TEXT_BASE=0x00800000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_THEADORABLE=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SATA_MV=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_RAM=y
-CONFIG_FPGA_ALTERA=y
-CONFIG_DM_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_MVNETA=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_MVEBU=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
deleted file mode 100644
index 2526a000840..00000000000
--- a/include/configs/theadorable.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- */
-
-#ifndef _CONFIG_THEADORABLE_H
-#define _CONFIG_THEADORABLE_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-/*
- * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
- * for DDR ECC byte filling in the SPL before loading the main
- * U-Boot into it.
- */
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-
-/*
- * Commands configuration
- */
-
-/*
- * The debugging version enables USB support via defconfig.
- * This version should also enable all other non-production
- * interfaces / features.
- */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-
-/* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
-#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
-#define CONFIG_ENV_OVERWRITE
-
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
-#define CONFIG_PREBOOT
-
-/* Keep device tree and initrd in lower memory so the kernel can access them */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "fdt_high=0x10000000\0" \
- "initrd_high=0x10000000\0"
-
-/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_LBA48
-
-/* PCIe support */
-#ifdef CONFIG_CMD_PCI
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#endif
-#endif
-
-/* Enable LCD and reserve 512KB from top of memory*/
-#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
-
-/* FPGA programming support */
-#define CONFIG_FPGA_STRATIX_V
-
-/*
- * Bootcounter
- */
-/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
-#define BOOTCOUNT_ADDR 0x1000
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Memory layout while starting into the bin_hdr via the
- * BootROM:
- *
- * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
- * 0x4000.4030 bin_hdr start address
- * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
- * 0x4007.fffc BootROM stack top
- *
- * The address space between 0x4007.fffc and 0x400f.fff is not locked in
- * L2 cache thus cannot be used.
- */
-
-/* SPL */
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x40004030
-#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-
-/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
-#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
-
-#endif /* _CONFIG_THEADORABLE_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 14/93] arm: Remove devkit3250 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (12 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 13/93] arm: Remove theadorable_debug board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 15/93] arm: Remove pcm051_rev3 board Simon Glass
` (83 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/arm926ejs/lpc32xx/Kconfig | 1 -
board/timll/devkit3250/Kconfig | 12 --
board/timll/devkit3250/MAINTAINERS | 6 -
board/timll/devkit3250/Makefile | 7 -
board/timll/devkit3250/devkit3250.c | 80 ----------
board/timll/devkit3250/devkit3250_spl.c | 67 --------
configs/devkit3250_defconfig | 48 ------
include/configs/devkit3250.h | 194 ------------------------
8 files changed, 415 deletions(-)
delete mode 100644 board/timll/devkit3250/Kconfig
delete mode 100644 board/timll/devkit3250/MAINTAINERS
delete mode 100644 board/timll/devkit3250/Makefile
delete mode 100644 board/timll/devkit3250/devkit3250.c
delete mode 100644 board/timll/devkit3250/devkit3250_spl.c
delete mode 100644 configs/devkit3250_defconfig
delete mode 100644 include/configs/devkit3250.h
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
index 986ad738ac1..407252c8c30 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
@@ -14,7 +14,6 @@ config TARGET_WORK_92105
endchoice
-source "board/timll/devkit3250/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
endif
diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig
deleted file mode 100644
index 5129c2dcae5..00000000000
--- a/board/timll/devkit3250/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DEVKIT3250
-
-config SYS_BOARD
- default "devkit3250"
-
-config SYS_VENDOR
- default "timll"
-
-config SYS_CONFIG_NAME
- default "devkit3250"
-
-endif
diff --git a/board/timll/devkit3250/MAINTAINERS b/board/timll/devkit3250/MAINTAINERS
deleted file mode 100644
index cb93563feda..00000000000
--- a/board/timll/devkit3250/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DEVKIT3250 BOARD
-M: Vladimir Zapolskiy <vz@mleia.com>
-S: Maintained
-F: board/timll/devkit3250/
-F: include/configs/devkit3250.h
-F: configs/devkit3250_defconfig
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
deleted file mode 100644
index 056813995eb..00000000000
--- a/board/timll/devkit3250/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
-# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
-
-obj-y := devkit3250.o
-obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
deleted file mode 100644
index a4b963d463a..00000000000
--- a/board/timll/devkit3250/devkit3250.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Embest/Timll DevKit3250 board support
- *
- * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-#include <asm/arch/wdt.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
-
-void reset_periph(void)
-{
- /* This function resets peripherals by triggering RESOUT_N */
- setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
- udelay(300);
-
- writel(0, &wdt->mctrl);
- clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
-
- /* Such a long delay is needed to initialize SMSC phy */
- udelay(10000);
-}
-
-int board_early_init_f(void)
-{
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
- lpc32xx_i2c_init(1);
- lpc32xx_i2c_init(2);
- lpc32xx_ssp_init();
- lpc32xx_mac_init();
-
- /*
- * nWP may be controlled by GPO19, but unpopulated by default R23
- * makes no sense to configure this GPIO level, nWP is always high
- */
- lpc32xx_slc_nand_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_SYS_FLASH_CFI
- /* Use 16-bit memory interface for NOR Flash */
- emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
-
- /* Change the NOR timings to optimum value to get maximum bandwidth */
- emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
- emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
- emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
- emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
- emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
- emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
-#endif
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
-
- return 0;
-}
diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c
deleted file mode 100644
index 47af78ae0b1..00000000000
--- a/board/timll/devkit3250/devkit3250_spl.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Timll DevKit3250 board support, SPL board configuration
- *
- * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-#include <asm/arch-lpc32xx/gpio.h>
-#include <spl.h>
-
-static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-/*
- * SDRAM K4S561632N-LC60 settings are selected in assumption that
- * SDRAM clock may be set up to 166 MHz, however at the moment
- * it is 104 MHz. Most delay values are converted to be a multiple of
- * base clock, and precise pinned values are not needed here.
- */
-struct emc_dram_settings dram_64mb = {
- .cmddelay = 0x0001C000,
- .config0 = 0x00005682,
- .rascas0 = 0x00000302,
- .rdconfig = 0x00000011, /* undocumented but crucial value */
-
- .trp = 83333333,
- .tras = 23809524,
- .tsrex = 12500000,
- .twr = 83000000, /* tWR = tRDL = 2 CLK */
- .trc = 15384616,
- .trfc = 15384616,
- .txsr = 12500000,
- .trrd = 1,
- .tmrd = 1,
- .tcdlr = 0,
-
- .refresh = 130000, /* 800 clock cycles */
-
- .mode = 0x00018000,
- .emode = 0x02000000,
-};
-
-void spl_board_init(void)
-{
- /* First of all silence buzzer controlled by GPO_20 */
- writel((1 << 20), &gpio->p3_outp_clr);
-
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
- preloader_console_init();
-
- ddr_init(&dram_64mb);
-
- /*
- * NAND initialization is done by nand_init(),
- * here just enable NAND SLC clocks
- */
- lpc32xx_slc_nand_init();
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_NAND;
-}
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
deleted file mode 100644
index b739f27803b..00000000000
--- a/configs/devkit3250_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_LPC32XX=y
-CONFIG_SYS_TEXT_BASE=0x83F00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_NAND=y
-CONFIG_NAND_LPC32XX_SLC=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=31
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_LPC32XX_SSP=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
deleted file mode 100644
index 2f8c655b2cc..00000000000
--- a/include/configs/devkit3250.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Embest/Timll DevKit3250 board configuration file
- *
- * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef __CONFIG_DEVKIT3250_H__
-#define __CONFIG_DEVKIT3250_H__
-
-/* SoC and board defines */
-#include <linux/sizes.h>
-#include <asm/arch/cpu.h>
-
-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
-
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * Memory configurations
- */
-#define CONFIG_SYS_MALLOC_LEN SZ_1M
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_64M
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
- - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
-
-/*
- * DMA
- */
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DMA_LPC32XX
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_LPC32XX
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/*
- * GPIO
- */
-#define CONFIG_LPC32XX_GPIO
-
-/*
- * SSP/SPI
- */
-#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
-
-/*
- * Ethernet
- */
-#define CONFIG_RMII
-#define CONFIG_PHY_SMSC
-#define CONFIG_LPC32XX_ETH
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-/*
- * NOR Flash
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
-#define CONFIG_SYS_FLASH_SIZE SZ_4M
-
-/*
- * NAND controller
- */
-#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-
-/*
- * NAND chip timings
- */
-#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
-#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
-#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
-#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
-#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
-#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
-#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
-#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
-#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI_LPC32XX
-#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
-
-/*
- * U-Boot General Configurations
- */
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * Pass open firmware flat tree
- */
-
-/*
- * Environment
- */
-#define CONFIG_ENV_SIZE SZ_128K
-#define CONFIG_ENV_OFFSET 0x000A0000
-
-#define CONFIG_BOOTCOMMAND \
- "dhcp; " \
- "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
- "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
- "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
- "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
- "bootm ${loadaddr} - ${dtbaddr}"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=no\0" \
- "ethaddr=00:01:90:00:C0:81\0" \
- "dtbaddr=0x81000000\0" \
- "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
- "tftpdir=vladimir/oe/devkit3250\0" \
- "userargs=oops=panic\0"
-
-/*
- * U-Boot Commands
- */
-
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x80008000
-
-/*
- * SPL specific defines
- */
-/* SPL will be executed at offset 0 */
-#define CONFIG_SPL_TEXT_BASE 0x00000000
-
-/* SPL will use SRAM as stack */
-#define CONFIG_SPL_STACK 0x0000FFF8
-
-/* Use the framework and generic lib */
-
-/* SPL will use serial */
-
-/* SPL loads an image from NAND */
-#define CONFIG_SPL_NAND_RAW_ONLY
-#define CONFIG_SPL_NAND_DRIVERS
-
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SOFTECC
-
-#define CONFIG_SPL_MAX_SIZE 0x20000
-#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
-
-/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-
-/* See common/spl/spl.c spl_set_header_raw_uboot() */
-#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
-
-/*
- * Include SoC specific configuration
- */
-#include <asm/arch/config.h>
-
-#endif /* __CONFIG_DEVKIT3250_H__*/
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 15/93] arm: Remove pcm051_rev3 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (13 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 14/93] arm: Remove devkit3250 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 16/93] arm: Remove ds109 board Simon Glass
` (82 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/phytec/pcm051/Kconfig | 15 --
board/phytec/pcm051/MAINTAINERS | 7 -
board/phytec/pcm051/Makefile | 11 --
board/phytec/pcm051/board.c | 256 --------------------------------
board/phytec/pcm051/board.h | 24 ---
board/phytec/pcm051/mux.c | 127 ----------------
configs/pcm051_rev1_defconfig | 58 --------
configs/pcm051_rev3_defconfig | 58 --------
include/configs/pcm051.h | 137 -----------------
10 files changed, 694 deletions(-)
delete mode 100644 board/phytec/pcm051/Kconfig
delete mode 100644 board/phytec/pcm051/MAINTAINERS
delete mode 100644 board/phytec/pcm051/Makefile
delete mode 100644 board/phytec/pcm051/board.c
delete mode 100644 board/phytec/pcm051/board.h
delete mode 100644 board/phytec/pcm051/mux.c
delete mode 100644 configs/pcm051_rev1_defconfig
delete mode 100644 configs/pcm051_rev3_defconfig
delete mode 100644 include/configs/pcm051.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 54ec8243084..c111d42a38f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1523,7 +1523,6 @@ source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
-source "board/phytec/pcm051/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig
deleted file mode 100644
index 2cc0d8872d7..00000000000
--- a/board/phytec/pcm051/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PCM051
-
-config SYS_BOARD
- default "pcm051"
-
-config SYS_VENDOR
- default "phytec"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "pcm051"
-
-endif
diff --git a/board/phytec/pcm051/MAINTAINERS b/board/phytec/pcm051/MAINTAINERS
deleted file mode 100644
index 18ea636a83f..00000000000
--- a/board/phytec/pcm051/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PCM051 BOARD
-M: Lars Poeschel <poeschel@lemonage.de>
-S: Maintained
-F: board/phytec/pcm051/
-F: include/configs/pcm051.h
-F: configs/pcm051_rev1_defconfig
-F: configs/pcm051_rev3_defconfig
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
deleted file mode 100644
index ff6f8b42216..00000000000
--- a/board/phytec/pcm051/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifdef CONFIG_SPL_BUILD
-obj-y += mux.o
-endif
-
-obj-y += board.o
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
deleted file mode 100644
index e720fdc0d92..00000000000
--- a/board/phytec/pcm051/board.c
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- */
-
-#include <common.h>
-#include <environment.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* MII mode defines */
-#define RMII_RGMII2_MODE_ENABLE 0x49
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifdef CONFIG_SPL_BUILD
-
-/* DDR RAM defines */
-#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
- DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr;
-}
-
-#ifdef CONFIG_REV1
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
- .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41J256M8HX15E_RD_DQS,
- .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
- .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
- .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41J256M8HX15E_RATIO,
- .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J256M8HX15E_RATIO,
- .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J256M8HX15E_RATIO,
- .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
- .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
- .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
- .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
- .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
- .zq_config = MT41J256M8HX15E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
- config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#else
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
- config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- /* Initalize the board header */
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- enable_board_pin_mux();
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-#if defined(CONFIG_DRIVER_TI_CPSW) || \
- (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
-#ifdef CONFIG_DRIVER_TI_CPSW
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- else
- goto try_usbether;
- }
-
- writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-try_usbether:
-#endif
-
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
- rv = usb_eth_initialize(bis);
- if (rv < 0)
- printf("Error %d registering USB_ETHER\n", rv);
- else
- n += rv;
-#endif
- return n;
-}
-#endif
diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h
deleted file mode 100644
index 3366e51c856..00000000000
--- a/board/phytec/pcm051/board.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * Phytec phyCORE-AM335x (pcm051) boards information header
- *
- * Copyright (C) 2013, Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(void);
-void enable_cbmux_pin_mux(void);
-#endif
diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c
deleted file mode 100644
index 6e9c3d257cc..00000000000
--- a/board/phytec/pcm051/mux.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-#ifdef CONFIG_MMC
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-#endif
-
-#ifdef CONFIG_I2C
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-#endif
-
-#ifdef CONFIG_SPI
-static struct module_pin_mux spi0_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
- {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
- {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
- {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
- {-1},
-};
-#endif
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
- {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
- {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
- {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
- {-1},
-};
-
-static struct module_pin_mux cbmux_pin_mux[] = {
- {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
- {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
- {-1},
-};
-
-#ifdef CONFIG_NAND
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-#endif
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux()
-{
- configure_module_pin_mux(rmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(cbmux_pin_mux);
-#ifdef CONFIG_NAND
- configure_module_pin_mux(nand_pin_mux);
-#endif
-#ifdef CONFIG_SPI
- configure_module_pin_mux(spi0_pin_mux);
-#endif
-}
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
deleted file mode 100644
index 0be0caa8262..00000000000
--- a/configs/pcm051_rev1_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_PCM051=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="REV1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETHER=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
deleted file mode 100644
index 33e8225e536..00000000000
--- a/configs/pcm051_rev3_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_PCM051=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="REV3"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETHER=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
deleted file mode 100644
index 5381ed1f453..00000000000
--- a/include/configs/pcm051.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * pcm051.h
- *
- * Phytec phyCORE-AM335x (pcm051) boards information header
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_PCM051_H
-#define __CONFIG_PCM051_H
-
-#include <configs/ti_am335x_common.h>
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
-
-/* set to negative value for no autoboot */
-#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "setenv mmcdev " #instance"; "\
- "setenv bootpart " #instance":2 ; "\
- "run mmcboot\0"
-
-#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel "=" \
- "run nandboot\0"
-
-#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(LEGACY_MMC, legacy_mmc, 0) \
- func(MMC, mmc, 1) \
- func(LEGACY_MMC, legacy_mmc, 1) \
- func(NAND, nand, 0)
-
-#define CONFIG_BOOTCOMMAND \
- "run distro_bootcmd"
-
-#include <config_distro_bootcmd.h>
-
-#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- DEFAULT_MMC_TI_ARGS \
- "bootfile=uImage\0" \
- "fdtfile=am335x-wega-rdk.dtb\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
- "ramrootfstype=ext2\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "ramargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
- "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run args_mmc; " \
- "bootm ${loadaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootm ${loadaddr}\0" \
- BOOTENV
-
-/* Clock Defines */
-#define V_OSCK 25000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-/*
- * memtest works on 8 MB in DRAM after skipping 32MB from
- * start addr of ram disk
- */
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (64 << 20))
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
- + (8 * 1024 * 1024))
-
-#define CONFIG_SF_DEFAULT_SPEED 24000000
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-
-/* I2C Configuration */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
-4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
-
-/* CPU */
-
-#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#endif
-
-/*
- * USB configuration
- */
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-#define CONFIG_PHY_SMSC
-
-#endif /* ! __CONFIG_PCM051_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 16/93] arm: Remove ds109 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (14 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 15/93] arm: Remove pcm051_rev3 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 17/93] arm: Remove pcm058 board Simon Glass
` (81 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/Synology/ds109/Kconfig | 12 --
board/Synology/ds109/MAINTAINERS | 6 -
board/Synology/ds109/Makefile | 7 --
board/Synology/ds109/ds109.c | 176 ------------------------------
board/Synology/ds109/ds109.h | 43 --------
board/Synology/ds109/kwbimage.cfg | 150 -------------------------
board/Synology/ds109/openocd.cfg | 115 -------------------
configs/ds109_defconfig | 38 -------
include/configs/ds109.h | 86 ---------------
10 files changed, 634 deletions(-)
delete mode 100644 board/Synology/ds109/Kconfig
delete mode 100644 board/Synology/ds109/MAINTAINERS
delete mode 100644 board/Synology/ds109/Makefile
delete mode 100644 board/Synology/ds109/ds109.c
delete mode 100644 board/Synology/ds109/ds109.h
delete mode 100644 board/Synology/ds109/kwbimage.cfg
delete mode 100644 board/Synology/ds109/openocd.cfg
delete mode 100644 configs/ds109_defconfig
delete mode 100644 include/configs/ds109.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 00ed62591ea..11491f61b8a 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -72,7 +72,6 @@ config SYS_SOC
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
-source "board/Synology/ds109/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig
deleted file mode 100644
index a7c75ae368f..00000000000
--- a/board/Synology/ds109/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DS109
-
-config SYS_BOARD
- default "ds109"
-
-config SYS_VENDOR
- default "Synology"
-
-config SYS_CONFIG_NAME
- default "ds109"
-
-endif
diff --git a/board/Synology/ds109/MAINTAINERS b/board/Synology/ds109/MAINTAINERS
deleted file mode 100644
index 8783fdb1f20..00000000000
--- a/board/Synology/ds109/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DS109 BOARD
-M: Walter Schweizer <swwa@users.sourceforge.net>
-S: Maintained
-F: board/Synology/ds109
-F: configs/ds109_defconfig
-F: include/configs/ds109.h
diff --git a/board/Synology/ds109/Makefile b/board/Synology/ds109/Makefile
deleted file mode 100644
index 9d103a61bcd..00000000000
--- a/board/Synology/ds109/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-
-obj-y := ds109.o
diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c
deleted file mode 100644
index 1f2fce989c9..00000000000
--- a/board/Synology/ds109/ds109.c
+++ /dev/null
@@ -1,176 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009-2012
- * Wojciech Dubowik <wojciech.dubowik@neratec.com>
- * Luka Perkov <luka@openwrt.org>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/setup.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "ds109.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(DS109_OE_VAL_LOW,
- DS109_OE_VAL_HIGH,
- DS109_OE_LOW, DS109_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn, /* SPI Flash */
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_GPIO,
- MPP5_GPO,
- MPP6_SYSRST_OUTn, /* Reset signal */
- MPP7_GPO,
- MPP8_TW_SDA, /* I2C */
- MPP9_TW_SCK, /* I2C */
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO,
- MPP13_UART1_TXD,
- MPP14_UART1_RXD,
- MPP15_GPIO,
- MPP16_GPIO,
- MPP17_GPIO,
- MPP18_GPO,
- MPP19_GPO,
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP22_GPIO, /* HDD2 FAIL LED */
- MPP23_GPIO, /* HDD1 FAIL LED */
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO, /* HDD2 */
- MPP32_GPIO, /* FAN A */
- MPP33_GPIO, /* FAN B */
- MPP34_GPIO, /* FAN C */
- MPP35_GPIO, /* FAN SENSE */
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-/* Synology reset uses UART */
-#include <ns16550.h>
-#define SOFTWARE_SHUTDOWN 0x31
-#define SOFTWARE_REBOOT 0x43
-#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
-void reset_misc(void)
-{
- int b_d;
- printf("Synology reset...");
- udelay(50000);
-
- b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
- CONFIG_SYS_NS16550_CLK, 9600);
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
-}
-
-/* Support old kernels */
-void setup_board_tags(struct tag **in_params)
-{
- unsigned int boardId;
- struct tag *params;
- struct tag_mv_uboot *t;
- int i;
-
- printf("Synology board tags...");
- params = *in_params;
- t = (struct tag_mv_uboot *)¶ms->u;
-
- t->uboot_version = VER_NUM;
-
- boardId = SYNO_DS109_ID;
- t->uboot_version |= boardId;
-
- t->tclk = CONFIG_SYS_TCLK;
- t->sysclk = CONFIG_SYS_TCLK*2;
-
- t->isusbhost = 1;
- for (i = 0; i < 4; i++) {
- memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
- t->mtu[i] = 0;
- }
-
- params->hdr.tag = ATAG_MV_UBOOT;
- params->hdr.size = tag_size(tag_mv_uboot);
- params = tag_next(params);
- *in_params = params;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
- printf("Error: 88E1116 could not read PHY dev address\n");
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Synology/ds109/ds109.h b/board/Synology/ds109/ds109.h
deleted file mode 100644
index cc6ef991f39..00000000000
--- a/board/Synology/ds109/ds109.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009-2012
- * Wojciech Dubowik <wojciech.dubowik@neratec.com>
- * Luka Perkov <luka@openwrt.org>
- */
-
-#ifndef __DS109_H
-#define __DS109_H
-
-#define DS109_OE_LOW (0)
-#define DS109_OE_HIGH (0)
-#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23))
-#define DS109_OE_VAL_HIGH ((1 << 1)|1)
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_MAC_CTRL2_REG 21
-
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-/* Marvell uboot parameters */
-#define ATAG_MV_UBOOT 0x41000403
-#define VER_NUM 0x03040400 /* 3.4.4 */
-#define BOARD_ID_BASE 0x0
-#define SYNO_DS109_ID (BOARD_ID_BASE+0x15)
-
-struct tag_mv_uboot {
- u32 uboot_version;
- u32 tclk;
- u32 sysclk;
- u32 isusbhost;
- char macaddr[4][6];
- u16 mtu[4];
- u32 fw_image_base;
- u32 fw_image_size;
-};
-
-#endif /* __DS109_H */
diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg
deleted file mode 100644
index 8f6e7051379..00000000000
--- a/board/Synology/ds109/kwbimage.cfg
+++ /dev/null
@@ -1,150 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011
-# Jason Cooper <u-boot@lakedaemon.net>
-#
-# Based on work by:
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0/1 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-DATA 0xFFD20134 0xbbbbbbbb
-DATA 0xFFD20138 0x00bbbbbb
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000000d # DDR Address Control
-# bit1-0: 01, Cs0width=x8
-# bit3-2: 10, Cs0size=1Gb
-# bit5-4: 01, Cs1width=x8
-# bit7-6: 10, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000042 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-
-DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Synology/ds109/openocd.cfg b/board/Synology/ds109/openocd.cfg
deleted file mode 100644
index baa512aef24..00000000000
--- a/board/Synology/ds109/openocd.cfg
+++ /dev/null
@@ -1,115 +0,0 @@
-# Synology DS109
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
-
-adapter_khz 2000
-
-# length of reset signal: [ms]
-adapter_nsrst_assert_width 1000
-
-# don't talk to JTAG after reset for: [ms]
-adapter_nsrst_delay 200
-
-source [find target/feroceon.cfg]
-
-reset_config trst_and_srst srst_nogate
-
-proc ds109_init { } {
-
- # We need to assert DBGRQ while holding nSRST down.
- # However DBGACK will be set only when nSRST is released.
- # Furthermore, the JTAG interface doesn't respond at all when
- # the CPU is in the WFI (wait for interrupts) state, so it is
- # possible that initial tap examination failed. So let's
- # re-examine the target again here when nSRST is asserted which
- # should then succeed.
- jtag_reset 0 1
- feroceon.cpu arp_examine
- halt 0
- jtag_reset 0 0
- wait_halt
- #reset run
- #soft_reset_halt
-
- arm mcr 15 0 0 1 0 0x00052078
-
- mww 0xD00100e0 0x1b1b1b9b ;#
- mww 0xD0020134 0xbbbbbbbb ;#
- mww 0xD0020138 0x00bbbbbb ;#
- mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
- mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
- mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
- mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
- mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
- mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
- mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
- mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
- mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
- mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
- mww 0xD0001428 0x00085520 ;# Dunit Control High Register
- mww 0xD000147c 0x00008552 ;# Dunit Control High Register
- mww 0xD0001500 0x00000000 ;#
- mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register
- mww 0xD0001508 0x10000000 ;# CS1n Base Register
- mww 0xD000150C 0x00000000 ;# CS1n Size Register
- mww 0xD0001510 0x20000000 ;#
- mww 0xD0001514 0x00000000 ;# CS2n Size Register
- mww 0xD000151C 0x00000000 ;# CS3n Size Register
- mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
- mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
- mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
- mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
- mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
-
- mww 0xD0010000 0x01111111 ;# MPP 0 to 7
- mww 0xD0010004 0x11113322 ;# MPP 8 to 15
- mww 0xD0010008 0x00001111 ;# MPP 16 to 23
-}
-
-proc ds109_load { } {
- # load u-Boot into RAM and execute it
- ds109_init
- load_image u-boot.bin 0x00600000 bin
- resume 0x00600000
-}
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
deleted file mode 100644
index 23f1886a249..00000000000
--- a/configs/ds109_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_DS109=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MVTWSI=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_FS_EXT4=y
diff --git a/include/configs/ds109.h b/include/configs/ds109.h
deleted file mode 100644
index c06f0058deb..00000000000
--- a/include/configs/ds109.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
- *
- * Based on work by:
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#ifndef _CONFIG_DS109_H
-#define _CONFIG_DS109_H
-
-/* Provide the MACH_TYPE value that the vendor kernel requires. */
-#define CONFIG_MACH_TYPE 527
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-
-/*
- * Commands configuration
- */
-#define CONFIG_CMD_EXT2
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-plug-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
-#endif
-
-#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI 1
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
-#endif
-
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_ADDR 0x3d0000
-#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
- "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "x_bootcmd_ethernet=ping 192.168.1.2\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
- "x_bootargs=console=ttyS0,115200\0" \
- "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \
- "ipaddr=192.168.1.5\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */
-#define CONFIG_PHY_BASE_ADR 8
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#endif /* _CONFIG_DS109_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 17/93] arm: Remove pcm058 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (15 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 16/93] arm: Remove ds109 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 18/93] arm: Remove am335x_shc_ict board Simon Glass
` (80 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/phytec/pcm058/Kconfig | 12 -
board/phytec/pcm058/MAINTAINERS | 6 -
board/phytec/pcm058/Makefile | 7 -
board/phytec/pcm058/README | 35 --
board/phytec/pcm058/pcm058.c | 568 --------------------------------
configs/pcm058_defconfig | 57 ----
include/configs/pcm058.h | 98 ------
8 files changed, 784 deletions(-)
delete mode 100644 board/phytec/pcm058/Kconfig
delete mode 100644 board/phytec/pcm058/MAINTAINERS
delete mode 100644 board/phytec/pcm058/Makefile
delete mode 100644 board/phytec/pcm058/README
delete mode 100644 board/phytec/pcm058/pcm058.c
delete mode 100644 configs/pcm058_defconfig
delete mode 100644 include/configs/pcm058.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 2b96c55b61b..93c8d46c600 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -548,7 +548,6 @@ source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
-source "board/phytec/pcm058/Kconfig"
source "board/phytec/pfla02/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
diff --git a/board/phytec/pcm058/Kconfig b/board/phytec/pcm058/Kconfig
deleted file mode 100644
index d099275d48e..00000000000
--- a/board/phytec/pcm058/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PCM058
-
-config SYS_BOARD
- default "pcm058"
-
-config SYS_VENDOR
- default "phytec"
-
-config SYS_CONFIG_NAME
- default "pcm058"
-
-endif
diff --git a/board/phytec/pcm058/MAINTAINERS b/board/phytec/pcm058/MAINTAINERS
deleted file mode 100644
index b0ca40277f0..00000000000
--- a/board/phytec/pcm058/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PHYTEC PHYBOARD MIRA
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/phytec/pcm058/
-F: include/configs/pcm058.h
-F: configs/pcm058_defconfig
diff --git a/board/phytec/pcm058/Makefile b/board/phytec/pcm058/Makefile
deleted file mode 100644
index 75b503d95d4..00000000000
--- a/board/phytec/pcm058/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := pcm058.o
diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README
deleted file mode 100644
index 33271356451..00000000000
--- a/board/phytec/pcm058/README
+++ /dev/null
@@ -1,35 +0,0 @@
-Board information
------------------
-
-The SBC produced by Phytec has a SOM based on a i.MX6Q.
-The SOM is sold in two versions, with eMMC or with NAND. Support
-here is for the SOM with NAND.
-The evaluation board "phyBoard-Mira" is thought to be used
-together with the SOM.
-
-More information on the board can be found on manufacturer's
-website:
-
-http://www.phytec.de/produkt/single-board-computer/phyboard-mira/
-http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf
-
-Building U-Boot
--------------------------------
-
-$ make pcm058_defconfig
-$ make
-
-This generates the artifacts SPL and u-boot.img.
-The SOM can boot from NAND or from SD-Card, having the SPI-NOR
-as second option.
-The dip switch "DIP-1" on the board let choose between
-NAND and SD.
-
-DIP-1 set to off: Boot first from NAND, then try SPI
-DIP-1 set to on: Boot first from SD, then try SPI
-
-The bootloader was tested with DIP-1 set to on. If a SD-card
-is present, then the RBL tries to load SPL from the SD Card, if not,
-RBL loads from SPI-NOR. The SPL tries then to load from the same
-device where SPL was loaded (SD or SPI). Booting from NAND is
-not supported.
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
deleted file mode 100644
index 5ecaf00be7b..00000000000
--- a/board/phytec/pcm058/pcm058.c
+++ /dev/null
@@ -1,568 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
- */
-
-/*
- * Please note: there are two version of the board
- * one with NAND and the other with eMMC.
- * Both NAND and eMMC cannot be set because they share the
- * same pins (SD4)
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <mmc.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <nand.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/sections.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
-#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31)
-#define USER_LED IMX_GPIO_NR(1, 4)
-#define IMX6Q_DRIVE_STRENGTH 0x30
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-void board_turn_off_led(void)
-{
- gpio_direction_output(USER_LED, 0);
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#ifdef CONFIG_CMD_NAND
-/* NAND */
-static iomux_v3_cfg_t const nfc_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
-};
-#endif
-
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
- {.esdhc_base = USDHC1_BASE_ADDR,
- .max_bus_width = 4},
-#ifndef CONFIG_CMD_NAND
- {USDHC4_BASE_ADDR},
-#endif
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-#endif
-
-int board_mmc_get_env_dev(int devno)
-{
- return devno - 1;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- int ret;
- int i;
-
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
-#ifndef CONFIG_CMD_NAND
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
-#endif
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-#else
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x2 SD2
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[0].max_bus_width = 4;
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- }
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
- gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
- mdelay(10);
- gpio_set_value(ENET_PHY_RESET_GPIO, 1);
- mdelay(30);
-}
-
-static void setup_spi(void)
-{
- gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
- gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
-
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-
- enable_spi_clk(true, 0);
-}
-
-#ifdef CONFIG_CMD_NAND
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-
- /* gate ENFC_CLK_ROOT clock first,before clk source switch */
- clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* config gpmi and bch clock to 100 MHz */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
- /* enable ENFC_CLK_ROOT clock */
- setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- if (bus != 0 || (cs != 0))
- return -EINVAL;
-
- return IMX_GPIO_NR(3, 19);
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
-
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
-
-#ifdef CONFIG_CMD_NAND
- setup_gpmi_nand();
-#endif
- return 0;
-}
-
-
-#ifdef CONFIG_CMD_BMODE
-/*
- * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
- * see Table 8-11 and Table 5-9
- * BOOT_CFG1[7] = 1 (boot from NAND)
- * BOOT_CFG1[5] = 0 - raw NAND
- * BOOT_CFG1[4] = 0 - default pad settings
- * BOOT_CFG1[3:2] = 00 - devices = 1
- * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
- * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
- * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
- * BOOT_CFG2[0] = 0 - Reset time 12ms
- */
-static const struct boot_mode board_boot_modes[] = {
- /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
- {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
- {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#include <linux/libfdt.h>
-
-static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00000030,
- .dram_sdclk_1 = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_reset = 0x00000030,
- .dram_sdcke0 = 0x00000030,
- .dram_sdcke1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00000030,
- .dram_sdodt1 = 0x00000030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_dqm2 = 0x00000030,
- .dram_dqm3 = 0x00000030,
- .dram_dqm4 = 0x00000030,
- .dram_dqm5 = 0x00000030,
- .dram_dqm6 = 0x00000030,
- .dram_dqm7 = 0x00000030,
-};
-
-static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6Q_DRIVE_STRENGTH,
- .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b1ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b2ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b3ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b4ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b5ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b6ds = IMX6Q_DRIVE_STRENGTH,
- .grp_b7ds = IMX6Q_DRIVE_STRENGTH,
-};
-
-static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00140014,
- .p0_mpwldectrl1 = 0x000A0015,
- .p1_mpwldectrl0 = 0x000A001E,
- .p1_mpwldectrl1 = 0x000A0015,
- .p0_mpdgctrl0 = 0x43080314,
- .p0_mpdgctrl1 = 0x02680300,
- .p1_mpdgctrl0 = 0x430C0318,
- .p1_mpdgctrl1 = 0x03000254,
- .p0_mprddlctl = 0x3A323234,
- .p1_mprddlctl = 0x3E3C3242,
- .p0_mpwrdlctl = 0x2A2E3632,
- .p1_mpwrdlctl = 0x3C323E34,
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 1,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
- spl_boot_list[0] = spl_boot_device();
- printf("Boot device %x\n", spl_boot_list[0]);
- switch (spl_boot_list[0]) {
- case BOOT_DEVICE_SPI:
- spl_boot_list[1] = BOOT_DEVICE_UART;
- break;
- case BOOT_DEVICE_MMC1:
- spl_boot_list[1] = BOOT_DEVICE_SPI;
- spl_boot_list[2] = BOOT_DEVICE_UART;
- break;
- default:
- printf("Boot device %x\n", spl_boot_list[0]);
- }
-}
-
-void board_init_f(ulong dummy)
-{
-#ifdef CONFIG_CMD_NAND
- /* Enable NAND */
- setup_gpmi_nand();
-#endif
-
- /* setup clock gating */
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- /* setup AXI */
- gpr_init();
-
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- setup_spi();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
deleted file mode 100644
index 66ee9ed38a2..00000000000
--- a/configs/pcm058_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PCM058=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
deleted file mode 100644
index 49048c163fd..00000000000
--- a/include/configs/pcm058.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- */
-
-
-#ifndef __PCM058_CONFIG_H
-#define __PCM058_CONFIG_H
-
-#ifdef CONFIG_SPL
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#include "imx6_spl.h"
-#endif
-
-#include "mx6_common.h"
-
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
-/* Serial */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONSOLE_DEV "ttymxc1"
-
-#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-
-/* Early setup */
-
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
-/* Ethernet */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 3
-
-/* SPI Flash */
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 20000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#ifndef CONFIG_SPL_BUILD
-/* Enable NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#endif
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* Filesystem support */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_OFFSET (1024 * SZ_1K)
-#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (0x1E0000)
-#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
-#endif
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 18/93] arm: Remove am335x_shc_ict board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (16 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 17/93] arm: Remove pcm058 board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:52 ` [U-Boot] [PATCH 19/93] arm: Remove vining_2000 board Simon Glass
` (79 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/bosch/shc/Kconfig | 87 ---
board/bosch/shc/MAINTAINERS | 11 -
board/bosch/shc/Makefile | 8 -
board/bosch/shc/README | 114 ----
board/bosch/shc/board.c | 647 ---------------------
board/bosch/shc/board.h | 186 ------
board/bosch/shc/mux.c | 260 ---------
configs/am335x_shc_defconfig | 46 --
configs/am335x_shc_ict_defconfig | 47 --
configs/am335x_shc_netboot_defconfig | 48 --
configs/am335x_shc_prompt_defconfig | 45 --
configs/am335x_shc_sdboot_defconfig | 47 --
configs/am335x_shc_sdboot_prompt_defconfig | 47 --
include/configs/am335x_shc.h | 263 ---------
15 files changed, 1857 deletions(-)
delete mode 100644 board/bosch/shc/Kconfig
delete mode 100644 board/bosch/shc/MAINTAINERS
delete mode 100644 board/bosch/shc/Makefile
delete mode 100644 board/bosch/shc/README
delete mode 100644 board/bosch/shc/board.c
delete mode 100644 board/bosch/shc/board.h
delete mode 100644 board/bosch/shc/mux.c
delete mode 100644 configs/am335x_shc_defconfig
delete mode 100644 configs/am335x_shc_ict_defconfig
delete mode 100644 configs/am335x_shc_netboot_defconfig
delete mode 100644 configs/am335x_shc_prompt_defconfig
delete mode 100644 configs/am335x_shc_sdboot_defconfig
delete mode 100644 configs/am335x_shc_sdboot_prompt_defconfig
delete mode 100644 include/configs/am335x_shc.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c111d42a38f..42e3fcb5e1a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1487,7 +1487,6 @@ source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/mach-imx/Kconfig"
-source "board/bosch/shc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig
deleted file mode 100644
index e0e56e6bfdc..00000000000
--- a/board/bosch/shc/Kconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-if TARGET_AM335X_SHC
-
-config SYS_BOARD
- default "shc"
-
-config SYS_VENDOR
- default "bosch"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "am335x_shc"
-
-choice
- prompt "enable different boot versions for the shc board"
- default SHC_EMMC
- help
- Select the boot version of the shc board.
-
-config SHC_EMMC
- bool "enable eMMC"
- help
- enable here the eMMC functionality on the bosch shc board.
-
-config SHC_ICT
- bool "enable ICT"
- help
- enable here the ICT functionality on the bosch shc board
-
-config SHC_NETBOOT
- bool "enable NETBOOT"
- help
- enable here the NETBOOT functionality on the bosch shc board
-
-config SHC_SDBOOT
- bool "enable SDBOOT"
- help
- enable here the SDBOOT functionality on the bosch shc board
-
-endchoice
-
-choice
- prompt "enable different board versions for the shc board"
- default C3_SAMPLE
- help
- Select the board version of the shc board.
-
-config B_SAMPLE
- bool "B Sample board version"
- help
- activate, if you want to build for the B sample version
- of the bosch shc board
-
-config B2_SAMPLE
- bool "B2 Sample board version"
- help
- activate, if you want to build for the B2 sample version
- of the bosch shc board
-
-config C_SAMPLE
- bool "C Sample board version"
- help
- activate, if you want to build for the C sample version
- of the bosch shc board
-
-config C2_SAMPLE
- bool "C2 Sample board version"
- help
- activate, if you want to build for the C2 sample version
- of the bosch shc board
-
-config C3_SAMPLE
- bool "C3 Sample board version"
- help
- activate, if you want to build for the C3 sample version
- of the bosch shc board
-
-config SERIES
- bool "Series board version"
- help
- activate, if you want to build for the Series version
- of the bosch shc board
-
-endchoice
-
-endif
diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS
deleted file mode 100644
index ae3c0355c07..00000000000
--- a/board/bosch/shc/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-SHC BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/bosch/shc
-F: include/configs/am335x_shc.h
-F: configs/am335x_shc_defconfig
-F: configs/am335x_shc_ict_defconfig
-F: configs/am335x_shc_netboot_defconfig
-F: configs/am335x_shc_prompt_defconfig
-F: configs/am335x_shc_sdboot_defconfig
-F: configs/am335x_shc_sdboot_prompt_defconfig
diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile
deleted file mode 100644
index 93f2df3773e..00000000000
--- a/board/bosch/shc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-obj-y := mux.o
-obj-y += board.o
diff --git a/board/bosch/shc/README b/board/bosch/shc/README
deleted file mode 100644
index 2f206e0d551..00000000000
--- a/board/bosch/shc/README
+++ /dev/null
@@ -1,114 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'am335x_shc' build.
-
-Hardware
-========
-
-AM335X based board:
-
-I2C: ready
-DRAM: 512 MiB
-Enabling the D-Cache
-MMC: OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz
-Net: cpsw
-
-Following boot options are possible:
-
-2 Jumpers:
-
-Jumper 1 Jumper 2 Bootmode
-off off eMMC boot
-on off SD boot
-off on Net boot
-
-Compiling
-=========
-
-$ make am335x_shc_defconfig
- HOSTCC scripts/basic/fixdep
- HOSTCC scripts/kconfig/conf.o
- SHIPPED scripts/kconfig/zconf.tab.c
- SHIPPED scripts/kconfig/zconf.lex.c
- SHIPPED scripts/kconfig/zconf.hash.c
- HOSTCC scripts/kconfig/zconf.tab.o
- HOSTLD scripts/kconfig/conf
-#
-# configuration written to .config
-#
-$ make -s all
-
--> now you have the MLO and the u-boot.img file, you can put
-on your SD card or eMMC.
-
-Configuring
-===========
-
-There are a lot of board versions and boot configurations, which
-can be selected through "make menuconfig"
-
-ARM architecture --->
- enable different boot versions for the shc board (enable eMMC) --->
- (X) enable eMMC
- ( ) enable ICT
- ( ) enable NETBOOT
- ( ) enable SDBOOT
-
- enable different board versions for the shc board (C3 Sample board version) --->
- ( ) B Sample board version
- ( ) B2 Sample board version
- ( ) C Sample board version
- ( ) C2 Sample board version
- (X) C3 Sample board version
- ( ) Series board version
-
-Netboot
-=======
-- see also doc/SPL/README.am335x-network
-
-- set the jumper into netboot mode
-- compile the U-boot sources with:
- make am335x_shc_netboot_defconfig
- make all
-- copy the images into your tftp boot directory
- cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin
- cp u-boot.img /tftpboot/.../u-boot-restore.img
-- power on the board, and you should get something like this:
-
-U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18)
-#### NETBOOT ####
-SHC
-MPU reference clock runs at 6 MHz
-Setting MPU clock to 594 MHz
-Enabling Spread Spectrum of 18 permille for MPU
-Trying to boot from net
-Using default environment
-
-<ethaddr> not set. Validating first E-fuse MAC
-cpsw
-cpsw Waiting for PHY auto negotiation to complete... done
-link up on port 0, speed 100, full duplex
-BOOTP broadcast 1
-BOOTP broadcast 2
-DHCP client bound to address 192.168.20.91 (258 ms)
-Using cpsw device
-TFTP from server 192.168.1.1; our IP address is 192.168.20.91
-Filename 'shc/u-boot-restore.img'.
-Load address: 0x807fffc0
-Loading: ##################
- 1.2 MiB/s
-done
-Bytes transferred = 262480 (40150 hex)
-
-
-U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200)
-
- Watchdog enabled
-I2C: ready
-DRAM: 512 MiB
-MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
-*** Warning - bad CRC, using default environment
-
-Net: cpsw
-switch to partitions #0, OK
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
deleted file mode 100644
index 1ec9a3f5ffc..00000000000
--- a/board/bosch/shc/board.c
+++ /dev/null
@@ -1,647 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * (C) Copyright 2016
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * Based on:
- * Board functions for TI AM335X based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <power/tps65217.h>
-#include <environment.h>
-#include <watchdog.h>
-#include <environment.h>
-#include "mmc.h"
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#endif
-static struct shc_eeprom __attribute__((section(".data"))) header;
-static int shc_eeprom_valid;
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return -ENODEV;
- }
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
- sizeof(header))) {
- puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header.magic != HDR_MAGIC) {
- printf("Incorrect magic number (0x%x) in EEPROM\n",
- header.magic);
- return -EIO;
- }
-
- shc_eeprom_valid = 1;
-
- return 0;
-}
-
-static void shc_request_gpio(void)
-{
- gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
- gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
- gpio_request(RESET_GPIO, "reset");
- gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
- gpio_request(WIFI_RST_GPIO, "WIFI rst");
- gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
- gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
- gpio_request(ENOC_RST_GPIO, "ENOC rst");
-#if defined CONFIG_B_SAMPLE
- gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
- gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
- gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
- gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
-#else
- gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
- gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
- gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
- gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
- gpio_request(LED_PWM_GPIO, "LED PWM");
- gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
-#endif
- gpio_request(BACK_BUTTON_GPIO, "Back button");
- gpio_request(FRONT_BUTTON_GPIO, "Front button");
-}
-
-/*
- * Function which forces all installed modules into running state for ICT
- * testing. Called by SPL.
- */
-static void __maybe_unused force_modules_running(void)
-{
- /* Wi-Fi power regulator enable - high = enabled */
- gpio_direction_output(WIFI_REGEN_GPIO, 1);
- /*
- * Wait for Wi-Fi power regulator to reach a stable voltage
- * (soft-start time, max. 350 µs)
- */
- __udelay(350);
-
- /* Wi-Fi module reset - high = running */
- gpio_direction_output(WIFI_RST_GPIO, 1);
-
- /* ZigBee reset - high = running */
- gpio_direction_output(ZIGBEE_RST_GPIO, 1);
-
- /* BidCos reset - high = running */
- gpio_direction_output(BIDCOS_RST_GPIO, 1);
-
-#if !defined(CONFIG_B_SAMPLE)
- /* Z-Wave reset - high = running */
- gpio_direction_output(Z_WAVE_RST_GPIO, 1);
-#endif
-
- /* EnOcean reset - low = running */
- gpio_direction_output(ENOC_RST_GPIO, 0);
-}
-
-/*
- * Function which forces all installed modules into reset - to be released by
- * the OS, called by SPL
- */
-static void __maybe_unused force_modules_reset(void)
-{
- /* Wi-Fi module reset - low = reset */
- gpio_direction_output(WIFI_RST_GPIO, 0);
-
- /* Wi-Fi power regulator enable - low = disabled */
- gpio_direction_output(WIFI_REGEN_GPIO, 0);
-
- /* ZigBee reset - low = reset */
- gpio_direction_output(ZIGBEE_RST_GPIO, 0);
-
- /* BidCos reset - low = reset */
- /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
-
-#if !defined(CONFIG_B_SAMPLE)
- /* Z-Wave reset - low = reset */
- gpio_direction_output(Z_WAVE_RST_GPIO, 0);
-#endif
-
- /* EnOcean reset - high = reset*/
- gpio_direction_output(ENOC_RST_GPIO, 1);
-}
-
-/*
- * Function to set the LEDs in the state "Bootloader booting"
- */
-static void __maybe_unused leds_set_booting(void)
-{
-#if defined(CONFIG_B_SAMPLE)
-
- /* Turn all red LEDs on */
- gpio_direction_output(LED_PWR_RD_GPIO, 1);
- gpio_direction_output(LED_CONN_RD_GPIO, 1);
-
-#else /* All other SHCs starting with B2-Sample */
- /* Set the PWM GPIO */
- gpio_direction_output(LED_PWM_GPIO, 1);
- /* Turn all red LEDs on */
- gpio_direction_output(LED_PWR_RD_GPIO, 1);
- gpio_direction_output(LED_LAN_RD_GPIO, 1);
- gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
-
-#endif
-}
-
-/*
- * Function to set the LEDs in the state "Bootloader error"
- */
-static void leds_set_failure(int state)
-{
-#if defined(CONFIG_B_SAMPLE)
- /* Turn all blue and green LEDs off */
- gpio_set_value(LED_PWR_BL_GPIO, 0);
- gpio_set_value(LED_PWR_GN_GPIO, 0);
- gpio_set_value(LED_CONN_BL_GPIO, 0);
- gpio_set_value(LED_CONN_GN_GPIO, 0);
-
- /* Turn all red LEDs to 'state' */
- gpio_set_value(LED_PWR_RD_GPIO, state);
- gpio_set_value(LED_CONN_RD_GPIO, state);
-
-#else /* All other SHCs starting with B2-Sample */
- /* Set the PWM GPIO */
- gpio_direction_output(LED_PWM_GPIO, 1);
-
- /* Turn all blue LEDs off */
- gpio_set_value(LED_PWR_BL_GPIO, 0);
- gpio_set_value(LED_LAN_BL_GPIO, 0);
- gpio_set_value(LED_CLOUD_BL_GPIO, 0);
-
- /* Turn all red LEDs to 'state' */
- gpio_set_value(LED_PWR_RD_GPIO, state);
- gpio_set_value(LED_LAN_RD_GPIO, state);
- gpio_set_value(LED_CLOUD_RD_GPIO, state);
-#endif
-}
-
-/*
- * Function to set the LEDs in the state "Bootloader finished"
- */
-static void leds_set_finish(void)
-{
-#if defined(CONFIG_B_SAMPLE)
- /* Turn all LEDs off */
- gpio_set_value(LED_PWR_BL_GPIO, 0);
- gpio_set_value(LED_PWR_RD_GPIO, 0);
- gpio_set_value(LED_PWR_GN_GPIO, 0);
- gpio_set_value(LED_CONN_BL_GPIO, 0);
- gpio_set_value(LED_CONN_RD_GPIO, 0);
- gpio_set_value(LED_CONN_GN_GPIO, 0);
-#else /* All other SHCs starting with B2-Sample */
- /* Turn all LEDs off */
- gpio_set_value(LED_PWR_BL_GPIO, 0);
- gpio_set_value(LED_PWR_RD_GPIO, 0);
- gpio_set_value(LED_LAN_BL_GPIO, 0);
- gpio_set_value(LED_LAN_RD_GPIO, 0);
- gpio_set_value(LED_CLOUD_BL_GPIO, 0);
- gpio_set_value(LED_CLOUD_RD_GPIO, 0);
-
- /* Turn off the PWM GPIO and mux it to EHRPWM */
- gpio_set_value(LED_PWM_GPIO, 0);
- enable_shc_board_pwm_pin_mux();
-#endif
-}
-
-static void check_button_status(void)
-{
- ulong value;
- gpio_direction_input(FRONT_BUTTON_GPIO);
- value = gpio_get_value(FRONT_BUTTON_GPIO);
-
- if (value == 0) {
- printf("front button activated !\n");
- env_set("harakiri", "1");
- }
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- return 1;
-}
-#endif
-
-static void shc_board_early_init(void)
-{
- shc_request_gpio();
-# ifdef CONFIG_SHC_ICT
- /* Force all modules into enabled state for ICT testing */
- force_modules_running();
-# else
- /* Force all modules to enter Reset state until released by the OS */
- force_modules_reset();
-# endif
- leds_set_booting();
-}
-
-#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
-#define OSC (V_OSCK/1000000)
-/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
-#define MPUPLL_N (4-1)
-/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
-#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
-
-const struct dpll_params dpll_ddr_shc = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr_shc;
-}
-
-/*
- * As we enabled downspread SSC with 1.8%, the values needed to be corrected
- * such that the 20% overshoot will not lead to too high frequencies.
- * In all cases, this is achieved by subtracting one from M (6 MHz less).
- * Example: 600 MHz CPU
- * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
- * 600 MHz - 6 MHz (1x Fref) = 594 MHz
- * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
- * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
- * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
- */
-const struct dpll_params dpll_mpu_shc_opp100 = {
- 99, MPUPLL_N, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- int sil_rev;
- int mpu_vdd;
-
- puts(BOARD_ID_STR);
-
- /*
- * Set CORE Frequency to OPP100
- * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
- */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- sil_rev = readl(&cdev->deviceid) >> 28;
- if (sil_rev < 2) {
- puts("We do not support Silicon Revisions below 2.0!\n");
- return;
- }
-
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
- if (i2c_probe(TPS65217_CHIP_PM))
- return;
-
- /*
- * Retrieve the CPU max frequency by reading the efuse
- * SHC-Default: 600 MHz
- */
- switch (dpll_mpu_opp100.m) {
- case MPUPLL_M_1000:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
- break;
- case MPUPLL_M_800:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
- break;
- case MPUPLL_M_720:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
- break;
- case MPUPLL_M_600:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
- break;
- case MPUPLL_M_300:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
- break;
- default:
- puts("Cannot determine the frequency, failing!\n");
- return;
- }
-
- if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
-
- /* Set MPU Frequency to what we detected */
- printf("MPU reference clock runs@%d MHz\n", MPUPLL_FREF);
- printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
- dpll_mpu_shc_opp100.m);
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
-
- /* Enable Spread Spectrum for this freq to be clean on EMI side */
- set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
-
- /*
- * Using the default voltages for the PMIC (TPS65217D)
- * LS1 = 1.8V (VDD_1V8)
- * LS2 = 3.3V (VDD_3V3A)
- * LDO1 = 1.8V (VIO and VRTC)
- * LDO2 = 3.3V (VDD_3V3AUX)
- */
- shc_board_early_init();
-}
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- enable_shc_board_pin_mux();
-}
-
-const struct ctrl_ioregs ioregs_evmsk = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_shc_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_shc_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
- /* Configure the DDR3 RAM */
- config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
- &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("EEPROM Content Invalid.\n");
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
- gpmc_init();
-#endif
- shc_request_gpio();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- check_button_status();
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (shc_eeprom_valid)
- if (is_valid_ethaddr(header.mac_addr))
- eth_env_set_enetaddr("ethaddr", header.mac_addr);
-#endif
-
- return 0;
-}
-#endif
-
-#ifndef CONFIG_DM_ETH
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-/*
- * This function will:
- * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
- * in the environment
- * Perform fixups to the PHY present on certain boards. We only need this
- * function in:
- * - SPL with either CPSW or USB ethernet support
- * - Full U-Boot, with either CPSW or USB ethernet
- * Build in only these cases to avoid warnings about unused variables
- * when we build an SPL that has neither option but full U-Boot will.
- */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
- defined(CONFIG_SPL_USB_ETHER)) && \
- defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
- cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-#endif
-
-#if defined(CONFIG_USB_ETHER) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
-
- rv = usb_eth_initialize(bis);
- if (rv < 0)
- printf("Error %d registering USB_ETHER\n", rv);
- else
- n += rv;
-#endif
- return n;
-}
-#endif
-
-#endif /* CONFIG_DM_ETH */
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-static void bosch_check_reset_pin(void)
-{
- if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
- printf("Resetting ...\n");
- writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
- disable_interrupts();
- reset_cpu(0);
- /*NOTREACHED*/
- }
-}
-
-static void hang_bosch(const char *cause, int code)
-{
- int lv;
-
- gpio_direction_input(RESET_GPIO);
-
- /* Enable reset pin interrupt on falling edge */
- writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
- writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
- enable_interrupts();
-
- puts(cause);
- for (;;) {
- for (lv = 0; lv < code; lv++) {
- bosch_check_reset_pin();
- leds_set_failure(1);
- __udelay(150 * 1000);
- leds_set_failure(0);
- __udelay(150 * 1000);
- }
-#if defined(BLINK_CODE)
- __udelay(300 * 1000);
-#endif
- }
-}
-
-void show_boot_progress(int val)
-{
- switch (val) {
- case BOOTSTAGE_ID_NEED_RESET:
- hang_bosch("need reset", 4);
- break;
- }
-}
-#endif
-
-void arch_preboot_os(void)
-{
- leds_set_finish();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
- ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
- if (ret)
- return ret;
-
- ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
- return ret;
-}
-#endif
diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h
deleted file mode 100644
index 997595bf42b..00000000000
--- a/board/bosch/shc/board.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * (C) Copyright 2016
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * Based on:
- * TI AM335x boards information header
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/* Definition to control the GPIOs (for LEDs and Reset) */
-#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
-
-static inline int board_is_b_sample(void)
-{
-#if defined CONFIG_B_SAMPLE
- return 1;
-#else
- return 0;
-#endif
-}
-
-static inline int board_is_c_sample(void)
-{
-#if defined CONFIG_C_SAMPLE
- return 1;
-#else
- return 0;
-#endif
-}
-
-static inline int board_is_c3_sample(void)
-{
-#if defined CONFIG_C3_SAMPLE
- return 1;
-#else
- return 0;
-#endif
-}
-
-static inline int board_is_series(void)
-{
-#if defined CONFIG_SERIES
- return 1;
-#else
- return 0;
-#endif
-}
-
-/*
- * Definitions for pinmuxing header and Board ID strings
- */
-#if defined CONFIG_B_SAMPLE
-# define BOARD_ID_STR "SHC B-Sample\n"
-#elif defined CONFIG_B2_SAMPLE
-# define BOARD_ID_STR "SHC B2-Sample\n"
-#elif defined CONFIG_C_SAMPLE
-# if defined(CONFIG_SHC_NETBOOT)
-# define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n"
-# elif defined(CONFIG_SHC_SDBOOT)
-# define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n"
-# else
-# define BOARD_ID_STR "SHC C-Sample\n"
-# endif
-#elif defined CONFIG_C2_SAMPLE
-# if defined(CONFIG_SHC_ICT)
-# define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n"
-# elif defined(CONFIG_SHC_NETBOOT)
-# define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n"
-# elif defined(CONFIG_SHC_SDBOOT)
-# define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n"
-# else
-# define BOARD_ID_STR "SHC C2-Sample\n"
-# endif
-#elif defined CONFIG_C3_SAMPLE
-# if defined(CONFIG_SHC_ICT)
-# define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n"
-# elif defined(CONFIG_SHC_NETBOOT)
-# define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n"
-# elif defined(CONFIG_SHC_SDBOOT)
-# define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n"
-# else
-# define BOARD_ID_STR "SHC C3-Sample\n"
-# endif
-#elif defined CONFIG_SERIES
-# if defined(CONFIG_SHC_ICT)
-# define BOARD_ID_STR "#### ICT ####\nSHC\n"
-# elif defined(CONFIG_SHC_NETBOOT)
-# define BOARD_ID_STR "#### NETBOOT ####\nSHC\n"
-# elif defined(CONFIG_SHC_SDBOOT)
-# define BOARD_ID_STR "#### SDBOOT ####\nSHC\n"
-# else
-# define BOARD_ID_STR "SHC\n"
-# endif
-#else
-# define BOARD_ID_STR "Unknown device!\n"
-#endif
-
-/*
- * Definitions for GPIO pin assignments
- */
-#if defined CONFIG_B_SAMPLE
-
-# define LED_PWR_BL_GPIO GPIO_TO_PIN(1, 17)
-# define LED_PWR_RD_GPIO GPIO_TO_PIN(1, 18)
-# define LED_PWR_GN_GPIO GPIO_TO_PIN(1, 19)
-# define LED_CONN_BL_GPIO GPIO_TO_PIN(0, 26)
-# define LED_CONN_RD_GPIO GPIO_TO_PIN(0, 22)
-# define LED_CONN_GN_GPIO GPIO_TO_PIN(0, 23)
-# define RESET_GPIO GPIO_TO_PIN(1, 29)
-# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16)
-# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27)
-# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18)
-# define BIDCOS_RST_GPIO GPIO_TO_PIN(0, 12)
-# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22)
-
-#else
-
-# define LED_PWR_BL_GPIO GPIO_TO_PIN(0, 22)
-# define LED_PWR_RD_GPIO GPIO_TO_PIN(0, 23)
-# define LED_LAN_BL_GPIO GPIO_TO_PIN(1, 17)
-# define LED_LAN_RD_GPIO GPIO_TO_PIN(0, 26)
-# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18)
-# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2)
-# define LED_PWM_GPIO GPIO_TO_PIN(1, 19)
-# define RESET_GPIO GPIO_TO_PIN(1, 29)
-# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16)
-# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27)
-# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18)
-# define BIDCOS_RST_GPIO GPIO_TO_PIN(1, 24)
-# define Z_WAVE_RST_GPIO GPIO_TO_PIN(1, 21)
-# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22)
-
-#endif
-
-#define BACK_BUTTON_GPIO GPIO_TO_PIN(1, 29)
-#define FRONT_BUTTON_GPIO GPIO_TO_PIN(1, 25)
-
-/* Reset is on GPIO pin 29 of GPIO bank 1 */
-#define RESET_MASK (0x1 << 29)
-
-#define HDR_MAGIC 0x43485342
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-#define HDR_REV_LEN 8
-#define HDR_SER_LEN 16
-#define HDR_ROOT_LEN 12
-#define HDR_FATC_LEN 12
-
-/*
-* SHC parameters held in On-Board I²C EEPROM device.
-*
-* Header Format
-*
-* Name Size Contents
-*-------------------------------------------------------------
-* Magic 4 0x42 0x53 0x48 0x43 [BSHC]
-*
-* Version 2 0x0100 for v1.0
-*
-* Lenght 2 The length of the complete structure, not only this header
-*
-* Eth-MAC 6 Ethernet MAC Address
-* SHC Pool: 7C:AC:B2:00:10:01 - TBD
-*
-* --- Further values follow, not important for Bootloader ---
-*/
-
-struct shc_eeprom {
- u32 magic;
- u16 version;
- u16 lenght;
- uint8_t mac_addr[HDR_ETH_ALEN];
-};
-
-void enable_uart0_pin_mux(void);
-void enable_shc_board_pin_mux(void);
-void enable_shc_board_pwm_pin_mux(void);
-
-#endif
diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c
deleted file mode 100644
index b04c5914f0d..00000000000
--- a/board/bosch/shc/mux.c
+++ /dev/null
@@ -1,260 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mux.c
- *
- * (C) Copyright 2016
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
- {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
- {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
- {-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
- {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
- {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
- {-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
- {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
- {-1},
-};
-
-static struct module_pin_mux spi1_pin_mux[] = {
- {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */
- {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */
- {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */
- {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */
- {-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
- {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
- {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
- {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
- {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
- {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */
- {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
- {-1},
-};
-
-static struct module_pin_mux mmc2_pin_mux[] = {
- {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */
- {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */
- {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */
- {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */
- {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */
- {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */
- {-1},
-};
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux gpio0_7_pin_mux[] = {
- {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */
- {-1},
-};
-
-static struct module_pin_mux jtag_pin_mux[] = {
- {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)},
- {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)},
- {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
- {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
- {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
- {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
- {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
- {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
- {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
- {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
- {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
- {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)},
- {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)},
- {-1},
-};
-
-static struct module_pin_mux gpio_pin_mux[] = {
- {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */
- {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */
- {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */
- {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */
- {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */
- {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */
- {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */
- {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */
- {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */
- {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */
- {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */
- {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */
- {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */
- {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */
- {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */
- {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */
- {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */
- {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */
- {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */
- {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */
- {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */
- {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */
- {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */
- {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */
- {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */
- {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */
- {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */
- {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */
- {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */
- {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */
- {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */
- {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */
- {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */
- {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */
- {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */
- {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */
- {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */
- {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */
- {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */
- {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */
- {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */
- {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */
- {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */
- {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */
- {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */
- {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */
- {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */
- {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */
- {-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_col), MODE(0) | RXACTIVE},
- {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
- {OFFSET(mii1_txen), MODE(0)},
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
- {OFFSET(mii1_txd3), MODE(0)},
- {OFFSET(mii1_txd2), MODE(0)},
- {OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
- {OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
- {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
- {-1},
-};
-
-static struct module_pin_mux pwm_pin_mux[] = {
- {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)},
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart1_pin_mux(void)
-{
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
- configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
-}
-
-void enable_uart4_pin_mux(void)
-{
- configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_shc_board_pwm_pin_mux(void)
-{
- configure_module_pin_mux(pwm_pin_mux);
-}
-
-void enable_shc_board_pin_mux(void)
-{
- /* Do board-specific muxes. */
- if (board_is_c3_sample() || board_is_series()) {
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(mmc1_pin_mux);
- configure_module_pin_mux(mmc2_pin_mux);
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(gpio0_7_pin_mux);
- configure_module_pin_mux(gpio_pin_mux);
- configure_module_pin_mux(uart1_pin_mux);
- configure_module_pin_mux(uart2_pin_mux);
- configure_module_pin_mux(uart4_pin_mux);
- configure_module_pin_mux(spi1_pin_mux);
- configure_module_pin_mux(jtag_pin_mux);
- } else {
- puts("Unknown board, cannot configure pinmux.");
- hang();
- }
-}
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
deleted file mode 100644
index 25e1a4f9437..00000000000
--- a/configs/am335x_shc_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
deleted file mode 100644
index 9ebfe5e7f59..00000000000
--- a/configs/am335x_shc_ict_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SHC_ICT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
deleted file mode 100644
index 064b3c355c5..00000000000
--- a/configs/am335x_shc_netboot_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SHC_NETBOOT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
deleted file mode 100644
index dce83347322..00000000000
--- a/configs/am335x_shc_prompt_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
deleted file mode 100644
index e4e6adef194..00000000000
--- a/configs/am335x_shc_sdboot_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SHC_SDBOOT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
deleted file mode 100644
index e4e6adef194..00000000000
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_SHC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SHC_SDBOOT=y
-CONFIG_SERIES=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
-CONFIG_AUTOBOOT_DELAY_STR="shc"
-CONFIG_AUTOBOOT_STOP_STR="noautoboot"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
deleted file mode 100644
index 6368872e5b5..00000000000
--- a/include/configs/am335x_shc.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2016
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * Based on:
- * am335x_evm.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#ifndef __CONFIG_AM335X_SHC_H
-#define __CONFIG_AM335X_SHC_H
-
-#include <configs/ti_am335x_common.h>
-
-/* settings we don;t want on this board */
-#undef CONFIG_CMD_SPI
-
-#define CONFIG_CMD_CACHE
-
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_TIMESTAMP
-#endif
-
-#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-/*
- * in case of SD Card or Network boot we want to have a possibility to
- * debrick the shc, therefore do not read environment from eMMC
- */
-#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#endif
-
-/*
- * Info when using boot partitions: As environment resides within first
- * 128 kB, MLO must start at 128 kB == 0x20000
- * ENV@MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1,
- * 4..7=general0..3
- */
-#define CONFIG_ENV_SIZE 0x1000 /* 4 KB */
-#define CONFIG_ENV_OFFSET 0x7000 /* 28 kB */
-
-#define CONFIG_HSMMC2_8BIT
-
-#define CONFIG_ENV_OFFSET_REDUND 0x9000 /* 36 kB */
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#ifndef CONFIG_SHC_ICT
-/*
- * In builds other than ICT, reset to retry after timeout
- * Define a timeout after which a stopped bootloader continues autoboot
- * (only works with CONFIG_RESET_TO_RETRY)
- */
-# define CONFIG_BOOT_RETRY_TIME 30
-# define CONFIG_RESET_TO_RETRY
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "kloadaddr=0x84000000\0" \
- "fdtaddr=0x85000000\0" \
- "fdt_high=0xffffffff\0" \
- "rdaddr=0x81000000\0" \
- "bootfile=uImage\0" \
- "fdtfile=am335x-shc.dtb\0" \
- "verify=no\0" \
- "serverip=10.55.152.184\0" \
- "rootpath=/srv/nfs/shc-rootfs\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=quiet\0" \
- "mmcdev=1\0" \
- "harakiri=0\0" \
- "mmcpart=2\0" \
- "active_root=root1\0" \
- "inactive_root=root2\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nfsopts=nolock\0" \
- "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
- "::off\0" \
- "ip_method=none\0" \
- "bootargs_defaults=setenv bootargs " \
- "console=${console} " \
- "${optargs}\0" \
- "mmcargs=run bootargs_defaults;" \
- "setenv bootargs ${bootargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype} ip=${ip_method}\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \
- "echo Loaded environment from ${bootenv}; " \
- "run importbootenv; " \
- "fi;\0" \
- "importbootenv=echo Importing environment variables from uEnv.txt ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \
- "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \
- "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \
- "netloaduimage=tftp ${loadaddr} ${bootfile}\0" \
- "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
- "mmcboot=echo Booting Linux from ${mmcdevice} ...; " \
- "run mmcargs; " \
- "if run loadfdt; then " \
- "echo device tree detected; " \
- "bootm ${kloadaddr} - ${fdtaddr}; " \
- "else " \
- "bootm ${kloadaddr}; " \
- "fi; \0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "run netloaduimage; " \
- "run netargs; " \
- "echo NFS path: ${serverip}:${rootpath};" \
- "if run netloadfdt; then " \
- "echo device tree detected; " \
- "bootm ${loadaddr} - ${fdtaddr}; " \
- "else " \
- "bootm ${loadaddr}; " \
- "fi; \0" \
- "emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \
- "mmcpart_gp=mmcpart gp 1 40; \0" \
- "mmcpart_enhance=mmcpart enhance 0 64; \0" \
- "mmcpart_rel_write=mmcpart rel_write 1f; \0" \
- "mmcpart_commit=mmcpart commit 1; \0" \
- "mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \
- "led_success=gpio set 22; \0" \
- "fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \
- "uenv_exec=if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
- "fi;\0" \
- "sd_setup=echo SD/MMC-Card detected on device 0; " \
- "setenv mmcdevice SD; " \
- "setenv mmcdev 0; " \
- "setenv mmcpart 2; " \
- "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \
- "emmc_setup=echo eMMC detected on device 1; " \
- "setenv mmcdevice eMMC; " \
- "setenv mmcdev 1; " \
- "run emmc_erase; " \
- "if test ${active_root} = root2; then " \
- "echo Active root is partition 6 (root2); " \
- "setenv mmcpart 6; " \
- "else " \
- "echo Active root is partition 5 (root1); " \
- "setenv mmcpart 5; " \
- "fi; " \
- "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0"
-#endif /* #ifndef CONFIG_SPL_BUILD */
-
-#if defined CONFIG_SHC_NETBOOT
-/* Network Boot */
-# define CONFIG_BOOTCOMMAND \
- "run fusecmd; " \
- "if run netboot; then " \
- "echo Booting from network; " \
- "else " \
- "echo ERROR: Cannot boot from network!; " \
- "panic; " \
- "fi; "
-
-#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */
-/* SD-Card Boot */
-# define CONFIG_BOOTCOMMAND \
- "if mmc dev 0; mmc rescan; then " \
- "run sd_setup; " \
- "else " \
- "echo ERROR: SD/MMC-Card not detected!; " \
- "panic; " \
- "fi; " \
- "if run loaduimage; then " \
- "echo Bootable SD/MMC-Card inserted, booting from it!; " \
- "run mmcboot; " \
- "else " \
- "echo ERROR: Unable to load uImage from SD/MMC-Card!; " \
- "panic; " \
- "fi; "
-
-#elif defined CONFIG_SHC_ICT
-/* ICT adapter boots only u-boot and does HW partitioning */
-# define CONFIG_BOOTCOMMAND \
- "if mmc dev 0; mmc rescan; then " \
- "run sd_setup; " \
- "else " \
- "echo ERROR: SD/MMC-Card not detected!; " \
- "panic; " \
- "fi; " \
- "run fusecmd; "
-
-#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */
-/* Regular Boot from internal eMMC */
-# define CONFIG_BOOTCOMMAND \
- "if mmc dev 1; mmc rescan; then " \
- "run emmc_setup; " \
- "else " \
- "echo ERROR: eMMC device not detected!; " \
- "panic; " \
- "fi; " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else " \
- "echo ERROR Unable to load uImage from eMMC!; " \
- "echo Performing Rollback!; " \
- "setenv _active_ ${active_root}; " \
- "setenv _inactive_ ${inactive_root}; " \
- "setenv active_root ${_inactive_}; " \
- "setenv inactive_root ${_active_}; " \
- "saveenv; " \
- "reset; " \
- "fi; "
-
-#endif /* Regular Boot */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-
-/* SPL */
-
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_TIMER
-#endif
-
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_SMSC
-
-/* I2C configuration */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 1
-
-#define CONFIG_SHOW_BOOT_PROGRESS
-#endif /* ! __CONFIG_AM335X_SHC_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 19/93] arm: Remove vining_2000 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (17 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 18/93] arm: Remove am335x_shc_ict board Simon Glass
@ 2018-11-19 15:52 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 20/93] arm: Remove cm_t43 board Simon Glass
` (78 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:52 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/samtec/vining_2000/Kconfig | 12 -
board/samtec/vining_2000/MAINTAINERS | 6 -
board/samtec/vining_2000/Makefile | 4 -
board/samtec/vining_2000/imximage.cfg | 131 -------
board/samtec/vining_2000/vining_2000.c | 517 -------------------------
configs/vining_2000_defconfig | 43 --
include/configs/vining_2000.h | 104 -----
8 files changed, 818 deletions(-)
delete mode 100644 board/samtec/vining_2000/Kconfig
delete mode 100644 board/samtec/vining_2000/MAINTAINERS
delete mode 100644 board/samtec/vining_2000/Makefile
delete mode 100644 board/samtec/vining_2000/imximage.cfg
delete mode 100644 board/samtec/vining_2000/vining_2000.c
delete mode 100644 configs/vining_2000_defconfig
delete mode 100644 include/configs/vining_2000.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 93c8d46c600..ed551b245c9 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -551,7 +551,6 @@ source "board/grinn/liteboard/Kconfig"
source "board/phytec/pfla02/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
-source "board/samtec/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
deleted file mode 100644
index 3447c27fa4f..00000000000
--- a/board/samtec/vining_2000/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SAMTEC_VINING_2000
-
-config SYS_BOARD
- default "vining_2000"
-
-config SYS_VENDOR
- default "samtec"
-
-config SYS_CONFIG_NAME
- default "vining_2000"
-
-endif
diff --git a/board/samtec/vining_2000/MAINTAINERS b/board/samtec/vining_2000/MAINTAINERS
deleted file mode 100644
index 027e52736fa..00000000000
--- a/board/samtec/vining_2000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VINING_2000 BOARD
-M: Ingo Schroeck <open-source@samtec.de>
-S: Maintained
-F: board/samtec/vining_2000/
-F: include/configs/vining_2000.h
-F: configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile b/board/samtec/vining_2000/Makefile
deleted file mode 100644
index 9650da711d9..00000000000
--- a/board/samtec/vining_2000/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2016 samtec automotive software & electronics gmbh
-
-obj-y := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg b/board/samtec/vining_2000/imximage.cfg
deleted file mode 100644
index 3e4fcad8ea1..00000000000
--- a/board/samtec/vining_2000/imximage.cfg
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 samtec automotive software & electronics gmbh
- */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi/sd/nand/onenand, qspi/nor
- */
-
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* Enable all clocks */
-DATA 4 0x020c4068 0xffffffff
-DATA 4 0x020c406c 0xffffffff
-DATA 4 0x020c4070 0xffffffff
-DATA 4 0x020c4074 0xffffffff
-DATA 4 0x020c4078 0xffffffff
-DATA 4 0x020c407c 0xffffffff
-DATA 4 0x020c4080 0xffffffff
-DATA 4 0x020c4084 0xffffffff
-
-/* IOMUX - DDR IO Type */
-DATA 4 0x020e0618 0x000c0000
-DATA 4 0x020e05fc 0x00000000
-
-/* Clock */
-DATA 4 0x020e032c 0x00000030
-
-/* Address */
-DATA 4 0x020e0300 0x00000028
-DATA 4 0x020e02fc 0x00000028
-DATA 4 0x020e05f4 0x00000028
-
-/* Control */
-DATA 4 0x020e0340 0x00000028
-
-DATA 4 0x020e0320 0x00000000
-DATA 4 0x020e0310 0x00000028
-DATA 4 0x020e0314 0x00000028
-DATA 4 0x020e0614 0x00000028
-
-/* Data Strobe */
-DATA 4 0x020e05f8 0x00020000
-DATA 4 0x020e0330 0x00000028
-DATA 4 0x020e0334 0x00000028
-DATA 4 0x020e0338 0x00000028
-DATA 4 0x020e033c 0x00000028
-
-/* Data */
-DATA 4 0x020e0608 0x00020000
-DATA 4 0x020e060c 0x00000028
-DATA 4 0x020e0610 0x00000028
-DATA 4 0x020e061c 0x00000028
-DATA 4 0x020e0620 0x00000028
-DATA 4 0x020e02ec 0x00000028
-DATA 4 0x020e02f0 0x00000028
-DATA 4 0x020e02f4 0x00000028
-DATA 4 0x020e02f8 0x00000028
-
-/* Calibrations - ZQ */
-DATA 4 0x021b0800 0xa1390003
-
-/* Write leveling */
-DATA 4 0x021b080c 0x00290025
-DATA 4 0x021b0810 0x00210022
-
-/* DQS Read Gate */
-DATA 4 0x021b083c 0x4142013a
-DATA 4 0x021b0840 0x012e0123
-
-/* Read/Write Delay */
-DATA 4 0x021b0848 0x43474949
-DATA 4 0x021b0850 0x38383c38
-
-/* Read data bit delay */
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-/* Complete calibration by forced measurement */
-DATA 4 0x021b08b8 0x00000800
-
-/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
-DATA 4 0x021b0004 0x0002002d
-DATA 4 0x021b0008 0x00333040
-DATA 4 0x021b000c 0x676b52f2
-DATA 4 0x021b0010 0x926e8b63
-DATA 4 0x021b0014 0x01ff00db
-DATA 4 0x021b0018 0x00011740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x006b1023
-DATA 4 0x021b0040 0x0000005f
-DATA 4 0x021b0000 0x84190000
-
-/* Initialize MT41K256M16HA-125 - MR2 */
-DATA 4 0x021b001c 0x02008032
-/* MR3 */
-DATA 4 0x021b001c 0x00008033
-/* MR1 */
-DATA 4 0x021b001c 0x00048031
-/* MR0 */
-DATA 4 0x021b001c 0x15108030
-/* DDR device ZQ calibration */
-DATA 4 0x021b001c 0x04008040
-
-/* Final DDR setup, before operation start */
-DATA 4 0x021b0020 0x00007800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b001c 0x00000000
diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c
deleted file mode 100644
index f37365c5cb9..00000000000
--- a/board/samtec/vining_2000/vining_2000.c
+++ /dev/null
@@ -1,517 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 samtec automotive software & electronics gmbh
- *
- * Author: Christoph Fritz <chf.fritz@googlemail.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/io.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <linux/sizes.h>
-#include <common.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-#include <pwm.h>
-#include <wait_bit.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
- PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
- PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm)
-
-#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
-
-#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST)
-
-#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_PKE)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
- MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
- MUX_MODE_SION,
- /* LAN8720 PHY Reset */
- MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const pwm_led_pads[] = {
- MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
- MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
- MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#define PHY_RESET IMX_GPIO_NR(5, 9)
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
- unsigned char eth1addr[6];
-
- /* just to get secound mac address */
- imx_get_mac_from_fuse(1, eth1addr);
- if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
- eth_env_set_enetaddr("eth1addr", eth1addr);
-
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
- /*
- * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
- * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
- * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1],
- IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
- IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
- IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
- IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
-
- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
- goto eth_fail;
-
- /* reset phy */
- gpio_direction_output(PHY_RESET, 0);
- mdelay(16);
- gpio_set_value(PHY_RESET, 1);
- mdelay(1);
-
- ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
- IMX_FEC_BASE);
- if (ret)
- goto eth_fail;
-
- return ret;
-
-eth_fail:
- printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
- gpio_set_value(PHY_RESET, 0);
- return ret;
-}
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-
-static struct pmic *pfuze_init(unsigned char i2cbus)
-{
- struct pmic *p;
- int ret;
- u32 reg;
-
- ret = power_pfuze100_init(i2cbus);
- if (ret)
- return NULL;
-
- p = pmic_get("PFUZE100");
- ret = pmic_probe(p);
- if (ret)
- return NULL;
-
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Set SW1AB stanby volage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
- reg &= ~SW1x_STBY_MASK;
- reg |= SW1x_0_975V;
- pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
-
- /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
- reg &= ~SW1xCONF_DVSSPEED_MASK;
- reg |= SW1xCONF_DVSSPEED_4US;
- pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
-
- /* Set SW1C standby voltage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
- reg &= ~SW1x_STBY_MASK;
- reg |= SW1x_0_975V;
- pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
-
- /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
- reg &= ~SW1xCONF_DVSSPEED_MASK;
- reg |= SW1xCONF_DVSSPEED_4US;
- pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
-
- return p;
-}
-
-static int pfuze_mode_init(struct pmic *p, u32 mode)
-{
- unsigned char offset, i, switch_num;
- u32 id;
- int ret;
-
- pmic_reg_read(p, PFUZE100_DEVICEID, &id);
- id = id & 0xf;
-
- if (id == 0) {
- switch_num = 6;
- offset = PFUZE100_SW1CMODE;
- } else if (id == 1) {
- switch_num = 4;
- offset = PFUZE100_SW2MODE;
- } else {
- printf("Not supported, id=%d\n", id);
- return -EINVAL;
- }
-
- ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
- if (ret < 0) {
- printf("Set SW1AB mode error!\n");
- return ret;
- }
-
- for (i = 0; i < switch_num - 1; i++) {
- ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
- if (ret < 0) {
- printf("Set switch 0x%x mode error!\n",
- offset + i * SWITCH_SIZE);
- return ret;
- }
- }
-
- return ret;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
- int ret;
-
- p = pfuze_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
-
- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OGT1 */
- MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-static void setup_iomux_usb(void)
-{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return usb_phy_mode(port);
-}
-#endif
-
-#ifdef CONFIG_PWM_IMX
-static int set_pwm_leds(void)
-{
- int ret;
-
- imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
- ARRAY_SIZE(pwm_led_pads));
- /* enable backlight PWM 2, green LED */
- ret = pwm_init(1, 0, 0);
- if (ret)
- goto error;
- /* duty cycle 200ns, period: 8000ns */
- ret = pwm_config(1, 200, 8000);
- if (ret)
- goto error;
- ret = pwm_enable(1);
- if (ret)
- goto error;
-
- /* enable backlight PWM 1, blue LED */
- ret = pwm_init(0, 0, 0);
- if (ret)
- goto error;
- /* duty cycle 200ns, period: 8000ns */
- ret = pwm_config(0, 200, 8000);
- if (ret)
- goto error;
- ret = pwm_enable(0);
- if (ret)
- goto error;
-
- /* enable backlight PWM 6, red LED */
- ret = pwm_init(5, 0, 0);
- if (ret)
- goto error;
- /* duty cycle 200ns, period: 8000ns */
- ret = pwm_config(5, 200, 8000);
- if (ret)
- goto error;
- ret = pwm_enable(5);
-
-error:
- return ret;
-}
-#else
-static int set_pwm_leds(void)
-{
- return 0;
-}
-#endif
-
-#define ADCx_HC0 0x00
-#define ADCx_HS 0x08
-#define ADCx_HS_C0 BIT(0)
-#define ADCx_R0 0x0c
-#define ADCx_CFG 0x14
-#define ADCx_CFG_SWMODE 0x308
-#define ADCx_GC 0x18
-#define ADCx_GC_CAL BIT(7)
-
-static int read_adc(u32 *val)
-{
- int ret;
- void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
-
- /* use software mode */
- writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
-
- /* start auto calibration */
- setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
- ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
- if (ret)
- goto adc_exit;
-
- /* start conversion */
- writel(0, b + ADCx_HC0);
-
- /* wait for conversion */
- ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
- if (ret)
- goto adc_exit;
-
- /* read result */
- *val = readl(b + ADCx_R0);
-
-adc_exit:
- if (ret)
- printf("ADC failure (ret=%i)\n", ret);
- unmap_physmem(b, MAP_NOCACHE);
- return ret;
-}
-
-#define VAL_UPPER 2498
-#define VAL_LOWER 1550
-
-static int set_pin_state(void)
-{
- u32 val;
- int ret;
-
- ret = read_adc(&val);
- if (ret)
- return ret;
-
- if (val >= VAL_UPPER)
- env_set("pin_state", "connected");
- else if (val < VAL_UPPER && val > VAL_LOWER)
- env_set("pin_state", "open");
- else
- env_set("pin_state", "button");
-
- return ret;
-}
-
-int board_late_init(void)
-{
- int ret;
-
- ret = set_pwm_leds();
- if (ret)
- return ret;
-
- ret = set_pin_state();
-
- return ret;
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- setup_iomux_usb();
-
- return 0;
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC4_BASE_ADDR, 0, 8},
- {USDHC2_BASE_ADDR, 0, 4},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- if (cfg->esdhc_base == USDHC4_BASE_ADDR)
- return 1;
- if (cfg->esdhc_base == USDHC2_BASE_ADDR)
- return !gpio_get_value(USDHC2_CD_GPIO);
-
- return -EINVAL;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 USDHC4
- * mmc1 USDHC2
- */
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- if (ret) {
- printf("Warning: failed to initialize USDHC4\n");
- return ret;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
- if (ret) {
- printf("Warning: failed to initialize USDHC2\n");
- return ret;
- }
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: VIN|ING 2000\n");
-
- return 0;
-}
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
deleted file mode 100644
index 019f79c8305..00000000000
--- a/configs/vining_2000_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_SAMTEC_VINING_2000=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg"
-CONFIG_BOOTDELAY=0
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
deleted file mode 100644
index d3cbdc6f2e4..00000000000
--- a/include/configs/vining_2000.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 samtec automotive software & electronics gmbh
- *
- * Configuration settings for the Samtec VIN|ING 2000 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-#include <config_distro_bootcmd.h>
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
-/* Network */
-#define CONFIG_FEC_MXC
-
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x0
-
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-
-#define CONFIG_PHY_ATHEROS
-
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif
-
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6)
-#endif
-
-#define CONFIG_IMX_THERMAL
-
-#define CONFIG_PWM_IMX
-#define CONFIG_IMX6_PWM_PER_CLK 66000000
-
-#define CONFIG_ENV_OFFSET (8 * SZ_64K)
-#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
-/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
-#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
-#endif
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 20/93] arm: Remove cm_t43 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (18 preceding siblings ...)
2018-11-19 15:52 ` [U-Boot] [PATCH 19/93] arm: Remove vining_2000 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 21:32 ` Marek Vasut
2018-11-19 15:53 ` [U-Boot] [PATCH 21/93] arm: Remove igep00x0 board Simon Glass
` (77 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/Kconfig | 1 -
board/compulab/cm_t43/Kconfig | 15 ---
board/compulab/cm_t43/MAINTAINERS | 6 --
board/compulab/cm_t43/Makefile | 11 --
board/compulab/cm_t43/board.h | 11 --
board/compulab/cm_t43/cm_t43.c | 164 ------------------------------
board/compulab/cm_t43/mux.c | 142 --------------------------
board/compulab/cm_t43/spl.c | 134 ------------------------
configs/cm_t43_defconfig | 72 -------------
include/configs/cm_t43.h | 140 -------------------------
10 files changed, 696 deletions(-)
delete mode 100644 board/compulab/cm_t43/Kconfig
delete mode 100644 board/compulab/cm_t43/MAINTAINERS
delete mode 100644 board/compulab/cm_t43/Makefile
delete mode 100644 board/compulab/cm_t43/board.h
delete mode 100644 board/compulab/cm_t43/cm_t43.c
delete mode 100644 board/compulab/cm_t43/mux.c
delete mode 100644 board/compulab/cm_t43/spl.c
delete mode 100644 configs/cm_t43_defconfig
delete mode 100644 include/configs/cm_t43.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 58e545a45b4..438cbb30419 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -185,7 +185,6 @@ source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/compulab/cm_t335/Kconfig"
-source "board/compulab/cm_t43/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/board/compulab/cm_t43/Kconfig b/board/compulab/cm_t43/Kconfig
deleted file mode 100644
index a19188975ec..00000000000
--- a/board/compulab/cm_t43/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CM_T43
-
-config SYS_BOARD
- default "cm_t43"
-
-config SYS_VENDOR
- default "compulab"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "cm_t43"
-
-endif
diff --git a/board/compulab/cm_t43/MAINTAINERS b/board/compulab/cm_t43/MAINTAINERS
deleted file mode 100644
index 951c370dd71..00000000000
--- a/board/compulab/cm_t43/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM_T43 BOARD
-M: Nikita Kiryanov <nikita@compulab.co.il>
-S: Maintained
-F: board/compulab/cm_t43/
-F: include/configs/cm_t43.h
-F: configs/cm_t43_defconfig
diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile
deleted file mode 100644
index 6fa231a045e..00000000000
--- a/board/compulab/cm_t43/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2015 Compulab, Ltd.
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o mux.o
-else
-obj-y += cm_t43.o mux.o
-endif
diff --git a/board/compulab/cm_t43/board.h b/board/compulab/cm_t43/board.h
deleted file mode 100644
index fcacd2bc0f8..00000000000
--- a/board/compulab/cm_t43/board.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Compulab, Ltd.
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-void set_i2c_pin_mux(void);
-void set_mdio_pin_mux(void);
-void set_rgmii_pin_mux(void);
-#endif
diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c
deleted file mode 100644
index 2aa453471d9..00000000000
--- a/board/compulab/cm_t43/cm_t43.c
+++ /dev/null
@@ -1,164 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Compulab, Ltd.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/emif.h>
-#include <power/pmic.h>
-#include <power/tps65218.h>
-#include "board.h"
-#include <usb.h>
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* setup board specific PMIC */
-int power_init_board(void)
-{
- struct pmic *p;
- uchar tps_status = 0;
-
- power_tps65218_init(I2C_PMIC);
- p = pmic_get("TPS65218_PMIC");
- if (p && !pmic_probe(p)) {
- puts("PMIC: TPS65218\n");
- /* We don't care if fseal is locked, but we do need it set */
- tps65218_lock_fseal();
- tps65218_reg_read(TPS65218_STATUS, &tps_status);
- if (!(tps_status & TPS65218_FSEAL))
- printf("WARNING: RTC not backed by battery!\n");
- }
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gpmc_init();
- set_i2c_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- i2c_probe(TPS65218_CHIP_PM);
-
- return 0;
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- enable_usb_clocks(index);
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- disable_usb_clocks(index);
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-static void cpsw_control(int enabled)
-{
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 2,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-#define GPIO_PHY1_RST 170
-#define GPIO_PHY2_RST 168
-
-int board_phy_config(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-
-static void board_phy_init(void)
-{
- set_mdio_pin_mux();
- writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
- writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
- writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
-
- /* For revision A */
- writel(0x2000009, 0x44df2e6c);
- writel(0x38a, 0x44df2e70);
-
- mdelay(10);
-
- gpio_request(GPIO_PHY1_RST, "phy1_rst");
- gpio_request(GPIO_PHY2_RST, "phy2_rst");
- gpio_direction_output(GPIO_PHY1_RST, 0);
- gpio_direction_output(GPIO_PHY2_RST, 0);
- mdelay(2);
-
- gpio_set_value(GPIO_PHY1_RST, 1);
- gpio_set_value(GPIO_PHY2_RST, 1);
- mdelay(2);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rv;
-
- set_rgmii_pin_mux();
- writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
- board_phy_init();
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
-
- return rv;
-}
-#endif
diff --git a/board/compulab/cm_t43/mux.c b/board/compulab/cm_t43/mux.c
deleted file mode 100644
index 778ea05e84c..00000000000
--- a/board/compulab/cm_t43/mux.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Compulab, Ltd.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include "board.h"
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)},
- {OFFSET(mii1_txd3), MODE(2)},
- {OFFSET(mii1_txd2), MODE(2)},
- {OFFSET(mii1_txd1), MODE(2)},
- {OFFSET(mii1_txd0), MODE(2)},
- {OFFSET(mii1_txclk), MODE(2)},
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN},
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN},
- {-1},
-};
-
-static struct module_pin_mux rgmii2_pin_mux[] = {
- {OFFSET(gpmc_a0), MODE(2)}, /* txen */
- {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */
- {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */
- {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */
- {OFFSET(gpmc_a5), MODE(2)}, /* txd0 */
- {OFFSET(gpmc_a6), MODE(2)}, /* txclk */
- {OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */
- {OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */
- {OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */
- {OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */
- {OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */
- {OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN}, /* rxd0 */
- {-1},
-};
-
-static struct module_pin_mux mdio_pin_mux[] = {
- {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
- {-1},
-};
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {-1},
-};
-
-static struct module_pin_mux i2c_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(spi2_cs0), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
- {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(gpmc_wpn), (MODE(0) | PULLUP_EN)},
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
- {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
- {-1},
-};
-
-static struct module_pin_mux emmc_pin_mux[] = {
- {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */
- {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */
- {OFFSET(gpmc_ad8), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */
- {OFFSET(gpmc_ad9), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */
- {OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */
- {OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */
- {OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */
- {OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */
- {OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */
- {OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */
- {-1},
-};
-
-static struct module_pin_mux spi_flash_pin_mux[] = {
- {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)},
- {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},
- {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN)},
- {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},
- {-1},
-};
-
-void set_uart_mux_conf(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void set_mdio_pin_mux(void)
-{
- configure_module_pin_mux(mdio_pin_mux);
-}
-
-void set_rgmii_pin_mux(void)
-{
- configure_module_pin_mux(rgmii1_pin_mux);
- configure_module_pin_mux(rgmii2_pin_mux);
-}
-
-void set_mux_conf_regs(void)
-{
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(emmc_pin_mux);
- configure_module_pin_mux(i2c_pin_mux);
- configure_module_pin_mux(spi_flash_pin_mux);
- configure_module_pin_mux(nand_pin_mux);
-}
-
-void set_i2c_pin_mux(void)
-{
- configure_module_pin_mux(i2c_pin_mux);
-}
diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c
deleted file mode 100644
index 7da9a9ad86b..00000000000
--- a/board/compulab/cm_t43/spl.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Compulab, Ltd.
- */
-
-#include <common.h>
-#include <spl.h>
-#include <i2c.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/gpio.h>
-#include <power/pmic.h>
-#include <power/tps65218.h>
-#include "board.h"
-
-const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
-const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
-const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
-const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
-
-const struct ctrl_ioregs ioregs_ddr3 = {
- .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
- .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
- .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
- .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
- .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
- .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .emif_sdram_config_ext = 0x0143,
-};
-
-/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
-struct emif_regs ddr3_emif_regs = {
- .sdram_config = 0x638413B2,
- .ref_ctrl = 0x00000C30,
- .sdram_tim1 = 0xEAAAD4DB,
- .sdram_tim2 = 0x266B7FDA,
- .sdram_tim3 = 0x107F8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E004008,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
- .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
- .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
- .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
- .emif_rd_wr_exec_thresh = 0x80000405,
- .emif_prio_class_serv_map = 0x80000001,
- .emif_connect_id_serv_1_map = 0x80000094,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x000FFFFF
-};
-
-const u32 ext_phy_ctrl_const_base_ddr3[] = {
- 0x00000000,
- 0x00000044,
- 0x00000044,
- 0x00000046,
- 0x00000046,
- 0x00000000,
- 0x00000059,
- 0x00000077,
- 0x00000093,
- 0x000000A8,
- 0x00000000,
- 0x00000019,
- 0x00000037,
- 0x00000053,
- 0x00000068,
- 0x00000000,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
- *regs = ext_phy_ctrl_const_base_ddr3;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr;
-}
-
-const struct dpll_params *get_dpll_mpu_params(void)
-{
- return &dpll_mpu;
-}
-
-const struct dpll_params *get_dpll_core_params(void)
-{
- return &dpll_core;
-}
-
-const struct dpll_params *get_dpll_per_params(void)
-{
- return &dpll_per;
-}
-
-void scale_vcores(void)
-{
- set_i2c_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (i2c_probe(TPS65218_CHIP_PM))
- return;
-
- tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
- tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
-}
-
-void sdram_init(void)
-{
- unsigned long ram_size;
-
- config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
- ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (ram_size == 0x80000000 ||
- ram_size == 0x40000000 ||
- ram_size == 0x20000000)
- return;
-
- ddr3_emif_regs.sdram_config = 0x638453B2;
- config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
- ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (ram_size == 0x08000000)
- return;
-
- hang();
-}
-
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
deleted file mode 100644
index eb4a8f5a330..00000000000
--- a/configs/cm_t43_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM43XX=y
-CONFIG_TARGET_CM_T43=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_PROMPT="CM-T43 # "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_EEPROM_LAYOUT=y
-CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_DM_GPIO=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
deleted file mode 100644
index 79eb865bf9c..00000000000
--- a/include/configs/cm_t43.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * cm_t43.h
- *
- * Copyright (C) 2015 Compulab, Ltd.
- */
-
-#ifndef __CONFIG_CM_T43_H
-#define __CONFIG_CM_T43_H
-
-#define CONFIG_CM_T43
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-
-#include <asm/arch/omap.h>
-
-/* Serial support */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK 48000000
-#define CONFIG_SYS_NS16550_COM1 0x44e09000
-#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#endif
-
-/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-/* CPSW Ethernet support */
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_PHY_ATHEROS
-#define CONFIG_SYS_RX_ETH_BUFFER 64
-
-/* USB support */
-#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_AM437X_USB2PHY2_HOST
-
-/* SPI Flash support */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_SF_DEFAULT_SPEED 48000000
-#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
-
-/* Power */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_TPS65218
-
-/* Enabling L2 Cache */
-#define CONFIG_SYS_L2_PL310
-#define CONFIG_SYS_PL310_BASE 0x48242000
-
-/*
- * Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-#define CONFIG_HSMMC2_8BIT
-
-#include <configs/ti_armv7_omap.h>
-#undef CONFIG_SYS_MONITOR_LEN
-
-#define CONFIG_ENV_SIZE (16 * 1024)
-
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_OFFSET (768 * 1024)
-#define CONFIG_ENV_SPI_MAX_HZ 48000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x81200000\0" \
- "bootm_size=0x8000000\0" \
- "autoload=no\0" \
- "console=ttyO0,115200n8\0" \
- "fdtfile=am437x-sb-som-t43.dtb\0" \
- "kernel=zImage-cm-t43\0" \
- "bootscr=bootscr.img\0" \
- "emmcroot=/dev/mmcblk0p2 rw\0" \
- "emmcrootfstype=ext4 rootwait\0" \
- "emmcargs=setenv bootargs console=${console} " \
- "root=${emmcroot} " \
- "rootfstype=${emmcrootfstype}\0" \
- "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "emmcboot=echo Booting from emmc ... && " \
- "run emmcargs && " \
- "load mmc 1 ${loadaddr} ${kernel} && " \
- "load mmc 1 ${fdtaddr} ${fdtfile} && " \
- "bootz ${loadaddr} - ${fdtaddr}\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev 0; " \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "fi; " \
- "fi; " \
- "mmc dev 1; " \
- "if mmc rescan; then " \
- "run emmcboot; " \
- "fi;"
-
-/* SPL defines. */
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
-
-#endif /* __CONFIG_CM_T43_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 21/93] arm: Remove igep00x0 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (19 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 20/93] arm: Remove cm_t43 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 22/93] arm: Remove sheevaplug board Simon Glass
` (76 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/isee/igep00x0/Kconfig | 12 --
board/isee/igep00x0/MAINTAINERS | 7 -
board/isee/igep00x0/Makefile | 10 --
board/isee/igep00x0/common.c | 67 --------
board/isee/igep00x0/igep00x0.c | 258 ------------------------------
board/isee/igep00x0/igep00x0.h | 127 ---------------
board/isee/igep00x0/spl.c | 63 --------
configs/igep0032_defconfig | 52 ------
configs/igep00x0_defconfig | 53 ------
include/configs/omap3_igep00x0.h | 135 ----------------
11 files changed, 785 deletions(-)
delete mode 100644 board/isee/igep00x0/Kconfig
delete mode 100644 board/isee/igep00x0/MAINTAINERS
delete mode 100644 board/isee/igep00x0/Makefile
delete mode 100644 board/isee/igep00x0/common.c
delete mode 100644 board/isee/igep00x0/igep00x0.c
delete mode 100644 board/isee/igep00x0/igep00x0.h
delete mode 100644 board/isee/igep00x0/spl.c
delete mode 100644 configs/igep0032_defconfig
delete mode 100644 configs/igep00x0_defconfig
delete mode 100644 include/configs/omap3_igep00x0.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 04b6ffe574a..9bd07dd8c55 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -200,7 +200,6 @@ source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
-source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig
deleted file mode 100644
index aa46882b051..00000000000
--- a/board/isee/igep00x0/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_IGEP00X0
-
-config SYS_BOARD
- default "igep00x0"
-
-config SYS_VENDOR
- default "isee"
-
-config SYS_CONFIG_NAME
- default "omap3_igep00x0"
-
-endif
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
deleted file mode 100644
index d75d400eed0..00000000000
--- a/board/isee/igep00x0/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-IGEP00X0 BOARD
-M: Enric Balletbo i Serra <eballetbo@gmail.com>
-S: Maintained
-F: board/isee/igep00x0/
-F: include/configs/omap3_igep00x0.h
-F: configs/igep00x0_defconfig
-F: configs/igep0032_defconfig
diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
deleted file mode 100644
index e095bcada29..00000000000
--- a/board/isee/igep00x0/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-ifdef CONFIG_SPL_BUILD
-obj-y := spl.o common.o
-else
-obj-y := igep00x0.o common.o
-endif
diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
deleted file mode 100644
index f5d62ffc2e5..00000000000
--- a/board/isee/igep00x0/common.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <common.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/omap_mmc.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <jffs2/load_kernel.h>
-#include <linux/mtd/rawnand.h>
-#include "igep00x0.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-}
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- int loops = 100;
-
- /* find out flash memory type, assume NAND first */
- gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
- gpmc_init();
-
- /* Issue a RESET and then READID */
- writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
- writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
- while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
- != NAND_STATUS_READY) {
- udelay(1);
- if (--loops == 0) {
- gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
- gpmc_init(); /* reinitialize for OneNAND */
- break;
- }
- }
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
deleted file mode 100644
index 367af82d4a1..00000000000
--- a/board/isee/igep00x0/igep00x0.c
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- */
-#include <common.h>
-#include <status_led.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include <netdev.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/onenand.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <fdt_support.h>
-#include "igep00x0.h"
-
-static const struct ns16550_platdata igep_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(igep_uart) = {
- "ns16550_serial",
- &igep_serial
-};
-
-/*
- * Routine: get_board_revision
- * Description: GPIO_28 and GPIO_129 are used to read board and revision from
- * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
- * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
- * this functionality is shared by USB HOST.
- * Once USB reset is applied, U-boot configures these pins as input pullup to
- * detect board and revision:
- * IGEP0020-RF = 0b00
- * IGEP0020-RC = 0b01
- * IGEP0030-RG = 0b10
- * IGEP0030-RE = 0b11
- */
-static int get_board_revision(void)
-{
- int revision;
-
- gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
- "igep0030_usb_transceiver_reset");
- gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
-
- gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
- gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
- revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
- gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
-
- gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
- "igep00x0_revision_detection");
- gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
- revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
- gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
-
- gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
-
- return revision;
-}
-
-int onenand_board_init(struct mtd_info *mtd)
-{
- if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
- struct onenand_chip *this = mtd->priv;
- this->base = (void *)CONFIG_SYS_ONENAND_BASE;
- return 0;
- }
- return 1;
-}
-
-#if defined(CONFIG_CMD_NET)
-static void reset_net_chip(int gpio)
-{
- if (!gpio_request(gpio, "eth nrst")) {
- gpio_direction_output(gpio, 1);
- udelay(1);
- gpio_set_value(gpio, 0);
- udelay(40);
- gpio_set_value(gpio, 1);
- mdelay(10);
- }
-}
-
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
- static const u32 gpmc_lan_config[] = {
- NET_LAN9221_GPMC_CONFIG1,
- NET_LAN9221_GPMC_CONFIG2,
- NET_LAN9221_GPMC_CONFIG3,
- NET_LAN9221_GPMC_CONFIG4,
- NET_LAN9221_GPMC_CONFIG5,
- NET_LAN9221_GPMC_CONFIG6,
- };
-
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-
- reset_net_chip(64);
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#else
- return 0;
-#endif
-}
-#else
-static inline void setup_net_chip(void) {}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int ft_enable_by_compatible(void *blob, char *compat, int enable)
-{
- int off = fdt_node_offset_by_compatible(blob, -1, compat);
- if (off < 0)
- return off;
-
- if (enable)
- fdt_status_okay(blob, off);
- else
- fdt_status_disabled(blob, off);
-
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
- static const struct node_info nodes[] = {
- { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
- { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
- };
-
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
- ft_enable_by_compatible(blob, "ti,omap2-nand",
- gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
- ft_enable_by_compatible(blob, "ti,omap2-onenand",
- gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
-
- return 0;
-}
-#endif
-
-void set_led(void)
-{
- switch (get_board_revision()) {
- case 0:
- case 1:
- gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
- gpio_direction_output(IGEP0020_GPIO_LED, 1);
- break;
- case 2:
- case 3:
- gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
- gpio_direction_output(IGEP0030_GPIO_LED, 0);
- break;
- default:
- /* Should not happen... */
- break;
- }
-}
-
-void set_boardname(void)
-{
- char rev[5] = { 'F','C','G','E', };
- int i = get_board_revision();
-
- rev[i+1] = 0;
- env_set("board_rev", rev + i);
- env_set("board_name", i < 2 ? "igep0020" : "igep0030");
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- t2_t *t2_base = (t2_t *)T2_BASE;
- u32 pbias_lite;
-
- twl4030_power_init();
-
- /* set VSIM to 1.8V */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
- TWL4030_PM_RECEIVER_VSIM_VSEL_18,
- TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
-
- /* set up dual-voltage GPIOs to 1.8V */
- pbias_lite = readl(&t2_base->pbias_lite);
- pbias_lite &= ~PBIASLITEVMODE1;
- pbias_lite |= PBIASLITEPWRDNZ1;
- writel(pbias_lite, &t2_base->pbias_lite);
- if (get_cpu_family() == CPU_OMAP36XX)
- writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
- OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
- OMAP34XX_CTRL_WKUP_CTRL);
-
- setup_net_chip();
-
- omap_die_id_display();
-
- set_led();
-
- set_boardname();
-
- return 0;
-}
-
-void board_mtdparts_default(const char **mtdids, const char **mtdparts)
-{
- struct mtd_info *mtd = get_mtd_device(NULL, 0);
- if (mtd) {
- static char ids[24];
- static char parts[48];
- const char *linux_name = "omap2-nand";
- if (strncmp(mtd->name, "onenand0", 8) == 0)
- linux_name = "omap2-onenand";
- snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
- snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
- linux_name, 4 * mtd->erasesize >> 10);
- *mtdids = ids;
- *mtdparts = parts;
- }
-}
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
deleted file mode 100644
index aa532acad95..00000000000
--- a/board/isee/igep00x0/igep00x0.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- */
-#ifndef _IGEP00X0_H_
-#define _IGEP00X0_H_
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
- MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
-#endif
diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c
deleted file mode 100644
index e092e1a418b..00000000000
--- a/board/isee/igep00x0/spl.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <jffs2/load_kernel.h>
-#include <linux/mtd/rawnand.h>
-#include "igep00x0.h"
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int mfr, id, err = identify_nand_chip(&mfr, &id);
-
- timings->mr = MICRON_V_MR_165;
- if (!err) {
- switch (mfr) {
- case NAND_MFR_HYNIX:
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- break;
- case NAND_MFR_MICRON:
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- break;
- default:
- /* Should not happen... */
- break;
- }
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
- } else {
- if (get_cpu_family() == CPU_OMAP34XX) {
- timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- } else {
- timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_200;
- timings->ctrlb = NUMONYX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- }
- gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
- }
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- return 0;
-}
-#endif
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
deleted file mode 100644
index 383648789c5..00000000000
--- a/configs/igep0032_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_ONENAND=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x2C000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_UDC=y
-CONFIG_USB_OMAP3=y
-CONFIG_TWL4030_USB=y
-CONFIG_FAT_WRITE=y
-CONFIG_UBIFS_SILENCE_MSG=y
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
deleted file mode 100644
index f2989e34e12..00000000000
--- a/configs/igep00x0_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_ONENAND=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x2C000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_UDC=y
-CONFIG_USB_OMAP3=y
-CONFIG_TWL4030_USB=y
-CONFIG_FAT_WRITE=y
-CONFIG_UBIFS_SILENCE_MSG=y
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
deleted file mode 100644
index b9d65697521..00000000000
--- a/include/configs/omap3_igep00x0.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Common configuration settings for IGEP technology based boards
- *
- * (C) Copyright 2012
- * ISEE 2007 SL, <www.iseebcn.com>
- */
-
-#ifndef __IGEP00X0_H
-#define __IGEP00X0_H
-
-#include <configs/ti_omap3_common.h>
-
-/*
- * We are only ever GP parts and will utilize all of the "downloaded image"
- * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
- */
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE 0x40200000
-
-#define CONFIG_REVISION_TAG 1
-
-/* GPIO banks */
-#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
-#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
-
-/* TPS65950 */
-#define PBIASLITEVMODE1 (1 << 8)
-
-/* LED */
-#define IGEP0020_GPIO_LED 27
-#define IGEP0030_GPIO_LED 16
-
-/* Board and revision detection GPIOs */
-#define IGEP0030_USB_TRANSCEIVER_RESET 54
-#define GPIO_IGEP00X0_BOARD_DETECTION 28
-#define GPIO_IGEP00X0_REVISION_DETECTION 129
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "IGEP"
-
-#ifndef CONFIG_SPL_BUILD
-
-/* Environment */
-#define ENV_DEVICE_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-#define MEM_LAYOUT_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "scriptaddr=0x87E00000\0" \
- "pxefile_addr_r=0x87F00000\0"
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0)
-
-#include <config_distro_bootcmd.h>
-
-#define ENV_FINDFDT \
- "findfdt="\
- "if test ${board_name} = igep0020; then " \
- "if test ${board_rev} = F; then " \
- "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
- "else " \
- "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
- "if test ${board_name} = igep0030; then " \
- "if test ${board_rev} = G; then " \
- "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
- "else " \
- "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
- "if test ${fdtfile} = ''; then " \
- "echo WARNING: Could not determine device tree to use; fi; \0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- ENV_FINDFDT \
- ENV_DEVICE_SETTINGS \
- MEM_LAYOUT_SETTINGS \
- BOOTENV
-
-#endif
-
-#define CONFIG_SYS_MTDPARTS_RUNTIME
-
-/* OneNAND config */
-#define CONFIG_USE_ONENAND_BOARD_INIT
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
-
-/* NAND config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-
-/* UBI configuration */
-#define CONFIG_SPL_UBI 1
-#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
-#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
-#define CONFIG_SPL_UBI_MAX_PEBS 4096
-#define CONFIG_SPL_UBI_VOL_IDS 8
-#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
-#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
-#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
-#define CONFIG_SPL_UBI_PEB_OFFSET 4
-#define CONFIG_SPL_UBI_VID_OFFSET 512
-#define CONFIG_SPL_UBI_LEB_START 2048
-#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
-
-/* environment organization */
-#define CONFIG_ENV_UBI_PART "UBI"
-#define CONFIG_ENV_UBI_VOLUME "config"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
-#define CONFIG_ENV_SIZE (32*1024)
-
-#endif /* __IGEP00X0_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 22/93] arm: Remove sheevaplug board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (20 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 21/93] arm: Remove igep00x0 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 23/93] arm: Remove omap3_overo board Simon Glass
` (75 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/Marvell/sheevaplug/Kconfig | 12 ---
board/Marvell/sheevaplug/MAINTAINERS | 6 --
board/Marvell/sheevaplug/Makefile | 7 --
board/Marvell/sheevaplug/kwbimage.cfg | 144 --------------------------
board/Marvell/sheevaplug/sheevaplug.c | 133 ------------------------
board/Marvell/sheevaplug/sheevaplug.h | 24 -----
configs/sheevaplug_defconfig | 44 --------
include/configs/sheevaplug.h | 92 ----------------
9 files changed, 463 deletions(-)
delete mode 100644 board/Marvell/sheevaplug/Kconfig
delete mode 100644 board/Marvell/sheevaplug/MAINTAINERS
delete mode 100644 board/Marvell/sheevaplug/Makefile
delete mode 100644 board/Marvell/sheevaplug/kwbimage.cfg
delete mode 100644 board/Marvell/sheevaplug/sheevaplug.c
delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h
delete mode 100644 configs/sheevaplug_defconfig
delete mode 100644 include/configs/sheevaplug.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 11491f61b8a..63fd39881ed 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -72,7 +72,6 @@ config SYS_SOC
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
-source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig
deleted file mode 100644
index e5f92847299..00000000000
--- a/board/Marvell/sheevaplug/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SHEEVAPLUG
-
-config SYS_BOARD
- default "sheevaplug"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "sheevaplug"
-
-endif
diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS
deleted file mode 100644
index 2b0103d07dc..00000000000
--- a/board/Marvell/sheevaplug/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SHEEVAPLUG BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/sheevaplug/
-F: include/configs/sheevaplug.h
-F: configs/sheevaplug_defconfig
diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile
deleted file mode 100644
index c39dd03e2d3..00000000000
--- a/board/Marvell/sheevaplug/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-
-obj-y := sheevaplug.o
diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg
deleted file mode 100644
index f5206451da4..00000000000
--- a/board/Marvell/sheevaplug/kwbimage.cfg
+++ /dev/null
@@ -1,144 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Refer to doc/README.kwbimage for more details about how-to
-# configure and create kirkwood boot images.
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
deleted file mode 100644
index 79999c7d304..00000000000
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "sheevaplug.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
- SHEEVAPLUG_OE_VAL_HIGH,
- SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_UART0_RTS,
- MPP9_UART0_CTS,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_TSMP9,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h
deleted file mode 100644
index e026c1b53bd..00000000000
--- a/board/Marvell/sheevaplug/sheevaplug.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __SHEEVAPLUG_H
-#define __SHEEVAPLUG_H
-
-#define SHEEVAPLUG_OE_LOW (~(0))
-#define SHEEVAPLUG_OE_HIGH (~(0))
-#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
-#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __SHEEVAPLUG_H */
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
deleted file mode 100644
index 04b00cdea9d..00000000000
--- a/configs/sheevaplug_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_SHEEVAPLUG=y
-CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
deleted file mode 100644
index deec71734dc..00000000000
--- a/include/configs/sheevaplug.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009-2014
- * Gerald Kerma <dreagle@doukki.net>
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef _CONFIG_SHEEVAPLUG_H
-#define _CONFIG_SHEEVAPLUG_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-
-/*
- * Commands configuration
- */
-
-/*
- * Standard filesystems
- */
-#define CONFIG_BZIP2
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-plug-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x80000
-#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MVEBU_MMC
-#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
-#endif /* CONFIG_CMD_MMC */
-
-/*
- * SATA driver configuration
- */
-#ifdef CONFIG_IDE
-#define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT0
-#define CONFIG_MVSATA_IDE_USE_PORT1
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /* CONFIG_IDE */
-
-#endif /* _CONFIG_SHEEVAPLUG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 23/93] arm: Remove omap3_overo board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (21 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 22/93] arm: Remove sheevaplug board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
[not found] ` <CAGDS+nkiuiUPGzwtU9kH1jG_hP-Xk7pZcsc7HoZw9PH34xt8jQ@mail.gmail.com>
2018-11-19 15:53 ` [U-Boot] [PATCH 24/93] arm: Remove am335x_boneblack board Simon Glass
` (74 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/overo/Kconfig | 9 -
board/overo/MAINTAINERS | 6 -
board/overo/Makefile | 10 -
board/overo/common.c | 341 ------------------------
board/overo/overo.c | 420 ------------------------------
board/overo/overo.h | 169 ------------
board/overo/spl.c | 59 -----
configs/omap3_overo_defconfig | 51 ----
include/configs/omap3_overo.h | 192 --------------
10 files changed, 1258 deletions(-)
delete mode 100644 board/overo/Kconfig
delete mode 100644 board/overo/MAINTAINERS
delete mode 100644 board/overo/Makefile
delete mode 100644 board/overo/common.c
delete mode 100644 board/overo/overo.c
delete mode 100644 board/overo/overo.h
delete mode 100644 board/overo/spl.c
delete mode 100644 configs/omap3_overo_defconfig
delete mode 100644 include/configs/omap3_overo.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 9bd07dd8c55..4e8be5f9d04 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -200,7 +200,6 @@ source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
-source "board/overo/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
diff --git a/board/overo/Kconfig b/board/overo/Kconfig
deleted file mode 100644
index 74572a62be6..00000000000
--- a/board/overo/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_OMAP3_OVERO
-
-config SYS_BOARD
- default "overo"
-
-config SYS_CONFIG_NAME
- default "omap3_overo"
-
-endif
diff --git a/board/overo/MAINTAINERS b/board/overo/MAINTAINERS
deleted file mode 100644
index 8f089e87f8b..00000000000
--- a/board/overo/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OVERO BOARD
-M: Steve Sakoman <sakoman@gmail.com>
-S: Maintained
-F: board/overo/
-F: include/configs/omap3_overo.h
-F: configs/omap3_overo_defconfig
diff --git a/board/overo/Makefile b/board/overo/Makefile
deleted file mode 100644
index b62bab9fe4f..00000000000
--- a/board/overo/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-ifdef CONFIG_SPL_BUILD
-obj-y := spl.o common.o
-else
-obj-y := overo.o common.o
-endif
diff --git a/board/overo/common.c b/board/overo/common.c
deleted file mode 100644
index fc02d66d531..00000000000
--- a/board/overo/common.c
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Maintainer : Steve Sakoman <steve@sakoman.com>
- *
- * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- */
-#include <twl4030.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TWL4030_I2C_BUS 0
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OVERO;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#define MUX_OVERO() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
- /* - MMC1_WP*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
- /* BT_NRESET*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
- /* - USBH_CPEN*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
- /* - USBH_RESET*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
- /* - W2W_NRESET*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
- /* die to die */\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-/*
- * Routine: get_board_revision
- * Description: Returns the board revision
- */
-int get_board_revision(void)
-{
- int revision;
-
- if (!gpio_request(112, "") &&
- !gpio_request(113, "") &&
- !gpio_request(115, "")) {
-
- gpio_direction_input(112);
- gpio_direction_input(113);
- gpio_direction_input(115);
-
- revision = gpio_get_value(115) << 2 |
- gpio_get_value(113) << 1 |
- gpio_get_value(112);
- } else {
- puts("Error: unable to acquire board revision GPIOs\n");
- revision = -1;
- }
-
- return revision;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_OVERO();
-}
diff --git a/board/overo/overo.c b/board/overo/overo.c
deleted file mode 100644
index 8fa41f81550..00000000000
--- a/board/overo/overo.c
+++ /dev/null
@@ -1,420 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Maintainer : Steve Sakoman <steve@sakoman.com>
- *
- * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <linux/mtd/rawnand.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include "overo.h"
-
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-
-#define TWL4030_I2C_BUS 0
-#define EXPANSION_EEPROM_I2C_BUS 2
-#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
-
-#define GUMSTIX_EMPTY_EEPROM 0x0
-
-#define GUMSTIX_SUMMIT 0x01000200
-#define GUMSTIX_TOBI 0x02000200
-#define GUMSTIX_TOBI_DUO 0x03000200
-#define GUMSTIX_PALO35 0x04000200
-#define GUMSTIX_PALO43 0x05000200
-#define GUMSTIX_CHESTNUT43 0x06000200
-#define GUMSTIX_PINTO 0x07000200
-#define GUMSTIX_GALLOP43 0x08000200
-#define GUMSTIX_ALTO35 0x09000200
-#define GUMSTIX_STAGECOACH 0x0A000200
-#define GUMSTIX_THUMBO 0x0B000200
-#define GUMSTIX_TURTLECORE 0x0C000200
-#define GUMSTIX_ARBOR43C 0x0D000200
-
-#define ETTUS_USRP_E 0x01000300
-
-#define GUMSTIX_NO_EEPROM 0xffffffff
-
-static struct {
- unsigned int device_vendor;
- unsigned char revision;
- unsigned char content;
- char fab_revision[8];
- char env_var[16];
- char env_setting[64];
-} expansion_config = {0x0};
-
-static const struct ns16550_platdata overo_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(overo_uart) = {
- "ns16550_serial",
- &overo_serial
-};
-
-/*
- * Routine: get_sdio2_config
- * Description: Return information about the wifi module connection
- * Returns 0 if the module connects though a level translator
- * Returns 1 if the module connects directly
- */
-int get_sdio2_config(void)
-{
- int sdio_direct;
-
- if (!gpio_request(130, "") && !gpio_request(139, "")) {
-
- gpio_direction_output(130, 0);
- gpio_direction_input(139);
-
- sdio_direct = 1;
- gpio_set_value(130, 0);
- if (gpio_get_value(139) == 0) {
- gpio_set_value(130, 1);
- if (gpio_get_value(139) == 1)
- sdio_direct = 0;
- }
-
- gpio_direction_input(130);
- } else {
- puts("Error: unable to acquire sdio2 clk GPIOs\n");
- sdio_direct = -1;
- }
-
- return sdio_direct;
-}
-
-/*
- * Routine: get_expansion_id
- * Description: This function checks for expansion board by checking I2C
- * bus 2 for the availability of an AT24C01B serial EEPROM.
- * returns the device_vendor field from the EEPROM
- */
-unsigned int get_expansion_id(void)
-{
- if (expansion_config.device_vendor != 0x0)
- return expansion_config.device_vendor;
-
- i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
-
- /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
- if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
- i2c_set_bus_num(TWL4030_I2C_BUS);
- return GUMSTIX_NO_EEPROM;
- }
-
- /* read configuration data */
- i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
- sizeof(expansion_config));
-
- i2c_set_bus_num(TWL4030_I2C_BUS);
-
- return expansion_config.device_vendor;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- unsigned int expansion_id;
-
- twl4030_power_init();
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-
- printf("Board revision: %d\n", get_board_revision());
-
- switch (get_sdio2_config()) {
- case 0:
- puts("Tranceiver detected on mmc2\n");
- MUX_OVERO_SDIO2_TRANSCEIVER();
- break;
- case 1:
- puts("Direct connection on mmc2\n");
- MUX_OVERO_SDIO2_DIRECT();
- break;
- default:
- puts("Unable to detect mmc2 connection type\n");
- }
-
- expansion_id = get_expansion_id();
- switch (expansion_id) {
- case GUMSTIX_SUMMIT:
- printf("Recognized Summit expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("defaultdisplay", "dvi");
- env_set("expansionname", "summit");
- break;
- case GUMSTIX_TOBI:
- printf("Recognized Tobi expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("defaultdisplay", "dvi");
- env_set("expansionname", "tobi");
- break;
- case GUMSTIX_TOBI_DUO:
- printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("expansionname", "tobiduo");
- break;
- case GUMSTIX_PALO35:
- printf("Recognized Palo35 expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("defaultdisplay", "lcd35");
- env_set("expansionname", "palo35");
- break;
- case GUMSTIX_PALO43:
- printf("Recognized Palo43 expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("defaultdisplay", "lcd43");
- env_set("expansionname", "palo43");
- break;
- case GUMSTIX_CHESTNUT43:
- printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("defaultdisplay", "lcd43");
- env_set("expansionname", "chestnut43");
- break;
- case GUMSTIX_PINTO:
- printf("Recognized Pinto expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- break;
- case GUMSTIX_GALLOP43:
- printf("Recognized Gallop43 expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- env_set("defaultdisplay", "lcd43");
- env_set("expansionname", "gallop43");
- break;
- case GUMSTIX_ALTO35:
- printf("Recognized Alto35 expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- MUX_ALTO35();
- env_set("defaultdisplay", "lcd35");
- env_set("expansionname", "alto35");
- break;
- case GUMSTIX_STAGECOACH:
- printf("Recognized Stagecoach expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- break;
- case GUMSTIX_THUMBO:
- printf("Recognized Thumbo expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- break;
- case GUMSTIX_TURTLECORE:
- printf("Recognized Turtlecore expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- break;
- case GUMSTIX_ARBOR43C:
- printf("Recognized Arbor43C expansion board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- MUX_ARBOR43C();
- env_set("defaultdisplay", "lcd43");
- env_set("expansionname", "arbor43c");
- break;
- case ETTUS_USRP_E:
- printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_GUMSTIX();
- MUX_USRP_E();
- env_set("defaultdisplay", "dvi");
- break;
- case GUMSTIX_NO_EEPROM:
- case GUMSTIX_EMPTY_EEPROM:
- puts("No or empty EEPROM on expansion board\n");
- MUX_GUMSTIX();
- env_set("expansionname", "tobi");
- break;
- default:
- printf("Unrecognized expansion board 0x%08x\n", expansion_id);
- break;
- }
-
- if (expansion_config.content == 1)
- env_set(expansion_config.env_var, expansion_config.env_setting);
-
- omap_die_id_display();
-
- if (get_cpu_family() == CPU_OMAP34XX)
- env_set("boardname", "overo");
- else
- env_set("boardname", "overo-storm");
-
- return 0;
-}
-
-#if defined(CONFIG_CMD_NET)
-/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
-static const u32 gpmc_lan_config[] = {
- NET_LAN9221_GPMC_CONFIG1,
- NET_LAN9221_GPMC_CONFIG2,
- NET_LAN9221_GPMC_CONFIG3,
- NET_LAN9221_GPMC_CONFIG4,
- NET_LAN9221_GPMC_CONFIG5,
- NET_LAN9221_GPMC_CONFIG6,
- /*CONFIG7- computed as params */
-};
-
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-}
-
-/*
- * Routine: reset_net_chip
- * Description: Reset the Ethernet hardware.
- */
-static void reset_net_chip(void)
-{
- /* Make GPIO 64 as output pin and send a magic pulse through it */
- if (!gpio_request(64, "")) {
- gpio_direction_output(64, 0);
- gpio_set_value(64, 1);
- udelay(1);
- gpio_set_value(64, 0);
- udelay(1);
- gpio_set_value(64, 1);
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- unsigned int expansion_id;
- int rc = 0;
-
-#ifdef CONFIG_SMC911X
- expansion_id = get_expansion_id();
- switch (expansion_id) {
- case GUMSTIX_TOBI_DUO:
- /* second lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
- 0x2B000000, GPMC_SIZE_16M);
- /* no break */
- case GUMSTIX_TOBI:
- case GUMSTIX_CHESTNUT43:
- case GUMSTIX_STAGECOACH:
- case GUMSTIX_NO_EEPROM:
- case GUMSTIX_EMPTY_EEPROM:
- /* first lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
- 0x2C000000, GPMC_SIZE_16M);
-
- setup_net_chip();
- reset_net_chip();
-
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- break;
- default:
- break;
- }
-#endif
-
- return rc;
-}
-#endif
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#if defined(CONFIG_USB_EHCI_HCD)
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-#define GUMSTIX_GPIO_USBH_CPEN 168
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- /* Enable USB power */
- if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
- gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
-
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(void)
-{
- /* Disable USB power */
- gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
- gpio_free(GUMSTIX_GPIO_USBH_CPEN);
-
- return omap_ehci_hcd_stop();
-}
-
-#endif /* CONFIG_USB_EHCI_HCD */
diff --git a/board/overo/overo.h b/board/overo/overo.h
deleted file mode 100644
index 513a3e3d632..00000000000
--- a/board/overo/overo.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Steve Sakoman <steve@sakoman.com>
- */
-#ifndef _OVERO_H_
-#define _OVERO_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "Gumstix Overo board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#else
- "NAND",
-#endif
-};
-
-int get_board_revision(void);
-
-/* overo revisions */
-#define REVISION_0 0x0
-#define REVISION_1 0x1
-#define REVISION_2 0x2
-#define REVISION_3 0x3
-#define REVISION_4 0x4
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_GUMSTIX() \
- /*GPMC*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
- /* - CAM_IRQ*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- /* - SMSC911X_NRES*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
- /* - PEN_DOWN*/\
- /*Bluetooth*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
- /* - LAN_INTR */\
- /*Control and debug */\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
-
-#define MUX_OVERO_SDIO2_DIRECT() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
-
-#define MUX_OVERO_SDIO2_TRANSCEIVER() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
-
-#define MUX_USRP_E() \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
-
-#define MUX_ALTO35() \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
- MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\
-
-#define MUX_ARBOR43C() \
- MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\
- MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\
-
-#endif
diff --git a/board/overo/spl.c b/board/overo/spl.c
deleted file mode 100644
index d577e00fbca..00000000000
--- a/board/overo/spl.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Maintainer : Steve Sakoman <steve@sakoman.com>
- *
- * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- */
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include "overo.h"
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->mr = MICRON_V_MR_165;
- switch (get_board_revision()) {
- case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
- timings->mcfg = MICRON_V_MCFG_165(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
- case REVISION_4:
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- break;
- case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- break;
- case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
- timings->mcfg = MCFG(512 << 20, 15);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- break;
- default:
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
-}
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
deleted file mode 100644
index 1e7e5f7d835..00000000000
--- a/configs/omap3_overo_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_OMAP3_OVERO=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Overo # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1792k(u-boot),256k(environ),8m(linux),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x2C000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_FAT_WRITE=y
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
deleted file mode 100644
index 35f3af4ae9a..00000000000
--- a/include/configs/omap3_overo.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for the Gumstix Overo board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/ti_omap3_common.h>
-/*
- * We are only ever GP parts and will utilize all of the "downloaded image"
- * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
- */
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE 0x40200000
-
-/* call misc_init_r */
-
-/* pass the revision tag */
-#define CONFIG_REVISION_TAG
-
-/* override size of malloc() pool */
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
-/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
- * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15))
-
-/* I2C Support */
-
-/* TWL4030 LED */
-
-/* USB EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
-
-/* commands to include */
-
-#ifdef CONFIG_NAND
-/* NAND block size is 128 KiB. Synchronize these values with
- * overo_nand_partitions in mach-omap2/board-overo.c in Linux:
- * xloader 4 * NAND_BLOCK_SIZE = 512 KiB
- * uboot 14 * NAND_BLOCK_SIZE = 1792 KiB
- * uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB
- * linux 64 * NAND_BLOCK_SIZE = 8 MiB
- * rootfs remainder
- */
-#endif /* CONFIG_NAND */
-
-/* Board NAND Info. */
-/* Environment information */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "usbtty=cdc_acm\0" \
- "console=ttyO2,115200n8\0" \
- "mpurate=auto\0" \
- "optargs=\0" \
- "vram=12M\0" \
- "dvimode=1024x768MR-16 at 60\0" \
- "defaultdisplay=dvi\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nandroot=ubi0:rootfs ubi.mtd=4\0" \
- "nandrootfstype=ubifs\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running boot script from mmc ...; " \
- "source ${loadaddr}\0" \
- "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t ${loadaddr} ${filesize}\0" \
- "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcbootfdt=echo Booting with DT from mmc ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "if nand read ${loadaddr} linux; then " \
- "bootm ${loadaddr};" \
- "fi;\0" \
- "nanddtsboot=echo Booting from nand with DTS...; " \
- "run nandargs; " \
- "ubi part rootfs; "\
- "ubifsmount ubi0:rootfs; "\
- "run loadubifdt; "\
- "run loadubizimage; "\
- "bootz ${loadaddr} - ${fdtaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "fi;" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loaduimage; then " \
- "run mmcboot;" \
- "fi;" \
- "if run loadzimage; then " \
- "if test -z \"${fdtfile}\"; then " \
- "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
- "fi;" \
- "if run loadfdt; then " \
- "run mmcbootfdt;" \
- "fi;" \
- "fi;" \
- "fi;" \
- "run nandboot; " \
- "if test -z \"${fdtfile}\"; then "\
- "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
- "fi;" \
- "run nanddtsboot; " \
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-/* FLASH and environment organization */
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#endif
-
-/* Monitor@start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x240000
-#define CONFIG_ENV_ADDR 0x240000
-
-/* Initial RAM setup */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
- 13, 14, 16, 17, 18, 19, 20, 21, 22, \
- 23, 24, 25, 26, 27, 28, 30, 31, 32, \
- 33, 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 44, 45, 46, 47, 48, 49, 50, 51, \
- 52, 53, 54, 55, 56}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 24/93] arm: Remove am335x_boneblack board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (22 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 23/93] arm: Remove omap3_overo board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 25/93] arm: Remove warp7 board Simon Glass
` (73 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/Kconfig | 1 -
board/ti/am335x/Kconfig | 24 -
board/ti/am335x/MAINTAINERS | 12 -
board/ti/am335x/Makefile | 11 -
board/ti/am335x/README | 205 -----
board/ti/am335x/board.c | 1073 ----------------------
board/ti/am335x/board.h | 97 --
board/ti/am335x/mux.c | 413 ---------
board/ti/am335x/u-boot.lds | 164 ----
configs/am335x_boneblack_defconfig | 51 -
configs/am335x_boneblack_vboot_defconfig | 56 --
configs/am335x_evm_defconfig | 64 --
configs/am335x_evm_nor_defconfig | 53 --
configs/am335x_evm_norboot_defconfig | 50 -
configs/am335x_evm_spiboot_defconfig | 48 -
configs/am335x_evm_usbspl_defconfig | 56 --
include/configs/am335x_evm.h | 343 -------
17 files changed, 2721 deletions(-)
delete mode 100644 board/ti/am335x/Kconfig
delete mode 100644 board/ti/am335x/MAINTAINERS
delete mode 100644 board/ti/am335x/Makefile
delete mode 100644 board/ti/am335x/README
delete mode 100644 board/ti/am335x/board.c
delete mode 100644 board/ti/am335x/board.h
delete mode 100644 board/ti/am335x/mux.c
delete mode 100644 board/ti/am335x/u-boot.lds
delete mode 100644 configs/am335x_boneblack_defconfig
delete mode 100644 configs/am335x_boneblack_vboot_defconfig
delete mode 100644 configs/am335x_evm_defconfig
delete mode 100644 configs/am335x_evm_nor_defconfig
delete mode 100644 configs/am335x_evm_norboot_defconfig
delete mode 100644 configs/am335x_evm_spiboot_defconfig
delete mode 100644 configs/am335x_evm_usbspl_defconfig
delete mode 100644 include/configs/am335x_evm.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 438cbb30419..3b4cb157d4d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -183,7 +183,6 @@ source "board/siemens/rut/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
-source "board/ti/am335x/Kconfig"
source "board/compulab/cm_t335/Kconfig"
config SPL_LDSCRIPT
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
deleted file mode 100644
index b66ca1a5798..00000000000
--- a/board/ti/am335x/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if TARGET_AM335X_EVM
-
-config SYS_BOARD
- default "am335x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "am335x_evm"
-
-config NOR
- bool "Support for NOR flash"
- help
- The AM335x SoC supports having a NOR flash connected to the GPMC.
- In practice this is seen as a NOR flash module connected to the
- "memory cape" for the BeagleBone family.
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
deleted file mode 100644
index c99e06dc10b..00000000000
--- a/board/ti/am335x/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-AM335X BOARD
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-F: board/ti/am335x/
-F: include/configs/am335x_evm.h
-F: configs/am335x_boneblack_defconfig
-F: configs/am335x_boneblack_vboot_defconfig
-F: configs/am335x_evm_defconfig
-F: configs/am335x_evm_nor_defconfig
-F: configs/am335x_evm_norboot_defconfig
-F: configs/am335x_evm_spiboot_defconfig
-F: configs/am335x_evm_usbspl_defconfig
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
deleted file mode 100644
index c34b9b1dd8a..00000000000
--- a/board/ti/am335x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/board/ti/am335x/README b/board/ti/am335x/README
deleted file mode 100644
index 19e0eccbac9..00000000000
--- a/board/ti/am335x/README
+++ /dev/null
@@ -1,205 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'am335x_evm' build, and some of
-the related build targets (am335x_evm_uartN, etc).
-
-Hardware
-========
-
-The binary produced by this board supports, based on parsing of the EEPROM
-documented in TI's reference designs:
-- AM335x GP EVM
-- AM335x EVM SK
-- Beaglebone White
-- Beaglebone Black
-
-Customization
-=============
-
-Given that all of the above boards are reference platforms (and the
-Beaglebone platforms are OSHA), it is likely that this platform code and
-configuration will be used as the basis of a custom platform. It is
-worth noting that aside from things such as NAND or MMC only being
-required if a custom platform makes use of these blocks, the following
-are required, depending on design:
-
-- GPIO is only required if DDR3 power is controlled in a way similar to
- EVM SK
-- SPI is only required for SPI flash, or exposing the SPI bus.
-
-The following blocks are required:
-- I2C, to talk with the PMIC and ensure that we do not run afoul of
- errata 1.0.24.
-
-When removing options as part of customization,
-CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
-needs and to remove no longer relevant options as in some cases we
-define additional text blocks (such as for NAND or DFU strings). Also
-note that all of the SPL options are grouped together, rather than with
-the IP blocks, so both areas will need their choices updated to reflect
-the custom design.
-
-NAND
-====
-
-The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
-this example to program the NAND we assume that an SD card has been
-inserted with the files to write in the first SD slot and that mtdparts
-have been configured correctly for the board. All images are first loaded
-into memory, then written to NAND.
-
-Step-1: Building u-boot for NAND boot
- Set following CONFIGxx options for NAND device.
- CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
- CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
- CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
- CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
- CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
-
-Step-2: Flashing NAND via MMC/SD
- # select BOOTSEL to MMC/SD boot and boot from MMC/SD card
- U-Boot # mmc rescan
- # erase flash
- U-Boot # nand erase.chip
- U-Boot # env default -f -a
- U-Boot # saveenv
- # flash MLO. Redundant copies of MLO are kept for failsafe
- U-Boot # load mmc 0 0x82000000 MLO
- U-Boot # nand write 0x82000000 0x00000 0x20000
- U-Boot # nand write 0x82000000 0x20000 0x20000
- U-Boot # nand write 0x82000000 0x40000 0x20000
- U-Boot # nand write 0x82000000 0x60000 0x20000
- # flash u-boot.img
- U-Boot # load mmc 0 0x82000000 u-boot.img
- U-Boot # nand write 0x82000000 0x80000 0x60000
- # flash kernel image
- U-Boot # load mmc 0 0x82000000 uImage
- U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
- # flash filesystem image
- U-Boot # load mmc 0 0x82000000 filesystem.img
- U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
-
-Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
- The device should boot from images flashed on NAND device.
-
-NOR
-===
-
-The Beaglebone White can be equipped with a "memory cape" that in turn can
-have a NOR module plugged into it. In this case it is then possible to
-program and boot from NOR. Note that due to how U-Boot is designed we
-must build a specific version of U-Boot that knows we have NOR flash. This
-build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
-build that will assume that the environment is on NOR rather than NAND. In
-the following example we assume that and SD card has been populated with
-MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
-'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a
-binary must be written to the start of NOR, with no header or similar
-prepended. In the following example we use a size of 512KiB (0x80000)
-as that is how much space we set aside before the environment, as per
-the config file.
-
-U-Boot # mmc rescan
-U-Boot # load mmc 0 ${loadaddr} u-boot.bin
-U-Boot # protect off 08000000 +80000
-U-Boot # erase 08000000 +80000
-U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
-
-Falcon Mode
-===========
-
-The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
-eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is
-to read a 'c' on the console while in SPL at any point prior to loading the
-OS payload (so as soon as possible) to opt to booting full U-Boot. Also
-note that while one can program Falcon Mode "in place" great care needs to
-be taken by the user to not 'brick' their setup. As these are all eval
-boards with multiple boot methods, recovery should not be an issue in this
-worst-case however.
-
-Falcon Mode: eMMC
-=================
-
-The recommended layout in this case is:
-
-MMC BLOCKS |--------------------------------| LOCATION IN BYTES
-0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
-0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
-0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
-0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
-0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
-0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
-0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
-
-Note that when we run 'spl export' it will prepare to boot the kernel.
-This includes relocation of the uImage from where we loaded it to the entry
-point defined in the header. As these locations overlap by default, it
-would leave us with an image that if written to MMC will not boot, so
-instead of using the loadaddr variable we use 0x81000000 in the following
-example. In this example we are loading from the network, for simplicity,
-and assume a valid partition table already exists and 'mmc dev' has already
-been run to select the correct device. Also note that if you previously
-had a FAT partition (such as on a Beaglebone Black) it is not enough to
-write garbage into the area, you must delete it from the partition table
-first.
-
-# Ensure we are able to talk with this mmc device
-U-Boot # mmc rescan
-U-Boot # tftp 81000000 am335x/MLO
-# Write to two of the backup locations ROM uses
-U-Boot # mmc write 81000000 100 100
-U-Boot # mmc write 81000000 200 100
-# Write U-Boot to the location set in the config
-U-Boot # tftp 81000000 am335x/u-boot.img
-U-Boot # mmc write 81000000 300 400
-# Load kernel and device tree into memory, perform export
-U-Boot # tftp 81000000 am335x/uImage
-U-Boot # run findfdt
-U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt 81000000 - ${fdtaddr}
-# Write the updated device tree to MMC
-U-Boot # mmc write ${fdtaddr} 80 80
-# Write the uImage to MMC
-U-Boot # mmc write 81000000 900 2000
-
-Falcon Mode: FAT SD cards
-=========================
-
-In this case the additional file is written to the filesystem. In this
-example we assume that the uImage and device tree to be used are already on
-the FAT filesystem (only the uImage MUST be for this to function
-afterwards) along with a Falcon Mode aware MLO and the FAT partition has
-already been created and marked bootable:
-
-U-Boot # mmc rescan
-# Load kernel and device tree into memory, perform export
-U-Boot # load mmc 0:1 ${loadaddr} uImage
-U-Boot # run findfdt
-U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-
-This will print a number of lines and then end with something like:
- Using Device Tree in place at 80f80000, end 80f85928
- Using Device Tree in place at 80f80000, end 80f88928
-So then you:
-
-U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
-
-Falcon Mode: NAND
-=================
-
-In this case the additional data is written to another partition of the
-NAND. In this example we assume that the uImage and device tree to be are
-already located on the NAND somewhere (such as filesystem or mtd partition)
-along with a Falcon Mode aware MLO written to the correct locations for
-booting and mtdparts have been configured correctly for the board:
-
-U-Boot # nand read ${loadaddr} kernel
-U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
-U-Boot # run nandargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-U-Boot # nand erase.part u-boot-spl-os
-U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
deleted file mode 100644
index 13845251afb..00000000000
--- a/board/ti/am335x/board.c
+++ /dev/null
@@ -1,1073 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for TI AM335X based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <spl.h>
-#include <serial.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk_synthesizer.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/omap_mmc.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <power/tps65217.h>
-#include <power/tps65910.h>
-#include <environment.h>
-#include <watchdog.h>
-#include <environment.h>
-#include "../common/board_detect.h"
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
-#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
-#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
-#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
-#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
-#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
-#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
-#define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
-#define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
-#define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
-
-#define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
-#define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
-
-#define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
-#define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
-
-/*
- * Read header information from EEPROM into global structure.
- */
-#ifdef CONFIG_TI_I2C_BOARD_DETECT
-void do_board_detect(void)
-{
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS))
- printf("ti_i2c_eeprom_init failed\n");
-}
-#endif
-
-#ifndef CONFIG_DM_SERIAL
-struct serial_device *default_serial_console(void)
-{
- if (board_is_icev2())
- return &eserial4_device;
- else
- return &eserial1_device;
-}
-#endif
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-static const struct ddr_data ddr2_data = {
- .datardsratio0 = MT47H128M16RT25E_RD_DQS,
- .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
- .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
- .cmd0csratio = MT47H128M16RT25E_RATIO,
-
- .cmd1csratio = MT47H128M16RT25E_RATIO,
-
- .cmd2csratio = MT47H128M16RT25E_RATIO,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
- .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
- .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
- .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
- .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
- .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
-};
-
-static const struct emif_regs ddr2_evm_emif_reg_data = {
- .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
- .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
- .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
- .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
- .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
- .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
- .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41J128MJT125_RD_DQS,
- .datawdsratio0 = MT41J128MJT125_WR_DQS,
- .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
- .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_beagleblack_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_evm_data = {
- .datardsratio0 = MT41J512M8RH125_RD_DQS,
- .datawdsratio0 = MT41J512M8RH125_WR_DQS,
- .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
- .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_icev2_data = {
- .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
- .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
- .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
- .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41J128MJT125_RATIO,
- .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J128MJT125_RATIO,
- .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J128MJT125_RATIO,
- .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
- .cmd0csratio = MT41J512M8RH125_RATIO,
- .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J512M8RH125_RATIO,
- .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J512M8RH125_RATIO,
- .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
- .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
- .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
-
- .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
- .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
-
- .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
- .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41J128MJT125_EMIF_SDCFG,
- .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
- .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
- .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
- .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
- .zq_config = MT41J128MJT125_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-static struct emif_regs ddr3_beagleblack_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-static struct emif_regs ddr3_evm_emif_reg_data = {
- .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
- .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
- .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
- .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
- .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
- .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
- .zq_config = MT41J512M8RH125_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-static struct emif_regs ddr3_icev2_emif_reg_data = {
- .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
- .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
- .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
- .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
- .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
- .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
- .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
- PHY_EN_DYN_PWRDN,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-#endif
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_load();
- if (env_get_yesno("boot_os") != 1)
- return 1;
-#endif
-
- return 0;
-}
-#endif
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- int ind = get_sys_clk_index();
-
- if (board_is_evm_sk())
- return &dpll_ddr3_303MHz[ind];
- else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
- return &dpll_ddr3_400MHz[ind];
- else if (board_is_evm_15_or_later())
- return &dpll_ddr3_303MHz[ind];
- else
- return &dpll_ddr2_266MHz[ind];
-}
-
-static u8 bone_not_connected_to_ac_power(void)
-{
- if (board_is_bone()) {
- uchar pmic_status_reg;
- if (tps65217_reg_read(TPS65217_STATUS,
- &pmic_status_reg))
- return 1;
- if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
- puts("No AC power, switching to default OPP\n");
- return 1;
- }
- }
- return 0;
-}
-
-const struct dpll_params *get_dpll_mpu_params(void)
-{
- int ind = get_sys_clk_index();
- int freq = am335x_get_efuse_mpu_max_freq(cdev);
-
- if (bone_not_connected_to_ac_power())
- freq = MPUPLL_M_600;
-
- if (board_is_pb() || board_is_bone_lt())
- freq = MPUPLL_M_1000;
-
- switch (freq) {
- case MPUPLL_M_1000:
- return &dpll_mpu_opp[ind][5];
- case MPUPLL_M_800:
- return &dpll_mpu_opp[ind][4];
- case MPUPLL_M_720:
- return &dpll_mpu_opp[ind][3];
- case MPUPLL_M_600:
- return &dpll_mpu_opp[ind][2];
- case MPUPLL_M_500:
- return &dpll_mpu_opp100;
- case MPUPLL_M_300:
- return &dpll_mpu_opp[ind][0];
- }
-
- return &dpll_mpu_opp[ind][0];
-}
-
-static void scale_vcores_bone(int freq)
-{
- int usb_cur_lim, mpu_vdd;
-
- /*
- * Only perform PMIC configurations if board rev > A1
- * on Beaglebone White
- */
- if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
- return;
-
- if (i2c_probe(TPS65217_CHIP_PM))
- return;
-
- /*
- * On Beaglebone White we need to ensure we have AC power
- * before increasing the frequency.
- */
- if (bone_not_connected_to_ac_power())
- freq = MPUPLL_M_600;
-
- /*
- * Override what we have detected since we know if we have
- * a Beaglebone Black it supports 1GHz.
- */
- if (board_is_pb() || board_is_bone_lt())
- freq = MPUPLL_M_1000;
-
- switch (freq) {
- case MPUPLL_M_1000:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
- break;
- case MPUPLL_M_800:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
- break;
- case MPUPLL_M_720:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
- break;
- case MPUPLL_M_600:
- case MPUPLL_M_500:
- case MPUPLL_M_300:
- default:
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
- break;
- }
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_POWER_PATH,
- usb_cur_lim,
- TPS65217_USB_INPUT_CUR_LIMIT_MASK))
- puts("tps65217_reg_write failure\n");
-
- /* Set DCDC3 (CORE) voltage to 1.10V */
- if (tps65217_voltage_update(TPS65217_DEFDCDC3,
- TPS65217_DCDC_VOLT_SEL_1100MV)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
-
- /* Set DCDC2 (MPU) voltage */
- if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
-
- /*
- * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
- * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
- */
- if (board_is_bone()) {
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS1,
- TPS65217_LDO_VOLTAGE_OUT_3_3,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
- } else {
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS1,
- TPS65217_LDO_VOLTAGE_OUT_1_8,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
- }
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS2,
- TPS65217_LDO_VOLTAGE_OUT_3_3,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
-}
-
-void scale_vcores_generic(int freq)
-{
- int sil_rev, mpu_vdd;
-
- /*
- * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
- * MPU frequencies we support we use a CORE voltage of
- * 1.10V. For MPU voltage we need to switch based on
- * the frequency we are running at.
- */
- if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
- return;
-
- /*
- * Depending on MPU clock and PG we will need a different
- * VDD to drive at that speed.
- */
- sil_rev = readl(&cdev->deviceid) >> 28;
- mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
-
- /* Tell the TPS65910 to use i2c */
- tps65910_set_i2c_control();
-
- /* First update MPU voltage. */
- if (tps65910_voltage_update(MPU, mpu_vdd))
- return;
-
- /* Second, update the CORE voltage. */
- if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
- return;
-
-}
-
-void gpi2c_init(void)
-{
- /* When needed to be invoked prior to BSS initialization */
- static bool first_time = true;
-
- if (first_time) {
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
- first_time = false;
- }
-}
-
-void scale_vcores(void)
-{
- int freq;
-
- gpi2c_init();
- freq = am335x_get_efuse_mpu_max_freq(cdev);
-
- if (board_is_beaglebonex())
- scale_vcores_bone(freq);
- else
- scale_vcores_generic(freq);
-}
-
-void set_uart_mux_conf(void)
-{
-#if CONFIG_CONS_INDEX == 1
- enable_uart0_pin_mux();
-#elif CONFIG_CONS_INDEX == 2
- enable_uart1_pin_mux();
-#elif CONFIG_CONS_INDEX == 3
- enable_uart2_pin_mux();
-#elif CONFIG_CONS_INDEX == 4
- enable_uart3_pin_mux();
-#elif CONFIG_CONS_INDEX == 5
- enable_uart4_pin_mux();
-#elif CONFIG_CONS_INDEX == 6
- enable_uart5_pin_mux();
-#endif
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-const struct ctrl_ioregs ioregs_evmsk = {
- .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs_bonelt = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs_evm15 = {
- .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
- if (board_is_evm_sk()) {
- /*
- * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
- * This is safe enough to do on older revs.
- */
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
- }
-
- if (board_is_icev2()) {
- gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
- }
-
- if (board_is_evm_sk())
- config_ddr(303, &ioregs_evmsk, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
- else if (board_is_pb() || board_is_bone_lt())
- config_ddr(400, &ioregs_bonelt,
- &ddr3_beagleblack_data,
- &ddr3_beagleblack_cmd_ctrl_data,
- &ddr3_beagleblack_emif_reg_data, 0);
- else if (board_is_evm_15_or_later())
- config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
- &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
- else if (board_is_icev2())
- config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
- &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
- 0);
- else if (board_is_gp_evm())
- config_ddr(266, &ioregs, &ddr2_data,
- &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
- else
- config_ddr(266, &ioregs, &ddr2_data,
- &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-}
-#endif
-
-#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
-static void request_and_set_gpio(int gpio, char *name, int val)
-{
- int ret;
-
- ret = gpio_request(gpio, name);
- if (ret < 0) {
- printf("%s: Unable to request %s\n", __func__, name);
- return;
- }
-
- ret = gpio_direction_output(gpio, 0);
- if (ret < 0) {
- printf("%s: Unable to set %s as output\n", __func__, name);
- goto err_free_gpio;
- }
-
- gpio_set_value(gpio, val);
-
- return;
-
-err_free_gpio:
- gpio_free(gpio);
-}
-
-#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
-#define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
-
-/**
- * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
- * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
- * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
- * give 50MHz output for Eth0 and 1.
- */
-static struct clk_synth cdce913_data = {
- .id = 0x81,
- .capacitor = 0x90,
- .mux = 0x6d,
- .pdiv2 = 0x2,
- .pdiv3 = 0x2,
-};
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
- defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
-
-#define MAX_CPSW_SLAVES 2
-
-/* At the moment, we do not want to stop booting for any failures here */
-int ft_board_setup(void *fdt, bd_t *bd)
-{
- const char *slave_path, *enet_name;
- int enetnode, slavenode, phynode;
- struct udevice *ethdev;
- char alias[16];
- u32 phy_id[2];
- int phy_addr;
- int i, ret;
-
- /* phy address fixup needed only on beagle bone family */
- if (!board_is_beaglebonex())
- goto done;
-
- for (i = 0; i < MAX_CPSW_SLAVES; i++) {
- sprintf(alias, "ethernet%d", i);
-
- slave_path = fdt_get_alias(fdt, alias);
- if (!slave_path)
- continue;
-
- slavenode = fdt_path_offset(fdt, slave_path);
- if (slavenode < 0)
- continue;
-
- enetnode = fdt_parent_offset(fdt, slavenode);
- enet_name = fdt_get_name(fdt, enetnode, NULL);
-
- ethdev = eth_get_dev_by_name(enet_name);
- if (!ethdev)
- continue;
-
- phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
-
- /* check for phy_id as well as phy-handle properties */
- ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
- phy_id, 2);
- if (ret == 2) {
- if (phy_id[1] != phy_addr) {
- printf("fixing up phy_id for %s, old: %d, new: %d\n",
- alias, phy_id[1], phy_addr);
-
- phy_id[0] = cpu_to_fdt32(phy_id[0]);
- phy_id[1] = cpu_to_fdt32(phy_addr);
- do_fixup_by_path(fdt, slave_path, "phy_id",
- phy_id, sizeof(phy_id), 0);
- }
- } else {
- phynode = fdtdec_lookup_phandle(fdt, slavenode,
- "phy-handle");
- if (phynode < 0)
- continue;
-
- ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
- if (ret < 0)
- continue;
-
- if (ret != phy_addr) {
- printf("fixing up phy-handle for %s, old: %d, new: %d\n",
- alias, ret, phy_addr);
-
- fdt_setprop_u32(fdt, phynode, "reg",
- cpu_to_fdt32(phy_addr));
- }
- }
- }
-
-done:
- return 0;
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
- gpmc_init();
-#endif
-
-#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
- if (board_is_icev2()) {
- int rv;
- u32 reg;
-
- REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
- /* Make J19 status available on GPIO1_26 */
- REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
-
- REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
- /*
- * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
- * jumpers near the port. Read the jumper value and set
- * the pinmux, external mux and PHY clock accordingly.
- * As jumper line is overridden by PHY RX_DV pin immediately
- * after bootstrap (power-up/reset), we need to sample
- * it during PHY reset using GPIO rising edge detection.
- */
- REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
- /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
- reg = readl(GPIO0_RISINGDETECT) | BIT(11);
- writel(reg, GPIO0_RISINGDETECT);
- reg = readl(GPIO1_RISINGDETECT) | BIT(26);
- writel(reg, GPIO1_RISINGDETECT);
- /* Reset PHYs to capture the Jumper setting */
- gpio_set_value(GPIO_PHY_RESET, 0);
- udelay(2); /* PHY datasheet states 1uS min. */
- gpio_set_value(GPIO_PHY_RESET, 1);
-
- reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
- if (reg) {
- writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
- /* RMII mode */
- printf("ETH0, CPSW\n");
- } else {
- /* MII mode */
- printf("ETH0, PRU\n");
- cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
- }
-
- reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
- if (reg) {
- writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
- /* RMII mode */
- printf("ETH1, CPSW\n");
- gpio_set_value(GPIO_MUX_MII_CTRL, 1);
- } else {
- /* MII mode */
- printf("ETH1, PRU\n");
- cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
- }
-
- /* disable rising edge IRQs */
- reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
- writel(reg, GPIO0_RISINGDETECT);
- reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
- writel(reg, GPIO1_RISINGDETECT);
-
- rv = setup_clock_synthesizer(&cdce913_data);
- if (rv) {
- printf("Clock synthesizer setup failed %d\n", rv);
- return rv;
- }
-
- /* reset PHYs */
- gpio_set_value(GPIO_PHY_RESET, 0);
- udelay(2); /* PHY datasheet states 1uS min. */
- gpio_set_value(GPIO_PHY_RESET, 1);
- }
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#if !defined(CONFIG_SPL_BUILD)
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- char *name = NULL;
-
- if (board_is_bone_lt()) {
- /* BeagleBoard.org BeagleBone Black Wireless: */
- if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
- name = "BBBW";
- }
- /* SeeedStudio BeagleBone Green Wireless */
- if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
- name = "BBGW";
- }
- /* BeagleBoard.org BeagleBone Blue */
- if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
- name = "BBBL";
- }
- }
-
- if (board_is_bbg1())
- name = "BBG1";
- if (board_is_bben())
- name = "BBEN";
- set_board_info_env(name);
-
- /*
- * Default FIT boot on HS devices. Non FIT images are not allowed
- * on HS devices.
- */
- if (get_device_type() == HS_DEVICE)
- env_set("boot_fit", "1");
-#endif
-
-#if !defined(CONFIG_SPL_BUILD)
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-#endif
-
- if (!env_get("serial#")) {
- char *board_serial = env_get("board_serial");
- char *ethaddr = env_get("ethaddr");
-
- if (!board_serial || !strncmp(board_serial, "unknown", 7))
- env_set("serial#", ethaddr);
- else
- env_set("serial#", board_serial);
- }
-
- return 0;
-}
-#endif
-
-#ifndef CONFIG_DM_ETH
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
- defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
-
-/*
- * This function will:
- * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
- * in the environment
- * Perform fixups to the PHY present on certain boards. We only need this
- * function in:
- * - SPL with either CPSW or USB ethernet support
- * - Full U-Boot, with either CPSW or USB ethernet
- * Build in only these cases to avoid warnings about unused variables
- * when we build an SPL that has neither option but full U-Boot will.
- */
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
-#if defined(CONFIG_USB_ETHER) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /*
- * use efuse mac address for USB ethernet as we know that
- * both CPSW and USB ethernet will never be active@the same time
- */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-#endif
-
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-
-#ifdef CONFIG_DRIVER_TI_CPSW
- if (board_is_bone() || board_is_bone_lt() || board_is_bben() ||
- board_is_idk()) {
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_MII;
- } else if (board_is_icev2()) {
- writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[0].phy_addr = 1;
- cpsw_slaves[1].phy_addr = 3;
- } else {
- writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_RGMII;
- }
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-#endif
-
- /*
- *
- * CPSW RGMII Internal Delay Mode is not supported in all PVT
- * operating points. So we must set the TX clock delay feature
- * in the AR8051 PHY. Since we only support a single ethernet
- * device in U-Boot, we only do this for the first instance.
- */
-#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
-#define AR8051_PHY_DEBUG_DATA_REG 0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
-#define AR8051_RGMII_TX_CLK_DLY 0x100
-
- if (board_is_evm_sk() || board_is_gp_evm() || board_is_bben()) {
- const char *devname;
- devname = miiphy_get_current_dev();
-
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
- AR8051_DEBUG_RGMII_CLK_DLY_REG);
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
- AR8051_RGMII_TX_CLK_DLY);
- }
-#endif
-#if defined(CONFIG_USB_ETHER) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
-
- rv = usb_eth_initialize(bis);
- if (rv < 0)
- printf("Error %d registering USB_ETHER\n", rv);
- else
- n += rv;
-#endif
- return n;
-}
-#endif
-
-#endif /* CONFIG_DM_ETH */
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
- return 0;
- else if (board_is_bone() && !strcmp(name, "am335x-bone"))
- return 0;
- else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
- return 0;
- else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
- return 0;
- else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
- return 0;
- else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
- return 0;
- else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
- return 0;
- else
- return -1;
-}
-#endif
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
-{
- secure_boot_verify_image(p_image, p_size);
-}
-#endif
-
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
- .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
- .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
- .cfg.f_min = 400000,
- .cfg.f_max = 52000000,
- .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
- .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-U_BOOT_DEVICE(am335x_mmc0) = {
- .name = "omap_hsmmc",
- .platdata = &am335x_mmc0_platdata,
-};
-
-static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
- .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
- .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
- .cfg.f_min = 400000,
- .cfg.f_max = 52000000,
- .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
- .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-U_BOOT_DEVICE(am335x_mmc1) = {
- .name = "omap_hsmmc",
- .platdata = &am335x_mmc1_platdata,
-};
-#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
deleted file mode 100644
index 48df914af96..00000000000
--- a/board/ti/am335x/board.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * TI AM335x boards information header
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/**
- * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
- * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
- * Synchronization Lost errors. The values are the biggest that work
- * reliably with offered video modes and the memory subsystem on the
- * boards. These register have are briefly documented in "7.3.3.5.2
- * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
- * REG_COS_COUNT_2 do not have any effect on current versions of
- * AM335x.
- */
-#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
-#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
-
-static inline int board_is_bone(void)
-{
- return board_ti_is("A335BONE");
-}
-
-static inline int board_is_bone_lt(void)
-{
- return board_ti_is("A335BNLT");
-}
-
-static inline int board_is_pb(void)
-{
- return board_ti_is("A335PBGL");
-}
-
-static inline int board_is_bbg1(void)
-{
- return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
-}
-
-static inline int board_is_bben(void)
-{
- return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "SE", 2);
-}
-
-static inline int board_is_beaglebonex(void)
-{
- return board_is_pb() || board_is_bone() || board_is_bone_lt() ||
- board_is_bbg1() || board_is_bben();
-}
-
-static inline int board_is_evm_sk(void)
-{
- return board_ti_is("A335X_SK");
-}
-
-static inline int board_is_idk(void)
-{
- return !strncmp(board_ti_get_config(), "SKU#02", 6);
-}
-
-static inline int board_is_gp_evm(void)
-{
- return board_ti_is("A33515BB");
-}
-
-static inline int board_is_evm_15_or_later(void)
-{
- return (board_is_gp_evm() &&
- strncmp("1.5", board_ti_get_rev(), 3) <= 0);
-}
-
-static inline int board_is_icev2(void)
-{
- return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
-}
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(void);
-#endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
deleted file mode 100644
index 41333f93f40..00000000000
--- a/board/ti/am335x/mux.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "../common/board_detect.h"
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
- {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
- {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
- {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
- {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
- {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
- {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
- {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
- {-1},
-};
-
-static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
- {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
- {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
- {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
- {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
- {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
- {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
- {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux spi0_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
- {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
- {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
- {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
- {-1},
-};
-
-static struct module_pin_mux gpio0_7_pin_mux[] = {
- {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
- {-1},
-};
-
-static struct module_pin_mux gpio0_18_pin_mux[] = {
- {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
- {-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
- {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
- {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
- {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
- {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
- {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
- {-1},
-};
-
-#ifdef CONFIG_NAND
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
- {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
- {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
- {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
- {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
- {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
- {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
- {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
-#endif
- {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
- {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
- {-1},
-};
-#elif defined(CONFIG_NOR)
-static struct module_pin_mux bone_norcape_pin_mux[] = {
- {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
- {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
- {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
- {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
- {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
- {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
- {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
- {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
- {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
- {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
- {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
- {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
- {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
- {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
- {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
- {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
- {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
- {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
- {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
- {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
- {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
- {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
- {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
- {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
- {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
- {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
- {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
- {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
- {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
- {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
- {-1},
-};
-#endif
-
-static struct module_pin_mux uart3_icev2_pin_mux[] = {
- {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */
- {-1},
-};
-
-#if defined(CONFIG_NOR_BOOT)
-void enable_norboot_pin_mux(void)
-{
- configure_module_pin_mux(bone_norcape_pin_mux);
-}
-#endif
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart1_pin_mux(void)
-{
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
- configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
- configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
- configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
- configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-/*
- * The AM335x GP EVM, if daughter card(s) are connected, can have 8
- * different profiles. These profiles determine what peripherals are
- * valid and need pinmux to be configured.
- */
-#define PROFILE_NONE 0x0
-#define PROFILE_0 (1 << 0)
-#define PROFILE_1 (1 << 1)
-#define PROFILE_2 (1 << 2)
-#define PROFILE_3 (1 << 3)
-#define PROFILE_4 (1 << 4)
-#define PROFILE_5 (1 << 5)
-#define PROFILE_6 (1 << 6)
-#define PROFILE_7 (1 << 7)
-#define PROFILE_MASK 0x7
-#define PROFILE_ALL 0xFF
-
-/* CPLD registers */
-#define I2C_CPLD_ADDR 0x35
-#define CFG_REG 0x10
-
-static unsigned short detect_daughter_board_profile(void)
-{
- unsigned short val;
-
- if (i2c_probe(I2C_CPLD_ADDR))
- return PROFILE_NONE;
-
- if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
- return PROFILE_NONE;
-
- return (1 << (val & PROFILE_MASK));
-}
-
-void enable_board_pin_mux(void)
-{
- /* Do board-specific muxes. */
- if (board_is_bone()) {
- /* Beaglebone pinmux */
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
-#if defined(CONFIG_NAND)
- configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR)
- configure_module_pin_mux(bone_norcape_pin_mux);
-#else
- configure_module_pin_mux(mmc1_pin_mux);
-#endif
- } else if (board_is_gp_evm()) {
- /* General Purpose EVM */
- unsigned short profile = detect_daughter_board_profile();
- configure_module_pin_mux(rgmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- /* In profile #2 i2c1 and spi0 conflict. */
- if (profile & ~PROFILE_2)
- configure_module_pin_mux(i2c1_pin_mux);
- /* Profiles 2 & 3 don't have NAND */
-#ifdef CONFIG_NAND
- if (profile & ~(PROFILE_2 | PROFILE_3))
- configure_module_pin_mux(nand_pin_mux);
-#endif
- else if (profile == PROFILE_2) {
- configure_module_pin_mux(mmc1_pin_mux);
- configure_module_pin_mux(spi0_pin_mux);
- }
- } else if (board_is_idk()) {
- /* Industrial Motor Control (IDK) */
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_no_cd_pin_mux);
- } else if (board_is_evm_sk()) {
- /* Starter Kit EVM */
- configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(gpio0_7_pin_mux);
- configure_module_pin_mux(rgmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux_sk_evm);
- } else if (board_is_bone_lt()) {
- if (board_is_bben()) {
- /* SanCloud Beaglebone LT Enhanced pinmux */
- configure_module_pin_mux(rgmii1_pin_mux);
- } else {
- /* Beaglebone LT pinmux */
- configure_module_pin_mux(mii1_pin_mux);
- }
- /* Beaglebone LT pinmux */
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
-#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
- configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
- configure_module_pin_mux(bone_norcape_pin_mux);
-#else
- configure_module_pin_mux(mmc1_pin_mux);
-#endif
- } else if (board_is_pb()) {
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- } else if (board_is_icev2()) {
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(gpio0_18_pin_mux);
- configure_module_pin_mux(uart3_icev2_pin_mux);
- configure_module_pin_mux(rmii1_pin_mux);
- configure_module_pin_mux(spi0_pin_mux);
- } else {
- /* Unknown board. We might still be able to boot. */
- puts("Bad EEPROM or unknown board, cannot configure pinmux.");
- }
-}
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
deleted file mode 100644
index 03c1d5f73b3..00000000000
--- a/board/ti/am335x/u-boot.lds
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/ti/am335x/built-in.o (.text*)
- }
-
- /* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(.text.efi_runtime*)
- *(.rodata.efi_runtime*)
- *(.data.efi_runtime*)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
- .text_rest :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
- .efi_runtime_rel : {
- *(.rel*.efi_runtime)
- *(.rel*.efi_runtime.*)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
deleted file mode 100644
index 90ccf9adfe1..00000000000
--- a/configs/am335x_boneblack_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_SPL=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
deleted file mode 100644
index d625599461f..00000000000
--- a/configs/am335x_boneblack_vboot_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_SPL=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_BLK is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
deleted file mode 100644
index b6cd49a469f..00000000000
--- a/configs/am335x_evm_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00080000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_BLK is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_NAND=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_DM_I2C=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_DYNAMIC_CRC_TABLE=y
-CONFIG_RSA=y
-CONFIG_LZO=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
deleted file mode 100644
index 54dc7dff780..00000000000
--- a/configs/am335x_evm_nor_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_NOR=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00080000
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_NAND=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
deleted file mode 100644
index 5d7ccf0c5a7..00000000000
--- a/configs/am335x_evm_norboot_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x08000000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_NOR=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NOR_BOOT=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),4m(kernel),-(rootfs)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_DEVICE=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
deleted file mode 100644
index 10a935f0c0b..00000000000
--- a/configs/am335x_evm_spiboot_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=m25p80-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=m25p80-flash.0:128k(SPL),512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),3464k(kernel),-(rootfs)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
deleted file mode 100644
index ec72538ddc0..00000000000
--- a/configs/am335x_evm_usbspl_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_AM33XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_ETHER=y
-# CONFIG_SPL_YMODEM_SUPPORT is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00080000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_NETCONSOLE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_NAND=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
deleted file mode 100644
index 5d5b09bbd1e..00000000000
--- a/include/configs/am335x_evm.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * am335x_evm.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_AM335X_EVM_H
-#define __CONFIG_AM335X_EVM_H
-
-#include <configs/ti_am335x_common.h>
-#include <linux/sizes.h>
-
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_TIMESTAMP
-#endif
-
-#define CONFIG_SYS_BOOTM_LEN SZ_16M
-
-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-/* Custom script for NOR */
-#define CONFIG_SYS_LDSCRIPT "board/ti/am335x/u-boot.lds"
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE SZ_128K
-
-#ifdef CONFIG_NAND
-#define NANDARGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${fdtaddr} NAND.u-boot-spl-os; " \
- "nand read ${loadaddr} NAND.kernel; " \
- "bootz ${loadaddr} - ${fdtaddr}\0"
-#else
-#define NANDARGS ""
-#endif
-
-#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "setenv mmcdev " #instance"; "\
- "setenv bootpart " #instance":2 ; "\
- "run mmcboot\0"
-
-#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel "=" \
- "run nandboot\0"
-
-#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#if CONFIG_IS_ENABLED(CMD_PXE)
-# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
-#else
-# define BOOT_TARGET_PXE(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_DHCP)
-# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
-#else
-# define BOOT_TARGET_DHCP(func)
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(LEGACY_MMC, legacy_mmc, 0) \
- func(MMC, mmc, 1) \
- func(LEGACY_MMC, legacy_mmc, 1) \
- func(NAND, nand, 0) \
- BOOT_TARGET_PXE(func) \
- BOOT_TARGET_DHCP(func)
-
-#include <config_distro_bootcmd.h>
-
-#ifndef CONFIG_SPL_BUILD
-#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- DEFAULT_MMC_TI_ARGS \
- DEFAULT_FIT_TI_ARGS \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "fdtfile=undefined\0" \
- "console=ttyO0,115200n8\0" \
- "partitions=" \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=bootloader,start=384K,size=1792K," \
- "uuid=${uuid_gpt_bootloader};" \
- "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
- "optargs=\0" \
- "ramroot=/dev/ram0 rw\0" \
- "ramrootfstype=ext2\0" \
- "spiroot=/dev/mtdblock4 rw\0" \
- "spirootfstype=jffs2\0" \
- "spisrcaddr=0xe0000\0" \
- "spiimgsize=0x362000\0" \
- "spibusno=0\0" \
- "spiargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${spiroot} " \
- "rootfstype=${spirootfstype}\0" \
- "ramargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "spiboot=echo Booting from spi ...; " \
- "run spiargs; " \
- "sf probe ${spibusno}:0; " \
- "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
- "bootz ${loadaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
- "findfdt="\
- "if test $board_name = A335BONE; then " \
- "setenv fdtfile am335x-bone.dtb; fi; " \
- "if test $board_name = A335BNLT; then " \
- "setenv fdtfile am335x-boneblack.dtb; fi; " \
- "if test $board_name = A335PBGL; then " \
- "setenv fdtfile am335x-pocketbeagle.dtb; fi; " \
- "if test $board_name = BBBW; then " \
- "setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \
- "if test $board_name = BBG1; then " \
- "setenv fdtfile am335x-bonegreen.dtb; fi; " \
- "if test $board_name = BBGW; then " \
- "setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
- "if test $board_name = BBBL; then " \
- "setenv fdtfile am335x-boneblue.dtb; fi; " \
- "if test $board_name = BBEN; then " \
- "setenv fdtfile am335x-sancloud-bbe.dtb; fi; " \
- "if test $board_name = A33515BB; then " \
- "setenv fdtfile am335x-evm.dtb; fi; " \
- "if test $board_name = A335X_SK; then " \
- "setenv fdtfile am335x-evmsk.dtb; fi; " \
- "if test $board_name = A335_ICE; then " \
- "setenv fdtfile am335x-icev2.dtb; fi; " \
- "if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree to use; fi; \0" \
- "init_console=" \
- "if test $board_name = A335_ICE; then "\
- "setenv console ttyO3,115200n8;" \
- "else " \
- "setenv console ttyO0,115200n8;" \
- "fi;\0" \
- NANDARGS \
- NETARGS \
- DFUARGS \
- BOOTENV
-#endif
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-#define CONFIG_POWER_TPS65910
-
-/* SPL */
-#ifndef CONFIG_NOR_BOOT
-/* Bootcount using the RTC block */
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-/* USB gadget RNDIS */
-#endif
-
-#ifdef CONFIG_NAND
-/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-/* NAND: SPL related configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
-#endif
-#endif /* !CONFIG_NAND */
-
-/*
- * For NOR boot, we must set this to the start of where NOR is mapped
- * in memory.
- */
-
-/*
- * USB configuration. We enable MUSB support, both for host and for
- * gadget. We set USB0 as peripheral and USB1 as host, based on the
- * board schematic and physical port wired to each. Then for host we
- * add mass storage support and for gadget we add both RNDIS ethernet
- * and DFU.
- */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_TIMER
-#undef CONFIG_DM_USB
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
-/* Remove other SPL modes. */
-/* disable host part of MUSB in SPL */
-/* disable EFI partitions and partition UUID support */
-#endif
-
-/* USB Device Firmware Update support */
-#ifndef CONFIG_SPL_BUILD
-#define DFUARGS \
- DFU_ALT_INFO_EMMC \
- DFU_ALT_INFO_MMC \
- DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_NAND
-#endif
-
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x020000 : SPL (128KiB)
- * 0x020000 - 0x0A0000 : U-Boot (512KiB)
- * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
- * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
- * 0x0E0000 - 0x442000 : Linux Kernel
- * 0x442000 - 0x800000 : Userland
- */
-#if defined(CONFIG_SPI_BOOT)
-/* SPL related */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
-#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
-#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
-#elif defined(CONFIG_EMMC_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_SYS_MMC_MAX_DEVICE 2
-#elif defined(CONFIG_NOR_BOOT)
-#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
-#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#endif
-
-/* SPI flash. */
-#define CONFIG_SF_DEFAULT_SPEED 24000000
-
-/* Network. */
-#define CONFIG_PHY_SMSC
-/* Enable Atheros phy driver */
-#define CONFIG_PHY_ATHEROS
-
-/*
- * NOR Size = 16 MiB
- * Number of Sectors/Blocks = 128
- * Sector Size = 128 KiB
- * Word length = 16 bits
- * Default layout:
- * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
- * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
- * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
- * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
- * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
- */
-#if defined(CONFIG_NOR)
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#endif /* NOR support */
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-#define CONFIG_CLOCK_SYNTHESIZER
-#define CLK_SYNTHESIZER_I2C_ADDR 0x65
-#endif
-
-#endif /* ! __CONFIG_AM335X_EVM_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 25/93] arm: Remove warp7 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (23 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 24/93] arm: Remove am335x_boneblack board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 17:56 ` Fabio Estevam
2018-11-19 15:53 ` [U-Boot] [PATCH 26/93] arm: Remove gwventana_gw5904 board Simon Glass
` (72 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx7/Kconfig | 1 -
board/warp7/Kconfig | 23 ----
board/warp7/MAINTAINERS | 7 -
board/warp7/Makefile | 4 -
board/warp7/README | 63 ---------
board/warp7/imximage.cfg | 98 --------------
board/warp7/warp7.c | 237 ----------------------------------
configs/warp7_bl33_defconfig | 41 ------
configs/warp7_defconfig | 52 --------
include/configs/warp7.h | 169 ------------------------
10 files changed, 695 deletions(-)
delete mode 100644 board/warp7/Kconfig
delete mode 100644 board/warp7/MAINTAINERS
delete mode 100644 board/warp7/Makefile
delete mode 100644 board/warp7/README
delete mode 100644 board/warp7/imximage.cfg
delete mode 100644 board/warp7/warp7.c
delete mode 100644 configs/warp7_bl33_defconfig
delete mode 100644 configs/warp7_defconfig
delete mode 100644 include/configs/warp7.h
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 232f33285d4..329a4acaebb 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -69,6 +69,5 @@ source "board/compulab/cl-som-imx7/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
-source "board/warp7/Kconfig"
endif
diff --git a/board/warp7/Kconfig b/board/warp7/Kconfig
deleted file mode 100644
index c089bca2baf..00000000000
--- a/board/warp7/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if TARGET_WARP7
-
-config SYS_BOARD
- default "warp7"
-
-config SYS_CONFIG_NAME
- default "warp7"
-
-config WARP7_ROOT_PART
- int "Partition number to use for root filesystem"
- default 2
- help
- The partition number to use for root filesystem this is the
- partition that is typically specified with root=/dev/sdaX or
- which gets converted into a root=PARTUUID=some_uuid.
-
-config SYS_FDT_ADDR
- hex "FDT load address"
- default 0x83000000
- help
- The address the FDT file should be loaded to.
-
-endif
diff --git a/board/warp7/MAINTAINERS b/board/warp7/MAINTAINERS
deleted file mode 100644
index 55f8c815d46..00000000000
--- a/board/warp7/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-WARP7 BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/warp7/
-F: include/configs/warp7.h
-F: configs/warp7_defconfig
-F: configs/warp7_bl33_defconfig
diff --git a/board/warp7/Makefile b/board/warp7/Makefile
deleted file mode 100644
index 92b0ca9060f..00000000000
--- a/board/warp7/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2016 NXP Semiconductors
-
-obj-y := warp7.o
diff --git a/board/warp7/README b/board/warp7/README
deleted file mode 100644
index 60339da5437..00000000000
--- a/board/warp7/README
+++ /dev/null
@@ -1,63 +0,0 @@
-How to Update U-Boot on Warp7 board
-----------------------------------
-
-Required software on the host PC:
-
-- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
-
-- dfu-util: http://dfu-util.sourceforge.net/releases/ (if you are in a
-Debian distribution then you can get it via libdfu-dev package)
-
-- libusb: http://libusb.org/ (if you are in a Debian distribution
-then you can get it via libusb-dev and libusb-1.0-0-dev)
-
-In U-Boot folder, build U-Boot for Warp7:
-
-$ make mrproper
-$ make warp7_config
-$ make
-
-This will generate the U-Boot binary called u-boot.imx.
-
-Put warp7 board in USB download mode:
-
-Remove the CPU board from the base board then put switch 2 in the upper
-position
-
-Connect a USB to serial adapter between the host PC and warp7
-
-Connect a USB cable between the OTG warp7 port and the host PC
-
-Copy u-boot.imx to the imx_usb_loader folder.
-
-Load u-boot.imx via USB:
-
-$ sudo ./imx_usb u-boot.imx
-
-Then U-Boot should start and its messages will appear in the console program.
-
-Open a terminal program such as minicom
-
-Use the default environment variables:
-
-=> env default -f -a
-=> saveenv
-
-Run the DFU command:
-=> dfu 0 mmc 0
-
-Transfer u-boot.imx that will be flashed into the eMMC:
-
-$ sudo dfu-util -D u-boot.imx -a boot
-
-Then on the U-Boot prompt the following message should be seen after a
-successful upgrade:
-
-#DOWNLOAD ... OK
-Ctrl+C to exit ...
-
-Remove power from the warp7 board.
-
-Put warp7 board into normal boot mode (put the switch 2 in the lower position)
-
-Power up the board and the new updated U-Boot should boot from eMMC
diff --git a/board/warp7/imximage.cfg b/board/warp7/imximage.cfg
deleted file mode 100644
index a6edfdacef3..00000000000
--- a/board/warp7/imximage.cfg
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2016 NXP Semiconductors
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-IMAGE_VERSION 2
-#ifdef CONFIG_SECURE_BOOT
-CSF CONFIG_CSF_SIZE
-#endif
-
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-DATA 4 0x30340004 0x4F400005
-
-DATA 4 0x30391000 0x00000002
-DATA 4 0x307a0000 0x03040008
-DATA 4 0x307a0064 0x00200038
-DATA 4 0x307a0490 0x00000001
-DATA 4 0x307a00d0 0x00350001
-DATA 4 0x307a00dc 0x00c3000a
-DATA 4 0x307a00e0 0x00010000
-DATA 4 0x307a00e4 0x00110006
-DATA 4 0x307a00f4 0x0000033f
-DATA 4 0x307a0100 0x0a0e110b
-DATA 4 0x307a0104 0x00020211
-DATA 4 0x307a0108 0x03060708
-DATA 4 0x307a010c 0x00a0500c
-DATA 4 0x307a0110 0x05020307
-DATA 4 0x307a0114 0x02020404
-DATA 4 0x307a0118 0x02020003
-DATA 4 0x307a011c 0x00000202
-DATA 4 0x307a0120 0x00000202
-
-DATA 4 0x307a0180 0x00600018
-DATA 4 0x307a0184 0x00e00100
-DATA 4 0x307a0190 0x02098205
-DATA 4 0x307a0194 0x00060303
-DATA 4 0x307a01a0 0x80400003
-DATA 4 0x307a01a4 0x00100020
-DATA 4 0x307a01a8 0x80100004
-
-DATA 4 0x307a0200 0x00000015
-DATA 4 0x307a0204 0x00161616
-DATA 4 0x307a0210 0x00000f0f
-DATA 4 0x307a0214 0x04040404
-DATA 4 0x307a0218 0x0f0f0404
-
-DATA 4 0x307a0240 0x06000600
-DATA 4 0x307a0244 0x00000000
-DATA 4 0x30391000 0x00000000
-DATA 4 0x30790000 0x17421e40
-DATA 4 0x30790004 0x10210100
-DATA 4 0x30790008 0x00010000
-DATA 4 0x30790010 0x0007080c
-DATA 4 0x307900b0 0x1010007e
-
-DATA 4 0x3079001C 0x01010000
-DATA 4 0x3079009c 0x00000d6e
-
-DATA 4 0x30790030 0x06060606
-DATA 4 0x30790020 0x0a0a0a0a
-DATA 4 0x30790050 0x01000008
-DATA 4 0x30790050 0x00000008
-DATA 4 0x30790018 0x0000000f
-DATA 4 0x307900c0 0x0e487304
-DATA 4 0x307900c0 0x0e4c7304
-DATA 4 0x307900c0 0x0e4c7306
-DATA 4 0x307900c0 0x0e4c7304
-
-CHECK_BITS_SET 4 0x307900c4 0x1
-
-DATA 4 0x307900c0 0x0e487304
-
-DATA 4 0x30384130 0x00000000
-DATA 4 0x30340020 0x00000178
-DATA 4 0x30384130 0x00000002
-
-CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
deleted file mode 100644
index 3d32b3eb52b..00000000000
--- a/board/warp7/warp7.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 NXP Semiconductors
- * Author: Fabio Estevam <fabio.estevam@nxp.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx7-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/hab.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <asm/arch/crm_regs.h>
-#include <usb.h>
-#include <netdev.h>
-#include <power/pmic.h>
-#include <power/pfuze3000_pmic.h>
-#include "../freescale/common/pfuze.h"
-#include <asm/setup.h>
-#include <asm/bootm.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
- PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
-#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
- .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
- .gp = IMX_GPIO_NR(4, 8),
- },
- .sda = {
- .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
- .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
- .gp = IMX_GPIO_NR(4, 9),
- },
-};
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_SIZE;
-
- /* Subtract the defined OPTEE runtime firmware length */
-#ifdef CONFIG_OPTEE_TZDRAM_SIZE
- gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
-#endif
-
- return 0;
-}
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* Assume uSDHC3 emmc is always present */
- return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-#ifdef CONFIG_POWER
-#define I2C_PMIC 0
-static struct pmic *pfuze;
-int power_init_board(void)
-{
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(I2C_PMIC);
- if (ret)
- return ret;
-
- pfuze = pmic_get("PFUZE3000");
- ret = pmic_probe(pfuze);
- if (ret)
- return ret;
-
- pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
-
- /* disable Low Power Mode during standby mode */
- pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
-
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int ret = 0;
-
-#ifdef CONFIG_USB_ETHER
- ret = usb_eth_initialize(bis);
- if (ret < 0)
- printf("Error %d registering USB ether.\n", ret);
-#endif
-
- return ret;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- #ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- #endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- char *mode;
-
- if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
- mode = "secure";
- else
- mode = "non-secure";
-
-#ifdef CONFIG_OPTEE_TZDRAM_SIZE
- unsigned long optee_start, optee_end;
-
- optee_end = PHYS_SDRAM + PHYS_SDRAM_SIZE;
- optee_start = optee_end - CONFIG_OPTEE_TZDRAM_SIZE;
-
- printf("Board: WARP7 in %s mode OPTEE DRAM 0x%08lx-0x%08lx\n",
- mode, optee_start, optee_end);
-#else
- printf("Board: WARP7 in %s mode\n", mode);
-#endif
-
- return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
- return USB_INIT_DEVICE;
-}
-
-int board_late_init(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-#ifdef CONFIG_SERIAL_TAG
- struct tag_serialnr serialnr;
- char serial_string[0x20];
-#endif
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- /*
- * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
- * since we use PMIC_PWRON to reset the board.
- */
- clrsetbits_le16(&wdog->wcr, 0, 0x10);
-
-#ifdef CONFIG_SECURE_BOOT
- /* Determine HAB state */
- env_set_ulong(HAB_ENABLED_ENVNAME, imx_hab_is_enabled());
-#else
- env_set_ulong(HAB_ENABLED_ENVNAME, 0);
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
- /* Set serial# standard environment variable based on OTP settings */
- get_board_serial(&serialnr);
- snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
- serialnr.low, serialnr.high);
- env_set("serial#", serial_string);
-#endif
-
- return 0;
-}
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
deleted file mode 100644
index a568c6d10e0..00000000000
--- a/configs/warp7_bl33_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX7=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SECURE_BOOT=y
-CONFIG_TARGET_WARP7=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OF_LIBFDT=y
-CONFIG_OPTEE_TZDRAM_SIZE=0x2000000
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
deleted file mode 100644
index 955c7af42af..00000000000
--- a/configs/warp7_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX7=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SECURE_BOOT=y
-CONFIG_TARGET_WARP7=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-# CONFIG_ARMV7_VIRT is not set
-CONFIG_IMX_RDC=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DFU_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_OPTEE=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OF_LIBFDT=y
-CONFIG_OPTEE_LOAD_ADDR=0x84000000
-CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
-CONFIG_OPTEE_TZDRAM_BASE=0x9d000000
-CONFIG_BOOTM_OPTEE=y
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
deleted file mode 100644
index a391dfb5c10..00000000000
--- a/include/configs/warp7.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 NXP Semiconductors
- *
- * Configuration settings for the i.MX7S Warp board.
- */
-
-#ifndef __WARP7_CONFIG_H
-#define __WARP7_CONFIG_H
-
-#include "mx7_common.h"
-#include <imximage.h>
-
-#define PHYS_SDRAM_SIZE SZ_512M
-
-/*
- * If we have defined the OPTEE ram size and not OPTEE it means that we were
- * launched by OPTEE, because of that we shall skip all the low level
- * initialization since it was already done by ATF or OPTEE
- */
-#ifdef CONFIG_OPTEE_TZDRAM_SIZE
-#ifndef CONFIG_OPTEE
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#endif
-
-#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
-
-/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-/* Switch on SERIAL_TAG */
-#define CONFIG_SERIAL_TAG
-
-#define CONFIG_DFU_ENV_SETTINGS \
- "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_DFU_ENV_SETTINGS \
- "script=boot.scr\0" \
- "script_signed=boot.scr.imx-signed\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "ethact=usb_ether\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=imx7s-warp.dtb\0" \
- "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \
- "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
- "rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \
- "finduuid=part uuid mmc 0:${rootpart} uuid\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=PARTUUID=${uuid} rootwait rw\0" \
- "ivt_offset=" __stringify(BOOTROM_IVT_HDR_OFFSET)"\0"\
- "warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \
- "do_bootscript_hab=" \
- "if test ${hab_enabled} -eq 1; then " \
- "setexpr hab_ivt_addr ${loadaddr} - ${ivt_offset}; " \
- "setenv script ${script_signed}; " \
- "load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \
- "run warp7_auth_or_fail; " \
- "run bootscript; "\
- "fi;\0" \
- "loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run finduuid; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "run do_bootscript_hab;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* I2C configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
-/* environment organization */
-#define CONFIG_ENV_SIZE SZ_8K
-
-#define CONFIG_ENV_OFFSET (8 * SZ_64K)
-#define CONFIG_SYS_FSL_USDHC_NUM 1
-
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 0
-
-/* USB Configs */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
-
-#define CONFIG_IMX_THERMAL
-
-#define CONFIG_USBD_HS
-
-/* USB Device Firmware Update support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-
-#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01"
-
-/* Environment variable name to represent HAB enable state */
-#define HAB_ENABLED_ENVNAME "hab_enabled"
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 25/93] arm: Remove warp7 board
2018-11-19 15:53 ` [U-Boot] [PATCH 25/93] arm: Remove warp7 board Simon Glass
@ 2018-11-19 17:56 ` Fabio Estevam
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Fabio Estevam @ 2018-11-19 17:56 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Mon, Nov 19, 2018 at 2:29 PM Simon Glass <sjg@chromium.org> wrote:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
CONFIG_DM_BLK does not exist.
Which deadline? Shouldn't we have a warning to let people know that
the board should be converted?
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 25/93] arm: Remove warp7 board
2018-11-19 17:56 ` Fabio Estevam
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On Mon, 19 Nov 2018 at 10:56, Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Nov 19, 2018 at 2:29 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
>
> CONFIG_DM_BLK does not exist.
>
> Which deadline? Shouldn't we have a warning to let people know that
> the board should be converted?
This should be CONFIG_BLK, not CONFIG_DM_BLK, which as you say does not exist.
Here are the release emails I can quickly find which mention it:
v2017.09 - migration note included in doc/driver-model
v2018.01 - general comment about DM migration
v2018.03-rc1 - CONFIG_BLK migration request
v2018.05 - I followed up mentioning CONFIG_BLK migration
v2018.07 CONFIG_BLK migration request
v2018.09 CONFIG_BLK migration request
I'll send a patch to print a build warning.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 26/93] arm: Remove gwventana_gw5904 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (24 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 25/93] arm: Remove warp7 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 27/93] arm: Remove cairo board Simon Glass
` (71 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/gateworks/gw_ventana/Kconfig | 25 -
board/gateworks/gw_ventana/MAINTAINERS | 8 -
board/gateworks/gw_ventana/Makefile | 11 -
board/gateworks/gw_ventana/README | 320 -----
board/gateworks/gw_ventana/common.c | 1422 -------------------
board/gateworks/gw_ventana/common.h | 98 --
board/gateworks/gw_ventana/eeprom.c | 238 ----
board/gateworks/gw_ventana/gsc.c | 274 ----
board/gateworks/gw_ventana/gsc.h | 70 -
board/gateworks/gw_ventana/gw_ventana.c | 1351 ------------------
board/gateworks/gw_ventana/gw_ventana_spl.c | 691 ---------
board/gateworks/gw_ventana/ventana_eeprom.h | 133 --
configs/gwventana_emmc_defconfig | 88 --
configs/gwventana_gw5904_defconfig | 92 --
configs/gwventana_nand_defconfig | 91 --
include/configs/gw_ventana.h | 355 -----
17 files changed, 5268 deletions(-)
delete mode 100644 board/gateworks/gw_ventana/Kconfig
delete mode 100644 board/gateworks/gw_ventana/MAINTAINERS
delete mode 100644 board/gateworks/gw_ventana/Makefile
delete mode 100644 board/gateworks/gw_ventana/README
delete mode 100644 board/gateworks/gw_ventana/common.c
delete mode 100644 board/gateworks/gw_ventana/common.h
delete mode 100644 board/gateworks/gw_ventana/eeprom.c
delete mode 100644 board/gateworks/gw_ventana/gsc.c
delete mode 100644 board/gateworks/gw_ventana/gsc.h
delete mode 100644 board/gateworks/gw_ventana/gw_ventana.c
delete mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c
delete mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h
delete mode 100644 configs/gwventana_emmc_defconfig
delete mode 100644 configs/gwventana_gw5904_defconfig
delete mode 100644 configs/gwventana_nand_defconfig
delete mode 100644 include/configs/gw_ventana.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ed551b245c9..7c7435b6d89 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -549,7 +549,6 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pfla02/Kconfig"
-source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig
deleted file mode 100644
index 5d1bae41ac5..00000000000
--- a/board/gateworks/gw_ventana/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_GW_VENTANA
-
-config SYS_BOARD
- default "gw_ventana"
-
-config SYS_VENDOR
- default "gateworks"
-
-config SYS_CONFIG_NAME
- default "gw_ventana"
-
-config CMD_EECONFIG
- bool "Enable the 'econfig' command"
- help
- Provides access to EEPROM configuration on Gateworks Ventana
-
-config CMD_GSC
- bool "Enable the 'gsc' command"
- help
- Provides access to the GSC configuration:
-
- gsc sleep - sleeps for a period of seconds
- gsc wd - enables / disables the watchdog
-
-endif
diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS
deleted file mode 100644
index 265ddac1c05..00000000000
--- a/board/gateworks/gw_ventana/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-GW_VENTANA BOARD
-M: Tim Harvey <tharvey@gateworks.com>
-S: Maintained
-F: board/gateworks/gw_ventana/
-F: include/configs/gw_ventana.h
-F: configs/gwventana_nand_defconfig
-F: configs/gwventana_emmc_defconfig
-F: configs/gwventana_gw5904_defconfig
diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile
deleted file mode 100644
index 8fa691aefc4..00000000000
--- a/board/gateworks/gw_ventana/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
-# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
-# Copyright (C) 2013, Gateworks Corporation
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := gw_ventana.o gsc.o eeprom.o common.o
-obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
-
diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
deleted file mode 100644
index 57c64a1b2ad..00000000000
--- a/board/gateworks/gw_ventana/README
+++ /dev/null
@@ -1,320 +0,0 @@
-U-Boot for the Gateworks Ventana Product Family boards
-
-This file contains information for the port of U-Boot to the Gateworks
-Ventana Product family boards.
-
-The entire Ventana product family (http://www.gateworks.com/product#ventana)
-is supported by a single bootloader build by using a common SPL and U-Boot
-that dynamically determines the characterstics of the board at runtime via
-information from an EEPROM on the board programmed at the factory and supports
-all of the various boot mediums available.
-
-1. Secondary Program Loader (SPL)
----------------------------------
-
-The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
-an executable image from various boot devices.
-
-The Gateworks Ventana board config uses an SPL build configuration. This
-will build the following artifacts from U-Boot source:
- - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
- Loader) boots. This detects CPU/DRAM configuration, configures
- The DRAM controller, loads u-boot.img from the detected boot device,
- and jumps to it. As this is booted from the PPL, it has an IVT/DCD
- table.
- - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
-
-
-2. Build
---------
-
-To build U-Boot for the Gateworks Ventana product family:
-
-For NAND FLASH based boards:
- make gwventana_nand_config
- make
-
-For EMMC FLASH based boards:
- make gwventana_emmc_config
- make
-
-
-3. Boot source:
----------------
-
-The Gateworks Ventana boards support booting from NAND or micro-SD depending
-on the board model. The IMX6 BOOT ROM will choose a boot media based on eFUSE
-settings programmed at the factory.
-
-Boards with NAND flash will always boot from NAND, and NAND-less boards will
-always boot from micro-SD. However, it is possible to use the U-Boot bmode
-command (or the technique it uses) to essentially bootstrap to another boot
-media at runtime.
-
-3.1. boot from NAND
--------------------
-
-The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
-and bad block information (referred to as 'bootstreams') which are replicated
-multiple times in NAND. The number of replications and their spacing (referred
-to as search stride) is configurable through board strapping options and/or
-eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In
-addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
-copies of a bootloader in flash in the case that a bad block has corrupted one.
-The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs
-under Linux and operates on an MTD partition, must be used to program the
-bootstream in order to setup this flash structure correctly.
-
-The Gateworks Ventana boards with NAND flash have been factory programmed
-such that their eFUSE settings expect 2 copies of the boostream (this is
-specified by providing kobs-ng with the --search_exponent=1 argument). Once in
-Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL
-with:
-
-kobs-ng init -v -x --search_exponent=1 SPL
-
-The kobs-ng application uses an imximage which contains the Image Vector Table
-(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
-requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and
-Discovered Bad Block Table (DBBT). The SPL build artifact from U-Boot is
-an imximage.
-
-The u-boot.img, which is the non SPL U-Boot binary appended to a U-Boot image
-header must be programmed in the NAND flash boot device at an offset hard
-coded in the SPL. For the Ventana boards, this has been chosen to be 14MB.
-The image can be programmed from either U-Boot or Linux:
-
-U-Boot:
-Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)
-Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \
- nand write ${loadaddr} uboot ${filesize}
-
-Linux:
-nandwrite /dev/mtd1 u-boot.img
-
-The above assumes the default Ventana partitioning scheme which is configured
-via the mtdparts env var:
- - spl: 14MB
- - uboot: 2M
- - env: 1M
- - rootfs: the rest
-
-This information is taken from:
- http://trac.gateworks.com/wiki/ventana/bootloader#nand
-
-More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
-
-3.1. boot from MMC (eMMC/microSD)
----------------------------------
-
-When the IMX6 eFUSE settings have been factory programmed to boot from
-MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
-booted, it will load and execute U-Boot (u-boot.img) from offset 69KB
-on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
-
-While it is technically possible to enable the SPL to be able to load
-U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to
-use raw micro-SD access to keep the code-size and boot time of the SPL down.
-
-For these reasons an MMC device that will be used as an IMX6 primary boot
-device must be carefully partitioned and prepared.
-
-The following shell commands are executed on a Linux host (adjust DEV to the
-block storage device of your MMC, ie /dev/mmcblk0):
-
- DEV=/dev/sdc
- # zero out 1MB of device
- sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync
- # copy SPL to 1KB offset
- sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync
- # copy U-Boot to 69KB offset
- sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync
- # create a partition table with a single rootfs partition starting at 1MB
- printf "1,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync
- # format partition
- sudo mkfs.ext4 -L root ${DEV}1
- # mount the partition
- sudo udisks --mount ${DEV}1
- # extract filesystem
- sudo tar xvf rootfs.tar.gz -C /media/root
- # flush and unmount
- sync && sudo umount /media/root
-
-The above assumes the default Ventana micro-SD partitioning scheme
- - spl : 1KB-69KB (68KB) required by IMX6 BOOT ROM
- - uboot : 69KB-709KB (640KB) defined by
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
- - env : 709KB-965KB (256KB) defined by
- CONFIG_ENV_MMC_SIZE
- CONFIG_ENV_MMC_OFFSET_REDUND
- - rootfs : 1MB-
-
-This information is taken from:
- http://trac.gateworks.com/wiki/ventana/bootloader#microsd
-
-More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
-
-4. Falcon Mode
-------------------------------
-
-The Gateworks Ventana board config enables Falcon mode (CONFIG_SPL_OS_BOOT)
-which allows the SPL to boot directly to an OS instead of to U-Boot
-(u-boot.img) thus acheiving a faster overall boot time. The time savings
-depends on your boot medium (ie NAND Flash vs micro-SD) and size/storage
-of the OS. The time savings can be anywhere from 2 seconds (256MB NAND Flash
-with ~1MB kernel) to 6 seconds or more (2GB NAND Flash with ~6 kernel)
-
-The Gateworks Ventana board supports Falcon mode for the following boot
-medium:
- - NAND flash
- - micro-SD
-
-For all boot mediums, raw mode is used. While support of more complex storage
-such as files on top of FAT/EXT filesystem is possible but not practical
-as the size of the SPL is fairly limitted (to 64KB based on the smallest
-size of available IMX6 iRAM) as well as the fact that this would increase
-OS load time which defeats the purpose of Falcon mode in the first place.
-
-The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
-based on the return value of the spl_start_uboot() function. While often
-this can simply be the state of a GPIO based pushbutton or DIP switch, for
-Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
-set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
-
-To use Falcon mode it is required that you first 'prepare' the 'args' data
-that is stored on your boot medium along with the kernel (which can be any
-OS or bare-metal application). In the case of the Linux kernel the 'args'
-is the flatenned device-tree which normally gets altered prior to booting linux
-by U-Boot's 'bootm' command. To achieve this for SPL we use the
-'spl export fdt' command in U-Boot after loading the kernel and dtb which
-will go through the same process of modifying the device-tree for the board
-being executed on but not jump to the kernel. This allows you to save the
-args data to the location the SPL expects it and then enable Falcon mode.
-
-It is important to realize that there are certain values in the dtb that
-are board model specific (IMX6Q vs IMX6DL for example) and board specific
-(board serial number, MAC addrs) so you do not want to use the 'args'
-data prepared from one board on another board.
-
-4.1. Falcon Mode on NAND flash
-------------------------------
-To prepare a Gateworks Ventana board that boots from NAND flash for Falcon
-mode you must program your flash such that the 'args' and 'kernel' are
-located where defined at compile time by the following:
- CONFIG_CMD_SPL_NAND_OFS 17MB - offset of 'args'
- CONFIG_SYS_NAND_SPL_KERNEL_OFFS 18MB - offset of 'kernel'
-
-The location offsets defined above are defaults chosen by Gateworks and are
-flexible if you want to re-define them.
-
-The following steps executed in U-Boot will configure Falcon mode for NAND
-using rootfs (ubi), kernel (uImage), and dtb from the network:
-
- # change mtd partitions to the above mapping
- Ventana > setenv mtdparts 'mtdparts=nand:14m(spl),2m(uboot),1m(env),1m(args),10m(kernel),-(rootfs)'
-
- # flash rootfs (at 28MB)
- Ventana > tftp ${loadaddr} rootfs_${flash_layout}.ubi && \
- nand erase.part rootfs && nand write ${loadaddr} rootfs ${filesize}
-
- # load the device-tree
- Ventana > tftp ${fdt_addr} ventana/${fdt_file2}
-
- # load the kernel
- Ventana > tftp ${loadaddr} ventana/uImage
-
- # flash kernel (at 18MB)
- Ventana > nand erase.part kernel && nand write ${loadaddr} kernel ${filesize}
-
- # set kernel args for the console and rootfs (used by spl export)
- Ventana > setenv bootargs 'console=ttymxc1,115200 root=ubi0:rootfs ubi.mtd=5 rootfstype=ubifs quiet'
-
- # create args based on env, board, EEPROM, and dtb
- Ventana > spl export fdt ${loadaddr} - ${fdt_addr}
-
- # flash args (at 17MB)
- Ventana > nand erase.part args && nand write 18000000 args 100000
-
- # set i2c register 0x50:0x00=0 to boot to Linux
- Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
-
-Be sure to adjust 'bootargs' above to your OS needs (this will be different
-for various distros such as OpenWrt, Yocto, Android, etc). You can use the
-value obtained from 'cat /proc/cmdline' when booted to Linux.
-
-This information is taken from:
- http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#nand
-
-
-4.2. Falcon Mode on micro-SD card
----------------------------------
-
-To prepare a Gateworks Ventana board with a primary boot device of micro-SD
-you first need to make sure you build U-Boot with CONFIG_ENV_IS_IN_MMC
-instead of CONFIG_ENV_IS_IN_NAND.
-
-For micro-SD based Falcon mode you must program your micro-SD such that
-the 'args' and 'kernel' are located where defined at compile time
-by the following:
- CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 (1MB) - offset of 'args'
- CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 (2MB) - offset of 'kernel'
-
-The location offsets defined above are defaults chosen by Gateworks and are
-flexible if you want to re-define them.
-
-First you must prepare a micro-SD such that the SPL can be loaded by the
-IMX6 BOOT ROM (fixed offset of 1KB), and U-Boot can be loaded by the SPL
-(fixed offset of 69KB defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
-
-The following shell commands are executed on a Linux host (adjust DEV to the
-block storage device of your micro-SD):
-
- DEV=/dev/sdc
- # zero out 1MB of device
- sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync
- # copy SPL to 1KB offset
- sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync
- # copy U-Boot to 69KB offset
- sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync
- # create a partition table with a single rootfs partition starting at 10MB
- printf "10,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync
- # format partition
- sudo mkfs.ext4 -L root ${DEV}1
- # mount the partition
- sudo udisks --mount ${DEV}1
- # extract filesystem
- sudo tar xvf rootfs.tar.gz -C /media/root
- # flush and unmount
- sync && sudo umount /media/root
-
-Now that your micro-SD partitioning has been adjusted to leave room for the
-raw 'args' and 'kernel' data boot the board with the prepared micro-SD, break
-out in U-Boot and use the following to enable Falcon mode:
-
- # load device-tree from rootfs
- Ventana > ext2load mmc 0:1 ${fdt_addr} boot/${fdt_file2}
-
- # load kernel from rootfs
- Ventana > ext2load mmc 0:1 ${loadaddr} boot/uImage
-
- # write kernel at 2MB offset
- Ventana > mmc write ${loadaddr} 0x1000 0x4000
-
- # setup kernel bootargs
- Ventana > setenv bootargs 'console=ttymxc1,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw'
-
- # prepare args
- Ventana > spl export fdt ${loadaddr} - ${fdt_addr}
-
- # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
- Ventana > mmc write 18000000 0x800 0x800
-
- # set i2c register 0x50:0x00=0 to boot to Linux
- Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
-
-Be sure to adjust 'bootargs' above to your OS needs (this will be different
-for various distros such as OpenWrt, Yocto, Android, etc). You can use the
-value obtained from 'cat /proc/cmdline' when booted to Linux.
-
-This information is taken from:
- http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#microsd
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
deleted file mode 100644
index 41fe8dc2403..00000000000
--- a/board/gateworks/gw_ventana/common.c
+++ /dev/null
@@ -1,1422 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
-#include <hwconfig.h>
-#include <power/pmic.h>
-#include <power/ltc3676_pmic.h>
-#include <power/pfuze100_pmic.h>
-
-#include "common.h"
-
-/* UART1: Function varies per baseboard */
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-/* UART2: Serial Console */
-static iomux_v3_cfg_t const uart2_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
- SETUP_IOMUX_PADS(uart2_pads);
-}
-
-/* MMC */
-static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-/* 4-bit microSD on SD2 */
-static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* CD */
- IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-/* 8-bit eMMC on SD2/NAND */
-static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-/* I2C1: GSC */
-static struct i2c_pads_info mx6q_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* I2C3: Misc/Expansion */
-static struct i2c_pads_info mx6q_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-void setup_ventana_i2c(void)
-{
- if (is_cpu_type(MXC_CPU_MX6Q)) {
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
- } else {
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
- }
-}
-
-/*
- * Baseboard specific GPIO
- */
-static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
- /* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
-
- /* GPS_SHDN */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* VID_PWR */
- IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
- /* SD3_VSELECT */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* RS232_EN# */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
- /* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
- /* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* GPS_SHDN */
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
- /* USBOTG_SEL */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* VID_PWR */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
- /* PCI_RST# (GW522x) */
- IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
- /* RS485_EN */
- IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
- /* SD3_VSELECT */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* RS232_EN# */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
- /* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
- /* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
- /* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* GPS_SHDN */
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
- /* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
- /* RS485_EN */
- IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
- /* SD3_VSELECT */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* RS232_EN# */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
- /* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG),
- /* MIPI_DIO */
- IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
- /* RS485_EN */
- IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
- /* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
- /* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
- /* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
- /* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* RS485_EN */
- IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLED# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
- /* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
- /* USBOTG_SEL */
- IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
- /* MX6_DIO[4:9] */
- IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
- IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
- IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
- IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
- IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
- IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
- /* PCIEGBE1_OFF# */
- IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
- /* PCIEGBE2_OFF# */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
- /* SD3_VSELECT */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
- /* VID_PWR */
- IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
- /* RS232_EN# */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
- /* CAN_STBY */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
- /* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
- /* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* PCI_RST# */
- IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
- /* RS485_EN */
- IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
- /* PCIESKT_WDIS# */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
- /* USBH2_PEN (OTG) */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* 12V0_PWR_EN */
- IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
- /* BKLT_12VEN */
- IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
- /* EMMY_PDN# */
- IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
- /* EMMY_CFG1# */
- IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
- /* EMMY_CFG1# */
- IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
- /* USBH1_PEN (EHCI) */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
- /* USBH2_PEN (OTG) */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* USBDPC_PEN */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* TOUCH_RST */
- IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
- /* AUDIO_RST# */
- IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
- /* UART1_TEN# */
- IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
- /* LVDS_BKLEN # */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
- /* RGMII_PDWN# */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
- /* TOUCH_IRQ# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* TOUCH_RST# */
- IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
-};
-
-static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
- /* USB_HUBRST# */
- IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
- /* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
- /* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
- /* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
- /* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
- /* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
- /* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* UART_RS485 */
- IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
- /* UART_HALF */
- IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
- /* SKT1_WDIS# */
- IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
- /* SKT1_RST# */
- IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
- /* SKT2_WDIS# */
- IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
- /* SKT2_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
- /* M2_OFF# */
- IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
- /* M2_WDIS# */
- IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
- /* M2_RST# */
- IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
-};
-
-/* Digital I/O */
-struct dio_cfg gw51xx_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
- IMX_GPIO_NR(1, 18),
- { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
- 4
- },
-};
-
-struct dio_cfg gw52xx_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
- IMX_GPIO_NR(1, 20),
- { 0, 0 },
- 0
- },
-};
-
-struct dio_cfg gw53xx_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
- IMX_GPIO_NR(1, 20),
- { 0, 0 },
- 0
- },
-};
-
-struct dio_cfg gw54xx_dio[] = {
- {
- { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
- IMX_GPIO_NR(1, 9),
- { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
- 1
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
- IMX_GPIO_NR(2, 9),
- { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
- 3
- },
- {
- { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
- IMX_GPIO_NR(2, 10),
- { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
- 4
- },
-};
-
-struct dio_cfg gw551x_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
-};
-
-struct dio_cfg gw552x_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
- IMX_GPIO_NR(1, 20),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
- IMX_GPIO_NR(5, 18),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
- IMX_GPIO_NR(5, 20),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
- IMX_GPIO_NR(5, 21),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
- IMX_GPIO_NR(5, 22),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
- IMX_GPIO_NR(5, 23),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
- IMX_GPIO_NR(5, 25),
- { 0, 0 },
- 0
- },
-};
-
-struct dio_cfg gw553x_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
- IMX_GPIO_NR(1, 18),
- { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
- 4
- },
-};
-
-struct dio_cfg gw560x_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
- IMX_GPIO_NR(1, 20),
- { 0, 0 },
- 0
- },
-};
-
-struct dio_cfg gw5903_dio[] = {
-};
-
-struct dio_cfg gw5904_dio[] = {
- {
- { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
- IMX_GPIO_NR(1, 16),
- { 0, 0 },
- 0
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
- IMX_GPIO_NR(1, 19),
- { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
- 2
- },
- {
- { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
- IMX_GPIO_NR(1, 17),
- { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
- 3
- },
- {
- {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
- IMX_GPIO_NR(1, 20),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
- IMX_GPIO_NR(2, 0),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
- IMX_GPIO_NR(2, 1),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
- IMX_GPIO_NR(2, 2),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
- IMX_GPIO_NR(2, 3),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
- IMX_GPIO_NR(2, 4),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
- IMX_GPIO_NR(2, 5),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
- IMX_GPIO_NR(2, 6),
- { 0, 0 },
- 0
- },
- {
- {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
- IMX_GPIO_NR(2, 7),
- { 0, 0 },
- 0
- },
-};
-
-/*
- * Board Specific GPIO
- */
-struct ventana gpio_cfg[GW_UNKNOWN] = {
- /* GW5400proto */
- {
- .gpio_pads = gw54xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
- .dio_cfg = gw54xx_dio,
- .dio_num = ARRAY_SIZE(gw54xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(4, 7),
- .mezz_irq = IMX_GPIO_NR(4, 9),
- .rs485en = IMX_GPIO_NR(3, 24),
- .dioi2c_en = IMX_GPIO_NR(4, 5),
- .pcie_sson = IMX_GPIO_NR(1, 20),
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- .mmc_cd = IMX_GPIO_NR(7, 0),
- },
-
- /* GW51xx */
- {
- .gpio_pads = gw51xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
- .dio_cfg = gw51xx_dio,
- .dio_num = ARRAY_SIZE(gw51xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 10),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .gps_shdn = IMX_GPIO_NR(1, 2),
- .vidin_en = IMX_GPIO_NR(5, 20),
- .wdis = IMX_GPIO_NR(7, 12),
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- },
-
- /* GW52xx */
- {
- .gpio_pads = gw52xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
- .dio_cfg = gw52xx_dio,
- .dio_num = ARRAY_SIZE(gw52xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
- .usb_sel = IMX_GPIO_NR(1, 2),
- .wdis = IMX_GPIO_NR(7, 12),
- .msata_en = GP_MSATA_SEL,
- .rs232_en = GP_RS232_EN,
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- .vsel_pin = IMX_GPIO_NR(6, 14),
- .mmc_cd = IMX_GPIO_NR(7, 0),
- },
-
- /* GW53xx */
- {
- .gpio_pads = gw53xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
- .dio_cfg = gw53xx_dio,
- .dio_num = ARRAY_SIZE(gw53xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .gps_shdn = IMX_GPIO_NR(1, 27),
- .vidin_en = IMX_GPIO_NR(3, 31),
- .wdis = IMX_GPIO_NR(7, 12),
- .msata_en = GP_MSATA_SEL,
- .rs232_en = GP_RS232_EN,
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- .vsel_pin = IMX_GPIO_NR(6, 14),
- .mmc_cd = IMX_GPIO_NR(7, 0),
- },
-
- /* GW54xx */
- {
- .gpio_pads = gw54xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
- .dio_cfg = gw54xx_dio,
- .dio_num = ARRAY_SIZE(gw54xx_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .rs485en = IMX_GPIO_NR(7, 1),
- .vidin_en = IMX_GPIO_NR(3, 31),
- .dioi2c_en = IMX_GPIO_NR(4, 5),
- .pcie_sson = IMX_GPIO_NR(1, 20),
- .wdis = IMX_GPIO_NR(5, 17),
- .msata_en = GP_MSATA_SEL,
- .rs232_en = GP_RS232_EN,
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- .vsel_pin = IMX_GPIO_NR(6, 14),
- .mmc_cd = IMX_GPIO_NR(7, 0),
- },
-
- /* GW551x */
- {
- .gpio_pads = gw551x_gpio_pads,
- .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
- .dio_cfg = gw551x_dio,
- .dio_num = ARRAY_SIZE(gw551x_dio),
- .leds = {
- IMX_GPIO_NR(4, 7),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
- .wdis = IMX_GPIO_NR(7, 12),
- },
-
- /* GW552x */
- {
- .gpio_pads = gw552x_gpio_pads,
- .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
- .dio_cfg = gw552x_dio,
- .dio_num = ARRAY_SIZE(gw552x_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 29),
- .usb_sel = IMX_GPIO_NR(1, 7),
- .wdis = IMX_GPIO_NR(7, 12),
- .msata_en = GP_MSATA_SEL,
- },
-
- /* GW553x */
- {
- .gpio_pads = gw553x_gpio_pads,
- .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
- .dio_cfg = gw553x_dio,
- .dio_num = ARRAY_SIZE(gw553x_dio),
- .leds = {
- IMX_GPIO_NR(4, 10),
- IMX_GPIO_NR(4, 11),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
- .vidin_en = IMX_GPIO_NR(5, 20),
- .wdis = IMX_GPIO_NR(7, 12),
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- .vsel_pin = IMX_GPIO_NR(6, 14),
- .mmc_cd = IMX_GPIO_NR(7, 0),
- },
-
- /* GW560x */
- {
- .gpio_pads = gw560x_gpio_pads,
- .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
- .dio_cfg = gw560x_dio,
- .dio_num = ARRAY_SIZE(gw560x_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(4, 31),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .rs232_en = GP_RS232_EN,
- .vidin_en = IMX_GPIO_NR(3, 31),
- .wdis = IMX_GPIO_NR(7, 12),
- .otgpwr_en = IMX_GPIO_NR(4, 15),
- .mmc_cd = IMX_GPIO_NR(7, 0),
- },
-
- /* GW5903 */
- {
- .gpio_pads = gw5903_gpio_pads,
- .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
- .dio_cfg = gw5903_dio,
- .dio_num = ARRAY_SIZE(gw5903_dio),
- .leds = {
- IMX_GPIO_NR(6, 14),
- },
- .otgpwr_en = IMX_GPIO_NR(4, 15),
- .mmc_cd = IMX_GPIO_NR(6, 11),
- },
-
- /* GW5904 */
- {
- .gpio_pads = gw5904_gpio_pads,
- .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
- .dio_cfg = gw5904_dio,
- .dio_num = ARRAY_SIZE(gw5904_dio),
- .leds = {
- IMX_GPIO_NR(4, 6),
- IMX_GPIO_NR(4, 7),
- IMX_GPIO_NR(4, 15),
- },
- .pcie_rst = IMX_GPIO_NR(1, 0),
- .mezz_pwren = IMX_GPIO_NR(2, 19),
- .mezz_irq = IMX_GPIO_NR(2, 18),
- .otgpwr_en = IMX_GPIO_NR(3, 22),
- },
-};
-
-void setup_iomux_gpio(int board, struct ventana_board_info *info)
-{
- int i;
-
- if (board >= GW_UNKNOWN)
- return;
-
- /* board specific iomux */
- imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
- gpio_cfg[board].num_pads);
-
- /* RS232_EN# */
- if (gpio_cfg[board].rs232_en) {
- gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
- gpio_direction_output(gpio_cfg[board].rs232_en, 0);
- }
-
- /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
- if (board == GW52xx && info->model[4] == '2')
- gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
-
- /* assert PCI_RST# */
- gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#");
- gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
-
- /* turn off (active-high) user LED's */
- for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
- char name[16];
- if (gpio_cfg[board].leds[i]) {
- sprintf(name, "led_user%d", i);
- gpio_request(gpio_cfg[board].leds[i], name);
- gpio_direction_output(gpio_cfg[board].leds[i], 1);
- }
- }
-
- /* MSATA Enable - default to PCI */
- if (gpio_cfg[board].msata_en) {
- gpio_request(gpio_cfg[board].msata_en, "msata_en");
- gpio_direction_output(gpio_cfg[board].msata_en, 0);
- }
-
- /* Expansion Mezzanine IO */
- if (gpio_cfg[board].mezz_pwren) {
- gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
- gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
- }
- if (gpio_cfg[board].mezz_irq) {
- gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
- gpio_direction_input(gpio_cfg[board].mezz_irq);
- }
-
- /* RS485 Transmit Enable */
- if (gpio_cfg[board].rs485en) {
- gpio_request(gpio_cfg[board].rs485en, "rs485_en");
- gpio_direction_output(gpio_cfg[board].rs485en, 0);
- }
-
- /* GPS_SHDN */
- if (gpio_cfg[board].gps_shdn) {
- gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
- gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
- }
-
- /* Analog video codec power enable */
- if (gpio_cfg[board].vidin_en) {
- gpio_request(gpio_cfg[board].vidin_en, "anavidin_en");
- gpio_direction_output(gpio_cfg[board].vidin_en, 1);
- }
-
- /* DIOI2C_DIS# */
- if (gpio_cfg[board].dioi2c_en) {
- gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
- gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
- }
-
- /* PCICK_SSON: disable spread-spectrum clock */
- if (gpio_cfg[board].pcie_sson) {
- gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
- gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
- }
-
- /* USBOTG mux routing */
- if (gpio_cfg[board].usb_sel) {
- gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
- gpio_direction_output(gpio_cfg[board].usb_sel, 0);
- }
-
- /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
- if (gpio_cfg[board].wdis) {
- gpio_request(gpio_cfg[board].wdis, "wlan_dis");
- gpio_direction_output(gpio_cfg[board].wdis, 1);
- }
-
- /* OTG power off */
- if (gpio_cfg[board].otgpwr_en) {
- gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr");
- gpio_direction_output(gpio_cfg[board].otgpwr_en, 0);
- }
-
- /* sense vselect pin to see if we support uhs-i */
- if (gpio_cfg[board].vsel_pin) {
- gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
- gpio_direction_input(gpio_cfg[board].vsel_pin);
- gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
- }
-
- /* microSD CD */
- if (gpio_cfg[board].mmc_cd) {
- gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
- gpio_direction_input(gpio_cfg[board].mmc_cd);
- }
-
- /* Anything else board specific */
- switch(board) {
- case GW560x:
- gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
- gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
- break;
- case GW5903:
- gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
- gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
- gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
- gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
- gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
- gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
- gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
- gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
- gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
- gpio_direction_input(IMX_GPIO_NR(4, 6));
- gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
- gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
- gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
- gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
- break;
- case GW5904:
- gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
- gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
- gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
- gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
- gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
- gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
- gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
- gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
- gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
- gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
- gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
- gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
- break;
- }
-}
-
-/* setup GPIO pinmux and default configuration per baseboard and env */
-void setup_board_gpio(int board, struct ventana_board_info *info)
-{
- const char *s;
- char arg[10];
- size_t len;
- int i;
- int quiet = simple_strtol(env_get("quiet"), NULL, 10);
-
- if (board >= GW_UNKNOWN)
- return;
-
- /* RS232_EN# */
- if (gpio_cfg[board].rs232_en) {
- gpio_direction_output(gpio_cfg[board].rs232_en,
- (hwconfig("rs232")) ? 0 : 1);
- }
-
- /* MSATA Enable */
- if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
- gpio_direction_output(GP_MSATA_SEL,
- (hwconfig("msata")) ? 1 : 0);
- }
-
- /* USBOTG Select (PCISKT or FrontPanel) */
- if (gpio_cfg[board].usb_sel) {
- gpio_direction_output(gpio_cfg[board].usb_sel,
- (hwconfig("usb_pcisel")) ? 1 : 0);
- }
-
- /*
- * Configure DIO pinmux/padctl registers
- * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
- */
- for (i = 0; i < gpio_cfg[board].dio_num; i++) {
- struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
- iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
- unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
-
- if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
- continue;
- sprintf(arg, "dio%d", i);
- if (!hwconfig(arg))
- continue;
- s = hwconfig_subarg(arg, "padctrl", &len);
- if (s) {
- ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
- & 0x1ffff) | MUX_MODE_SION;
- }
- if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
- if (!quiet) {
- printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
- (cfg->gpio_param/32)+1,
- cfg->gpio_param%32,
- cfg->gpio_param);
- }
- imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
- ctrl);
- gpio_requestf(cfg->gpio_param, "dio%d", i);
- gpio_direction_input(cfg->gpio_param);
- } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
- cfg->pwm_padmux) {
- if (!cfg->pwm_param) {
- printf("DIO%d: Error: pwm config invalid\n",
- i);
- continue;
- }
- if (!quiet)
- printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
- imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
- MUX_PAD_CTRL(ctrl));
- }
- }
-
- if (!quiet) {
- if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
- printf("MSATA: %s\n", (hwconfig("msata") ?
- "enabled" : "disabled"));
- }
- if (gpio_cfg[board].rs232_en) {
- printf("RS232: %s\n", (hwconfig("rs232")) ?
- "enabled" : "disabled");
- }
- }
-}
-
-/* setup board specific PMIC */
-void setup_pmic(void)
-{
- struct pmic *p;
- struct ventana_board_info ventana_info;
- int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
- const int i2c_pmic = 1;
- u32 reg;
-
- i2c_set_bus_num(i2c_pmic);
-
- /* configure PFUZE100 PMIC */
- if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
- debug("probed PFUZE100 at 0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
- power_pfuze100_init(i2c_pmic);
- p = pmic_get("PFUZE100");
- if (p && !pmic_probe(p)) {
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Set VGEN1 to 1.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
- reg &= ~(LDO_VOL_MASK);
- reg |= (LDOA_1_50V | LDO_EN);
- pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
-
- /* Set SWBST to 5.0V and enable */
- pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
- reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
- reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
- pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
- }
- }
-
- /* configure LTC3676 PMIC */
- else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
- debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
- power_ltc3676_init(i2c_pmic);
- p = pmic_get("LTC3676_PMIC");
- if (!p || pmic_probe(p))
- return;
- puts("PMIC: LTC3676\n");
- /*
- * set board-specific scalar for max CPU frequency
- * per CPU based on the LDO enabled Operating Ranges
- * defined in the respective IMX6DQ and IMX6SDL
- * datasheets. The voltage resulting from the R1/R2
- * feedback inputs on Ventana is 1308mV. Note that this
- * is a bit shy of the Vmin of 1350mV in the datasheet
- * for LDO enabled mode but is as high as we can go.
- */
- switch (board) {
- case GW560x:
- /* mask PGOOD during SW3 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
- break;
- case GW5903:
- /* mask PGOOD during SW1 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
-
- /* mask PGOOD during SW4 transition */
- pmic_reg_write(p, LTC3676_DVB4B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW4 (VDD_SOC) */
- pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
- break;
- default:
- /* mask PGOOD during SW1 transition */
- pmic_reg_write(p, LTC3676_DVB1B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW1 (VDD_SOC) */
- pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
-
- /* mask PGOOD during SW3 transition */
- pmic_reg_write(p, LTC3676_DVB3B,
- 0x1f | LTC3676_PGOOD_MASK);
- /* set SW3 (VDD_ARM) */
- pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
- }
- }
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[2];
-
-int board_mmc_init(bd_t *bis)
-{
- struct ventana_board_info ventana_info;
- int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
- int ret;
-
- switch (board_type) {
- case GW52xx:
- case GW53xx:
- case GW54xx:
- case GW553x:
- /* usdhc3: 4bit microSD */
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 4;
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- case GW560x:
- /* usdhc2: 8-bit eMMC */
- SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[0].max_bus_width = 8;
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- if (ret)
- return ret;
- /* usdhc3: 4-bit microSD */
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[1].max_bus_width = 4;
- return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
- case GW5903:
- /* usdhc3: 8-bit eMMC */
- SETUP_IOMUX_PADS(gw5904_emmc_pads);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 8;
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- if (ret)
- return ret;
- /* usdhc2: 4-bit microSD */
- SETUP_IOMUX_PADS(gw5904_mmc_pads);
- usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[1].max_bus_width = 4;
- return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
- case GW5904:
- /* usdhc3: 8bit eMMC */
- SETUP_IOMUX_PADS(gw5904_emmc_pads);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 8;
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- default:
- /* doesn't have MMC */
- return -1;
- }
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct ventana_board_info ventana_info;
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
- int gpio = gpio_cfg[board].mmc_cd;
-
- /* Card Detect */
- switch (board) {
- case GW560x:
- /* emmc is always present */
- if (cfg->esdhc_base == USDHC2_BASE_ADDR)
- return 1;
- break;
- case GW5903:
- case GW5904:
- /* emmc is always present */
- if (cfg->esdhc_base == USDHC3_BASE_ADDR)
- return 1;
- break;
- }
-
- if (gpio) {
- debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
- return !gpio_get_value(gpio);
- }
-
- return -1;
-}
-
-#endif /* CONFIG_FSL_ESDHC */
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
deleted file mode 100644
index 8019e27f6e0..00000000000
--- a/board/gateworks/gw_ventana/common.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#ifndef _GWVENTANA_COMMON_H_
-#define _GWVENTANA_COMMON_H_
-
-#include "ventana_eeprom.h"
-
-/* GPIO's common to all baseboards */
-#define GP_PHY_RST IMX_GPIO_NR(1, 30)
-#define GP_RS232_EN IMX_GPIO_NR(2, 11)
-#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
-
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-
-#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/*
- * each baseboard has an optional set user configurable Digital IO lines which
- * can be pinmuxed as a GPIO or in some cases a PWM
- */
-struct dio_cfg {
- iomux_v3_cfg_t gpio_padmux[2];
- unsigned gpio_param;
- iomux_v3_cfg_t pwm_padmux[2];
- unsigned pwm_param;
-};
-
-struct ventana {
- /* pinmux */
- iomux_v3_cfg_t const *gpio_pads;
- int num_pads;
- /* DIO pinmux/val */
- struct dio_cfg *dio_cfg;
- int dio_num;
- /* various gpios (0 if non-existent) */
- int leds[3];
- int pcie_rst;
- int mezz_pwren;
- int mezz_irq;
- int rs485en;
- int gps_shdn;
- int vidin_en;
- int dioi2c_en;
- int pcie_sson;
- int usb_sel;
- int wdis;
- int msata_en;
- int rs232_en;
- int otgpwr_en;
- int vsel_pin;
- int mmc_cd;
- /* various features */
- bool usd_vsel;
-};
-
-extern struct ventana gpio_cfg[GW_UNKNOWN];
-
-/* configure i2c iomux */
-void setup_ventana_i2c(void);
-/* configure uart iomux */
-void setup_iomux_uart(void);
-/* conifgure PMIC */
-void setup_pmic(void);
-/* configure gpio iomux/defaults */
-void setup_iomux_gpio(int board, struct ventana_board_info *);
-/* late setup of GPIO (configuration per baseboard and env) */
-void setup_board_gpio(int board, struct ventana_board_info *);
-
-#endif /* #ifndef _GWVENTANA_COMMON_H_ */
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
deleted file mode 100644
index f0ae820988e..00000000000
--- a/board/gateworks/gw_ventana/eeprom.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Gateworks Corporation
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <i2c.h>
-#include <malloc.h>
-#include <asm/bitops.h>
-
-#include "gsc.h"
-#include "ventana_eeprom.h"
-
-/* read ventana EEPROM, check for validity, and return baseboard type */
-int
-read_eeprom(int bus, struct ventana_board_info *info)
-{
- int i;
- int chksum;
- char baseboard;
- int type;
- unsigned char *buf = (unsigned char *)info;
-
- memset(info, 0, sizeof(*info));
-
- /*
- * On a board with a missing/depleted backup battery for GSC, the
- * board may be ready to probe the GSC before its firmware is
- * running. We will wait here indefinately for the GSC/EEPROM.
- */
- while (1) {
- if (0 == i2c_set_bus_num(bus) &&
- 0 == i2c_probe(GSC_EEPROM_ADDR))
- break;
- mdelay(1);
- }
-
- /* read eeprom config section */
- if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
- puts("EEPROM: Failed to read EEPROM\n");
- return GW_UNKNOWN;
- }
-
- /* sanity checks */
- if (info->model[0] != 'G' || info->model[1] != 'W') {
- puts("EEPROM: Invalid Model in EEPROM\n");
- return GW_UNKNOWN;
- }
-
- /* validate checksum */
- for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
- chksum += buf[i];
- if ((info->chksum[0] != chksum>>8) ||
- (info->chksum[1] != (chksum&0xff))) {
- puts("EEPROM: Failed EEPROM checksum\n");
- return GW_UNKNOWN;
- }
-
- /* original GW5400-A prototype */
- baseboard = info->model[3];
- if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
- baseboard = '0';
-
- type = GW_UNKNOWN;
- switch (baseboard) {
- case '0': /* original GW5400-A prototype */
- type = GW54proto;
- break;
- case '1':
- type = GW51xx;
- break;
- case '2':
- type = GW52xx;
- break;
- case '3':
- type = GW53xx;
- break;
- case '4':
- type = GW54xx;
- break;
- case '5':
- if (info->model[4] == '1') {
- type = GW551x;
- break;
- } else if (info->model[4] == '2') {
- type = GW552x;
- break;
- } else if (info->model[4] == '3') {
- type = GW553x;
- break;
- }
- break;
- case '6':
- if (info->model[4] == '0')
- type = GW560x;
- break;
- case '9':
- if (info->model[4] == '0' && info->model[5] == '3')
- type = GW5903;
- if (info->model[4] == '0' && info->model[5] == '4')
- type = GW5904;
- break;
- }
- return type;
-}
-
-/* list of config bits that the bootloader will remove from dtb if not set */
-struct ventana_eeprom_config econfig[] = {
- { "eth0", "ethernet0", EECONFIG_ETH0 },
- { "usb0", NULL, EECONFIG_USB0 },
- { "usb1", NULL, EECONFIG_USB1 },
- { "mmc0", NULL, EECONFIG_SD0 },
- { "mmc1", NULL, EECONFIG_SD1 },
- { "mmc2", NULL, EECONFIG_SD2 },
- { "mmc3", NULL, EECONFIG_SD3 },
- { /* Sentinel */ }
-};
-
-#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD)
-static struct ventana_eeprom_config *get_config(const char *name)
-{
- struct ventana_eeprom_config *cfg = econfig;
-
- while (cfg->name) {
- if (0 == strcmp(name, cfg->name))
- return cfg;
- cfg++;
- }
- return NULL;
-}
-
-static u8 econfig_bytes[sizeof(ventana_info.config)];
-static int econfig_init = -1;
-
-static int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct ventana_eeprom_config *cfg;
- struct ventana_board_info *info = &ventana_info;
- int i;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- /* initialize */
- if (econfig_init != 1) {
- memcpy(econfig_bytes, info->config, sizeof(econfig_bytes));
- econfig_init = 1;
- }
-
- /* list configs */
- if ((strncmp(argv[1], "list", 4) == 0)) {
- cfg = econfig;
- while (cfg->name) {
- printf("%s: %d\n", cfg->name,
- test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
- cfg++;
- }
- }
-
- /* save */
- else if ((strncmp(argv[1], "save", 4) == 0)) {
- unsigned char *buf = (unsigned char *)info;
- int chksum;
-
- /* calculate new checksum */
- memcpy(info->config, econfig_bytes, sizeof(econfig_bytes));
- for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
- chksum += buf[i];
- debug("old chksum:0x%04x\n",
- (info->chksum[0] << 8) | info->chksum[1]);
- debug("new chksum:0x%04x\n", chksum);
- info->chksum[0] = chksum >> 8;
- info->chksum[1] = chksum & 0xff;
-
- /* write new config data */
- if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info,
- 1, econfig_bytes, sizeof(econfig_bytes))) {
- printf("EEPROM: Failed updating config\n");
- return CMD_RET_FAILURE;
- }
-
- /* write new config data */
- if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info,
- 1, info->chksum, 2)) {
- printf("EEPROM: Failed updating checksum\n");
- return CMD_RET_FAILURE;
- }
-
- printf("Config saved to EEPROM\n");
- }
-
- /* get config */
- else if (argc == 2) {
- cfg = get_config(argv[1]);
- if (cfg) {
- printf("%s: %d\n", cfg->name,
- test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
- } else {
- printf("invalid config: %s\n", argv[1]);
- return CMD_RET_FAILURE;
- }
- }
-
- /* set config */
- else if (argc == 3) {
- cfg = get_config(argv[1]);
- if (cfg) {
- if (simple_strtol(argv[2], NULL, 10)) {
- test_and_set_bit(cfg->bit, econfig_bytes);
- printf("Enabled %s\n", cfg->name);
- } else {
- test_and_clear_bit(cfg->bit, econfig_bytes);
- printf("Disabled %s\n", cfg->name);
- }
- } else {
- printf("invalid config: %s\n", argv[1]);
- return CMD_RET_FAILURE;
- }
- }
-
- else
- return CMD_RET_USAGE;
-
- return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(
- econfig, 3, 0, do_econfig,
- "EEPROM configuration",
- "list - list config\n"
- "save - save config to EEPROM\n"
- "<name> - get config 'name'\n"
- "<name> [0|1] - set config 'name' to value\n"
-);
-
-#endif /* CONFIG_CMD_EECONFIG */
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
deleted file mode 100644
index c31ef117b29..00000000000
--- a/board/gateworks/gw_ventana/gsc.c
+++ /dev/null
@@ -1,274 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <linux/errno.h>
-#include <common.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-
-#include "ventana_eeprom.h"
-#include "gsc.h"
-
-/*
- * The Gateworks System Controller will fail to ACK a master transaction if
- * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
- * When this does occur, it will never be busy long enough to fail more than
- * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
- * 3 retries.
- */
-int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
- int retry = 3;
- int n = 0;
- int ret;
-
- while (n++ < retry) {
- ret = i2c_read(chip, addr, alen, buf, len);
- if (!ret)
- break;
- debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
- n, ret);
- if (ret != -ENODEV)
- break;
- mdelay(10);
- }
- return ret;
-}
-
-int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
- int retry = 3;
- int n = 0;
- int ret;
-
- while (n++ < retry) {
- ret = i2c_write(chip, addr, alen, buf, len);
- if (!ret)
- break;
- debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
- n, ret);
- if (ret != -ENODEV)
- break;
- mdelay(10);
- }
- mdelay(100);
- return ret;
-}
-
-static void read_hwmon(const char *name, uint reg, uint size)
-{
- unsigned char buf[3];
- uint ui;
-
- printf("%-8s:", name);
- memset(buf, 0, sizeof(buf));
- if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
- puts("fRD\n");
- } else {
- ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
- if (reg == GSC_HWMON_TEMP && ui > 0x8000)
- ui -= 0xffff;
- if (ui == 0xffffff)
- puts("invalid\n");
- else
- printf("%d\n", ui);
- }
-}
-
-int gsc_info(int verbose)
-{
- unsigned char buf[16];
-
- i2c_set_bus_num(0);
- if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
- return CMD_RET_FAILURE;
-
- printf("GSC: v%d", buf[GSC_SC_FWVER]);
- printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
- printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
- ? "en" : "dis");
- if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
- buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
- puts(" WDT_RESET");
- gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
- &buf[GSC_SC_STATUS], 1);
- }
- if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
- int ui = buf[0] | buf[1]<<8;
- if (ui > 0x8000)
- ui -= 0xffff;
- printf(" board temp at %dC", ui / 10);
- }
- puts("\n");
- if (!verbose)
- return CMD_RET_SUCCESS;
-
- read_hwmon("Temp", GSC_HWMON_TEMP, 2);
- read_hwmon("VIN", GSC_HWMON_VIN, 3);
- read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
- read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
- read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3);
- read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
- read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
- read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
- read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
- if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
- read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
- read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
- read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
- switch (ventana_info.model[3]) {
- case '1': /* GW51xx */
- read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
- break;
- case '2': /* GW52xx */
- break;
- case '3': /* GW53xx */
- read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */
- read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
- break;
- case '4': /* GW54xx */
- read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
- read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
- break;
- case '5': /* GW55xx */
- break;
- case '6': /* GW560x */
- read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
- read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
- break;
- }
- return 0;
-}
-
-/*
- * The Gateworks System Controller implements a boot
- * watchdog (always enabled) as a workaround for IMX6 boot related
- * errata such as:
- * ERR005768 - no fix scheduled
- * ERR006282 - fixed in silicon r1.2
- * ERR007117 - fixed in silicon r1.3
- * ERR007220 - fixed in silicon r1.3
- * ERR007926 - no fix scheduled
- * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
- *
- * Disable the boot watchdog
- */
-int gsc_boot_wd_disable(void)
-{
- u8 reg;
-
- i2c_set_bus_num(CONFIG_I2C_GSC);
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
- reg |= (1 << GSC_SC_CTRL1_WDDIS);
- if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return 0;
- }
- puts("Error: could not disable GSC Watchdog\n");
- return 1;
-}
-
-#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
-static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned char reg;
- unsigned long secs = 0;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- secs = simple_strtoul(argv[1], NULL, 10);
- printf("GSC Sleeping for %ld seconds\n", secs);
-
- i2c_set_bus_num(0);
- reg = (secs >> 24) & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
- goto error;
- reg = (secs >> 16) & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1))
- goto error;
- reg = (secs >> 8) & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1))
- goto error;
- reg = secs & 0xff;
- if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1))
- goto error;
- if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- goto error;
- reg |= (1 << 2);
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- goto error;
- reg &= ~(1 << 2);
- reg |= 0x3;
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- goto error;
-
- return CMD_RET_SUCCESS;
-
-error:
- printf("i2c error\n");
- return CMD_RET_FAILURE;
-}
-
-static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned char reg;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- if (strcasecmp(argv[1], "enable") == 0) {
- int timeout = 0;
-
- if (argc > 2)
- timeout = simple_strtoul(argv[2], NULL, 10);
- i2c_set_bus_num(0);
- if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
- if (timeout == 60)
- reg |= (1 << GSC_SC_CTRL1_WDTIME);
- else
- timeout = 30;
- reg |= (1 << GSC_SC_CTRL1_WDEN);
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- printf("GSC Watchdog enabled with timeout=%d seconds\n",
- timeout);
- } else if (strcasecmp(argv[1], "disable") == 0) {
- i2c_set_bus_num(0);
- if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
- if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
- return CMD_RET_FAILURE;
- printf("GSC Watchdog disabled\n");
- } else {
- return CMD_RET_USAGE;
- }
- return CMD_RET_SUCCESS;
-}
-
-static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc < 2)
- return gsc_info(1);
-
- if (strcasecmp(argv[1], "wd") == 0)
- return do_gsc_wd(cmdtp, flag, --argc, ++argv);
- else if (strcasecmp(argv[1], "sleep") == 0)
- return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
-
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- gsc, 4, 1, do_gsc, "GSC configuration",
- "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
- );
-
-#endif /* CONFIG_CMD_GSC */
diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h
deleted file mode 100644
index 0cce9b1b3a2..00000000000
--- a/board/gateworks/gw_ventana/gsc.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#ifndef __ASSEMBLY__
-
-/* i2c slave addresses */
-#define GSC_SC_ADDR 0x20
-#define GSC_RTC_ADDR 0x68
-#define GSC_HWMON_ADDR 0x29
-#define GSC_EEPROM_ADDR 0x51
-
-/* System Controller registers */
-enum {
- GSC_SC_CTRL0 = 0x00,
- GSC_SC_CTRL1 = 0x01,
- GSC_SC_STATUS = 0x0a,
- GSC_SC_FWCRC = 0x0c,
- GSC_SC_FWVER = 0x0e,
-};
-
-/* System Controller Control1 bits */
-enum {
- GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
- GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
- GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
-};
-
-/* System Controller Interrupt bits */
-enum {
- GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
- GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
- GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
- GSC_SC_IRQ_GPIO = 4, /* GPIO change */
- GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
- GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
- GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
-};
-
-/* Hardware Monitor registers */
-enum {
- GSC_HWMON_TEMP = 0x00,
- GSC_HWMON_VIN = 0x02,
- GSC_HWMON_VDD_3P3 = 0x05,
- GSC_HWMON_VBATT = 0x08,
- GSC_HWMON_VDD_5P0 = 0x0b,
- GSC_HWMON_VDD_CORE = 0x0e,
- GSC_HWMON_VDD_HIGH = 0x14,
- GSC_HWMON_VDD_DDR = 0x17,
- GSC_HWMON_VDD_SOC = 0x11,
- GSC_HWMON_VDD_1P8 = 0x1d,
- GSC_HWMON_VDD_IO2 = 0x20,
- GSC_HWMON_VDD_2P5 = 0x23,
- GSC_HWMON_VDD_IO3 = 0x26,
- GSC_HWMON_VDD_IO4 = 0x29,
-};
-
-/*
- * I2C transactions to the GSC are done via these functions which
- * perform retries in the case of a busy GSC NAK'ing the transaction
- */
-int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
-int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
-int gsc_info(int verbose);
-int gsc_boot_wd_disable(void);
-#endif
-
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
deleted file mode 100644
index c4ec97435f4..00000000000
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ /dev/null
@@ -1,1351 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/spi.h>
-#include <asm/mach-imx/video.h>
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <dm.h>
-#include <dm/platform_data/serial_mxc.h>
-#include <environment.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <jffs2/load_kernel.h>
-#include <linux/ctype.h>
-#include <miiphy.h>
-#include <mtd_node.h>
-#include <netdev.h>
-#include <pci.h>
-#include <power/pmic.h>
-#include <power/ltc3676_pmic.h>
-#include <power/pfuze100_pmic.h>
-#include <fdt_support.h>
-#include <jffs2/load_kernel.h>
-#include <spi_flash.h>
-
-#include "gsc.h"
-#include "common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-/*
- * EEPROM board info struct populated by read_eeprom so that we only have to
- * read it once.
- */
-struct ventana_board_info ventana_info;
-
-static int board_type;
-
-/* ENET */
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* PHY nRST */
- IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
-};
-
-#ifdef CONFIG_CMD_NAND
-static iomux_v3_cfg_t const nfc_pads[] = {
- IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- SETUP_IOMUX_PADS(nfc_pads);
-
- /* config gpmi and bch clock to 100 MHz */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-static void setup_iomux_enet(int gpio)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- /* toggle PHY_RST# */
- gpio_request(gpio, "phy_rst#");
- gpio_direction_output(gpio, 0);
- mdelay(10);
- gpio_set_value(gpio, 1);
- mdelay(100);
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
- IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
- /* OTG PWR */
- IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
-};
-
-int board_ehci_hcd_init(int port)
-{
- int gpio;
-
- SETUP_IOMUX_PADS(usb_pads);
-
- /* Reset USB HUB */
- switch (board_type) {
- case GW53xx:
- case GW552x:
- gpio = (IMX_GPIO_NR(1, 9));
- break;
- case GW54proto:
- case GW54xx:
- gpio = (IMX_GPIO_NR(1, 16));
- break;
- default:
- return 0;
- }
-
- /* request and toggle hub rst */
- gpio_request(gpio, "usb_hub_rst#");
- gpio_direction_output(gpio, 0);
- mdelay(2);
- gpio_set_value(gpio, 1);
-
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- /* enable OTG VBUS */
- if (!port && board_type < GW_UNKNOWN) {
- if (gpio_cfg[board_type].otgpwr_en)
- gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
- }
- return 0;
-}
-#endif /* CONFIG_USB_EHCI_MX6 */
-
-#ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t const ecspi1_pads[] = {
- /* SS1 */
- IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
-}
-
-static void setup_spi(void)
-{
- gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
- gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
- SETUP_IOMUX_PADS(ecspi1_pads);
-}
-#endif
-
-/* configure eth0 PHY board-specific LED behavior */
-int board_phy_config(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* Marvel 88E1510 */
- if (phydev->phy_id == 0x1410dd1) {
- /*
- * Page 3, Register 16: LED[2:0] Function Control Register
- * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
- * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
- */
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
- val &= 0xff00;
- val |= 0x0017;
- phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
- }
-
- /* TI DP83867 */
- else if (phydev->phy_id == 0x2000a231) {
- /* configure register 0x170 for ref CLKOUT */
- phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
- phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
- phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
- val &= ~0x1f00;
- val |= 0x0b00; /* chD tx clock*/
- phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
- }
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-#ifdef CONFIG_MV88E61XX_SWITCH
-int mv88e61xx_hw_reset(struct phy_device *phydev)
-{
- struct mii_dev *bus = phydev->bus;
-
- /* GPIO[0] output, CLK125 */
- debug("enabling RGMII_REFCLK\n");
- bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
- 0x1a /*MV_SCRATCH_MISC*/,
- (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
- bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
- 0x1a /*MV_SCRATCH_MISC*/,
- (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
-
- /* RGMII delay - Physical Control register bit[15:14] */
- debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
- /* forced 1000mbps full-duplex link */
- bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
- phydev->autoneg = AUTONEG_DISABLE;
- phydev->speed = SPEED_1000;
- phydev->duplex = DUPLEX_FULL;
-
- /* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
- bus->write(bus, 0x10, 0, 0x16, 0x8089);
- bus->write(bus, 0x11, 0, 0x16, 0x8089);
- bus->write(bus, 0x12, 0, 0x16, 0x8089);
- bus->write(bus, 0x13, 0, 0x16, 0x8089);
-
- return 0;
-}
-#endif // CONFIG_MV88E61XX_SWITCH
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FEC_MXC
- struct ventana_board_info *info = &ventana_info;
-
- if (test_bit(EECONFIG_ETH0, info->config)) {
- setup_iomux_enet(GP_PHY_RST);
- cpu_eth_init(bis);
- }
-#endif
-
-#ifdef CONFIG_E1000
- e1000_initialize(bis);
-#endif
-
-#ifdef CONFIG_CI_UDC
- /* For otg ethernet*/
- usb_eth_initialize(bis);
-#endif
-
- /* default to the first detected enet dev */
- if (!env_get("ethprime")) {
- struct eth_device *dev = eth_get_dev_by_index(0);
- if (dev) {
- env_set("ethprime", dev->name);
- printf("set ethprime to %s\n", env_get("ethprime"));
- }
- }
-
- return 0;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static void enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-static int detect_i2c(struct display_info_t const *dev)
-{
- return i2c_set_bus_num(dev->bus) == 0 &&
- i2c_probe(dev->addr) == 0;
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
-
- /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
- writel(reg, &iomux->gpr[2]);
-
- /* Enable Backlight */
- gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
- gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
- SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
- gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
-}
-
-struct display_info_t const displays[] = {{
- /* HDMI Output */
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
- .bus = 2,
- .addr = 0x4,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
- .enable = enable_lvds,
- .mode = {
- .name = "Hannstar-XGA",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- /* DLC700JMG-T-4 */
- .bus = 0,
- .addr = 0,
- .detect = NULL,
- .enable = enable_lvds,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .mode = {
- .name = "DLC700JMGT4",
- .refresh = 60,
- .xres = 1024, /* 1024x600active pixels */
- .yres = 600,
- .pixclock = 15385, /* 64MHz */
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- /* DLC800FIG-T-3 */
- .bus = 0,
- .addr = 0,
- .detect = NULL,
- .enable = enable_lvds,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .mode = {
- .name = "DLC800FIGT3",
- .refresh = 60,
- .xres = 1024, /* 1024x768 active pixels */
- .yres = 768,
- .pixclock = 15385, /* 64MHz */
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
- imx_setup_hdmi();
- /* Turn on LDB0,IPU,IPU DI0 clocks */
- reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* set LDB0, LDB1 clk select to 011/011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
- |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
- |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-
- /* LVDS Backlight GPIO on LVDS connector - output low */
- SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
- gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/* setup board specific PMIC */
-int power_init_board(void)
-{
- setup_pmic();
- return 0;
-}
-
-#if defined(CONFIG_CMD_PCI)
-int imx6_pcie_toggle_reset(void)
-{
- if (board_type < GW_UNKNOWN) {
- uint pin = gpio_cfg[board_type].pcie_rst;
- gpio_request(pin, "pci_rst#");
- gpio_direction_output(pin, 0);
- mdelay(50);
- gpio_direction_output(pin, 1);
- }
- return 0;
-}
-
-/*
- * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
- * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
- * properly and assert reset for 100ms.
- */
-#define MAX_PCI_DEVS 32
-struct pci_dev {
- pci_dev_t devfn;
- unsigned short vendor;
- unsigned short device;
- unsigned short class;
- unsigned short busno; /* subbordinate busno */
- struct pci_dev *ppar;
-};
-struct pci_dev pci_devs[MAX_PCI_DEVS];
-int pci_devno;
-int pci_bridgeno;
-
-void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
- unsigned short vendor, unsigned short device,
- unsigned short class)
-{
- int i;
- u32 dw;
- struct pci_dev *pdev = &pci_devs[pci_devno++];
-
- debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
-
- /* store array of devs for later use in device-tree fixup */
- pdev->devfn = dev;
- pdev->vendor = vendor;
- pdev->device = device;
- pdev->class = class;
- pdev->ppar = NULL;
- if (class == PCI_CLASS_BRIDGE_PCI)
- pdev->busno = ++pci_bridgeno;
- else
- pdev->busno = 0;
-
- /* fixup RC - it should be 00:00.0 not 00:01.0 */
- if (PCI_BUS(dev) == 0)
- pdev->devfn = 0;
-
- /* find dev's parent */
- for (i = 0; i < pci_devno; i++) {
- if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
- pdev->ppar = &pci_devs[i];
- break;
- }
- }
-
- /* assert downstream PERST# */
- if (vendor == PCI_VENDOR_ID_PLX &&
- (device & 0xfff0) == 0x8600 &&
- PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
- debug("configuring PLX 860X downstream PERST#\n");
- pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
- dw |= 0xaaa8; /* GPIO1-7 outputs */
- pci_hose_write_config_dword(hose, dev, 0x62c, dw);
-
- pci_hose_read_config_dword(hose, dev, 0x644, &dw);
- dw |= 0xfe; /* GPIO1-7 output high */
- pci_hose_write_config_dword(hose, dev, 0x644, dw);
-
- mdelay(100);
- }
-}
-#endif /* CONFIG_CMD_PCI */
-
-#ifdef CONFIG_SERIAL_TAG
-/*
- * called when setting up ATAGS before booting kernel
- * populate serialnum from the following (in order of priority):
- * serial# env var
- * eeprom
- */
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- char *serial = env_get("serial#");
-
- if (serial) {
- serialnr->high = 0;
- serialnr->low = simple_strtoul(serial, NULL, 10);
- } else if (ventana_info.model[0]) {
- serialnr->high = 0;
- serialnr->low = ventana_info.serial;
- } else {
- serialnr->high = 0;
- serialnr->low = 0;
- }
-}
-#endif
-
-/*
- * Board Support
- */
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-int board_init(void)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- clrsetbits_le32(&iomuxc_regs->gpr[1],
- IOMUXC_GPR1_OTG_ID_MASK,
- IOMUXC_GPR1_OTG_ID_GPIO1);
-
- /* address of linux boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- setup_gpmi_nand();
-#endif
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
- setup_ventana_i2c();
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
- /* read Gateworks EEPROM into global struct (used later) */
- board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
-
- setup_iomux_gpio(board_type, &ventana_info);
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
-/*
- * called during late init (after relocation and after board_init())
- * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
- * EEPROM read.
- */
-int checkboard(void)
-{
- struct ventana_board_info *info = &ventana_info;
- unsigned char buf[4];
- const char *p;
- int quiet; /* Quiet or minimal output mode */
-
- quiet = 0;
- p = env_get("quiet");
- if (p)
- quiet = simple_strtol(p, NULL, 10);
- else
- env_set("quiet", "0");
-
- puts("\nGateworks Corporation Copyright 2014\n");
- if (info->model[0]) {
- printf("Model: %s\n", info->model);
- printf("MFGDate: %02x-%02x-%02x%02x\n",
- info->mfgdate[0], info->mfgdate[1],
- info->mfgdate[2], info->mfgdate[3]);
- printf("Serial:%d\n", info->serial);
- } else {
- puts("Invalid EEPROM - board will not function fully\n");
- }
- if (quiet)
- return 0;
-
- /* Display GSC firmware revision/CRC/status */
- gsc_info(0);
-
- /* Display RTC */
- if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
- printf("RTC: %d\n",
- buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_BMODE
-/*
- * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
- * see Table 8-11 and Table 5-9
- * BOOT_CFG1[7] = 1 (boot from NAND)
- * BOOT_CFG1[5] = 0 - raw NAND
- * BOOT_CFG1[4] = 0 - default pad settings
- * BOOT_CFG1[3:2] = 00 - devices = 1
- * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
- * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
- * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
- * BOOT_CFG2[0] = 0 - Reset time 12ms
- */
-static const struct boot_mode board_boot_modes[] = {
- /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
- { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
- { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
- { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
- { NULL, 0 },
-};
-#endif
-
-/* late init */
-int misc_init_r(void)
-{
- struct ventana_board_info *info = &ventana_info;
- char buf[256];
- int i;
-
- /* set env vars based on EEPROM data */
- if (ventana_info.model[0]) {
- char str[16], fdt[36];
- char *p;
- const char *cputype = "";
-
- /*
- * FDT name will be prefixed with CPU type. Three versions
- * will be created each increasingly generic and bootloader
- * env scripts will try loading each from most specific to
- * least.
- */
- if (is_cpu_type(MXC_CPU_MX6Q) ||
- is_cpu_type(MXC_CPU_MX6D))
- cputype = "imx6q";
- else if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO))
- cputype = "imx6dl";
- env_set("soctype", cputype);
- if (8 << (ventana_info.nand_flash_size-1) >= 2048)
- env_set("flash_layout", "large");
- else
- env_set("flash_layout", "normal");
- memset(str, 0, sizeof(str));
- for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
- str[i] = tolower(info->model[i]);
- env_set("model", str);
- if (!env_get("fdt_file")) {
- sprintf(fdt, "%s-%s.dtb", cputype, str);
- env_set("fdt_file", fdt);
- }
- p = strchr(str, '-');
- if (p) {
- *p++ = 0;
-
- env_set("model_base", str);
- sprintf(fdt, "%s-%s.dtb", cputype, str);
- env_set("fdt_file1", fdt);
- if (board_type != GW551x &&
- board_type != GW552x &&
- board_type != GW553x &&
- board_type != GW560x)
- str[4] = 'x';
- str[5] = 'x';
- str[6] = 0;
- sprintf(fdt, "%s-%s.dtb", cputype, str);
- env_set("fdt_file2", fdt);
- }
-
- /* initialize env from EEPROM */
- if (test_bit(EECONFIG_ETH0, info->config) &&
- !env_get("ethaddr")) {
- eth_env_set_enetaddr("ethaddr", info->mac0);
- }
- if (test_bit(EECONFIG_ETH1, info->config) &&
- !env_get("eth1addr")) {
- eth_env_set_enetaddr("eth1addr", info->mac1);
- }
-
- /* board serial-number */
- sprintf(str, "%6d", info->serial);
- env_set("serial#", str);
-
- /* memory MB */
- sprintf(str, "%d", (int) (gd->ram_size >> 20));
- env_set("mem_mb", str);
- }
-
- /* Set a non-initialized hwconfig based on board configuration */
- if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
- buf[0] = 0;
- if (gpio_cfg[board_type].rs232_en)
- strcat(buf, "rs232;");
- for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
- char buf1[32];
- sprintf(buf1, "dio%d:mode=gpio;", i);
- if (strlen(buf) + strlen(buf1) < sizeof(buf))
- strcat(buf, buf1);
- }
- env_set("hwconfig", buf);
- }
-
- /* setup baseboard specific GPIO based on board and env */
- setup_board_gpio(board_type, info);
-
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
- /* disable boot watchdog */
- gsc_boot_wd_disable();
-
- return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-
-static int ft_sethdmiinfmt(void *blob, char *mode)
-{
- int off;
-
- if (!mode)
- return -EINVAL;
-
- off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
- if (off < 0)
- return off;
-
- if (0 == strcasecmp(mode, "yuv422bt656")) {
- u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
- 0x00, 0x00, 0x00 };
- mode = "422_ccir";
- fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
- fdt_setprop_u32(blob, off, "vidout_trc", 1);
- fdt_setprop_u32(blob, off, "vidout_blc", 1);
- fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
- printf(" set HDMI input mode to %s\n", mode);
- } else if (0 == strcasecmp(mode, "yuv422smp")) {
- u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
- 0x82, 0x81, 0x00 };
- mode = "422_smp";
- fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
- fdt_setprop_u32(blob, off, "vidout_trc", 0);
- fdt_setprop_u32(blob, off, "vidout_blc", 0);
- fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
- printf(" set HDMI input mode to %s\n", mode);
- } else {
- return -EINVAL;
- }
-
- return 0;
-}
-
-/* enable a property of a node if the node is found */
-static inline void ft_enable_path(void *blob, const char *path)
-{
- int i = fdt_path_offset(blob, path);
- if (i >= 0) {
- debug("enabling %s\n", path);
- fdt_status_okay(blob, i);
- }
-}
-
-/* remove a property of a node if the node is found */
-static inline void ft_delprop_path(void *blob, const char *path,
- const char *name)
-{
- int i = fdt_path_offset(blob, path);
- if (i) {
- debug("removing %s/%s\n", path, name);
- fdt_delprop(blob, i, name);
- }
-}
-
-#if defined(CONFIG_CMD_PCI)
-#define PCI_ID(x) ( \
- (PCI_BUS(x->devfn)<<16)| \
- (PCI_DEV(x->devfn)<<11)| \
- (PCI_FUNC(x->devfn)<<8) \
- )
-#define PCIE_PATH "/soc/pcie@0x01000000"
-int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
-{
- uint32_t reg[5];
- char node[32];
- int np;
-
- sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
- PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
-
- np = fdt_subnode_offset(blob, par, node);
- if (np >= 0)
- return np;
- np = fdt_add_subnode(blob, par, node);
- if (np < 0) {
- printf(" %s failed: no space\n", __func__);
- return np;
- }
-
- memset(reg, 0, sizeof(reg));
- reg[0] = cpu_to_fdt32(PCI_ID(dev));
- fdt_setprop(blob, np, "reg", reg, sizeof(reg));
-
- return np;
-}
-
-/* build a path of nested PCI devs for all bridges passed through */
-int fdt_add_pci_path(void *blob, struct pci_dev *dev)
-{
- struct pci_dev *bridges[MAX_PCI_DEVS];
- int k, np;
-
- /* build list of parents */
- np = fdt_path_offset(blob, PCIE_PATH);
- if (np < 0)
- return np;
-
- k = 0;
- while (dev) {
- bridges[k++] = dev;
- dev = dev->ppar;
- };
-
- /* now add them the to DT in reverse order */
- while (k--) {
- np = fdt_add_pci_node(blob, np, bridges[k]);
- if (np < 0)
- break;
- }
-
- return np;
-}
-
-/*
- * The GW16082 has a hardware errata errata such that it's
- * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
- * of this normal PCI interrupt swizzling will not work so we will
- * provide an irq-map via device-tree.
- */
-int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
-{
- int len;
- int host;
- uint32_t imap_new[8*4*4];
- const uint32_t *imap;
- uint32_t irq[4];
- uint32_t reg[4];
- int i;
-
- /* build irq-map based on host controllers map */
- host = fdt_path_offset(blob, PCIE_PATH);
- if (host < 0) {
- printf(" %s failed: missing host\n", __func__);
- return host;
- }
-
- /* use interrupt data from root complex's node */
- imap = fdt_getprop(blob, host, "interrupt-map", &len);
- if (!imap || len != 128) {
- printf(" %s failed: invalid interrupt-map\n",
- __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- /* obtain irq's of host controller in pin order */
- for (i = 0; i < 4; i++)
- irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
-
- /*
- * determine number of swizzles necessary:
- * For each bridge we pass through we need to swizzle
- * the number of the slot we are on.
- */
- struct pci_dev *d;
- int b;
- b = 0;
- d = dev->ppar;
- while(d && d->ppar) {
- b += PCI_DEV(d->devfn);
- d = d->ppar;
- }
-
- /* create new irq mappings for slots12-15
- * <skt> <idsel> <slot> <skt-inta> <skt-intb>
- * J3 AD28 12 INTD INTA
- * J4 AD29 13 INTC INTD
- * J5 AD30 14 INTB INTC
- * J2 AD31 15 INTA INTB
- */
- for (i = 0; i < 4; i++) {
- /* addr matches bus:dev:func */
- u32 addr = dev->busno << 16 | (12+i) << 11;
-
- /* default cells from root complex */
- memcpy(&imap_new[i*32], imap, 128);
- /* first cell is PCI device address (BDF) */
- imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
- imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
- imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
- imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
- /* third cell is pin */
- imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
- imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
- imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
- imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
- /* sixth cell is relative interrupt */
- imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
- imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
- imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
- imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
- }
- fdt_setprop(blob, np, "interrupt-map", imap_new,
- sizeof(imap_new));
- reg[0] = cpu_to_fdt32(0xfff00);
- reg[1] = 0;
- reg[2] = 0;
- reg[3] = cpu_to_fdt32(0x7);
- fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
- fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
- fdt_setprop_string(blob, np, "device_type", "pci");
- fdt_setprop_cell(blob, np, "#address-cells", 3);
- fdt_setprop_cell(blob, np, "#size-cells", 2);
- printf(" Added custom interrupt-map for GW16082\n");
-
- return 0;
-}
-
-/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
-int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
-{
- char *tmp, *end;
- char mac[16];
- unsigned char mac_addr[6];
- int j;
-
- sprintf(mac, "eth1addr");
- tmp = env_get(mac);
- if (tmp) {
- for (j = 0; j < 6; j++) {
- mac_addr[j] = tmp ?
- simple_strtoul(tmp, &end,16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
- }
- fdt_setprop(blob, np, "local-mac-address", mac_addr,
- sizeof(mac_addr));
- printf(" Added mac addr for eth1\n");
- return 0;
- }
-
- return -1;
-}
-
-/*
- * PCI DT nodes must be nested therefore if we need to apply a DT fixup
- * we will walk the PCI bus and add bridge nodes up to the device receiving
- * the fixup.
- */
-void ft_board_pci_fixup(void *blob, bd_t *bd)
-{
- int i, np;
- struct pci_dev *dev;
-
- for (i = 0; i < pci_devno; i++) {
- dev = &pci_devs[i];
-
- /*
- * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
- * an EEPROM@i2c1-0x50.
- */
- if ((dev->vendor == PCI_VENDOR_ID_TI) &&
- (dev->device == 0x8240) &&
- (i2c_set_bus_num(1) == 0) &&
- (i2c_probe(0x50) == 0))
- {
- np = fdt_add_pci_path(blob, dev);
- if (np > 0)
- fdt_fixup_gw16082(blob, np, dev);
- }
-
- /* ethernet1 mac address */
- else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
- (dev->device == 0x4380))
- {
- np = fdt_add_pci_path(blob, dev);
- if (np > 0)
- fdt_fixup_sky2(blob, np, dev);
- }
- }
-}
-#endif /* if defined(CONFIG_CMD_PCI) */
-
-void ft_board_wdog_fixup(void *blob, const char *path)
-{
- ft_delprop_path(blob, path, "ext-reset-output");
- ft_delprop_path(blob, path, "fsl,ext-reset-output");
-}
-
-/*
- * called prior to booting kernel or by 'fdt boardsetup' command
- *
- * unless 'fdt_noauto' env var is set we will update the following in the DTB:
- * - mtd partitions based on mtdparts/mtdids env
- * - system-serial (board serial num from EEPROM)
- * - board (full model from EEPROM)
- * - peripherals removed from DTB if not loaded on board (per EEPROM config)
- */
-#define UART1_PATH "/soc/aips-bus at 02100000/serial at 021ec000"
-#define WDOG1_PATH "/soc/aips-bus at 02000000/wdog at 020bc000"
-#define WDOG2_PATH "/soc/aips-bus at 02000000/wdog at 020c0000"
-#define GPIO3_PATH "/soc/aips-bus at 02000000/gpio at 020a4000"
-int ft_board_setup(void *blob, bd_t *bd)
-{
- struct ventana_board_info *info = &ventana_info;
- struct ventana_eeprom_config *cfg;
- static const struct node_info nodes[] = {
- { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
- { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
- };
- const char *model = env_get("model");
- const char *display = env_get("display");
- int i;
- char rev = 0;
-
- /* determine board revision */
- for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
- if (ventana_info.model[i] >= 'A') {
- rev = ventana_info.model[i];
- break;
- }
- }
-
- if (env_get("fdt_noauto")) {
- puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
- return 0;
- }
-
- if (test_bit(EECONFIG_NAND, info->config)) {
- /* Update partition nodes using info from mtdparts env var */
- puts(" Updating MTD partitions...\n");
- fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
- }
-
- /* Update display timings from display env var */
- if (display) {
- if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
- display) >= 0)
- printf(" Set display timings for %s...\n", display);
- }
-
- printf(" Adjusting FDT per EEPROM for %s...\n", model);
-
- /* board serial number */
- fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
- strlen(env_get("serial#")) + 1);
-
- /* board (model contains model from device-tree) */
- fdt_setprop(blob, 0, "board", info->model,
- strlen((const char *)info->model) + 1);
-
- /* set desired digital video capture format */
- ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
-
- /*
- * Board model specific fixups
- */
- switch (board_type) {
- case GW51xx:
- /*
- * disable wdog node for GW51xx-A/B to work around
- * errata causing wdog timer to be unreliable.
- */
- if (rev >= 'A' && rev < 'C') {
- i = fdt_path_offset(blob, WDOG1_PATH);
- if (i)
- fdt_status_disabled(blob, i);
- }
-
- /* GW51xx-E adds WDOG1_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_PATH);
- break;
-
- case GW52xx:
- /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
- if (info->model[4] == '2') {
- u32 handle = 0;
- u32 *range = NULL;
-
- i = fdt_node_offset_by_compatible(blob, -1,
- "fsl,imx6q-pcie");
- if (i)
- range = (u32 *)fdt_getprop(blob, i,
- "reset-gpio", NULL);
-
- if (range) {
- i = fdt_path_offset(blob, GPIO3_PATH);
- if (i)
- handle = fdt_get_phandle(blob, i);
- if (handle) {
- range[0] = cpu_to_fdt32(handle);
- range[1] = cpu_to_fdt32(23);
- }
- }
-
- /* these have broken usd_vsel */
- if (strstr((const char *)info->model, "SP318-B") ||
- strstr((const char *)info->model, "SP331-B"))
- gpio_cfg[board_type].usd_vsel = 0;
-
- /* GW522x-B adds WDOG1_B external reset */
- ft_board_wdog_fixup(blob, WDOG1_PATH);
- }
-
- /* GW520x-E adds WDOG1_B external reset */
- else if (info->model[4] == '0' && rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_PATH);
- break;
-
- case GW53xx:
- /* GW53xx-E adds WDOG1_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG1_PATH);
- break;
-
- case GW54xx:
- /*
- * disable serial2 node for GW54xx for compatibility with older
- * 3.10.x kernel that improperly had this node enabled in the DT
- */
- i = fdt_path_offset(blob, UART1_PATH);
- if (i)
- fdt_del_node(blob, i);
-
- /* GW54xx-E adds WDOG2_B external reset */
- if (rev < 'E')
- ft_board_wdog_fixup(blob, WDOG2_PATH);
- break;
-
- case GW551x:
- /*
- * isolate CSI0_DATA_EN for GW551x-A to work around errata
- * causing non functional digital video in (it is not hooked up)
- */
- if (rev == 'A') {
- u32 *range = NULL;
- int len;
- const u32 *handle = NULL;
-
- i = fdt_node_offset_by_compatible(blob, -1,
- "fsl,imx-tda1997x-video");
- if (i)
- handle = fdt_getprop(blob, i, "pinctrl-0",
- NULL);
- if (handle)
- i = fdt_node_offset_by_phandle(blob,
- fdt32_to_cpu(*handle));
- if (i)
- range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
- &len);
- if (range) {
- len /= sizeof(u32);
- for (i = 0; i < len; i += 6) {
- u32 mux_reg = fdt32_to_cpu(range[i+0]);
- u32 conf_reg = fdt32_to_cpu(range[i+1]);
- /* mux PAD_CSI0_DATA_EN to GPIO */
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- mux_reg == 0x260 &&
- conf_reg == 0x630)
- range[i+3] = cpu_to_fdt32(0x5);
- else if (!is_cpu_type(MXC_CPU_MX6Q) &&
- mux_reg == 0x08c &&
- conf_reg == 0x3a0)
- range[i+3] = cpu_to_fdt32(0x5);
- }
- fdt_setprop_inplace(blob, i, "fsl,pins", range,
- len);
- }
-
- /* set BT656 video format */
- ft_sethdmiinfmt(blob, "yuv422bt656");
- }
-
- /* GW551x-C adds WDOG1_B external reset */
- if (rev < 'C')
- ft_board_wdog_fixup(blob, WDOG1_PATH);
- break;
- }
-
- /* Configure DIO */
- for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
- struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
- char arg[10];
-
- sprintf(arg, "dio%d", i);
- if (!hwconfig(arg))
- continue;
- if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
- {
- char path[48];
- sprintf(path, "/soc/aips-bus at 02000000/pwm@%08x",
- 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
- printf(" Enabling pwm%d for DIO%d\n",
- cfg->pwm_param, i);
- ft_enable_path(blob, path);
- }
- }
-
- /* remove no-1-8-v if UHS-I support is present */
- if (gpio_cfg[board_type].usd_vsel) {
- debug("Enabling UHS-I support\n");
- ft_delprop_path(blob, "/soc/aips-bus at 02100000/usdhc at 02198000",
- "no-1-8-v");
- }
-
-#if defined(CONFIG_CMD_PCI)
- if (!env_get("nopcifixup"))
- ft_board_pci_fixup(blob, bd);
-#endif
-
- /*
- * Peripheral Config:
- * remove nodes by alias path if EEPROM config tells us the
- * peripheral is not loaded on the board.
- */
- if (env_get("fdt_noconfig")) {
- puts(" Skiping periperhal config (fdt_noconfig defined)\n");
- return 0;
- }
- cfg = econfig;
- while (cfg->name) {
- if (!test_bit(cfg->bit, info->config)) {
- fdt_del_node_and_alias(blob, cfg->dtalias ?
- cfg->dtalias : cfg->name);
- }
- cfg++;
- }
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-static struct mxc_serial_platdata ventana_mxc_serial_plat = {
- .reg = (struct mxc_uart *)UART2_BASE,
-};
-
-U_BOOT_DEVICE(ventana_serial) = {
- .name = "serial_mxc",
- .platdata = &ventana_mxc_serial_plat,
-};
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
deleted file mode 100644
index a6ac546e959..00000000000
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ /dev/null
@@ -1,691 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Gateworks Corporation
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <environment.h>
-#include <i2c.h>
-#include <spl.h>
-
-#include "gsc.h"
-#include "common.h"
-
-#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
-#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
-#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
-
-/* configure MX6Q/DUAL mmdc DDR io registers */
-struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
- /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- /* SDCKE[0:1]: 100k pull-up */
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- /* SDBA2: pull-up disabled */
- .dram_sdba2 = 0x00000000,
- /* SDODT[0:1]: 100k pull-up, 40 ohm */
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- /* SDQS[0:7]: Differential input, 40 ohm */
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
-
- /* DQM[0:7]: Differential input, 40 ohm */
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-/* configure MX6Q/DUAL mmdc GRP io registers */
-struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
- /* DDR3 */
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- /* disable DDR pullups */
- .grp_ddrpke = 0x00000000,
- /* ADDR[00:16], SDBA[0:1]: 40 ohm */
- .grp_addds = 0x00000030,
- /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
- .grp_ctlds = 0x00000030,
- /* DATA[00:63]: Differential input, 40 ohm */
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- /* SDCKE[0:1]: 100k pull-up */
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- /* SDBA2: pull-up disabled */
- .dram_sdba2 = 0x00000000,
- /* SDODT[0:1]: 100k pull-up, 40 ohm */
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- /* SDQS[0:7]: Differential input, 40 ohm */
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
-
- /* DQM[0:7]: Differential input, 40 ohm */
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- /* DDR3 */
- .grp_ddr_type = 0x000c0000,
- /* SDQS[0:7]: Differential input, 40 ohm */
- .grp_ddrmode_ctl = 0x00020000,
- /* disable DDR pullups */
- .grp_ddrpke = 0x00000000,
- /* ADDR[00:16], SDBA[0:1]: 40 ohm */
- .grp_addds = 0x00000030,
- /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
- .grp_ctlds = 0x00000030,
- /* DATA[00:63]: Differential input, 40 ohm */
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-/* MT41K64M16JT-125 (1Gb density) */
-static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
- .mem_speed = 1600,
- .density = 1,
- .width = 16,
- .banks = 8,
- .rowaddr = 13,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* MT41K128M16JT-125 (2Gb density) */
-static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* MT41K256M16HA-125 (4Gb density) */
-static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* MT41K512M16HA-125 (8Gb density) */
-static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
- .mem_speed = 1600,
- .density = 8,
- .width = 16,
- .banks = 8,
- .rowaddr = 16,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/*
- * calibration - these are the various CPU/DDR3 combinations we support
- */
-static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x004C004E,
- .p0_mpwldectrl1 = 0x00440044,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x42440247,
- .p0_mpdgctrl1 = 0x02310232,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x45424746,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x33382C31,
-};
-
-static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x001B0016,
- .p0_mpwldectrl1 = 0x000C000E,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x4324033A,
- .p0_mpdgctrl1 = 0x00000000,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x40403438,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x40403D36,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00420043,
- .p0_mpwldectrl1 = 0x0016001A,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x4238023B,
- .p0_mpdgctrl1 = 0x00000000,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x40404849,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x40402E2F,
-};
-
-static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00190017,
- .p0_mpwldectrl1 = 0x00140026,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x43380347,
- .p0_mpdgctrl1 = 0x433C034D,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x3C313539,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x36393C39,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x003C003C,
- .p0_mpwldectrl1 = 0x001F002A,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x42410244,
- .p0_mpdgctrl1 = 0x4234023A,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x484A4C4B,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x33342B32,
-};
-
-static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00190017,
- .p0_mpwldectrl1 = 0x00140026,
- .p1_mpwldectrl0 = 0x0021001C,
- .p1_mpwldectrl1 = 0x0011001D,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x43380347,
- .p0_mpdgctrl1 = 0x433C034D,
- .p1_mpdgctrl0 = 0x032C0324,
- .p1_mpdgctrl1 = 0x03310232,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x3C313539,
- .p1_mprddlctl = 0x37343141,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x36393C39,
- .p1_mpwrdlctl = 0x42344438,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x003C003C,
- .p0_mpwldectrl1 = 0x001F002A,
- .p1_mpwldectrl0 = 0x00330038,
- .p1_mpwldectrl1 = 0x0022003F,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x42410244,
- .p0_mpdgctrl1 = 0x4234023A,
- .p1_mpdgctrl0 = 0x022D022D,
- .p1_mpdgctrl1 = 0x021C0228,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x484A4C4B,
- .p1_mprddlctl = 0x4B4D4E4B,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x33342B32,
- .p1_mpwrdlctl = 0x3933332B,
-};
-
-static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x001E001A,
- .p0_mpwldectrl1 = 0x0026001F,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x43370349,
- .p0_mpdgctrl1 = 0x032D0327,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x3D303639,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x32363934,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0X00480047,
- .p0_mpwldectrl1 = 0X003D003F,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0X423E0241,
- .p0_mpdgctrl1 = 0X022B022C,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0X49454A4A,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0X2E372C32,
-};
-
-static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0X00220021,
- .p0_mpwldectrl1 = 0X00200030,
- .p1_mpwldectrl0 = 0X002D0027,
- .p1_mpwldectrl1 = 0X00150026,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x43330342,
- .p0_mpdgctrl1 = 0x0339034A,
- .p1_mpdgctrl0 = 0x032F0325,
- .p1_mpdgctrl1 = 0x032F022E,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0X3A2E3437,
- .p1_mprddlctl = 0X35312F3F,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0X33363B37,
- .p1_mpwrdlctl = 0X40304239,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x0048004A,
- .p0_mpwldectrl1 = 0x003F004A,
- .p1_mpwldectrl0 = 0x001E0028,
- .p1_mpwldectrl1 = 0x002C0043,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x02250219,
- .p0_mpdgctrl1 = 0x01790202,
- .p1_mpdgctrl0 = 0x02080208,
- .p1_mpdgctrl1 = 0x016C0175,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x4A4C4D4C,
- .p1_mprddlctl = 0x494C4A48,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x403F3437,
- .p1_mpwrdlctl = 0x383A3930,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x001F003F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x001F004E,
- .p1_mpwldectrl1 = 0x0059001F,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x42220225,
- .p0_mpdgctrl1 = 0x0213021F,
- .p1_mpdgctrl0 = 0x022C0242,
- .p1_mpdgctrl1 = 0x022C0244,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x474A4C4A,
- .p1_mprddlctl = 0x48494C45,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x3F3F3F36,
- .p1_mpwrdlctl = 0x3F36363F,
-};
-
-static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x002A0025,
- .p0_mpwldectrl1 = 0x003A002A,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x43430356,
- .p0_mpdgctrl1 = 0x033C0335,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x4B373F42,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x303E3C36,
-};
-
-static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00230020,
- .p0_mpwldectrl1 = 0x002F002A,
- .p1_mpwldectrl0 = 0x001D0027,
- .p1_mpwldectrl1 = 0x00100023,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x03250339,
- .p0_mpdgctrl1 = 0x031C0316,
- .p1_mpdgctrl0 = 0x03210331,
- .p1_mpdgctrl1 = 0x031C025A,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x40373C40,
- .p1_mprddlctl = 0x3A373646,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x2E353933,
- .p1_mpwrdlctl = 0x3C2F3F35,
-};
-
-static void spl_dram_init(int width, int size_mb, int board_model)
-{
- struct mx6_ddr3_cfg *mem = NULL;
- struct mx6_mmdc_calibration *calib = NULL;
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = width/32,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
-#ifdef RTT_NOM_120OHM
- .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
-#else
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
-#endif
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .pd_fast_exit = 1, /* enable precharge power-down fast exit */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- /*
- * MMDC Calibration requires the following data:
- * mx6_mmdc_calibration - board-specific calibration (routing delays)
- * these calibration values depend on board routing, SoC, and DDR
- * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
- * mx6_ddr_cfg - chip specific timing/layout details
- */
- if (width == 16 && size_mb == 128) {
- mem = &mt41k64m16jt_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- ;
- else
- calib = &mx6sdl_64x16_mmdc_calib;
- debug("1gB density\n");
- } else if (width == 16 && size_mb == 256) {
- /* 1x 2Gb density chip - same calib as 2x 2Gb */
- mem = &mt41k128m16jt_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_128x32_mmdc_calib;
- else
- calib = &mx6sdl_128x32_mmdc_calib;
- debug("2gB density\n");
- } else if (width == 16 && size_mb == 512) {
- mem = &mt41k256m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_256x16_mmdc_calib;
- else
- calib = &mx6sdl_256x16_mmdc_calib;
- debug("4gB density\n");
- } else if (width == 32 && size_mb == 256) {
- /* Same calib as width==16, size==128 */
- mem = &mt41k64m16jt_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- ;
- else
- calib = &mx6sdl_64x16_mmdc_calib;
- debug("1gB density\n");
- } else if (width == 32 && size_mb == 512) {
- mem = &mt41k128m16jt_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_128x32_mmdc_calib;
- else
- calib = &mx6sdl_128x32_mmdc_calib;
- debug("2gB density\n");
- } else if (width == 32 && size_mb == 1024) {
- mem = &mt41k256m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_256x32_mmdc_calib;
- else
- calib = &mx6sdl_256x32_mmdc_calib;
- debug("4gB density\n");
- } else if (width == 32 && size_mb == 2048) {
- mem = &mt41k512m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_512x32_mmdc_calib;
- debug("8gB density\n");
- } else if (width == 64 && size_mb == 512) {
- mem = &mt41k64m16jt_125;
- debug("1gB density\n");
- } else if (width == 64 && size_mb == 1024) {
- mem = &mt41k128m16jt_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_128x64_mmdc_calib;
- else
- calib = &mx6sdl_128x64_mmdc_calib;
- debug("2gB density\n");
- } else if (width == 64 && size_mb == 2048) {
- mem = &mt41k256m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_256x64_mmdc_calib;
- else
- calib = &mx6sdl_256x64_mmdc_calib;
- debug("4gB density\n");
- } else if (width == 64 && size_mb == 4096) {
- switch(board_model) {
- case GW5903:
- /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
- mem = &mt41k256m16ha_125;
- debug("4gB density\n");
- if (!is_cpu_type(MXC_CPU_MX6Q)) {
- calib = &mx6sdl_256x64x2_mmdc_calib;
- sysinfo.ncs = 2;
- sysinfo.cs_density = 18; /* CS0_END=71 */
- sysinfo.cs1_mirror = 1; /* mirror enabled */
- }
- break;
- default:
- mem = &mt41k512m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_512x64_mmdc_calib;
- debug("8gB density\n");
- break;
- }
- }
-
- if (!(mem && calib)) {
- puts("Error: Invalid Calibration/Board Configuration\n");
- printf("MEM : %s\n", mem ? "OKAY" : "NULL");
- printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
- printf("CPUTYPE: %s\n",
- is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
- printf("SIZE_MB: %d\n", size_mb);
- printf("WIDTH : %d\n", width);
- hang();
- }
-
- if (is_cpu_type(MXC_CPU_MX6Q))
- mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
- &mx6dq_grp_ioregs);
- else
- mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
- &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&sysinfo, calib, mem);
-}
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-/*
- * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
- * - we have a stack and a place to store GD, both in SRAM
- * - no variable global data is available
- */
-void board_init_f(ulong dummy)
-{
- struct ventana_board_info ventana_info;
- int board_model;
-
- /* setup clock gating */
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- /* setup AXI */
- gpr_init();
-
- /* iomux and setup of i2c */
- setup_iomux_uart();
- setup_ventana_i2c();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* read/validate EEPROM info to determine board model and SDRAM cfg */
- board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
-
- /* configure model-specific gpio */
- setup_iomux_gpio(board_model, &ventana_info);
-
- /* provide some some default: 32bit 128MB */
- if (GW_UNKNOWN == board_model)
- hang();
-
- /* configure MMDC for SDRAM width/size and per-model calibration */
- spl_dram_init(8 << ventana_info.sdram_width,
- 16 << ventana_info.sdram_size,
- board_model);
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
- spl_boot_list[0] = spl_boot_device();
- switch (spl_boot_list[0]) {
- case BOOT_DEVICE_NAND:
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_UART;
- break;
- case BOOT_DEVICE_MMC1:
- spl_boot_list[1] = BOOT_DEVICE_UART;
- break;
- }
-}
-
-/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
-/* its our chance to print info about boot device */
-void spl_board_init(void)
-{
- /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
- u32 boot_device = spl_boot_device();
-
- switch (boot_device) {
- case BOOT_DEVICE_MMC1:
- puts("Booting from MMC\n");
- break;
- case BOOT_DEVICE_NAND:
- puts("Booting from NAND\n");
- break;
- case BOOT_DEVICE_SATA:
- puts("Booting from SATA\n");
- break;
- default:
- puts("Unknown boot device\n");
- }
-
- /* PMIC init */
- setup_pmic();
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/* return 1 if we wish to boot to uboot vs os (falcon mode) */
-int spl_start_uboot(void)
-{
- unsigned char ret = 1;
-
- debug("%s\n", __func__);
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_load();
- debug("boot_os=%s\n", env_get("boot_os"));
- if (env_get_yesno("boot_os") == 1)
- ret = 0;
-#else
- /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
- i2c_set_bus_num(0);
- gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
-#endif
- if (!ret)
- gsc_boot_wd_disable();
-
- debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
- return ret;
-}
-#endif
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
deleted file mode 100644
index d2a16f1a008..00000000000
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Gateworks Corporation
- */
-
-#ifndef _VENTANA_EEPROM_
-#define _VENTANA_EEPROM_
-
-struct ventana_board_info {
- u8 mac0[6]; /* 0x00: MAC1 */
- u8 mac1[6]; /* 0x06: MAC2 */
- u8 res0[12]; /* 0x0C: reserved */
- u32 serial; /* 0x18: Serial Number (read only) */
- u8 res1[4]; /* 0x1C: reserved */
- u8 mfgdate[4]; /* 0x20: MFG date (read only) */
- u8 res2[7]; /* 0x24 */
- /* sdram config */
- u8 sdram_size; /* 0x2B: (16 << n) MB */
- u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
- u8 sdram_width; /* 0x2D: (8 << n) bit */
- /* cpu config */
- u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */
- u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */
- u8 model[16]; /* 0x30: model string */
- /* FLASH config */
- u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */
- u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */
-
- /* Config1: SoC Peripherals */
- u8 config[8]; /* 0x42: loading options */
-
- u8 res3[4]; /* 0x4A */
-
- u8 chksum[2]; /* 0x4E */
-};
-
-/* config bits */
-enum {
- EECONFIG_ETH0,
- EECONFIG_ETH1,
- EECONFIG_HDMI_OUT,
- EECONFIG_SATA,
- EECONFIG_PCIE,
- EECONFIG_SSI0,
- EECONFIG_SSI1,
- EECONFIG_LCD,
- EECONFIG_LVDS0,
- EECONFIG_LVDS1,
- EECONFIG_USB0,
- EECONFIG_USB1,
- EECONFIG_SD0,
- EECONFIG_SD1,
- EECONFIG_SD2,
- EECONFIG_SD3,
- EECONFIG_UART0,
- EECONFIG_UART1,
- EECONFIG_UART2,
- EECONFIG_UART3,
- EECONFIG_UART4,
- EECONFIG_IPU0,
- EECONFIG_IPU1,
- EECONFIG_FLEXCAN,
- EECONFIG_MIPI_DSI,
- EECONFIG_MIPI_CSI,
- EECONFIG_TZASC0,
- EECONFIG_TZASC1,
- EECONFIG_I2C0,
- EECONFIG_I2C1,
- EECONFIG_I2C2,
- EECONFIG_VPU,
- EECONFIG_CSI0,
- EECONFIG_CSI1,
- EECONFIG_CAAM,
- EECONFIG_MEZZ,
- EECONFIG_RES1,
- EECONFIG_RES2,
- EECONFIG_RES3,
- EECONFIG_RES4,
- EECONFIG_ESPCI0,
- EECONFIG_ESPCI1,
- EECONFIG_ESPCI2,
- EECONFIG_ESPCI3,
- EECONFIG_ESPCI4,
- EECONFIG_ESPCI5,
- EECONFIG_RES5,
- EECONFIG_RES6,
- EECONFIG_GPS,
- EECONFIG_SPIFL0,
- EECONFIG_SPIFL1,
- EECONFIG_GSPBATT,
- EECONFIG_HDMI_IN,
- EECONFIG_VID_OUT,
- EECONFIG_VID_IN,
- EECONFIG_NAND,
- EECONFIG_RES8,
- EECONFIG_RES9,
- EECONFIG_RES10,
- EECONFIG_RES11,
- EECONFIG_RES12,
- EECONFIG_RES13,
- EECONFIG_RES14,
- EECONFIG_RES15,
-};
-
-enum {
- GW54proto, /* original GW5400-A prototype */
- GW51xx,
- GW52xx,
- GW53xx,
- GW54xx,
- GW551x,
- GW552x,
- GW553x,
- GW560x,
- GW5903,
- GW5904,
- GW_UNKNOWN,
- GW_BADCRC,
-};
-
-/* config items */
-struct ventana_eeprom_config {
- const char *name; /* name of item */
- const char *dtalias; /* name of dt node to remove if not set */
- int bit; /* bit within config */
-};
-
-extern struct ventana_eeprom_config econfig[];
-extern struct ventana_board_info ventana_info;
-
-int read_eeprom(int bus, struct ventana_board_info *);
-
-#endif
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
deleted file mode 100644
index eb7614a75a9..00000000000
--- a/configs/gwventana_emmc_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_GW_VENTANA=y
-CONFIG_CMD_EECONFIG=y
-CONFIG_CMD_GSC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x18000000
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Ventana > "
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_DEVICE=y
-CONFIG_PHYLIB=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
deleted file mode 100644
index e2408766e2e..00000000000
--- a/configs/gwventana_gw5904_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_GW_VENTANA=y
-CONFIG_CMD_EECONFIG=y
-CONFIG_CMD_GSC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x18000000
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Ventana > "
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_DEVICE=y
-CONFIG_PHYLIB=y
-CONFIG_MV88E61XX_SWITCH=y
-CONFIG_MV88E61XX_CPU_PORT=5
-CONFIG_MV88E61XX_PHY_PORTS=0xf
-CONFIG_MV88E61XX_FIXED_PORTS=0x0
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
deleted file mode 100644
index 83690f52580..00000000000
--- a/configs/gwventana_nand_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_GW_VENTANA=y
-CONFIG_CMD_EECONFIG=y
-CONFIG_CMD_GSC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x18000000
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Ventana > "
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_FSL_ESDHC=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_PHYLIB=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
deleted file mode 100644
index 6cafdc66859..00000000000
--- a/include/configs/gw_ventana.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Gateworks Corporation
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SPL */
-/* Location in NAND to read U-Boot from */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M)
-
-/* Falcon Mode */
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
-
-/* Falcon Mode - NAND support: args at 17MB kernel at 18MB */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M)
-
-/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
-
-#include "imx6_spl.h" /* common IMX6 SPL configuration */
-#include "mx6_common.h"
-
-#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
-
-/* Serial ATAG */
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
-/* Init Functions */
-
-/* Driver Model */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_THERMAL
-#endif
-
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
-/* Serial */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-#ifdef CONFIG_SPI_FLASH
-
-/* SPI */
-#ifdef CONFIG_CMD_SF
- #define CONFIG_SPI_FLASH_MTD
- #define CONFIG_SPI_FLASH_BAR
- #define CONFIG_SF_DEFAULT_BUS 0
- #define CONFIG_SF_DEFAULT_CS 0
- /* GPIO 3-19 (21248) */
- #define CONFIG_SF_DEFAULT_SPEED 30000000
- #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-#endif
-
-#elif defined(CONFIG_SPL_NAND_SUPPORT)
-/* Enable NAND support */
-#ifdef CONFIG_CMD_NAND
- #define CONFIG_SYS_MAX_NAND_DEVICE 1
- #define CONFIG_SYS_NAND_BASE 0x40000000
- #define CONFIG_SYS_NAND_5_ADDR_CYCLE
- #define CONFIG_SYS_NAND_ONFI_DETECTION
-
- /* DMA stuff, needed for GPMI/MXS NAND support */
-#endif
-
-#endif /* CONFIG_SPI_FLASH */
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_I2C_GSC 0
-#define CONFIG_I2C_EDID
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-/* eMMC Configs */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
- #define CONFIG_SYS_SATA_MAX_DEVICE 1
- #define CONFIG_DWC_AHSATA_PORT_ID 0
- #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
- #define CONFIG_LBA48
-#endif
-
-/*
- * PCI express
- */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCI_FIXUP_DEV
-#define CONFIG_PCIE_IMX
-#endif
-
-/*
- * PMIC
- */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-#define CONFIG_POWER_LTC3676
-#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c
-
-/* Various command support */
-#define CONFIG_CMD_UNZIP /* gzwrite */
-
-/* Ethernet support */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USBD_HS
-#define CONFIG_NETCONSOLE
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */
-
-/* Miscellaneous configurable options */
-#define CONFIG_HWCONFIG
-#define CONFIG_PREBOOT
-
-/* Memory configuration */
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/* Persistent Environment Config */
-#if defined(CONFIG_ENV_IS_IN_MMC)
- #define CONFIG_SYS_MMC_ENV_DEV 0
- #define CONFIG_SYS_MMC_ENV_PART 1
- #define CONFIG_ENV_OFFSET (709 * SZ_1K)
- #define CONFIG_ENV_SIZE (128 * SZ_1K)
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K))
-#elif defined(CONFIG_ENV_IS_IN_NAND)
- #define CONFIG_ENV_OFFSET (16 * SZ_1M)
- #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 * SZ_1K))
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
- #define CONFIG_ENV_OFFSET (512 * SZ_1K)
- #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
- #define CONFIG_ENV_SIZE (8 * SZ_1K)
- #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
- #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
- #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
- #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
-
-/* Environment */
-#define CONFIG_IPADDR 192.168.1.1
-#define CONFIG_SERVERIP 192.168.1.146
-
-#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
- "pcidisable=1\0" \
- "splashpos=m,m\0" \
- "usb_pgood_delay=2000\0" \
- "console=ttymxc1\0" \
- "bootdevs=usb mmc sata flash\0" \
- "hwconfig=_UNKNOWN_\0" \
- "video=\0" \
- \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "disk=0\0" \
- "part=1\0" \
- \
- "fdt_high=0xffffffff\0" \
- "fdt_addr=0x18000000\0" \
- "initrd_high=0xffffffff\0" \
- "fixfdt=" \
- "fdt addr ${fdt_addr}\0" \
- "bootdir=boot\0" \
- "loadfdt=" \
- "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
- "echo Loaded DTB from ${bootdir}/${fdt_file}; " \
- "run fixfdt; " \
- "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
- "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
- "run fixfdt; " \
- "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
- "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
- "run fixfdt; " \
- "fi\0" \
- \
- "fs=ext4\0" \
- "script=6x_bootscript-ventana\0" \
- "loadscript=" \
- "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
- "source ${loadaddr}; " \
- "fi\0" \
- \
- "uimage=uImage\0" \
- "mmc_root=mmcblk0p1\0" \
- "mmc_boot=" \
- "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
- "mmc dev ${disk} && mmc rescan && " \
- "setenv dtype mmc; run loadscript; " \
- "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
- "setenv bootargs console=${console},${baudrate} " \
- "root=/dev/${mmc_root} rootfstype=${fs} " \
- "rootwait rw ${video} ${extra}; " \
- "if run loadfdt; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "bootm; " \
- "fi; " \
- "fi\0" \
- \
- "sata_boot=" \
- "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \
- "sata init && " \
- "setenv dtype sata; run loadscript; " \
- "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
- "setenv bootargs console=${console},${baudrate} " \
- "root=/dev/sda1 rootfstype=${fs} " \
- "rootwait rw ${video} ${extra}; " \
- "if run loadfdt; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "bootm; " \
- "fi; " \
- "fi\0" \
- "usb_boot=" \
- "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \
- "usb start && usb dev ${disk} && " \
- "setenv dtype usb; run loadscript; " \
- "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
- "setenv bootargs console=${console},${baudrate} " \
- "root=/dev/sda1 rootfstype=${fs} " \
- "rootwait rw ${video} ${extra}; " \
- "if run loadfdt; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "bootm; " \
- "fi; " \
- "fi\0"
-
-#ifdef CONFIG_SPI_FLASH
- #define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_EXTRA_ENV_SETTINGS_COMMON \
- "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \
- "image_uboot=ventana/u-boot_spi.imx\0" \
- \
- "spi_koffset=0x90000\0" \
- "spi_klen=0x200000\0" \
- \
- "spi_updateuboot=echo Updating uboot from " \
- "${serverip}:${image_uboot}...; " \
- "tftpboot ${loadaddr} ${image_uboot} && " \
- "sf probe && sf erase 0 80000 && " \
- "sf write ${loadaddr} 400 ${filesize}\0" \
- "spi_update=echo Updating OS from ${serverip}:${image_os} " \
- "to ${spi_koffset} ...; " \
- "tftp ${loadaddr} ${image_os} && " \
- "sf probe && " \
- "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \
- \
- "flash_boot=" \
- "if sf probe && " \
- "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \
- "setenv bootargs console=${console},${baudrate} " \
- "root=/dev/mtdblock3 " \
- "rootfstype=squashfs,jffs2 " \
- "${video} ${extra}; " \
- "bootm; " \
- "fi\0"
-#else
- #define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_EXTRA_ENV_SETTINGS_COMMON \
- \
- "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
- "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
- "tftp ${loadaddr} ${image_rootfs} && " \
- "nand erase.part rootfs && " \
- "nand write ${loadaddr} rootfs ${filesize}\0" \
- \
- "flash_boot=" \
- "setenv fsload 'ubifsload'; " \
- "ubi part rootfs; " \
- "if ubi check boot; then " \
- "ubifsmount ubi0:boot; " \
- "setenv root ubi0:rootfs ubi.mtd=2 " \
- "rootfstype=squashfs,ubifs; " \
- "setenv bootdir; " \
- "elif ubi check rootfs; then " \
- "ubifsmount ubi0:rootfs; " \
- "setenv root ubi0:rootfs ubi.mtd=2 " \
- "rootfstype=ubifs; " \
- "fi; " \
- "setenv dtype nand; run loadscript; " \
- "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
- "setenv bootargs console=${console},${baudrate} " \
- "root=${root} ${video} ${extra}; " \
- "if run loadfdt; then " \
- "ubifsumount; " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "ubifsumount; bootm; " \
- "fi; " \
- "fi\0"
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "for btype in ${bootdevs}; do " \
- "echo; echo Attempting ${btype} boot...; " \
- "if run ${btype}_boot; then; fi; " \
- "done"
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 27/93] arm: Remove cairo board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (25 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 26/93] arm: Remove gwventana_gw5904 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 28/93] arm: Remove pico-hobbit-imx7d board Simon Glass
` (70 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/quipos/cairo/Kconfig | 12 --
board/quipos/cairo/MAINTAINERS | 6 -
board/quipos/cairo/Makefile | 6 -
board/quipos/cairo/cairo.c | 98 ---------
board/quipos/cairo/cairo.h | 318 ------------------------------
configs/cairo_defconfig | 39 ----
include/configs/omap3_cairo.h | 231 ----------------------
8 files changed, 711 deletions(-)
delete mode 100644 board/quipos/cairo/Kconfig
delete mode 100644 board/quipos/cairo/MAINTAINERS
delete mode 100644 board/quipos/cairo/Makefile
delete mode 100644 board/quipos/cairo/cairo.c
delete mode 100644 board/quipos/cairo/cairo.h
delete mode 100644 configs/cairo_defconfig
delete mode 100644 include/configs/omap3_cairo.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 4e8be5f9d04..8970a8023cb 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -209,6 +209,5 @@ source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
-source "board/quipos/cairo/Kconfig"
endif
diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig
deleted file mode 100644
index 8df9421b574..00000000000
--- a/board/quipos/cairo/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_CAIRO
-
-config SYS_BOARD
- default "cairo"
-
-config SYS_VENDOR
- default "quipos"
-
-config SYS_CONFIG_NAME
- default "omap3_cairo"
-
-endif
diff --git a/board/quipos/cairo/MAINTAINERS b/board/quipos/cairo/MAINTAINERS
deleted file mode 100644
index 01332da5ab3..00000000000
--- a/board/quipos/cairo/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CAIRO BOARD
-M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
-S: Maintained
-F: board/quipos/cairo/
-F: include/configs/omap3_cairo.h
-F: configs/cairo_defconfig
diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile
deleted file mode 100644
index ec2c83cc890..00000000000
--- a/board/quipos/cairo/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2014 DENX Software Engineering
-# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
-
-obj-y := cairo.o
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
deleted file mode 100644
index 8999542a7dd..00000000000
--- a/board/quipos/cairo/cairo.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2014 DENX
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * Derived from code written by Robert Aigner (ra at spiid.net)
- *
- * Itself derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <netdev.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <asm/mach-types.h>
-#include <asm/omap_mmc.h>
-#include "cairo.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_CAIRO();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank. This
- * provides the timing values back to the function that configures
- * the memory.
- *
- * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->sharing = SAMSUNG_SHARING;
- timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
- timings->ctrla = SAMSUNG_V_ACTIMA_165;
- timings->ctrlb = SAMSUNG_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- timings->mr = SAMSUNG_V_MR_165;
-}
-#endif
-
-static const struct ns16550_platdata cairo_serial = {
- .base = OMAP34XX_UART2,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(cairo_uart) = {
- "ns16550_serial",
- &cairo_serial
-};
-
-/* force SPL booting into U-Boot, not Linux */
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- return 1;
-}
-#endif
diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h
deleted file mode 100644
index f57a6081d82..00000000000
--- a/board/quipos/cairo/cairo.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) DENX
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * Original code (C) Copyright 2010
- * Robert Aigner (ra at spiid.net)
- */
-#ifndef _EVM_H_
-#define _EVM_H_
-
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 Cairo board",
- "NAND",
-};
-
-/*
- * OMAP3 Cairo handheld hardware revision
- */
-enum {
- OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */
- OMAP3_CAIRO_BOARD_GEN_2,
-};
-
-#define MUX_CAIRO() \
-MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
-MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
- (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-
-#endif
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
deleted file mode 100644
index dc1245f1bfb..00000000000
--- a/configs/cairo_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TARGET_OMAP3_CAIRO=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_BOOTDELAY=-2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Cairo # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_CONS_INDEX=2
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-# CONFIG_REGEX is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
deleted file mode 100644
index 04bce2f8b46..00000000000
--- a/include/configs/omap3_cairo.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for the QUIPOS Cairo board.
- *
- * Copyright (C) DENX GmbH
- *
- * Author :
- * Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * Derived from EVM code by
- * Manikandan Pillai <mani.pillai@ti.com>
- * Itself derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * Also derived from include/configs/omap3_beagle.h
- */
-
-#ifndef __OMAP3_CAIRO_CONFIG_H
-#define __OMAP3_CAIRO_CONFIG_H
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs. We use this rather than the inherited defines from
- * ti_armv7_common.h for backwards compatibility.
- */
-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
-#include <configs/ti_omap3_common.h>
-
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_ENV_OVERWRITE
-
-/* Enable Multi Bus support for I2C */
-#define CONFIG_I2C_MULTI_BUS 1
-
-/* Probe all devices */
-#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
-
-/*
- * TWL4030
- */
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "machid=ffffffff\0" \
- "fdt_high=0x87000000\0" \
- "baudrate=115200\0" \
- "fec_addr=00:50:C2:7E:90:F0\0" \
- "netmask=255.255.255.0\0" \
- "ipaddr=192.168.2.9\0" \
- "gateway=192.168.2.1\0" \
- "serverip=192.168.2.10\0" \
- "nfshost=192.168.2.10\0" \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "bootargs_mmc_ramdisk=mem=128M " \
- "console=ttyO1,115200n8 " \
- "root=/dev/ram0 rw " \
- "initrd=0x81600000,16M " \
- "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
- "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
- "mmcboot=mmc init; " \
- "fatload mmc 0 0x80000000 uImage; " \
- "fatload mmc 0 0x81600000 ramdisk.gz; " \
- "setenv bootargs ${bootargs_mmc_ramdisk}; " \
- "bootm 0x80000000\0" \
- "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
- "root=/dev/nfs " \
- "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
- "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
- "omap_vout.vid1_static_vrfb_alloc=y\0" \
- "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
- "bootm 0x80000000\0" \
- "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
- "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
- "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
- "omapfb.rotate_type=1\0" \
- "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
- "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
- "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
- "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
- "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
- "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
- "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
- "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
- "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
- "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
- "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
- "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
- "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
- "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
- "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
- "nand erase 0 20000; " \
- "fatload mmc 0 0x81600000 MLO; " \
- "nandecc hw; " \
- "nand write.i 0x81600000 0 20000;\0" \
- "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
- "nand erase 80000 40000; " \
- "fatload mmc 0 0x81600000 u-boot.bin; " \
- "nandecc sw; " \
- "nand write.i 0x81600000 80000 40000;\0" \
- "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
- "nand erase 280000 300000; " \
- "fatload mmc 0 0x81600000 uImage; " \
- "nandecc sw; " \
- "nand write.i 0x81600000 280000 300000;\0" \
- "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
- "nandecc sw; " \
- "nand write.jffs2 0x680000 0xFF ${filesize}; " \
- "nand erase 680000 ${filesize}; " \
- "nand write.jffs2 81600000 680000 ${filesize};\0" \
- "flash_scrub=nand scrub; " \
- "run flash_xloader; " \
- "run flash_uboot; " \
- "run flash_kernel; " \
- "run flash_rootfs;\0" \
- "flash_all=run ledred; " \
- "nand erase.chip; " \
- "run ledorange; " \
- "run flash_xloader; " \
- "run flash_uboot; " \
- "run flash_kernel; " \
- "run flash_rootfs; " \
- "run ledgreen; " \
- "run boot_nand; \0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
- "else run boot_nand; fi"
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-/* Defines for SPL */
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
-/* env defaults */
-#define CONFIG_BOOTFILE "uImage"
-
-/* Override OMAP3 common serial console configuration from UART3
- * to UART2.
- *
- * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
- * are needed and peripheral clocks for UART2 must be enabled in
- * function per_clocks_enable().
- */
-#ifdef CONFIG_SPL_BUILD
-#endif
-
-/* Provide the MACH_TYPE value the vendor kernel requires */
-#define CONFIG_MACH_TYPE 3063
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
- /* on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-#endif /* __OMAP3_CAIRO_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 28/93] arm: Remove pico-hobbit-imx7d board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (26 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 27/93] arm: Remove cairo board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 29/93] arm: Remove mccmon6_sd board Simon Glass
` (69 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx7/Kconfig | 1 -
board/technexion/pico-imx7d/Kconfig | 15 --
board/technexion/pico-imx7d/MAINTAINERS | 16 --
board/technexion/pico-imx7d/Makefile | 4 -
board/technexion/pico-imx7d/README | 64 -----
board/technexion/pico-imx7d/pico-imx7d.c | 315 -----------------------
board/technexion/pico-imx7d/spl.c | 122 ---------
configs/pico-hobbit-imx7d_defconfig | 60 -----
configs/pico-imx7d_defconfig | 60 -----
configs/pico-pi-imx7d_defconfig | 60 -----
include/configs/pico-imx7d.h | 151 -----------
11 files changed, 868 deletions(-)
delete mode 100644 board/technexion/pico-imx7d/Kconfig
delete mode 100644 board/technexion/pico-imx7d/MAINTAINERS
delete mode 100644 board/technexion/pico-imx7d/Makefile
delete mode 100644 board/technexion/pico-imx7d/README
delete mode 100644 board/technexion/pico-imx7d/pico-imx7d.c
delete mode 100644 board/technexion/pico-imx7d/spl.c
delete mode 100644 configs/pico-hobbit-imx7d_defconfig
delete mode 100644 configs/pico-imx7d_defconfig
delete mode 100644 configs/pico-pi-imx7d_defconfig
delete mode 100644 include/configs/pico-imx7d.h
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 329a4acaebb..63b90f99500 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -67,7 +67,6 @@ config SYS_SOC
source "board/compulab/cl-som-imx7/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
-source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
endif
diff --git a/board/technexion/pico-imx7d/Kconfig b/board/technexion/pico-imx7d/Kconfig
deleted file mode 100644
index f4ae18ca62f..00000000000
--- a/board/technexion/pico-imx7d/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PICO_IMX7D
-
-config SYS_BOARD
- default "pico-imx7d"
-
-config SYS_VENDOR
- default "technexion"
-
-config SYS_SOC
- default "mx7"
-
-config SYS_CONFIG_NAME
- default "pico-imx7d"
-
-endif
diff --git a/board/technexion/pico-imx7d/MAINTAINERS b/board/technexion/pico-imx7d/MAINTAINERS
deleted file mode 100644
index f9a1dfc05ec..00000000000
--- a/board/technexion/pico-imx7d/MAINTAINERS
+++ /dev/null
@@ -1,16 +0,0 @@
-TechNexion PICO-IMX7D board
-M: Vanessa Maegima <vanessa.maegima@nxp.com>
-S: Maintained
-F: board/technexion/pico-imx7d/
-F: include/configs/pico-imx7d.h
-F: configs/pico-imx7d_defconfig
-
-TechNexion PICO-HOBBIT-IMX7
-M: Otavio Salvador <otavio@ossystems.com.br>
-S: Maintained
-F: configs/pico-hobbit-imx7d_defconfig
-
-TechNexion PICO-PI-IMX7
-M: Otavio Salvador <otavio@ossystems.com.br>
-S: Maintained
-F: configs/pico-pi-imx7d_defconfig
diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile
deleted file mode 100644
index 4ae3d606b58..00000000000
--- a/board/technexion/pico-imx7d/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2017 NXP Semiconductors
-
-obj-y := pico-imx7d.o spl.o
diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README
deleted file mode 100644
index 24eb97e82cc..00000000000
--- a/board/technexion/pico-imx7d/README
+++ /dev/null
@@ -1,64 +0,0 @@
-How to update U-Boot on pico-imx7d board
-----------------------------------------
-
-Required software on the host PC:
-
-- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
-
-Build U-Boot for pico:
-
-$ make mrproper
-$ make pico-imx7d_defconfig
-$ make
-
-This generates the SPL and u-boot.img binaries.
-
-1. Loading U-Boot via USB Serial Download Protocol
-
-Note: This method is convenient for development purposes.
-If the eMMC has already a U-Boot flashed with DFU support then
-the user can go to step 2 below in order to update U-Boot.
-
-Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide
-page 3)
-
-Connect a USB to serial adapter between the host PC and pico.
-
-Connect a USB cable between the OTG pico port and the host PC.
-
-Open a terminal program such as minicom.
-
-Copy SPL and u-boot.img to the imx_usb_loader folder.
-
-Load the SPL binary via USB:
-
-$ sudo ./imx_usb SPL
-
-Load the u-boot.img binary via USB:
-
-$ sudo ./imx_usb u-boot.img
-
-Then U-Boot starts and its messages appear in the console program.
-
-Use the default environment variables:
-
-=> env default -f -a
-=> saveenv
-
-2. Flashing U-Boot into the eMMC
-
-Run the DFU agent so we can flash the new images using dfu-util tool:
-
-=> dfu 0 mmc 0
-
-Flash SPL and u-boot.img into the eMMC running the following commands on a PC:
-
-$ sudo dfu-util -D SPL -a spl
-
-$ sudo dfu-util -D u-boot.img -a u-boot
-
-Remove power from the pico board.
-
-Put pico board into normal boot mode.
-
-Power up the board and the new updated U-Boot should boot from eMMC.
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c
deleted file mode 100644
index 53e14693a53..00000000000
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 NXP Semiconductors
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx7-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <usb.h>
-#include <power/pmic.h>
-#include <power/pfuze3000_pmic.h>
-#include "../../freescale/common/pfuze.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
- PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-
-#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C4 for PMIC */
-static struct i2c_pads_info i2c_pad_info4 = {
- .scl = {
- .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
- .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
- .gp = IMX_GPIO_NR(6, 16),
- },
- .sda = {
- .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
- .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
- .gp = IMX_GPIO_NR(6, 17),
- },
-};
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-#ifdef CONFIG_POWER
-#define I2C_PMIC 3
-int power_init_board(void)
-{
- struct pmic *p;
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE3000");
- ret = pmic_probe(p);
- if (ret)
- return ret;
-
- pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
-
- /* disable Low Power Mode during standby mode */
- pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
- reg |= 0x1;
- pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
-
- /* SW1A/1B mode set to APS/APS */
- reg = 0x8;
- pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
- pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
-
- /* SW1A/1B standby voltage set to 1.025V */
- reg = 0xd;
- pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
- pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
-
- /* decrease SW1B normal voltage to 0.975V */
- pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
- reg &= ~0x1f;
- reg |= PFUZE3000_SW1AB_SETP(975);
- pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
-
- return 0;
-}
-#endif
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart5_pads[] = {
- MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
- MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
- gpio_direction_output(FEC1_RST_GPIO, 0);
- udelay(500);
- gpio_set_value(FEC1_RST_GPIO, 1);
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return fecmxc_initialize_multi(bis, 0,
- CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-}
-
-static int setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
- = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
- clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
- (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
- IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
-
- return set_clk_enet(ENET_125MHZ);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe7;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* Assume uSDHC3 emmc is always present */
- return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
-#endif
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_FEC_MXC
- setup_fec();
-#endif
-
- return 0;
-}
-
-int board_late_init(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- /*
- * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
- * since we use PMIC_PWRON to reset the board.
- */
- clrsetbits_le16(&wdog->wcr, 0, 0x10);
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: i.MX7D PICOSOM\n");
-
- return 0;
-}
-
-static iomux_v3_cfg_t const usb_otg2_pads[] = {
- MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
- ARRAY_SIZE(usb_otg2_pads));
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
- switch (port) {
- case 0:
- return USB_INIT_DEVICE;
- case 1:
- return USB_INIT_HOST;
- default:
- return -EINVAL;
- }
- return 0;
-}
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
deleted file mode 100644
index 8c3443875de..00000000000
--- a/board/technexion/pico-imx7d/spl.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Technexion Ltd.
- *
- * Author: Richard Hu <richard.hu@technexion.com>
- */
-
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch-mx7/mx7-ddr.h>
-#include <asm/gpio.h>
-#include <spl.h>
-
-#if defined(CONFIG_SPL_BUILD)
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- return 0;
-}
-#endif
-
-static struct ddrc ddrc_regs_val = {
- .mstr = 0x01040001,
- .rfshtmg = 0x00400046,
- .init1 = 0x00690000,
- .init0 = 0x00020083,
- .init3 = 0x09300004,
- .init4 = 0x04080000,
- .init5 = 0x00100004,
- .rankctl = 0x0000033F,
- .dramtmg0 = 0x09081109,
- .dramtmg1 = 0x0007020d,
- .dramtmg2 = 0x03040407,
- .dramtmg3 = 0x00002006,
- .dramtmg4 = 0x04020205,
- .dramtmg5 = 0x03030202,
- .dramtmg8 = 0x00000803,
- .zqctl0 = 0x00800020,
- .dfitmg0 = 0x02098204,
- .dfitmg1 = 0x00030303,
- .dfiupd0 = 0x80400003,
- .dfiupd1 = 0x00100020,
- .dfiupd2 = 0x80100004,
- .addrmap4 = 0x00000F0F,
- .odtcfg = 0x06000604,
- .odtmap = 0x00000001,
- .rfshtmg = 0x00400046,
- .dramtmg0 = 0x09081109,
- .addrmap0 = 0x0000001f,
- .addrmap1 = 0x00080808,
- .addrmap4 = 0x00000f0f,
- .addrmap5 = 0x07070707,
- .addrmap6 = 0x0f0f0707,
-};
-
-static struct ddrc_mp ddrc_mp_val = {
- .pctrl_0 = 0x00000001,
-};
-
-static struct ddr_phy ddr_phy_regs_val = {
- .phy_con0 = 0x17420f40,
- .phy_con1 = 0x10210100,
- .phy_con4 = 0x00060807,
- .mdll_con0 = 0x1010007e,
- .drvds_con0 = 0x00000d6e,
- .cmd_sdll_con0 = 0x00000010,
- .offset_lp_con0 = 0x0000000f,
- .offset_rd_con0 = 0x08080808,
- .offset_wr_con0 = 0x08080808,
-};
-
-static struct mx7_calibration calib_param = {
- .num_val = 5,
- .values = {
- 0x0E407304,
- 0x0E447304,
- 0x0E447306,
- 0x0E447304,
- 0x0E447304,
- },
-};
-
-static void gpr_init(void)
-{
- struct iomuxc_gpr_base_regs *gpr_regs =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
- writel(0x4F400005, &gpr_regs->gpr[1]);
-}
-
-static bool is_1g(void)
-{
- gpio_direction_input(IMX_GPIO_NR(1, 12));
- return !gpio_get_value(IMX_GPIO_NR(1, 12));
-}
-
-static void ddr_init(void)
-{
- if (is_1g())
- ddrc_regs_val.addrmap6 = 0x0f070707;
-
- mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
- &calib_param);
-}
-
-void board_init_f(ulong dummy)
-{
- arch_cpu_init();
- gpr_init();
- board_early_init_f();
- timer_init();
- preloader_console_init();
- ddr_init();
- memset(__bss_start, 0, __bss_end - __bss_start);
- board_init_r(NULL, 0);
-}
-
-void reset_cpu(ulong addr)
-{
-}
-#endif
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
deleted file mode 100644
index b02cae52379..00000000000
--- a/configs/pico-hobbit-imx7d_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX7=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-CONFIG_IMX_RDC=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTMENU=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MII is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_DFU_MMC=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
deleted file mode 100644
index f355f07be7e..00000000000
--- a/configs/pico-imx7d_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX7=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-CONFIG_IMX_RDC=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="ask"
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTMENU=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MII is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_DFU_MMC=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
deleted file mode 100644
index 3a182dcb810..00000000000
--- a/configs/pico-pi-imx7d_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX7=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PICO_IMX7D=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-CONFIG_IMX_RDC=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTMENU=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_MII is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_DFU_MMC=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
deleted file mode 100644
index 2bc42a04a04..00000000000
--- a/include/configs/pico-imx7d.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 NXP Semiconductors
- *
- * Configuration settings for the i.MX7D Pico board.
- */
-
-#ifndef __PICO_IMX7D_CONFIG_H
-#define __PICO_IMX7D_CONFIG_H
-
-#include "mx7_common.h"
-
-#include "imx7_spl.h"
-
-#ifdef CONFIG_SPL_OS_BOOT
-/* Falcon Mode */
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000
-
-/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
-#endif
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
-#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
-
-/* Network */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-
-#define CONFIG_PHY_ATHEROS
-
-/* ENET1 */
-#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
-
-/* MMC Config */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-#define CONFIG_DFU_ENV_SETTINGS \
- "dfu_alt_info=" \
- "spl raw 0x2 0x400;" \
- "u-boot raw 0x8a 0x400;" \
- "/boot/zImage ext4 0 1;" \
- "/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \
- "/boot/imx7d-pico-pi.dtb ext4 0 1;" \
- "rootfs part 0 1\0" \
-
-#define BOOTMENU_ENV \
- "bootmenu_0=Boot using PICO-Hobbit baseboard=" \
- "setenv fdtfile imx7d-pico-hobbit.dtb\0" \
- "bootmenu_1=Boot using PICO-Pi baseboard=" \
- "setenv fdtfile imx7d-pico-pi.dtb\0" \
-
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc4\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- BOOTMENU_ENV \
- "fdt_addr=0x83000000\0" \
- "fdt_addr_r=0x83000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_addr_r=0x83000000\0" \
- "ramdiskaddr=0x83000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- CONFIG_DFU_ENV_SETTINGS \
- "findfdt=" \
- "if test $fdtfile = ask ; then " \
- "bootmenu -1; fi;" \
- "if test $fdtfile != ask ; then " \
- "saveenv; fi;\0" \
- "finduuid=part uuid mmc 0:1 uuid\0" \
- "partitions=" \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
- "fastboot_partition_alias_system=rootfs\0" \
- "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* I2C configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
-#define CONFIG_SYS_I2C_MXC_I2C2
-#define CONFIG_SYS_I2C_MXC_I2C3
-#define CONFIG_SYS_I2C_MXC_I2C4
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
-/* FLASH and environment organization */
-#define CONFIG_ENV_SIZE SZ_8K
-
-#define CONFIG_ENV_OFFSET (8 * SZ_64K)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 0
-
-/* USB Configs */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-#define CONFIG_IMX_THERMAL
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 29/93] arm: Remove mccmon6_sd board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (27 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 28/93] arm: Remove pico-hobbit-imx7d board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 30/93] arm: Remove apalis_imx6_nospl_it board Simon Glass
` (68 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/liebherr/mccmon6/Kconfig | 12 -
board/liebherr/mccmon6/MAINTAINERS | 7 -
board/liebherr/mccmon6/Makefile | 6 -
board/liebherr/mccmon6/mccmon6.c | 489 -------------------
board/liebherr/mccmon6/mon6_imximage_nor.cfg | 8 -
board/liebherr/mccmon6/mon6_imximage_sd.cfg | 8 -
board/liebherr/mccmon6/spl.c | 298 -----------
configs/mccmon6_nor_defconfig | 50 --
configs/mccmon6_sd_defconfig | 51 --
include/configs/mccmon6.h | 293 -----------
11 files changed, 1223 deletions(-)
delete mode 100644 board/liebherr/mccmon6/Kconfig
delete mode 100644 board/liebherr/mccmon6/MAINTAINERS
delete mode 100644 board/liebherr/mccmon6/Makefile
delete mode 100644 board/liebherr/mccmon6/mccmon6.c
delete mode 100644 board/liebherr/mccmon6/mon6_imximage_nor.cfg
delete mode 100644 board/liebherr/mccmon6/mon6_imximage_sd.cfg
delete mode 100644 board/liebherr/mccmon6/spl.c
delete mode 100644 configs/mccmon6_nor_defconfig
delete mode 100644 configs/mccmon6_sd_defconfig
delete mode 100644 include/configs/mccmon6.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 7c7435b6d89..de9bf156ce2 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -551,7 +551,6 @@ source "board/grinn/liteboard/Kconfig"
source "board/phytec/pfla02/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/liebherr/display5/Kconfig"
-source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig
deleted file mode 100644
index 4cc7fc2ba2c..00000000000
--- a/board/liebherr/mccmon6/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MCCMON6
-
-config SYS_BOARD
- default "mccmon6"
-
-config SYS_VENDOR
- default "liebherr"
-
-config SYS_CONFIG_NAME
- default "mccmon6"
-
-endif
diff --git a/board/liebherr/mccmon6/MAINTAINERS b/board/liebherr/mccmon6/MAINTAINERS
deleted file mode 100644
index c9c718305f3..00000000000
--- a/board/liebherr/mccmon6/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MCCMON6 BOARD
-M: Lukasz Majewski <lukma@denx.de>
-S: Maintained
-F: board/liebherr/mccmon6/
-F: include/configs/mccmon6.h
-F: configs/mccmon6_nor_defconfig
-F: configs/mccmon6_sd_defconfig
diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile
deleted file mode 100644
index ead6750ebf9..00000000000
--- a/board/liebherr/mccmon6/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2016-2017
-# Lukasz Majewski, DENX Software Engineering, lukma at denx.de
-
-obj-y := mccmon6.o spl.o
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
deleted file mode 100644
index 946b91f3a1c..00000000000
--- a/board/liebherr/mccmon6/mccmon6.c
+++ /dev/null
@@ -1,489 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016-2017
- * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/io.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <micrel.h>
-#include <phy.h>
-#include <input.h>
-#include <i2c.h>
-#include <spl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define ETH_PHY_RESET IMX_GPIO_NR(1, 27)
-#define ECSPI3_CS0 IMX_GPIO_NR(4, 24)
-#define ECSPI3_FLWP IMX_GPIO_NR(4, 27)
-#define NOR_WP IMX_GPIO_NR(1, 1)
-#define DISPLAY_EN IMX_GPIO_NR(1, 2)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* Carrier MicroSD Card Detect */
- IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
- | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
- | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
- | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* KSZ9031 PHY Reset */
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- /* Reset KSZ9031 PHY */
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR},
- {USDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- /*
- * eMMC don't have card detect pin - since it is soldered to the
- * PCB board
- */
- ret = 1;
- break;
- }
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- u32 index = 0;
-
- /*
- * MMC MAP
- * (U-Boot device node) (Physical Port)
- * mmc0 Soldered on board eMMC device
- * mmc1 MicroSD card
- */
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 8;
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[1].max_bus_width = 4;
- gpio_direction_input(USDHC2_CD_GPIO);
- break;
- default:
- printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static iomux_v3_cfg_t const eimnor_pads[] = {
- IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eimnor_cs_setup(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
-
- /* NOR configuration */
- writel(0x00620181, &weim_regs->cs0gcr1);
- writel(0x00000001, &weim_regs->cs0gcr2);
- writel(0x0b020000, &weim_regs->cs0rcr1);
- writel(0x0000b000, &weim_regs->cs0rcr2);
- writel(0x0804a240, &weim_regs->cs0wcr1);
- writel(0x00000000, &weim_regs->cs0wcr2);
-
- writel(0x00000120, &weim_regs->wcr);
- writel(0x00000010, &weim_regs->wiar);
- writel(0x00000000, &weim_regs->ear);
-
- set_chipselect_size(CS0_128);
-}
-
-static void setup_eimnor(void)
-{
- SETUP_IOMUX_PADS(eimnor_pads);
- gpio_direction_output(NOR_WP, 1);
-
- enable_eim_clk(1);
- eimnor_cs_setup();
-}
-
-/* mccmon6 board has SPI Flash is connected to SPI3 */
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
-}
-
-static iomux_v3_cfg_t const ecspi3_pads[] = {
- /* SPI3 */
- IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-};
-
-void setup_spi(void)
-{
- SETUP_IOMUX_PADS(ecspi3_pads);
-
- enable_spi_clk(true, 2);
-
- /* set cs0 to high */
- gpio_direction_output(ECSPI3_CS0, 1);
-
- /* set flwp to high */
- gpio_direction_output(ECSPI3_FLWP, 1);
-}
-
-struct i2c_pads_info mx6q_i2c1_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-struct i2c_pads_info mx6q_i2c2_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- gpio_direction_output(DISPLAY_EN, 1);
-
- setup_eimnor();
- setup_spi();
-
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
-
- return 0;
-}
-
-int board_late_init(void)
-{
- env_set("board_name", "mccmon6");
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: MCCMON6\n");
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- /*
- * Default setting for GMII Clock Pad Skew Register 0x1EF:
- * MMD Address 0x2h, Register 0x8h
- *
- * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
- * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
- *
- * Adjustment -> write 0x3FF:
- * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
- * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
- *
- */
- ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
-
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
-
- ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x3333);
-
- ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x2052);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void)
-{
- setup_eimnor();
-
- gpio_direction_output(DISPLAY_EN, 1);
-}
-#endif /* CONFIG_SPL_BOARD_INIT */
-
-#ifdef CONFIG_SPL_BUILD
-void board_boot_order(u32 *spl_boot_list)
-{
- switch (spl_boot_device()) {
- case BOOT_DEVICE_MMC2:
- case BOOT_DEVICE_MMC1:
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
- break;
-
- case BOOT_DEVICE_NOR:
- spl_boot_list[0] = BOOT_DEVICE_NOR;
- break;
- }
-}
-#endif /* CONFIG_SPL_BUILD */
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- char s[16];
- int ret;
- /*
- * We use BOOT_DEVICE_MMC1, but SD card is connected
- * to MMC2
- *
- * Correct "mapping" is delivered in board defined
- * board_boot_order() function.
- *
- * SD card boot is regarded as a "development" one,
- * hence we _always_ go through the u-boot.
- *
- */
- if (spl_boot_device() == BOOT_DEVICE_MMC1)
- return 1;
-
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- env_init();
- ret = env_get_f("boot_os", s, sizeof(s));
- if ((ret != -1) && (strcmp(s, "no") == 0))
- return 1;
-
- /*
- * Check if SWUpdate recovery needs to be started
- *
- * recovery_status = NULL (not set - ret == -1) -> normal operation
- *
- * recovery_status = progress or
- * recovery_status = failed or
- * recovery_status = <any value> -> start SWUpdate
- *
- */
- ret = env_get_f("recovery_status", s, sizeof(s));
- if (ret != -1)
- return 1;
-
- return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
diff --git a/board/liebherr/mccmon6/mon6_imximage_nor.cfg b/board/liebherr/mccmon6/mon6_imximage_nor.cfg
deleted file mode 100644
index 6f966a7dd75..00000000000
--- a/board/liebherr/mccmon6/mon6_imximage_nor.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016-2017
- * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
- */
-
-IMAGE_VERSION 2
-BOOT_FROM nor
diff --git a/board/liebherr/mccmon6/mon6_imximage_sd.cfg b/board/liebherr/mccmon6/mon6_imximage_sd.cfg
deleted file mode 100644
index 5a65e0f54ca..00000000000
--- a/board/liebherr/mccmon6/mon6_imximage_sd.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016-2017
- * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
- */
-
-IMAGE_VERSION 2
-BOOT_FROM sd
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
deleted file mode 100644
index acfc4902c11..00000000000
--- a/board/liebherr/mccmon6/spl.c
+++ /dev/null
@@ -1,298 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Wandboard
- * Author: Tungyi Lin <tungyilin1127@gmail.com>
- * Richard Hu <hakahu@gmail.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-
-#if defined(CONFIG_SPL_BUILD)
-#include <asm/arch/mx6-ddr.h>
-/*
- * Driving strength:
- * 0x30 == 40 Ohm
- * 0x28 == 48 Ohm
- */
-
-#define IMX6DQ_DRIVE_STRENGTH 0x30
-#define IMX6SDL_DRIVE_STRENGTH 0x28
-
-/* configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
- .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_cas = IMX6DQ_DRIVE_STRENGTH,
- .dram_ras = IMX6DQ_DRIVE_STRENGTH,
- .dram_reset = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
-};
-
-/* configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* H5T04G63AFR-PB */
-static struct mx6_ddr3_cfg h5t04g63afr = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* H5TQ2G63DFR-H9 */
-static struct mx6_ddr3_cfg h5tq2g63dfr = {
- .mem_speed = 1333,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1350,
- .trcmin = 4950,
- .trasmin = 3600,
-};
-
-static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001f001f,
- .p0_mpwldectrl1 = 0x001f001f,
- .p1_mpwldectrl0 = 0x001f001f,
- .p1_mpwldectrl1 = 0x001f001f,
- .p0_mpdgctrl0 = 0x4301030d,
- .p0_mpdgctrl1 = 0x03020277,
- .p1_mpdgctrl0 = 0x4300030a,
- .p1_mpdgctrl1 = 0x02780248,
- .p0_mprddlctl = 0x4536393b,
- .p1_mprddlctl = 0x36353441,
- .p0_mpwrdlctl = 0x41414743,
- .p1_mpwrdlctl = 0x462f453f,
-};
-
-/* DDR 64bit 2GB */
-static struct mx6_ddr_sysinfo mem_q = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
-};
-
-static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001f001f,
- .p0_mpwldectrl1 = 0x001f001f,
- .p1_mpwldectrl0 = 0x001f001f,
- .p1_mpwldectrl1 = 0x001f001f,
- .p0_mpdgctrl0 = 0x420e020e,
- .p0_mpdgctrl1 = 0x02000200,
- .p1_mpdgctrl0 = 0x42020202,
- .p1_mpdgctrl1 = 0x01720172,
- .p0_mprddlctl = 0x494c4f4c,
- .p1_mprddlctl = 0x4a4c4c49,
- .p0_mpwrdlctl = 0x3f3f3133,
- .p1_mpwrdlctl = 0x39373f2e,
-};
-
-static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0040003c,
- .p0_mpwldectrl1 = 0x0032003e,
- .p0_mpdgctrl0 = 0x42350231,
- .p0_mpdgctrl1 = 0x021a0218,
- .p0_mprddlctl = 0x4b4b4e49,
- .p0_mpwrdlctl = 0x3f3f3035,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_dl = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
-};
-
-/* DDR 32bit 512MB */
-static struct mx6_ddr_sysinfo mem_s = {
- .dsize = 1,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
- if (is_cpu_type(MXC_CPU_MX6SOLO)) {
- mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
- } else if (is_cpu_type(MXC_CPU_MX6DL)) {
- mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
- } else if (is_cpu_type(MXC_CPU_MX6Q)) {
- mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
- mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
- }
-
- udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- gpr_init();
-
- /* iomux */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
-#endif
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
deleted file mode 100644
index 69fab7c7794..00000000000
--- a/configs/mccmon6_nor_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MCCMON6=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor),128k at 0x1980000(kernel-dtb.nor),128k at 0x19C0000(swupdate-kernel-dtb.nor)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_DEVICE=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
deleted file mode 100644
index 05c6572beb3..00000000000
--- a/configs/mccmon6_sd_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MCCMON6=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m at 0x0(mccmon6-image.nor),256k at 0x40000(u-boot-env.nor),1m at 0x80000(u-boot.nor),8m at 0x180000(kernel.nor),8m at 0x980000(swupdate-kernel.nor),8m at 0x1180000(swupdate-rootfs.nor),128k at 0x1980000(kernel-dtb.nor),128k at 0x19C0000(swupdate-kernel-dtb.nor)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_DEVICE=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
deleted file mode 100644
index 644f3399938..00000000000
--- a/include/configs/mccmon6.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016-2017
- * Lukasz Majewski, DENX Software Engineering, lukma at denx.de
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#include "imx6_spl.h"
-
-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
-#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
-
-/*
- * Below defines are set but NOT really used since we by
- * design force U-Boot run when we boot in development
- * mode from SD card (SD2)
- */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-
-#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* MMC Configuration */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-/* NOR 16-bit mode */
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_FLASH_VERIFY
-
-/* NOR Flash MTD */
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
-
-/* MTD support */
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200 quiet\0" \
- "fdtfile=imx6q-mccmon6.dtb\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "boot_os=yes\0" \
- "download_kernel=" \
- "tftpboot ${kernel_addr} ${kernel_file};" \
- "tftpboot ${fdt_addr} ${fdtfile};\0" \
- "get_boot_medium=" \
- "setenv boot_medium nor;" \
- "setexpr.l _src_sbmr1 *0x020d8004;" \
- "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \
- "if test ${_b_medium} = 40; then " \
- "setenv boot_medium sdcard;" \
- "fi\0" \
- "kernel_file=uImage\0" \
- "load_kernel=" \
- "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
- "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
- "boot_sd=" \
- "echo '#######################';" \
- "echo '# Factory SDcard Boot #';" \
- "echo '#######################';" \
- "setenv mmcdev 1;" \
- "setenv mmcfactorydev 0;" \
- "setenv mmcfactorypart 1;" \
- "run factory_flash_img;\0" \
- "boot_nor=" \
- "setenv kernelnor 0x08180000;" \
- "setenv dtbnor 0x09980000;" \
- "setenv bootargs console=${console} " \
- CONFIG_MTDPARTS_DEFAULT " " \
- "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
- "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
- "bootm ${kernelnor} - ${dtbloadaddr};\0" \
- "boot_recovery=" \
- "echo '#######################';" \
- "echo '# RECOVERY SWU Boot #';" \
- "echo '#######################';" \
- "setenv rootfsloadaddr 0x13000000;" \
- "setenv swukernelnor 0x08980000;" \
- "setenv swurootfsnor 0x09180000;" \
- "setenv swudtbnor 0x099A0000;" \
- "setenv bootargs console=${console} " \
- CONFIG_MTDPARTS_DEFAULT " " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}::off root=/dev/ram rw;" \
- "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
- "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
- "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
- "boot_tftp=" \
- "echo '#######################';" \
- "echo '# TFTP Boot #';" \
- "echo '#######################';" \
- "if run download_kernel; then " \
- "setenv bootargs console=${console} " \
- "root=/dev/mmcblk0p2 rootwait;" \
- "bootm ${kernel_addr} - ${fdt_addr};" \
- "fi\0" \
- "bootcmd=" \
- "if test -n ${recovery_status}; then " \
- "run boot_recovery;" \
- "else " \
- "if test ! -n ${boot_medium}; then " \
- "run get_boot_medium;" \
- "if test ${boot_medium} = sdcard; then " \
- "run boot_sd;" \
- "else " \
- "run boot_nor;" \
- "fi;" \
- "else " \
- "if test ${boot_medium} = tftp; then " \
- "run boot_tftp;" \
- "fi;" \
- "fi;" \
- "fi\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "fdt_addr=0x18000000\0" \
- "bootdev=1\0" \
- "bootpart=1\0" \
- "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
- "netdev=eth0\0" \
- "load_addr=0x11000000\0" \
- "dtbloadaddr=0x12000000\0" \
- "uboot_file=u-boot.img\0" \
- "SPL_file=SPL\0" \
- "load_uboot=tftp ${load_addr} ${uboot_file}\0" \
- "nor_img_addr=0x11000000\0" \
- "nor_img_file=core-image-lwn-mccmon6.nor\0" \
- "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
- "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
- "nor_img_size=0x02000000\0" \
- "factory_script_file=factory.scr\0" \
- "factory_load_script=" \
- "if test -e mmc ${mmcdev}:${mmcfactorypart} " \
- "${factory_script_file}; then " \
- "load mmc ${mmcdev}:${mmcfactorypart} " \
- "${loadaddr} ${factory_script_file};" \
- "fi\0" \
- "factory_script=echo Running factory script from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "factory_flash_img="\
- "echo 'Flash mccmon6 with factory images'; " \
- "if run factory_load_script; then " \
- "run factory_script;" \
- "else " \
- "echo No factory script: ${factory_script_file} found on " \
- "device ${mmcdev};" \
- "run factory_nor_img;" \
- "run factory_eMMC_img;" \
- "fi\0" \
- "factory_eMMC_img="\
- "echo 'Update mccmon6 eMMC image'; " \
- "if load mmc ${mmcdev}:${mmcfactorypart} " \
- "${loadaddr} ${emmc_img_file}; then " \
- "setexpr fw_sz ${filesize} / 0x200;" \
- "setexpr fw_sz ${fw_sz} + 1;" \
- "mmc dev ${mmcfactorydev};" \
- "mmc write ${loadaddr} 0x0 ${fw_sz};" \
- "fi\0" \
- "factory_nor_img="\
- "echo 'Update mccmon6 NOR image'; " \
- "if load mmc ${mmcdev}:${mmcfactorypart} " \
- "${nor_img_addr} ${nor_img_file}; then " \
- "run nor_update;" \
- "fi\0" \
- "nor_update=" \
- "protect off ${nor_bank_start} +${nor_img_size};" \
- "erase ${nor_bank_start} +${nor_img_size};" \
- "setexpr nor_img_size ${nor_img_size} / 4; " \
- "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
- "tftp_nor_uboot="\
- "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
- "setenv nor_img_file u-boot.img; " \
- "setenv nor_img_size 0x80000; " \
- "setenv nor_bank_start 0x08080000; " \
- "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
- "run nor_update;" \
- "fi\0" \
- "tftp_nor_uImg="\
- "echo 'Update mccmon6 NOR uImage via TFTP'; " \
- "setenv nor_img_file uImage; " \
- "setenv nor_img_size 0x500000; " \
- "setenv nor_bank_start 0x08180000; " \
- "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
- "run nor_update;" \
- "fi\0" \
- "tftp_nor_dtb="\
- "echo 'Update mccmon6 NOR DTB via TFTP'; " \
- "setenv nor_img_file imx6q-mccmon6.dtb; " \
- "setenv nor_img_size 0x20000; " \
- "setenv nor_bank_start 0x09980000; " \
- "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
- "run nor_update;" \
- "fi\0" \
- "tftp_nor_img="\
- "echo 'Update mccmon6 NOR image via TFTP'; " \
- "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
- "run nor_update;" \
- "fi\0" \
- "tftp_nor_SPL="\
- "if tftp ${load_addr} SPL_padded; then " \
- "erase 0x08000000 +0x20000;" \
- "cp.b ${load_addr} 0x08000000 0x20000;" \
- "fi;\0" \
- "tftp_sd_SPL="\
- "if mmc dev 1; then " \
- "if tftp ${load_addr} ${SPL_file}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${load_addr} 0x2 ${fw_sz};" \
- "fi;" \
- "fi;\0" \
- "tftp_sd_uboot="\
- "if mmc dev 1; then " \
- "if run load_uboot; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${load_addr} 0x8A ${fw_sz};" \
- "fi;" \
- "fi;\0"
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (SZ_128K)
-
-/* Envs are stored in NOR flash */
-#define CONFIG_ENV_SECT_SIZE (SZ_128K)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#endif /* __CONFIG_H * */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 30/93] arm: Remove apalis_imx6_nospl_it board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (28 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 29/93] arm: Remove mccmon6_sd board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 21:33 ` Marek Vasut
2018-11-19 15:53 ` [U-Boot] [PATCH 31/93] arm: Remove wandboard board Simon Glass
` (67 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
.../toradex/apalis_imx6/1066mhz_4x128mx16.cfg | 47 -
.../toradex/apalis_imx6/1066mhz_4x256mx16.cfg | 47 -
board/toradex/apalis_imx6/Kconfig | 55 -
board/toradex/apalis_imx6/MAINTAINERS | 9 -
board/toradex/apalis_imx6/Makefile | 5 -
board/toradex/apalis_imx6/apalis_imx6.c | 1236 -----------------
board/toradex/apalis_imx6/apalis_imx6q.cfg | 33 -
board/toradex/apalis_imx6/clocks.cfg | 41 -
board/toradex/apalis_imx6/ddr-setup.cfg | 96 --
board/toradex/apalis_imx6/do_fuse.c | 97 --
board/toradex/apalis_imx6/pf0100.c | 230 ---
board/toradex/apalis_imx6/pf0100.h | 52 -
board/toradex/apalis_imx6/pf0100_otp.inc | 190 ---
configs/apalis_imx6_defconfig | 75 -
configs/apalis_imx6_nospl_com_defconfig | 63 -
configs/apalis_imx6_nospl_it_defconfig | 63 -
include/configs/apalis_imx6.h | 277 ----
18 files changed, 2617 deletions(-)
delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
delete mode 100644 board/toradex/apalis_imx6/Kconfig
delete mode 100644 board/toradex/apalis_imx6/MAINTAINERS
delete mode 100644 board/toradex/apalis_imx6/Makefile
delete mode 100644 board/toradex/apalis_imx6/apalis_imx6.c
delete mode 100644 board/toradex/apalis_imx6/apalis_imx6q.cfg
delete mode 100644 board/toradex/apalis_imx6/clocks.cfg
delete mode 100644 board/toradex/apalis_imx6/ddr-setup.cfg
delete mode 100644 board/toradex/apalis_imx6/do_fuse.c
delete mode 100644 board/toradex/apalis_imx6/pf0100.c
delete mode 100644 board/toradex/apalis_imx6/pf0100.h
delete mode 100644 board/toradex/apalis_imx6/pf0100_otp.inc
delete mode 100644 configs/apalis_imx6_defconfig
delete mode 100644 configs/apalis_imx6_nospl_com_defconfig
delete mode 100644 configs/apalis_imx6_nospl_it_defconfig
delete mode 100644 include/configs/apalis_imx6.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index de9bf156ce2..0cfb565dd70 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -556,7 +556,6 @@ source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tqc/tqma6/Kconfig"
-source "board/toradex/apalis_imx6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
source "board/k+p/kp_imx6q_tpc/Kconfig"
source "board/udoo/Kconfig"
diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
deleted file mode 100644
index 29d1c3126c5..00000000000
--- a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
deleted file mode 100644
index 02e90dd5e65..00000000000
--- a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig
deleted file mode 100644
index 14f8c10c64c..00000000000
--- a/board/toradex/apalis_imx6/Kconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-if TARGET_APALIS_IMX6
-
-config SYS_BOARD
- default "apalis_imx6"
-
-config SYS_CONFIG_NAME
- default "apalis_imx6"
-
-config SYS_CPU
- default "armv7"
-
-config SYS_SOC
- default "mx6"
-
-config SYS_VENDOR
- default "toradex"
-
-config TDX_CFG_BLOCK
- default y
-
-config TDX_HAVE_MMC
- default y
-
-config TDX_CFG_BLOCK_DEV
- default "0"
-
-config TDX_CFG_BLOCK_PART
- default "1"
-
-# Toradex config block in eMMC, at the end of 1st "boot sector"
-config TDX_CFG_BLOCK_OFFSET
- default "-512"
-
-config TDX_CMD_IMX_MFGR
- bool "Enable factory testing commands for Toradex iMX 6 modules"
- help
- This adds the commands
- pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
- If executed on already fused modules it doesn't change any fuse setting.
- default y
-
-config TDX_APALIS_IMX6_V1_0
- bool "Apalis iMX6 V1.0 HW"
- help
- Apalis iMX6 V1.0 HW has a different pinout for the UART.
- The UARTs must be used in DCE mode, RTS/CTS are swapped and
- thus unusable on standard carrier boards.
- This option configures DCE mode unconditionally. Whithout this
- option the config block stating V1.0 HW selects DCE mode,
- otherwise the UARTs are configuered in DTE mode.
- default n
-
-source "board/toradex/common/Kconfig"
-
-endif
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
deleted file mode 100644
index 2c70ab4fbd9..00000000000
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-Apalis iMX6
-M: Max Krummenacher <max.krummenacher@toradex.com>
-W: http://developer.toradex.com/software/linux/linux-software
-S: Maintained
-F: board/toradex/apalis_imx6/
-F: include/configs/apalis_imx6.h
-F: configs/apalis_imx6_defconfig
-F: configs/apalis_imx6_nospl_com_defconfig
-F: configs/apalis_imx6_nospl_it_defconfig
diff --git a/board/toradex/apalis_imx6/Makefile b/board/toradex/apalis_imx6/Makefile
deleted file mode 100644
index 128f1794d16..00000000000
--- a/board/toradex/apalis_imx6/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2012-2014 Toradex, Inc.
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := apalis_imx6.o do_fuse.o
-obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
deleted file mode 100644
index 368db9c488c..00000000000
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ /dev/null
@@ -1,1236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
- * copied from nitrogen6x
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/bootm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <input.h>
-#include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-#include "../common/tdx-cfg-block.h"
-#ifdef CONFIG_TDX_CMD_IMX_MFGR
-#include "pf0100.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
-
-#define NO_PULLUP ( \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
-
-#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
-
-#define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
-
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
- /* use the DDR controllers configured size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- (ulong)imx_ddr_size());
-
- return 0;
-}
-
-/* Apalis UART1 */
-iomux_v3_cfg_t const uart1_pads_dce[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-iomux_v3_cfg_t const uart1_pads_dte[] = {
- MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Apalis I2C1 */
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-/* Apalis local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-/* Apalis I2C3 / CAM */
-struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
- .gp = IMX_GPIO_NR(3, 17)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-
-/* Apalis I2C2 / DDC */
-struct i2c_pads_info i2c_pad_info_ddc = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
- .gp = IMX_GPIO_NR(3, 16)
- }
-};
-
-/* Apalis MMC1 */
-iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-# define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
-};
-
-/* Apalis SD1 */
-iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-# define GPIO_SD_CD IMX_GPIO_NR(6, 14)
-};
-
-/* eMMC */
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
-};
-
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- /* control data pad skew - devaddr = 0x02, register = 0x04 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* rx data pad skew - devaddr = 0x02, register = 0x05 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* tx data pad skew - devaddr = 0x02, register = 0x05 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
- return 0;
-}
-
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* KSZ9031 PHY Reset */
- MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
-};
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static int reset_enet_phy(struct mii_dev *bus)
-{
- /* Reset KSZ9031 PHY */
- gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(GPIO_ENET_PHY_RESET, 1);
-
- return 0;
-}
-
-/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
-iomux_v3_cfg_t const gpio_pads[] = {
- /* Apalis GPIO1 - GPIO8 */
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN),
- MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP),
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP),
-};
-
-static void setup_iomux_gpio(void)
-{
- imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
-}
-
-iomux_v3_cfg_t const usb_pads[] = {
- /* USBH_EN */
- MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
- /* USB_VBUS_DET */
- MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
- /* USBO1_ID */
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
- /* USBO1_EN */
- MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
-};
-
-/*
- * UARTs are used in DTE mode, switch the mode on all UARTs before
- * any pinmuxing connects a (DCE) output to a transceiver output.
- */
-#define UFCR 0x90 /* FIFO Control Register */
-#define UFCR_DCEDTE (1<<6) /* DCE=0 */
-
-static void setup_dtemode_uart(void)
-{
- setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
- setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
- setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
- setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
-}
-static void setup_dcemode_uart(void)
-{
- clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
- clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
- clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
- clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
-}
-
-static void setup_iomux_dte_uart(void)
-{
- setup_dtemode_uart();
- imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
- ARRAY_SIZE(uart1_pads_dte));
-}
-
-static void setup_iomux_dce_uart(void)
-{
- setup_dcemode_uart();
- imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
- ARRAY_SIZE(uart1_pads_dce));
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
-{
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- /* control OTG power */
- gpio_direction_output(GPIO_USBO_EN, on);
- mdelay(100);
- break;
- case 1:
- /* Control MXM USBH */
- gpio_direction_output(GPIO_USBH_EN, on);
- mdelay(2);
- /* Control onboard USB Hub VBUS */
- gpio_direction_output(GPIO_USB_VBUS_DET, on);
- mdelay(100);
- break;
- default:
- break;
- }
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-/* use the following sequence: eMMC, MMC, SD */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
- {USDHC3_BASE_ADDR},
- {USDHC1_BASE_ADDR},
- {USDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = true; /* default: assume inserted */
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- gpio_direction_input(GPIO_MMC_CD);
- ret = !gpio_get_value(GPIO_MMC_CD);
- break;
- case USDHC2_BASE_ADDR:
- gpio_direction_input(GPIO_SD_CD);
- ret = !gpio_get_value(GPIO_SD_CD);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- s32 status = 0;
- u32 index = 0;
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- usdhc_cfg[0].max_bus_width = 8;
- usdhc_cfg[1].max_bus_width = 8;
- usdhc_cfg[2].max_bus_width = 4;
-
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- break;
- default:
- printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
- }
-
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- }
-
- return status;
-#else
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x2 SD2
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- default:
- puts("MMC boot device not available");
- }
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-#endif
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return 0;
- bus->reset = reset_enet_phy;
- /* scan PHY 4,5,6,7 */
- phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- free(bus);
- puts("no PHY found\n");
- return 0;
- }
- printf("using PHY@%d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- free(phydev);
- free(bus);
- }
-#endif
- return 0;
-}
-
-static iomux_v3_cfg_t const pwr_intb_pads[] = {
- /*
- * the bootrom sets the iomux to vselect, potentially connecting
- * two outputs. Set this back to GPIO
- */
- MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static iomux_v3_cfg_t const backlight_pads[] = {
- /* Backlight on RGB connector: J15 */
- MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
- /* additional CPU pin on BKL_PWM, keep in tristate */
- MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
- /* Backlight PWM, used as GPIO in U-Boot */
- MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
- /* buffer output enable 0: buffer enabled */
- MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
-#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
- /* PSAVE# integrated VDAC */
- MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
-};
-
-static iomux_v3_cfg_t const rgb_pads[] = {
- MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
- MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
-};
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-static int detect_i2c(struct display_info_t const *dev)
-{
- return (0 == i2c_set_bus_num(dev->bus)) &&
- (0 == i2c_probe(dev->addr));
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
- writel(reg, &iomux->gpr[2]);
- gpio_direction_output(RGB_BACKLIGHT_GP, 1);
- gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
- gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
-}
-
-static void enable_rgb(struct display_info_t const *dev)
-{
- imx_iomux_v3_setup_multiple_pads(
- rgb_pads,
- ARRAY_SIZE(rgb_pads));
- gpio_direction_output(RGB_BACKLIGHT_GP, 1);
- gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
- gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
-}
-
-static int detect_default(struct display_info_t const *dev)
-{
- (void) dev;
- return 1;
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .di = 1,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_default,
- .enable = enable_rgb,
- .mode = {
- .name = "vga-rgb",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 33000,
- .left_margin = 48,
- .right_margin = 16,
- .upper_margin = 31,
- .lower_margin = 11,
- .hsync_len = 96,
- .vsync_len = 2,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .di = 1,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .enable = enable_rgb,
- .mode = {
- .name = "wvga-rgb",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 25000,
- .left_margin = 40,
- .right_margin = 88,
- .upper_margin = 33,
- .lower_margin = 10,
- .hsync_len = 128,
- .vsync_len = 2,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
- .enable = enable_lvds,
- .mode = {
- .name = "wsvga-lvds",
- .refresh = 60,
- .xres = 1024,
- .yres = 600,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
- imx_setup_hdmi();
- /* Turn on LDB0,IPU,IPU DI0 clocks */
- reg = __raw_readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* set LDB0, LDB1 clk select to 011/011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
- |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
- |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
- |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-
- /* backlight unconditionally on for now */
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
- /* use 0 for EDT 7", use 1 for LG fullHD panel */
- gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
- gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
- gpio_direction_output(RGB_BACKLIGHT_GP, 1);
-}
-#endif /* defined(CONFIG_VIDEO_IPUV3) */
-
-int board_early_init_f(void)
-{
- imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
- ARRAY_SIZE(pwr_intb_pads));
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
- setup_iomux_dte_uart();
-#else
- setup_iomux_dce_uart();
-#endif
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
-#endif
-
-#ifdef CONFIG_TDX_CMD_IMX_MFGR
- (void) pmic_init();
-#endif
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
-
- setup_iomux_gpio();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#if defined(CONFIG_REVISION_TAG) && \
- defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
- char env_str[256];
- u32 rev;
-
- rev = get_board_rev();
- snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
- env_set("board_rev", env_str);
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
- if ((rev & 0xfff0) == 0x0100) {
- char *fdt_env;
-
- /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
- setup_iomux_dce_uart();
-
- /* if using the default device tree, use version for V1.0 HW */
- fdt_env = env_get("fdt_file");
- if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
- env_set("fdt_file", FDT_FILE_V1_0);
- printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
-#ifndef CONFIG_ENV_IS_NOWHERE
- env_save();
-#endif
- }
- }
-#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
-#endif /* CONFIG_REVISION_TAG */
-
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
- return 0;
-}
-#endif
-
-int checkboard(void)
-{
- char it[] = " IT";
- int minc, maxc;
-
- switch (get_cpu_temp_grade(&minc, &maxc)) {
- case TEMP_AUTOMOTIVE:
- case TEMP_INDUSTRIAL:
- break;
- case TEMP_EXTCOMMERCIAL:
- default:
- it[0] = 0;
- };
- printf("Model: Toradex Apalis iMX6 %s %s%s\n",
- is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
- (gd->ram_size == 0x80000000) ? "2GB" :
- (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- return ft_common_board_setup(blob, bd);
-}
-#endif
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4-bit bus width */
- {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_LDO_BYPASS_CHECK
-/* TODO, use external pmic, for now always ldo_enable */
-void ldo_mode_set(int ldo_bypass)
-{
- return;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#include <linux/libfdt.h>
-#include "asm/arch/mx6q-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-static int mx6_com_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x128mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x555A7954,
-MX6_MMDC_P0_MDCFG1, 0xDB328F64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x005A1023,
-MX6_MMDC_P0_MDOTC, 0x09555050,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000027,
-MX6_MMDC_P0_MDCTL, 0x831A0000,
-MX6_MMDC_P0_MDSCR, 0x04088032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00428031,
-MX6_MMDC_P0_MDSCR, 0x19308030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00005800,
-MX6_MMDC_P0_MPODTCTRL, 0x00000000,
-MX6_MMDC_P1_MPODTCTRL, 0x00000000,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
-MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
-MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
-MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
-MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-static int mx6_it_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x256mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x898E78f5,
-MX6_MMDC_P0_MDCFG1, 0xff328f64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x008E1023,
-MX6_MMDC_P0_MDOTC, 0x09444040,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000047,
-MX6_MMDC_P0_MDCTL, 0x841A0000,
-MX6_MMDC_P0_MDSCR, 0x02888032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00048031,
-MX6_MMDC_P0_MDSCR, 0x19408030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00007800,
-MX6_MMDC_P0_MPODTCTRL, 0x00022227,
-MX6_MMDC_P1_MPODTCTRL, 0x00022227,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
-MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
-MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
-MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
-MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFFFF3, &ccm->CCGR2);
- writel(0x3FF0300F, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000F3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
- writel(0x000000FB, &ccm->ccosr);
-}
-
-static void ddr_init(int *table, int size)
-{
- int i;
-
- for (i = 0; i < size / 2 ; i++)
- writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
- int minc, maxc;
-
- switch (get_cpu_temp_grade(&minc, &maxc)) {
- case TEMP_COMMERCIAL:
- case TEMP_EXTCOMMERCIAL:
- puts("Commercial temperature grade DDR3 timings.\n");
- ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
- break;
- case TEMP_INDUSTRIAL:
- case TEMP_AUTOMOTIVE:
- default:
- puts("Industrial temperature grade DDR3 timings.\n");
- ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
- break;
- };
- udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
- /* Make sure we use dte mode */
- setup_dtemode_uart();
-#endif
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-
-void reset_cpu(ulong addr)
-{
-}
-
-#endif
-
-static struct mxc_serial_platdata mxc_serial_plat = {
- .reg = (struct mxc_uart *)UART1_BASE,
- .use_dte = true,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
- .name = "serial_mxc",
- .platdata = &mxc_serial_plat,
-};
diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg
deleted file mode 100644
index 739b1b70615..00000000000
--- a/board/toradex/apalis_imx6/apalis_imx6q.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#if CONFIG_DDR_MB == 2048
-#include "1066mhz_4x256mx16.cfg"
-#else
-#include "1066mhz_4x128mx16.cfg"
-#endif
-#include "clocks.cfg"
diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4fa380..00000000000
--- a/board/toradex/apalis_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg
deleted file mode 100644
index e42e3ce4387..00000000000
--- a/board/toradex/apalis_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
- * memory bus width: 64 bits x16/x32/x64
- * MX6DL ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 64 bits x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 32 bits x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC mirroring interleaved (row/bank/col)
- */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c
deleted file mode 100644
index e6793e366a3..00000000000
--- a/board/toradex/apalis_imx6/do_fuse.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for i.MX OTP fusing during module production
-*/
-
-#include <common.h>
-#ifndef CONFIG_SPL_BUILD
-#include <console.h>
-#include <fuse.h>
-
-static int mfgr_fuse(void)
-{
- unsigned val, val6;
-
- fuse_sense(0, 5, &val);
- printf("Fuse 0, 5: %8x\n", val);
- fuse_sense(0, 6, &val6);
- printf("Fuse 0, 6: %8x\n", val6);
- fuse_sense(4, 3, &val);
- printf("Fuse 4, 3: %8x\n", val);
- fuse_sense(4, 2, &val);
- printf("Fuse 4, 2: %8x\n", val);
- if (val6 & 0x10) {
- puts("BT_FUSE_SEL already fused, will do nothing\n");
- return CMD_RET_FAILURE;
- }
- /* boot cfg */
- fuse_prog(0, 5, 0x00005072);
- /* BT_FUSE_SEL */
- fuse_prog(0, 6, 0x00000010);
- return CMD_RET_SUCCESS;
-}
-
-int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int ret;
- puts("Fusing...\n");
- ret = mfgr_fuse();
- if (ret == CMD_RET_SUCCESS)
- puts("done.\n");
- else
- puts("failed.\n");
- return ret;
-}
-
-int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned val;
- int ret;
- int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
-
- /* can be used in scripts for command availability check */
- if (argc >= 1 && !strcmp(argv[1], "-n"))
- return CMD_RET_SUCCESS;
-
- /* boot cfg */
- fuse_sense(0, 5, &val);
- printf("Fuse 0, 5: %8x\n", val);
- if (val & 0x10) {
- puts("Fast boot mode already fused, no need to fuse\n");
- return CMD_RET_SUCCESS;
- }
- if (!confirmed) {
- puts("Warning: Programming fuses is an irreversible operation!\n"
- " Updating to fast boot mode prevents easy\n"
- " downgrading to previous BSP versions.\n"
- "\nReally perform this fuse programming? <y/N>\n");
- if (!confirm_yesno())
- return CMD_RET_FAILURE;
- }
- puts("Fusing fast boot mode...\n");
- ret = fuse_prog(0, 5, 0x00005072);
- if (ret == CMD_RET_SUCCESS)
- puts("done.\n");
- else
- puts("failed.\n");
- return ret;
-}
-
-U_BOOT_CMD(
- mfgr_fuse, 1, 0, do_mfgr_fuse,
- "OTP fusing during module production",
- ""
-);
-
-U_BOOT_CMD(
- updt_fuse, 2, 0, do_updt_fuse,
- "OTP fusing during module update",
- "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
-);
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
deleted file mode 100644
index 7334e92f2ef..00000000000
--- a/board/toradex/apalis_imx6/pf0100.c
+++ /dev/null
@@ -1,230 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for Freescale PMIC PF0100
-*/
-
-#include <common.h>
-#include <i2c.h>
-#include <linux/compiler.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-
-#include "pf0100_otp.inc"
-#include "pf0100.h"
-
-/* define for PMIC register dump */
-/*#define DEBUG */
-
-/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
-static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
-};
-
-unsigned pmic_init(void)
-{
- unsigned programmed = 0;
- uchar bus = 1;
- uchar devid, revid, val;
-
- puts("PMIC: ");
- if (!((0 == i2c_set_bus_num(bus)) &&
- (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
- puts("i2c bus failed\n");
- return 0;
- }
- /* get device ident */
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
- puts("i2c pmic devid read failed\n");
- return 0;
- }
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
- puts("i2c pmic revid read failed\n");
- return 0;
- }
- printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
-
-#ifdef DEBUG
- {
- unsigned i, j;
-
- for (i = 0; i < 16; i++)
- printf("\t%x", i);
- for (j = 0; j < 0x80; ) {
- printf("\n%2x", j);
- for (i = 0; i < 16; i++) {
- i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
- printf("\t%2x", val);
- }
- j += 0x10;
- }
- printf("\nEXT Page 1");
-
- val = PFUZE100_PAGE_REGISTER_PAGE1;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
- &val, 1)) {
- puts("i2c write failed\n");
- return 0;
- }
-
- for (j = 0x80; j < 0x100; ) {
- printf("\n%2x", j);
- for (i = 0; i < 16; i++) {
- i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
- printf("\t%2x", val);
- }
- j += 0x10;
- }
- printf("\nEXT Page 2");
-
- val = PFUZE100_PAGE_REGISTER_PAGE2;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
- &val, 1)) {
- puts("i2c write failed\n");
- return 0;
- }
-
- for (j = 0x80; j < 0x100; ) {
- printf("\n%2x", j);
- for (i = 0; i < 16; i++) {
- i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
- printf("\t%2x", val);
- }
- j += 0x10;
- }
- printf("\n");
- }
-#endif
- /* get device programmed state */
- val = PFUZE100_PAGE_REGISTER_PAGE1;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
- puts("i2c write failed\n");
- return 0;
- }
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
- puts("i2c fuse_por read failed\n");
- return 0;
- }
- if (val & PFUZE100_FUSE_POR_M)
- programmed++;
-
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
- puts("i2c fuse_por read failed\n");
- return programmed;
- }
- if (val & PFUZE100_FUSE_POR_M)
- programmed++;
-
- if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
- puts("i2c fuse_por read failed\n");
- return programmed;
- }
- if (val & PFUZE100_FUSE_POR_M)
- programmed++;
-
- switch (programmed) {
- case 0:
- printf("PMIC: not programmed\n");
- break;
- case 3:
- printf("PMIC: programmed\n");
- break;
- default:
- printf("PMIC: undefined programming state\n");
- break;
- }
-
- /* The following is needed during production */
- if (programmed != 3) {
- /* set VGEN1 to 1.2V */
- val = PFUZE100_VGEN1_VAL;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1,
- &val, 1)) {
- puts("i2c write failed\n");
- return programmed;
- }
-
- /* set SWBST to 5.0V */
- val = PFUZE100_SWBST_VAL;
- if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1,
- &val, 1)) {
- puts("i2c write failed\n");
- }
- }
- return programmed;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static int pf0100_prog(void)
-{
- unsigned char bus = 1;
- unsigned char val;
- unsigned int i;
-
- if (pmic_init() == 3) {
- puts("PMIC already programmed, exiting\n");
- return CMD_RET_FAILURE;
- }
- /* set up gpio to manipulate vprog, initially off */
- imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
- ARRAY_SIZE(pmic_prog_pads));
- gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
-
- if (!((0 == i2c_set_bus_num(bus)) &&
- (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
- puts("i2c bus failed\n");
- return CMD_RET_FAILURE;
- }
-
- for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
- switch (pmic_otp_prog[i].cmd) {
- case pmic_i2c:
- val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
- if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
- 1, &val, 1)) {
- printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
- pmic_otp_prog[i].reg, val);
- return CMD_RET_FAILURE;
- }
- break;
- case pmic_delay:
- udelay(pmic_otp_prog[i].value * 1000);
- break;
- case pmic_vpgm:
- gpio_direction_output(PMIC_PROG_VOLTAGE,
- pmic_otp_prog[i].value);
- break;
- case pmic_pwr:
- /* TODO */
- break;
- }
- }
- return CMD_RET_SUCCESS;
-}
-
-static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int ret;
- puts("Programming PMIC OTP...");
- ret = pf0100_prog();
- if (ret == CMD_RET_SUCCESS)
- puts("done.\n");
- else
- puts("failed.\n");
- return ret;
-}
-
-U_BOOT_CMD(
- pf0100_otp_prog, 1, 0, do_pf0100_prog,
- "Program the OTP fuses on the PMIC PF0100",
- ""
-);
-#endif
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
deleted file mode 100644
index c0efb79bbc9..00000000000
--- a/board/toradex/apalis_imx6/pf0100.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for Freescale PMIC PF0100
-*/
-
-#ifndef PF0100_H_
-#define PF0100_H_
-
-/* 7-bit I2C bus slave address */
-#define PFUZE100_I2C_ADDR (0x08)
-/* Register Addresses */
-#define PFUZE100_DEVICEID (0x0)
-#define PFUZE100_REVID (0x3)
-#define PFUZE100_SW1AMODE (0x23)
-#define PFUZE100_SW1ACON 36
-#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */
-#define PFUZE100_SW1ACON_SPEED_M (0x3<<6)
-#define PFUZE100_SW1CCON 49
-#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */
-#define PFUZE100_SW1CCON_SPEED_M (0x3<<6)
-#define PFUZE100_SW1AVOL 32
-#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
-#define PFUZE100_SW1CVOL 46
-#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
-#define PFUZE100_VGEN1CTL (0x6c)
-#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */
-#define PFUZE100_SWBSTCTL (0x66)
-/* Always ON, Auto Switching Mode, 5.0V */
-#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00)
-
-/* chooses the extended page (registers 0x80..0xff) */
-#define PFUZE100_PAGE_REGISTER 0x7f
-#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0)
-#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
-#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
-
-/* extended page 1 */
-#define PFUZE100_FUSE_POR1 0xe4
-#define PFUZE100_FUSE_POR2 0xe5
-#define PFUZE100_FUSE_POR3 0xe6
-#define PFUZE100_FUSE_POR_M (0x1 << 1)
-
-
-/* output some informational messages, return the number FUSE_POR=1 */
-/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
-unsigned pmic_init(void);
-
-#endif /* PF0100_H_ */
diff --git a/board/toradex/apalis_imx6/pf0100_otp.inc b/board/toradex/apalis_imx6/pf0100_otp.inc
deleted file mode 100644
index a7790fd6c60..00000000000
--- a/board/toradex/apalis_imx6/pf0100_otp.inc
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-// Register Output for PF0100 programmer
-// Customer: Toradex AG
-// Program: Apalis iMX6
-// Sample marking:
-// Date: 12.02.2014
-// Time: 17:16:41
-// Generated from Spreadsheet Revision: P1.8
-
-/* sed commands to get from programmer script to struct */
-/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
- sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
- sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
-
-enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
-struct pmic_otp_prog_t{
- unsigned char cmd;
- unsigned char reg;
- unsigned short value;
-};
-
-struct pmic_otp_prog_t pmic_otp_prog[] = {
-{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
-{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
-{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
-{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
-{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
-{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
-{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
-{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
-{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
-{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
-{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
-{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
-{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
-{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
-{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
-{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
-{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
-{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
-{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
-{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
-{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
-{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
-{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
-{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
-{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
-{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
-{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
-{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
-{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
-{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
-{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
-{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
-
-#if 0 /* TBB mode */
-{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
-{pmic_delay, 0, 10},
-#else
-// Write OTP
-{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
-{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
-{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
-{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
-{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
-{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
-{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
-{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
-//VPGM:DOWN:n
-//VPGM:UP:n
-{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
-//-----------------------------------------------------------------------------------
-// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
-//-----------------------------------------------------------------------------------
-// BANK 1
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 2
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 3
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 4
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 5
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 6
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 7
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 8
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 9
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 10
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
-{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
-{pmic_i2c, 0xD0, 0x00}, // Clear
-{pmic_i2c, 0xD1, 0x00}, // Clear
-{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
-{pmic_delay, 0, 500},
-{pmic_pwr, 0, 1},
-#endif
-};
\ No newline at end of file
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
deleted file mode 100644
index 133fc1a4dbd..00000000000
--- a/configs/apalis_imx6_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
deleted file mode 100644
index 6e72422e0eb..00000000000
--- a/configs/apalis_imx6_nospl_com_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
deleted file mode 100644
index bc04aabbbc7..00000000000
--- a/configs/apalis_imx6_nospl_it_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
deleted file mode 100644
index 135b3c9584d..00000000000
--- a/include/configs/apalis_imx6.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2015 Toradex, Inc.
- *
- * Configuration settings for the Toradex Apalis iMX6
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#undef CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_MACH_TYPE 4886
-
-#include <asm/arch/imx-regs.h>
-#include <asm/mach-imx/gpio.h>
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
-/* MMC Configs */
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* Network */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 6
-#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 4096
-#define CONFIG_TFTP_TSIZE
-
-/* USB Configs */
-/* Host */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-/* Client */
-#define CONFIG_USBD_HS
-
-#define CONFIG_USB_GADGET_MASS_STORAGE
-/* USB DFU */
-#define CONFIG_DFU_MMC
-
-/* Miscellaneous commands */
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition */
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FLASH
-
-#undef CONFIG_IPADDR
-#define CONFIG_IPADDR 192.168.10.2
-#define CONFIG_NETMASK 255.255.255.0
-#undef CONFIG_SERVERIP
-#define CONFIG_SERVERIP 192.168.10.1
-
-#define CONFIG_LOADADDR 0x12000000
-
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DRIVE_SATA "sata "
-#else
-#define CONFIG_DRIVE_SATA
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
-#else
-#define CONFIG_DRIVE_MMC
-#endif
-
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
-
-#define DFU_ALT_EMMC_INFO \
- "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "uImage fat 0 1;" \
- "imx6q-colibri-eval-v3.dtb fat 0 1;" \
- "imx6q-colibri-cam-eval-v3.dtb fat 0 1"
-
-#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
- "rootwait\0" \
- "emmcboot=run setup; " \
- "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
- "${vidargs}; echo Booting from internal eMMC chip...; " \
- "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} ${dtbparam}\0" \
- "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0x20000000\0" \
- "fdt_addr_r=0x12000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x11000000\0" \
- "ramdisk_addr_r=0x12100000\0"
-
-#define NFS_BOOTCMD \
- "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
- "nfsboot=run setup; " \
- "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
- "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
- "run nfsdtbload; dhcp ${kernel_addr_r} " \
- "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
- "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
- "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define SD_BOOTCMD \
- "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
- "rootwait\0" \
- "sdboot=run setup; " \
- "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
- "${vidargs}; echo Booting from SD card; " \
- "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} ${dtbparam}\0" \
- "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define USB_BOOTCMD \
- "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
- "rootwait\0" \
- "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
- "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} ${dtbparam}\0" \
- "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
-#define FDT_FILE "imx6q-apalis-eval.dtb"
-#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
-#else
-#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
- "run nfsboot ; echo ; echo nfsboot failed ; " \
- "usb start ;" \
- "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
- "boot_file=uImage\0" \
- "console=ttymxc0\0" \
- "defargs=enable_wait_mode=off vmalloc=400M\0" \
- "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
- EMMC_BOOTCMD \
- "fdt_file=" FDT_FILE "\0" \
- "fdt_fixup=;\0" \
- MEM_LAYOUT_ENV_SETTINGS \
- NFS_BOOTCMD \
- SD_BOOTCMD \
- "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
- "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
- "flash_eth.img && source ${loadaddr}\0" \
- "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
- "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
- "source ${loadaddr}\0" \
- "setup=setenv setupargs fec_mac=${ethaddr} " \
- "consoleblank=0 no_console_suspend=1 console=tty1 " \
- "console=${console},${baudrate}n8\0 " \
- "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
- "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
- "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
- "source ${loadaddr}\0" \
- "splashpos=m,m\0" \
- "vidargs=mxc_hdmi.only_cea=1 " \
- "video=mxcfb0:dev=hdmi,1920x1080M at 60,if=RGB24 " \
- "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
- "fbmem=32M\0 "
-
-/* Miscellaneous configurable options */
-#undef CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_CBSIZE 1024
-#undef CONFIG_SYS_MAXARGS
-#define CONFIG_SYS_MAXARGS 48
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
- CONFIG_TDX_CFG_BLOCK_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 1
-#endif
-
-#define CONFIG_OF_SYSTEM_SETUP
-
-#define CONFIG_CMD_TIME
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 31/93] arm: Remove wandboard board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (29 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 30/93] arm: Remove apalis_imx6_nospl_it board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 21:33 ` Marek Vasut
2018-11-19 15:53 ` [U-Boot] [PATCH 32/93] arm: Remove birdland_bav335a board Simon Glass
` (66 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/wandboard/Kconfig | 9 -
board/wandboard/MAINTAINERS | 6 -
board/wandboard/Makefile | 5 -
board/wandboard/README | 39 ---
board/wandboard/spl.c | 425 --------------------------
board/wandboard/wandboard.c | 559 ----------------------------------
configs/wandboard_defconfig | 46 ---
include/configs/wandboard.h | 156 ----------
9 files changed, 1246 deletions(-)
delete mode 100644 board/wandboard/Kconfig
delete mode 100644 board/wandboard/MAINTAINERS
delete mode 100644 board/wandboard/Makefile
delete mode 100644 board/wandboard/README
delete mode 100644 board/wandboard/spl.c
delete mode 100644 board/wandboard/wandboard.c
delete mode 100644 configs/wandboard_defconfig
delete mode 100644 include/configs/wandboard.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 0cfb565dd70..194e8d855fc 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -560,7 +560,6 @@ source "board/toradex/colibri-imx6ull/Kconfig"
source "board/k+p/kp_imx6q_tpc/Kconfig"
source "board/udoo/Kconfig"
source "board/udoo/neo/Kconfig"
-source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
endif
diff --git a/board/wandboard/Kconfig b/board/wandboard/Kconfig
deleted file mode 100644
index def63696e5f..00000000000
--- a/board/wandboard/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_WANDBOARD
-
-config SYS_BOARD
- default "wandboard"
-
-config SYS_CONFIG_NAME
- default "wandboard"
-
-endif
diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
deleted file mode 100644
index d7cbae8f950..00000000000
--- a/board/wandboard/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-WANDBOARD BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/wandboard/
-F: include/configs/wandboard.h
-F: configs/wandboard_defconfig
diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile
deleted file mode 100644
index 6e886f729a8..00000000000
--- a/board/wandboard/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y := wandboard.o spl.o
diff --git a/board/wandboard/README b/board/wandboard/README
deleted file mode 100644
index e5170bcc812..00000000000
--- a/board/wandboard/README
+++ /dev/null
@@ -1,39 +0,0 @@
-U-Boot for Wandboard
---------------------
-
-This file contains information for the port of U-Boot to the Wandboard.
-
-Wandboard is a development board that has three variants based on the following
-SoCs: mx6 quad, mx6 quad plus, mx6 dual lite and mx6 solo.
-
-For more details about Wandboard, please refer to:
-http://www.wandboard.org/
-
-Building U-Boot for Wandboard
------------------------------
-
-To build U-Boot for the Wandboard:
-
-$ make wandboard_config
-$ make
-
-Flashing U-Boot into the SD card
---------------------------------
-
-- After the 'make' command completes, the generated 'SPL' binary must be
-flashed into the SD card;
-
-$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-(Note - the SD card node may vary, so adjust this as needed).
-
-- Flash the u-boot.img image into the SD card:
-
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Insert the SD card into the slot located in the bottom of the board (same side
-as the mx6 processor)
-
-- Connect the serial cable to the host PC
-
-- Power up the board and U-Boot messages will appear in the serial console.
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
deleted file mode 100644
index 9c3350019c8..00000000000
--- a/board/wandboard/spl.c
+++ /dev/null
@@ -1,425 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Wandboard
- * Author: Tungyi Lin <tungyilin1127@gmail.com>
- * Richard Hu <hakahu@gmail.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-
-#if defined(CONFIG_SPL_BUILD)
-#include <asm/arch/mx6-ddr.h>
-/*
- * Driving strength:
- * 0x30 == 40 Ohm
- * 0x28 == 48 Ohm
- */
-
-#define IMX6DQ_DRIVE_STRENGTH 0x30
-#define IMX6SDL_DRIVE_STRENGTH 0x28
-#define IMX6QP_DRIVE_STRENGTH 0x28
-
-/* configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
- .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_cas = IMX6DQ_DRIVE_STRENGTH,
- .dram_ras = IMX6DQ_DRIVE_STRENGTH,
- .dram_reset = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
-};
-
-/* configure MX6QP mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
- .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
- .dram_cas = IMX6QP_DRIVE_STRENGTH,
- .dram_ras = IMX6QP_DRIVE_STRENGTH,
- .dram_reset = IMX6QP_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
-};
-
-/* configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
-};
-
-/* configure MX6QP mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6QP_DRIVE_STRENGTH,
- .grp_ctlds = IMX6QP_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b1ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b2ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b3ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b4ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b5ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b6ds = IMX6QP_DRIVE_STRENGTH,
- .grp_b7ds = IMX6QP_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* H5T04G63AFR-PB */
-static struct mx6_ddr3_cfg h5t04g63afr = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* H5TQ2G63DFR-H9 */
-static struct mx6_ddr3_cfg h5tq2g63dfr = {
- .mem_speed = 1333,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1350,
- .trcmin = 4950,
- .trasmin = 3600,
-};
-
-static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001f001f,
- .p0_mpwldectrl1 = 0x001f001f,
- .p1_mpwldectrl0 = 0x001f001f,
- .p1_mpwldectrl1 = 0x001f001f,
- .p0_mpdgctrl0 = 0x4301030d,
- .p0_mpdgctrl1 = 0x03020277,
- .p1_mpdgctrl0 = 0x4300030a,
- .p1_mpdgctrl1 = 0x02780248,
- .p0_mprddlctl = 0x4536393b,
- .p1_mprddlctl = 0x36353441,
- .p0_mpwrdlctl = 0x41414743,
- .p1_mpwrdlctl = 0x462f453f,
-};
-
-/* DDR 64bit 2GB */
-static struct mx6_ddr_sysinfo mem_q = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 3, /* 4 refresh commands per refresh cycle */
-};
-
-static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001f001f,
- .p0_mpwldectrl1 = 0x001f001f,
- .p1_mpwldectrl0 = 0x001f001f,
- .p1_mpwldectrl1 = 0x001f001f,
- .p0_mpdgctrl0 = 0x420e020e,
- .p0_mpdgctrl1 = 0x02000200,
- .p1_mpdgctrl0 = 0x42020202,
- .p1_mpdgctrl1 = 0x01720172,
- .p0_mprddlctl = 0x494c4f4c,
- .p1_mprddlctl = 0x4a4c4c49,
- .p0_mpwrdlctl = 0x3f3f3133,
- .p1_mpwrdlctl = 0x39373f2e,
-};
-
-static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0040003c,
- .p0_mpwldectrl1 = 0x0032003e,
- .p0_mpdgctrl0 = 0x42350231,
- .p0_mpdgctrl1 = 0x021a0218,
- .p0_mprddlctl = 0x4b4b4e49,
- .p0_mpwrdlctl = 0x3f3f3035,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_dl = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 3, /* 4 refresh commands per refresh cycle */
-};
-
-/* DDR 32bit 512MB */
-static struct mx6_ddr_sysinfo mem_s = {
- .dsize = 1,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 0,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 3, /* 4 refresh commands per refresh cycle */
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF03000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init_imx6qp_lpddr3(void)
-{
- /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
- writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
- /* Calibrations - ZQ */
- writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
- /* write leveling */
- writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
- writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
- writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
- writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
- /*
- * DQS gating, read delay, write delay calibration values
- * based on calibration compare of 0x00ffff00
- */
- writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
- writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
- writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
- writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
- writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
- writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
- writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
- writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
- writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
- writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
- writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
- writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
- writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
- writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
- writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
- writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
- writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
- writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
- writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
- writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
- /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
- writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
- writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
- writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
- writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
- writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
- writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
- writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
- writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
- writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
- writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
- writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
- writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
- writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
- /* add NOC DDR configuration */
- writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
- writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
- writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
- writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
- writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
- writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
- writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
- writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
- writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
- writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
- writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
- writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
- writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
- writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
- writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
- writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
- writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
-}
-
-static void spl_dram_init(void)
-{
- if (is_mx6dqp()) {
- mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
- spl_dram_init_imx6qp_lpddr3();
- } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
- mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
- } else if (is_cpu_type(MXC_CPU_MX6DL)) {
- mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
- } else if (is_cpu_type(MXC_CPU_MX6Q)) {
- mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
- mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
- }
-
- udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- gpr_init();
-
- /* iomux */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
-#endif
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
deleted file mode 100644
index 6af1b458829..00000000000
--- a/board/wandboard/wandboard.c
+++ /dev/null
@@ -1,559 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014 O.S. Systems Software LTDA.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/io.h>
-#include <linux/sizes.h>
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <phy.h>
-#include <i2c.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
-#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
-#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
-#define REV_DETECTION IMX_GPIO_NR(2, 28)
-
-static bool with_pmic;
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* Carrier MicroSD Card Detect */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* SOM MicroSD Card Detect */
- IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8031 PHY Reset */
- IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
- /* AR8035 POWER */
- IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const rev_detection_pad[] = {
- IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- if (with_pmic) {
- SETUP_IOMUX_PADS(enet_ar8035_power_pads);
- /* enable AR8035 POWER */
- gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
- }
- /* wait until 3.3V of PHY and clock become stable */
- mdelay(10);
-
- /* Reset AR8031 PHY */
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR},
- {USDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- u32 index = 0;
-
- /*
- * Following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 SOM MicroSD
- * mmc1 Carrier board MicroSD
- */
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 4;
- gpio_direction_input(USDHC3_CD_GPIO);
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc1_pads);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[1].max_bus_width = 4;
- gpio_direction_input(USDHC1_CD_GPIO);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static int ar8031_phy_fixup(struct phy_device *phydev)
-{
- unsigned short val;
- int mask;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- if (with_pmic)
- mask = 0xffe7; /* AR8035 */
- else
- mask = 0xffe3; /* AR8031 */
-
- val &= mask;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- ar8031_phy_fixup(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-struct i2c_pads_info mx6q_i2c2_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-struct i2c_pads_info mx6dl_i2c2_pad_info = {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-struct i2c_pads_info mx6q_i2c3_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
-
-struct i2c_pads_info mx6dl_i2c3_pad_info = {
- .scl = {
- .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
-
-static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
- IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
- IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
- IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
- IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
- IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
- IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
- IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
- IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
- IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
- IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
- IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
- IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
- IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
- IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
- IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
- IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
- IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
- IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
- IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
- IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
- IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
- IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
- IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
- IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
-};
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-static int detect_i2c(struct display_info_t const *dev)
-{
- return (0 == i2c_set_bus_num(dev->bus)) &&
- (0 == i2c_probe(dev->addr));
-}
-
-static void enable_fwadapt_7wvga(struct display_info_t const *dev)
-{
- SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
-
- gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
- gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 1,
- .addr = 0x10,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = detect_i2c,
- .enable = enable_fwadapt_7wvga,
- .mode = {
- .name = "FWBADAPT-LCD-F07A-0102",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 33260,
- .left_margin = 128,
- .right_margin = 128,
- .upper_margin = 22,
- .lower_margin = 22,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
- imx_setup_hdmi();
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- /* Disable LCD backlight */
- SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
- gpio_direction_input(IMX_GPIO_NR(4, 20));
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
-
- return 0;
-}
-
-#define PMIC_I2C_BUS 2
-
-int power_init_board(void)
-{
- struct pmic *p;
- u32 reg;
-
- /* configure PFUZE100 PMIC */
- power_pfuze100_init(PMIC_I2C_BUS);
- p = pmic_get("PFUZE100");
- if (p && !pmic_probe(p)) {
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
- with_pmic = true;
-
- /* Set VGEN2 to 1.5V and enable */
- pmic_reg_read(p, PFUZE100_VGEN2VOL, ®);
- reg &= ~(LDO_VOL_MASK);
- reg |= (LDOA_1_50V | (1 << (LDO_EN)));
- pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
- }
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-static bool is_revc1(void)
-{
- SETUP_IOMUX_PADS(rev_detection_pad);
- gpio_direction_input(REV_DETECTION);
-
- if (gpio_get_value(REV_DETECTION))
- return true;
- else
- return false;
-}
-
-static bool is_revd1(void)
-{
- if (with_pmic)
- return true;
- else
- return false;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_mx6dqp())
- env_set("board_rev", "MX6QP");
- else if (is_mx6dq())
- env_set("board_rev", "MX6Q");
- else
- env_set("board_rev", "MX6DL");
-
- if (is_revd1())
- env_set("board_name", "D1");
- else if (is_revc1())
- env_set("board_name", "C1");
- else
- env_set("board_name", "B1");
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
- if (is_mx6dq() || is_mx6dqp()) {
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
- } else {
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
- }
-
- setup_display();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- if (is_revd1())
- puts("Board: Wandboard rev D1\n");
- else if (is_revc1())
- puts("Board: Wandboard rev C1\n");
- else
- puts("Board: Wandboard rev B1\n");
-
- return 0;
-}
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
deleted file mode 100644
index 4d8ccff675e..00000000000
--- a/configs/wandboard_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_WANDBOARD=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
deleted file mode 100644
index b03a1c550cd..00000000000
--- a/include/configs/wandboard.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Wandboard.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#include "imx6_spl.h"
-
-#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* SATA Configs */
-
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
-/* MMC Configuration */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-#define CONFIG_PHY_ATHEROS
-
-/* Framebuffer */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0\0" \
- "splashpos=m,m\0" \
- "fdtfile=undefined\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_addr_r=0x18000000\0" \
- "fdt_addr=0x18000000\0" \
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "finduuid=part uuid mmc 0:1 uuid\0" \
- "update_sd_firmware_filename=u-boot.imx\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "findfdt="\
- "if test $board_name = D1 && test $board_rev = MX6QP ; then " \
- "setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \
- "if test $board_name = D1 && test $board_rev = MX6Q ; then " \
- "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
- "if test $board_name = D1 && test $board_rev = MX6DL ; then " \
- "setenv fdtfile imx6dl-wandboard-revd1.dtb; fi; " \
- "if test $board_name = C1 && test $board_rev = MX6Q ; then " \
- "setenv fdtfile imx6q-wandboard.dtb; fi; " \
- "if test $board_name = C1 && test $board_rev = MX6DL ; then " \
- "setenv fdtfile imx6dl-wandboard.dtb; fi; " \
- "if test $board_name = B1 && test $board_rev = MX6Q ; then " \
- "setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \
- "if test $board_name = B1 && test $board_rev = MX6DL ; then " \
- "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \
- "if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine dtb to use; fi; \0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_addr_r=0x13000000\0" \
- "ramdiskaddr=0x13000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(SATA, sata, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#define CONFIG_ENV_OFFSET (768 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-#endif /* __CONFIG_H * */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 32/93] arm: Remove birdland_bav335a board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (30 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 31/93] arm: Remove wandboard board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 33/93] arm: Remove gurnard board Simon Glass
` (65 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/birdland/bav335x/Kconfig | 23 --
board/birdland/bav335x/Makefile | 11 -
board/birdland/bav335x/README | 31 --
board/birdland/bav335x/board.c | 429 ------------------------
board/birdland/bav335x/board.h | 58 ----
board/birdland/bav335x/mux.c | 190 -----------
board/birdland/bav335x/u-boot.lds | 115 -------
configs/birdland_bav335a_defconfig | 67 ----
configs/birdland_bav335b_defconfig | 67 ----
include/configs/bav335x.h | 501 -----------------------------
11 files changed, 1493 deletions(-)
delete mode 100644 board/birdland/bav335x/Kconfig
delete mode 100644 board/birdland/bav335x/Makefile
delete mode 100644 board/birdland/bav335x/README
delete mode 100644 board/birdland/bav335x/board.c
delete mode 100644 board/birdland/bav335x/board.h
delete mode 100644 board/birdland/bav335x/mux.c
delete mode 100644 board/birdland/bav335x/u-boot.lds
delete mode 100644 configs/birdland_bav335a_defconfig
delete mode 100644 configs/birdland_bav335b_defconfig
delete mode 100644 include/configs/bav335x.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42e3fcb5e1a..7389b8db46d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1531,7 +1531,6 @@ source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/ucRobotics/bubblegum_96/Kconfig"
-source "board/birdland/bav335x/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
diff --git a/board/birdland/bav335x/Kconfig b/board/birdland/bav335x/Kconfig
deleted file mode 100644
index 40053665aab..00000000000
--- a/board/birdland/bav335x/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if TARGET_BAV335X
-
-config SYS_BOARD
- default "bav335x"
-
-config SYS_VENDOR
- default "birdland"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "bav335x"
-
-config BAV_VERSION
- int "BAV335x Version (1=A, 2=B)"
- range 1 2
- help
- The BAV335x has various version of the board. Rev.A (mostly obsolete)
- used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY.
- Overwrite this if you have an older Rev.A and want ethernet support.
-
-endif
diff --git a/board/birdland/bav335x/Makefile b/board/birdland/bav335x/Makefile
deleted file mode 100644
index 42cefa1f85d..00000000000
--- a/board/birdland/bav335x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/board/birdland/bav335x/README b/board/birdland/bav335x/README
deleted file mode 100644
index 08c73eee0c2..00000000000
--- a/board/birdland/bav335x/README
+++ /dev/null
@@ -1,31 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'BAV335x' board build.
-For more information about this board, visit http://birdland.com/oem
-
-
-Hardware
-========
-
-The binary produced supports the bav335x Rev.A with 10/100 MB PHY
-and Rev.B (default) with GB ethernet PHY.
-If the BAV335x EEPROM is populated and programmed, the board will
-automatically detect the version and extract proper serial# and
-mac address from the EE.
-
-
-Customization
-=============
-
-The following blocks are required:
-- I2C, to talk with the PMIC and ensure that we do not run afoul of
- errata 1.0.24.
-
-When removing options as part of customization,
-CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
-needs and to remove no longer relevant options as in some cases we
-define additional text blocks (such as for NAND or DFU strings). Also
-note that all of the SPL options are grouped together, rather than with
-the IP blocks, so both areas will need their choices updated to reflect
-the custom design.
diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c
deleted file mode 100644
index b95186026fd..00000000000
--- a/board/birdland/bav335x/board.c
+++ /dev/null
@@ -1,429 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for Birdland Audio BAV335x Network Processor
- *
- * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <power/tps65217.h>
-#include <power/tps65910.h>
-#include <environment.h>
-#include <watchdog.h>
-#include <environment.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
-
-static __maybe_unused struct ctrl_dev *cdev =
- (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(struct board_eeconfig *header)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
- return -ENODEV;
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
- sizeof(struct board_eeconfig)))
- return -EIO;
-
- if (header->magic != BOARD_MAGIC) {
- /* read the i2c eeprom again using only a 1 byte address */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
- sizeof(struct board_eeconfig)))
- return -EIO;
-
- if (header->magic != BOARD_MAGIC)
- return -EINVAL;
- }
- return 0;
-}
-
-
-
-
-enum board_type get_board_type(bool debug)
-{
- int ecode;
- struct board_eeconfig header;
-
- ecode = read_eeprom(&header);
- if (ecode == 0) {
- if (header.version[1] == 'A') {
- if (debug)
- puts("=== Detected Board model BAV335x Rev.A");
- return BAV335A;
- } else if (header.version[1] == 'B') {
- if (debug)
- puts("=== Detected Board model BAV335x Rev.B");
- return BAV335B;
- } else if (debug) {
- puts("### Un-known board model in serial-EE\n");
- }
- } else if (debug) {
- switch (ecode) {
- case -ENODEV:
- puts("### Board doesn't have a serial-EE\n");
- break;
- case -EINVAL:
- puts("### Board serial-EE signature is incorrect.\n");
- break;
- default:
- puts("### IO Error reading serial-EE.\n");
- break;
- }
- }
-
-#if (CONFIG_BAV_VERSION == 1)
- if (debug)
- puts("### Selecting BAV335A as per config\n");
- return BAV335A;
-#elif (CONFIG_BAV_VERSION == 2)
- if (debug)
- puts("### Selecting BAV335B as per config\n");
- return BAV335B;
-#endif
-#if (NOT_DEFINED == 2)
-#error "SHOULD NEVER DISPLAY THIS"
-#endif
-
- if (debug)
- puts("### Defaulting to model BAV335x Rev.B\n");
- return BAV335B;
-}
-
-
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-static const struct ddr_data ddr3_bav335x_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-
-static struct emif_regs ddr3_bav335x_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_load();
- if (env_get_yesno("boot_os") != 1)
- return 1;
-#endif
-
- return 0;
-}
-#endif
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
- 266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
- 303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_bone_black = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- /* debug print detect status */
- (void)get_board_type(true);
-
- /* Get the frequency */
- /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
- dpll_mpu_opp100.m = MPUPLL_M_1000;
-
- if (i2c_probe(TPS65217_CHIP_PM))
- return;
-
- /* Set the USB Current Limit */
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
- TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
- TPS65217_USB_INPUT_CUR_LIMIT_MASK))
- puts("! tps65217_reg_write: could not set USB limit\n");
-
- /* Set the Core Voltage (DCDC3) to 1.125V */
- if (tps65217_voltage_update(TPS65217_DEFDCDC3,
- TPS65217_DCDC_VOLT_SEL_1125MV)) {
- puts("! tps65217_reg_write: could not set Core Voltage\n");
- return;
- }
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set the MPU Voltage (DCDC2) */
- if (tps65217_voltage_update(TPS65217_DEFDCDC2,
- TPS65217_DCDC_VOLT_SEL_1325MV)) {
- puts("! tps65217_reg_write: could not set MPU Voltage\n");
- return;
- }
-
- /*
- * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
- * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
- */
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
- TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
- puts("! tps65217_reg_write: could not set LDO3\n");
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
- TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
- puts("! tps65217_reg_write: could not set LDO4\n");
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- return &dpll_ddr_bone_black;
-}
-
-void set_uart_mux_conf(void)
-{
-#if CONFIG_CONS_INDEX == 1
- enable_uart0_pin_mux();
-#elif CONFIG_CONS_INDEX == 2
- enable_uart1_pin_mux();
-#elif CONFIG_CONS_INDEX == 3
- enable_uart2_pin_mux();
-#elif CONFIG_CONS_INDEX == 4
- enable_uart3_pin_mux();
-#elif CONFIG_CONS_INDEX == 5
- enable_uart4_pin_mux();
-#elif CONFIG_CONS_INDEX == 6
- enable_uart5_pin_mux();
-#endif
-}
-
-void set_mux_conf_regs(void)
-{
- enum board_type board;
-
- board = get_board_type(false);
- enable_board_pin_mux(board);
-}
-
-const struct ctrl_ioregs ioregs_bonelt = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-
-void sdram_init(void)
-{
- config_ddr(400, &ioregs_bonelt,
- &ddr3_bav335x_data,
- &ddr3_bav335x_cmd_ctrl_data,
- &ddr3_bav335x_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
- gpmc_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", "BAV335xB");
- env_set("board_rev", "B"); /* Fix me, but why bother.. */
-#endif
- return 0;
-}
-#endif
-
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-
-/*
- * This function will:
- * Perform fixups to the PHY present on certain boards. We only need this
- * function in:
- * - SPL with either CPSW or USB ethernet support
- * - Full U-Boot, with either CPSW or USB ethernet
- * Build in only these cases to avoid warnings about unused variables
- * when we build an SPL that has neither option but full U-Boot will.
- */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
- defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
-int board_eth_init(bd_t *bis)
-{
- int ecode, rv, n;
- uint8_t mac_addr[6];
- struct board_eeconfig header;
- __maybe_unused enum board_type board;
-
- /* Default manufacturing address; used when no EE or invalid */
- n = 0;
- mac_addr[0] = 0;
- mac_addr[1] = 0x20;
- mac_addr[2] = 0x18;
- mac_addr[3] = 0x1C;
- mac_addr[4] = 0x00;
- mac_addr[5] = 0x01;
-
- ecode = read_eeprom(&header);
- /* if we have a valid EE, get mac address from there */
- if ((ecode == 0) &&
- is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
- memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
- }
-
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
- board = get_board_type(false);
-
- /* Rev.A uses 10/100 PHY in mii mode */
- if (board == BAV335A) {
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
- }
- /* Rev.B (default) uses GB PHY in rmii mode */
- else {
- writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
- = PHY_INTERFACE_MODE_RGMII;
- }
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-#endif
-
-#endif
-
- return n;
-}
-#endif
diff --git a/board/birdland/bav335x/board.h b/board/birdland/bav335x/board.h
deleted file mode 100644
index ddbd5d04594..00000000000
--- a/board/birdland/bav335x/board.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.c
- *
- * Board functions for Birdland Audio BAV335x Network Processor
- *
- * Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem
- *
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/* Serial MagicE: AA 55 BA BE */
-#define BOARD_MAGIC 0xBEBA55AA
-enum board_type {UNKNOWN, BAV335A, BAV335B};
-
-
-/*
- * The BAV335x may use a built-in read-only serial EEProm.
- * The Evaluation board, disables the write-protect so the Serial-EE
- * Can be programmed during manufacturing to store fields such as
- * a board serial number, ethernet mac address and other user fields.
- * Additionally, the Serial-EE can store the specific version of the
- * board it runs on, and overwrite the defaults in _defconfig
- */
-#define HDR_NO_OF_MAC_ADDR 3
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-
-struct board_eeconfig {
- unsigned int magic;
- char name[HDR_NAME_LEN]; /* BAV3354 */
- char version[4]; /* 0B20 - Rev.B2 */
- char serial[16];
- char config[32];
- char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
-enum board_type get_board_type(bool verbose_debug_output);
-
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(enum board_type board);
-
-#endif
diff --git a/board/birdland/bav335x/mux.c b/board/birdland/bav335x/mux.c
deleted file mode 100644
index f18bfa4f604..00000000000
--- a/board/birdland/bav335x/mux.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
- {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
- {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
- {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
- {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
- {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
- {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
- {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
- {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
- {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
- {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
- {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
- {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
- {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
- {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
- {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
- {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart1_pin_mux(void)
-{
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
- configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
- configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
- configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
- configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-
-/* CPLD registers */
-#define I2C_CPLD_ADDR 0x35
-#define CFG_REG 0x10
-
-
-void enable_board_pin_mux(enum board_type board)
-{
- configure_module_pin_mux(i2c1_pin_mux);
- if (board == BAV335A)
- configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
- else
- configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
-
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(mmc1_pin_mux);
-}
diff --git a/board/birdland/bav335x/u-boot.lds b/board/birdland/bav335x/u-boot.lds
deleted file mode 100644
index 5d0c5cf27e4..00000000000
--- a/board/birdland/bav335x/u-boot.lds
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/birdland/bav335x/built-in.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
deleted file mode 100644
index 89c777872a4..00000000000
--- a/configs/birdland_bav335a_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_BAV335X=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_BAV_VERSION=1
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
deleted file mode 100644
index e3dc88b0058..00000000000
--- a/configs/birdland_bav335b_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_BAV335X=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_BAV_VERSION=2
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MUSB_NEW_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
deleted file mode 100644
index df5d5bdc4a9..00000000000
--- a/include/configs/bav335x.h
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
- * bav335x.h
- *
- * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_BAV335X_H
-#define __CONFIG_BAV335X_H
-
-#include <configs/ti_am335x_common.h>
-
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_TIMESTAMP
-#endif
-
-#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-
-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-/* Custom script for NOR */
-#define CONFIG_SYS_LDSCRIPT "board/birdland/bav335x/u-boot.lds"
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
-
-#ifdef CONFIG_NAND
-#define NANDARGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${fdtaddr} u-boot-spl-os; " \
- "nand read ${loadaddr} kernel; " \
- "bootz ${loadaddr} - ${fdtaddr}\0"
-#else
-#define NANDARGS ""
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
-DEFAULT_LINUX_BOOT_ENV \
-"boot_fdt=try\0" \
-"bootpart=0:2\0" \
-"bootdir=\0" \
-"fdtdir=/dtbs\0" \
-"bootfile=zImage\0" \
-"fdtfile=undefined\0" \
-"console=ttyO0,115200n8\0" \
-"loadaddr=0x82000000\0" \
-"fdtaddr=0x88000000\0" \
-"rdaddr=0x88080000\0" \
-"initrd_high=0xffffffff\0" \
-"fdt_high=0xffffffff\0" \
-"partitions=" \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
-"optargs=\0" \
-"cmdline=\0" \
-"mmcdev=0\0" \
-"mmcpart=1\0" \
-"mmcroot=/dev/mmcblk0p2 ro\0" \
-"mmcrootfstype=ext4 rootwait fixrtc\0" \
-"rootpath=/export/rootfs\0" \
-"nfsopts=nolock\0" \
-"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
-"ramroot=/dev/ram0 rw\0" \
-"ramrootfstype=ext2\0" \
-"mmcargs=setenv bootargs console=${console} ${optargs} " \
- "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
-"server_ip=192.168.1.100\0" \
-"gw_ip=192.168.1.1\0" \
-"netmask=255.255.255.0\0" \
-"hostname=\0" \
-"device=eth0\0" \
-"autoconf=off\0" \
-"root_dir=/home/userid/targetNFS\0" \
-"nfs_options=,vers=3\0" \
-"nfsrootfstype=ext4 rootwait fixrtc\0" \
-"nfsargs=setenv bootargs console=${console} ${optargs} " \
- "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
- "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
-"netargs=setenv bootargs console=${console} " \
- "${optargs} root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
-"bootenv=uEnv.txt\0" \
-"script=boot.scr\0" \
-"scriptfile=${script}\0" \
-"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
-"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
- "source ${loadaddr}\0" \
- "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
-"importbootenv=echo Importing environment from mmc ...; " \
- "env import -t -r $loadaddr $filesize\0" \
-"ramargs=setenv bootargs console=${console} " \
- "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
-"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
-"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadrd=load mmc ${bootpart} ${rdaddr} " \
- "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
-"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
- "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
-"mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "gpio set 54;" \
- "setenv bootpart ${mmcdev}:1; " \
- "if test -e mmc ${bootpart} /etc/fstab; then " \
- "setenv mmcpart 1;" \
- "fi; " \
- "echo Checking for: /uEnv.txt ...;" \
- "if test -e mmc ${bootpart} /uEnv.txt; then " \
- "if run loadbootenv; then " \
- "gpio set 55;" \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "echo Checking if uenvcmd is set ...;" \
- "if test -n ${uenvcmd}; then " \
- "gpio set 56; " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "echo Checking if client_ip is set ...;" \
- "if test -n ${client_ip}; then " \
- "if test -n ${dtb}; then " \
- "setenv fdtfile ${dtb};" \
- "echo using ${fdtfile} ...;" \
- "fi;" \
- "gpio set 56; " \
- "if test -n ${uname_r}; then " \
- "echo Running nfsboot_uname_r ...;" \
- "run nfsboot_uname_r;" \
- "fi;" \
- "echo Running nfsboot ...;" \
- "run nfsboot;" \
- "fi;" \
- "fi; " \
- "echo Checking for: /${script} ...;" \
- "if test -e mmc ${bootpart} /${script}; then " \
- "gpio set 55;" \
- "setenv scriptfile ${script};" \
- "run loadbootscript;" \
- "echo Loaded script from ${scriptfile};" \
- "gpio set 56; " \
- "run bootscript;" \
- "fi; " \
- "echo Checking for: /boot/${script} ...;" \
- "if test -e mmc ${bootpart} /boot/${script}; then " \
- "gpio set 55;" \
- "setenv scriptfile /boot/${script};" \
- "run loadbootscript;" \
- "echo Loaded script from ${scriptfile};" \
- "gpio set 56; " \
- "run bootscript;" \
- "fi; " \
- "echo Checking for: /boot/uEnv.txt ...;" \
- "for i in 1 2 3 4 5 6 7 ; do " \
- "setenv mmcpart ${i};" \
- "setenv bootpart ${mmcdev}:${mmcpart};" \
- "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
- "gpio set 55;" \
- "load mmc ${bootpart} ${loadaddr} " \
- "/boot/uEnv.txt;" \
- "env import -t ${loadaddr} ${filesize};" \
- "echo Loaded environment from /boot/uEnv.txt;" \
- "if test -n ${dtb}; then " \
- "setenv fdtfile ${dtb};" \
- "echo Using: dtb=${fdtfile} ...;" \
- "fi;" \
- "echo Checking if uname_r is set in " \
- "/boot/uEnv.txt...;" \
- "if test -n ${uname_r}; then " \
- "gpio set 56; " \
- "echo Running uname_boot ...;" \
- "setenv mmcroot /dev/mmcblk${mmcdev}" \
- "p${mmcpart} ro;" \
- "run uname_boot;" \
- "fi;" \
- "fi;" \
- "done;" \
- "fi;\0" \
-"netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "tftp ${fdtaddr} ${fdtfile}; " \
- "run netargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
-"nfsboot=echo Booting from ${server_ip} ...; " \
- "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
- "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
- ":${device}:${autoconf}; " \
- "setenv autoload no; " \
- "setenv serverip ${server_ip}; " \
- "setenv ipaddr ${client_ip}; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "tftp ${fdtaddr} dtbs/${fdtfile}; " \
- "run nfsargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
-"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
- "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
- "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
- ":${device}:${autoconf}; " \
- "setenv autoload no; " \
- "setenv serverip ${server_ip}; " \
- "setenv ipaddr ${client_ip}; " \
- "tftp ${loadaddr} vmlinuz-${uname_r}; " \
- "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
- "run nfsargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
-"ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
-"findfdt="\
- "if test $board_rev = B; then " \
- "setenv fdtfile birdland_bav335b.dtb; " \
- "setenv fdtbase am335x-boneblack; fi; " \
- "if test $board_rev = A; then " \
- "setenv fdtfile birdland_bav335a.dtb; " \
- "setenv fdtbase am335x-boneblack; fi; " \
- "if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree to use; fi; \0" \
-"uname_boot="\
- "setenv bootdir /boot; " \
- "setenv bootfile vmlinuz-${uname_r}; " \
- "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
- "echo loading ${bootdir}/${bootfile} ...; "\
- "run loadimage;" \
- "setenv fdtdir /boot/dtbs/${uname_r}; " \
- "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
- "run loadfdt;" \
- "else " \
- "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
- "if test -e mmc ${bootpart} ${fdtdir}/" \
- "${fdtfile}; then " \
- "run loadfdt;" \
- "else " \
- "setenv fdtdir /boot/dtb-${uname_r}; " \
- "if test -e mmc ${bootpart} ${fdtdir}" \
- "/${fdtfile}; then " \
- "run loadfdt;" \
- "else " \
- "setenv fdtdir /boot/dtbs; " \
- "if test -e mmc ${bootpart} ${fdtdir}" \
- "/${fdtfile}; then " \
- "run loadfdt;" \
- "else " \
- "echo; echo unable to find " \
- "[${fdtfile}] " \
- "did you name it correctly?" \
- "echo booting fallback " \
- "[/boot/dtbs/" \
- "${uname_r}" \
- "/${fdtbase}.dtb]...;" \
- "setenv fdtdir /boot/dtbs/" \
- "${uname_r}; " \
- "setenv fdtfile " \
- "${fdtbase}.dtb; " \
- "run loadfdt;" \
- "fi;" \
- "fi;" \
- "fi;" \
- "fi;" \
- "fi; " \
- "setenv rdfile initrd.img-${uname_r}; " \
- "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
- "echo loading ${bootdir}/${rdfile} ...; "\
- "run loadrd;" \
- "if test -n ${uuid}; then " \
- "setenv mmcroot UUID=${uuid} ro;" \
- "fi;" \
- "run mmcargs;" \
- "echo debug: [${bootargs}] ... ;" \
- "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
- "${fdtaddr}] ... ;" \
- "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
- "else " \
- "run mmcargs;" \
- "echo debug: [${bootargs}] ... ;" \
- "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
-"fi;\0" \
- NANDARGS \
- DFUARGS
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "gpio set 53; " \
- "i2c mw 0x24 1 0x3e; " \
- "run findfdt; " \
- "setenv mmcdev 0; " \
- "setenv bootpart 0:1; " \
- "run mmcboot;" \
- "gpio clear 56; " \
- "gpio clear 55; " \
- "gpio clear 54; " \
- "setenv mmcdev 1; " \
- "setenv bootpart 1:1; " \
- "run mmcboot;"
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-#define CONFIG_POWER_TPS65910
-
-/* SPL */
-#ifndef CONFIG_NOR_BOOT
-/* Bootcount using the RTC block */
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-/* USB gadget RNDIS */
-#endif
-
-#ifdef CONFIG_NAND
-/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { \
- 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-/* NAND: SPL related configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
-#endif
-#endif /* !CONFIG_NAND */
-
-/*
- * For NOR boot, we must set this to the start of where NOR is mapped
- * in memory.
- */
-
-/*
- * USB configuration. We enable MUSB support, both for host and for
- * gadget. We set USB0 as peripheral and USB1 as host, based on the
- * board schematic and physical port wired to each. Then for host we
- * add mass storage support and for gadget we add both RNDIS ethernet
- * and DFU.
- */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
-/* disable host part of MUSB in SPL */
-/* disable EFI partitions and partition UUID support */
-#endif
-
-/* USB Device Firmware Update support */
-#ifndef CONFIG_SPL_BUILD
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-#ifdef CONFIG_NAND
-#define DFU_ALT_INFO_NAND \
- "dfu_alt_info_nand=" \
- "SPL part 0 1;" \
- "SPL.backup1 part 0 2;" \
- "SPL.backup2 part 0 3;" \
- "SPL.backup3 part 0 4;" \
- "u-boot part 0 5;" \
- "u-boot-spl-os part 0 6;" \
- "kernel part 0 8;" \
- "rootfs part 0 9\0"
-#else
-#define DFU_ALT_INFO_NAND ""
-#endif
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0xD80000;" \
- "fdt ram 0x80F80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-#define DFUARGS \
- "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
- DFU_ALT_INFO_MMC \
- DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_NAND
-#endif
-
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x020000 : SPL (128KiB)
- * 0x020000 - 0x0A0000 : U-Boot (512KiB)
- * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
- * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
- * 0x0E0000 - 0x442000 : Linux Kernel
- * 0x442000 - 0x800000 : Userland
- */
-#if defined(CONFIG_SPI_BOOT)
-/* SPL related */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
-#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
-#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
-#elif defined(CONFIG_EMMC_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#define CONFIG_SYS_MMC_ENV_PART 2
-#define CONFIG_ENV_OFFSET 0x0
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#endif
-
-/* SPI flash. */
-#define CONFIG_SF_DEFAULT_SPEED 24000000
-
-/* Network. */
-#define CONFIG_PHY_SMSC
-
-/*
- * NOR Size = 16 MiB
- * Number of Sectors/Blocks = 128
- * Sector Size = 128 KiB
- * Word length = 16 bits
- * Default layout:
- * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
- * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
- * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
- * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
- * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
- */
-#if defined(CONFIG_NOR)
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
-#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
-#endif
-#endif /* NOR support */
-
-#endif /* ! __CONFIG_AM335X_EVM_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 33/93] arm: Remove gurnard board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (31 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 32/93] arm: Remove birdland_bav335a board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 34/93] arm: Remove xpress_spl board Simon Glass
` (64 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 1 -
board/bluewater/gurnard/Kconfig | 12 -
board/bluewater/gurnard/MAINTAINERS | 6 -
board/bluewater/gurnard/Makefile | 9 -
board/bluewater/gurnard/gurnard.c | 423 ----
board/bluewater/gurnard/splash_logo.h | 2619 -------------------------
configs/gurnard_defconfig | 38 -
include/configs/snapper9g45.h | 112 --
8 files changed, 3220 deletions(-)
delete mode 100644 board/bluewater/gurnard/Kconfig
delete mode 100644 board/bluewater/gurnard/MAINTAINERS
delete mode 100644 board/bluewater/gurnard/Makefile
delete mode 100644 board/bluewater/gurnard/gurnard.c
delete mode 100644 board/bluewater/gurnard/splash_logo.h
delete mode 100644 configs/gurnard_defconfig
delete mode 100644 include/configs/snapper9g45.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a6329dc0220..0fe93263ba8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -278,7 +278,6 @@ source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
-source "board/bluewater/gurnard/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig
deleted file mode 100644
index e2cd9f00df8..00000000000
--- a/board/bluewater/gurnard/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_GURNARD
-
-config SYS_BOARD
- default "gurnard"
-
-config SYS_VENDOR
- default "bluewater"
-
-config SYS_CONFIG_NAME
- default "snapper9g45"
-
-endif
diff --git a/board/bluewater/gurnard/MAINTAINERS b/board/bluewater/gurnard/MAINTAINERS
deleted file mode 100644
index 5e546d43fb4..00000000000
--- a/board/bluewater/gurnard/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GURNARD BOARD
-M: Simon Glass <sjg@chromium.org>
-S: Maintained
-F: board/bluewater/gurnard/
-F: include/configs/snapper9g45.h
-F: configs/gurnard_defconfig
diff --git a/board/bluewater/gurnard/Makefile b/board/bluewater/gurnard/Makefile
deleted file mode 100644
index 8218e2cd58b..00000000000
--- a/board/bluewater/gurnard/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2011 Bluewater Systems
-# Ryan Mallon <ryan@bluewatersys.com>
-
-obj-y += gurnard.o
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
deleted file mode 100644
index 3cda2fafab2..00000000000
--- a/board/bluewater/gurnard/gurnard.c
+++ /dev/null
@@ -1,423 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluewater Systems Snapper 9260/9G20 modules
- *
- * (C) Copyright 2011 Bluewater Systems
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
- */
-
-#include <common.h>
-#include <atmel_lcd.h>
-#include <atmel_lcdc.h>
-#include <atmel_mci.h>
-#include <dm.h>
-#include <lcd.h>
-#include <net.h>
-#ifndef CONFIG_DM_ETH
-#include <netdev.h>
-#endif
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/at91sam9g45_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_emac.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_rtc.h>
-#include <asm/arch/at91_sck.h>
-#include <asm/arch/atmel_serial.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <dm/uclass-internal.h>
-
-#ifdef CONFIG_GURNARD_SPLASH
-#include "splash_logo.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* IO Expander pins */
-#define IO_EXP_ETH_RESET (0 << 1)
-#define IO_EXP_ETH_POWER (1 << 1)
-
-#ifdef CONFIG_MACB
-static void gurnard_macb_hw_init(void)
-{
- struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
- at91_periph_clk_enable(ATMEL_ID_EMAC);
-
- /*
- * Enable pull-up on:
- * RXDV (PA12) => MODE0 - PHY also has pull-up
- * ERX0 (PA13) => MODE1 - PHY also has pull-up
- * ERX1 (PA15) => MODE2 - PHY also has pull-up
- */
- writel(pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA12) |
- pin_to_mask(AT91_PIN_PA13),
- &pioa->puer);
-
- at91_phy_reset();
-
- at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_CMD_NAND
-static int gurnard_nand_hw_init(void)
-{
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- ulong flags;
- int ret;
-
- /* Enable CS3 as NAND/SmartMedia */
- setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
- &smc->cs[3].cycle);
-#ifdef CONFIG_SYS_NAND_DBW_16
- flags = AT91_SMC_MODE_DBW_16;
-#else
- flags = AT91_SMC_MODE_DBW_8;
-#endif
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- flags |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-
- ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
- if (ret)
- return ret;
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
- if (ret)
- return ret;
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_GURNARD_SPLASH
-static void lcd_splash(int width, int height)
-{
- u16 colour;
- int x, y;
- u16 *base_addr = (u16 *)gd->video_bottom;
-
- memset(base_addr, 0xff, width * height * 2);
- /*
- * Blit the logo to the center of the screen
- */
- for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
- for (x = 0; x < BMP_LOGO_WIDTH; x++) {
- int posx, posy;
- colour = bmp_logo_palette[bmp_logo_bitmap[
- y * BMP_LOGO_WIDTH + x]];
- posx = x + (width - BMP_LOGO_WIDTH) / 2;
- posy = y;
- base_addr[posy * width + posx] = colour;
- }
- }
-}
-#endif
-
-#ifdef CONFIG_DM_VIDEO
-static void at91sam9g45_lcd_hw_init(void)
-{
- at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
- at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
- at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
- at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
- at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
-
- at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
- at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
- at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
- at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
- at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
- at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
- at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
- at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
- at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
- at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
- at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
- at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
- at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
- at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
- at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
- at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
- at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
- at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
- at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
- at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
- at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
- at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
- at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
- at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
-
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-#endif
-
-#ifdef CONFIG_GURNARD_FPGA
-/**
- * Initialise the memory bus settings so that we can talk to the
- * memory mapped FPGA
- */
-static int fpga_hw_init(void)
-{
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- int i;
-
- setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
-
- at91_set_a_periph(2, 4, 0); /* EBIA21 */
- at91_set_a_periph(2, 5, 0); /* EBIA22 */
- at91_set_a_periph(2, 6, 0); /* EBIA23 */
- at91_set_a_periph(2, 7, 0); /* EBIA24 */
- at91_set_a_periph(2, 12, 0); /* EBIA25 */
- for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
- at91_set_a_periph(2, i, 0);
-
- /* configure SMC cs0 for FPGA access timing */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
- &smc->cs[0].setup);
- writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[0].pulse);
- writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
- &smc->cs[0].cycle);
- writel(AT91_SMC_MODE_BAT |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_32 |
- AT91_SMC_MODE_TDF |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[0].mode);
-
- /* Do a write to within EBI_CS1 to enable the SDCK */
- writel(0, ATMEL_BASE_CS1);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_USB
-
-#define USB0_ENABLE_PIN AT91_PIN_PB22
-#define USB1_ENABLE_PIN AT91_PIN_PB23
-
-void gurnard_usb_init(void)
-{
- at91_set_gpio_output(USB0_ENABLE_PIN, 1);
- at91_set_gpio_value(USB0_ENABLE_PIN, 0);
- at91_set_gpio_output(USB1_ENABLE_PIN, 1);
- at91_set_gpio_value(USB1_ENABLE_PIN, 0);
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int cpu_mmc_init(bd_t *bis)
-{
- return atmel_mci_init((void *)ATMEL_BASE_MCI0);
-}
-#endif
-
-static void gurnard_enable_console(int enable)
-{
- at91_set_gpio_output(AT91_PIN_PB14, 1);
- at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
-}
-
-void at91sam9g45_slowclock_init(void)
-{
- /*
- * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
- * internal impreciseRC oscillator or an external 32kHz oscillator.
- * Switch to the latter.
- */
- unsigned i, tmp;
- ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
-
- tmp = readl(reg);
- if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
- timer_init();
- tmp |= AT91SAM9G45_SCKCR_OSC32EN;
- writel(tmp, reg);
- for (i = 0; i < 1200; i++)
- udelay(1000);
- tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
- writel(tmp, reg);
- udelay(200);
- tmp &= ~AT91SAM9G45_SCKCR_RCEN;
- writel(tmp, reg);
- }
-}
-
-int board_early_init_f(void)
-{
- at91_seriald_hw_init();
- gurnard_enable_console(1);
-
- return 0;
-}
-
-int board_init(void)
-{
- const char *rev_str;
-#ifdef CONFIG_CMD_NAND
- int ret;
-#endif
-
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIODE);
-
- at91sam9g45_slowclock_init();
-
- /*
- * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
- * boots with spurious IRQs.
- */
- writel(0xffffffff, AT91_RTC_IDR);
-
- /* Make sure that the reset signal is attached properly */
- setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
-
- gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
-
- /* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- ret = gurnard_nand_hw_init();
- if (ret)
- return ret;
-#endif
-#ifdef CONFIG_ATMEL_SPI
- at91_spi0_hw_init(1 << 4);
-#endif
-
-#ifdef CONFIG_MACB
- gurnard_macb_hw_init();
-#endif
-
-#ifdef CONFIG_GURNARD_FPGA
- fpga_hw_init();
-#endif
-
-#ifdef CONFIG_CMD_USB
- gurnard_usb_init();
-#endif
-
-#ifdef CONFIG_CMD_MMC
- at91_set_A_periph(AT91_PIN_PA12, 0);
- at91_set_gpio_output(AT91_PIN_PA8, 1);
- at91_set_gpio_value(AT91_PIN_PA8, 0);
- at91_mci_hw_init();
-#endif
-
-#ifdef CONFIG_DM_VIDEO
- at91sam9g45_lcd_hw_init();
- at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
-
- /* Select the second timing index for board rev 2 */
- rev_str = env_get("board_rev");
- if (rev_str && !strncmp(rev_str, "2", 1)) {
- struct udevice *dev;
-
- uclass_find_first_device(UCLASS_VIDEO, &dev);
- if (dev) {
- struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
-
- plat->timing_index = 1;
- }
- }
-#endif
-
- return 0;
-}
-
-int board_late_init(void)
-{
- u_int8_t env_enetaddr[8];
- char *env_str;
- char *end;
- int i;
-
- /*
- * Set MAC address so we do not need to init Ethernet before Linux
- * boot
- */
- env_str = env_get("ethaddr");
- if (env_str) {
- struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
- /* Parse MAC address */
- for (i = 0; i < 6; i++) {
- env_enetaddr[i] = env_str ?
- simple_strtoul(env_str, &end, 16) : 0;
- if (env_str)
- env_str = (*end) ? end+1 : end;
- }
-
- /* Set hardware address */
- writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
- env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
- &emac->sa2l);
- writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
-
- printf("MAC: %s\n", env_get("ethaddr"));
- } else {
- /* Not set in environment */
- printf("MAC: not set\n");
- }
-#ifdef CONFIG_GURNARD_SPLASH
- lcd_splash(480, 272);
-#endif
-
- return 0;
-}
-
-#ifndef CONFIG_DM_ETH
-int board_eth_init(bd_t *bis)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-void reset_phy(void)
-{
-}
-
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
- .base_addr = ATMEL_BASE_DBGU,
-};
-
-U_BOOT_DEVICE(at91sam9260_serial) = {
- .name = "serial_atmel",
- .platdata = &at91sam9260_serial_plat,
-};
diff --git a/board/bluewater/gurnard/splash_logo.h b/board/bluewater/gurnard/splash_logo.h
deleted file mode 100644
index fb87dea86cf..00000000000
--- a/board/bluewater/gurnard/splash_logo.h
+++ /dev/null
@@ -1,2619 +0,0 @@
-/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/
-#ifndef __BMP_LOGO_H__
-#define __BMP_LOGO_H__
-#define BMP_LOGO_WIDTH 187
-#define BMP_LOGO_HEIGHT 139
-#define BMP_LOGO_COLORS 255
-#define BMP_LOGO_OFFSET 50
-
-unsigned short bmp_logo_palette[] = {
- 0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e,
- 0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7,
- 0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf,
- 0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d,
- 0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410,
- 0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe,
- 0xffff, 0xef3c, };
-
-unsigned char bmp_logo_bitmap[] = {
- 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
- 0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
- 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
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- 0x000e, 0x000e, 0x0009, };
-#endif
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
deleted file mode 100644
index 3c3537a77b5..00000000000
--- a/configs/gurnard_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x73f00000
-CONFIG_TARGET_GURNARD=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_NAND=y
-CONFIG_NAND_ATMEL=y
-CONFIG_PHYLIB=y
-CONFIG_TIMER=y
-CONFIG_ATMEL_PIT_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_DM_VIDEO=y
-CONFIG_CMD_DHRYSTONE=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
deleted file mode 100644
index f2c47dabc5c..00000000000
--- a/include/configs/snapper9g45.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Bluewater Systems Snapper 9G45 module
- *
- * (C) Copyright 2011 Bluewater Systems
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SoC type is defined in boards.cfg */
-#include <asm/hardware.h>
-#include <linux/sizes.h>
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-
-/* CPU */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/* Mem test settings */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
-
-/* NAND Flash */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_RESET_PHY_R
-#define CONFIG_AT91_WANTS_COMMON_PHY
-#define CONFIG_TFTP_PORT
-#define CONFIG_TFTP_TSIZE
-
-/* MMC */
-#define CONFIG_GENERIC_ATMEL_MCI
-
-/* LCD */
-#define CONFIG_ATMEL_LCD
-#define CONFIG_GURNARD_SPLASH
-
-/* GPIOs and IO expander */
-#define CONFIG_ATMEL_LEGACY
-#define CONFIG_AT91_GPIO
-#define CONFIG_AT91_GPIO_PULLUP 1
-
-/* UARTs/Serial console */
-#define CONFIG_ATMEL_USART
-
-/* Boot options */
-#define CONFIG_SYS_LOAD_ADDR 0x23000000
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Environment settings */
-#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ethaddr=00:00:00:00:00:00\0" \
- "serial=0\0" \
- "stdout=serial_atmel\0" \
- "stderr=serial_atmel\0" \
- "stdin=serial_atmel\0" \
- "bootlimit=3\0" \
- "loadaddr=0x71000000\0" \
- "board_rev=2\0" \
- "bootfile=/tftpboot/uImage\0" \
- "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
- "nfsroot=/export/root\0" \
- "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
- "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
- "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
- "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
- "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
- "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
- "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
-
-/* Console settings */
-
-/* U-Boot memory settings */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-
-/* Command line configuration */
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_CACHE
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 34/93] arm: Remove xpress_spl board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (32 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 33/93] arm: Remove gurnard board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 35/93] arm: Remove udoo_neo board Simon Glass
` (63 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/ccv/xpress/Kconfig | 12 --
board/ccv/xpress/MAINTAINERS | 7 -
board/ccv/xpress/Makefile | 6 -
board/ccv/xpress/imximage.cfg | 175 ------------------
board/ccv/xpress/spl.c | 117 ------------
board/ccv/xpress/xpress.c | 336 ----------------------------------
configs/xpress_defconfig | 32 ----
configs/xpress_spl_defconfig | 42 -----
include/configs/xpress.h | 135 --------------
10 files changed, 863 deletions(-)
delete mode 100644 board/ccv/xpress/Kconfig
delete mode 100644 board/ccv/xpress/MAINTAINERS
delete mode 100644 board/ccv/xpress/Makefile
delete mode 100644 board/ccv/xpress/imximage.cfg
delete mode 100644 board/ccv/xpress/spl.c
delete mode 100644 board/ccv/xpress/xpress.c
delete mode 100644 configs/xpress_defconfig
delete mode 100644 configs/xpress_spl_defconfig
delete mode 100644 include/configs/xpress.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 194e8d855fc..3f0d27b76dd 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -529,7 +529,6 @@ source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/bticino/mamoj/Kconfig"
-source "board/ccv/xpress/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
diff --git a/board/ccv/xpress/Kconfig b/board/ccv/xpress/Kconfig
deleted file mode 100644
index 9157013c306..00000000000
--- a/board/ccv/xpress/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPRESS
-
-config SYS_BOARD
- default "xpress"
-
-config SYS_VENDOR
- default "ccv"
-
-config SYS_CONFIG_NAME
- default "xpress"
-
-endif
diff --git a/board/ccv/xpress/MAINTAINERS b/board/ccv/xpress/MAINTAINERS
deleted file mode 100644
index e242bfb2065..00000000000
--- a/board/ccv/xpress/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-CCV XPRESS BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/ccv/xpress/
-F: include/configs/xpress.h
-F: configs/xpress_defconfig
-F: configs/xpress_spl_defconfig
diff --git a/board/ccv/xpress/Makefile b/board/ccv/xpress/Makefile
deleted file mode 100644
index b750b6ae498..00000000000
--- a/board/ccv/xpress/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
-
-obj-y := xpress.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
deleted file mode 100644
index be7e391ddbe..00000000000
--- a/board/ccv/xpress/imximage.cfg
+++ /dev/null
@@ -1,175 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * sd, nand
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-/* Enable all clocks */
-DATA 4 0x020c4068 0xffffffff
-DATA 4 0x020c406c 0xffffffff
-DATA 4 0x020c4070 0xffffffff
-DATA 4 0x020c4074 0xffffffff
-DATA 4 0x020c4078 0xffffffff
-DATA 4 0x020c407c 0xffffffff
-DATA 4 0x020c4080 0xffffffff
-DATA 4 0x020c4084 0xffffffff
-
-/* ddr io type */
-DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
-DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
-
-/* clock */
-DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
-
-/* control and address */
-DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
-DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
-DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
-DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
-DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
- configured using Group Control Register:
- IOMUXC_SW_PAD_CTL_GRP_CTLDS */
-DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
-DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
-DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
-
-/* data strobes */
-DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
-DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
-DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
-
-/* data */
-DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
-DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
-DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
-DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
-DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
-
-/*
- * DDR Controller Registers
- *
- * Manufacturer: IM
- * Device Part Number: IME1G16D3EEBG-15EI
- * Clock Freq.: 400MHz
- * Density per CS in Gb: 1
- * Chip Selects used: 1
- * Number of Banks: 8
- * Row address: 13
- * Column address: 10
- * Data bus width 16
- */
-DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
- during MMDC set up */
-
-/*
- * Calibration setup
- */
-DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
- periodic HW ZQ calibration. */
-
-/*
- * For target board, may need to run write leveling calibration to fine tune
- * these settings.
- */
-DATA 4 0x021b080c 0x00000000
-
-/* Read DQS Gating calibration */
-DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
-
-/* Read calibration */
-DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
-
-/* Write calibration */
-DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
-
-/*
- * read data bit delay: (3 is the reccommended default value, although out of
- * reset value is 0)
- */
-DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
-DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
-DATA 4 0x021b082c 0xF3333333
-DATA 4 0x021b0830 0xF3333333
-
-DATA 4 0x021b08c0 0x00921012
-
-/* Clock Fine Tuning */
-DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
-
-/* Complete calibration by forced measurement: */
-DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
-/*
- * Calibration setup end
- */
-
-/* MMDC init: */
-DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
-DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
-DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
-DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
-DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
-
-/*
- * MDMISC: RALAT kept to the high level of 5.
- * MDMISC: consider reducing RALAT if your 528MHz board design allow that.
- * Lower RALAT benefits:
- * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
- * to 3
- * b. Small performence improvment
- */
-DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
-
-DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
- during MMDC set up */
-
-DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
-DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
-DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
-DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
-
-/* Mode register writes */
-DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
-DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
-DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
-DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
-DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
- device on CS0 */
-
-DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
-DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
-DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
-DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
- enter automatically to self-refresh while the
- number of idle cycle reached. */
-DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
- the configuration bit as initialization is
- complete) */
diff --git a/board/ccv/xpress/spl.c b/board/ccv/xpress/spl.c
deleted file mode 100644
index 90f655ab2e7..00000000000
--- a/board/ccv/xpress/spl.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL specific code for CCV xPress
- *
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/crm_regs.h>
-
-/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000030,
- .dram_dqm1 = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_odt0 = 0x00000030,
- .dram_odt1 = 0x00000030,
- .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000008,
- .dram_sdqs0 = 0x00000038,
- .dram_sdqs1 = 0x00000030,
- .dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x4164015C,
- .p0_mprddlctl = 0x40404446,
- .p0_mpwrdlctl = 0x40405A52,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 800,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 13,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
- writel(0xFFFFFFFF, &ccm->CCGR7);
-}
-
-static void spl_dram_init(void)
-{
- mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
- /* Setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
-
- /* Setup iomux and i2c */
- board_early_init_f();
-
- /* Setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c
deleted file mode 100644
index dcf5e1448f6..00000000000
--- a/board/ccv/xpress/xpress.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6ul_pins.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-
-#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_FAST)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
- .gp = IMX_GPIO_NR(1, 2),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3),
- },
-};
-
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-
-static struct i2c_pads_info i2c_pad_info4 = {
- .scl = {
- .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
- .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
- .gp = IMX_GPIO_NR(1, 20),
- },
- .sda = {
- .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
- .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
- .gp = IMX_GPIO_NR(1, 21),
- },
-};
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart4_pads[] = {
- MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart5_pads[] = {
- MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart7_pads[] = {
- MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart8_pads[] = {
- MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
- imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
- imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
- imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
-}
-
-/* eMMC on USDHC2 */
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /*
- * RST_B
- */
- MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg = {
- .esdhc_base = USDHC2_BASE_ADDR,
- .max_bus_width = 8,
-};
-
-#define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* eMMC is always present */
- return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg);
-}
-
-#define USB_OTHERREGS_OFFSET 0x800
-#define UCTRL_PWR_POL (1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OTG1 */
- MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
-};
-
-static void setup_usb(void)
-{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
- u32 *usbnc_usb_ctrl;
-
- if (port > 1)
- return -EINVAL;
-
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
-
- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
- return 0;
-}
-
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-
- /* ENET1 reset */
- MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* ENET1 interrupt */
- MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
-
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
- /* Reset LAN8742 PHY */
- ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
- if (!ret)
- gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
- mdelay(10);
- gpio_set_value(ENET_PHY_RESET_GPIO, 1);
- mdelay(10);
-
- return cpu_eth_init(bis);
-}
-
-static int setup_fec(int fec_id)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
-
- /*
- * Use 50M anatop loopback REF_CLK1 for ENET1,
- * clear gpr1[13], set gpr1[17].
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
- IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
-
- ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
- if (ret)
- return ret;
-
- enable_enet_clk(1);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
-
- setup_fec(CONFIG_FEC_ENET_DEV);
-
- setup_usb();
-
- return 0;
-}
-
-static const struct boot_mode board_boot_modes[] = {
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
- { NULL, 0 },
-};
-
-int board_late_init(void)
-{
- add_board_boot_modes(board_boot_modes);
- env_set("board_name", "xpress");
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: CCV-EVA xPress\n");
-
- return 0;
-}
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
deleted file mode 100644
index caf0f6165aa..00000000000
--- a/configs/xpress_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_TARGET_XPRESS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
deleted file mode 100644
index 7eefa92fc51..00000000000
--- a/configs/xpress_spl_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_XPRESS=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
deleted file mode 100644
index 08e0ca0c8f1..00000000000
--- a/include/configs/xpress.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- *
- * Configuration settings for the CCV xPress board
- */
-#ifndef __XPRESS_CONFIG_H
-#define __XPRESS_CONFIG_H
-
-#include "mx6_common.h"
-#include <asm/mach-imx/gpio.h>
-
-/* SPL options */
-#include "imx6_spl.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-/* I2C configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE (128 << 20)
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment is in stored in the eMMC boot partition */
-#define CONFIG_ENV_SIZE (16 << 10)
-#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
-#define CONFIG_SYS_MMC_ENV_PART 1 /* boot parition */
-#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */
-
-/* USB Configs */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_ENET_DEV 0
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_PHY_SMSC
-
-#define CONFIG_IMX_THERMAL
-
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_UBOOT_SECTOR_START 0x2
-#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc6\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=undefined\0" \
- "fdt_addr=0x83000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "uboot=ccv/u-boot.imx\0" \
- "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \
- "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \
- "update_uboot=if tftp ${uboot}; then " \
- "if itest ${filesize} > 0; then " \
- "mmc dev 0 1;" \
- "setexpr blkc ${filesize} / 0x200;" \
- "setexpr blkc ${blkc} + 1;" \
- "if itest ${blkc} <= ${uboot_size}; then " \
- "mmc write ${loadaddr} ${uboot_start} " \
- "${blkc};" \
- "fi;" \
- "fi; fi;" \
- "setenv filesize; setenv blkc\0" \
- "update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0"
-
-#endif /* __XPRESS_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 35/93] arm: Remove udoo_neo board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (33 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 34/93] arm: Remove xpress_spl board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 36/93] arm: Remove nas220 board Simon Glass
` (62 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/udoo/neo/Kconfig | 12 -
board/udoo/neo/MAINTAINERS | 7 -
board/udoo/neo/Makefile | 4 -
board/udoo/neo/neo.c | 595 ----------------------------------
configs/udoo_neo_defconfig | 33 --
include/configs/udoo_neo.h | 106 ------
7 files changed, 758 deletions(-)
delete mode 100644 board/udoo/neo/Kconfig
delete mode 100644 board/udoo/neo/MAINTAINERS
delete mode 100644 board/udoo/neo/Makefile
delete mode 100644 board/udoo/neo/neo.c
delete mode 100644 configs/udoo_neo_defconfig
delete mode 100644 include/configs/udoo_neo.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 3f0d27b76dd..8169bfb18e6 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -558,7 +558,6 @@ source "board/tqc/tqma6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
source "board/k+p/kp_imx6q_tpc/Kconfig"
source "board/udoo/Kconfig"
-source "board/udoo/neo/Kconfig"
source "board/warp/Kconfig"
endif
diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig
deleted file mode 100644
index 8f474df2487..00000000000
--- a/board/udoo/neo/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_UDOO_NEO
-
-config SYS_VENDOR
- default "udoo"
-
-config SYS_BOARD
- default "neo"
-
-config SYS_CONFIG_NAME
- default "udoo_neo"
-
-endif
diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS
deleted file mode 100644
index 743fe33d059..00000000000
--- a/board/udoo/neo/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-UDOO NEO BOARD
-M: Breno Lima <breno.lima@nxp.com>
-M: Francesco Montefoschi <francesco.montefoschi@udoo.org>
-S: Maintained
-F: board/udoo/neo/
-F: include/configs/udoo_neo.h
-F: configs/udoo_neo_defconfig
diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile
deleted file mode 100644
index 831c084ce59..00000000000
--- a/board/udoo/neo/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2015 UDOO Team
-
-obj-y := neo.o
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
deleted file mode 100644
index 828161360cb..00000000000
--- a/board/udoo/neo/neo.c
+++ /dev/null
@@ -1,595 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
- * Copyright (C) Jasbir Matharu
- * Copyright (C) UDOO Team
- *
- * Author: Breno Lima <breno.lima@nxp.com>
- * Author: Francesco Montefoschi <francesco.monte@gmail.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-#include <linux/sizes.h>
-#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <power/pmic.h>
-#include <power/pfuze3000_pmic.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum {
- UDOO_NEO_TYPE_BASIC,
- UDOO_NEO_TYPE_BASIC_KS,
- UDOO_NEO_TYPE_FULL,
- UDOO_NEO_TYPE_EXTENDED,
-};
-
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
-
-#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm)
-
-#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
- MUX_MODE_SION)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-#endif
-
-#ifdef CONFIG_POWER
-int power_init_board(void)
-{
- struct pmic *p;
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE3000");
- ret = pmic_probe(p);
- if (ret)
- return ret;
-
- pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
-
- /* disable Low Power Mode during standby mode */
- pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
- reg |= 0x1;
- ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
- if (ret)
- return ret;
-
- ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
- if (ret)
- return ret;
-
- ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
- if (ret)
- return ret;
-
- ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
- if (ret)
- return ret;
-
- ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
- if (ret)
- return ret;
-
- /* set SW1A standby voltage 0.975V */
- pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(9750);
- ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
- if (ret)
- return ret;
-
- /* set SW1B standby voltage 0.975V */
- pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(9750);
- ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
- if (ret)
- return ret;
-
- /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
- if (ret)
- return ret;
-
- /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
- if (ret)
- return ret;
-
- /* set VDD_ARM_IN to 1.350V */
- pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(13500);
- ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
- if (ret)
- return ret;
-
- /* set VDD_SOC_IN to 1.350V */
- pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
- reg &= ~0x3f;
- reg |= PFUZE3000_SW1AB_SETP(13500);
- ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
- if (ret)
- return ret;
-
- /* set DDR_1_5V to 1.350V */
- pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
- reg &= ~0x0f;
- reg |= PFUZE3000_SW3_SETP(13500);
- ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
- if (ret)
- return ret;
-
- /* set VGEN2_1V5 to 1.5V */
- pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®);
- reg &= ~0x0f;
- reg |= PFUZE3000_VLDO_SETP(15000);
- /* enable */
- reg |= 0x10;
- ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
- if (ret)
- return ret;
-
- return 0;
-}
-#endif
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD pin */
- MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* Power */
- MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const phy_control_pads[] = {
- /* 25MHz Ethernet PHY Clock */
- MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
- MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const board_recognition_pads[] = {
- /*Connected to R184*/
- MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
- /*Connected to R185*/
- MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
-};
-
-static iomux_v3_cfg_t const wdog_b_pad = {
- MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const peri_3v3_pads[] = {
- MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-static int setup_fec(int fec_id)
-{
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg;
-
- imx_iomux_v3_setup_multiple_pads(phy_control_pads,
- ARRAY_SIZE(phy_control_pads));
-
- /* Reset PHY */
- gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(2, 1), 1);
- udelay(100);
-
- reg = readl(&anatop->pll_enet);
- reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
- writel(reg, &anatop->pll_enet);
-
- return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
-}
-
-int board_eth_init(bd_t *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
- setup_fec(CONFIG_FEC_ENET_DEV);
-
- bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
- if (!bus)
- return -EINVAL;
-
- phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
- PHY_INTERFACE_MODE_RMII);
- if (!phydev) {
- free(bus);
- return -EINVAL;
- }
-
- ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
- if (ret) {
- free(bus);
- free(phydev);
- return ret;
- }
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /*
- * Because kernel set WDOG_B mux before pad with the commone pinctrl
- * framwork now and wdog reset will be triggered once set WDOG_B mux
- * with default pad setting, we set pad setting here to workaround this.
- * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
- * as GPIO mux firstly here to workaround it.
- */
- imx_iomux_v3_setup_pad(wdog_b_pad);
-
- /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
- imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
- ARRAY_SIZE(peri_3v3_pads));
-
- /* Active high for ncp692 */
- gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
-
- return 0;
-}
-
-static int get_board_value(void)
-{
- int r184, r185;
-
- imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
- ARRAY_SIZE(board_recognition_pads));
-
- gpio_direction_input(IMX_GPIO_NR(4, 13));
- gpio_direction_input(IMX_GPIO_NR(4, 0));
-
- r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
- r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
-
- /*
- * Machine selection -
- * Machine r184, r185
- * ---------------------------------
- * Basic 0 0
- * Basic Ks 0 1
- * Full 1 0
- * Extended 1 1
- */
-
- return (r184 << 1) + r185;
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR, 0, 4},
-};
-
-#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
-#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !gpio_get_value(USDHC2_CD_GPIO);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- gpio_direction_input(USDHC2_CD_GPIO);
- gpio_direction_output(USDHC2_PWR_GPIO, 1);
-
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-static char *board_string(void)
-{
- switch (get_board_value()) {
- case UDOO_NEO_TYPE_BASIC:
- return "BASIC";
- case UDOO_NEO_TYPE_BASIC_KS:
- return "BASICKS";
- case UDOO_NEO_TYPE_FULL:
- return "FULL";
- case UDOO_NEO_TYPE_EXTENDED:
- return "EXTENDED";
- }
- return "UNDEFINED";
-}
-
-int checkboard(void)
-{
- printf("Board: UDOO Neo %s\n", board_string());
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", board_string());
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-
-#include <linux/libfdt.h>
-#include <asm/arch/mx6-ddr.h>
-
-static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_dqm0 = 0x00000028,
- .dram_dqm1 = 0x00000028,
- .dram_dqm2 = 0x00000028,
- .dram_dqm3 = 0x00000028,
- .dram_ras = 0x00000020,
- .dram_cas = 0x00000020,
- .dram_odt0 = 0x00000020,
- .dram_odt1 = 0x00000020,
- .dram_sdba2 = 0x00000000,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00000028,
- .dram_sdqs1 = 0x00000028,
- .dram_sdqs2 = 0x00000028,
- .dram_sdqs3 = 0x00000028,
- .dram_reset = 0x00000020,
-};
-
-static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000020,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000028,
- .grp_b1ds = 0x00000028,
- .grp_ctlds = 0x00000020,
- .grp_ddr_type = 0x000c0000,
- .grp_b2ds = 0x00000028,
- .grp_b3ds = 0x00000028,
-};
-
-static const struct mx6_mmdc_calibration neo_mmcd_calib = {
- .p0_mpwldectrl0 = 0x000E000B,
- .p0_mpwldectrl1 = 0x000E0010,
- .p0_mpdgctrl0 = 0x41600158,
- .p0_mpdgctrl1 = 0x01500140,
- .p0_mprddlctl = 0x3A383E3E,
- .p0_mpwrdlctl = 0x3A383C38,
-};
-
-static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
- .p0_mpwldectrl0 = 0x001E0022,
- .p0_mpwldectrl1 = 0x001C0019,
- .p0_mpdgctrl0 = 0x41540150,
- .p0_mpdgctrl1 = 0x01440138,
- .p0_mprddlctl = 0x403E4644,
- .p0_mpwrdlctl = 0x3C3A4038,
-};
-
-/* MT41K256M16 */
-static struct mx6_ddr3_cfg neo_mem_ddr = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* MT41K128M16 */
-static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0xFFFFFFFF, &ccm->CCGR0);
- writel(0xFFFFFFFF, &ccm->CCGR1);
- writel(0xFFFFFFFF, &ccm->CCGR2);
- writel(0xFFFFFFFF, &ccm->CCGR3);
- writel(0xFFFFFFFF, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0xFFFFFFFF, &ccm->CCGR6);
- writel(0xFFFFFFFF, &ccm->CCGR7);
-}
-
-static void spl_dram_init(void)
-{
- int board = get_board_value();
-
- struct mx6_ddr_sysinfo sysinfo = {
- .dsize = 1, /* width of data bus: 1 = 32 bits */
- .cs_density = 24,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- };
-
- mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
- mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
- &neo_basic_mem_ddr);
- else
- mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-
-#endif
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
deleted file mode 100644
index de0e03726b8..00000000000
--- a/configs/udoo_neo_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_UDOO_NEO=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_MII=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
deleted file mode 100644
index 6ba4270b72d..00000000000
--- a/include/configs/udoo_neo.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright Jasbir Matharu
- * Copyright 2015 UDOO Team
- *
- * Configuration settings for the UDOO NEO board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#include "imx6_spl.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
-#define CONFIG_MXC_UART
-
-/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-
-/* Command definition */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/
-
-/* Linux only */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdtfile=undefined\0" \
- "fdt_addr=0x83000000\0" \
- "fdt_addr_r=0x83000000\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcrootfstype=ext4\0" \
- "findfdt="\
- "if test $board_name = BASIC; then " \
- "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
- "if test $board_name = BASICKS; then " \
- "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
- "if test $board_name = FULL; then " \
- "setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \
- "if test $board_name = EXTENDED; then " \
- "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
- "if test $fdtfile = UNDEFINED; then " \
- "echo WARNING: Could not determine dtb to use; fi\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_addr_r=0x84000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_OFFSET (8 * SZ_64K)
-#define CONFIG_ENV_SIZE SZ_8K
-
-#define CONFIG_IMX_THERMAL
-
-/* I2C configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-#define PFUZE3000_I2C_BUS 0
-
-/* Network */
-#define CONFIG_FEC_MXC
-
-#define CONFIG_FEC_ENET_DEV 0
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x0
-
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC0"
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 36/93] arm: Remove nas220 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (34 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 35/93] arm: Remove udoo_neo board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-21 15:26 ` Evgeni Dobrev
2018-11-19 15:53 ` [U-Boot] [PATCH 37/93] arm: Remove am335x_pdu001 board Simon Glass
` (61 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/Seagate/nas220/Kconfig | 12 ---
board/Seagate/nas220/MAINTAINERS | 6 --
board/Seagate/nas220/Makefile | 7 --
board/Seagate/nas220/kwbimage.cfg | 151 ------------------------------
board/Seagate/nas220/nas220.c | 118 -----------------------
configs/nas220_defconfig | 42 ---------
include/configs/nas220.h | 112 ----------------------
8 files changed, 449 deletions(-)
delete mode 100644 board/Seagate/nas220/Kconfig
delete mode 100644 board/Seagate/nas220/MAINTAINERS
delete mode 100644 board/Seagate/nas220/Makefile
delete mode 100644 board/Seagate/nas220/kwbimage.cfg
delete mode 100644 board/Seagate/nas220/nas220.c
delete mode 100644 configs/nas220_defconfig
delete mode 100644 include/configs/nas220.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 63fd39881ed..d4afdaccd3b 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -82,7 +82,6 @@ source "board/LaCie/netspace_v2/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
-source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
diff --git a/board/Seagate/nas220/Kconfig b/board/Seagate/nas220/Kconfig
deleted file mode 100644
index 0fa529cde11..00000000000
--- a/board/Seagate/nas220/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_NAS220
-
-config SYS_BOARD
- default "nas220"
-
-config SYS_VENDOR
- default "Seagate"
-
-config SYS_CONFIG_NAME
- default "nas220"
-
-endif
diff --git a/board/Seagate/nas220/MAINTAINERS b/board/Seagate/nas220/MAINTAINERS
deleted file mode 100644
index f2df7ea64f2..00000000000
--- a/board/Seagate/nas220/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-NAS220 BOARD
-M: Evgeni Dobrev <evgeni@studio-punkt.com>
-S: Maintained
-F: board/Seagate/nas220/
-F: include/configs/nas220.h
-F: configs/nas220_defconfig
diff --git a/board/Seagate/nas220/Makefile b/board/Seagate/nas220/Makefile
deleted file mode 100644
index 9de73e6f5ea..00000000000
--- a/board/Seagate/nas220/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := nas220.o
diff --git a/board/Seagate/nas220/kwbimage.cfg b/board/Seagate/nas220/kwbimage.cfg
deleted file mode 100644
index dbbfb9c0204..00000000000
--- a/board/Seagate/nas220/kwbimage.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
-#
-# Based on sheevaplug/kwbimage.cfg originally written by
-# Prafulla Wadaskar <prafulla@marvell.com>
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0200
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-
-DATA 0xFFD01410 0x0000000d # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 0
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-DATA 0xffd01620 0x00465000
-
-# End of Header extension
-DATA 0x0 0x0
-
diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c
deleted file mode 100644
index 1e6c43b1fab..00000000000
--- a/board/Seagate/nas220/nas220.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
- *
- * Based on sheevaplug.c originally written by
- * Prafulla Wadaskar <prafulla@marvell.com>
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- */
- mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
- NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_SPI_SCn,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO,
- MPP13_GPIO,
- MPP14_GPIO,
- MPP15_SATA0_ACTn,
- MPP16_SATA1_ACTn,
- MPP17_SATA0_PRESENTn,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
- printf("Err..%s could not read PHY dev address\n", __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
deleted file mode 100644
index 6bd308bb826..00000000000
--- a/configs/nas220_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_NAS220=y
-CONFIG_IDENT_STRING="\nNAS 220"
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="nas220> "
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
deleted file mode 100644
index bdfa42fd30c..00000000000
--- a/include/configs/nas220.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
- *
- * based on work from:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef _CONFIG_NAS220_H
-#define _CONFIG_NAS220_H
-
-/*
- * Machine type ID
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
-#define CONFIG_KW88F6192 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/* power-on led, regulator, sata0, sata1 */
-#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))
-#define NAS220_GE_OE_VAL_HIGH (0)
-#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)))
-#define NAS220_GE_OE_HIGH (~(0))
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#endif
-
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_OFFSET 0xa0000
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND ""
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs=console=ttyS0,115200\0" \
- "mtdparts=mtdparts=orion_nand:0xa0000 at 0x0(uboot),"\
- "0x010000 at 0xa0000(env),"\
- "0x500000 at 0xc0000(uimage),"\
- "0x1a40000@0x5c0000(rootfs)\0" \
- "mtdids=nand0=orion_nand\0"\
- "autostart=no\0"\
- "autoload=no\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 8
-#endif /* CONFIG_CMD_NET */
-
-/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
- * File system
- */
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_LZO
-
-/*
- * SATA
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif
-
-/*
- * EFI partition
- */
-
-#define CONFIG_KIRKWOOD_GPIO
-
-#endif /* _CONFIG_NAS220_H */
-
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 37/93] arm: Remove am335x_pdu001 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (35 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 36/93] arm: Remove nas220 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-29 10:39 ` Felix Brack
2018-11-19 15:53 ` [U-Boot] [PATCH 38/93] arm: Remove snapper9260 board Simon Glass
` (60 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/eets/pdu001/Kconfig | 50 ------
board/eets/pdu001/MAINTAINERS | 6 -
board/eets/pdu001/Makefile | 13 --
board/eets/pdu001/README | 35 ----
board/eets/pdu001/board.c | 275 --------------------------------
board/eets/pdu001/board.h | 37 -----
board/eets/pdu001/mux.c | 119 --------------
configs/am335x_pdu001_defconfig | 53 ------
include/configs/pdu001.h | 86 ----------
10 files changed, 675 deletions(-)
delete mode 100644 board/eets/pdu001/Kconfig
delete mode 100644 board/eets/pdu001/MAINTAINERS
delete mode 100644 board/eets/pdu001/Makefile
delete mode 100644 board/eets/pdu001/README
delete mode 100644 board/eets/pdu001/board.c
delete mode 100644 board/eets/pdu001/board.h
delete mode 100644 board/eets/pdu001/mux.c
delete mode 100644 configs/am335x_pdu001_defconfig
delete mode 100644 include/configs/pdu001.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7389b8db46d..76f9977eda9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1501,7 +1501,6 @@ source "board/broadcom/bcmnsp/Kconfig"
source "board/broadcom/bcmns2/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
-source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig
deleted file mode 100644
index e64ae28875b..00000000000
--- a/board/eets/pdu001/Kconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-if TARGET_PDU001
-
-config SYS_BOARD
- default "pdu001"
-
-config SYS_VENDOR
- default "eets"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "pdu001"
-
-choice
- prompt "State of Run LED"
- default RUN_LED_RED
- help
- The PDU001 has a bi-color (red/green) LED labeled 'Run' which
- can be used to indicate the operating state of the board. By
- default it will be lit red by U-Boot. Later in the start-up
- process it can be changed to green (or heartbeat or anything else)
- by the kernel or some other software.
-
-config RUN_LED_RED
- bool
- prompt "Red"
- help
- Lit Run LED red.
-
-config RUN_LED_GREEN
- bool
- prompt "Green"
- help
- Lit Run LED green.
-
-config RUN_LED_OFF
- bool
- prompt "Off"
- help
- Do not lit Run LED.
-
-endchoice
-
-endif
diff --git a/board/eets/pdu001/MAINTAINERS b/board/eets/pdu001/MAINTAINERS
deleted file mode 100644
index 95295ddea9a..00000000000
--- a/board/eets/pdu001/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PDU001 BOARD
-M: Felix Brack <fb@ltec.ch>
-S: Maintained
-F: board/eets/pdu001/
-F: include/configs/pdu001.h
-F: configs/am335x_pdu001_defconfig
diff --git a/board/eets/pdu001/Makefile b/board/eets/pdu001/Makefile
deleted file mode 100644
index 08c6d536d36..00000000000
--- a/board/eets/pdu001/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README
deleted file mode 100644
index 50e715446b6..00000000000
--- a/board/eets/pdu001/README
+++ /dev/null
@@ -1,35 +0,0 @@
-# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-Summary
-=======
-
-This document covers the PDU001 target.
-
-Hardware
-========
-
-The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
-manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
-SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
-AM3352 SOC from TI (http://www.ti.com).
-
-Customization
-=============
-
-As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice
-is 4 here since UART3 is wired to the connector K2.
-The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED
-or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn
-off the Run LED.
-
-Booting
-=======
-
-The system boots from either eMMC or SD card cage. It will first try to boot
-from the SD card cage. If this fails (missing or unbootable SD card) it will
-try to boot from the internal eMMC. The root file system is always expected to
-be located in the second partition of the device (eMMC or SD card) that pro-
-vided the boot loader.
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
deleted file mode 100644
index b4b8081c90a..00000000000
--- a/board/eets/pdu001/board.c
+++ /dev/null
@@ -1,275 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for EETS PDU001 board
- *
- * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <i2c.h>
-#include <environment.h>
-#include <watchdog.h>
-#include <debug_uart.h>
-#include <dm/ofnode.h>
-#include <power/pmic.h>
-#include <power/regulator.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define I2C_ADDR_NODE_ID 0x50
-#define I2C_REG_NODE_ID_BASE 0xfa
-#define NODE_ID_BYTE_COUNT 6
-
-#define I2C_ADDR_LEDS 0x60
-#define I2C_REG_RUN_LED 0x06
-#define RUN_LED_OFF 0x0
-#define RUN_LED_RED 0x1
-#define RUN_LED_GREEN (0x1 << 2)
-
-#define VDD_MPU_REGULATOR "regulator at 2"
-#define VDD_CORE_REGULATOR "regulator at 3"
-#define DEFAULT_CORE_VOLTAGE 1137500
-
-/*
- * boot device save register
- * -------------------------
- * The boot device can be quired by 'spl_boot_device()' in
- * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
- * environment here. In turn 'spl_boot_device' can't be called in
- * 'board_late_init' which allows writing to u-boot environment.
- * To get the boot device from 'am33xx_spl_board_init' to
- * 'board_late_init' we therefore use a scratch register from the RTC.
- */
-#define CONFIG_SYS_RTC_SCRATCH0 0x60
-#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
-
-#ifdef CONFIG_SPL_BUILD
-static void save_boot_device(void)
-{
- *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
-}
-#endif
-
-u32 boot_device(void)
-{
- return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
-}
-
-/* Store the boot device in the environment variable 'boot_device' */
-static void env_set_boot_device(void)
-{
- switch (boot_device()) {
- case BOOT_DEVICE_MMC1: {
- env_set("boot_device", "emmc");
- break;
- }
- case BOOT_DEVICE_MMC2: {
- env_set("boot_device", "sdcard");
- break;
- }
- default: {
- env_set("boot_device", "unknown");
- break;
- }
- }
-}
-
-static void set_run_led(struct udevice *dev)
-{
- int val = RUN_LED_OFF;
-
- if (IS_ENABLED(CONFIG_RUN_LED_RED))
- val = RUN_LED_RED;
- else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
- val = RUN_LED_GREEN;
-
- dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
-}
-
-/* Set 'serial#' to the EUI-48 value of board node ID chip */
-static void env_set_serial(struct udevice *dev)
-{
- int val;
- char serial[2 * NODE_ID_BYTE_COUNT + 1];
- int n;
-
- for (n = 0; n < sizeof(serial); n += 2) {
- val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
- sprintf(serial + n, "%02X", val);
- }
- serial[2 * NODE_ID_BYTE_COUNT] = '\0';
- env_set("serial#", serial);
-}
-
-static void set_mpu_and_core_voltage(void)
-{
- int mpu_vdd;
- int sil_rev;
- struct udevice *dev;
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
- /*
- * The PDU001 (more precisely the computing module m2) uses a
- * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
- * voltage of 1.1375V. For MPU voltage we need to switch based on
- * the frequency we are running at.
- */
-
- /*
- * Depending on MPU clock and PG we will need a different VDD
- * to drive@that speed.
- */
- sil_rev = readl(&cdev->deviceid) >> 28;
- mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
-
- /* first update the MPU voltage */
- if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
- if (regulator_set_value(dev, mpu_vdd))
- debug("failed to set MPU voltage\n");
- } else {
- debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
- }
-
- /* second update the CORE voltage */
- if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
- if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
- debug("failed to set CORE voltage\n");
- } else {
- debug("invalid CORE voltage ragulator %s\n",
- VDD_CORE_REGULATOR);
- }
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-static const struct ddr_data ddr2_data = {
- .datardsratio0 = MT47H128M16RT25E_RD_DQS,
- .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
- .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
- .cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd2csratio = MT47H128M16RT25E_RATIO,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
- .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
- .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
- .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
- .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
- .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
-};
-
-#define OSC (V_OSCK / 1000000)
-const struct dpll_params dpll_ddr = {
- 266, OSC - 1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
- 303, OSC - 1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_bone_black = {
- 400, OSC - 1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-
- /* save boot device for later use by 'board_late_init' */
- save_boot_device();
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
- return &dpll_ddr;
-}
-
-void set_mux_conf_regs(void)
-{
- /* done first by the ROM and afterwards by the pin controller driver */
- enable_i2c0_pin_mux();
-}
-
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
- config_ddr(266, &ioregs, &ddr2_data,
- &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifdef CONFIG_DEBUG_UART
-void board_debug_uart_init(void)
-{
- /* done by pin controller driver if not debugging */
- enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- struct udevice *dev;
-
- set_mpu_and_core_voltage();
- env_set_boot_device();
-
- /* second I2C bus connects to node ID and front panel LED chip */
- if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
- set_run_led(dev);
- if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
- env_set_serial(dev);
-
- return 0;
-}
-#endif
diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h
deleted file mode 100644
index bfea96e5f02..00000000000
--- a/board/eets/pdu001/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * EETS GmbH PDU001 board information header
- *
- * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * We have two pin mux functions that must exist. First we need I2C0 to
- * access the TPS65910 PMIC located on the M2 computing module.
- * Second, if we want low-level debugging or a early UART (ie. before the
- * pin controller driver is running), we need one of the UART ports UART0 to
- * UART5 (usually UART3 since it is wired to K2).
- * In case of I2C0 access we explicitly don't rely on the the ROM but we could
- * do so as we use the primary mode (mode 0) for I2C0.
- * All other multiplexing and pin configuration is done by the DT once it
- * gets parsed by the pin controller driver.
- * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
- * as MMC1 (microSD card-cage) since these are our boot devices.
- */
-void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_uart_pin_mux(u32 addr);
-void enable_i2c0_pin_mux(void);
-
-#endif
diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c
deleted file mode 100644
index f1d38e9b74d..00000000000
--- a/board/eets/pdu001/mux.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mux.c
- *
- * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
- {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
- {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
- {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
- {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
- {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
- {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart1_pin_mux(void)
-{
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
- configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
- configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
- configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
- configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_uart_pin_mux(u32 addr)
-{
- switch (addr) {
- case CONFIG_SYS_NS16550_COM1:
- enable_uart0_pin_mux();
- break;
- case CONFIG_SYS_NS16550_COM2:
- enable_uart1_pin_mux();
- break;
- case CONFIG_SYS_NS16550_COM3:
- enable_uart2_pin_mux();
- break;
- case CONFIG_SYS_NS16550_COM4:
- enable_uart3_pin_mux();
- break;
- case CONFIG_SYS_NS16550_COM5:
- enable_uart4_pin_mux();
- break;
- case CONFIG_SYS_NS16550_COM6:
- enable_uart5_pin_mux();
- break;
- }
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
deleted file mode 100644
index 065efca633e..00000000000
--- a/configs/am335x_pdu001_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_PDU001=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_LOCALVERSION="-EETS-1.0.0"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
-# CONFIG_NET is not set
-CONFIG_SPL_DM=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_SDHCI=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_TPS65910=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_TPS65910=y
-CONFIG_CONS_INDEX=4
-CONFIG_SPI=y
-# CONFIG_USE_TINY_PRINTF is not set
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h
deleted file mode 100644
index 7b809e2329b..00000000000
--- a/include/configs/pdu001.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * pdu001.h
- *
- * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#ifndef __CONFIG_PDU001_H
-#define __CONFIG_PDU001_H
-
-#include <configs/ti_am335x_common.h>
-
-/* No more need for I2C legacy compatibility for this board.
- * CONFIG_DM_I2C_COMPAT is defined in ti_armv7_common.h. See the comment there
- * for the right moment to delete the following line.
- */
-#undef CONFIG_DM_I2C_COMPAT
-
-/* Using 32K of volatile storage for environment */
-#define CONFIG_ENV_SIZE 0x4000
-
-#define MACH_TYPE_PDU001 5075
-#define CONFIG_MACH_TYPE MACH_TYPE_PDU001
-#define CONFIG_BOARD_LATE_INIT
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#if CONFIG_CONS_INDEX == 1
- #define CONSOLE_DEV "ttyO0"
-#elif CONFIG_CONS_INDEX == 2
- #define CONSOLE_DEV "ttyO1"
-#elif CONFIG_CONS_INDEX == 3
- #define CONSOLE_DEV "ttyO2"
-#elif CONFIG_CONS_INDEX == 4
- #define CONSOLE_DEV "ttyO3"
-#elif CONFIG_CONS_INDEX == 5
- #define CONSOLE_DEV "ttyO4"
-#elif CONFIG_CONS_INDEX == 6
- #define CONSOLE_DEV "ttyO5"
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "run eval_boot_device;" \
- "setenv bootargs console=${console} " \
- "vt.global_cursor_default=0 " \
- "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \
- "rootfstype=ext4 " \
- "rootwait " \
- "rootdelay=1;" \
- "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \
- "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \
- "bootz ${loadaddr} - ${fdtaddr}"
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "fdtfile=am335x-pdu001.dtb\0" \
- "bootfile=zImage\0" \
- "console=" CONSOLE_DEV ",115200n8\0" \
- "root_fs_partition=2\0" \
- "eval_boot_device=" \
- "if test $boot_device = emmc; then " \
- "setenv mmc_boot 0;" \
- "elif test $boot_device = sdcard; then " \
- "setenv mmc_boot 1;" \
- "else " \
- "echo Bootdevice is neither MMC0 nor MMC1;" \
- "reset;" \
- "fi;" \
- "\0"
-#endif
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 UART2_BASE
-#define CONFIG_SYS_NS16550_COM4 UART3_BASE
-#define CONFIG_SYS_NS16550_COM5 UART4_BASE
-#define CONFIG_SYS_NS16550_COM6 UART5_BASE
-#define CONFIG_BAUDRATE 115200
-
-#endif /* ! __CONFIG_PDU001_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 37/93] arm: Remove am335x_pdu001 board
2018-11-19 15:53 ` [U-Boot] [PATCH 37/93] arm: Remove am335x_pdu001 board Simon Glass
@ 2018-11-29 10:39 ` Felix Brack
2018-11-29 18:42 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Felix Brack @ 2018-11-29 10:39 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 19.11.2018 16:53, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
I'm working on a patch for this board. It should be ready in a few days.
regards, Felix
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 37/93] arm: Remove am335x_pdu001 board
2018-11-29 10:39 ` Felix Brack
@ 2018-11-29 18:42 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-29 18:42 UTC (permalink / raw)
To: u-boot
Hi Felix,
On Thu, 29 Nov 2018 at 03:40, Felix Brack <fb@ltec.ch> wrote:
>
> Hi Simon,
>
> On 19.11.2018 16:53, Simon Glass wrote:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> I'm working on a patch for this board. It should be ready in a few days.
That's great, thanks!
- Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 38/93] arm: Remove snapper9260 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (36 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 37/93] arm: Remove am335x_pdu001 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 39/93] arm: Remove pfla02 board Simon Glass
` (59 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 1 -
board/bluewater/snapper9260/Kconfig | 12 --
board/bluewater/snapper9260/MAINTAINERS | 7 -
board/bluewater/snapper9260/Makefile | 9 --
board/bluewater/snapper9260/snapper9260.c | 151 ----------------------
configs/snapper9260_defconfig | 34 -----
configs/snapper9g20_defconfig | 33 -----
include/configs/snapper9260.h | 123 ------------------
8 files changed, 370 deletions(-)
delete mode 100644 board/bluewater/snapper9260/Kconfig
delete mode 100644 board/bluewater/snapper9260/MAINTAINERS
delete mode 100644 board/bluewater/snapper9260/Makefile
delete mode 100644 board/bluewater/snapper9260/snapper9260.c
delete mode 100644 configs/snapper9260_defconfig
delete mode 100644 configs/snapper9g20_defconfig
delete mode 100644 include/configs/snapper9260.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0fe93263ba8..a879e79af2d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -278,7 +278,6 @@ source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
-source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig
deleted file mode 100644
index b8e9cbc5855..00000000000
--- a/board/bluewater/snapper9260/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_SNAPPER9260
-
-config SYS_BOARD
- default "snapper9260"
-
-config SYS_VENDOR
- default "bluewater"
-
-config SYS_CONFIG_NAME
- default "snapper9260"
-
-endif
diff --git a/board/bluewater/snapper9260/MAINTAINERS b/board/bluewater/snapper9260/MAINTAINERS
deleted file mode 100644
index 1f8f4d6988f..00000000000
--- a/board/bluewater/snapper9260/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-SNAPPER9260 BOARD
-M: Simon Glass <sjg@chromium.org>
-S: Maintained
-F: board/bluewater/snapper9260/
-F: include/configs/snapper9260.h
-F: configs/snapper9260_defconfig
-F: configs/snapper9g20_defconfig
diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile
deleted file mode 100644
index 842abf4eeeb..00000000000
--- a/board/bluewater/snapper9260/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2011 Bluewater Systems
-# Ryan Mallon <ryan@bluewatersys.com>
-
-obj-y += snapper9260.o
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
deleted file mode 100644
index d2a1b97d7b1..00000000000
--- a/board/bluewater/snapper9260/snapper9260.c
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluewater Systems Snapper 9260/9G20 modules
- *
- * (C) Copyright 2011 Bluewater Systems
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/atmel_serial.h>
-#include <net.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <pca953x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* IO Expander pins */
-#define IO_EXP_ETH_RESET (0 << 1)
-#define IO_EXP_ETH_POWER (1 << 1)
-
-static void macb_hw_init(void)
-{
- struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
- at91_periph_clk_enable(ATMEL_ID_EMAC0);
-
- /* Disable pull-ups to prevent PHY going into test mode */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA18),
- &pioa->pudr);
-
- /* Power down ethernet */
- pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
- pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
-
- /* Hold ethernet in reset */
- pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
- pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
-
- /* Enable ethernet power */
- pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
-
- at91_phy_reset();
-
- /* Bring the ethernet out of reset */
- pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
-
- /* The phy internal reset take 21ms */
- udelay(21 * 1000);
-
- /* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA18),
- &pioa->puer);
-
- at91_macb_hw_init();
-}
-
-static void nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- unsigned long csa;
-
- /* Enable CS3 as NAND/SmartMedia */
- csa = readl(&matrix->ebicsa);
- csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
- writel(csa, &matrix->ebicsa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-
-int board_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
-
- /* The mach-type is the same for both Snapper 9260 and 9G20 */
- gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
-
- /* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- /* Initialise peripherals */
- at91_seriald_hw_init();
- i2c_set_bus_num(0);
- nand_hw_init();
- macb_hw_init();
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-void reset_phy(void)
-{
-}
-
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
- .base_addr = ATMEL_BASE_DBGU,
-};
-
-U_BOOT_DEVICE(at91sam9260_serial) = {
- .name = "serial_atmel",
- .platdata = &at91sam9260_serial_plat,
-};
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
deleted file mode 100644
index 7ce29bfb904..00000000000
--- a/configs/snapper9260_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_SNAPPER9260=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 ip=any"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Snapper> "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_CMD_PCA953X=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_NAND_ATMEL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
deleted file mode 100644
index 2773c6b41b1..00000000000
--- a/configs/snapper9g20_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_TARGET_SNAPPER9260=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 ip=any"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_CMD_PCA953X=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_NAND_ATMEL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
deleted file mode 100644
index f212d154e9c..00000000000
--- a/include/configs/snapper9260.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Bluewater Systems Snapper 9260 and 9G20 modules
- *
- * (C) Copyright 2011 Bluewater Systems
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SoC type is defined in boards.cfg */
-#include <asm/hardware.h>
-#include <linux/sizes.h>
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/* Mem test settings */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
-
-/* NAND Flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_RESET_PHY_R
-#define CONFIG_AT91_WANTS_COMMON_PHY
-#define CONFIG_TFTP_PORT
-#define CONFIG_TFTP_TSIZE
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
-/* GPIOs and IO expander */
-#define CONFIG_ATMEL_LEGACY
-#define CONFIG_AT91_GPIO
-#define CONFIG_AT91_GPIO_PULLUP 1
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
-
-/* UARTs/Serial console */
-#define CONFIG_ATMEL_USART
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#endif
-
-/* I2C - Bit-bashed */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define I2C_INIT do { \
- at91_set_gpio_output(AT91_PIN_PA23, 1); \
- at91_set_gpio_output(AT91_PIN_PA24, 1); \
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
- } while (0)
-#define I2C_SOFT_DECLARATIONS
-#define I2C_ACTIVE
-#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
-#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
-#define I2C_SDA(bit) do { \
- if (bit) { \
- at91_set_gpio_input(AT91_PIN_PA23, 1); \
- } else { \
- at91_set_gpio_output(AT91_PIN_PA23, 1); \
- at91_set_gpio_value(AT91_PIN_PA23, bit); \
- } \
- } while (0)
-#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
-#define I2C_DELAY udelay(2)
-
-/* Boot options */
-#define CONFIG_SYS_LOAD_ADDR 0x23000000
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Environment settings */
-#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_ENV_OVERWRITE
-
-/* Console settings */
-
-/* U-Boot memory settings */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 39/93] arm: Remove pfla02 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (37 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 38/93] arm: Remove snapper9260 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board Simon Glass
` (58 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/phytec/pfla02/Kconfig | 18 -
board/phytec/pfla02/MAINTAINERS | 6 -
board/phytec/pfla02/Makefile | 7 -
board/phytec/pfla02/README | 24 --
board/phytec/pfla02/pfla02.c | 707 --------------------------------
configs/pfla02_defconfig | 57 ---
include/configs/pfla02.h | 157 -------
8 files changed, 977 deletions(-)
delete mode 100644 board/phytec/pfla02/Kconfig
delete mode 100644 board/phytec/pfla02/MAINTAINERS
delete mode 100644 board/phytec/pfla02/Makefile
delete mode 100644 board/phytec/pfla02/README
delete mode 100644 board/phytec/pfla02/pfla02.c
delete mode 100644 configs/pfla02_defconfig
delete mode 100644 include/configs/pfla02.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 8169bfb18e6..701973b3866 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -547,7 +547,6 @@ source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
-source "board/phytec/pfla02/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/logicpd/imx6/Kconfig"
diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig
deleted file mode 100644
index f4da68b5ba9..00000000000
--- a/board/phytec/pfla02/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if TARGET_PFLA02
-
-config SYS_BOARD
- default "pfla02"
-
-config SYS_VENDOR
- default "phytec"
-
-config SYS_CONFIG_NAME
- default "pfla02"
-
-config SPL_DRAM_1_BANK
- bool "DRAM on just one bank"
- help
- activate, if the module has just one bank
- of RAM
-
-endif
diff --git a/board/phytec/pfla02/MAINTAINERS b/board/phytec/pfla02/MAINTAINERS
deleted file mode 100644
index 4b069a90cdc..00000000000
--- a/board/phytec/pfla02/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PHYTEC PHYFLEX
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/phytec/pfla02/
-F: include/configs/pfla02.h
-F: configs/pfla02_defconfig
diff --git a/board/phytec/pfla02/Makefile b/board/phytec/pfla02/Makefile
deleted file mode 100644
index c50f315d911..00000000000
--- a/board/phytec/pfla02/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := pfla02.o
diff --git a/board/phytec/pfla02/README b/board/phytec/pfla02/README
deleted file mode 100644
index 0f46ab86233..00000000000
--- a/board/phytec/pfla02/README
+++ /dev/null
@@ -1,24 +0,0 @@
-Board information
------------------
-
-The evaluation board "pbab01" is thought to be used
-together with the SOM.
-
-More information on the board can be found on manufacturer's
-website:
-
-http://www.phytec.de/produkt/system-on-modules/phyflex-imx-6/
-
-Building U-Boot
--------------------------------
-
-$ make pfla02_defconfig
-$ make
-
-This generates the artifacts SPL and u-boot.img.
-The SOM can boot from NAND or from SD-Card, having the SPI-NOR
-as second option.
-The dip switch "SW3" on the board let choose the boot device.
-
-SW3_1(on), SW3_2(on), SW3_3(off): Boot first from SD, then try SPI
-SW3_1(off), SW3_2(on), SW3_3(off): Boot from SPI
diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c
deleted file mode 100644
index aae23a3e444..00000000000
--- a/board/phytec/pfla02/pfla02.c
+++ /dev/null
@@ -1,707 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <mmc.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <nand.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/sections.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define GREEN_LED IMX_GPIO_NR(2, 31)
-#define RED_LED IMX_GPIO_NR(1, 30)
-#define IMX6Q_DRIVE_STRENGTH 0x30
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-static iomux_v3_cfg_t const uart4_pads[] = {
- IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const ecspi3_pads[] = {
- IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const gpios_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-#ifdef CONFIG_CMD_NAND
-/* NAND */
-static iomux_v3_cfg_t const nfc_pads[] = {
- IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
-};
-#endif
-
-static struct i2c_pads_info i2c_pad_info = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
- {USDHC3_BASE_ADDR,
- .max_bus_width = 4},
- {.esdhc_base = USDHC2_BASE_ADDR,
- .max_bus_width = 4},
-};
-
-#if !defined(CONFIG_SPL_BUILD)
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-#endif
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-int board_mmc_get_env_dev(int devno)
-{
- return devno - 1;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- ret = 1;
- break;
- case USDHC3_BASE_ADDR:
- ret = 1;
- break;
- }
-
- return ret;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- int i;
-
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart4_pads);
-}
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
- mdelay(10);
- gpio_set_value(ENET_PHY_RESET_GPIO, 1);
- mdelay(30);
-}
-
-static void setup_spi(void)
-{
- gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
- gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
-
- SETUP_IOMUX_PADS(ecspi3_pads);
-
- enable_spi_clk(true, 2);
-}
-
-static void setup_gpios(void)
-{
- SETUP_IOMUX_PADS(gpios_pads);
-}
-
-#ifdef CONFIG_CMD_NAND
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- SETUP_IOMUX_PADS(nfc_pads);
-
- /* gate ENFC_CLK_ROOT clock first,before clk source switch */
- clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* config gpmi and bch clock to 100 MHz */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
- /* enable ENFC_CLK_ROOT clock */
- setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-/*
- * Board revision is coded in 4 GPIOs
- */
-u32 get_board_rev(void)
-{
- u32 rev;
- int i;
-
- for (i = 0, rev = 0; i < 4; i++)
- rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
-
- return 16 - rev;
-}
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- if (bus != 2 || (cs != 0))
- return -EINVAL;
-
- return IMX_GPIO_NR(4, 24);
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
-#endif
-
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
-
- setup_gpios();
-
-#ifdef CONFIG_CMD_NAND
- setup_gpmi_nand();
-#endif
- return 0;
-}
-
-
-#ifdef CONFIG_CMD_BMODE
-/*
- * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
- * see Table 8-11 and Table 5-9
- * BOOT_CFG1[7] = 1 (boot from NAND)
- * BOOT_CFG1[5] = 0 - raw NAND
- * BOOT_CFG1[4] = 0 - default pad settings
- * BOOT_CFG1[3:2] = 00 - devices = 1
- * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
- * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
- * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
- * BOOT_CFG2[0] = 0 - Reset time 12ms
- */
-static const struct boot_mode board_boot_modes[] = {
- /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
- {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
- {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
- char buf[10];
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
- snprintf(buf, sizeof(buf), "%d", get_board_rev());
- env_set("board_rev", buf);
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-#include <spl.h>
-#include <linux/libfdt.h>
-
-#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
-static void phyflex_err006282_workaround(void)
-{
- /*
- * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
- * to the CMIC. If this pin isn't toggled within 10s the boards
- * reset. The pin is unconnected on older boards, so we do not
- * need a check for older boards before applying this fixup.
- */
-
- gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
- mdelay(2);
- gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
- mdelay(2);
- gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
-
- gpio_direction_input(MX6_PHYFLEX_ERR006282);
-}
-
-static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00000030,
- .dram_sdclk_1 = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_reset = 0x00000030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000030,
- .dram_sdodt0 = 0x00000030,
- .dram_sdodt1 = 0x00000030,
-
- .dram_sdqs0 = 0x00000028,
- .dram_sdqs1 = 0x00000028,
- .dram_sdqs2 = 0x00000028,
- .dram_sdqs3 = 0x00000028,
- .dram_sdqs4 = 0x00000028,
- .dram_sdqs5 = 0x00000028,
- .dram_sdqs6 = 0x00000028,
- .dram_sdqs7 = 0x00000028,
- .dram_dqm0 = 0x00000028,
- .dram_dqm1 = 0x00000028,
- .dram_dqm2 = 0x00000028,
- .dram_dqm3 = 0x00000028,
- .dram_dqm4 = 0x00000028,
- .dram_dqm5 = 0x00000028,
- .dram_dqm6 = 0x00000028,
- .dram_dqm7 = 0x00000028,
-};
-
-static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6Q_DRIVE_STRENGTH,
- .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000028,
- .grp_b1ds = 0x00000028,
- .grp_b2ds = 0x00000028,
- .grp_b3ds = 0x00000028,
- .grp_b4ds = 0x00000028,
- .grp_b5ds = 0x00000028,
- .grp_b6ds = 0x00000028,
- .grp_b7ds = 0x00000028,
-};
-
-static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00110011,
- .p0_mpwldectrl1 = 0x00240024,
- .p1_mpwldectrl0 = 0x00260038,
- .p1_mpwldectrl1 = 0x002C0038,
- .p0_mpdgctrl0 = 0x03400350,
- .p0_mpdgctrl1 = 0x03440340,
- .p1_mpdgctrl0 = 0x034C0354,
- .p1_mpdgctrl1 = 0x035C033C,
- .p0_mprddlctl = 0x322A2A2A,
- .p1_mprddlctl = 0x302C2834,
- .p0_mpwrdlctl = 0x34303834,
- .p1_mpwrdlctl = 0x422A3E36,
-};
-
-/* Index in RAM Chip array */
-enum {
- RAM_MT64K,
- RAM_MT128K,
- RAM_MT256K
-};
-
-static struct mx6_ddr3_cfg mt41k_xx[] = {
-/* MT41K64M16JT-125 (1Gb density) */
- {
- .mem_speed = 1600,
- .density = 1,
- .width = 16,
- .banks = 8,
- .rowaddr = 13,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 1,
- },
-
-/* MT41K256M16JT-125 (2Gb density) */
- {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 1,
- },
-
-/* MT41K256M16JT-125 (4Gb density) */
- {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 1,
- }
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
- struct mx6_ddr3_cfg *mem_ddr)
-{
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (spl_boot_device() == BOOT_DEVICE_SPI)
- printf("MMC SEtup, Boot SPI");
-
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 4;
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-
-void board_boot_order(u32 *spl_boot_list)
-{
- spl_boot_list[0] = spl_boot_device();
- printf("Boot device %x\n", spl_boot_list[0]);
- switch (spl_boot_list[0]) {
- case BOOT_DEVICE_SPI:
- spl_boot_list[1] = BOOT_DEVICE_UART;
- break;
- case BOOT_DEVICE_MMC1:
- spl_boot_list[1] = BOOT_DEVICE_SPI;
- spl_boot_list[2] = BOOT_DEVICE_UART;
- break;
- default:
- printf("Boot device %x\n", spl_boot_list[0]);
- }
-}
-
-/*
- * This is used because get_ram_size() does not
- * take care of cache, resulting a wrong size
- * pfla02 has just 1, 2 or 4 GB option
- * Function checks for mirrors in the first CS
- */
-#define RAM_TEST_PATTERN 0xaa5555aa
-#define MIN_BANK_SIZE (512 * 1024 * 1024)
-
-static unsigned int pfla02_detect_chiptype(void)
-{
- u32 *p, *p1;
- unsigned int offset = MIN_BANK_SIZE;
- int i;
-
- for (i = 0; i < 2; i++) {
- p = (u32 *)PHYS_SDRAM;
- p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
-
- *p1 = 0;
- *p = RAM_TEST_PATTERN;
-
- /*
- * This is required to detect mirroring
- * else we read back values from cache
- */
- flush_dcache_all();
-
- if (*p == *p1)
- return i;
- }
- return RAM_MT256K;
-}
-
-void board_init_f(ulong dummy)
-{
- unsigned int ramchip;
-
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 512 MB */
- /* single chip select */
-#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
- .ncs = 1,
-#else
- .ncs = 2,
-#endif
- .cs1_mirror = 1,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
-#ifdef CONFIG_CMD_NAND
- /* Enable NAND */
- setup_gpmi_nand();
-#endif
-
- /* setup clock gating */
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- /* setup AXI */
- gpr_init();
-
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- setup_spi();
-
- setup_gpios();
-
- /* DDR initialization */
- spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
- ramchip = pfla02_detect_chiptype();
- debug("Detected chip %d\n", ramchip);
-#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
- switch (ramchip) {
- case RAM_MT64K:
- sysinfo.cs_density = 6;
- break;
- case RAM_MT128K:
- sysinfo.cs_density = 10;
- break;
- case RAM_MT256K:
- sysinfo.cs_density = 18;
- break;
- }
-#endif
- spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- phyflex_err006282_workaround();
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
deleted file mode 100644
index 18d35a130f3..00000000000
--- a/configs/pfla02_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_PFLA02=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_NAND is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:-(nand);spi2.0:1024k(bootloader),64k(env1),64k(env2),-(rescue)"
-CONFIG_CMD_UBI=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h
deleted file mode 100644
index e2aae19484c..00000000000
--- a/include/configs/pfla02.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- */
-
-
-#ifndef __PCM058_CONFIG_H
-#define __PCM058_CONFIG_H
-
-#ifdef CONFIG_SPL
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#include "imx6_spl.h"
-#endif
-
-#include "mx6_common.h"
-
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
-/* Serial */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONSOLE_DEV "ttymxc3"
-
-/* Early setup */
-
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
-/* Ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 3
-
-/* SPI Flash */
-#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 20000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_NAND
-/* Enable NAND support */
-#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#endif
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* Filesystem support */
-
-/* Various command support */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-/* Environment organization */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_OFFSET (1024 * SZ_1K)
-#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (0x1E0000)
-#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
-#endif
-
-/* Default environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
- "addmtd=run mtdnand;run mtdspi;" \
- "setenv bootargs ${bootargs} ${mtdparts}\0" \
- "mtdnand=setenv mtdparts mtdparts=gpmi-nand:" \
- "40m(Kernels),400m(root),-(nand)\0" \
- "mtdspi=setenv mtdparts ${mtdparts}" \
- "';spi2.0:1024k(bootloader)," \
- "64k(env1),64k(env2),-(rescue)'\0" \
- "bootcmd=if test -n ${rescue};" \
- "then run swupdate;fi;run nandboot;run swupdate\0" \
- "bootfile=uImage\0" \
- "bootimage=uImage\0" \
- "console=ttymxc3\0" \
- "fdt_addr_r=0x18000000\0" \
- "fdt_file=pfla02.dtb\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "miscargs=panic=1 quiet\0" \
- "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
- "mmcboot=if run mmcload;then " \
- "run mmcargs addcons addmisc;" \
- "bootm;fi\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1\0" \
- "ubiroot=1\0" \
- "nandargs=setenv bootargs ubi.mtd=1 " \
- "root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0" \
- "nandboot=run mtdnand;ubi part nand0,0;" \
- "ubi readvol ${kernel_addr_r} kernel${ubiroot};" \
- "run nandargs addip addcons addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
- "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
- "run nfsargs addip addcons addmtd addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};" \
- "run nfsargs addip addcons addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs" \
- " nfsroot=${serverip}:${nfsroot},v3 panic=1\0" \
- "swupdate=setenv bootargs root=/dev/ram;" \
- "run addip addcons addmtd addmisc;" \
- "sf probe;" \
- "sf read ${kernel_addr_r} 120000 600000;" \
- "sf read 14000000 730000 800000;" \
- "bootm ${kernel_addr_r} 14000000\0"
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (38 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 39/93] arm: Remove pfla02 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-26 7:57 ` Marcel Ziswiler
2018-11-19 15:53 ` [U-Boot] [PATCH 41/93] arm: Remove work_92105 board Simon Glass
` (57 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/toradex/colibri_pxa270/Kconfig | 23 ---
board/toradex/colibri_pxa270/MAINTAINERS | 6 -
board/toradex/colibri_pxa270/Makefile | 7 -
board/toradex/colibri_pxa270/colibri_pxa270.c | 138 -------------
configs/colibri_pxa270_defconfig | 40 ----
include/configs/colibri_pxa270.h | 188 ------------------
7 files changed, 403 deletions(-)
delete mode 100644 board/toradex/colibri_pxa270/Kconfig
delete mode 100644 board/toradex/colibri_pxa270/MAINTAINERS
delete mode 100644 board/toradex/colibri_pxa270/Makefile
delete mode 100644 board/toradex/colibri_pxa270/colibri_pxa270.c
delete mode 100644 configs/colibri_pxa270_defconfig
delete mode 100644 include/configs/colibri_pxa270.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 76f9977eda9..740897539e8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1530,7 +1530,6 @@ source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/ucRobotics/bubblegum_96/Kconfig"
-source "board/toradex/colibri_pxa270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
deleted file mode 100644
index f646baa3f05..00000000000
--- a/board/toradex/colibri_pxa270/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if TARGET_COLIBRI_PXA270
-
-config SYS_BOARD
- default "colibri_pxa270"
-
-config SYS_VENDOR
- default "toradex"
-
-config SYS_CONFIG_NAME
- default "colibri_pxa270"
-
-config TDX_CFG_BLOCK
- default y
-
-config TDX_HAVE_NOR
- default y
-
-config TDX_CFG_BLOCK_OFFSET
- default "262144"
-
-source "board/toradex/common/Kconfig"
-
-endif
diff --git a/board/toradex/colibri_pxa270/MAINTAINERS b/board/toradex/colibri_pxa270/MAINTAINERS
deleted file mode 100644
index b378d7be5a4..00000000000
--- a/board/toradex/colibri_pxa270/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-COLIBRI_PXA270 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/toradex/colibri_pxa270/
-F: include/configs/colibri_pxa270.h
-F: configs/colibri_pxa270_defconfig
diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile
deleted file mode 100644
index ea610cfea92..00000000000
--- a/board/toradex/colibri_pxa270/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Toradex Colibri PXA270 Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-
-obj-y := colibri_pxa270.o
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
deleted file mode 100644
index e9e17508a57..00000000000
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Toradex Colibri PXA270 Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-#include <asm/arch/regs-uart.h>
-#include <asm/io.h>
-#include <dm/platdata.h>
-#include <dm/platform_data/serial_pxa.h>
-#include <netdev.h>
-#include <serial.h>
-#include <usb.h>
-#include <asm/mach-types.h>
-#include "../common/tdx-common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of Toradex Colibri PXA270 */
- gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Model: Toradex Colibri PXA270\n");
-
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- return ft_common_board_setup(blob, bd);
-}
-#endif
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (UHCHR & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- /* enable port 2 */
- writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
- UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-static const struct pxa_serial_platdata serial_platdata = {
- .base = (struct pxa_uart_regs *)FFUART_BASE,
- .port = FFUART_INDEX,
- .baudrate = CONFIG_BAUDRATE,
-};
-
-U_BOOT_DEVICE(pxa_serials) = {
- .name = "serial_pxa",
- .platdata = &serial_platdata,
-};
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
deleted file mode 100644
index 2ff489f4a92..00000000000
--- a/configs/colibri_pxa270_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_COLIBRI_PXA270=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="$ "
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SERIAL=y
-CONFIG_PXA_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-# CONFIG_REGEX is not set
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
deleted file mode 100644
index 622b02492dd..00000000000
--- a/include/configs/colibri_pxa270.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Toradex Colibri PXA270 configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-/* Avoid overwriting factory configuration block */
-#define CONFIG_BOARD_SIZE_LIMIT 0x40000
-
-/* We will never enable dcache because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "if fatload mmc 0 0xa0000000 uImage; then " \
- "bootm 0xa0000000; " \
- "fi; " \
- "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
- "bootm 0xa0000000; " \
- "fi; " \
- "bootm 0xc0000;"
-#define CONFIG_TIMESTAMP
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/*
- * Serial Console Configuration
- */
-
-/*
- * Bootloader Components Configuration
- */
-
-/* I2C support */
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PXA
-#define CONFIG_PXA_STD_I2C
-#define CONFIG_PXA_PWR_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
-/* LCD support */
-#ifdef CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_PXA_VGA
-#define CONFIG_LCD_LOGO
-#endif
-
-/*
- * Networking Configuration
- */
-#ifdef CONFIG_CMD_NET
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000000
-#define DM9000_IO (CONFIG_DM9000_BASE)
-#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
-#define CONFIG_NET_RETRY_COUNT 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#endif
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
-
-/*
- * DRAM Map
- */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-
-#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-/* Skip factory configuration block */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x00000000
-#define CONFIG_SYS_GPSR1_VAL 0x00020000
-#define CONFIG_SYS_GPSR2_VAL 0x0002c000
-#define CONFIG_SYS_GPSR3_VAL 0x00000000
-
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-
-#define CONFIG_SYS_GPDR0_VAL 0xc8008000
-#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
-#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
-#define CONFIG_SYS_GPDR3_VAL 0x0061e804
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
-#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
-#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
-#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x00500240
-#define CONFIG_SYS_CCCR 0x02000290
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
-#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
-#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
-#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
-#define CONFIG_SYS_MDREFR_VAL 0x2003a031
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00028307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x00038787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0002830f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-#include "pxa-common.h"
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board
2018-11-19 15:53 ` [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board Simon Glass
@ 2018-11-26 7:57 ` Marcel Ziswiler
2018-11-26 12:57 ` Tom Rini
2018-11-27 0:08 ` Simon Glass
0 siblings, 2 replies; 211+ messages in thread
From: Marcel Ziswiler @ 2018-11-26 7:57 UTC (permalink / raw)
To: u-boot
On Mon, 2018-11-19 at 08:53 -0700, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
NAK. I started working on PXA MMC driver which so far is not DM
enabled. Hopefully, I have something ready later this week.
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/Kconfig | 1 -
> board/toradex/colibri_pxa270/Kconfig | 23 ---
> board/toradex/colibri_pxa270/MAINTAINERS | 6 -
> board/toradex/colibri_pxa270/Makefile | 7 -
> board/toradex/colibri_pxa270/colibri_pxa270.c | 138 -------------
> configs/colibri_pxa270_defconfig | 40 ----
> include/configs/colibri_pxa270.h | 188 ----------------
> --
> 7 files changed, 403 deletions(-)
> delete mode 100644 board/toradex/colibri_pxa270/Kconfig
> delete mode 100644 board/toradex/colibri_pxa270/MAINTAINERS
> delete mode 100644 board/toradex/colibri_pxa270/Makefile
> delete mode 100644 board/toradex/colibri_pxa270/colibri_pxa270.c
> delete mode 100644 configs/colibri_pxa270_defconfig
> delete mode 100644 include/configs/colibri_pxa270.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 76f9977eda9..740897539e8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1530,7 +1530,6 @@ source "board/spear/x600/Kconfig"
> source "board/st/stv0991/Kconfig"
> source "board/tcl/sl50/Kconfig"
> source "board/ucRobotics/bubblegum_96/Kconfig"
> -source "board/toradex/colibri_pxa270/Kconfig"
> source "board/vscom/baltos/Kconfig"
> source "board/woodburn/Kconfig"
> source "board/xilinx/Kconfig"
> diff --git a/board/toradex/colibri_pxa270/Kconfig
> b/board/toradex/colibri_pxa270/Kconfig
> deleted file mode 100644
> index f646baa3f05..00000000000
> --- a/board/toradex/colibri_pxa270/Kconfig
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -if TARGET_COLIBRI_PXA270
> -
> -config SYS_BOARD
> - default "colibri_pxa270"
> -
> -config SYS_VENDOR
> - default "toradex"
> -
> -config SYS_CONFIG_NAME
> - default "colibri_pxa270"
> -
> -config TDX_CFG_BLOCK
> - default y
> -
> -config TDX_HAVE_NOR
> - default y
> -
> -config TDX_CFG_BLOCK_OFFSET
> - default "262144"
> -
> -source "board/toradex/common/Kconfig"
> -
> -endif
> diff --git a/board/toradex/colibri_pxa270/MAINTAINERS
> b/board/toradex/colibri_pxa270/MAINTAINERS
> deleted file mode 100644
> index b378d7be5a4..00000000000
> --- a/board/toradex/colibri_pxa270/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -COLIBRI_PXA270 BOARD
> -M: Marek Vasut <marek.vasut@gmail.com>
> -S: Maintained
> -F: board/toradex/colibri_pxa270/
> -F: include/configs/colibri_pxa270.h
> -F: configs/colibri_pxa270_defconfig
> diff --git a/board/toradex/colibri_pxa270/Makefile
> b/board/toradex/colibri_pxa270/Makefile
> deleted file mode 100644
> index ea610cfea92..00000000000
> --- a/board/toradex/colibri_pxa270/Makefile
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Toradex Colibri PXA270 Support
> -#
> -# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
> -
> -obj-y := colibri_pxa270.o
> diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c
> b/board/toradex/colibri_pxa270/colibri_pxa270.c
> deleted file mode 100644
> index e9e17508a57..00000000000
> --- a/board/toradex/colibri_pxa270/colibri_pxa270.c
> +++ /dev/null
> @@ -1,138 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Toradex Colibri PXA270 Support
> - *
> - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
> - * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
> - */
> -
> -#include <common.h>
> -#include <dm.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/pxa.h>
> -#include <asm/arch/regs-mmc.h>
> -#include <asm/arch/regs-uart.h>
> -#include <asm/io.h>
> -#include <dm/platdata.h>
> -#include <dm/platform_data/serial_pxa.h>
> -#include <netdev.h>
> -#include <serial.h>
> -#include <usb.h>
> -#include <asm/mach-types.h>
> -#include "../common/tdx-common.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_init(void)
> -{
> - /* We have RAM, disable cache */
> - dcache_disable();
> - icache_disable();
> -
> - /* arch number of Toradex Colibri PXA270 */
> - gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
> -
> - /* adress of boot parameters */
> - gd->bd->bi_boot_params = 0xa0000100;
> -
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - puts("Model: Toradex Colibri PXA270\n");
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - return ft_common_board_setup(blob, bd);
> -}
> -#endif
> -
> -int dram_init(void)
> -{
> - pxa2xx_dram_init();
> - gd->ram_size = PHYS_SDRAM_1_SIZE;
> - return 0;
> -}
> -
> -#ifdef CONFIG_CMD_USB
> -int board_usb_init(int index, enum usb_init_type init)
> -{
> - writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
> - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 |
> UHCHR_SSE),
> - UHCHR);
> -
> - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
> -
> - while (UHCHR & UHCHR_FSBIR)
> - ;
> -
> - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
> - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
> -
> - /* Clear any OTG Pin Hold */
> - if (readl(PSSR) & PSSR_OTGPH)
> - writel(readl(PSSR) | PSSR_OTGPH, PSSR);
> -
> - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
> - writel(readl(UHCRHDA) | 0x100, UHCRHDA);
> -
> - /* Set port power control mask bits, only 3 ports. */
> - writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
> -
> - /* enable port 2 */
> - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
> - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
> -
> - return 0;
> -}
> -
> -int board_usb_cleanup(int index, enum usb_init_type init)
> -{
> - return 0;
> -}
> -
> -void usb_board_stop(void)
> -{
> - writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
> - udelay(11);
> - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
> -
> - writel(readl(UHCCOMS) | 1, UHCCOMS);
> - udelay(10);
> -
> - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
> -
> - return;
> -}
> -#endif
> -
> -#ifdef CONFIG_DRIVER_DM9000
> -int board_eth_init(bd_t *bis)
> -{
> - return dm9000_initialize(bis);
> -}
> -#endif
> -
> -#ifdef CONFIG_CMD_MMC
> -int board_mmc_init(bd_t *bis)
> -{
> - pxa_mmc_register(0);
> - return 0;
> -}
> -#endif
> -
> -static const struct pxa_serial_platdata serial_platdata = {
> - .base = (struct pxa_uart_regs *)FFUART_BASE,
> - .port = FFUART_INDEX,
> - .baudrate = CONFIG_BAUDRATE,
> -};
> -
> -U_BOOT_DEVICE(pxa_serials) = {
> - .name = "serial_pxa",
> - .platdata = &serial_platdata,
> -};
> diff --git a/configs/colibri_pxa270_defconfig
> b/configs/colibri_pxa270_defconfig
> deleted file mode 100644
> index 2ff489f4a92..00000000000
> --- a/configs/colibri_pxa270_defconfig
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_TARGET_COLIBRI_PXA270=y
> -CONFIG_SYS_TEXT_BASE=0x0
> -CONFIG_ENV_VARS_UBOOT_CONFIG=y
> -CONFIG_NR_DRAM_BANKS=1
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200"
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_DISPLAY_BOARDINFO_LATE=y
> -# CONFIG_CMDLINE_EDITING is not set
> -# CONFIG_AUTO_COMPLETE is not set
> -# CONFIG_SYS_LONGHELP is not set
> -CONFIG_SYS_PROMPT="$ "
> -# CONFIG_CMD_ELF is not set
> -# CONFIG_CMD_EXPORTENV is not set
> -# CONFIG_CMD_IMPORTENV is not set
> -# CONFIG_CMD_LOADB is not set
> -# CONFIG_CMD_LOADS is not set
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_ENV_IS_IN_FLASH=y
> -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_DM=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_SYS_FLASH_PROTECTION=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_DM_SERIAL=y
> -CONFIG_PXA_SERIAL=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -# CONFIG_REGEX is not set
> -CONFIG_OF_LIBFDT=y
> -# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/colibri_pxa270.h
> b/include/configs/colibri_pxa270.h
> deleted file mode 100644
> index 622b02492dd..00000000000
> --- a/include/configs/colibri_pxa270.h
> +++ /dev/null
> @@ -1,188 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Toradex Colibri PXA270 configuration file
> - *
> - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
> - * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Board Configuration Options
> - */
> -#define CONFIG_CPU_PXA27X 1 /* Marvell
> PXA270 CPU */
> -/* Avoid overwriting factory configuration block */
> -#define CONFIG_BOARD_SIZE_LIMIT 0x40000
> -
> -/* We will never enable dcache because we have to setup MMU first */
> -#define CONFIG_SYS_DCACHE_OFF
> -
> -/*
> - * Environment settings
> - */
> -#define CONFIG_ENV_OVERWRITE
> -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
> -#define CONFIG_ARCH_CPU_INIT
> -#define CONFIG_BOOTCOMMAND
> \
> - "if fatload mmc 0 0xa0000000 uImage; then "
> \
> - "bootm 0xa0000000; "
> \
> - "fi; "
> \
> - "if usb reset && fatload usb 0 0xa0000000 uImage; then "
> \
> - "bootm 0xa0000000; "
> \
> - "fi; "
> \
> - "bootm 0xc0000;"
> -#define CONFIG_TIMESTAMP
> -#define CONFIG_CMDLINE_TAG
> -#define CONFIG_SETUP_MEMORY_TAGS
> -
> -/*
> - * Serial Console Configuration
> - */
> -
> -/*
> - * Bootloader Components Configuration
> - */
> -
> -/* I2C support */
> -#ifdef CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_PXA
> -#define CONFIG_PXA_STD_I2C
> -#define CONFIG_PXA_PWR_I2C
> -#define CONFIG_SYS_I2C_SPEED 100000
> -#endif
> -
> -/* LCD support */
> -#ifdef CONFIG_LCD
> -#define CONFIG_PXA_LCD
> -#define CONFIG_PXA_VGA
> -#define CONFIG_LCD_LOGO
> -#endif
> -
> -/*
> - * Networking Configuration
> - */
> -#ifdef CONFIG_CMD_NET
> -
> -#define CONFIG_DRIVER_DM9000 1
> -#define CONFIG_DM9000_BASE 0x08000000
> -#define DM9000_IO (CONFIG_DM9000_BASE)
> -#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
> -#define CONFIG_NET_RETRY_COUNT 10
> -
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#endif
> -
> -#define CONFIG_SYS_DEVICE_NULLDEV 1
> -
> -/*
> - * Clock Configuration
> - */
> -#define CONFIG_SYS_CPUSPEED 0x290
> /* 520MHz */
> -
> -/*
> - * DRAM Map
> - */
> -#define PHYS_SDRAM_1 0xa0000000
> /* SDRAM Bank #1 */
> -#define PHYS_SDRAM_1_SIZE 0x04000000 /*
> 64 MB */
> -
> -#define CONFIG_SYS_DRAM_BASE 0xa0000000
> /* CS0 */
> -#define CONFIG_SYS_DRAM_SIZE 0x04000000
> /* 64 MB DRAM */
> -
> -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest
> works on */
> -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4
> ... 8 MB in DRAM */
> -
> -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
> -
> -/*
> - * NOR FLASH
> - */
> -#ifdef CONFIG_CMD_FLASH
> -#define PHYS_FLASH_1 0x00000000
> /* Flash Bank #1 */
> -#define PHYS_FLASH_SIZE 0x02000000
> /* 32 MB */
> -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
> -
> -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
> -
> -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1
> -
> -#define CONFIG_SYS_FLASH_ERASE_TOUT (25 *
> CONFIG_SYS_HZ)
> -#define CONFIG_SYS_FLASH_WRITE_TOUT (25 *
> CONFIG_SYS_HZ)
> -#define CONFIG_SYS_FLASH_LOCK_TOUT (25 *
> CONFIG_SYS_HZ)
> -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 *
> CONFIG_SYS_HZ)
> -#endif
> -
> -#define CONFIG_SYS_MONITOR_BASE 0x0
> -#define CONFIG_SYS_MONITOR_LEN 0x40000
> -
> -/* Skip factory configuration block */
> -#define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_MONITOR_BASE +
> CONFIG_SYS_MONITOR_LEN + 0x40000)
> -#define CONFIG_ENV_SIZE 0x40000
> -#define CONFIG_ENV_SECT_SIZE 0x40000
> -
> -/*
> - * GPIO settings
> - */
> -#define CONFIG_SYS_GPSR0_VAL 0x00000000
> -#define CONFIG_SYS_GPSR1_VAL 0x00020000
> -#define CONFIG_SYS_GPSR2_VAL 0x0002c000
> -#define CONFIG_SYS_GPSR3_VAL 0x00000000
> -
> -#define CONFIG_SYS_GPCR0_VAL 0x00000000
> -#define CONFIG_SYS_GPCR1_VAL 0x00000000
> -#define CONFIG_SYS_GPCR2_VAL 0x00000000
> -#define CONFIG_SYS_GPCR3_VAL 0x00000000
> -
> -#define CONFIG_SYS_GPDR0_VAL 0xc8008000
> -#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
> -#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
> -#define CONFIG_SYS_GPDR3_VAL 0x0061e804
> -
> -#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
> -#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
> -#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
> -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
> -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
> -#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
> -#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
> -#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
> -
> -#define CONFIG_SYS_PSSR_VAL 0x30
> -
> -/*
> - * Clock settings
> - */
> -#define CONFIG_SYS_CKEN 0x00500240
> -#define CONFIG_SYS_CCCR 0x02000290
> -
> -/*
> - * Memory settings
> - */
> -#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
> -#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
> -#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
> -#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
> -#define CONFIG_SYS_MDREFR_VAL 0x2003a031
> -#define CONFIG_SYS_MDMRS_VAL 0x00220022
> -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
> -#define CONFIG_SYS_SXCNFG_VAL 0x40044004
> -
> -/*
> - * PCMCIA and CF Interfaces
> - */
> -#define CONFIG_SYS_MECR_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM0_VAL 0x00028307
> -#define CONFIG_SYS_MCMEM1_VAL 0x00014307
> -#define CONFIG_SYS_MCATT0_VAL 0x00038787
> -#define CONFIG_SYS_MCATT1_VAL 0x0001c787
> -#define CONFIG_SYS_MCIO0_VAL 0x0002830f
> -#define CONFIG_SYS_MCIO1_VAL 0x0001430f
> -
> -#include "pxa-common.h"
> -
> -#endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board
2018-11-26 7:57 ` Marcel Ziswiler
@ 2018-11-26 12:57 ` Tom Rini
2018-11-27 0:08 ` Simon Glass
1 sibling, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-26 12:57 UTC (permalink / raw)
To: u-boot
On Mon, Nov 26, 2018 at 07:57:10AM +0000, Marcel Ziswiler wrote:
> On Mon, 2018-11-19 at 08:53 -0700, Simon Glass wrote:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> NAK. I started working on PXA MMC driver which so far is not DM
> enabled. Hopefully, I have something ready later this week.
Thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board
2018-11-26 7:57 ` Marcel Ziswiler
2018-11-26 12:57 ` Tom Rini
@ 2018-11-27 0:08 ` Simon Glass
2018-11-27 12:24 ` Marek Vasut
1 sibling, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-27 0:08 UTC (permalink / raw)
To: u-boot
On Mon, 26 Nov 2018 at 00:57, Marcel Ziswiler
<marcel.ziswiler@toradex.com> wrote:
>
> On Mon, 2018-11-19 at 08:53 -0700, Simon Glass wrote:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> NAK. I started working on PXA MMC driver which so far is not DM
> enabled. Hopefully, I have something ready later this week.
Thanks Marcel, sounds good.
- Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board
2018-11-27 0:08 ` Simon Glass
@ 2018-11-27 12:24 ` Marek Vasut
0 siblings, 0 replies; 211+ messages in thread
From: Marek Vasut @ 2018-11-27 12:24 UTC (permalink / raw)
To: u-boot
On 11/27/2018 01:08 AM, Simon Glass wrote:
> On Mon, 26 Nov 2018 at 00:57, Marcel Ziswiler
> <marcel.ziswiler@toradex.com> wrote:
>>
>> On Mon, 2018-11-19 at 08:53 -0700, Simon Glass wrote:
>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
>>> Remove it.
>>
>> NAK. I started working on PXA MMC driver which so far is not DM
>> enabled. Hopefully, I have something ready later this week.
>
> Thanks Marcel, sounds good.
Thanks Marcel, much appreciated.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 41/93] arm: Remove work_92105 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (39 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 40/93] arm: Remove colibri_pxa270 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 42/93] arm: Remove omap3_pandora board Simon Glass
` (56 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/cpu/arm926ejs/lpc32xx/Kconfig | 1 -
board/work-microwave/work_92105/Kconfig | 24 --
board/work-microwave/work_92105/MAINTAINERS | 6 -
board/work-microwave/work_92105/Makefile | 10 -
board/work-microwave/work_92105/README | 91 -----
board/work-microwave/work_92105/work_92105.c | 76 ----
.../work_92105/work_92105_display.c | 348 ------------------
.../work_92105/work_92105_display.h | 13 -
.../work_92105/work_92105_spl.c | 84 -----
configs/work_92105_defconfig | 41 ---
include/configs/work_92105.h | 161 --------
11 files changed, 855 deletions(-)
delete mode 100644 board/work-microwave/work_92105/Kconfig
delete mode 100644 board/work-microwave/work_92105/MAINTAINERS
delete mode 100644 board/work-microwave/work_92105/Makefile
delete mode 100644 board/work-microwave/work_92105/README
delete mode 100644 board/work-microwave/work_92105/work_92105.c
delete mode 100644 board/work-microwave/work_92105/work_92105_display.c
delete mode 100644 board/work-microwave/work_92105/work_92105_display.h
delete mode 100644 board/work-microwave/work_92105/work_92105_spl.c
delete mode 100644 configs/work_92105_defconfig
delete mode 100644 include/configs/work_92105.h
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
index 407252c8c30..189884ad930 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
@@ -14,6 +14,5 @@ config TARGET_WORK_92105
endchoice
-source "board/work-microwave/work_92105/Kconfig"
endif
diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig
deleted file mode 100644
index 32632f5ab52..00000000000
--- a/board/work-microwave/work_92105/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if TARGET_WORK_92105
-
-config SYS_BOARD
- default "work_92105"
-
-config SYS_VENDOR
- default "work-microwave"
-
-config SYS_CONFIG_NAME
- default "work_92105"
-
-config CMD_HD44760
- bool "Enable 'hd44780' LCD-control comand"
- help
- This controls the LCD driver.
-
-config CMD_MAX6957
- bool "Enable 'max6957aax' PMIC command"
- help
- DEPRECATED: Needs conversion to driver model.
-
- This allows PMIC registers to be read and written.
-
-endif
diff --git a/board/work-microwave/work_92105/MAINTAINERS b/board/work-microwave/work_92105/MAINTAINERS
deleted file mode 100644
index 29a92c5ffe2..00000000000
--- a/board/work-microwave/work_92105/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-WORK_92105 BOARD
-M: Albert ARIBAUD <albert.aribaud@3adev.fr>
-S: Maintained
-F: board/work-microwave/work_92105/
-F: include/configs/work_92105.h
-F: configs/work_92105_defconfig
diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile
deleted file mode 100644
index e3803bb0431..00000000000
--- a/board/work-microwave/work_92105/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2014 DENX Software Engineering GmbH
-# Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
-
-ifdef CONFIG_SPL_BUILD
-obj-y += work_92105_spl.o
-else
-obj-y += work_92105.o work_92105_display.o
-endif
diff --git a/board/work-microwave/work_92105/README b/board/work-microwave/work_92105/README
deleted file mode 100644
index 3c256e0b2cd..00000000000
--- a/board/work-microwave/work_92105/README
+++ /dev/null
@@ -1,91 +0,0 @@
-Work_92105 from Work Microwave is an LPC3250- based board with the
-following features:
-
- - 64MB SDR DRAM
- - 1 GB SLC NAND, managed through MLC controller.
- - Ethernet
- - Ethernet + PHY SMSC8710
- - I2C:
- - EEPROM (24M01-compatible)
- - RTC (DS1374-compatible)
- - Temperature sensor (DS620)
- - DACs (2 x MAX518)
- - SPI (through SSP interface)
- - Port expander MAX6957
- - LCD display (HD44780-compatible), controlled
- through the port expander and DACs
-
-Standard SPL and U-Boot binaries
---------------------------------
-
-The default 'make' (or the 'make all') command will produce the
-following files:
-
-1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0.
- This file can be loaded in SRAM through a JTAG
- debugger or through the LPC32XX Service Boot
- mechanism.
-
-2. u-boot.bin The raw U-Boot image, which can be loaded in
- DDR through a JTAG debugger (for instance by
- breaking SPL after DDR init), or by a running
- U-Boot through e.g. 'loady' or 'tftp' and then
- executed with 'go'.
-
-3. u-boot.img A U-Boot image with a mkimage header prepended.
- SPL assumes (even when loaded through JTAG or
- Service Boot) that such an image will be found
- at offset 0x00040000 in NAND.
-
-NAND cold-boot binaries
------------------------
-
-The board can boot entirely from power-on with only SPL and U-Boot in
-NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce
-(in addition to spl/u-boot-spl.bin and u-boot.img if they were not made
-already) the following files:
-
-4. lpc32xx-spl.img spl/u-boot-spl.bin, with a LPC32XX boot header
- prepended. This header is required for the ROM
- code to load SPL into SRAM and branch into it.
- The content of this file is expected to reside
- in NAND at addresses 0x00000000 and 0x00020000
- (two copies).
-
-5. lpc32xx-boot-0.bin lpc32xx-spl.img, padded with 0xFF bytes to a
- size of 0x20000 bytes. This file covers exactly
- the reserved area for the first bootloader copy
- in NAND.
-
-6. lpc32xx-boot-1.bin Same as lpc32xx-boot-0.bin. This is intended to
- be used as the second bootloader copy.
-
-7. lpc32xx-full.bin lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and
- u-boot.img concatenated. This file represents
- the content of whole bootloader as present in
- NAND at offset 00x00000000.
-
-Flashing instructions
----------------------
-
-The following assumes a working U-Boot on the target, with the ability
-to load files into DDR.
-
-To update the whole bootloader:
-
- nand erase 0x00000000 0x80000
- (load lpc32xx-full.bin at location $loadaddr)
- nand write $loadaddr 0x00000000 $filesize
-
-To update SPL only (note the double nand write) :
-
- nand erase 0x00000000 0x40000
- (load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr)
- nand write $loadaddr 0x00000000 $filesize
- nand write $loadaddr 0x00020000 $filesize
-
-To update U-Boot only:
-
- nand erase 0x00040000 0x40000
- (load u-boot.img at location $loadaddr)
- nand write $loadaddr 0x00040000 $filesize
diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c
deleted file mode 100644
index eb2e7d7eb88..00000000000
--- a/board/work-microwave/work_92105/work_92105.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * WORK Microwave work_92105 board support
- *
- * (C) Copyright 2014 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/emc.h>
-#include <asm/arch/wdt.h>
-#include <asm/gpio.h>
-#include <spl.h>
-#include "work_92105_display.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
-
-void reset_periph(void)
-{
- setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
- udelay(150);
- writel(0, &wdt->mctrl);
- clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
-}
-
-int board_early_init_f(void)
-{
- /* initialize serial port for console */
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
- /* enable I2C, SSP, MAC, NAND */
- lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
- lpc32xx_ssp_init();
- lpc32xx_mac_init();
- lpc32xx_mlc_nand_init();
- /* Display must wait until after relocation and devices init */
- return 0;
-}
-
-#define GPO_19 115
-
-int board_early_init_r(void)
-{
- /* Set NAND !WP to 1 through GPO_19 */
- gpio_request(GPO_19, "NAND_nWP");
- gpio_direction_output(GPO_19, 1);
-
- /* initialize display */
- work_92105_display_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- reset_periph();
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
-
- return 0;
-}
diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c
deleted file mode 100644
index ffa0fcfa874..00000000000
--- a/board/work-microwave/work_92105/work_92105_display.c
+++ /dev/null
@@ -1,348 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * work_92105 display support
- *
- * (C) Copyright 2014 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * The work_92105 display is a HD44780-compatible module
- * controlled through a MAX6957AAX SPI port expander, two
- * MAX518 I2C DACs and native LPC32xx GPO 15.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-#include <asm/gpio.h>
-#include <spi.h>
-#include <i2c.h>
-#include <version.h>
-#include <vsprintf.h>
-
-/*
- * GPO 15 in port 3 is gpio 3*32+15 = 111
- */
-
-#define GPO_15 111
-
-/**
- * MAX6957AAX registers that we will be using
- */
-
-#define MAX6957_CONF 0x04
-
-#define MAX6957_CONF_08_11 0x0A
-#define MAX6957_CONF_12_15 0x0B
-#define MAX6957_CONF_16_19 0x0C
-
-/**
- * Individual gpio ports (one per gpio) to HD44780
- */
-
-#define MAX6957AAX_HD44780_RS 0x29
-#define MAX6957AAX_HD44780_R_W 0x2A
-#define MAX6957AAX_HD44780_EN 0x2B
-#define MAX6957AAX_HD44780_DATA 0x4C
-
-/**
- * Display controller instructions
- */
-
-/* Function set: eight bits, two lines, 8-dot font */
-#define HD44780_FUNCTION_SET 0x38
-
-/* Display ON / OFF: turn display on */
-#define HD44780_DISPLAY_ON_OFF_CONTROL 0x0C
-
-/* Entry mode: increment */
-#define HD44780_ENTRY_MODE_SET 0x06
-
-/* Clear */
-#define HD44780_CLEAR_DISPLAY 0x01
-
-/* Set DDRAM addr (to be ORed with exact address) */
-#define HD44780_SET_DDRAM_ADDR 0x80
-
-/* Set CGRAM addr (to be ORed with exact address) */
-#define HD44780_SET_CGRAM_ADDR 0x40
-
-/**
- * Default value for contrats
- */
-
-#define CONTRAST_DEFAULT 25
-
-/**
- * Define slave as a module-wide local to save passing it around,
- * plus we will need it after init for the "hd44780" command.
- */
-
-static struct spi_slave *slave;
-
-/*
- * Write a value into a MAX6957AAX register.
- */
-
-static void max6957aax_write(uint8_t reg, uint8_t value)
-{
- uint8_t dout[2];
-
- dout[0] = reg;
- dout[1] = value;
- gpio_set_value(GPO_15, 0);
- /* do SPI read/write (passing din==dout is OK) */
- spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END);
- gpio_set_value(GPO_15, 1);
-}
-
-/*
- * Read a value from a MAX6957AAX register.
- *
- * According to the MAX6957AAX datasheet, we should release the chip
- * select halfway through the read sequence, when the actual register
- * value is read; but the WORK_92105 hardware prevents the MAX6957AAX
- * SPI OUT from reaching the LPC32XX SIP MISO if chip is not selected.
- * so let's release the CS an hold it again while reading the result.
- */
-
-static uint8_t max6957aax_read(uint8_t reg)
-{
- uint8_t dout[2], din[2];
-
- /* send read command */
- dout[0] = reg | 0x80; /* set bit 7 to indicate read */
- dout[1] = 0;
- gpio_set_value(GPO_15, 0);
- /* do SPI read/write (passing din==dout is OK) */
- spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END);
- /* latch read command */
- gpio_set_value(GPO_15, 1);
- /* read register -- din = noop on xmit, din[1] = reg on recv */
- din[0] = 0;
- din[1] = 0;
- gpio_set_value(GPO_15, 0);
- /* do SPI read/write (passing din==dout is OK) */
- spi_xfer(slave, 16, din, din, SPI_XFER_BEGIN | SPI_XFER_END);
- /* end of read. */
- gpio_set_value(GPO_15, 1);
- return din[1];
-}
-
-static void hd44780_instruction(unsigned long instruction)
-{
- max6957aax_write(MAX6957AAX_HD44780_RS, 0);
- max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
- max6957aax_write(MAX6957AAX_HD44780_EN, 1);
- max6957aax_write(MAX6957AAX_HD44780_DATA, instruction);
- max6957aax_write(MAX6957AAX_HD44780_EN, 0);
- /* HD44780 takes 37 us for most instructions, 1520 for clear */
- if (instruction == HD44780_CLEAR_DISPLAY)
- udelay(2000);
- else
- udelay(100);
-}
-
-static void hd44780_write_char(char c)
-{
- max6957aax_write(MAX6957AAX_HD44780_RS, 1);
- max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
- max6957aax_write(MAX6957AAX_HD44780_EN, 1);
- max6957aax_write(MAX6957AAX_HD44780_DATA, c);
- max6957aax_write(MAX6957AAX_HD44780_EN, 0);
- /* HD44780 takes 37 us to write to DDRAM or CGRAM */
- udelay(100);
-}
-
-static void hd44780_write_str(char *s)
-{
- max6957aax_write(MAX6957AAX_HD44780_RS, 1);
- max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
- while (*s) {
- max6957aax_write(MAX6957AAX_HD44780_EN, 1);
- max6957aax_write(MAX6957AAX_HD44780_DATA, *s);
- max6957aax_write(MAX6957AAX_HD44780_EN, 0);
- s++;
- /* HD44780 takes 37 us to write to DDRAM or CGRAM */
- udelay(100);
- }
-}
-
-/*
- * Existing user code might expect these custom characters to be
- * recognized and displayed on the LCD
- */
-
-static u8 char_gen_chars[] = {
- /* #8, empty rectangle */
- 0x1F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x1F,
- /* #9, filled right arrow */
- 0x10, 0x18, 0x1C, 0x1E, 0x1C, 0x18, 0x10, 0x00,
- /* #10, filled left arrow */
- 0x01, 0x03, 0x07, 0x0F, 0x07, 0x03, 0x01, 0x00,
- /* #11, up and down arrow */
- 0x04, 0x0E, 0x1F, 0x00, 0x00, 0x1F, 0x0E, 0x04,
- /* #12, plus/minus */
- 0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x1F, 0x00,
- /* #13, fat exclamation mark */
- 0x06, 0x06, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00,
- /* #14, empty square */
- 0x00, 0x1F, 0x11, 0x11, 0x11, 0x1F, 0x00, 0x00,
- /* #15, struck out square */
- 0x00, 0x1F, 0x19, 0x15, 0x13, 0x1F, 0x00, 0x00,
-};
-
-static void hd44780_init_char_gen(void)
-{
- int i;
-
- hd44780_instruction(HD44780_SET_CGRAM_ADDR);
-
- for (i = 0; i < sizeof(char_gen_chars); i++)
- hd44780_write_char(char_gen_chars[i]);
-
- hd44780_instruction(HD44780_SET_DDRAM_ADDR);
-}
-
-void work_92105_display_init(void)
-{
- int claim_err;
- char *display_contrast_str;
- uint8_t display_contrast = CONTRAST_DEFAULT;
- uint8_t enable_backlight = 0x96;
-
- slave = spi_setup_slave(0, 0, 500000, 0);
-
- if (!slave) {
- printf("Failed to set up SPI slave\n");
- return;
- }
-
- claim_err = spi_claim_bus(slave);
-
- if (claim_err)
- debug("Failed to claim SPI bus: %d\n", claim_err);
-
- /* enable backlight */
- i2c_write(0x2c, 0x01, 1, &enable_backlight, 1);
-
- /* set display contrast */
- display_contrast_str = env_get("fwopt_dispcontrast");
- if (display_contrast_str)
- display_contrast = simple_strtoul(display_contrast_str,
- NULL, 10);
- i2c_write(0x2c, 0x00, 1, &display_contrast, 1);
-
- /* request GPO_15 as an output initially set to 1 */
- gpio_request(GPO_15, "MAX6957_nCS");
- gpio_direction_output(GPO_15, 1);
-
- /* enable MAX6957 portexpander */
- max6957aax_write(MAX6957_CONF, 0x01);
- /* configure pin 8 as input, pins 9..19 as outputs */
- max6957aax_write(MAX6957_CONF_08_11, 0x56);
- max6957aax_write(MAX6957_CONF_12_15, 0x55);
- max6957aax_write(MAX6957_CONF_16_19, 0x55);
-
- /* initialize HD44780 */
- max6957aax_write(MAX6957AAX_HD44780_EN, 0);
- hd44780_instruction(HD44780_FUNCTION_SET);
- hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL);
- hd44780_instruction(HD44780_ENTRY_MODE_SET);
-
- /* write custom character glyphs */
- hd44780_init_char_gen();
-
- /* Show U-Boot version, date and time as a sign-of-life */
- hd44780_instruction(HD44780_CLEAR_DISPLAY);
- hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0);
- hd44780_write_str(U_BOOT_VERSION);
- hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64);
- hd44780_write_str(U_BOOT_DATE);
- hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20);
- hd44780_write_str(U_BOOT_TIME);
-}
-
-#ifdef CONFIG_CMD_MAX6957
-
-static int do_max6957aax(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
-{
- int reg, val;
-
- if (argc != 3)
- return CMD_RET_USAGE;
- switch (argv[1][0]) {
- case 'r':
- case 'R':
- reg = simple_strtoul(argv[2], NULL, 0);
- val = max6957aax_read(reg);
- printf("MAX6957 reg 0x%02x read 0x%02x\n", reg, val);
- return 0;
- default:
- reg = simple_strtoul(argv[1], NULL, 0);
- val = simple_strtoul(argv[2], NULL, 0);
- max6957aax_write(reg, val);
- printf("MAX6957 reg 0x%02x wrote 0x%02x\n", reg, val);
- return 0;
- }
- return 1;
-}
-
-#ifdef CONFIG_SYS_LONGHELP
-static char max6957aax_help_text[] =
- "max6957aax - write or read display register:\n"
- "\tmax6957aax R|r reg - read display register;\n"
- "\tmax6957aax reg val - write display register.";
-#endif
-
-U_BOOT_CMD(
- max6957aax, 6, 1, do_max6957aax,
- "SPI MAX6957 display write/read",
- max6957aax_help_text
-);
-#endif /* CONFIG_CMD_MAX6957 */
-
-#ifdef CONFIG_CMD_HD44760
-
-/*
- * We need the HUSH parser because we need string arguments, and
- * only HUSH can understand them.
- */
-
-#if !defined(CONFIG_HUSH_PARSER)
-#error CONFIG_CMD_HD44760 requires CONFIG_HUSH_PARSER
-#endif
-
-static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- char *cmd;
-
- if (argc != 3)
- return CMD_RET_USAGE;
-
- cmd = argv[1];
-
- if (strcasecmp(cmd, "cmd") == 0)
- hd44780_instruction(simple_strtol(argv[2], NULL, 0));
- else if (strcasecmp(cmd, "data") == 0)
- hd44780_write_char(simple_strtol(argv[2], NULL, 0));
- else if (strcasecmp(cmd, "str") == 0)
- hd44780_write_str(argv[2]);
- return 0;
-}
-
-#ifdef CONFIG_SYS_LONGHELP
-static char hd44780_help_text[] =
- "hd44780 - control LCD driver:\n"
- "\thd44780 cmd <val> - send command <val> to driver;\n"
- "\thd44780 data <val> - send data <val> to driver;\n"
- "\thd44780 str \"<text>\" - send \"<text>\" to driver.";
-#endif
-
-U_BOOT_CMD(
- hd44780, 6, 1, do_hd44780,
- "HD44780 LCD driver control",
- hd44780_help_text
-);
-#endif /* CONFIG_CMD_HD44760 */
diff --git a/board/work-microwave/work_92105/work_92105_display.h b/board/work-microwave/work_92105/work_92105_display.h
deleted file mode 100644
index 17a9aa04e02..00000000000
--- a/board/work-microwave/work_92105/work_92105_display.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * work_92105 display support interface
- *
- * (C) Copyright 2014 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * The work_92105 display is a HD44780-compatible module
- * controlled through a MAX6957AAX SPI port expander, two
- * MAX518 I2C DACs and native LPC32xx GPO 15.
- */
-
-void work_92105_display_init(void);
diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c
deleted file mode 100644
index a31553a2d25..00000000000
--- a/board/work-microwave/work_92105/work_92105_spl.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * WORK Microwave work_92105 board support
- *
- * (C) Copyright 2014 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-#include <asm/gpio.h>
-#include <spl.h>
-#include "work_92105_display.h"
-
-struct emc_dram_settings dram_64mb = {
- .cmddelay = 0x0001C000,
- .config0 = 0x00005682,
- .rascas0 = 0x00000302,
- .rdconfig = 0x00000011,
- .trp = 52631578,
- .tras = 20833333,
- .tsrex = 12500000,
- .twr = 66666666,
- .trc = 13888888,
- .trfc = 10256410,
- .txsr = 12500000,
- .trrd = 1,
- .tmrd = 1,
- .tcdlr = 0,
- .refresh = 128000,
- .mode = 0x00018000,
- .emode = 0x02000000
-};
-
-const struct emc_dram_settings dram_128mb = {
- .cmddelay = 0x0001C000,
- .config0 = 0x00005882,
- .rascas0 = 0x00000302,
- .rdconfig = 0x00000011,
- .trp = 52631578,
- .tras = 22222222,
- .tsrex = 8333333,
- .twr = 66666666,
- .trc = 14814814,
- .trfc = 10256410,
- .txsr = 8333333,
- .trrd = 1,
- .tmrd = 1,
- .tcdlr = 0,
- .refresh = 128000,
- .mode = 0x00030000,
- .emode = 0x02000000
-};
-
-void spl_board_init(void)
-{
- /* initialize serial port for console */
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
- /* initialize console */
- preloader_console_init();
- /* init DDR and NAND to chainload U-Boot */
- ddr_init(&dram_128mb);
- /*
- * If this is actually a 64MB module, then the highest column
- * bit in any address will be ignored, and thus address 0x80000000
- * should be mirrored at address 0x80000800. Test this.
- */
- writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */
- writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */
- if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ {
- /* actually 64MB mirrored: reconfigure controller */
- ddr_init(&dram_64mb);
- }
- /* initialize NAND controller to load U-Boot from NAND */
- lpc32xx_mlc_nand_init();
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_NAND;
-}
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
deleted file mode 100644
index 105e51a4001..00000000000
--- a/configs/work_92105_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_LPC32XX=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_WORK_92105=y
-CONFIG_CMD_HD44760=y
-CONFIG_CMD_MAX6957=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS2,115200n8"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_MMC is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_LPC32XX_SSP=y
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
deleted file mode 100644
index 67b5e9aa113..00000000000
--- a/include/configs/work_92105.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * WORK Microwave work_92105 board configuration file
- *
- * (C) Copyright 2014 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- */
-
-#ifndef __CONFIG_WORK_92105_H__
-#define __CONFIG_WORK_92105_H__
-
-/* SoC and board defines */
-#include <linux/sizes.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Define work_92105 machine type by hand -- done only for compatibility
- * with original board code
- */
-#define CONFIG_MACH_TYPE 736
-
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * Memory configurations
- */
-#define CONFIG_SYS_MALLOC_LEN SZ_1M
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
- - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
-
-/*
- * Ethernet Driver
- */
-
-#define CONFIG_PHY_SMSC
-#define CONFIG_LPC32XX_ETH
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
-
-/*
- * I2C driver
- */
-
-#define CONFIG_SYS_I2C_LPC32XX
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SPEED 350000
-
-/*
- * I2C EEPROM
- */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * I2C RTC
- */
-
-#define CONFIG_RTC_DS1374
-
-/*
- * U-Boot General Configurations
- */
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * NAND chip timings for FIXME: which one?
- */
-
-#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
-#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
-#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
-#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
-#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
-#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
-#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
-
-/*
- * NAND
- */
-
-/* driver configuration */
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
-#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
-#define CONFIG_NAND_LPC32XX_MLC
-
-/*
- * GPIO
- */
-
-#define CONFIG_LPC32XX_GPIO
-
-/*
- * SSP/SPI/DISPLAY
- */
-
-#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
-/*
- * Environment
- */
-
-#define CONFIG_ENV_SIZE 0x00020000
-#define CONFIG_ENV_OFFSET 0x00100000
-#define CONFIG_ENV_OFFSET_REDUND 0x00120000
-#define CONFIG_ENV_ADDR 0x80000100
-
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x80008000
-
-/*
- * SPL
- */
-
-/* SPL will be executed at offset 0 */
-#define CONFIG_SPL_TEXT_BASE 0x00000000
-/* SPL will use SRAM as stack */
-#define CONFIG_SPL_STACK 0x0000FFF8
-/* Use the framework and generic lib */
-/* SPL will use serial */
-/* SPL will load U-Boot from NAND offset 0x40000 */
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
-#define CONFIG_SPL_PAD_TO 0x20000
-/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-
-/*
- * Include SoC specific configuration
- */
-#include <asm/arch/config.h>
-
-#endif /* __CONFIG_WORK_92105_H__*/
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 42/93] arm: Remove omap3_pandora board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (40 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 41/93] arm: Remove work_92105 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 43/93] arm: Remove cl-som-imx7 board Simon Glass
` (55 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/pandora/Kconfig | 9 -
board/pandora/MAINTAINERS | 6 -
board/pandora/Makefile | 6 -
board/pandora/pandora.c | 147 -----------
board/pandora/pandora.h | 391 ------------------------------
configs/omap3_pandora_defconfig | 40 ---
include/configs/omap3_pandora.h | 69 ------
8 files changed, 669 deletions(-)
delete mode 100644 board/pandora/Kconfig
delete mode 100644 board/pandora/MAINTAINERS
delete mode 100644 board/pandora/Makefile
delete mode 100644 board/pandora/pandora.c
delete mode 100644 board/pandora/pandora.h
delete mode 100644 configs/omap3_pandora_defconfig
delete mode 100644 include/configs/omap3_pandora.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 8970a8023cb..d2d4d2b3809 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -201,7 +201,6 @@ source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/ti/am3517crane/Kconfig"
-source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig
deleted file mode 100644
index 0b338180082..00000000000
--- a/board/pandora/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_OMAP3_PANDORA
-
-config SYS_BOARD
- default "pandora"
-
-config SYS_CONFIG_NAME
- default "omap3_pandora"
-
-endif
diff --git a/board/pandora/MAINTAINERS b/board/pandora/MAINTAINERS
deleted file mode 100644
index e12351735c6..00000000000
--- a/board/pandora/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PANDORA BOARD
-M: Grazvydas Ignotas <notasas@gmail.com>
-S: Maintained
-F: board/pandora/
-F: include/configs/omap3_pandora.h
-F: configs/omap3_pandora_defconfig
diff --git a/board/pandora/Makefile b/board/pandora/Makefile
deleted file mode 100644
index c05c8fb854b..00000000000
--- a/board/pandora/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := pandora.o
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
deleted file mode 100644
index a9aae7951d9..00000000000
--- a/board/pandora/pandora.c
+++ /dev/null
@@ -1,147 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
- *
- * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "pandora.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TWL4030_BB_CFG_BBCHEN (1 << 4)
-#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
-#define TWL4030_BB_CFG_BBISEL_500UA 2
-
-#define CONTROL_WKUP_CTRL 0x48002a5c
-#define GPIO_IO_PWRDNZ (1 << 6)
-#define PBIASLITEVMODE1 (1 << 8)
-
-static const struct ns16550_platdata pandora_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(pandora_uart) = {
- "ns16550_serial",
- &pandora_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-static void set_output_gpio(unsigned int gpio, int value)
-{
- int ret;
-
- ret = gpio_request(gpio, "");
- if (ret != 0) {
- printf("could not request GPIO %u\n", gpio);
- return;
- }
- ret = gpio_direction_output(gpio, value);
- if (ret != 0)
- printf("could not set GPIO %u to %d\n", gpio, value);
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- t2_t *t2_base = (t2_t *)T2_BASE;
- u32 pbias_lite;
-
- twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
-
- /* set up dual-voltage GPIOs to 1.8V */
- pbias_lite = readl(&t2_base->pbias_lite);
- pbias_lite &= ~PBIASLITEVMODE1;
- pbias_lite |= PBIASLITEPWRDNZ1;
- writel(pbias_lite, &t2_base->pbias_lite);
- if (get_cpu_family() == CPU_OMAP36XX)
- writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
- CONTROL_WKUP_CTRL);
-
- /* make sure audio and BT chips are in powerdown state */
- set_output_gpio(14, 0);
- set_output_gpio(15, 0);
- set_output_gpio(118, 0);
-
- /* enable USB supply */
- set_output_gpio(164, 1);
-
- /* wifi needs a short pulse to enter powersave state */
- set_output_gpio(23, 1);
- udelay(5000);
- gpio_direction_output(23, 0);
-
- /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
- TWL4030_PM_RECEIVER_BB_CFG,
- TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
- TWL4030_BB_CFG_BBISEL_500UA);
-
- omap_die_id_display();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_PANDORA();
- if (get_cpu_family() == CPU_OMAP36XX) {
- MUX_PANDORA_3730();
- }
-}
-
-#ifdef CONFIG_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h
deleted file mode 100644
index 9c4c5d1cd79..00000000000
--- a/board/pandora/pandora.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
- */
-#ifndef _PANDORA_H_
-#define _PANDORA_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 Pandora",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_PANDORA() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*GPIO based game buttons*/\
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\
- MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*GPIO_106 - B*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*GPIO_107 - R2*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109 - X*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M4)) /*GPIO_110 - UP*/\
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M4)) /*GPIO_111 - A*/\
- /*Audio Interface To External DAC (Headphone, Speakers)*/\
- MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\
- /* - nPOWERDOWN_DAC*/\
- /*Expansion card 1*/\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
- /*Expansion card 2*/\
- MUX_VAL(CP(MMC2_CLK), (IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\
- MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
- /*SDIO Interface to WIFI Module*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /*MMC3_CLK*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
- /*Audio Interface To Bluetooth chip*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
- /*Digital Interface to Bluetooth (UART)*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- /*Audio Interface to Triton2 chip (TPS65950)*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
- /*GPIO definitions for muxed pins on AV connector*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M4)) /*GPIO_144,*/\
- /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)) /*GPIO_145,*/\
- /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)) /*GPIO_146,*/\
- /*UART2_TX*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\
- /*UART2_RX*/\
- /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
- /*RX pulled up to avoid noise when nothing is connected to serial port*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
- /*LEDs (Controlled by OMAP)*/\
- MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\
- /* - LED_MMC1*/\
- MUX_VAL(CP(MMC1_DAT7), (IDIS | PTD | DIS | M4)) /*GPIO_129*/\
- /* - LED_MMC2*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
- /* - LED_BT*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- /* - LED_WIFI*/\
- /*Switches*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\
- /* - nHOLD_SWITCH*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*GPIO_108*/\
- /* - nLID_SWITCH*/\
- /*External IRQs*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*GPIO_94*/\
- /* - nTOUCH_IRQ*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\
- /* - WIFI_IRQ*/\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
- /* - nIRQ_NUB1*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
- /* - nIRQ_NUB2*/\
- /*Various other stuff*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\
- /* - nOC_USB5*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\
- /* - MSECURE*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M4)) /*GPIO_115*/\
- /* - POP_OVERHEAT*/\
- /*External Resets and Enables*/\
- MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\
- /* - nHDPHN_SHUTDOWN*/\
- MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_15*/\
- /* - nBT_SHUTDOWN*/\
- MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_23*/\
- /* - nWIFI_RESET*/\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157*/\
- /* - nLCD_RESET*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- /* - RESET_NUBS*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*GPIO_164*/\
- /* - EN_USB_5V*/\
- /*Spare GPIOs*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | EN | M4)) /*GPIO_65*/\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*GPIO_95*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) /*GPIO_167*/\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /*GPIO_170*/\
- /*HS USB OTG Port (connects to HSUSB0)*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- /*I2C Ports*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL - T2_CTRL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA - T2_CTRL*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL - NUBS*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA - NUBS*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL - T2_SR*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA - T2_SR*/\
- /*Serial Interface (Touch, LCD control)*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
- MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0 - TOUCH*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTU | EN | M0)) /*McSPI1_CS1 - LCD*/\
- /*HS USB HOST Port (connects to HSUSB2)*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*USB_HOST_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D1*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*USB_HOST_D2*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*USB_HOST_D3*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*USB_HOST_D4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*USB_HOST_D5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*USB_HOST_D6*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*USB_HOST_D7*/\
- MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_16*/\
- /* - nRESET_USB_HOST*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- /*JTAG*/\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- /*Die to Die stuff*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm*/\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq*/\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-#define MUX_PANDORA_3730() \
- MUX_VAL(CP(GPIO126), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
- MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
- MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\
- MUX_VAL(CP(GPIO129), (IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/
-
-#endif
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
deleted file mode 100644
index fb87d0da176..00000000000
--- a/configs/omap3_pandora_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80008000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_OMAP3_PANDORA=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SYS_PROMPT="Pandora # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-# CONFIG_REGEX is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
deleted file mode 100644
index 82c66c4b8c4..00000000000
--- a/include/configs/omap3_pandora.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008-2010
- * Gražvydas Ignotas <notasas@gmail.com>
- *
- * Configuration settings for the OMAP3 Pandora.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* override base for compatibility with MLO the device ships with */
-
-#include <configs/ti_omap3_common.h>
-
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-
-
-#define CONFIG_BOOTCOMMAND \
- "run distro_bootcmd; " \
- "setenv bootargs ${bootargs_ubi}; " \
- "if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \
- "source ${loadaddr}; " \
- "fi; " \
- "ubi part boot && ubifsmount ubi:boot && " \
- "ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
-
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "usbtty=cdc_acm\0" \
- "bootargs_ubi=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
- "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- BOOTENV \
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 43/93] arm: Remove cl-som-imx7 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (41 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 42/93] arm: Remove omap3_pandora board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 44/93] arm: Remove devkit8000 board Simon Glass
` (54 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx7/Kconfig | 1 -
board/compulab/cl-som-imx7/Kconfig | 28 --
board/compulab/cl-som-imx7/MAINTAINERS | 6 -
board/compulab/cl-som-imx7/Makefile | 17 --
board/compulab/cl-som-imx7/cl-som-imx7.c | 331 -----------------------
board/compulab/cl-som-imx7/common.c | 45 ---
board/compulab/cl-som-imx7/common.h | 31 ---
board/compulab/cl-som-imx7/mux.c | 141 ----------
board/compulab/cl-som-imx7/spl.c | 210 --------------
configs/cl-som-imx7_defconfig | 67 -----
include/configs/cl-som-imx7.h | 182 -------------
11 files changed, 1059 deletions(-)
delete mode 100644 board/compulab/cl-som-imx7/Kconfig
delete mode 100644 board/compulab/cl-som-imx7/MAINTAINERS
delete mode 100644 board/compulab/cl-som-imx7/Makefile
delete mode 100644 board/compulab/cl-som-imx7/cl-som-imx7.c
delete mode 100644 board/compulab/cl-som-imx7/common.c
delete mode 100644 board/compulab/cl-som-imx7/common.h
delete mode 100644 board/compulab/cl-som-imx7/mux.c
delete mode 100644 board/compulab/cl-som-imx7/spl.c
delete mode 100644 configs/cl-som-imx7_defconfig
delete mode 100644 include/configs/cl-som-imx7.h
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 63b90f99500..248e5003575 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -65,7 +65,6 @@ endchoice
config SYS_SOC
default "mx7"
-source "board/compulab/cl-som-imx7/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
diff --git a/board/compulab/cl-som-imx7/Kconfig b/board/compulab/cl-som-imx7/Kconfig
deleted file mode 100644
index 6d69cf31f44..00000000000
--- a/board/compulab/cl-som-imx7/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if TARGET_CL_SOM_IMX7
-
-config SYS_BOARD
- default "cl-som-imx7"
-
-config SYS_VENDOR
- default "compulab"
-
-config SYS_CONFIG_NAME
- default "cl-som-imx7"
-
-config SYS_MMC_DEV
- int
- default 0
-
-config SYS_USB_DEV
- int
- default 0
-
-config SYS_MMC_IMG_LOAD_PART
- int
- default 1
-
-config SYS_USB_IMG_LOAD_PART
- int
- default 1
-
-endif
diff --git a/board/compulab/cl-som-imx7/MAINTAINERS b/board/compulab/cl-som-imx7/MAINTAINERS
deleted file mode 100644
index 2b917a5c807..00000000000
--- a/board/compulab/cl-som-imx7/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CL-SOM-IMX7 BOARD
-M: Uri Mashiach <uri.mashiach@compulab.co.il>
-S: Maintained
-F: board/compulab/cl-som-imx7
-F: include/configs/cl-som-imx7.h
-F: configs/cl-som-imx7_defconfig
diff --git a/board/compulab/cl-som-imx7/Makefile b/board/compulab/cl-som-imx7/Makefile
deleted file mode 100644
index 8f0e068b7e9..00000000000
--- a/board/compulab/cl-som-imx7/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile
-#
-# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
-#
-# Author: Uri Mashiach <uri.mashiach@compulab.co.il>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mux.o common.o
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += cl-som-imx7.o
-endif
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
deleted file mode 100644
index 1bc33b0a7ba..00000000000
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ /dev/null
@@ -1,331 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot board functions for CompuLab CL-SOM-iMX7 module
- *
- * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <common.h>
-#include <environment.h>
-#include <mmc.h>
-#include <phy.h>
-#include <netdev.h>
-#include <fsl_esdhc.h>
-#include <power/pmic.h>
-#include <power/pfuze3000_pmic.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/arch-mx7/mx7-pins.h>
-#include <asm/arch-mx7/sys_proto.h>
-#include <asm/arch-mx7/clock.h>
-#include "../common/eeprom.h"
-#include "common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SYS_I2C_MXC
-
-#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS)
-
-#define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6)
-#define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7)
-
-static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
- MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
- MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
- },
- .sda = {
- .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
- MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
- MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
- },
-};
-
-/*
- * cl_som_imx7_setup_i2c() - I2C pinmux configuration.
- */
-static void cl_som_imx7_setup_i2c(void)
-{
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
-}
-#else /* !CONFIG_SYS_I2C_MXC */
-static void cl_som_imx7_setup_i2c(void) {}
-#endif /* CONFIG_SYS_I2C_MXC */
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-
-#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
-
-static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
- {USDHC1_BASE_ADDR, 0, 4},
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 USDHC1
- * mmc2 USDHC3 (eMMC)
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- cl_som_imx7_usdhc1_pads_set();
- gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
- cl_som_imx7_usdhc_cfg[0].sdhc_clk =
- mxc_get_clock(MXC_ESDHC_CLK);
- break;
- case 1:
- cl_som_imx7_usdhc3_emmc_pads_set();
- gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
- gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
- udelay(500);
- gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
- cl_som_imx7_usdhc_cfg[1].sdhc_clk =
- mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers "
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif /* CONFIG_FSL_ESDHC */
-
-#ifdef CONFIG_FEC_MXC
-
-#define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4)
-
-/*
- * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
- */
-static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* Ar8031 phy SmartEEE feature cause link status generates glitch,
- * which cause ethernet link down/up issue, so disable SmartEEE
- */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= ~(0x1 << 8);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- cl_som_imx7_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-/*
- * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
- *
- * @env_var: MAC address environment variable
- * @eeprom_bus: I2C bus of the environment EEPROM
- *
- * @return: 0 on success, < 0 on failure
- */
-static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
-{
- int ret;
- unsigned char enetaddr[6];
-
- ret = eth_env_get_enetaddr(env_var, enetaddr);
- if (ret)
- return 0;
-
- ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
- if (ret)
- return ret;
-
- ret = is_valid_ethaddr(enetaddr);
- if (!ret)
- return -1;
-
- return eth_env_set_enetaddr(env_var, enetaddr);
-}
-
-#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
-
-int board_eth_init(bd_t *bis)
-{
- /* set Ethernet MAC address environment */
- cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
- /* Ethernet interface pinmux configuration */
- cl_som_imx7_phy1_rst_pads_set();
- cl_som_imx7_fec1_pads_set();
- /* PHY reset */
- gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
- gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
- mdelay(10);
- gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
- /* MAC initialization */
- return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
- CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-}
-
-/*
- * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
- * - ENET1 reference clock mode select.
- * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
- */
-static void cl_som_imx7_setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
- = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
- clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
- (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
- IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
-
- set_clk_enet(ENET_125MHZ);
-}
-#else /* !CONFIG_FEC_MXC */
-static void cl_som_imx7_setup_fec(void) {}
-#endif /* CONFIG_FEC_MXC */
-
-#ifdef CONFIG_SPI
-
-static void cl_som_imx7_spi_init(void)
-{
- cl_som_imx7_espi1_pads_set();
-}
-#else /* !CONFIG_SPI */
-static void cl_som_imx7_spi_init(void) {}
-#endif /* CONFIG_SPI */
-
-int board_early_init_f(void)
-{
- cl_som_imx7_uart1_pads_set();
- cl_som_imx7_usb_otg1_pads_set();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- cl_som_imx7_setup_i2c();
- cl_som_imx7_setup_fec();
- cl_som_imx7_spi_init();
-
- return 0;
-}
-
-#ifdef CONFIG_POWER
-#define I2C_PMIC 0
-int power_init_board(void)
-{
- struct pmic *p;
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE3000");
- ret = pmic_probe(p);
- if (ret)
- return ret;
-
- pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
-
- /* disable Low Power Mode during standby mode */
- pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
-
- return 0;
-}
-#endif /* CONFIG_POWER */
-
-/*
- * cl_som_imx7_setup_wdog() - watchdog configuration.
- * - Output WDOG_B signal to reset external pmic.
- * - Suspend the watchdog timer during low-power modes.
- */
-void cl_som_imx7_setup_wdog(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- cl_som_imx7_wdog_pads_set();
- set_wdog_reset(wdog);
- /*
- * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
- * since we use PMIC_PWRON to reset the board.
- */
- clrsetbits_le16(&wdog->wcr, 0, 0x10);
-}
-
-int board_late_init(void)
-{
- env_set("board_name", "CL-SOM-iMX7");
- cl_som_imx7_setup_wdog();
- return 0;
-}
-
-int checkboard(void)
-{
- char *mode;
-
- if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
- mode = "secure";
- else
- mode = "non-secure";
-
- printf("Board: CL-SOM-iMX7 in %s mode\n", mode);
-
- return 0;
-}
diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c
deleted file mode 100644
index e0f90fd5c48..00000000000
--- a/board/compulab/cl-som-imx7/common.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module
- *
- * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <asm-generic/gpio.h>
-#include "common.h"
-
-#ifdef CONFIG_SPI
-
-#define CL_SOM_IMX7_GPIO_SPI_CS IMX_GPIO_NR(4, 19)
-
-int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
-{
- return CL_SOM_IMX7_GPIO_SPI_CS;
-}
-
-#endif /* CONFIG_SPI */
-
-#ifdef CONFIG_FSL_ESDHC
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD);
- break;
- case USDHC3_BASE_ADDR:
- ret = 1; /* Assume uSDHC3 emmc is always present */
- break;
- }
-
- return ret;
-}
-
-#endif /* CONFIG_FSL_ESDHC */
diff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h
deleted file mode 100644
index 8b15a59abeb..00000000000
--- a/board/compulab/cl-som-imx7/common.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module
- *
- * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)
-
-#ifdef CONFIG_FSL_ESDHC
-#define CL_SOM_IMX7_GPIO_USDHC1_CD IMX_GPIO_NR(5, 0)
-PADS_SET_PROT(usdhc1_pads);
-#endif /* CONFIG_FSL_ESDHC */
-PADS_SET_PROT(uart1_pads);
-#ifdef CONFIG_SPI
-PADS_SET_PROT(espi1_pads);
-#endif /* CONFIG_SPI */
-
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_ESDHC
-PADS_SET_PROT(usdhc3_emmc_pads);
-#endif /* CONFIG_FSL_ESDHC */
-#ifdef CONFIG_FEC_MXC
-PADS_SET_PROT(phy1_rst_pads);
-PADS_SET_PROT(fec1_pads);
-#endif /* CONFIG_FEC_MXC */
-PADS_SET_PROT(usb_otg1_pads);
-PADS_SET_PROT(wdog_pads);
-#endif /* !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c
deleted file mode 100644
index e29d2deaf2b..00000000000
--- a/board/compulab/cl-som-imx7/mux.c
+++ /dev/null
@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module
- *
- * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <common.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/arch-mx7/mx7-pins.h>
-
-#define PADS_SET(pads_array) \
-void cl_som_imx7_##pads_array##_set(void) \
-{ \
- imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \
-}
-
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | \
- PAD_CTL_PUS_PU47KOHM)
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-PADS_SET(usdhc1_pads)
-
-#endif /* CONFIG_FSL_ESDHC */
-
-#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
- PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-PADS_SET(uart1_pads)
-
-#ifdef CONFIG_SPI
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \
- PAD_CTL_DSE_3P3V_32OHM)
-
-#define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \
- PAD_CTL_SRE_SLOW)
-
-static iomux_v3_cfg_t const espi1_pads[] = {
- MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
-};
-
-PADS_SET(espi1_pads)
-
-#endif /* CONFIG_SPI */
-
-#ifndef CONFIG_SPL_BUILD
-
-#ifdef CONFIG_FSL_ESDHC
-
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
- MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-PADS_SET(usdhc3_emmc_pads)
-
-#endif /* CONFIG_FSL_ESDHC */
-
-#ifdef CONFIG_FEC_MXC
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM)
-
-static iomux_v3_cfg_t const phy1_rst_pads[] = {
- /* PHY1 RST */
- MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
-};
-
-PADS_SET(phy1_rst_pads)
-
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-};
-
-PADS_SET(fec1_pads)
-
-#endif /* CONFIG_FEC_MXC */
-
-static iomux_v3_cfg_t const usb_otg1_pads[] = {
- MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-PADS_SET(usb_otg1_pads)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-PADS_SET(wdog_pads)
-
-#endif /* !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c
deleted file mode 100644
index 76a4c8beb02..00000000000
--- a/board/compulab/cl-som-imx7/spl.c
+++ /dev/null
@@ -1,210 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL board functions for CompuLab CL-SOM-iMX7 module
- *
- * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <common.h>
-#include <spl.h>
-#include <fsl_esdhc.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/arch-mx7/mx7-pins.h>
-#include <asm/arch-mx7/clock.h>
-#include <asm/arch-mx7/mx7-ddr.h>
-#include "common.h"
-
-#ifdef CONFIG_FSL_ESDHC
-
-static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
- USDHC1_BASE_ADDR, 0, 4};
-
-int board_mmc_init(bd_t *bis)
-{
- cl_som_imx7_usdhc1_pads_set();
- cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
-}
-#endif /* CONFIG_FSL_ESDHC */
-
-static iomux_v3_cfg_t const led_pads[] = {
- MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
- PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
-};
-
-static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
- .init1 = 0x00690000,
- .init0 = 0x00020083,
- .init3 = 0x09300004,
- .init4 = 0x04080000,
- .init5 = 0x00100004,
- .rankctl = 0x0000033F,
- .dramtmg1 = 0x0007020E,
- .dramtmg2 = 0x03040407,
- .dramtmg3 = 0x00002006,
- .dramtmg4 = 0x04020305,
- .dramtmg5 = 0x03030202,
- .dramtmg8 = 0x00000803,
- .zqctl0 = 0x00810021,
- .dfitmg0 = 0x02098204,
- .dfitmg1 = 0x00030303,
- .dfiupd0 = 0x80400003,
- .dfiupd1 = 0x00100020,
- .dfiupd2 = 0x80100004,
- .addrmap4 = 0x00000F0F,
- .odtcfg = 0x06000604,
- .odtmap = 0x00000001,
-};
-
-static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = {
- .pctrl_0 = 0x00000001,
-};
-
-static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
- .phy_con0 = 0x17420F40,
- .phy_con1 = 0x10210100,
- .phy_con4 = 0x00060807,
- .mdll_con0 = 0x1010007E,
- .drvds_con0 = 0x00000D6E,
- .cmd_sdll_con0 = 0x00000010,
- .offset_lp_con0 = 0x0000000F,
-};
-
-struct mx7_calibration cl_som_imx7_spl_calib_param = {
- .num_val = 5,
- .values = {
- 0x0E407304,
- 0x0E447304,
- 0x0E447306,
- 0x0E447304,
- 0x0E407304,
- },
-};
-
-static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size)
-{
- switch (ram_size) {
- case SZ_256M:
- cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001;
- cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
- cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
- cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000014;
- cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00151515;
- cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x03030303;
- cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0303;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
- break;
- case SZ_512M:
- cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
- cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
- cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
- cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000015;
- cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00161616;
- cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
- cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0404;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
- break;
- case SZ_1G:
- cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
- cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
- cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
- cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000016;
- cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00171717;
- cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
- cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F040404;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x02020202;
- break;
- case SZ_2G:
- cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
- cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x0040005E;
- cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A;
- cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000018;
- cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00181818;
- cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
- cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x04040404;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A;
- cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
- break;
- }
-
- mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val,
- &cl_som_imx7_spl_ddrc_mp_val,
- &cl_som_imx7_spl_ddr_phy_regs_val,
- &cl_som_imx7_spl_calib_param);
-}
-
-static void cl_som_imx7_spl_dram_cfg(void)
-{
- ulong ram_size_test, ram_size = 0;
-
- for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) {
- cl_som_imx7_spl_dram_cfg_size(ram_size);
- ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
- if (ram_size_test == ram_size)
- break;
- }
-
- if (ram_size < SZ_256M) {
- puts("!!!ERROR!!! DRAM detection failed!!!\n");
- hang();
- }
-}
-
-#ifdef CONFIG_SPL_SPI_SUPPORT
-
-static void cl_som_imx7_spl_spi_init(void)
-{
- cl_som_imx7_espi1_pads_set();
-}
-#else /* !CONFIG_SPL_SPI_SUPPORT */
-static void cl_som_imx7_spl_spi_init(void) {}
-#endif /* CONFIG_SPL_SPI_SUPPORT */
-
-void board_init_f(ulong dummy)
-{
- imx_iomux_v3_setup_multiple_pads(led_pads, 1);
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
- /* setup GP timer */
- timer_init();
- cl_som_imx7_spl_spi_init();
- cl_som_imx7_uart1_pads_set();
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
- /* DRAM detection */
- cl_som_imx7_spl_dram_cfg();
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-
-void spl_board_init(void)
-{
- u32 boot_device = spl_boot_device();
-
- if (boot_device == BOOT_DEVICE_SPI)
- puts("Booting from SPI flash\n");
- else if (boot_device == BOOT_DEVICE_MMC1)
- puts("Booting from SD card\n");
- else
- puts("Unknown boot device\n");
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
- spl_boot_list[0] = spl_boot_device();
- switch (spl_boot_list[0]) {
- case BOOT_DEVICE_SPI:
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
- break;
- case BOOT_DEVICE_MMC1:
- spl_boot_list[1] = BOOT_DEVICE_SPI;
- break;
- }
-}
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
deleted file mode 100644
index 0eed5264f2a..00000000000
--- a/configs/cl-som-imx7_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX7=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_CL_SOM_IMX7=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-CONFIG_IMX_RDC=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="CL-SOM-iMX7 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_ENV_IS_IN_MMC is not set
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_MXC_USB_OTG_HACTIVE=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_CI_UDC=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
deleted file mode 100644
index f84a11215e4..00000000000
--- a/include/configs/cl-som-imx7.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 CompuLab, Ltd.
- *
- * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module.
- */
-
-#ifndef __CL_SOM_IMX7_CONFIG_H
-#define __CL_SOM_IMX7_CONFIG_H
-
-#include "mx7_common.h"
-
-#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
-#define CONFIG_BOARD_LATE_INIT
-
-/* Uncomment to enable secure boot support */
-/* #define CONFIG_SECURE_BOOT */
-#define CONFIG_CSF_SIZE 0x4000
-
-/* Network */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
-/* ENET1 */
-#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
-/* I2C configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define SYS_I2C_BUS_SOM 0
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM
-
-#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
-
-#undef CONFIG_SYS_AUTOLOAD
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_SYS_AUTOLOAD "no"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=off\0" \
- "script=boot.scr\0" \
- "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \
- "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \
- "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \
- "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \
- "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \
- "kernel=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdtfile=imx7d-sbc-imx7.dtb\0" \
- "fdtaddr=0x83000000\0" \
- "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \
- "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
- "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \
- "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \
- "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \
- "mmcbootscript=" \
- "if run mmc_config; then " \
- "setenv storagetype mmc;" \
- "setenv storagedev ${mmcdev}:${mmcpart};" \
- "if run loadscript; then " \
- "run bootscript; " \
- "fi; " \
- "fi;\0" \
- "mmcboot=" \
- "if run mmc_config; then " \
- "setenv storagetype mmc;" \
- "setenv storagedev ${mmcdev}:${mmcpart};" \
- "if run loadkernel; then " \
- "if run loadfdt; then " \
- "run storagebootcmd;" \
- "fi; " \
- "fi; " \
- "fi;\0" \
- "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \
- "run mmcbootscript\0" \
- "usbbootscript=setenv usbdev ${usbdev_def}; " \
- "setenv storagetype usb;" \
- "setenv storagedev ${usbdev}:${usbpart};" \
- "if run loadscript; then " \
- "run bootscript; " \
- "fi; " \
- "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \
- "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \
- "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "echo SD boot attempt ...; run sdbootscript; run sdboot; " \
- "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
- "echo USB boot attempt ...; run usbbootscript; "
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* SPI Flash support */
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 20000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-
-/* FLASH and environment organization */
-#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_OFFSET (768 * 1024)
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-
-/* MMC Config*/
-#define CONFIG_FSL_USDHC
-#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#endif
-
-/* USB Configs */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* Uncomment to enable iMX thermal driver support */
-/*#define CONFIG_IMX_THERMAL*/
-
-/* SPL */
-#include "imx7_spl.h"
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#endif /* CONFIG_SPL_BUILD */
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 44/93] arm: Remove devkit8000 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (42 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 43/93] arm: Remove cl-som-imx7 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 45/93] arm: Remove pengwyn board Simon Glass
` (53 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/timll/devkit8000/Kconfig | 12 -
board/timll/devkit8000/MAINTAINERS | 6 -
board/timll/devkit8000/Makefile | 9 -
board/timll/devkit8000/README | 15 --
board/timll/devkit8000/devkit8000.c | 206 ----------------
board/timll/devkit8000/devkit8000.h | 359 ----------------------------
configs/devkit8000_defconfig | 34 ---
include/configs/devkit8000.h | 190 ---------------
9 files changed, 832 deletions(-)
delete mode 100644 board/timll/devkit8000/Kconfig
delete mode 100644 board/timll/devkit8000/MAINTAINERS
delete mode 100644 board/timll/devkit8000/Makefile
delete mode 100644 board/timll/devkit8000/README
delete mode 100644 board/timll/devkit8000/devkit8000.c
delete mode 100644 board/timll/devkit8000/devkit8000.h
delete mode 100644 configs/devkit8000_defconfig
delete mode 100644 include/configs/devkit8000.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index d2d4d2b3809..edd5e3f255b 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -198,7 +198,6 @@ source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
-source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
diff --git a/board/timll/devkit8000/Kconfig b/board/timll/devkit8000/Kconfig
deleted file mode 100644
index 3c63ced9a1a..00000000000
--- a/board/timll/devkit8000/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DEVKIT8000
-
-config SYS_BOARD
- default "devkit8000"
-
-config SYS_VENDOR
- default "timll"
-
-config SYS_CONFIG_NAME
- default "devkit8000"
-
-endif
diff --git a/board/timll/devkit8000/MAINTAINERS b/board/timll/devkit8000/MAINTAINERS
deleted file mode 100644
index c490757d684..00000000000
--- a/board/timll/devkit8000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DEVKIT8000 BOARD
-M: Thomas Weber <weber@corscience.de>
-S: Maintained
-F: board/timll/devkit8000/
-F: include/configs/devkit8000.h
-F: configs/devkit8000_defconfig
diff --git a/board/timll/devkit8000/Makefile b/board/timll/devkit8000/Makefile
deleted file mode 100644
index 4d681701cf3..00000000000
--- a/board/timll/devkit8000/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2009
-# Frederik Kriewitz <frederik@kriewitz.eu>
-
-obj-y := devkit8000.o
diff --git a/board/timll/devkit8000/README b/board/timll/devkit8000/README
deleted file mode 100644
index 609bf51aee2..00000000000
--- a/board/timll/devkit8000/README
+++ /dev/null
@@ -1,15 +0,0 @@
-DevKit8000
-==========
-
-The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board
-with Ethernet and Touch Screen controller on board.
-
-For more information go to:
-http://www.embedinfo.com/English/Product/devkit8000.asp
-
-There's no real MAC address available.
-If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used.
-
-Build:
-make devkit8000_config
-make
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
deleted file mode 100644
index 50b70a501cc..00000000000
--- a/board/timll/devkit8000/devkit8000.c
+++ /dev/null
@@ -1,206 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2009
- * Frederik Kriewitz <frederik@kriewitz.eu>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- */
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/mach-types.h>
-#include "devkit8000.h"
-#include <asm/gpio.h>
-#ifdef CONFIG_DRIVER_DM9000
-#include <net.h>
-#include <netdev.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
- NET_GPMC_CONFIG1,
- NET_GPMC_CONFIG2,
- NET_GPMC_CONFIG3,
- NET_GPMC_CONFIG4,
- NET_GPMC_CONFIG5,
- NET_GPMC_CONFIG6,
- 0
-};
-
-static const struct ns16550_platdata devkit8000_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(devkit8000_uart) = {
- "ns16550_serial",
- &devkit8000_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/* Configure GPMC registers for DM9000 */
-static void gpmc_dm9000_config(void)
-{
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
- CONFIG_DM9000_BASE, GPMC_SIZE_16M);
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
-#ifdef CONFIG_DRIVER_DM9000
- uchar enetaddr[6];
- u32 die_id_0;
-#endif
-
- twl4030_power_init();
-#ifdef CONFIG_TWL4030_LED
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
- /* Configure GPMC registers for DM9000 */
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
- CONFIG_DM9000_BASE, GPMC_SIZE_16M);
-
- /* Use OMAP DIE_ID as MAC address */
- if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
- printf("ethaddr not set, using Die ID\n");
- die_id_0 = readl(&id_base->die_id_0);
- enetaddr[0] = 0x02; /* locally administered */
- enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
- enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
- enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
- enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
- enetaddr[5] = (die_id_0 & 0x000000ff);
- eth_env_set_enetaddr("ethaddr", enetaddr);
- }
-#endif
-
- omap_die_id_display();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DEVKIT8000();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
-/*
- * Routine: board_eth_init
- * Description: Setting up the Ethernet hardware.
- */
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * Do board specific preparation before SPL
- * Linux boot
- */
-void spl_board_prepare_for_linux(void)
-{
- gpmc_dm9000_config();
-}
-
-/*
- * devkit8000 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if the button is not pressed
- * 1 if the button is pressed
- */
-int spl_start_uboot(void)
-{
- int val = 0;
- if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
- gpio_direction_input(SPL_OS_BOOT_KEY);
- val = gpio_get_value(SPL_OS_BOOT_KEY);
- gpio_free(SPL_OS_BOOT_KEY);
- }
- return !val;
-}
-#endif
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank. This
- * provides the timing values back to the function that configures
- * the memory. We have either one or two banks of 128MB DDR.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- /* General SDRC config */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-
- /* AC timings */
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
-
- timings->mr = MICRON_V_MR_165;
-}
diff --git a/board/timll/devkit8000/devkit8000.h b/board/timll/devkit8000/devkit8000.h
deleted file mode 100644
index c8d57d167eb..00000000000
--- a/board/timll/devkit8000/devkit8000.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * (C) Copyright 2009
- * Frederik Kriewitz <frederik@kriewitz.eu>
- */
-#ifndef _DEVKIT8000_H_
-#define _DEVKIT8000_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 DevKit8000",
- "NAND",
-};
-
-/* GPIO used to select between U-Boot and kernel */
-#define SPL_OS_BOOT_KEY 26
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-#define MUX_DEVKIT8000() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6 DM9000*/\
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /* Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /* MMC Slot */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /* Expansion Header */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
- MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /* Serial Interface */\
- MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- /* Host USB0 */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | DIS | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
- /* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
-
-#endif
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
deleted file mode 100644
index ea2aee4ef4a..00000000000
--- a/configs/devkit8000_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TARGET_DEVKIT8000=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x680000
-CONFIG_CMD_SPL_WRITE_SIZE=0x400
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_NTPSERVER=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_CONS_INDEX=3
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
deleted file mode 100644
index 1b175be3870..00000000000
--- a/include/configs/devkit8000.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * (C) Copyright 2009
- * Frederik Kriewitz <frederik@kriewitz.eu>
- *
- * Configuration settings for the DevKit8000 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
-
-/* Physical Memory Map */
-
-#include <configs/ti_omap3_common.h>
-
-#define CONFIG_REVISION_TAG 1
-
-/* Size of malloc() pool */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/* Hardware drivers */
-/* DM9000 */
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x2c000000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
-#define CONFIG_DM9000_USE_16BIT 1
-#define CONFIG_DM9000_NO_SROM 1
-#undef CONFIG_DM9000_DEBUG
-
-/* TWL4030 */
-
-/* Board NAND Info */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
- /* partition */
-
-/* BOOTP/DHCP options */
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_TIMEOFFSET
-#undef CONFIG_BOOTP_VENDOREX
-
-/* Environment information */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcdev=0\0" \
- "vram=12M\0" \
- "dvimode=1024x768MR-16@60\0" \
- "defaultdisplay=dvi\0" \
- "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
- "kernelopts=rw\0" \
- "commonargs=" \
- "setenv bootargs console=${console} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay}\0" \
- "mmcargs=" \
- "run commonargs; " \
- "setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p2 " \
- "rootwait " \
- "${kernelopts}\0" \
- "nandargs=" \
- "run commonargs; " \
- "setenv bootargs ${bootargs} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=/dev/mtdblock4 " \
- "rootfstype=jffs2 " \
- "${kernelopts}\0" \
- "netargs=" \
- "run commonargs; " \
- "setenv bootargs ${bootargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
- "${kernelopts} " \
- "dnsip1=${dnsip} " \
- "dnsip2=${dnsip2}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
- "netboot=echo Booting from network ...; " \
- "dhcp ${loadaddr}; " \
- "run netargs; " \
- "bootm ${loadaddr}\0" \
- "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi\0"
-
-#define CONFIG_BOOTCOMMAND "run autoboot"
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- 0x01000000) /* 16MB */
-
-/* NAND and environment organization */
-
-#define CONFIG_ENV_OFFSET 0x260000
-
-/* SRAM config */
-#define CONFIG_SYS_SRAM_START 0x40200000
-#define CONFIG_SYS_SRAM_SIZE 0x10000
-
-/* Defines for SPL */
-
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
-
-/* SPL OS boot options */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-
-#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
-#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
-#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
-
-#undef CONFIG_SYS_SPL_ARGS_ADDR
-#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 45/93] arm: Remove pengwyn board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (43 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 44/93] arm: Remove devkit8000 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 46/93] arm: Remove dreamplug board Simon Glass
` (52 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/silica/pengwyn/Kconfig | 15 ---
board/silica/pengwyn/MAINTAINERS | 6 -
board/silica/pengwyn/Makefile | 11 --
board/silica/pengwyn/board.c | 201 -------------------------------
board/silica/pengwyn/board.h | 14 ---
board/silica/pengwyn/mux.c | 97 ---------------
configs/pengwyn_defconfig | 62 ----------
include/configs/pengwyn.h | 171 --------------------------
9 files changed, 578 deletions(-)
delete mode 100644 board/silica/pengwyn/Kconfig
delete mode 100644 board/silica/pengwyn/MAINTAINERS
delete mode 100644 board/silica/pengwyn/Makefile
delete mode 100644 board/silica/pengwyn/board.c
delete mode 100644 board/silica/pengwyn/board.h
delete mode 100644 board/silica/pengwyn/mux.c
delete mode 100644 configs/pengwyn_defconfig
delete mode 100644 include/configs/pengwyn.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 740897539e8..4cb32325ed3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1521,7 +1521,6 @@ source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
-source "board/silica/pengwyn/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig
deleted file mode 100644
index f2e1098f62a..00000000000
--- a/board/silica/pengwyn/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PENGWYN
-
-config SYS_BOARD
- default "pengwyn"
-
-config SYS_VENDOR
- default "silica"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "pengwyn"
-
-endif
diff --git a/board/silica/pengwyn/MAINTAINERS b/board/silica/pengwyn/MAINTAINERS
deleted file mode 100644
index 14ef7750c54..00000000000
--- a/board/silica/pengwyn/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PENGWYN BOARD
-M: Lothar Felten <lothar.felten@gmail.com>
-S: Maintained
-F: board/silica/pengwyn/
-F: include/configs/pengwyn.h
-F: configs/pengwyn_defconfig
diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
deleted file mode 100644
index c34b9b1dd8a..00000000000
--- a/board/silica/pengwyn/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
deleted file mode 100644
index 90ea8c601c4..00000000000
--- a/board/silica/pengwyn/board.c
+++ /dev/null
@@ -1,201 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- */
-
-#include <common.h>
-#include <environment.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <phy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#if defined(CONFIG_SPL_BUILD)
-
-/* DDR3 RAM timings */
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41K128MJT187E_RD_DQS,
- .datawdsratio0 = MT41K128MJT187E_WR_DQS,
- .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41K128MJT187E_RATIO,
- .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
- .cmd1csratio = MT41K128MJT187E_RATIO,
- .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
- .cmd2csratio = MT41K128MJT187E_RATIO,
- .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
- .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
- .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
- .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
- .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
- .zq_config = MT41K128MJT187E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-const struct ctrl_ioregs ddr3_ioregs = {
- .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return serial_tstc() && serial_getc() == 'c';
-}
-#endif
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr_266 = {
- 266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_303 = {
- 303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_400 = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- /*
- * The pengwyn board uses the TPS650250 PMIC without I2C
- * interface and will output the following fixed voltages:
- * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
- * VLDO1=1V8 (IO) VLDO2=1V8(IO)
- * Vcore=1V1 is fixed, generated by TPS62231
- */
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* 720MHz cpu, this might change on newer board revisions */
- dpll_mpu_opp100.m = MPUPLL_M_720;
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- /* future configs can return other clock settings */
- return &dpll_ddr_303;
-}
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-void sdram_init(void)
-{
- config_ddr(303, &ddr3_ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif /* if CONFIG_SPL_BUILD */
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gpmc_init();
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 1,
- .phy_if = PHY_INTERFACE_MODE_MII,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- else
- return n;
- }
-
- writel(MII_MODE_ENABLE, &cdev->miisel);
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
- return n;
-}
-#endif /* if CONFIG_DRIVER_TI_CPSW */
diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h
deleted file mode 100644
index 3d5ce6d3939..00000000000
--- a/board/silica/pengwyn/board.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-void enable_uart0_pin_mux(void);
-void enable_board_pin_mux(void);
-
-#endif
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
deleted file mode 100644
index 7583e833ed4..00000000000
--- a/board/silica/pengwyn/mux.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mux.c
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include "board.h"
-
-/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
-
-/* I2C pins C16(scl)/C17(sda) */
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
- {-1},
-};
-
-/* MMC0 pins */
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-/* MII pins */
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
- {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
- {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
- {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-/* NAND pins */
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_board_pin_mux()
-{
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(uart0_pin_mux);
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(nand_pin_mux);
-}
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
deleted file mode 100644
index 3c8684ad958..00000000000
--- a/configs/pengwyn_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_PENGWYN=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_WOL=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)"
-CONFIG_CMD_DIAG=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
deleted file mode 100644
index 48f1f7baccb..00000000000
--- a/include/configs/pengwyn.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * pengwyn.h
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- *
- * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
- */
-
-#ifndef __CONFIG_PENGWYN_H
-#define __CONFIG_PENGWYN_H
-
-
-#include <configs/ti_am335x_common.h>
-
-/* Clock Defines */
-#define V_OSCK 24000000
-#define V_SCLK V_OSCK
-
-/* set env size */
-#define CONFIG_ENV_SIZE 0x4000
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "fdtfile=am335x-pengwyn.dtb\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 ro\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "rootpath=/export/rootfs\0" \
- "nfsopts=nolock\0" \
- "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
- "::off\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcloados=run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr};\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcloados;" \
- "fi;" \
- "fi;\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "tftp ${fdtaddr} ${fdtfile}; " \
- "run netargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${fdtaddr} u-boot-spl-os; " \
- "nand read ${loadaddr} kernel; " \
- "bootz ${loadaddr} - ${fdtaddr}\0"
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "run mmcboot;" \
- "run nandboot;"
-
-/* NS16550 Configuration: primary UART via FTDI */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* SPL */
-
-/* NAND support */
-
-/* NAND Configuration. */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 4096
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
- 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
- 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\
- 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\
- 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\
- 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\
- 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
- 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
- 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
- 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
- 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
- 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_ECCSTEPS 8
-#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
- CONFIG_SYS_NAND_ECCSTEPS)
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
-/* END NAND Configuration. */
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-
-/* Size must be a multiple of Nand erase size (524288 b) */
-#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
-/*
- * USB configuration. We enable MUSB support, both for host and for
- * gadget. We set USB0 as peripheral and USB1 as host, based on the
- * board schematic and physical port wired to each. Then for host we
- * add mass storage support.
- */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-/* Network */
-#define CONFIG_PHY_RESET 1
-#define CONFIG_PHY_NATSEMI
-#define CONFIG_PHY_REALTEK
-
-#endif /* ! __CONFIG_PENGWYN_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 46/93] arm: Remove dreamplug board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (44 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 45/93] arm: Remove pengwyn board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 47/93] arm: Remove mx6sabreauto board Simon Glass
` (51 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/Marvell/dreamplug/Kconfig | 12 ---
board/Marvell/dreamplug/MAINTAINERS | 6 --
board/Marvell/dreamplug/Makefile | 10 --
board/Marvell/dreamplug/dreamplug.c | 135 -------------------------
board/Marvell/dreamplug/dreamplug.h | 25 -----
board/Marvell/dreamplug/kwbimage.cfg | 145 ---------------------------
configs/dreamplug_defconfig | 40 --------
include/configs/dreamplug.h | 83 ---------------
9 files changed, 457 deletions(-)
delete mode 100644 board/Marvell/dreamplug/Kconfig
delete mode 100644 board/Marvell/dreamplug/MAINTAINERS
delete mode 100644 board/Marvell/dreamplug/Makefile
delete mode 100644 board/Marvell/dreamplug/dreamplug.c
delete mode 100644 board/Marvell/dreamplug/dreamplug.h
delete mode 100644 board/Marvell/dreamplug/kwbimage.cfg
delete mode 100644 configs/dreamplug_defconfig
delete mode 100644 include/configs/dreamplug.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index d4afdaccd3b..299977c87d6 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -71,7 +71,6 @@ config SYS_SOC
default "kirkwood"
source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/dreamplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
diff --git a/board/Marvell/dreamplug/Kconfig b/board/Marvell/dreamplug/Kconfig
deleted file mode 100644
index f65ff73713e..00000000000
--- a/board/Marvell/dreamplug/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DREAMPLUG
-
-config SYS_BOARD
- default "dreamplug"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "dreamplug"
-
-endif
diff --git a/board/Marvell/dreamplug/MAINTAINERS b/board/Marvell/dreamplug/MAINTAINERS
deleted file mode 100644
index 2561ba8134e..00000000000
--- a/board/Marvell/dreamplug/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DREAMPLUG BOARD
-M: Jason Cooper <u-boot@lakedaemon.net>
-S: Maintained
-F: board/Marvell/dreamplug/
-F: include/configs/dreamplug.h
-F: configs/dreamplug_defconfig
diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile
deleted file mode 100644
index e239d591b7b..00000000000
--- a/board/Marvell/dreamplug/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011
-# Jason Cooper <u-boot@lakedaemon.net>
-#
-# Based on work by:
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-
-obj-y := dreamplug.o
diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c
deleted file mode 100644
index ede168c9ece..00000000000
--- a/board/Marvell/dreamplug/dreamplug.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
- *
- * Based on work by:
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "dreamplug.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
- DREAMPLUG_OE_VAL_HIGH,
- DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn, /* SPI Flash */
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD, /* Serial */
- MPP11_UART0_RXD,
- MPP12_SD_CLK, /* SDIO Slot */
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0, /* Gigabit Ethernet */
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GE1_8,
- MPP29_GE1_9,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GE1_14,
- MPP35_GE1_15,
- MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_TDM_SPI_SCK,
- MPP41_TDM_SPI_MISO,
- MPP42_TDM_SPI_MOSI,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO, /* Bluetooth LED */
- MPP48_GPIO, /* Wifi LED */
- MPP49_GPIO, /* Wifi AP LED */
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void mv_phy_88e1116_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-
-void reset_phy(void)
-{
- /* configure and initialize both PHY's */
- mv_phy_88e1116_init("egiga0");
- mv_phy_88e1116_init("egiga1");
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/dreamplug/dreamplug.h b/board/Marvell/dreamplug/dreamplug.h
deleted file mode 100644
index 6f62238985b..00000000000
--- a/board/Marvell/dreamplug/dreamplug.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
- *
- * Based on work by:
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#ifndef __DREAMPLUG_H
-#define __DREAMPLUG_H
-
-#define DREAMPLUG_OE_LOW (~(0))
-#define DREAMPLUG_OE_HIGH (~(0))
-#define DREAMPLUG_OE_VAL_LOW 0
-#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
-
-/* PHY related */
-#define MV88E1116_MAC_CTRL2_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DREAMPLUG_H */
diff --git a/board/Marvell/dreamplug/kwbimage.cfg b/board/Marvell/dreamplug/kwbimage.cfg
deleted file mode 100644
index f916208c192..00000000000
--- a/board/Marvell/dreamplug/kwbimage.cfg
+++ /dev/null
@@ -1,145 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011
-# Jason Cooper <u-boot@lakedaemon.net>
-#
-# Based on work by:
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0/1 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b9b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 01, Cs0width=x8
-# bit3-2: 10, Cs0size=1Gb
-# bit5-4: 01, Cs1width=x8
-# bit7-6: 10, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
deleted file mode 100644
index 76c768006d3..00000000000
--- a/configs/dreamplug_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_DREAMPLUG=y
-CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
deleted file mode 100644
index 1c94bf9fa1b..00000000000
--- a/include/configs/dreamplug.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Jason Cooper <u-boot@lakedaemon.net>
- *
- * Based on work by:
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Siddarth Gore <gores@marvell.com>
- */
-
-#ifndef _CONFIG_DREAMPLUG_H
-#define _CONFIG_DREAMPLUG_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
-
-/*
- * Commands configuration
- */
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-plug-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
-#endif
-
-#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI 1
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
-#endif
-
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x1000 /* 4k */
-#define CONFIG_ENV_ADDR 0x100000
-#define CONFIG_ENV_OFFSET 0x100000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
- "${x_bootcmd_ethernet}; setenv ethact egiga1; " \
- "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "x_bootcmd_ethernet=ping 192.168.2.1\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
- "x_bootargs=console=ttyS0,115200\0" \
- "x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_PHY_BASE_ADR 0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#endif /* _CONFIG_DREAMPLUG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 47/93] arm: Remove mx6sabreauto board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (45 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 46/93] arm: Remove dreamplug board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 23:56 ` Peng Fan
2018-11-19 15:53 ` [U-Boot] [PATCH 48/93] arm: Remove imx6q_logic board Simon Glass
` (50 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/freescale/mx6sabreauto/Kconfig | 12 -
board/freescale/mx6sabreauto/MAINTAINERS | 7 -
board/freescale/mx6sabreauto/Makefile | 7 -
board/freescale/mx6sabreauto/README | 82 --
board/freescale/mx6sabreauto/mx6sabreauto.c | 1099 -------------------
configs/mx6sabreauto_defconfig | 67 --
include/configs/mx6sabreauto.h | 78 --
8 files changed, 1353 deletions(-)
delete mode 100644 board/freescale/mx6sabreauto/Kconfig
delete mode 100644 board/freescale/mx6sabreauto/MAINTAINERS
delete mode 100644 board/freescale/mx6sabreauto/Makefile
delete mode 100644 board/freescale/mx6sabreauto/README
delete mode 100644 board/freescale/mx6sabreauto/mx6sabreauto.c
delete mode 100644 configs/mx6sabreauto_defconfig
delete mode 100644 include/configs/mx6sabreauto.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 701973b3866..face0f09827 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -538,7 +538,6 @@ source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6memcal/Kconfig"
-source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sllevk/Kconfig"
diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig
deleted file mode 100644
index 5b4faf6d5fd..00000000000
--- a/board/freescale/mx6sabreauto/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6SABREAUTO
-
-config SYS_BOARD
- default "mx6sabreauto"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "mx6sabreauto"
-
-endif
diff --git a/board/freescale/mx6sabreauto/MAINTAINERS b/board/freescale/mx6sabreauto/MAINTAINERS
deleted file mode 100644
index a89f05a8293..00000000000
--- a/board/freescale/mx6sabreauto/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MX6SABREAUTO BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-M: Peng Fan <peng.fan@nxp.com>
-S: Maintained
-F: board/freescale/mx6sabreauto/
-F: include/configs/mx6sabreauto.h
-F: configs/mx6sabreauto_defconfig
diff --git a/board/freescale/mx6sabreauto/Makefile b/board/freescale/mx6sabreauto/Makefile
deleted file mode 100644
index 7ecdb6b4ad2..00000000000
--- a/board/freescale/mx6sabreauto/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx6sabreauto.o
diff --git a/board/freescale/mx6sabreauto/README b/board/freescale/mx6sabreauto/README
deleted file mode 100644
index e8c589b92aa..00000000000
--- a/board/freescale/mx6sabreauto/README
+++ /dev/null
@@ -1,82 +0,0 @@
-How to use and build U-Boot on mx6sabreauto
--------------------------------------------
-
-mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
-
-In order to build it:
-
-$ make mx6sabreauto_defconfig
-
-$ make
-
-This will generate the SPL and u-boot.img binaries.
-
-- Flash the SPL binary into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-
-- Flash the u-boot.img binary into the SD card:
-
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
-
-Booting via Falcon mode
------------------------
-
-Write in mx6sabreauto_defconfig the following define below:
-
-CONFIG_SPL_OS_BOOT=y
-
-In order to build it:
-
-$ make mx6sabreauto_defconfig
-
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
-
-- Flash the u-boot.img image into the SD card:
-
-$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync
-
-Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
-
-$ sudo cp uImage /media/boot
-
-$ sudo cp imx6dl-sabreauto.dtb /media/boot
-
-Create a partition for root file system and extract it there:
-
-$ sudo tar xvf rootfs.tar.gz -C /media/root
-
-The SD card must have enough space for raw "args" and "kernel".
-To configure Falcon mode for the first time, on U-Boot do the following commands:
-
-- Load dtb file from boot partition:
-
-# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
-
-- Load kernel image from boot partition:
-
-# load mmc 0:1 ${loadaddr} uImage
-
-- Write kernel at 2MB offset:
-
-# mmc write ${loadaddr} 0x1000 0x4000
-
-- Setup kernel bootargs:
-
-# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
-
-- Prepare args:
-
-# spl export fdt ${loadaddr} - ${fdt_addr}
-
-- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
-
-# mmc write 18000000 0x800 0x800
-
-- Restart the board and then SPL binary will launch the kernel directly.
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
deleted file mode 100644
index c1bef8507c2..00000000000
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ /dev/null
@@ -1,1099 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/spi.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <input.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/mach-imx/video.h>
-#include <asm/arch/crm_regs.h>
-#include <pca953x.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include "../common/pfuze.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
- PAD_CTL_SRE_FAST)
-#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC 1
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart4_pads[] = {
- IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-};
-
-/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-#ifndef CONFIG_SYS_FLASH_CFI
-/*
- * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
- * Compass Sensor, Accelerometer, Res Touch
- */
-static struct i2c_pads_info mx6q_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-#endif
-
-static iomux_v3_cfg_t const i2c3_pads[] = {
- IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const port_exp[] = {
- IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
- ((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
- (gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
- (gpio_nr & 0x1f)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
- int ret;
-
- i2c_set_bus_num(2);
- ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
- if (ret)
- return ret;
-
- ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
- (1 << PORTEXP_IO_TO_PIN(gpio)),
- (value << PORTEXP_IO_TO_PIN(gpio)));
-
- if (ret)
- return ret;
-
- return 0;
-}
-
-#ifdef CONFIG_MTD_NOR_FLASH
-static iomux_v3_cfg_t const eimnor_pads[] = {
- IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eimnor_cs_setup(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
- writel(0x00020181, &weim_regs->cs0gcr1);
- writel(0x00000001, &weim_regs->cs0gcr2);
- writel(0x0a020000, &weim_regs->cs0rcr1);
- writel(0x0000c000, &weim_regs->cs0rcr2);
- writel(0x0804a240, &weim_regs->cs0wcr1);
- writel(0x00000120, &weim_regs->wcr);
-
- set_chipselect_size(CS0_128);
-}
-
-static void eim_clk_setup(void)
-{
- struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int cscmr1, ccgr6;
-
-
- /* Turn off EIM clock */
- ccgr6 = readl(&imx_ccm->CCGR6);
- ccgr6 &= ~(0x3 << 10);
- writel(ccgr6, &imx_ccm->CCGR6);
-
- /*
- * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
- * and aclk_eim_slow_podf = 01 --> divide by 2
- * so that we can have EIM at the maximum clock of 132MHz
- */
- cscmr1 = readl(&imx_ccm->cscmr1);
- cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
- MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
- cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
- writel(cscmr1, &imx_ccm->cscmr1);
-
- /* Turn on EIM clock */
- ccgr6 |= (0x3 << 10);
- writel(ccgr6, &imx_ccm->CCGR6);
-}
-
-static void setup_iomux_eimnor(void)
-{
- SETUP_IOMUX_PADS(eimnor_pads);
-
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-
- eimnor_cs_setup();
-}
-#endif
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart4_pads);
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- gpio_direction_input(IMX_GPIO_NR(6, 15));
- return !gpio_get_value(IMX_GPIO_NR(6, 15));
-}
-
-int board_mmc_init(bd_t *bis)
-{
- SETUP_IOMUX_PADS(usdhc3_pads);
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-#endif
-
-#ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t gpmi_pads[] = {
- IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
- IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
- IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- SETUP_IOMUX_PADS(gpmi_pads);
-
- setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-static void setup_fec(void)
-{
- if (is_mx6dqp()) {
- /*
- * select ENET MAC0 TX clock from PLL
- */
- imx_iomux_set_gpr_register(5, 9, 1, 1);
- enable_fec_anatop_clock(0, ENET_125MHZ);
- }
-
- setup_iomux_enet();
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_fec();
-
- return cpu_eth_init(bis);
-}
-
-u32 get_board_rev(void)
-{
- int rev = nxp_board_rev();
-
- return (get_cpu_rev() & ~(0xF << 8)) | rev;
-}
-
-static int ar8031_phy_fixup(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- ar8031_phy_fixup(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static void disable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- clrbits_le32(&iomux->gpr[2],
- IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
- IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
-}
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- disable_lvds(dev);
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = NULL,
- .enable = NULL,
- .mode = {
- .name = "Hannstar-XGA",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED,
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-iomux_v3_cfg_t const backlight_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-};
-
-static void setup_iomux_backlight(void)
-{
- gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
- SETUP_IOMUX_PADS(backlight_pads);
-}
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- setup_iomux_backlight();
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* Turn on LDB_DI0 and LDB_DI1 clocks */
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
- MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
- (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
- MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
- IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
- IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
- IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
- IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
- IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
- IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
- reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
- (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
- IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
-#ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
- eim_clk_setup();
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
- if (is_mx6dq() || is_mx6dqp())
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
- else
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
- /* I2C 3 Steer */
- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
- SETUP_IOMUX_PADS(i2c3_pads);
-#ifndef CONFIG_SYS_FLASH_CFI
- if (is_mx6dq() || is_mx6dqp())
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
- else
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
-#endif
- gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
- SETUP_IOMUX_PADS(port_exp);
-
-#ifdef CONFIG_VIDEO_IPUV3
- setup_display();
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
- setup_iomux_eimnor();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
-#endif
-
-int power_init_board(void)
-{
- struct pmic *p;
- unsigned int value;
-
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
-
- if (is_mx6dqp()) {
- /* set SW2 staby volatage 0.975V*/
- pmic_reg_read(p, PFUZE100_SW2STBY, &value);
- value &= ~0x3f;
- value |= 0x17;
- pmic_reg_write(p, PFUZE100_SW2STBY, value);
- }
-
- return pfuze_mode_init(p, APS_PFM);
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", "SABREAUTO");
-
- if (is_mx6dqp())
- env_set("board_rev", "MX6QP");
- else if (is_mx6dq())
- env_set("board_rev", "MX6Q");
- else if (is_mx6sdl())
- env_set("board_rev", "MX6DL");
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
-
- return 0;
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
-#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
-
-iomux_v3_cfg_t const usb_otg_pads[] = {
- IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-int board_ehci_hcd_init(int port)
-{
- switch (port) {
- case 0:
- SETUP_IOMUX_PADS(usb_otg_pads);
-
- /*
- * Set daisy chain for otg_pin_id on 6q.
- * For 6dl, this bit is reserved.
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
- break;
- case 1:
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- if (on)
- port_exp_direction_output(USB_OTG_PWR, 1);
- else
- port_exp_direction_output(USB_OTG_PWR, 0);
- break;
- case 1:
- if (on)
- port_exp_direction_output(USB_HOST1_PWR, 1);
- else
- port_exp_direction_output(USB_HOST1_PWR, 0);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-#include <spl.h>
-#include <linux/libfdt.h>
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- return 0;
-}
-#endif
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static int mx6q_dcd_table[] = {
- 0x020e0798, 0x000C0000,
- 0x020e0758, 0x00000000,
- 0x020e0588, 0x00000030,
- 0x020e0594, 0x00000030,
- 0x020e056c, 0x00000030,
- 0x020e0578, 0x00000030,
- 0x020e074c, 0x00000030,
- 0x020e057c, 0x00000030,
- 0x020e058c, 0x00000000,
- 0x020e059c, 0x00000030,
- 0x020e05a0, 0x00000030,
- 0x020e078c, 0x00000030,
- 0x020e0750, 0x00020000,
- 0x020e05a8, 0x00000028,
- 0x020e05b0, 0x00000028,
- 0x020e0524, 0x00000028,
- 0x020e051c, 0x00000028,
- 0x020e0518, 0x00000028,
- 0x020e050c, 0x00000028,
- 0x020e05b8, 0x00000028,
- 0x020e05c0, 0x00000028,
- 0x020e0774, 0x00020000,
- 0x020e0784, 0x00000028,
- 0x020e0788, 0x00000028,
- 0x020e0794, 0x00000028,
- 0x020e079c, 0x00000028,
- 0x020e07a0, 0x00000028,
- 0x020e07a4, 0x00000028,
- 0x020e07a8, 0x00000028,
- 0x020e0748, 0x00000028,
- 0x020e05ac, 0x00000028,
- 0x020e05b4, 0x00000028,
- 0x020e0528, 0x00000028,
- 0x020e0520, 0x00000028,
- 0x020e0514, 0x00000028,
- 0x020e0510, 0x00000028,
- 0x020e05bc, 0x00000028,
- 0x020e05c4, 0x00000028,
- 0x021b0800, 0xa1390003,
- 0x021b080c, 0x001F001F,
- 0x021b0810, 0x001F001F,
- 0x021b480c, 0x001F001F,
- 0x021b4810, 0x001F001F,
- 0x021b083c, 0x43260335,
- 0x021b0840, 0x031A030B,
- 0x021b483c, 0x4323033B,
- 0x021b4840, 0x0323026F,
- 0x021b0848, 0x483D4545,
- 0x021b4848, 0x44433E48,
- 0x021b0850, 0x41444840,
- 0x021b4850, 0x4835483E,
- 0x021b081c, 0x33333333,
- 0x021b0820, 0x33333333,
- 0x021b0824, 0x33333333,
- 0x021b0828, 0x33333333,
- 0x021b481c, 0x33333333,
- 0x021b4820, 0x33333333,
- 0x021b4824, 0x33333333,
- 0x021b4828, 0x33333333,
- 0x021b08b8, 0x00000800,
- 0x021b48b8, 0x00000800,
- 0x021b0004, 0x00020036,
- 0x021b0008, 0x09444040,
- 0x021b000c, 0x8A8F7955,
- 0x021b0010, 0xFF328F64,
- 0x021b0014, 0x01FF00DB,
- 0x021b0018, 0x00001740,
- 0x021b001c, 0x00008000,
- 0x021b002c, 0x000026d2,
- 0x021b0030, 0x008F1023,
- 0x021b0040, 0x00000047,
- 0x021b0000, 0x841A0000,
- 0x021b001c, 0x04088032,
- 0x021b001c, 0x00008033,
- 0x021b001c, 0x00048031,
- 0x021b001c, 0x09408030,
- 0x021b001c, 0x04008040,
- 0x021b0020, 0x00005800,
- 0x021b0818, 0x00011117,
- 0x021b4818, 0x00011117,
- 0x021b0004, 0x00025576,
- 0x021b0404, 0x00011006,
- 0x021b001c, 0x00000000,
- 0x020c4068, 0x00C03F3F,
- 0x020c406c, 0x0030FC03,
- 0x020c4070, 0x0FFFC000,
- 0x020c4074, 0x3FF00000,
- 0x020c4078, 0xFFFFF300,
- 0x020c407c, 0x0F0000F3,
- 0x020c4080, 0x00000FFF,
- 0x020e0010, 0xF00000CF,
- 0x020e0018, 0x007F007F,
- 0x020e001c, 0x007F007F,
-};
-
-static int mx6qp_dcd_table[] = {
- 0x020e0798, 0x000C0000,
- 0x020e0758, 0x00000000,
- 0x020e0588, 0x00000030,
- 0x020e0594, 0x00000030,
- 0x020e056c, 0x00000030,
- 0x020e0578, 0x00000030,
- 0x020e074c, 0x00000030,
- 0x020e057c, 0x00000030,
- 0x020e058c, 0x00000000,
- 0x020e059c, 0x00000030,
- 0x020e05a0, 0x00000030,
- 0x020e078c, 0x00000030,
- 0x020e0750, 0x00020000,
- 0x020e05a8, 0x00000030,
- 0x020e05b0, 0x00000030,
- 0x020e0524, 0x00000030,
- 0x020e051c, 0x00000030,
- 0x020e0518, 0x00000030,
- 0x020e050c, 0x00000030,
- 0x020e05b8, 0x00000030,
- 0x020e05c0, 0x00000030,
- 0x020e0774, 0x00020000,
- 0x020e0784, 0x00000030,
- 0x020e0788, 0x00000030,
- 0x020e0794, 0x00000030,
- 0x020e079c, 0x00000030,
- 0x020e07a0, 0x00000030,
- 0x020e07a4, 0x00000030,
- 0x020e07a8, 0x00000030,
- 0x020e0748, 0x00000030,
- 0x020e05ac, 0x00000030,
- 0x020e05b4, 0x00000030,
- 0x020e0528, 0x00000030,
- 0x020e0520, 0x00000030,
- 0x020e0514, 0x00000030,
- 0x020e0510, 0x00000030,
- 0x020e05bc, 0x00000030,
- 0x020e05c4, 0x00000030,
- 0x021b0800, 0xa1390003,
- 0x021b080c, 0x001b001e,
- 0x021b0810, 0x002e0029,
- 0x021b480c, 0x001b002a,
- 0x021b4810, 0x0019002c,
- 0x021b083c, 0x43240334,
- 0x021b0840, 0x0324031a,
- 0x021b483c, 0x43340344,
- 0x021b4840, 0x03280276,
- 0x021b0848, 0x44383A3E,
- 0x021b4848, 0x3C3C3846,
- 0x021b0850, 0x2e303230,
- 0x021b4850, 0x38283E34,
- 0x021b081c, 0x33333333,
- 0x021b0820, 0x33333333,
- 0x021b0824, 0x33333333,
- 0x021b0828, 0x33333333,
- 0x021b481c, 0x33333333,
- 0x021b4820, 0x33333333,
- 0x021b4824, 0x33333333,
- 0x021b4828, 0x33333333,
- 0x021b08c0, 0x24912492,
- 0x021b48c0, 0x24912492,
- 0x021b08b8, 0x00000800,
- 0x021b48b8, 0x00000800,
- 0x021b0004, 0x00020036,
- 0x021b0008, 0x09444040,
- 0x021b000c, 0x898E7955,
- 0x021b0010, 0xFF328F64,
- 0x021b0014, 0x01FF00DB,
- 0x021b0018, 0x00001740,
- 0x021b001c, 0x00008000,
- 0x021b002c, 0x000026d2,
- 0x021b0030, 0x008E1023,
- 0x021b0040, 0x00000047,
- 0x021b0400, 0x14420000,
- 0x021b0000, 0x841A0000,
- 0x00bb0008, 0x00000004,
- 0x00bb000c, 0x2891E41A,
- 0x00bb0038, 0x00000564,
- 0x00bb0014, 0x00000040,
- 0x00bb0028, 0x00000020,
- 0x00bb002c, 0x00000020,
- 0x021b001c, 0x04088032,
- 0x021b001c, 0x00008033,
- 0x021b001c, 0x00048031,
- 0x021b001c, 0x09408030,
- 0x021b001c, 0x04008040,
- 0x021b0020, 0x00005800,
- 0x021b0818, 0x00011117,
- 0x021b4818, 0x00011117,
- 0x021b0004, 0x00025576,
- 0x021b0404, 0x00011006,
- 0x021b001c, 0x00000000,
- 0x020c4068, 0x00C03F3F,
- 0x020c406c, 0x0030FC03,
- 0x020c4070, 0x0FFFC000,
- 0x020c4074, 0x3FF00000,
- 0x020c4078, 0xFFFFF300,
- 0x020c407c, 0x0F0000F3,
- 0x020c4080, 0x00000FFF,
- 0x020e0010, 0xF00000CF,
- 0x020e0018, 0x77177717,
- 0x020e001c, 0x77177717,
-};
-
-static int mx6dl_dcd_table[] = {
- 0x020e0774, 0x000C0000,
- 0x020e0754, 0x00000000,
- 0x020e04ac, 0x00000030,
- 0x020e04b0, 0x00000030,
- 0x020e0464, 0x00000030,
- 0x020e0490, 0x00000030,
- 0x020e074c, 0x00000030,
- 0x020e0494, 0x00000030,
- 0x020e04a0, 0x00000000,
- 0x020e04b4, 0x00000030,
- 0x020e04b8, 0x00000030,
- 0x020e076c, 0x00000030,
- 0x020e0750, 0x00020000,
- 0x020e04bc, 0x00000028,
- 0x020e04c0, 0x00000028,
- 0x020e04c4, 0x00000028,
- 0x020e04c8, 0x00000028,
- 0x020e04cc, 0x00000028,
- 0x020e04d0, 0x00000028,
- 0x020e04d4, 0x00000028,
- 0x020e04d8, 0x00000028,
- 0x020e0760, 0x00020000,
- 0x020e0764, 0x00000028,
- 0x020e0770, 0x00000028,
- 0x020e0778, 0x00000028,
- 0x020e077c, 0x00000028,
- 0x020e0780, 0x00000028,
- 0x020e0784, 0x00000028,
- 0x020e078c, 0x00000028,
- 0x020e0748, 0x00000028,
- 0x020e0470, 0x00000028,
- 0x020e0474, 0x00000028,
- 0x020e0478, 0x00000028,
- 0x020e047c, 0x00000028,
- 0x020e0480, 0x00000028,
- 0x020e0484, 0x00000028,
- 0x020e0488, 0x00000028,
- 0x020e048c, 0x00000028,
- 0x021b0800, 0xa1390003,
- 0x021b080c, 0x001F001F,
- 0x021b0810, 0x001F001F,
- 0x021b480c, 0x001F001F,
- 0x021b4810, 0x001F001F,
- 0x021b083c, 0x42190217,
- 0x021b0840, 0x017B017B,
- 0x021b483c, 0x4176017B,
- 0x021b4840, 0x015F016C,
- 0x021b0848, 0x4C4C4D4C,
- 0x021b4848, 0x4A4D4C48,
- 0x021b0850, 0x3F3F3F40,
- 0x021b4850, 0x3538382E,
- 0x021b081c, 0x33333333,
- 0x021b0820, 0x33333333,
- 0x021b0824, 0x33333333,
- 0x021b0828, 0x33333333,
- 0x021b481c, 0x33333333,
- 0x021b4820, 0x33333333,
- 0x021b4824, 0x33333333,
- 0x021b4828, 0x33333333,
- 0x021b08b8, 0x00000800,
- 0x021b48b8, 0x00000800,
- 0x021b0004, 0x00020025,
- 0x021b0008, 0x00333030,
- 0x021b000c, 0x676B5313,
- 0x021b0010, 0xB66E8B63,
- 0x021b0014, 0x01FF00DB,
- 0x021b0018, 0x00001740,
- 0x021b001c, 0x00008000,
- 0x021b002c, 0x000026d2,
- 0x021b0030, 0x006B1023,
- 0x021b0040, 0x00000047,
- 0x021b0000, 0x841A0000,
- 0x021b001c, 0x04008032,
- 0x021b001c, 0x00008033,
- 0x021b001c, 0x00048031,
- 0x021b001c, 0x05208030,
- 0x021b001c, 0x04008040,
- 0x021b0020, 0x00005800,
- 0x021b0818, 0x00011117,
- 0x021b4818, 0x00011117,
- 0x021b0004, 0x00025565,
- 0x021b0404, 0x00011006,
- 0x021b001c, 0x00000000,
- 0x020c4068, 0x00C03F3F,
- 0x020c406c, 0x0030FC03,
- 0x020c4070, 0x0FFFC000,
- 0x020c4074, 0x3FF00000,
- 0x020c4078, 0xFFFFF300,
- 0x020c407c, 0x0F0000C3,
- 0x020c4080, 0x00000FFF,
- 0x020e0010, 0xF00000CF,
- 0x020e0018, 0x007F007F,
- 0x020e001c, 0x007F007F,
-};
-
-static void ddr_init(int *table, int size)
-{
- int i;
-
- for (i = 0; i < size / 2 ; i++)
- writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
- if (is_mx6dq())
- ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
- else if (is_mx6dqp())
- ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
- else if (is_mx6sdl())
- ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
-}
-
-void board_init_f(ulong dummy)
-{
- /* DDR initialization */
- spl_dram_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
deleted file mode 100644
index 88565678467..00000000000
--- a/configs/mx6sabreauto_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6SABREAUTO=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_NXP_BOARD_REVISION=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_SF=y
-CONFIG_FSL_ESDHC=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
deleted file mode 100644
index e444930dc87..00000000000
--- a/include/configs/mx6sabreauto.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Freescale i.MX6Q SabreAuto board.
- */
-
-#ifndef __MX6SABREAUTO_CONFIG_H
-#define __MX6SABREAUTO_CONFIG_H
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_MACH_TYPE 3529
-#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONSOLE_DEV "ttymxc3"
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
-
-#include "mx6sabre_common.h"
-
-/* Falcon Mode */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
-
-/* Falcon Mode - MMC support: args at 1MB kernel@2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#endif
-
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
-#endif /* __MX6SABREAUTO_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 47/93] arm: Remove mx6sabreauto board
2018-11-19 15:53 ` [U-Boot] [PATCH 47/93] arm: Remove mx6sabreauto board Simon Glass
@ 2018-11-19 23:56 ` Peng Fan
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Peng Fan @ 2018-11-19 23:56 UTC (permalink / raw)
To: u-boot
Hi Simon,
Please not remove this, we will work on that.
Thanks,
Peng.
> -----Original Message-----
> From: Simon Glass [mailto:sjg at chromium.org]
> Sent: 2018年11月19日 23:53
> To: U-Boot Mailing List <u-boot@lists.denx.de>
> Cc: Akshay Saraswat <akshay.s@samsung.com>; Aleksei Mamlin
> <mamlinav@gmail.com>; Jelle de Jong <jelledejong@powercraft.nl>; Jelle
> van der Waa <jelle@vdwaa.nl>; Quentin Schulz
> <quentin.schulz@free-electrons.com>; Peter Howard
> <phoward@gme.net.au>; Rask Ingemann Lambertsen <rask@formelder.dk>;
> Zoltan Herpai <wigyori@uid0.hu>; Siarhei Siamashka
> <siarhei.siamashka@gmail.com>; Dirk Eibach <dirk.eibach@gdsys.cc>; Marek
> Vasut <marek.vasut@gmail.com>; Chander Kashyap
> <k.chander@samsung.com>; Vitaly Andrianov <vitalya@ti.com>; Derald D .
> Woods <woods.technical@gmail.com>; Jaehoon Chung
> <jh80.chung@samsung.com>; Hans de Goede <hdegoede@redhat.com>;
> Heiko Schocher <hs@denx.de>; Iain Paton <ipaton0@gmail.com>; Pavel
> Machek <pavel@denx.de>; Tom Rini <trini@konsulko.com>; Adam Sampson
> <ats@offog.org>; Paul Kocialkowski <contact@paulk.fr>; Mario Six
> <mario.six@gdsys.cc>; Gregory CLEMENT
> <gregory.clement@free-electrons.com>; Stelian Pop <stelian@popies.net>;
> Feng Li <feng.li_2@nxp.com>; Sumit Garg <sumit.garg@nxp.com>; Ilko Iliev
> <iliev@ronetix.at>; egnite GmbH <info@egnite.de>; Adam Ford
> <aford173@gmail.com>; Stefan Roese <sr@denx.de>; Alison Wang
> <alison.wang@nxp.com>; Michael Walle <michael@walle.cc>; Roger Meier
> <r.meier@siemens.com>; Simon Glass <sjg@chromium.org>; FUKAUMI Naoki
> <naobsd@gmail.com>; Ian Campbell <ijc@hellion.org.uk>; Andrew F . Davis
> <afd@ti.com>; Priit Laes <plaes@plaes.org>; Stefan Mavrodiev
> <stefan.mavrodiev@gmail.com>; Icenowy Zheng <icenowy@aosc.xyz>;
> Chen-Yu Tsai <wens@csie.org>; Marcus Cooper <codekipper@gmail.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Albert Aribaud
> <albert.u.boot@aribaud.net>; Peng Fan <peng.fan@nxp.com>
> Subject: [PATCH 47/93] arm: Remove mx6sabreauto board
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-imx/mx6/Kconfig | 1 -
> board/freescale/mx6sabreauto/Kconfig | 12 -
> board/freescale/mx6sabreauto/MAINTAINERS | 7 -
> board/freescale/mx6sabreauto/Makefile | 7 -
> board/freescale/mx6sabreauto/README | 82 --
> board/freescale/mx6sabreauto/mx6sabreauto.c | 1099 -------------------
> configs/mx6sabreauto_defconfig | 67 --
> include/configs/mx6sabreauto.h | 78 --
> 8 files changed, 1353 deletions(-)
> delete mode 100644 board/freescale/mx6sabreauto/Kconfig
> delete mode 100644 board/freescale/mx6sabreauto/MAINTAINERS
> delete mode 100644 board/freescale/mx6sabreauto/Makefile
> delete mode 100644 board/freescale/mx6sabreauto/README
> delete mode 100644 board/freescale/mx6sabreauto/mx6sabreauto.c
> delete mode 100644 configs/mx6sabreauto_defconfig delete mode
> 100644 include/configs/mx6sabreauto.h
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig
> b/arch/arm/mach-imx/mx6/Kconfig index 701973b3866..face0f09827
> 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -538,7 +538,6 @@ source "board/engicam/imx6q/Kconfig"
> source "board/engicam/imx6ul/Kconfig"
> source "board/freescale/mx6qarm2/Kconfig"
> source "board/freescale/mx6memcal/Kconfig"
> -source "board/freescale/mx6sabreauto/Kconfig"
> source "board/freescale/mx6sabresd/Kconfig"
> source "board/freescale/mx6slevk/Kconfig"
> source "board/freescale/mx6sllevk/Kconfig"
> diff --git a/board/freescale/mx6sabreauto/Kconfig
> b/board/freescale/mx6sabreauto/Kconfig
> deleted file mode 100644
> index 5b4faf6d5fd..00000000000
> --- a/board/freescale/mx6sabreauto/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MX6SABREAUTO
> -
> -config SYS_BOARD
> - default "mx6sabreauto"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "mx6sabreauto"
> -
> -endif
> diff --git a/board/freescale/mx6sabreauto/MAINTAINERS
> b/board/freescale/mx6sabreauto/MAINTAINERS
> deleted file mode 100644
> index a89f05a8293..00000000000
> --- a/board/freescale/mx6sabreauto/MAINTAINERS
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -MX6SABREAUTO BOARD
> -M: Fabio Estevam <fabio.estevam@nxp.com>
> -M: Peng Fan <peng.fan@nxp.com>
> -S: Maintained
> -F: board/freescale/mx6sabreauto/
> -F: include/configs/mx6sabreauto.h
> -F: configs/mx6sabreauto_defconfig
> diff --git a/board/freescale/mx6sabreauto/Makefile
> b/board/freescale/mx6sabreauto/Makefile
> deleted file mode 100644
> index 7ecdb6b4ad2..00000000000
> --- a/board/freescale/mx6sabreauto/Makefile
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C)
> Copyright 2011 Freescale Semiconductor, Inc.
> -
> -obj-y := mx6sabreauto.o
> diff --git a/board/freescale/mx6sabreauto/README
> b/board/freescale/mx6sabreauto/README
> deleted file mode 100644
> index e8c589b92aa..00000000000
> --- a/board/freescale/mx6sabreauto/README
> +++ /dev/null
> @@ -1,82 +0,0 @@
> -How to use and build U-Boot on mx6sabreauto
> --------------------------------------------
> -
> -mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto
> variants.
> -
> -In order to build it:
> -
> -$ make mx6sabreauto_defconfig
> -
> -$ make
> -
> -This will generate the SPL and u-boot.img binaries.
> -
> -- Flash the SPL binary into the SD card:
> -
> -$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
> -
> -- Flash the u-boot.img binary into the SD card:
> -
> -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
> -
> -Booting via Falcon mode
> ------------------------
> -
> -Write in mx6sabreauto_defconfig the following define below:
> -
> -CONFIG_SPL_OS_BOOT=y
> -
> -In order to build it:
> -
> -$ make mx6sabreauto_defconfig
> -
> -$ make
> -
> -This will generate the SPL image called SPL and the u-boot.img.
> -
> -- Flash the SPL image into the SD card:
> -
> -$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
> -
> -- Flash the u-boot.img image into the SD card:
> -
> -$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync
> -
> -Create a FAT16 boot partition to store uImage and the dtb file, then copy the
> files there:
> -
> -$ sudo cp uImage /media/boot
> -
> -$ sudo cp imx6dl-sabreauto.dtb /media/boot
> -
> -Create a partition for root file system and extract it there:
> -
> -$ sudo tar xvf rootfs.tar.gz -C /media/root
> -
> -The SD card must have enough space for raw "args" and "kernel".
> -To configure Falcon mode for the first time, on U-Boot do the following
> commands:
> -
> -- Load dtb file from boot partition:
> -
> -# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
> -
> -- Load kernel image from boot partition:
> -
> -# load mmc 0:1 ${loadaddr} uImage
> -
> -- Write kernel at 2MB offset:
> -
> -# mmc write ${loadaddr} 0x1000 0x4000
> -
> -- Setup kernel bootargs:
> -
> -# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1
> rootfstype=ext4 rootwait quiet rw"
> -
> -- Prepare args:
> -
> -# spl export fdt ${loadaddr} - ${fdt_addr}
> -
> -- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
> -
> -# mmc write 18000000 0x800 0x800
> -
> -- Restart the board and then SPL binary will launch the kernel directly.
> diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c
> b/board/freescale/mx6sabreauto/mx6sabreauto.c
> deleted file mode 100644
> index c1bef8507c2..00000000000
> --- a/board/freescale/mx6sabreauto/mx6sabreauto.c
> +++ /dev/null
> @@ -1,1099 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2012 Freescale Semiconductor, Inc.
> - *
> - * Author: Fabio Estevam <fabio.estevam@freescale.com>
> - */
> -
> -#include <common.h>
> -#include <asm/io.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/imx-regs.h>
> -#include <asm/arch/iomux.h>
> -#include <asm/arch/mx6-pins.h>
> -#include <linux/errno.h>
> -#include <asm/gpio.h>
> -#include <asm/mach-imx/iomux-v3.h>
> -#include <asm/mach-imx/mxc_i2c.h>
> -#include <asm/mach-imx/boot_mode.h>
> -#include <asm/mach-imx/spi.h>
> -#include <mmc.h>
> -#include <fsl_esdhc.h>
> -#include <miiphy.h>
> -#include <netdev.h>
> -#include <asm/arch/sys_proto.h>
> -#include <i2c.h>
> -#include <input.h>
> -#include <asm/arch/mxc_hdmi.h>
> -#include <asm/mach-imx/video.h>
> -#include <asm/arch/crm_regs.h>
> -#include <pca953x.h>
> -#include <power/pmic.h>
> -#include <power/pfuze100_pmic.h>
> -#include "../common/pfuze.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
> - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> -
> -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> - PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> -
> -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE |
> PAD_CTL_PUS_100K_UP) -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm
> | PAD_CTL_SPEED_MED | \
> - PAD_CTL_SRE_FAST)
> -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
> -
> -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> -
> -#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |
> \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> -
> -#define I2C_PMIC 1
> -
> -int dram_init(void)
> -{
> - gd->ram_size = imx_ddr_size();
> -
> - return 0;
> -}
> -
> -static iomux_v3_cfg_t const uart4_pads[] = {
> - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA |
> MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA |
> MUX_PAD_CTRL(UART_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const enet_pads[] = {
> - IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_COL2__ENET_MDC |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> -};
> -
> -/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
> -static struct i2c_pads_info mx6q_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
> - .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
> - .gp = IMX_GPIO_NR(2, 30)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
> - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
> - .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
> - .gp = IMX_GPIO_NR(2, 30)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
> - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -#ifndef CONFIG_SYS_FLASH_CFI
> -/*
> - * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
> - * Compass Sensor, Accelerometer, Res Touch
> - */
> -static struct i2c_pads_info mx6q_i2c_pad_info2 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
> - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
> - .gp = IMX_GPIO_NR(1, 3)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
> - .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
> - .gp = IMX_GPIO_NR(3, 18)
> - }
> -};
> -
> -static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
> - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
> - .gp = IMX_GPIO_NR(1, 3)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
> - .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
> - .gp = IMX_GPIO_NR(3, 18)
> - }
> -};
> -#endif
> -
> -static iomux_v3_cfg_t const i2c3_pads[] = {
> - IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const port_exp[] = {
> - IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -/*Define for building port exp gpio, pin starts from 0*/ -#define
> PORTEXP_IO_NR(chip, pin) \
> - ((chip << 5) + pin)
> -
> -/*Get the chip addr from a ioexp gpio*/ -#define
> PORTEXP_IO_TO_CHIP(gpio_nr) \
> - (gpio_nr >> 5)
> -
> -/*Get the pin number from a ioexp gpio*/ -#define
> PORTEXP_IO_TO_PIN(gpio_nr) \
> - (gpio_nr & 0x1f)
> -
> -static int port_exp_direction_output(unsigned gpio, int value) -{
> - int ret;
> -
> - i2c_set_bus_num(2);
> - ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
> - if (ret)
> - return ret;
> -
> - ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
> - (1 << PORTEXP_IO_TO_PIN(gpio)),
> - (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
> -
> - if (ret)
> - return ret;
> -
> - ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
> - (1 << PORTEXP_IO_TO_PIN(gpio)),
> - (value << PORTEXP_IO_TO_PIN(gpio)));
> -
> - if (ret)
> - return ret;
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_MTD_NOR_FLASH
> -static iomux_v3_cfg_t const eimnor_pads[] = {
> - IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 |
> MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_OE__EIM_OE_B |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_RW__EIM_RW |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void eimnor_cs_setup(void)
> -{
> - struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
> -
> - writel(0x00020181, &weim_regs->cs0gcr1);
> - writel(0x00000001, &weim_regs->cs0gcr2);
> - writel(0x0a020000, &weim_regs->cs0rcr1);
> - writel(0x0000c000, &weim_regs->cs0rcr2);
> - writel(0x0804a240, &weim_regs->cs0wcr1);
> - writel(0x00000120, &weim_regs->wcr);
> -
> - set_chipselect_size(CS0_128);
> -}
> -
> -static void eim_clk_setup(void)
> -{
> - struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> - int cscmr1, ccgr6;
> -
> -
> - /* Turn off EIM clock */
> - ccgr6 = readl(&imx_ccm->CCGR6);
> - ccgr6 &= ~(0x3 << 10);
> - writel(ccgr6, &imx_ccm->CCGR6);
> -
> - /*
> - * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
> - * and aclk_eim_slow_podf = 01 --> divide by 2
> - * so that we can have EIM at the maximum clock of 132MHz
> - */
> - cscmr1 = readl(&imx_ccm->cscmr1);
> - cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
> - MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
> - cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
> - writel(cscmr1, &imx_ccm->cscmr1);
> -
> - /* Turn on EIM clock */
> - ccgr6 |= (0x3 << 10);
> - writel(ccgr6, &imx_ccm->CCGR6);
> -}
> -
> -static void setup_iomux_eimnor(void)
> -{
> - SETUP_IOMUX_PADS(eimnor_pads);
> -
> - gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
> -
> - eimnor_cs_setup();
> -}
> -#endif
> -
> -static void setup_iomux_enet(void)
> -{
> - SETUP_IOMUX_PADS(enet_pads);
> -}
> -
> -static iomux_v3_cfg_t const usdhc3_pads[] = {
> - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_uart(void)
> -{
> - SETUP_IOMUX_PADS(uart4_pads);
> -}
> -
> -#ifdef CONFIG_FSL_ESDHC
> -static struct fsl_esdhc_cfg usdhc_cfg[1] = {
> - {USDHC3_BASE_ADDR},
> -};
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - gpio_direction_input(IMX_GPIO_NR(6, 15));
> - return !gpio_get_value(IMX_GPIO_NR(6, 15));
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> - SETUP_IOMUX_PADS(usdhc3_pads);
> -
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> -}
> -#endif
> -
> -#ifdef CONFIG_NAND_MXS
> -static iomux_v3_cfg_t gpmi_pads[] = {
> - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B |
> MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
> - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 |
> MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
> - IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS |
> MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
> -};
> -
> -static void setup_gpmi_nand(void)
> -{
> - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> -
> - /* config gpmi nand iomux */
> - SETUP_IOMUX_PADS(gpmi_pads);
> -
> - setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
> - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
> - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
> -
> - /* enable apbh clock gating */
> - setbits_le32(&mxc_ccm->CCGR0,
> MXC_CCM_CCGR0_APBHDMA_MASK);
> -}
> -#endif
> -
> -static void setup_fec(void)
> -{
> - if (is_mx6dqp()) {
> - /*
> - * select ENET MAC0 TX clock from PLL
> - */
> - imx_iomux_set_gpr_register(5, 9, 1, 1);
> - enable_fec_anatop_clock(0, ENET_125MHZ);
> - }
> -
> - setup_iomux_enet();
> -}
> -
> -int board_eth_init(bd_t *bis)
> -{
> - setup_fec();
> -
> - return cpu_eth_init(bis);
> -}
> -
> -u32 get_board_rev(void)
> -{
> - int rev = nxp_board_rev();
> -
> - return (get_cpu_rev() & ~(0xF << 8)) | rev;
> -}
> -
> -static int ar8031_phy_fixup(struct phy_device *phydev) -{
> - unsigned short val;
> -
> - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> -
> - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> - val &= 0xffe3;
> - val |= 0x18;
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
> -
> - /* introduce tx clock delay */
> - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
> - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
> - val |= 0x0100;
> - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
> -
> - return 0;
> -}
> -
> -int board_phy_config(struct phy_device *phydev) -{
> - ar8031_phy_fixup(phydev);
> -
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_VIDEO_IPUV3)
> -static void disable_lvds(struct display_info_t const *dev) -{
> - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> -
> - clrbits_le32(&iomux->gpr[2],
> - IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
> - IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
> -}
> -
> -static void do_enable_hdmi(struct display_info_t const *dev) -{
> - disable_lvds(dev);
> - imx_enable_hdmi_phy();
> -}
> -
> -struct display_info_t const displays[] = {{
> - .bus = -1,
> - .addr = 0,
> - .pixfmt = IPU_PIX_FMT_RGB666,
> - .detect = NULL,
> - .enable = NULL,
> - .mode = {
> - .name = "Hannstar-XGA",
> - .refresh = 60,
> - .xres = 1024,
> - .yres = 768,
> - .pixclock = 15385,
> - .left_margin = 220,
> - .right_margin = 40,
> - .upper_margin = 21,
> - .lower_margin = 7,
> - .hsync_len = 60,
> - .vsync_len = 10,
> - .sync = FB_SYNC_EXT,
> - .vmode = FB_VMODE_NONINTERLACED
> -} }, {
> - .bus = -1,
> - .addr = 0,
> - .pixfmt = IPU_PIX_FMT_RGB24,
> - .detect = detect_hdmi,
> - .enable = do_enable_hdmi,
> - .mode = {
> - .name = "HDMI",
> - .refresh = 60,
> - .xres = 1024,
> - .yres = 768,
> - .pixclock = 15385,
> - .left_margin = 220,
> - .right_margin = 40,
> - .upper_margin = 21,
> - .lower_margin = 7,
> - .hsync_len = 60,
> - .vsync_len = 10,
> - .sync = FB_SYNC_EXT,
> - .vmode = FB_VMODE_NONINTERLACED,
> -} } };
> -size_t display_count = ARRAY_SIZE(displays);
> -
> -iomux_v3_cfg_t const backlight_pads[] = {
> - IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_backlight(void) -{
> - gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
> - SETUP_IOMUX_PADS(backlight_pads);
> -}
> -
> -static void setup_display(void)
> -{
> - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> - int reg;
> -
> - setup_iomux_backlight();
> - enable_ipu_clock();
> - imx_setup_hdmi();
> -
> - /* Turn on LDB_DI0 and LDB_DI1 clocks */
> - reg = readl(&mxc_ccm->CCGR3);
> - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK |
> MXC_CCM_CCGR3_LDB_DI1_MASK;
> - writel(reg, &mxc_ccm->CCGR3);
> -
> - /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
> - reg = readl(&mxc_ccm->cs2cdr);
> - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
> - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
> - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
> - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
> - writel(reg, &mxc_ccm->cs2cdr);
> -
> - reg = readl(&mxc_ccm->cscmr2);
> - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
> MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
> - writel(reg, &mxc_ccm->cscmr2);
> -
> - reg = readl(&mxc_ccm->chsccdr);
> - reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
> - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
> - MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
> - writel(reg, &mxc_ccm->chsccdr);
> -
> - reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
> - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
> - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
> - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
> - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
> - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
> - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
> - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
> - writel(reg, &iomux->gpr[2]);
> -
> - reg = readl(&iomux->gpr[3]);
> - reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
> - IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
> - reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
> - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
> - (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
> - IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
> - writel(reg, &iomux->gpr[3]);
> -}
> -#endif /* CONFIG_VIDEO_IPUV3 */
> -
> -/*
> - * Do not overwrite the console
> - * Use always serial for U-Boot console
> - */
> -int overwrite_console(void)
> -{
> - return 1;
> -}
> -
> -int board_early_init_f(void)
> -{
> - setup_iomux_uart();
> -
> -#ifdef CONFIG_NAND_MXS
> - setup_gpmi_nand();
> -#endif
> -
> -#ifdef CONFIG_MTD_NOR_FLASH
> - eim_clk_setup();
> -#endif
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* address of boot parameters */
> - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> -
> - /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
> - if (is_mx6dq() || is_mx6dqp())
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
> - else
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f,
> &mx6dl_i2c_pad_info1);
> - /* I2C 3 Steer */
> - gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
> - SETUP_IOMUX_PADS(i2c3_pads);
> -#ifndef CONFIG_SYS_FLASH_CFI
> - if (is_mx6dq() || is_mx6dqp())
> - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
> - else
> - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f,
> &mx6dl_i2c_pad_info2);
> -#endif
> - gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
> - SETUP_IOMUX_PADS(port_exp);
> -
> -#ifdef CONFIG_VIDEO_IPUV3
> - setup_display();
> -#endif
> -
> -#ifdef CONFIG_MTD_NOR_FLASH
> - setup_iomux_eimnor();
> -#endif
> - return 0;
> -}
> -
> -#ifdef CONFIG_MXC_SPI
> -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{
> - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
> -}
> -#endif
> -
> -int power_init_board(void)
> -{
> - struct pmic *p;
> - unsigned int value;
> -
> - p = pfuze_common_init(I2C_PMIC);
> - if (!p)
> - return -ENODEV;
> -
> - if (is_mx6dqp()) {
> - /* set SW2 staby volatage 0.975V*/
> - pmic_reg_read(p, PFUZE100_SW2STBY, &value);
> - value &= ~0x3f;
> - value |= 0x17;
> - pmic_reg_write(p, PFUZE100_SW2STBY, value);
> - }
> -
> - return pfuze_mode_init(p, APS_PFM);
> -}
> -
> -#ifdef CONFIG_CMD_BMODE
> -static const struct boot_mode board_boot_modes[] = {
> - /* 4 bit bus width */
> - {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> - {NULL, 0},
> -};
> -#endif
> -
> -int board_late_init(void)
> -{
> -#ifdef CONFIG_CMD_BMODE
> - add_board_boot_modes(board_boot_modes);
> -#endif
> -
> -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> - env_set("board_name", "SABREAUTO");
> -
> - if (is_mx6dqp())
> - env_set("board_rev", "MX6QP");
> - else if (is_mx6dq())
> - env_set("board_rev", "MX6Q");
> - else if (is_mx6sdl())
> - env_set("board_rev", "MX6DL");
> -#endif
> -
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_USB_EHCI_MX6
> -#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
> -#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
> -
> -iomux_v3_cfg_t const usb_otg_pads[] = {
> - IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -int board_ehci_hcd_init(int port)
> -{
> - switch (port) {
> - case 0:
> - SETUP_IOMUX_PADS(usb_otg_pads);
> -
> - /*
> - * Set daisy chain for otg_pin_id on 6q.
> - * For 6dl, this bit is reserved.
> - */
> - imx_iomux_set_gpr_register(1, 13, 1, 0);
> - break;
> - case 1:
> - break;
> - default:
> - printf("MXC USB port %d not yet supported\n", port);
> - return -EINVAL;
> - }
> - return 0;
> -}
> -
> -int board_ehci_power(int port, int on)
> -{
> - switch (port) {
> - case 0:
> - if (on)
> - port_exp_direction_output(USB_OTG_PWR, 1);
> - else
> - port_exp_direction_output(USB_OTG_PWR, 0);
> - break;
> - case 1:
> - if (on)
> - port_exp_direction_output(USB_HOST1_PWR, 1);
> - else
> - port_exp_direction_output(USB_HOST1_PWR, 0);
> - break;
> - default:
> - printf("MXC USB port %d not yet supported\n", port);
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -#endif
> -
> -#ifdef CONFIG_SPL_BUILD
> -#include <asm/arch/mx6-ddr.h>
> -#include <spl.h>
> -#include <linux/libfdt.h>
> -
> -#ifdef CONFIG_SPL_OS_BOOT
> -int spl_start_uboot(void)
> -{
> - return 0;
> -}
> -#endif
> -
> -static void ccgr_init(void)
> -{
> - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -
> - writel(0x00C03F3F, &ccm->CCGR0);
> - writel(0x0030FC03, &ccm->CCGR1);
> - writel(0x0FFFC000, &ccm->CCGR2);
> - writel(0x3FF00000, &ccm->CCGR3);
> - writel(0x00FFF300, &ccm->CCGR4);
> - writel(0x0F0000C3, &ccm->CCGR5);
> - writel(0x000003FF, &ccm->CCGR6);
> -}
> -
> -static int mx6q_dcd_table[] = {
> - 0x020e0798, 0x000C0000,
> - 0x020e0758, 0x00000000,
> - 0x020e0588, 0x00000030,
> - 0x020e0594, 0x00000030,
> - 0x020e056c, 0x00000030,
> - 0x020e0578, 0x00000030,
> - 0x020e074c, 0x00000030,
> - 0x020e057c, 0x00000030,
> - 0x020e058c, 0x00000000,
> - 0x020e059c, 0x00000030,
> - 0x020e05a0, 0x00000030,
> - 0x020e078c, 0x00000030,
> - 0x020e0750, 0x00020000,
> - 0x020e05a8, 0x00000028,
> - 0x020e05b0, 0x00000028,
> - 0x020e0524, 0x00000028,
> - 0x020e051c, 0x00000028,
> - 0x020e0518, 0x00000028,
> - 0x020e050c, 0x00000028,
> - 0x020e05b8, 0x00000028,
> - 0x020e05c0, 0x00000028,
> - 0x020e0774, 0x00020000,
> - 0x020e0784, 0x00000028,
> - 0x020e0788, 0x00000028,
> - 0x020e0794, 0x00000028,
> - 0x020e079c, 0x00000028,
> - 0x020e07a0, 0x00000028,
> - 0x020e07a4, 0x00000028,
> - 0x020e07a8, 0x00000028,
> - 0x020e0748, 0x00000028,
> - 0x020e05ac, 0x00000028,
> - 0x020e05b4, 0x00000028,
> - 0x020e0528, 0x00000028,
> - 0x020e0520, 0x00000028,
> - 0x020e0514, 0x00000028,
> - 0x020e0510, 0x00000028,
> - 0x020e05bc, 0x00000028,
> - 0x020e05c4, 0x00000028,
> - 0x021b0800, 0xa1390003,
> - 0x021b080c, 0x001F001F,
> - 0x021b0810, 0x001F001F,
> - 0x021b480c, 0x001F001F,
> - 0x021b4810, 0x001F001F,
> - 0x021b083c, 0x43260335,
> - 0x021b0840, 0x031A030B,
> - 0x021b483c, 0x4323033B,
> - 0x021b4840, 0x0323026F,
> - 0x021b0848, 0x483D4545,
> - 0x021b4848, 0x44433E48,
> - 0x021b0850, 0x41444840,
> - 0x021b4850, 0x4835483E,
> - 0x021b081c, 0x33333333,
> - 0x021b0820, 0x33333333,
> - 0x021b0824, 0x33333333,
> - 0x021b0828, 0x33333333,
> - 0x021b481c, 0x33333333,
> - 0x021b4820, 0x33333333,
> - 0x021b4824, 0x33333333,
> - 0x021b4828, 0x33333333,
> - 0x021b08b8, 0x00000800,
> - 0x021b48b8, 0x00000800,
> - 0x021b0004, 0x00020036,
> - 0x021b0008, 0x09444040,
> - 0x021b000c, 0x8A8F7955,
> - 0x021b0010, 0xFF328F64,
> - 0x021b0014, 0x01FF00DB,
> - 0x021b0018, 0x00001740,
> - 0x021b001c, 0x00008000,
> - 0x021b002c, 0x000026d2,
> - 0x021b0030, 0x008F1023,
> - 0x021b0040, 0x00000047,
> - 0x021b0000, 0x841A0000,
> - 0x021b001c, 0x04088032,
> - 0x021b001c, 0x00008033,
> - 0x021b001c, 0x00048031,
> - 0x021b001c, 0x09408030,
> - 0x021b001c, 0x04008040,
> - 0x021b0020, 0x00005800,
> - 0x021b0818, 0x00011117,
> - 0x021b4818, 0x00011117,
> - 0x021b0004, 0x00025576,
> - 0x021b0404, 0x00011006,
> - 0x021b001c, 0x00000000,
> - 0x020c4068, 0x00C03F3F,
> - 0x020c406c, 0x0030FC03,
> - 0x020c4070, 0x0FFFC000,
> - 0x020c4074, 0x3FF00000,
> - 0x020c4078, 0xFFFFF300,
> - 0x020c407c, 0x0F0000F3,
> - 0x020c4080, 0x00000FFF,
> - 0x020e0010, 0xF00000CF,
> - 0x020e0018, 0x007F007F,
> - 0x020e001c, 0x007F007F,
> -};
> -
> -static int mx6qp_dcd_table[] = {
> - 0x020e0798, 0x000C0000,
> - 0x020e0758, 0x00000000,
> - 0x020e0588, 0x00000030,
> - 0x020e0594, 0x00000030,
> - 0x020e056c, 0x00000030,
> - 0x020e0578, 0x00000030,
> - 0x020e074c, 0x00000030,
> - 0x020e057c, 0x00000030,
> - 0x020e058c, 0x00000000,
> - 0x020e059c, 0x00000030,
> - 0x020e05a0, 0x00000030,
> - 0x020e078c, 0x00000030,
> - 0x020e0750, 0x00020000,
> - 0x020e05a8, 0x00000030,
> - 0x020e05b0, 0x00000030,
> - 0x020e0524, 0x00000030,
> - 0x020e051c, 0x00000030,
> - 0x020e0518, 0x00000030,
> - 0x020e050c, 0x00000030,
> - 0x020e05b8, 0x00000030,
> - 0x020e05c0, 0x00000030,
> - 0x020e0774, 0x00020000,
> - 0x020e0784, 0x00000030,
> - 0x020e0788, 0x00000030,
> - 0x020e0794, 0x00000030,
> - 0x020e079c, 0x00000030,
> - 0x020e07a0, 0x00000030,
> - 0x020e07a4, 0x00000030,
> - 0x020e07a8, 0x00000030,
> - 0x020e0748, 0x00000030,
> - 0x020e05ac, 0x00000030,
> - 0x020e05b4, 0x00000030,
> - 0x020e0528, 0x00000030,
> - 0x020e0520, 0x00000030,
> - 0x020e0514, 0x00000030,
> - 0x020e0510, 0x00000030,
> - 0x020e05bc, 0x00000030,
> - 0x020e05c4, 0x00000030,
> - 0x021b0800, 0xa1390003,
> - 0x021b080c, 0x001b001e,
> - 0x021b0810, 0x002e0029,
> - 0x021b480c, 0x001b002a,
> - 0x021b4810, 0x0019002c,
> - 0x021b083c, 0x43240334,
> - 0x021b0840, 0x0324031a,
> - 0x021b483c, 0x43340344,
> - 0x021b4840, 0x03280276,
> - 0x021b0848, 0x44383A3E,
> - 0x021b4848, 0x3C3C3846,
> - 0x021b0850, 0x2e303230,
> - 0x021b4850, 0x38283E34,
> - 0x021b081c, 0x33333333,
> - 0x021b0820, 0x33333333,
> - 0x021b0824, 0x33333333,
> - 0x021b0828, 0x33333333,
> - 0x021b481c, 0x33333333,
> - 0x021b4820, 0x33333333,
> - 0x021b4824, 0x33333333,
> - 0x021b4828, 0x33333333,
> - 0x021b08c0, 0x24912492,
> - 0x021b48c0, 0x24912492,
> - 0x021b08b8, 0x00000800,
> - 0x021b48b8, 0x00000800,
> - 0x021b0004, 0x00020036,
> - 0x021b0008, 0x09444040,
> - 0x021b000c, 0x898E7955,
> - 0x021b0010, 0xFF328F64,
> - 0x021b0014, 0x01FF00DB,
> - 0x021b0018, 0x00001740,
> - 0x021b001c, 0x00008000,
> - 0x021b002c, 0x000026d2,
> - 0x021b0030, 0x008E1023,
> - 0x021b0040, 0x00000047,
> - 0x021b0400, 0x14420000,
> - 0x021b0000, 0x841A0000,
> - 0x00bb0008, 0x00000004,
> - 0x00bb000c, 0x2891E41A,
> - 0x00bb0038, 0x00000564,
> - 0x00bb0014, 0x00000040,
> - 0x00bb0028, 0x00000020,
> - 0x00bb002c, 0x00000020,
> - 0x021b001c, 0x04088032,
> - 0x021b001c, 0x00008033,
> - 0x021b001c, 0x00048031,
> - 0x021b001c, 0x09408030,
> - 0x021b001c, 0x04008040,
> - 0x021b0020, 0x00005800,
> - 0x021b0818, 0x00011117,
> - 0x021b4818, 0x00011117,
> - 0x021b0004, 0x00025576,
> - 0x021b0404, 0x00011006,
> - 0x021b001c, 0x00000000,
> - 0x020c4068, 0x00C03F3F,
> - 0x020c406c, 0x0030FC03,
> - 0x020c4070, 0x0FFFC000,
> - 0x020c4074, 0x3FF00000,
> - 0x020c4078, 0xFFFFF300,
> - 0x020c407c, 0x0F0000F3,
> - 0x020c4080, 0x00000FFF,
> - 0x020e0010, 0xF00000CF,
> - 0x020e0018, 0x77177717,
> - 0x020e001c, 0x77177717,
> -};
> -
> -static int mx6dl_dcd_table[] = {
> - 0x020e0774, 0x000C0000,
> - 0x020e0754, 0x00000000,
> - 0x020e04ac, 0x00000030,
> - 0x020e04b0, 0x00000030,
> - 0x020e0464, 0x00000030,
> - 0x020e0490, 0x00000030,
> - 0x020e074c, 0x00000030,
> - 0x020e0494, 0x00000030,
> - 0x020e04a0, 0x00000000,
> - 0x020e04b4, 0x00000030,
> - 0x020e04b8, 0x00000030,
> - 0x020e076c, 0x00000030,
> - 0x020e0750, 0x00020000,
> - 0x020e04bc, 0x00000028,
> - 0x020e04c0, 0x00000028,
> - 0x020e04c4, 0x00000028,
> - 0x020e04c8, 0x00000028,
> - 0x020e04cc, 0x00000028,
> - 0x020e04d0, 0x00000028,
> - 0x020e04d4, 0x00000028,
> - 0x020e04d8, 0x00000028,
> - 0x020e0760, 0x00020000,
> - 0x020e0764, 0x00000028,
> - 0x020e0770, 0x00000028,
> - 0x020e0778, 0x00000028,
> - 0x020e077c, 0x00000028,
> - 0x020e0780, 0x00000028,
> - 0x020e0784, 0x00000028,
> - 0x020e078c, 0x00000028,
> - 0x020e0748, 0x00000028,
> - 0x020e0470, 0x00000028,
> - 0x020e0474, 0x00000028,
> - 0x020e0478, 0x00000028,
> - 0x020e047c, 0x00000028,
> - 0x020e0480, 0x00000028,
> - 0x020e0484, 0x00000028,
> - 0x020e0488, 0x00000028,
> - 0x020e048c, 0x00000028,
> - 0x021b0800, 0xa1390003,
> - 0x021b080c, 0x001F001F,
> - 0x021b0810, 0x001F001F,
> - 0x021b480c, 0x001F001F,
> - 0x021b4810, 0x001F001F,
> - 0x021b083c, 0x42190217,
> - 0x021b0840, 0x017B017B,
> - 0x021b483c, 0x4176017B,
> - 0x021b4840, 0x015F016C,
> - 0x021b0848, 0x4C4C4D4C,
> - 0x021b4848, 0x4A4D4C48,
> - 0x021b0850, 0x3F3F3F40,
> - 0x021b4850, 0x3538382E,
> - 0x021b081c, 0x33333333,
> - 0x021b0820, 0x33333333,
> - 0x021b0824, 0x33333333,
> - 0x021b0828, 0x33333333,
> - 0x021b481c, 0x33333333,
> - 0x021b4820, 0x33333333,
> - 0x021b4824, 0x33333333,
> - 0x021b4828, 0x33333333,
> - 0x021b08b8, 0x00000800,
> - 0x021b48b8, 0x00000800,
> - 0x021b0004, 0x00020025,
> - 0x021b0008, 0x00333030,
> - 0x021b000c, 0x676B5313,
> - 0x021b0010, 0xB66E8B63,
> - 0x021b0014, 0x01FF00DB,
> - 0x021b0018, 0x00001740,
> - 0x021b001c, 0x00008000,
> - 0x021b002c, 0x000026d2,
> - 0x021b0030, 0x006B1023,
> - 0x021b0040, 0x00000047,
> - 0x021b0000, 0x841A0000,
> - 0x021b001c, 0x04008032,
> - 0x021b001c, 0x00008033,
> - 0x021b001c, 0x00048031,
> - 0x021b001c, 0x05208030,
> - 0x021b001c, 0x04008040,
> - 0x021b0020, 0x00005800,
> - 0x021b0818, 0x00011117,
> - 0x021b4818, 0x00011117,
> - 0x021b0004, 0x00025565,
> - 0x021b0404, 0x00011006,
> - 0x021b001c, 0x00000000,
> - 0x020c4068, 0x00C03F3F,
> - 0x020c406c, 0x0030FC03,
> - 0x020c4070, 0x0FFFC000,
> - 0x020c4074, 0x3FF00000,
> - 0x020c4078, 0xFFFFF300,
> - 0x020c407c, 0x0F0000C3,
> - 0x020c4080, 0x00000FFF,
> - 0x020e0010, 0xF00000CF,
> - 0x020e0018, 0x007F007F,
> - 0x020e001c, 0x007F007F,
> -};
> -
> -static void ddr_init(int *table, int size) -{
> - int i;
> -
> - for (i = 0; i < size / 2 ; i++)
> - writel(table[2 * i + 1], table[2 * i]);
> -}
> -
> -static void spl_dram_init(void)
> -{
> - if (is_mx6dq())
> - ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
> - else if (is_mx6dqp())
> - ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
> - else if (is_mx6sdl())
> - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> - /* DDR initialization */
> - spl_dram_init();
> -
> - /* setup AIPS and disable watchdog */
> - arch_cpu_init();
> -
> - ccgr_init();
> - gpr_init();
> -
> - /* iomux and setup of i2c */
> - board_early_init_f();
> -
> - /* setup GP timer */
> - timer_init();
> -
> - /* UART clocks enabled and gd valid - init serial console */
> - preloader_console_init();
> -
> - /* Clear the BSS. */
> - memset(__bss_start, 0, __bss_end - __bss_start);
> -
> - /* load/boot image from boot device */
> - board_init_r(NULL, 0);
> -}
> -#endif
> diff --git a/configs/mx6sabreauto_defconfig
> b/configs/mx6sabreauto_defconfig deleted file mode 100644 index
> 88565678467..00000000000
> --- a/configs/mx6sabreauto_defconfig
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_MX6=y
> -CONFIG_SYS_TEXT_BASE=0x17800000
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_TARGET_MX6SABREAUTO=y
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_LIBDISK_SUPPORT=y
> -CONFIG_NXP_BOARD_REVISION=y
> -CONFIG_NR_DRAM_BANKS=1
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.c
> fg"
> -# CONFIG_CONSOLE_MUX is not set
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> -CONFIG_SUPPORT_RAW_INITRD=y
> -CONFIG_SPL_EXT_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_WATCHDOG_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_BOOTZ=y
> -CONFIG_CMD_DFU=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_NAND_TRIMFFS=y
> -CONFIG_CMD_PART=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_FS_GENERIC=y
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_DFU_MMC=y
> -CONFIG_DFU_SF=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_NAND=y
> -CONFIG_NAND_MXS=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_MII=y
> -CONFIG_SPI=y
> -CONFIG_MXC_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="FSL"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> -CONFIG_CI_UDC=y
> -CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USB_HOST_ETHER=y
> -CONFIG_USB_ETHER_ASIX=y
> -CONFIG_VIDEO=y
> -# CONFIG_VIDEO_SW_CURSOR is not set
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/mx6sabreauto.h
> b/include/configs/mx6sabreauto.h deleted file mode 100644 index
> e444930dc87..00000000000
> --- a/include/configs/mx6sabreauto.h
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright (C) 2012 Freescale Semiconductor, Inc.
> - *
> - * Configuration settings for the Freescale i.MX6Q SabreAuto board.
> - */
> -
> -#ifndef __MX6SABREAUTO_CONFIG_H
> -#define __MX6SABREAUTO_CONFIG_H
> -
> -#ifdef CONFIG_SPL
> -#include "imx6_spl.h"
> -#endif
> -
> -#define CONFIG_MACH_TYPE 3529
> -#define CONFIG_MXC_UART_BASE UART4_BASE
> -#define CONSOLE_DEV "ttymxc3"
> -
> -/* USB Configs */
> -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
> -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> -#define CONFIG_MXC_USB_FLAGS 0
> -
> -#define CONFIG_PCA953X
> -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34,
> 8} }
> -
> -#include "mx6sabre_common.h"
> -
> -/* Falcon Mode */
> -#ifdef CONFIG_SPL_OS_BOOT
> -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
> -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
> -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
> -
> -/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
> -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /*
> 1MB */
> -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
> (CONFIG_CMD_SPL_WRITE_SIZE / 512)
> -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
> 0x1000 /* 2MB */
> -#endif
> -
> -#ifdef CONFIG_MTD_NOR_FLASH
> -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
> -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory
> banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on
> one chip */
> -#define CONFIG_SYS_FLASH_EMPTY_INFO
> -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> -#endif
> -
> -#define CONFIG_SYS_FSL_USDHC_NUM 2
> -#if defined(CONFIG_ENV_IS_IN_MMC)
> -#define CONFIG_SYS_MMC_ENV_DEV 0
> -#endif
> -
> -/* I2C Configs */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_MXC
> -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> -#define CONFIG_SYS_I2C_SPEED 100000
> -
> -/* NAND stuff */
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -#define CONFIG_SYS_NAND_BASE 0x40000000
> -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> -#define CONFIG_SYS_NAND_ONFI_DETECTION
> -
> -/* DMA stuff, needed for GPMI/MXS NAND support */
> -
> -/* PMIC */
> -#define CONFIG_POWER
> -#define CONFIG_POWER_I2C
> -#define CONFIG_POWER_PFUZE100
> -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
> -
> -#endif /* __MX6SABREAUTO_CONFIG_H */
> --
> 2.19.1.1215.g8438c0b245-goog
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 48/93] arm: Remove imx6q_logic board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (46 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 47/93] arm: Remove mx6sabreauto board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 18:10 ` Adam Ford
2018-11-19 15:53 ` [U-Boot] [PATCH 49/93] arm: Remove zc5202 board Simon Glass
` (49 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/logicpd/imx6/Kconfig | 12 --
board/logicpd/imx6/MAINTAINERS | 6 -
board/logicpd/imx6/Makefile | 10 -
board/logicpd/imx6/README | 37 ----
board/logicpd/imx6/imx6logic.c | 325 ---------------------------------
configs/imx6q_logic_defconfig | 77 --------
include/configs/imx6_logic.h | 172 -----------------
8 files changed, 640 deletions(-)
delete mode 100644 board/logicpd/imx6/Kconfig
delete mode 100644 board/logicpd/imx6/MAINTAINERS
delete mode 100644 board/logicpd/imx6/Makefile
delete mode 100644 board/logicpd/imx6/README
delete mode 100644 board/logicpd/imx6/imx6logic.c
delete mode 100644 configs/imx6q_logic_defconfig
delete mode 100644 include/configs/imx6_logic.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index face0f09827..7e0f9369eaf 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -548,7 +548,6 @@ source "board/freescale/mx6ullevk/Kconfig"
source "board/grinn/liteboard/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/liebherr/display5/Kconfig"
-source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
deleted file mode 100644
index f5e2f58b12b..00000000000
--- a/board/logicpd/imx6/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6LOGICPD
-
-config SYS_BOARD
- default "imx6"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_CONFIG_NAME
- default "imx6_logic"
-
-endif
diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
deleted file mode 100644
index 5db7d2cadd9..00000000000
--- a/board/logicpd/imx6/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX6LOGICPD BOARD
-M: Adam Ford <aford173@gmail.com>
-S: Maintained
-F: board/logicpd/imx6/
-F: include/configs/imx6_logic.h
-F: configs/imx6q_logic_defconfig
diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
deleted file mode 100644
index 337df9247df..00000000000
--- a/board/logicpd/imx6/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx6logic.o
-
diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
deleted file mode 100644
index df43b55d6bf..00000000000
--- a/board/logicpd/imx6/README
+++ /dev/null
@@ -1,37 +0,0 @@
-U-Boot for LogicPD i.MX6 Development Kit
-----------------------------------------
-
-This file contains information for the port of U-Boot to the Logic PD Development kit.
-
-Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
-board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has
-an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
-
-On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
-
-For more details about Logic PD i.MX6 Development kit, visit:
-https://www.logicpd.com/
-
-Building U-Boot for Logic PD Development Kit
---------------------------------------------
-To build U-Boot for the Dual and Quad variants:
-
- make imx6q_logic_defconfig
- make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
-
-
-Flashing U-Boot into the SD card
---------------------------------
-
-See README.imximage for details on booting from SD
-
-Flashing U-Boot into NAND
--------------------------
-Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
-with:
-
- kobs-ng init -v -x u-boot-dtb.imx
-
-Additional Support Documentation can be found at:
-https://support.logicpd.com/
-
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
deleted file mode 100644
index ce1c8a5d6bc..00000000000
--- a/board/logicpd/imx6/imx6logic.c
+++ /dev/null
@@ -1,325 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Logic PD, Inc.
- *
- * Author: Adam Ford <aford173@gmail.com>
- *
- * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
- * and updates by Jagan Teki <jagan@amarulasolutions.com>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <input.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <linux/sizes.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart3_pads[] = {
- MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void fixup_enet_clock(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct gpio_desc nint;
- struct gpio_desc reset;
- int ret;
-
- /* Set Ref Clock to 50 MHz */
- enable_fec_anatop_clock(0, ENET_50MHZ);
-
- /* Set GPIO_16 as ENET_REF_CLK_OUT */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- /* Request GPIO Pins to reset Ethernet with new clock */
- ret = dm_gpio_lookup_name("GPIO4_7", &nint);
- if (ret) {
- printf("Unable to lookup GPIO4_7\n");
- return;
- }
-
- ret = dm_gpio_request(&nint, "eth0_nInt");
- if (ret) {
- printf("Unable to request eth0_nInt\n");
- return;
- }
-
- /* Ensure nINT is input or PHY won't startup */
- dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
-
- ret = dm_gpio_lookup_name("GPIO4_9", &reset);
- if (ret) {
- printf("Unable to lookup GPIO4_9\n");
- return;
- }
-
- ret = dm_gpio_request(&reset, "eth0_reset");
- if (ret) {
- printf("Unable to request eth0_reset\n");
- return;
- }
-
- /* Reset LAN8710A PHY */
- dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
- dm_gpio_set_value(&reset, 0);
- udelay(150);
- dm_gpio_set_value(&reset, 1);
- mdelay(50);
-}
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
- imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
-}
-
-static iomux_v3_cfg_t const nand_pads[] = {
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
-};
-
-static void setup_nand_pins(void)
-{
- imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_early_init_f(void)
-{
- fixup_enet_clock();
- setup_iomux_uart();
- setup_nand_pins();
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- return 0;
-}
-
-int board_late_init(void)
-{
- env_set("board_name", "imx6logic");
-
- if (is_mx6dq()) {
- env_set("board_rev", "MX6DQ");
- env_set("fdt_file", "imx6q-logicpd.dtb");
- }
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6q-ddr.h>
-#include <spl.h>
-#include <linux/libfdt.h>
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- return 0;
-}
-#endif
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0xFFFFF300, &ccm->CCGR4);
- writel(0x0F0000F3, &ccm->CCGR5);
- writel(0x00000FFF, &ccm->CCGR6);
-}
-
-static int mx6q_dcd_table[] = {
- MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
- MX6_IOM_GRP_DDRPKE, 0x00000000,
- MX6_IOM_DRAM_SDCLK_0, 0x00000030,
- MX6_IOM_DRAM_SDCLK_1, 0x00000030,
- MX6_IOM_DRAM_CAS, 0x00000030,
- MX6_IOM_DRAM_RAS, 0x00000030,
- MX6_IOM_GRP_ADDDS, 0x00000030,
- MX6_IOM_DRAM_RESET, 0x00000030,
- MX6_IOM_DRAM_SDBA2, 0x00000000,
- MX6_IOM_DRAM_SDODT0, 0x00000030,
- MX6_IOM_DRAM_SDODT1, 0x00000030,
- MX6_IOM_GRP_CTLDS, 0x00000030,
- MX6_IOM_DDRMODE_CTL, 0x00020000,
- MX6_IOM_DRAM_SDQS0, 0x00000030,
- MX6_IOM_DRAM_SDQS1, 0x00000030,
- MX6_IOM_DRAM_SDQS2, 0x00000030,
- MX6_IOM_DRAM_SDQS3, 0x00000030,
- MX6_IOM_GRP_DDRMODE, 0x00020000,
- MX6_IOM_GRP_B0DS, 0x00000030,
- MX6_IOM_GRP_B1DS, 0x00000030,
- MX6_IOM_GRP_B2DS, 0x00000030,
- MX6_IOM_GRP_B3DS, 0x00000030,
- MX6_IOM_DRAM_DQM0, 0x00000030,
- MX6_IOM_DRAM_DQM1, 0x00000030,
- MX6_IOM_DRAM_DQM2, 0x00000030,
- MX6_IOM_DRAM_DQM3, 0x00000030,
- MX6_MMDC_P0_MDSCR, 0x00008000,
- MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
- MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
- MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
- MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
- MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
- MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
- MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
- MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
- MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
- MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
- MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
- MX6_MMDC_P0_MPMUR0, 0x00000800,
- MX6_MMDC_P0_MDPDC, 0x00020036,
- MX6_MMDC_P0_MDOTC, 0x09444040,
- MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
- MX6_MMDC_P0_MDCFG1, 0xFF328F64,
- MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
- MX6_MMDC_P0_MDMISC, 0x00011740,
- MX6_MMDC_P0_MDSCR, 0x00008000,
- MX6_MMDC_P0_MDRWD, 0x000026D2,
- MX6_MMDC_P0_MDOR, 0x00BE1023,
- MX6_MMDC_P0_MDASP, 0x00000047,
- MX6_MMDC_P0_MDCTL, 0x85190000,
- MX6_MMDC_P0_MDSCR, 0x00888032,
- MX6_MMDC_P0_MDSCR, 0x00008033,
- MX6_MMDC_P0_MDSCR, 0x00008031,
- MX6_MMDC_P0_MDSCR, 0x19408030,
- MX6_MMDC_P0_MDSCR, 0x04008040,
- MX6_MMDC_P0_MDREF, 0x00007800,
- MX6_MMDC_P0_MPODTCTRL, 0x00000007,
- MX6_MMDC_P0_MDPDC, 0x00025576,
- MX6_MMDC_P0_MAPSR, 0x00011006,
- MX6_MMDC_P0_MDSCR, 0x00000000,
- /* enable AXI cache for VDOA/VPU/IPU */
-
- MX6_IOMUXC_GPR4, 0xF00000CF,
- /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
- MX6_IOMUXC_GPR6, 0x007F007F,
- MX6_IOMUXC_GPR7, 0x007F007F,
-};
-
-static void ddr_init(int *table, int size)
-{
- int i;
-
- for (i = 0; i < size / 2 ; i++)
- writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
- if (is_mx6dq())
- ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
-}
-
-void board_init_f(ulong dummy)
-{
- /* DDR initialization */
- spl_dram_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of uart and NAND pins */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
deleted file mode 100644
index 036069a4374..00000000000
--- a/configs/imx6q_logic_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_MX6LOGICPD=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_PROMPT="i.MX6 Logic # "
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_LED is not set
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
-CONFIG_CMD_UBI=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SPL_DM=y
-CONFIG_PCF8575_GPIO=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_FSL_ESDHC=y
-CONFIG_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_PMIC_PFUZE100=y
-CONFIG_MXC_UART=y
-CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
deleted file mode 100644
index e55941408c9..00000000000
--- a/include/configs/imx6_logic.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Logic PD, Inc.
- *
- * Configuration settings for the LogicPD i.MX6 SOM.
- */
-
-#ifndef __IMX6LOGIC_CONFIG_H
-#define __IMX6LOGIC_CONFIG_H
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONSOLE_DEV "ttymxc0"
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#include "mx6_common.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
-
-/* Ethernet Configs */
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "bootm_size=0x10000000\0" \
- "fdt_addr_r=0x13000000\0" \
- "ramdisk_addr_r=0x14000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_file=rootfs.cpio.uboot\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "console=" CONSOLE_DEV "\0" \
- "mmcdev=1\0" \
- "mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "nandroot=ubi0:rootfs rootfstype=ubifs\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate}" \
- " root=${mmcroot} ${mtdparts}\0" \
- "nandargs=setenv bootargs console=${console},${baudrate}" \
- " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
- "ramargs=setenv bootargs console=${console},${baudrate}" \
- " root=/dev/ram rw ${mtdparts}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...;" \
- " source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \
- " setenv kernelsize ${filesize}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \
- "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \
- " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \
- "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
- " run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \
- "mmcramboot=run ramargs; run loadimage;" \
- " run loadfdt; run loadramdisk;" \
- " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "nandboot=echo Booting from nand ...; " \
- " run nandargs;" \
- " nand read ${loadaddr} kernel ${kernelsize};" \
- " nand read ${fdt_addr} dtb;" \
- " bootz ${loadaddr} - ${fdt_addr}\0" \
- "nandramboot=echo Booting RAMdisk from nand ...; " \
- " nand read ${ramdisk_addr_r} fs ${ramdisksize};" \
- " nand read ${loadaddr} kernel ${kernelsize};" \
- " nand read ${fdt_addr_r} dtb;" \
- " run ramargs;" \
- " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs" \
- " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "autoboot=mmc dev ${mmcdev};" \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-#define CONFIG_BOOTCOMMAND \
- "run autoboot"
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (1024 * 1024)
-#define CONFIG_ENV_OFFSET 0x400000
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-
-/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
-/* MTD device */
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* EEPROM contains serial no, MAC addr and other Logic PD info */
-#define CONFIG_I2C_EEPROM
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
-#endif
-
-/* Falcon Mode */
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x15000000
-
-/* Falcon Mode - MMC support: args at 1MB kernel@2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
-
-#endif /* __IMX6LOGIC_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 48/93] arm: Remove imx6q_logic board
2018-11-19 15:53 ` [U-Boot] [PATCH 48/93] arm: Remove imx6q_logic board Simon Glass
@ 2018-11-19 18:10 ` Adam Ford
2018-11-27 0:08 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Adam Ford @ 2018-11-19 18:10 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 9:55 AM Simon Glass <sjg@chromium.org> wrote:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
NAK. I disagree with your assessment.
make imx6q_logic_defconfig
cat .config | grep BLK
CONFIG_BLK=y
CONFIG_SPL_BLK=y
Like the other board, I think you're looking for CONFIG_DM_BLK when
you should be looking for CONFIG_BLK which is dependent on DM
adam
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-imx/mx6/Kconfig | 1 -
> board/logicpd/imx6/Kconfig | 12 --
> board/logicpd/imx6/MAINTAINERS | 6 -
> board/logicpd/imx6/Makefile | 10 -
> board/logicpd/imx6/README | 37 ----
> board/logicpd/imx6/imx6logic.c | 325 ---------------------------------
> configs/imx6q_logic_defconfig | 77 --------
> include/configs/imx6_logic.h | 172 -----------------
> 8 files changed, 640 deletions(-)
> delete mode 100644 board/logicpd/imx6/Kconfig
> delete mode 100644 board/logicpd/imx6/MAINTAINERS
> delete mode 100644 board/logicpd/imx6/Makefile
> delete mode 100644 board/logicpd/imx6/README
> delete mode 100644 board/logicpd/imx6/imx6logic.c
> delete mode 100644 configs/imx6q_logic_defconfig
> delete mode 100644 include/configs/imx6_logic.h
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index face0f09827..7e0f9369eaf 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -548,7 +548,6 @@ source "board/freescale/mx6ullevk/Kconfig"
> source "board/grinn/liteboard/Kconfig"
> source "board/kosagi/novena/Kconfig"
> source "board/liebherr/display5/Kconfig"
> -source "board/logicpd/imx6/Kconfig"
> source "board/seco/Kconfig"
> source "board/solidrun/mx6cuboxi/Kconfig"
> source "board/technexion/pico-imx6ul/Kconfig"
> diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
> deleted file mode 100644
> index f5e2f58b12b..00000000000
> --- a/board/logicpd/imx6/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MX6LOGICPD
> -
> -config SYS_BOARD
> - default "imx6"
> -
> -config SYS_VENDOR
> - default "logicpd"
> -
> -config SYS_CONFIG_NAME
> - default "imx6_logic"
> -
> -endif
> diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
> deleted file mode 100644
> index 5db7d2cadd9..00000000000
> --- a/board/logicpd/imx6/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MX6LOGICPD BOARD
> -M: Adam Ford <aford173@gmail.com>
> -S: Maintained
> -F: board/logicpd/imx6/
> -F: include/configs/imx6_logic.h
> -F: configs/imx6q_logic_defconfig
> diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
> deleted file mode 100644
> index 337df9247df..00000000000
> --- a/board/logicpd/imx6/Makefile
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -#
> -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> -#
> -# (C) Copyright 2011 Freescale Semiconductor, Inc.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := imx6logic.o
> -
> diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
> deleted file mode 100644
> index df43b55d6bf..00000000000
> --- a/board/logicpd/imx6/README
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -U-Boot for LogicPD i.MX6 Development Kit
> -----------------------------------------
> -
> -This file contains information for the port of U-Boot to the Logic PD Development kit.
> -
> -Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
> -board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has
> -an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
> -
> -On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
> -
> -For more details about Logic PD i.MX6 Development kit, visit:
> -https://www.logicpd.com/
> -
> -Building U-Boot for Logic PD Development Kit
> ---------------------------------------------
> -To build U-Boot for the Dual and Quad variants:
> -
> - make imx6q_logic_defconfig
> - make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
> -
> -
> -Flashing U-Boot into the SD card
> ---------------------------------
> -
> -See README.imximage for details on booting from SD
> -
> -Flashing U-Boot into NAND
> --------------------------
> -Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
> -with:
> -
> - kobs-ng init -v -x u-boot-dtb.imx
> -
> -Additional Support Documentation can be found at:
> -https://support.logicpd.com/
> -
> diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
> deleted file mode 100644
> index ce1c8a5d6bc..00000000000
> --- a/board/logicpd/imx6/imx6logic.c
> +++ /dev/null
> @@ -1,325 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2017 Logic PD, Inc.
> - *
> - * Author: Adam Ford <aford173@gmail.com>
> - *
> - * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
> - * and updates by Jagan Teki <jagan@amarulasolutions.com>
> - */
> -
> -#include <common.h>
> -#include <miiphy.h>
> -#include <input.h>
> -#include <mmc.h>
> -#include <fsl_esdhc.h>
> -#include <asm/io.h>
> -#include <asm/gpio.h>
> -#include <linux/sizes.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/crm_regs.h>
> -#include <asm/arch/iomux.h>
> -#include <asm/arch/mxc_hdmi.h>
> -#include <asm/arch/mx6-pins.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/mach-imx/boot_mode.h>
> -#include <asm/mach-imx/iomux-v3.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> -
> -int dram_init(void)
> -{
> - gd->ram_size = imx_ddr_size();
> - return 0;
> -}
> -
> -static iomux_v3_cfg_t const uart1_pads[] = {
> - MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
> -static iomux_v3_cfg_t const uart2_pads[] = {
> - MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
> -static iomux_v3_cfg_t const uart3_pads[] = {
> - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
> -static void fixup_enet_clock(void)
> -{
> - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> - struct gpio_desc nint;
> - struct gpio_desc reset;
> - int ret;
> -
> - /* Set Ref Clock to 50 MHz */
> - enable_fec_anatop_clock(0, ENET_50MHZ);
> -
> - /* Set GPIO_16 as ENET_REF_CLK_OUT */
> - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> -
> - /* Request GPIO Pins to reset Ethernet with new clock */
> - ret = dm_gpio_lookup_name("GPIO4_7", &nint);
> - if (ret) {
> - printf("Unable to lookup GPIO4_7\n");
> - return;
> - }
> -
> - ret = dm_gpio_request(&nint, "eth0_nInt");
> - if (ret) {
> - printf("Unable to request eth0_nInt\n");
> - return;
> - }
> -
> - /* Ensure nINT is input or PHY won't startup */
> - dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
> -
> - ret = dm_gpio_lookup_name("GPIO4_9", &reset);
> - if (ret) {
> - printf("Unable to lookup GPIO4_9\n");
> - return;
> - }
> -
> - ret = dm_gpio_request(&reset, "eth0_reset");
> - if (ret) {
> - printf("Unable to request eth0_reset\n");
> - return;
> - }
> -
> - /* Reset LAN8710A PHY */
> - dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
> - dm_gpio_set_value(&reset, 0);
> - udelay(150);
> - dm_gpio_set_value(&reset, 1);
> - mdelay(50);
> -}
> -
> -static void setup_iomux_uart(void)
> -{
> - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
> - imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
> -}
> -
> -static iomux_v3_cfg_t const nand_pads[] = {
> - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> -};
> -
> -static void setup_nand_pins(void)
> -{
> - imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
> -}
> -
> -int board_phy_config(struct phy_device *phydev)
> -{
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> -
> - return 0;
> -}
> -
> -/*
> - * Do not overwrite the console
> - * Use always serial for U-Boot console
> - */
> -int overwrite_console(void)
> -{
> - return 1;
> -}
> -
> -int board_early_init_f(void)
> -{
> - fixup_enet_clock();
> - setup_iomux_uart();
> - setup_nand_pins();
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* address of boot parameters */
> - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> - return 0;
> -}
> -
> -int board_late_init(void)
> -{
> - env_set("board_name", "imx6logic");
> -
> - if (is_mx6dq()) {
> - env_set("board_rev", "MX6DQ");
> - env_set("fdt_file", "imx6q-logicpd.dtb");
> - }
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_SPL_BUILD
> -#include <asm/arch/mx6-ddr.h>
> -#include <asm/arch/mx6q-ddr.h>
> -#include <spl.h>
> -#include <linux/libfdt.h>
> -
> -#ifdef CONFIG_SPL_OS_BOOT
> -int spl_start_uboot(void)
> -{
> - /* break into full u-boot on 'c' */
> - if (serial_tstc() && serial_getc() == 'c')
> - return 1;
> -
> - return 0;
> -}
> -#endif
> -
> -static void ccgr_init(void)
> -{
> - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -
> - writel(0x00C03F3F, &ccm->CCGR0);
> - writel(0x0030FC03, &ccm->CCGR1);
> - writel(0x0FFFC000, &ccm->CCGR2);
> - writel(0x3FF00000, &ccm->CCGR3);
> - writel(0xFFFFF300, &ccm->CCGR4);
> - writel(0x0F0000F3, &ccm->CCGR5);
> - writel(0x00000FFF, &ccm->CCGR6);
> -}
> -
> -static int mx6q_dcd_table[] = {
> - MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
> - MX6_IOM_GRP_DDRPKE, 0x00000000,
> - MX6_IOM_DRAM_SDCLK_0, 0x00000030,
> - MX6_IOM_DRAM_SDCLK_1, 0x00000030,
> - MX6_IOM_DRAM_CAS, 0x00000030,
> - MX6_IOM_DRAM_RAS, 0x00000030,
> - MX6_IOM_GRP_ADDDS, 0x00000030,
> - MX6_IOM_DRAM_RESET, 0x00000030,
> - MX6_IOM_DRAM_SDBA2, 0x00000000,
> - MX6_IOM_DRAM_SDODT0, 0x00000030,
> - MX6_IOM_DRAM_SDODT1, 0x00000030,
> - MX6_IOM_GRP_CTLDS, 0x00000030,
> - MX6_IOM_DDRMODE_CTL, 0x00020000,
> - MX6_IOM_DRAM_SDQS0, 0x00000030,
> - MX6_IOM_DRAM_SDQS1, 0x00000030,
> - MX6_IOM_DRAM_SDQS2, 0x00000030,
> - MX6_IOM_DRAM_SDQS3, 0x00000030,
> - MX6_IOM_GRP_DDRMODE, 0x00020000,
> - MX6_IOM_GRP_B0DS, 0x00000030,
> - MX6_IOM_GRP_B1DS, 0x00000030,
> - MX6_IOM_GRP_B2DS, 0x00000030,
> - MX6_IOM_GRP_B3DS, 0x00000030,
> - MX6_IOM_DRAM_DQM0, 0x00000030,
> - MX6_IOM_DRAM_DQM1, 0x00000030,
> - MX6_IOM_DRAM_DQM2, 0x00000030,
> - MX6_IOM_DRAM_DQM3, 0x00000030,
> - MX6_MMDC_P0_MDSCR, 0x00008000,
> - MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
> - MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
> - MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
> - MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
> - MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
> - MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
> - MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
> - MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
> - MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
> - MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
> - MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
> - MX6_MMDC_P0_MPMUR0, 0x00000800,
> - MX6_MMDC_P0_MDPDC, 0x00020036,
> - MX6_MMDC_P0_MDOTC, 0x09444040,
> - MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
> - MX6_MMDC_P0_MDCFG1, 0xFF328F64,
> - MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
> - MX6_MMDC_P0_MDMISC, 0x00011740,
> - MX6_MMDC_P0_MDSCR, 0x00008000,
> - MX6_MMDC_P0_MDRWD, 0x000026D2,
> - MX6_MMDC_P0_MDOR, 0x00BE1023,
> - MX6_MMDC_P0_MDASP, 0x00000047,
> - MX6_MMDC_P0_MDCTL, 0x85190000,
> - MX6_MMDC_P0_MDSCR, 0x00888032,
> - MX6_MMDC_P0_MDSCR, 0x00008033,
> - MX6_MMDC_P0_MDSCR, 0x00008031,
> - MX6_MMDC_P0_MDSCR, 0x19408030,
> - MX6_MMDC_P0_MDSCR, 0x04008040,
> - MX6_MMDC_P0_MDREF, 0x00007800,
> - MX6_MMDC_P0_MPODTCTRL, 0x00000007,
> - MX6_MMDC_P0_MDPDC, 0x00025576,
> - MX6_MMDC_P0_MAPSR, 0x00011006,
> - MX6_MMDC_P0_MDSCR, 0x00000000,
> - /* enable AXI cache for VDOA/VPU/IPU */
> -
> - MX6_IOMUXC_GPR4, 0xF00000CF,
> - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> - MX6_IOMUXC_GPR6, 0x007F007F,
> - MX6_IOMUXC_GPR7, 0x007F007F,
> -};
> -
> -static void ddr_init(int *table, int size)
> -{
> - int i;
> -
> - for (i = 0; i < size / 2 ; i++)
> - writel(table[2 * i + 1], table[2 * i]);
> -}
> -
> -static void spl_dram_init(void)
> -{
> - if (is_mx6dq())
> - ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> - /* DDR initialization */
> - spl_dram_init();
> -
> - /* setup AIPS and disable watchdog */
> - arch_cpu_init();
> -
> - ccgr_init();
> - gpr_init();
> -
> - /* iomux and setup of uart and NAND pins */
> - board_early_init_f();
> -
> - /* setup GP timer */
> - timer_init();
> -
> - /* UART clocks enabled and gd valid - init serial console */
> - preloader_console_init();
> -
> - /* Clear the BSS. */
> - memset(__bss_start, 0, __bss_end - __bss_start);
> -
> - /* load/boot image from boot device */
> - board_init_r(NULL, 0);
> -}
> -#endif
> diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
> deleted file mode 100644
> index 036069a4374..00000000000
> --- a/configs/imx6q_logic_defconfig
> +++ /dev/null
> @@ -1,77 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_MX6=y
> -CONFIG_SYS_TEXT_BASE=0x17800000
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_TARGET_MX6LOGICPD=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
> -CONFIG_SPL=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> -CONFIG_BOOTDELAY=3
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> -CONFIG_SPL_SEPARATE_BSS=y
> -CONFIG_SPL_DMA_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_NAND_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -CONFIG_SPL_USB_HOST_SUPPORT=y
> -CONFIG_SPL_USB_GADGET_SUPPORT=y
> -CONFIG_SPL_USB_SDP_SUPPORT=y
> -CONFIG_SPL_WATCHDOG_SUPPORT=y
> -CONFIG_SYS_PROMPT="i.MX6 Logic # "
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_SPL_WRITE_SIZE=0x20000
> -CONFIG_CMD_MEMTEST=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_NAND_TRIMFFS=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_USB_SDP=y
> -CONFIG_CMD_USB_MASS_STORAGE=y
> -CONFIG_CMD_CACHE=y
> -# CONFIG_CMD_LED is not set
> -CONFIG_CMD_PMIC=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
> -CONFIG_CMD_UBI=y
> -CONFIG_SPL_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_SPL_DM=y
> -CONFIG_PCF8575_GPIO=y
> -CONFIG_SYS_I2C_MXC=y
> -CONFIG_LED=y
> -CONFIG_LED_GPIO=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_NAND=y
> -CONFIG_NAND_MXS=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_FEC_MXC=y
> -CONFIG_MII=y
> -CONFIG_PINCTRL=y
> -CONFIG_SPL_PINCTRL=y
> -CONFIG_PINCTRL_IMX6=y
> -CONFIG_DM_PMIC_PFUZE100=y
> -CONFIG_MXC_UART=y
> -CONFIG_USB=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="FSL"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> -CONFIG_CI_UDC=y
> -CONFIG_USB_GADGET_DOWNLOAD=y
> diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
> deleted file mode 100644
> index e55941408c9..00000000000
> --- a/include/configs/imx6_logic.h
> +++ /dev/null
> @@ -1,172 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright (C) 2017 Logic PD, Inc.
> - *
> - * Configuration settings for the LogicPD i.MX6 SOM.
> - */
> -
> -#ifndef __IMX6LOGIC_CONFIG_H
> -#define __IMX6LOGIC_CONFIG_H
> -
> -#define CONFIG_MXC_UART_BASE UART1_BASE
> -#define CONSOLE_DEV "ttymxc0"
> -
> -#ifdef CONFIG_SPL
> -#include "imx6_spl.h"
> -#endif
> -
> -#include "mx6_common.h"
> -
> -/* Size of malloc() pool */
> -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
> -
> -/* MMC Configs */
> -#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> -#define CONFIG_SYS_FSL_USDHC_NUM 2
> -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
> -
> -/* Ethernet Configs */
> -#define CONFIG_FEC_XCV_TYPE RMII
> -#define CONFIG_ETHPRIME "FEC"
> -#define CONFIG_FEC_MXC_PHYADDR 0
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "script=boot.scr\0" \
> - "image=zImage\0" \
> - "bootm_size=0x10000000\0" \
> - "fdt_addr_r=0x13000000\0" \
> - "ramdisk_addr_r=0x14000000\0" \
> - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> - "ramdisk_file=rootfs.cpio.uboot\0" \
> - "boot_fdt=try\0" \
> - "ip_dyn=yes\0" \
> - "console=" CONSOLE_DEV "\0" \
> - "mmcdev=1\0" \
> - "mmcpart=1\0" \
> - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> - "nandroot=ubi0:rootfs rootfstype=ubifs\0" \
> - "mmcargs=setenv bootargs console=${console},${baudrate}" \
> - " root=${mmcroot} ${mtdparts}\0" \
> - "nandargs=setenv bootargs console=${console},${baudrate}" \
> - " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
> - "ramargs=setenv bootargs console=${console},${baudrate}" \
> - " root=/dev/ram rw ${mtdparts}\0" \
> - "loadbootscript=" \
> - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> - "bootscript=echo Running bootscript from mmc ...;" \
> - " source\0" \
> - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \
> - " setenv kernelsize ${filesize}\0" \
> - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \
> - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \
> - " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \
> - "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
> - " run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \
> - "mmcramboot=run ramargs; run loadimage;" \
> - " run loadfdt; run loadramdisk;" \
> - " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
> - "nandboot=echo Booting from nand ...; " \
> - " run nandargs;" \
> - " nand read ${loadaddr} kernel ${kernelsize};" \
> - " nand read ${fdt_addr} dtb;" \
> - " bootz ${loadaddr} - ${fdt_addr}\0" \
> - "nandramboot=echo Booting RAMdisk from nand ...; " \
> - " nand read ${ramdisk_addr_r} fs ${ramdisksize};" \
> - " nand read ${loadaddr} kernel ${kernelsize};" \
> - " nand read ${fdt_addr_r} dtb;" \
> - " run ramargs;" \
> - " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
> - "netargs=setenv bootargs console=${console},${baudrate} " \
> - "root=/dev/nfs" \
> - " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> - "netboot=echo Booting from net ...; " \
> - "run netargs; " \
> - "if test ${ip_dyn} = yes; then " \
> - "setenv get_cmd dhcp; " \
> - "else " \
> - "setenv get_cmd tftp; " \
> - "fi; " \
> - "${get_cmd} ${image}; " \
> - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> - "bootz ${loadaddr} - ${fdt_addr}; " \
> - "else " \
> - "if test ${boot_fdt} = try; then " \
> - "bootz; " \
> - "else " \
> - "echo WARN: Cannot load the DT; " \
> - "fi; " \
> - "fi; " \
> - "else " \
> - "bootz; " \
> - "fi;\0" \
> - "autoboot=mmc dev ${mmcdev};" \
> - "if mmc rescan; then " \
> - "if run loadbootscript; then " \
> - "run bootscript; " \
> - "else " \
> - "if run loadimage; then " \
> - "run mmcboot; " \
> - "else run netboot; " \
> - "fi; " \
> - "fi; " \
> - "else run netboot; fi"
> -#define CONFIG_BOOTCOMMAND \
> - "run autoboot"
> -
> -#define CONFIG_ARP_TIMEOUT 200UL
> -
> -#define CONFIG_SYS_MEMTEST_START 0x10000000
> -#define CONFIG_SYS_MEMTEST_END 0x10010000
> -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
> -
> -/* Physical Memory Map */
> -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> -
> -#define CONFIG_SYS_INIT_SP_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_ADDR \
> - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> -
> -/* Environment organization */
> -#define CONFIG_ENV_SIZE (1024 * 1024)
> -#define CONFIG_ENV_OFFSET 0x400000
> -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
> -
> -/* NAND stuff */
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1
> -#define CONFIG_SYS_NAND_BASE 0x40000000
> -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> -#define CONFIG_SYS_NAND_ONFI_DETECTION
> -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
> -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
> -/* MTD device */
> -
> -/* DMA stuff, needed for GPMI/MXS NAND support */
> -
> -/* EEPROM contains serial no, MAC addr and other Logic PD info */
> -#define CONFIG_I2C_EEPROM
> -
> -/* USB Configs */
> -#ifdef CONFIG_CMD_USB
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> -#define CONFIG_MXC_USB_FLAGS 0
> -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
> -#endif
> -
> -/* Falcon Mode */
> -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
> -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
> -#define CONFIG_SYS_SPL_ARGS_ADDR 0x15000000
> -
> -/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
> -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
> -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
> -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
> -
> -#endif /* __IMX6LOGIC_CONFIG_H */
> --
> 2.19.1.1215.g8438c0b245-goog
>
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 48/93] arm: Remove imx6q_logic board
2018-11-19 18:10 ` Adam Ford
@ 2018-11-27 0:08 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-27 0:08 UTC (permalink / raw)
To: u-boot
Hi Adam,
On Mon, 19 Nov 2018 at 11:10, Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Nov 19, 2018 at 9:55 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
>
> NAK. I disagree with your assessment.
>
> make imx6q_logic_defconfig
> cat .config | grep BLK
> CONFIG_BLK=y
> CONFIG_SPL_BLK=y
>
> Like the other board, I think you're looking for CONFIG_DM_BLK when
> you should be looking for CONFIG_BLK which is dependent on DM
>
> adam
>
Yes it is the latter one that changed, as per my other emails. I
changed the default for SPL to n, which fixed some boards but
unfortunately broke others.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 49/93] arm: Remove zc5202 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (47 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 48/93] arm: Remove imx6q_logic board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 50/93] arm: Remove imx6dl_mamoj board Simon Glass
` (48 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/el/el6x/Kconfig | 25 --
board/el/el6x/MAINTAINERS | 8 -
board/el/el6x/Makefile | 5 -
board/el/el6x/el6x.c | 631 ----------------------------------
configs/zc5202_defconfig | 42 ---
configs/zc5601_defconfig | 41 ---
include/configs/zc5202.h | 30 --
include/configs/zc5601.h | 28 --
9 files changed, 811 deletions(-)
delete mode 100644 board/el/el6x/Kconfig
delete mode 100644 board/el/el6x/MAINTAINERS
delete mode 100644 board/el/el6x/Makefile
delete mode 100644 board/el/el6x/el6x.c
delete mode 100644 configs/zc5202_defconfig
delete mode 100644 configs/zc5601_defconfig
delete mode 100644 include/configs/zc5202.h
delete mode 100644 include/configs/zc5601.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 7e0f9369eaf..6f59044d4ff 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -532,7 +532,6 @@ source "board/bticino/mamoj/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
-source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig
deleted file mode 100644
index aa9bf25fb47..00000000000
--- a/board/el/el6x/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_ZC5202
-
-config SYS_BOARD
- default "el6x"
-
-config SYS_VENDOR
- default "el"
-
-config SYS_CONFIG_NAME
- default "zc5202"
-
-endif
-
-if TARGET_ZC5601
-
-config SYS_BOARD
- default "el6x"
-
-config SYS_VENDOR
- default "el"
-
-config SYS_CONFIG_NAME
- default "zc5601"
-
-endif
diff --git a/board/el/el6x/MAINTAINERS b/board/el/el6x/MAINTAINERS
deleted file mode 100644
index 9a40010f50e..00000000000
--- a/board/el/el6x/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-EL6X BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/el/el6x/
-F: include/configs/zc5202.h
-F: include/configs/zc5601.h
-F: configs/zc5202_defconfig
-F: configs/zc5601_defconfig
diff --git a/board/el/el6x/Makefile b/board/el/el6x/Makefile
deleted file mode 100644
index 065a867475a..00000000000
--- a/board/el/el6x/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) Stefano Babic <sbabic@denx.de>
-
-obj-y := el6x.o
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
deleted file mode 100644
index dd0c1120888..00000000000
--- a/board/el/el6x/el6x.c
+++ /dev/null
@@ -1,631 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- *
- * Based on other i.MX6 boards
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <input.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include <asm/arch/mx6-ddr.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12))
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC 1
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define ETH_PHY_RESET IMX_GPIO_NR(2, 4)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}
-
-#ifdef CONFIG_TARGET_ZC5202
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- /* Switch Reset */
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- /* Switch Interrupt */
- MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* use CRS and COL pads as GPIOs */
- MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
- MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
-
-};
-
-#define BOARD_NAME "EL6x-ZC5202"
-#else
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#define BOARD_NAME "EL6x-ZC5601"
-#endif
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
-#ifdef CONFIG_TARGET_ZC5202
- /* set CRS and COL to input */
- gpio_direction_input(IMX_GPIO_NR(4, 9));
- gpio_direction_input(IMX_GPIO_NR(4, 12));
-
- /* Reset Switch */
- gpio_direction_output(ETH_PHY_RESET , 0);
- mdelay(2);
- gpio_set_value(ETH_PHY_RESET, 1);
-#endif
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-#ifdef CONFIG_TARGET_ZC5202
-iomux_v3_cfg_t const ecspi1_pads[] = {
- MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const ecspi3_pads[] = {
- MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-#endif
-
-iomux_v3_cfg_t const ecspi4_pads[] = {
- MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
- ? (IMX_GPIO_NR(3, 20)) : -1;
-}
-
-static void setup_spi(void)
-{
-#ifdef CONFIG_TARGET_ZC5202
- gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
- gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
- gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
- gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-#endif
-
- gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
- gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
- imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
-
- enable_spi_clk(true, 3);
-}
-#endif
-
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
- .gp = IMX_GPIO_NR(7, 11)
- }
-};
-
-iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC2_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- int ret;
- int i;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 SD2
- * mmc1 SD3
- * mmc2 eMMC
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-#else
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
-
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x2 SD2
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x3:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- }
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-
-}
-#endif
-
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
- enable_enet_clk(1);
-
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
-
- setup_iomux_uart();
- setup_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
- return 0;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
- int ret;
- unsigned int reg;
-
- ret = power_pfuze100_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE100");
- ret = pmic_probe(p);
- if (ret)
- return ret;
-
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Increase VGEN3 from 2.5 to 2.8V */
- pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
- reg &= ~LDO_VOL_MASK;
- reg |= LDOB_2_80V;
- pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
-
- /* Increase VGEN5 from 2.8 to 3V */
- pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
- reg &= ~LDO_VOL_MASK;
- reg |= LDOB_3_00V;
- pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
-
- /* Set SW1AB stanby volage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
- reg &= ~SW1x_STBY_MASK;
- reg |= SW1x_0_975V;
- pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
-
- /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
- reg &= ~SW1xCONF_DVSSPEED_MASK;
- reg |= SW1xCONF_DVSSPEED_4US;
- pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
-
- /* Set SW1C standby voltage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
- reg &= ~SW1x_STBY_MASK;
- reg |= SW1x_0_975V;
- pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
-
- /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
- reg &= ~SW1xCONF_DVSSPEED_MASK;
- reg |= SW1xCONF_DVSSPEED_4US;
- pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
- env_set("board_name", BOARD_NAME);
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: ");
- puts(BOARD_NAME "\n");
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#include <linux/libfdt.h>
-
-const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x001F001F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x00440044,
- .p1_mpwldectrl1 = 0x00440044,
- .p0_mpdgctrl0 = 0x434B0350,
- .p0_mpdgctrl1 = 0x034C0359,
- .p1_mpdgctrl0 = 0x434B0350,
- .p1_mpdgctrl1 = 0x03650348,
- .p0_mprddlctl = 0x4436383B,
- .p1_mprddlctl = 0x39393341,
- .p0_mpwrdlctl = 0x35373933,
- .p1_mpwrdlctl = 0x48254A36,
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-/*
- * This section requires the differentiation between iMX6 Sabre boards, but
- * for now, it will configure only for the mx6q variant.
- */
-static void spl_dram_init(void)
-{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-
-#endif
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
deleted file mode 100644
index c79cd22936f..00000000000
--- a/configs/zc5202_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_ZC5202=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
deleted file mode 100644
index e92c63df129..00000000000
--- a/configs/zc5601_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_ZC5601=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h
deleted file mode 100644
index 40d33f7830a..00000000000
--- a/include/configs/zc5202.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- *
- * Configuration settings for the E+L i.MX6Q DO82 board.
- */
-
-#ifndef __EL_ZC5202_H
-#define __EL_ZC5202_H
-
-#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONSOLE_DEV "ttymxc1"
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
-
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-#include "el6x_common.h"
-
-/* Ethernet */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE MII100
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_MV88E6352_SWITCH
-
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-
-#endif /*__EL6Q_CONFIG_H */
diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h
deleted file mode 100644
index b9673e2c065..00000000000
--- a/include/configs/zc5601.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- *
- * Configuration settings for the E+L i.MX6Q DO82 board.
- */
-
-#ifndef __EL_ZC5601_H
-#define __EL_ZC5601_H
-
-
-#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONSOLE_DEV "ttymxc1"
-#define CONFIG_MMCROOT "/dev/mmcblk0p1"
-
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-#include "el6x_common.h"
-
-/* Ethernet */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0x10
-#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */
-
-#endif /*__EL6Q_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 50/93] arm: Remove imx6dl_mamoj board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (48 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 49/93] arm: Remove zc5202 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 17:22 ` Jagan Teki
2018-11-19 15:53 ` [U-Boot] [PATCH 51/93] arm: Remove omap3_logic_somlv board Simon Glass
` (47 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/dts/imx6dl-mamoj-u-boot.dtsi | 14 --
arch/arm/dts/imx6dl-mamoj.dts | 225 --------------------------
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/bticino/mamoj/Kconfig | 12 --
board/bticino/mamoj/MAINTAINERS | 10 --
board/bticino/mamoj/Makefile | 8 -
board/bticino/mamoj/README | 124 --------------
board/bticino/mamoj/mamoj.c | 26 ---
board/bticino/mamoj/spl.c | 171 --------------------
configs/imx6dl_mamoj_defconfig | 46 ------
include/configs/imx6dl-mamoj.h | 99 ------------
11 files changed, 736 deletions(-)
delete mode 100644 arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
delete mode 100644 arch/arm/dts/imx6dl-mamoj.dts
delete mode 100644 board/bticino/mamoj/Kconfig
delete mode 100644 board/bticino/mamoj/MAINTAINERS
delete mode 100644 board/bticino/mamoj/Makefile
delete mode 100644 board/bticino/mamoj/README
delete mode 100644 board/bticino/mamoj/mamoj.c
delete mode 100644 board/bticino/mamoj/spl.c
delete mode 100644 configs/imx6dl_mamoj_defconfig
delete mode 100644 include/configs/imx6dl-mamoj.h
diff --git a/arch/arm/dts/imx6dl-mamoj-u-boot.dtsi b/arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
deleted file mode 100644
index 3af57ff8eb8..00000000000
--- a/arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
- */
-
-#include "imx6qdl-u-boot.dtsi"
-
-&usdhc3 {
- u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
- u-boot,dm-spl;
-};
diff --git a/arch/arm/dts/imx6dl-mamoj.dts b/arch/arm/dts/imx6dl-mamoj.dts
deleted file mode 100644
index 3f6d8aa4a25..00000000000
--- a/arch/arm/dts/imx6dl-mamoj.dts
+++ /dev/null
@@ -1,225 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2018 BTicino
- * Copyright (C) 2018 Amarula Solutions B.V.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "imx6dl.dtsi"
-
-/ {
- model = "BTicino i.MX6DL Mamoj board";
- compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "mii";
- status = "okay";
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- pmic: pfuze100 at 08 {
- compatible = "fsl,pfuze100";
- reg = <0x08>;
-
- regulators {
- /* CPU vdd_arm core */
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- /* SOC vdd_soc */
- sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- /* I/O power GEN_3V3 */
- sw2_reg: sw2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* DDR memory */
- sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* DDR memory */
- sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* not used */
- sw4_reg: sw4 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- /* not used */
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- /* PMIC vsnvs. EX boot mode */
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* not used */
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- /* not used */
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- /* not used */
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- /* 1v8 general power */
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- /* 2v8 general power IMX6 */
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- /* 3v3 Ethernet */
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- bus-width = <8>;
- non-removable;
- keep-power-in-suspend;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
- MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
- MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
- MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
- >;
- };
-};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 6f59044d4ff..c001aaf8cb6 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -528,7 +528,6 @@ source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
-source "board/bticino/mamoj/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
diff --git a/board/bticino/mamoj/Kconfig b/board/bticino/mamoj/Kconfig
deleted file mode 100644
index e5aec589c87..00000000000
--- a/board/bticino/mamoj/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6DL_MAMOJ
-
-config SYS_BOARD
- default "mamoj"
-
-config SYS_VENDOR
- default "bticino"
-
-config SYS_CONFIG_NAME
- default "imx6dl-mamoj"
-
-endif
diff --git a/board/bticino/mamoj/MAINTAINERS b/board/bticino/mamoj/MAINTAINERS
deleted file mode 100644
index c35b387a820..00000000000
--- a/board/bticino/mamoj/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-MX6DL_MAMOJ BOARD
-M: Jagan Teki <jagan@amarulasolutions.com>
-M: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
-M: Simone CIANNI <simone.cianni@bticino.it>
-S: Maintained
-F: board/bticino/mamoj
-F: include/configs/imx6dl-mamoj.h
-F: configs/imx6dl_mamoj_defconfig
-F: arch/arm/dts/imx6dl-mamoj.dts
-F: arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
diff --git a/board/bticino/mamoj/Makefile b/board/bticino/mamoj/Makefile
deleted file mode 100644
index f1ddda48918..00000000000
--- a/board/bticino/mamoj/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (C) 2018 BTicino
-# Copyright (C) 2017 Amarula Solutions B.V.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mamoj.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/bticino/mamoj/README b/board/bticino/mamoj/README
deleted file mode 100644
index 5333c72537a..00000000000
--- a/board/bticino/mamoj/README
+++ /dev/null
@@ -1,124 +0,0 @@
-BTicino Mamoj board:
-===================
-
-Build:
-
- $ make mrproper
- $ make imx6dl_mamoj_defconfig
- $ make
-
- This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-The following methods can be used for booting Mamoj boards:
-
-1. USB SDP boot
-
-2. eMMC boot (via DFU)
-
-3. Falcon mode
-
-1. USB SDP boot:
----------------
-
- - Build imx_usb_loader
-
- $ git clone git://github.com/boundarydevices/imx_usb_loader.git
- $ cd imx_usb_loader
- $ make
-
- - Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory
-
- - Put the board in "Serial Download Mode"
-
- - Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host
-
- - Turn-on board
-
- - Identify VID/PID using lsusb
-
- Bus 001 Device 010: ID 15a2:0061 Freescale Semiconductor, Inc. i.MX 6Solo/6DualLite SystemOnChip in RecoveryMode
-
- - Update the conf files
-
- imx_usb.conf
- 0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf
-
- mx6_usb_rom.conf
- mx6_usb
- hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000
- SPL:jump header2
-
- mx6_usb_sdp_spl.conf
- mx6_spl_sdp
- hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000
- u-boot-dtb.img:jump header2
-
- - Launch the loader
-
- $ ./imx_usb
-
- We can see U-Boot boot from USB SDP on minicom
-
-2. eMMC boot via DFU:
---------------------
-
- Once booted from USB SDP, program the eMMC as below(make sure to connect USB OTG)
-
- - Change eMMC partition config
-
- => mmc partconf 2 1 0 0
-
- - Partition eMMC on host
-
- => ums 0 mmc 2
-
- Host will able to detect the eMMC disk as UMS, partition the same.
-
- - Program SPL
-
- => setenv dfu_alt_info $dfu_alt_info_spl
- => dfu 0 mmc 2
-
- At Host
-
- # dfu-util -D SPL -a spl
-
- - Program u-boot-dtb.img
-
- => setenv dfu_alt_info $dfu_alt_info_uboot
- => dfu 0 mmc 2
-
- At Host
-
- # dfu-util -D u-boot-dtb.img -a u-boot
-
- Poweroff and Poweron the board and see U-Boot booting from eMMC.
-
-3. Falcon mode:
---------------
-
- - Skip 10M space and create dual partitions for eMMC, start sector is 20480
-
- Partition Map for MMC device 2 -- Partition Type: DOS
-
- Part Start Sector Num Sectors UUID Type
- 1 20480 131072 c52e78be-01 83
- 2 151552 7581696 c52e78be-02 83
-
- - Write uImage
-
- => fatload mmc 2:1 $kernel_addr_r uImage
- => mmc write $kernel_addr_r 0x1000 0x4000
-
- - Write dtb and args
-
- => setenv bootargs console=ttymxc2,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw quiet
- => fatload mmc 2:1 $fdt_addr_r imx6dl-mamoj.dtb
- => spl export fdt $kernel_addr_r - $fdt_addr_r
- => mmc write 0x13000000 0x800 0x800
-
- Poweroff and Poweron the board and see Linux booting directly after SPL.
-
---
-Jagan Teki <jagan@amarulasolutions.com>
-03/12/18
diff --git a/board/bticino/mamoj/mamoj.c b/board/bticino/mamoj/mamoj.c
deleted file mode 100644
index 6ad7e31092b..00000000000
--- a/board/bticino/mamoj/mamoj.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
- * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
- * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
diff --git a/board/bticino/mamoj/spl.c b/board/bticino/mamoj/spl.c
deleted file mode 100644
index c53bdce0ceb..00000000000
--- a/board/bticino/mamoj/spl.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
- * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
- * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include <asm/io.h>
-#include <linux/sizes.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define IMX6SDL_DRIVE_STRENGTH 0x28
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart3_pads[] = {
- IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- return 0;
-}
-#endif
-
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
-};
-
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
-};
-
-static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
- .mem_speed = 1600,
- .density = 4,
- .width = 32,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 0,
-};
-
-static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0042004b,
- .p0_mpwldectrl1 = 0x0038003c,
- .p0_mpdgctrl0 = 0x42340230,
- .p0_mpdgctrl1 = 0x0228022c,
- .p0_mprddlctl = 0x42444646,
- .p0_mpwrdlctl = 0x38382e2e,
-};
-
-static struct mx6_ddr_sysinfo mem_dl = {
- .dsize = 1,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 1,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1,
- .refr = 7,
-};
-
-static void spl_dram_init(void)
-{
- mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
-
- udelay(100);
-}
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00003f3f, &ccm->CCGR0);
- writel(0x0030fc00, &ccm->CCGR1);
- writel(0x000fc000, &ccm->CCGR2);
- writel(0x3f300000, &ccm->CCGR3);
- writel(0xff00f300, &ccm->CCGR4);
- writel(0x0f0000c3, &ccm->CCGR5);
- writel(0x000003cc, &ccm->CCGR6);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- gpr_init();
-
- /* iomux */
- SETUP_IOMUX_PADS(uart3_pads);
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
deleted file mode 100644
index a7c5c3628de..00000000000
--- a/configs/imx6dl_mamoj_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SECURE_BOOT=y
-CONFIG_TARGET_MX6DL_MAMOJ=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DFU_MMC=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FASTBOOT_BUF_SIZE=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=2
-CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_MXC_UART=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h
deleted file mode 100644
index 030dbedce81..00000000000
--- a/include/configs/imx6dl-mamoj.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
- * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
- * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
- *
- * Configuration settings for the BTicion i.MX6DL Mamoj board.
- */
-
-#ifndef __IMX6DL_MAMOJ_CONFIG_H
-#define __IMX6DL_MAMOJ_CONFIG_H
-
-#include <linux/sizes.h>
-#include "mx6_common.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
-
-/* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE SZ_128K
-
-/* Allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Environment */
-#ifndef CONFIG_ENV_IS_NOWHERE
-/* Environment in MMC */
-# if defined(CONFIG_ENV_IS_IN_MMC)
-# define CONFIG_ENV_OFFSET 0x100000
-# endif
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "scriptaddr=0x14000000\0" \
- "fdt_addr_r=0x13000000\0" \
- "kernel_addr_r=0x10008000\0" \
- "fdt_high=0xffffffff\0" \
- "dfu_alt_info_spl=spl raw 0x2 0x400\0" \
- "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 2)
-
-#include <config_distro_bootcmd.h>
-#endif
-
-/* UART */
-#define CONFIG_MXC_UART_BASE UART3_BASE
-
-/* MMC */
-#define CONFIG_SYS_MMC_ENV_DEV 2
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-/* Ethernet */
-#define CONFIG_FEC_MXC_PHYADDR 1
-
-/* USB */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* Falcon */
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
-#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
-
-/* MMC support: args at 1MB kernel at 2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_SP_OFFSET)
-
-/* SPL */
-#include "imx6_spl.h"
-
-#endif /* __IMX6DL_MAMOJ_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 50/93] arm: Remove imx6dl_mamoj board
2018-11-19 15:53 ` [U-Boot] [PATCH 50/93] arm: Remove imx6dl_mamoj board Simon Glass
@ 2018-11-19 17:22 ` Jagan Teki
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Jagan Teki @ 2018-11-19 17:22 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 9:25 PM Simon Glass <sjg@chromium.org> wrote:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
It is CONFIG_BLK right? which is driver model block layer and it's
already enabled. Did I missed anything?
₹ ls drivers/block/*.o
drivers/block/blkcache.o drivers/block/blk-uclass.o drivers/block/built-in.o
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 50/93] arm: Remove imx6dl_mamoj board
2018-11-19 17:22 ` Jagan Teki
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Jagan,
On Mon, 19 Nov 2018 at 10:23, Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Mon, Nov 19, 2018 at 9:25 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> It is CONFIG_BLK right? which is driver model block layer and it's
> already enabled. Did I missed anything?
>
> ₹ ls drivers/block/*.o
> drivers/block/blkcache.o drivers/block/blk-uclass.o drivers/block/built-in.o
This was the result of my removing the default CONFIG_SPL_BLK=y in the
Kconfig, since it produced a smaller list of broken boards. But having
thought about it, it is not the right thing to do.
So this board should be fine. Sorry for the trouble.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 51/93] arm: Remove omap3_logic_somlv board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (49 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 50/93] arm: Remove imx6dl_mamoj board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 18:07 ` Adam Ford
2018-11-19 15:53 ` [U-Boot] [PATCH 52/93] arm: Remove cm_t335 board Simon Glass
` (46 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/logicpd/omap3som/Kconfig | 14 --
board/logicpd/omap3som/MAINTAINERS | 9 -
board/logicpd/omap3som/Makefile | 6 -
board/logicpd/omap3som/README | 56 -----
board/logicpd/omap3som/omap3logic.c | 329 ---------------------------
board/logicpd/omap3som/omap3logic.h | 236 -------------------
configs/omap35_logic_defconfig | 72 ------
configs/omap35_logic_somlv_defconfig | 78 -------
configs/omap3_logic_defconfig | 73 ------
configs/omap3_logic_somlv_defconfig | 78 -------
include/configs/omap3_logic.h | 210 -----------------
12 files changed, 1162 deletions(-)
delete mode 100644 board/logicpd/omap3som/Kconfig
delete mode 100644 board/logicpd/omap3som/MAINTAINERS
delete mode 100644 board/logicpd/omap3som/Makefile
delete mode 100644 board/logicpd/omap3som/README
delete mode 100644 board/logicpd/omap3som/omap3logic.c
delete mode 100644 board/logicpd/omap3som/omap3logic.h
delete mode 100644 configs/omap35_logic_defconfig
delete mode 100644 configs/omap35_logic_somlv_defconfig
delete mode 100644 configs/omap3_logic_defconfig
delete mode 100644 configs/omap3_logic_somlv_defconfig
delete mode 100644 include/configs/omap3_logic.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index edd5e3f255b..6e3942ad2d3 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -203,7 +203,6 @@ source "board/ti/am3517crane/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
deleted file mode 100644
index 68d40dcd62d..00000000000
--- a/board/logicpd/omap3som/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_OMAP3_LOGIC
-
-config SYS_BOARD
- default "omap3som"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_CONFIG_NAME
- default "omap3_logic"
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS
deleted file mode 100644
index 459393cf54c..00000000000
--- a/board/logicpd/omap3som/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-OMAP3SOM BOARD
-M: Adam Ford <aford173@gmail.com>
-S: Maintained
-F: board/logicpd/omap3som/
-F: include/configs/omap3_logic.h
-F: configs/omap3_logic_defconfig
-F: configs/omap35_logic_defconfig
-F: configs/omap35_logic_somlv_defconfig
-F: configs/omap3_logic_somlv_defconfig
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
deleted file mode 100644
index 61ef14e87a0..00000000000
--- a/board/logicpd/omap3som/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := omap3logic.o
diff --git a/board/logicpd/omap3som/README b/board/logicpd/omap3som/README
deleted file mode 100644
index 5aaf58f0a69..00000000000
--- a/board/logicpd/omap3som/README
+++ /dev/null
@@ -1,56 +0,0 @@
-Summary
-=======
-
-The source for omap3logic.c encompases the OMAP35 and DM3730 SOM-LV and DM3730 Torpedo platforms, but there are device trees custom taylored to each board.
-
-omap3_logic_defconfig = DM37 Torpedo / Torpedo + Wireless
-omap35_logic_defconfig = OMAP35 Torpedo
-omap3_logic_somlv_defconfig = DM37 SOM-LV
-omap35_logic_somlv_defconfig = OMAP35 SOM-LV
-
-The device tree included with each of the defconfig files will also direct the board as to which dtb file to load when loading the kernel, so it is not
-recomended to mix and match the defconfig files.
-
-Falcon Mode: FAT SD cards
-=========================
-
-In this case the additional file is written to the filesystem. In this
-example we assume that the uImage and device tree to be used are already on
-the FAT filesystem (only the uImage MUST be for this to function
-afterwards) along with a Falcon Mode aware MLO and the FAT partition has
-already been created and marked bootable:
-
-U-Boot # mmc rescan
-# Load kernel and device tree into memory, perform export
-U-Boot # fatload mmc 0 ${loadaddr} uImage
-U-Boot # run loadfdt
-U-Boot # setenv optargs quiet
-U-Boot # run mmcargs
-U-Boot # run common_bootargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-
-This will print a number of lines and then end with something like:
- Loading Device Tree to 8dec9000, end 8dee0295 ... OK
-
-So then note the starting address and write the args to mmc/sd:
-
-U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000
-
-The size of 0x20000 matches the CMD_SPL_WRITE_SIZE.
-
-Falcon Mode: NAND
-=================
-
-In this case the additional data is written to another partition of the
-NAND. In this example we assume that the uImage and device tree to be are
-already located on the NAND somewhere (such as filesystem or mtd partition)
-along with a Falcon Mode aware MLO written to the correct locations for
-booting and mtdparts have been configured correctly for the board:
-
-U-Boot # nand read ${loadaddr} kernel
-U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
-U-Boot # run nandargs
-U-Boot # run common_bootargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-U-Boot # nand erase.part u-boot-spl-os
-U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
deleted file mode 100644
index 691d38fdf27..00000000000
--- a/board/logicpd/omap3som/omap3logic.c
+++ /dev/null
@@ -1,329 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * Logic Product Development <www.logicpd.com>
- *
- * Author :
- * Peter Barada <peter.barada@logicpd.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <netdev.h>
-#include <flash.h>
-#include <nand.h>
-#include <i2c.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/omap_mmc.h>
-#include <asm/mach-types.h>
-#include <linux/mtd/rawnand.h>
-#include <asm/omap_musb.h>
-#include <linux/errno.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <linux/usb/musb.h>
-#include "omap3logic.h"
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
-#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
-
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
-#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
-
-/* This is only needed until SPL gets OF support */
-#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata omap3logic_serial = {
- .base = OMAP34XX_UART1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(omap3logic_uart) = {
- "omap_serial",
- &omap3logic_serial
-};
-
-static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = {
- .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
- .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
- .cfg.f_min = 400000,
- .cfg.f_max = 52000000,
- .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
- .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-U_BOOT_DEVICE(omap3_logic_mmc0) = {
- .name = "omap_hsmmc",
- .platdata = &omap3_logic_mmc0_platdata,
-};
-
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return serial_tstc() && serial_getc() == 'c';
-}
-#endif
-
-#if defined(CONFIG_SPL_BUILD)
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank. This
- * provides the timing values back to the function that configures
- * the memory.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->mr = MICRON_V_MR_165;
-
- if (get_cpu_family() == CPU_OMAP36XX) {
- /* 200 MHz works for OMAP36/DM37 */
- /* 256MB DDR */
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- } else {
- /* 165 MHz works for OMAP35 */
- timings->mcfg = MICRON_V_MCFG_165(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
-}
-
-#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
-#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
-#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
-
-void spl_board_prepare_for_linux(void)
-{
- /* The Micron NAND starts locked which
- * prohibits mounting the NAND as RW
- * The following commands are what unlocks
- * the NAND to become RW Falcon Mode does not
- * have as many smarts as U-Boot, but Logic PD
- * only makes NAND with 512MB so these hard coded
- * values should work for all current models
- */
-
- writeb(0x70, GPMC_NAND_COMMAND_0);
- writeb(-1, GPMC_NAND_DATA_0);
- writeb(0x7a, GPMC_NAND_COMMAND_0);
- writeb(0x00, GPMC_NAND_ADDRESS_0);
- writeb(0x00, GPMC_NAND_ADDRESS_0);
- writeb(0x00, GPMC_NAND_ADDRESS_0);
- writeb(-1, GPMC_NAND_COMMAND_0);
-
- /* Begin address 0 */
- writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
- writeb(0x00, GPMC_NAND_ADDRESS_0);
- writeb(0x00, GPMC_NAND_ADDRESS_0);
- writeb(0x00, GPMC_NAND_ADDRESS_0);
- writeb(-1, GPMC_NAND_DATA_0);
-
- /* Ending address at the end of Flash */
- writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
- writeb(0xc0, GPMC_NAND_ADDRESS_0);
- writeb(0xff, GPMC_NAND_ADDRESS_0);
- writeb(0x03, GPMC_NAND_ADDRESS_0);
- writeb(-1, GPMC_NAND_DATA_0);
- writeb(0x79, GPMC_NAND_COMMAND_0);
- writeb(-1, GPMC_NAND_DATA_0);
- writeb(-1, GPMC_NAND_DATA_0);
-}
-#endif
-
-#if !CONFIG_IS_ENABLED(DM_USB)
-#ifdef CONFIG_USB_MUSB_OMAP2PLUS
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
-#endif
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-#endif
-
-#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
-/* Call usb_stop() before starting the kernel */
-void show_boot_progress(int val)
-{
- if (val == BOOTSTAGE_ID_RUN_OS)
- usb_stop();
-}
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-
-#endif /* CONFIG_USB_EHCI_HCD */
-#endif /* !DM_USB*/
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- twl4030_power_init();
- omap_die_id_display();
-
-#if !CONFIG_IS_ENABLED(DM_USB)
-#ifdef CONFIG_USB_MUSB_OMAP2PLUS
- musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
-#endif
-#endif
- return 0;
-}
-
-#if defined(CONFIG_FLASH_CFI_DRIVER)
-static const u32 gpmc_dm37_c2nor_config[] = {
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
- LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
-};
-
-static const u32 gpmc_omap35_c2nor_config[] = {
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
- LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
-};
-#endif
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-#if defined(CONFIG_FLASH_CFI_DRIVER)
- if (get_cpu_family() == CPU_OMAP36XX) {
- /* Enable CS2 for NOR Flash */
- enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
- 0x10000000, GPMC_SIZE_64M);
- } else {
- enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
- 0x10000000, GPMC_SIZE_64M);
- }
-#endif
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-
-static void unlock_nand(void)
-{
- int dev = nand_curr_device;
- struct mtd_info *mtd;
-
- mtd = get_nand_dev_by_index(dev);
- nand_unlock(mtd, 0, mtd->size, 0);
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
- unlock_nand();
-#endif
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_SMC911X
-/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
-static const u32 gpmc_lan92xx_config[] = {
- NET_LAN92XX_GPMC_CONFIG1,
- NET_LAN92XX_GPMC_CONFIG2,
- NET_LAN92XX_GPMC_CONFIG3,
- NET_LAN92XX_GPMC_CONFIG4,
- NET_LAN92XX_GPMC_CONFIG5,
- NET_LAN92XX_GPMC_CONFIG6,
-};
-
-int board_eth_init(bd_t *bis)
-{
- enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
deleted file mode 100644
index aeb26b90d71..00000000000
--- a/board/logicpd/omap3som/omap3logic.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Logic Product Development <www.logicpd.com>
- *
- * Author:
- * Peter Barada <peter.barada@logicpd.com>
- */
-#ifndef _OMAP3LOGIC_H_
-#define _OMAP3LOGIC_H_
-
-/*
- * OMAP3 GPMC register settings for CS1 LAN922x
- */
-#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
-#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
-#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
-#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
-#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
-#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
-
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "Logic DM37x/OMAP35x reference board",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
-
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
-
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
-
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
-
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
-
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
-
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
-}
-
-#endif
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
deleted file mode 100644
index 80219eeacfa..00000000000
--- a/configs/omap35_logic_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_OMAP3_LOGIC=y
-# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="OMAP Logic # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_EEPROM is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
-# CONFIG_ENV_IS_IN_FAT is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SPL_DM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x08000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="TI"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_BCH=y
-# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
deleted file mode 100644
index 8a8c7147c3a..00000000000
--- a/configs/omap35_logic_somlv_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_OMAP3_LOGIC=y
-# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="OMAP Logic # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_EEPROM is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
-# CONFIG_ENV_IS_IN_FAT is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SPL_DM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x08000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="TI"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_BCH=y
-# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
deleted file mode 100644
index 969387a37cb..00000000000
--- a/configs/omap3_logic_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_OMAP3_LOGIC=y
-# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="OMAP Logic # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_EEPROM is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
-# CONFIG_ENV_IS_IN_FAT is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SPL_DM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_OMAP36XX_PINS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x08000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="TI"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_BCH=y
-# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
deleted file mode 100644
index 396543e56bc..00000000000
--- a/configs/omap3_logic_somlv_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_OMAP3_LOGIC=y
-# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="OMAP Logic # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_EEPROM is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
-# CONFIG_ENV_IS_IN_FAT is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SPL_DM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MMC_OMAP36XX_PINS=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x08000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_DM_PMIC=y
-# CONFIG_SPL_PMIC_CHILDREN is not set
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="TI"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_BCH=y
-# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
deleted file mode 100644
index fe557f91caa..00000000000
--- a/include/configs/omap3_logic.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
- * Peter Barada <peter.barada@logicpd.com>
- *
- * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
- * reference boards.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-
-#include <configs/ti_omap3_common.h>
-
-/*
- * We are only ever GP parts and will utilize all of the "downloaded image"
- * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
- * order to allow for BCH8 to fit in.
- */
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE 0x40200000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Hardware drivers */
-
-/* I2C */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
-
-/* Board NAND Info. */
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
- 13, 14, 16, 17, 18, 19, 20, 21, 22, \
- 23, 24, 25, 26, 27, 28, 30, 31, 32, \
- 33, 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 44, 45, 46, 47, 48, 49, 50, 51, \
- 52, 53, 54, 55, 56}
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-#endif
-
-/* Environment information */
-
-#define CONFIG_PREBOOT \
- "setenv preboot;" \
- "saveenv;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
- "nandrootfstype=ubifs rootwait\0" \
- "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "run defaultboot;" \
- "fi; " \
- "else run defaultboot; fi\0" \
- "defaultboot=run mmcramboot\0" \
- "consoledevice=ttyS0\0" \
- "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
- "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
- "rotation=0\0" \
- "vrfb_arg=if itest ${rotation} -ne 0; then " \
- "setenv bootargs ${bootargs} omapfb.vrfb=y " \
- "omapfb.rotate=${rotation}; " \
- "fi\0" \
- "optargs=ignore_loglevel early_printk no_console_suspend\0" \
- "common_bootargs=run setconsole; setenv bootargs " \
- "${bootargs} "\
- "console=${console} " \
- "${mtdparts} "\
- "${optargs}; " \
- "run vrfb_arg\0" \
- "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo 'Running bootscript from mmc ...'; " \
- "source ${loadaddr}\0" \
- "loadimage=mmc rescan; " \
- "load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
- "ramdisksize=64000\0" \
- "ramdiskimage=rootfs.ext2.gz.uboot\0" \
- "loadramdisk=mmc rescan; " \
- "load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \
- "ramargs=setenv bootargs "\
- "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
- "mmcargs=setenv bootargs "\
- "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs "\
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nfsargs=setenv serverip ${tftpserver}; " \
- "setenv bootargs root=/dev/nfs " \
- "nfsroot=${nfsrootpath} " \
- "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \
- "nfsrootpath=/opt/nfs-exports/omap\0" \
- "autoload=no\0" \
- "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "loadfdt=mmc rescan; " \
- "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
- "mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "run common_bootargs; " \
- "run dump_bootargs; " \
- "run loadimage; " \
- "run loadfdt;\0 " \
- "mmcbootz=setenv bootfile zImage; " \
- "run mmcbootcommon; "\
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "mmcboot=setenv bootfile uImage; "\
- "run mmcbootcommon; "\
- "bootm ${loadaddr} - ${fdtaddr}\0" \
- "mmcrambootcommon=echo 'Booting kernel from MMC w/ramdisk...'; " \
- "run ramargs; " \
- "run common_bootargs; " \
- "run dump_bootargs; " \
- "run loadimage; " \
- "run loadfdt; " \
- "run loadramdisk\0" \
- "mmcramboot=setenv bootfile uImage; " \
- "run mmcrambootcommon; " \
- "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
- "mmcrambootz=setenv bootfile zImage; " \
- "run mmcrambootcommon; " \
- "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
- "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
- "run ramargs; " \
- "run common_bootargs; " \
- "run dump_bootargs; " \
- "tftpboot ${loadaddr} ${zimage}; " \
- "tftpboot ${rdaddr} ${ramdiskimage}; " \
- "bootm ${loadaddr} ${rdaddr}\0" \
- "tftpbootz=echo 'Booting kernel NFS rootfs...'; " \
- "dhcp;" \
- "run nfsargs;" \
- "run common_bootargs;" \
- "run dump_bootargs;" \
- "tftpboot $loadaddr zImage;" \
- "bootz $loadaddr\0" \
- "nandbootcommon=echo 'Booting kernel from NAND...';" \
- "run nandargs;" \
- "run common_bootargs;" \
- "run dump_bootargs;" \
- "nand read ${loadaddr} kernel;" \
- "nand read ${fdtaddr} spl-os;\0" \
- "nandbootz=run nandbootcommon; "\
- "bootz ${loadaddr} - ${fdtaddr}\0"\
- "nandboot=run nandbootcommon; "\
- "bootm ${loadaddr} - ${fdtaddr}\0"\
-
-#define CONFIG_BOOTCOMMAND \
- "run autoboot"
-
-/* Miscellaneous configurable options */
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-/* FLASH and environment organization */
-
-/* **** PISMO SUPPORT *** */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE 0x4000000
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-/* Defines for SPL */
-
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 51/93] arm: Remove omap3_logic_somlv board
2018-11-19 15:53 ` [U-Boot] [PATCH 51/93] arm: Remove omap3_logic_somlv board Simon Glass
@ 2018-11-19 18:07 ` Adam Ford
2018-11-27 0:08 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Adam Ford @ 2018-11-19 18:07 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 9:55 AM Simon Glass <sjg@chromium.org> wrote:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
NAK! This board does support BLK. I think your algorithm is looking
for CONFIG_DM_BLK when it should be looking for CONFIG_BLK which
depends on DM.
make omap3_logic_somlv_defconfig
cat .config | grep BLK
CONFIG_BLK=y
CONFIG_SPL_BLK=y
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-omap2/omap3/Kconfig | 1 -
> board/logicpd/omap3som/Kconfig | 14 --
> board/logicpd/omap3som/MAINTAINERS | 9 -
> board/logicpd/omap3som/Makefile | 6 -
> board/logicpd/omap3som/README | 56 -----
> board/logicpd/omap3som/omap3logic.c | 329 ---------------------------
> board/logicpd/omap3som/omap3logic.h | 236 -------------------
> configs/omap35_logic_defconfig | 72 ------
> configs/omap35_logic_somlv_defconfig | 78 -------
> configs/omap3_logic_defconfig | 73 ------
> configs/omap3_logic_somlv_defconfig | 78 -------
> include/configs/omap3_logic.h | 210 -----------------
> 12 files changed, 1162 deletions(-)
> delete mode 100644 board/logicpd/omap3som/Kconfig
> delete mode 100644 board/logicpd/omap3som/MAINTAINERS
> delete mode 100644 board/logicpd/omap3som/Makefile
> delete mode 100644 board/logicpd/omap3som/README
> delete mode 100644 board/logicpd/omap3som/omap3logic.c
> delete mode 100644 board/logicpd/omap3som/omap3logic.h
> delete mode 100644 configs/omap35_logic_defconfig
> delete mode 100644 configs/omap35_logic_somlv_defconfig
> delete mode 100644 configs/omap3_logic_defconfig
> delete mode 100644 configs/omap3_logic_somlv_defconfig
> delete mode 100644 include/configs/omap3_logic.h
>
> diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
> index edd5e3f255b..6e3942ad2d3 100644
> --- a/arch/arm/mach-omap2/omap3/Kconfig
> +++ b/arch/arm/mach-omap2/omap3/Kconfig
> @@ -203,7 +203,6 @@ source "board/ti/am3517crane/Kconfig"
> source "board/8dtech/eco5pk/Kconfig"
> source "board/corscience/tricorder/Kconfig"
> source "board/htkw/mcx/Kconfig"
> -source "board/logicpd/omap3som/Kconfig"
> source "board/nokia/rx51/Kconfig"
> source "board/technexion/tao3530/Kconfig"
> source "board/technexion/twister/Kconfig"
> diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
> deleted file mode 100644
> index 68d40dcd62d..00000000000
> --- a/board/logicpd/omap3som/Kconfig
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -if TARGET_OMAP3_LOGIC
> -
> -config SYS_BOARD
> - default "omap3som"
> -
> -config SYS_VENDOR
> - default "logicpd"
> -
> -config SYS_CONFIG_NAME
> - default "omap3_logic"
> -
> -source "board/ti/common/Kconfig"
> -
> -endif
> diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS
> deleted file mode 100644
> index 459393cf54c..00000000000
> --- a/board/logicpd/omap3som/MAINTAINERS
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -OMAP3SOM BOARD
> -M: Adam Ford <aford173@gmail.com>
> -S: Maintained
> -F: board/logicpd/omap3som/
> -F: include/configs/omap3_logic.h
> -F: configs/omap3_logic_defconfig
> -F: configs/omap35_logic_defconfig
> -F: configs/omap35_logic_somlv_defconfig
> -F: configs/omap3_logic_somlv_defconfig
> diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
> deleted file mode 100644
> index 61ef14e87a0..00000000000
> --- a/board/logicpd/omap3som/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2000, 2001, 2002
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -
> -obj-y := omap3logic.o
> diff --git a/board/logicpd/omap3som/README b/board/logicpd/omap3som/README
> deleted file mode 100644
> index 5aaf58f0a69..00000000000
> --- a/board/logicpd/omap3som/README
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -Summary
> -=======
> -
> -The source for omap3logic.c encompases the OMAP35 and DM3730 SOM-LV and DM3730 Torpedo platforms, but there are device trees custom taylored to each board.
> -
> -omap3_logic_defconfig = DM37 Torpedo / Torpedo + Wireless
> -omap35_logic_defconfig = OMAP35 Torpedo
> -omap3_logic_somlv_defconfig = DM37 SOM-LV
> -omap35_logic_somlv_defconfig = OMAP35 SOM-LV
> -
> -The device tree included with each of the defconfig files will also direct the board as to which dtb file to load when loading the kernel, so it is not
> -recomended to mix and match the defconfig files.
> -
> -Falcon Mode: FAT SD cards
> -=========================
> -
> -In this case the additional file is written to the filesystem. In this
> -example we assume that the uImage and device tree to be used are already on
> -the FAT filesystem (only the uImage MUST be for this to function
> -afterwards) along with a Falcon Mode aware MLO and the FAT partition has
> -already been created and marked bootable:
> -
> -U-Boot # mmc rescan
> -# Load kernel and device tree into memory, perform export
> -U-Boot # fatload mmc 0 ${loadaddr} uImage
> -U-Boot # run loadfdt
> -U-Boot # setenv optargs quiet
> -U-Boot # run mmcargs
> -U-Boot # run common_bootargs
> -U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
> -
> -This will print a number of lines and then end with something like:
> - Loading Device Tree to 8dec9000, end 8dee0295 ... OK
> -
> -So then note the starting address and write the args to mmc/sd:
> -
> -U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000
> -
> -The size of 0x20000 matches the CMD_SPL_WRITE_SIZE.
> -
> -Falcon Mode: NAND
> -=================
> -
> -In this case the additional data is written to another partition of the
> -NAND. In this example we assume that the uImage and device tree to be are
> -already located on the NAND somewhere (such as filesystem or mtd partition)
> -along with a Falcon Mode aware MLO written to the correct locations for
> -booting and mtdparts have been configured correctly for the board:
> -
> -U-Boot # nand read ${loadaddr} kernel
> -U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
> -U-Boot # run nandargs
> -U-Boot # run common_bootargs
> -U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
> -U-Boot # nand erase.part u-boot-spl-os
> -U-Boot # nand write ${fdtaddr} u-boot-spl-os
> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
> deleted file mode 100644
> index 691d38fdf27..00000000000
> --- a/board/logicpd/omap3som/omap3logic.c
> +++ /dev/null
> @@ -1,329 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * (C) Copyright 2011
> - * Logic Product Development <www.logicpd.com>
> - *
> - * Author :
> - * Peter Barada <peter.barada@logicpd.com>
> - *
> - * Derived from Beagle Board and 3430 SDP code by
> - * Richard Woodruff <r-woodruff2@ti.com>
> - * Syed Mohammed Khasim <khasim@ti.com>
> - */
> -#include <common.h>
> -#include <dm.h>
> -#include <ns16550.h>
> -#include <netdev.h>
> -#include <flash.h>
> -#include <nand.h>
> -#include <i2c.h>
> -#include <twl4030.h>
> -#include <asm/io.h>
> -#include <asm/arch/mmc_host_def.h>
> -#include <asm/arch/mux.h>
> -#include <asm/arch/mem.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/gpio.h>
> -#include <asm/omap_mmc.h>
> -#include <asm/mach-types.h>
> -#include <linux/mtd/rawnand.h>
> -#include <asm/omap_musb.h>
> -#include <linux/errno.h>
> -#include <linux/usb/ch9.h>
> -#include <linux/usb/gadget.h>
> -#include <linux/usb/musb.h>
> -#include "omap3logic.h"
> -#ifdef CONFIG_USB_EHCI_HCD
> -#include <usb.h>
> -#include <asm/ehci-omap.h>
> -#endif
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
> -#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
> -
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
> -#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
> -
> -/* This is only needed until SPL gets OF support */
> -#ifdef CONFIG_SPL_BUILD
> -static const struct ns16550_platdata omap3logic_serial = {
> - .base = OMAP34XX_UART1,
> - .reg_shift = 2,
> - .clock = V_NS16550_CLK,
> - .fcr = UART_FCR_DEFVAL,
> -};
> -
> -U_BOOT_DEVICE(omap3logic_uart) = {
> - "omap_serial",
> - &omap3logic_serial
> -};
> -
> -static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = {
> - .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
> - .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
> - .cfg.f_min = 400000,
> - .cfg.f_max = 52000000,
> - .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
> - .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
> -};
> -
> -U_BOOT_DEVICE(omap3_logic_mmc0) = {
> - .name = "omap_hsmmc",
> - .platdata = &omap3_logic_mmc0_platdata,
> -};
> -
> -#endif
> -
> -#ifdef CONFIG_SPL_OS_BOOT
> -int spl_start_uboot(void)
> -{
> - /* break into full u-boot on 'c' */
> - return serial_tstc() && serial_getc() == 'c';
> -}
> -#endif
> -
> -#if defined(CONFIG_SPL_BUILD)
> -/*
> - * Routine: get_board_mem_timings
> - * Description: If we use SPL then there is no x-loader nor config header
> - * so we have to setup the DDR timings ourself on the first bank. This
> - * provides the timing values back to the function that configures
> - * the memory.
> - */
> -void get_board_mem_timings(struct board_sdrc_timings *timings)
> -{
> - timings->mr = MICRON_V_MR_165;
> -
> - if (get_cpu_family() == CPU_OMAP36XX) {
> - /* 200 MHz works for OMAP36/DM37 */
> - /* 256MB DDR */
> - timings->mcfg = MICRON_V_MCFG_200(256 << 20);
> - timings->ctrla = MICRON_V_ACTIMA_200;
> - timings->ctrlb = MICRON_V_ACTIMB_200;
> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> - } else {
> - /* 165 MHz works for OMAP35 */
> - timings->mcfg = MICRON_V_MCFG_165(256 << 20);
> - timings->ctrla = MICRON_V_ACTIMA_165;
> - timings->ctrlb = MICRON_V_ACTIMB_165;
> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> - }
> -}
> -
> -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
> -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
> -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
> -
> -void spl_board_prepare_for_linux(void)
> -{
> - /* The Micron NAND starts locked which
> - * prohibits mounting the NAND as RW
> - * The following commands are what unlocks
> - * the NAND to become RW Falcon Mode does not
> - * have as many smarts as U-Boot, but Logic PD
> - * only makes NAND with 512MB so these hard coded
> - * values should work for all current models
> - */
> -
> - writeb(0x70, GPMC_NAND_COMMAND_0);
> - writeb(-1, GPMC_NAND_DATA_0);
> - writeb(0x7a, GPMC_NAND_COMMAND_0);
> - writeb(0x00, GPMC_NAND_ADDRESS_0);
> - writeb(0x00, GPMC_NAND_ADDRESS_0);
> - writeb(0x00, GPMC_NAND_ADDRESS_0);
> - writeb(-1, GPMC_NAND_COMMAND_0);
> -
> - /* Begin address 0 */
> - writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
> - writeb(0x00, GPMC_NAND_ADDRESS_0);
> - writeb(0x00, GPMC_NAND_ADDRESS_0);
> - writeb(0x00, GPMC_NAND_ADDRESS_0);
> - writeb(-1, GPMC_NAND_DATA_0);
> -
> - /* Ending address at the end of Flash */
> - writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
> - writeb(0xc0, GPMC_NAND_ADDRESS_0);
> - writeb(0xff, GPMC_NAND_ADDRESS_0);
> - writeb(0x03, GPMC_NAND_ADDRESS_0);
> - writeb(-1, GPMC_NAND_DATA_0);
> - writeb(0x79, GPMC_NAND_COMMAND_0);
> - writeb(-1, GPMC_NAND_DATA_0);
> - writeb(-1, GPMC_NAND_DATA_0);
> -}
> -#endif
> -
> -#if !CONFIG_IS_ENABLED(DM_USB)
> -#ifdef CONFIG_USB_MUSB_OMAP2PLUS
> -static struct musb_hdrc_config musb_config = {
> - .multipoint = 1,
> - .dyn_fifo = 1,
> - .num_eps = 16,
> - .ram_bits = 12,
> -};
> -
> -static struct omap_musb_board_data musb_board_data = {
> - .interface_type = MUSB_INTERFACE_ULPI,
> -};
> -
> -static struct musb_hdrc_platform_data musb_plat = {
> -#if defined(CONFIG_USB_MUSB_HOST)
> - .mode = MUSB_HOST,
> -#elif defined(CONFIG_USB_MUSB_GADGET)
> - .mode = MUSB_PERIPHERAL,
> -#else
> -#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
> -#endif
> - .config = &musb_config,
> - .power = 100,
> - .platform_ops = &omap2430_ops,
> - .board_data = &musb_board_data,
> -};
> -#endif
> -
> -#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
> -/* Call usb_stop() before starting the kernel */
> -void show_boot_progress(int val)
> -{
> - if (val == BOOTSTAGE_ID_RUN_OS)
> - usb_stop();
> -}
> -
> -static struct omap_usbhs_board_data usbhs_bdata = {
> - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
> - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
> - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
> -};
> -
> -int ehci_hcd_init(int index, enum usb_init_type init,
> - struct ehci_hccr **hccr, struct ehci_hcor **hcor)
> -{
> - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
> -}
> -
> -int ehci_hcd_stop(int index)
> -{
> - return omap_ehci_hcd_stop();
> -}
> -
> -#endif /* CONFIG_USB_EHCI_HCD */
> -#endif /* !DM_USB*/
> -/*
> - * Routine: misc_init_r
> - * Description: Configure board specific parts
> - */
> -int misc_init_r(void)
> -{
> - twl4030_power_init();
> - omap_die_id_display();
> -
> -#if !CONFIG_IS_ENABLED(DM_USB)
> -#ifdef CONFIG_USB_MUSB_OMAP2PLUS
> - musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
> -#endif
> -#endif
> - return 0;
> -}
> -
> -#if defined(CONFIG_FLASH_CFI_DRIVER)
> -static const u32 gpmc_dm37_c2nor_config[] = {
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
> - LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
> -};
> -
> -static const u32 gpmc_omap35_c2nor_config[] = {
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
> - LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
> -};
> -#endif
> -
> -/*
> - * Routine: board_init
> - * Description: Early hardware init.
> - */
> -int board_init(void)
> -{
> - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> -
> - /* boot param addr */
> - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> -#if defined(CONFIG_FLASH_CFI_DRIVER)
> - if (get_cpu_family() == CPU_OMAP36XX) {
> - /* Enable CS2 for NOR Flash */
> - enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
> - 0x10000000, GPMC_SIZE_64M);
> - } else {
> - enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
> - 0x10000000, GPMC_SIZE_64M);
> - }
> -#endif
> - return 0;
> -}
> -
> -#ifdef CONFIG_BOARD_LATE_INIT
> -
> -static void unlock_nand(void)
> -{
> - int dev = nand_curr_device;
> - struct mtd_info *mtd;
> -
> - mtd = get_nand_dev_by_index(dev);
> - nand_unlock(mtd, 0, mtd->size, 0);
> -}
> -
> -int board_late_init(void)
> -{
> -#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
> - unlock_nand();
> -#endif
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_MMC)
> -void board_mmc_power_init(void)
> -{
> - twl4030_power_mmc_init(0);
> -}
> -#endif
> -
> -#ifdef CONFIG_SMC911X
> -/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> -static const u32 gpmc_lan92xx_config[] = {
> - NET_LAN92XX_GPMC_CONFIG1,
> - NET_LAN92XX_GPMC_CONFIG2,
> - NET_LAN92XX_GPMC_CONFIG3,
> - NET_LAN92XX_GPMC_CONFIG4,
> - NET_LAN92XX_GPMC_CONFIG5,
> - NET_LAN92XX_GPMC_CONFIG6,
> -};
> -
> -int board_eth_init(bd_t *bis)
> -{
> - enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
> - CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
> -
> - return smc911x_initialize(0, CONFIG_SMC911X_BASE);
> -}
> -#endif
> diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
> deleted file mode 100644
> index aeb26b90d71..00000000000
> --- a/board/logicpd/omap3som/omap3logic.h
> +++ /dev/null
> @@ -1,236 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * (C) Copyright 2011
> - * Logic Product Development <www.logicpd.com>
> - *
> - * Author:
> - * Peter Barada <peter.barada@logicpd.com>
> - */
> -#ifndef _OMAP3LOGIC_H_
> -#define _OMAP3LOGIC_H_
> -
> -/*
> - * OMAP3 GPMC register settings for CS1 LAN922x
> - */
> -#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
> -#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
> -#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
> -#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
> -#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
> -#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
> -
> -
> -const omap3_sysinfo sysinfo = {
> - DDR_DISCRETE,
> - "Logic DM37x/OMAP35x reference board",
> - "NAND",
> -};
> -
> -/*
> - * IEN - Input Enable
> - * IDIS - Input Disable
> - * PTD - Pull type Down
> - * PTU - Pull type Up
> - * DIS - Pull type selection is inactive
> - * EN - Pull type selection is active
> - * M0 - Mode 0
> - * The commented string gives the final mux configuration for that pin
> - */
> -
> -/*
> - * Routine: set_muxconf_regs
> - * Description: Setting up the configuration Mux registers specific to the
> - * hardware. Many pins need to be moved from protect to primary
> - * mode.
> - */
> -void set_muxconf_regs(void)
> -{
> - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
> - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
> - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
> - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
> - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
> - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
> - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
> - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
> - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
> - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
> - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
> - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
> - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
> - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
> - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
> - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
> - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
> - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
> - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
> - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
> - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
> - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
> - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
> - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
> - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
> - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
> - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
> - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
> - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
> - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
> - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
> - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
> - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
> - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
> - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
> - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
> - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
> - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
> - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
> -
> - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
> - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
> - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
> - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
> - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
> - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
> - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
> - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
> - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
> - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
> - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
> - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
> - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
> - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
> - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
> - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
> - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
> - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
> - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
> - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
> - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
> - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
> - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
> - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
> - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
> - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
> - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
> - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
> - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
> - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
> - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
> - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
> - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
> - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
> - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
> - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
> - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
> - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
> - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
> - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
> - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
> - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
> - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
> - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
> - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
> -
> - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
> - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
> - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
> - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
> - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
> - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
> -
> - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
> - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
> - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
> - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
> -
> - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
> - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
> - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
> - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
> - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
> -
> - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
> - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
> - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
> - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
> - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
> - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
> - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
> - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
> - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
> - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
> - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
> - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
> - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
> - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
> - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
> - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
> - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
> - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
> -
> - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
> - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
> - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
> - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
> - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
> - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
> - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
> - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
> - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
> - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
> - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
> - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
> - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
> - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
> - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
> - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
> - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
> - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
> - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
> - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
> - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
> - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
> - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
> - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
> - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
> - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
> - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
> - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
> - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
> - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
> - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
> - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
> - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
> - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
> - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
> - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
> - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
> - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
> - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
> - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
> - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
> - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
> - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
> - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
> - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
> - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
> - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
> - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
> - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
> - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
> - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
> - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
> - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
> - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
> - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
> - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
> - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
> - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
> - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
> - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
> - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
> - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
> - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
> -}
> -
> -#endif
> diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
> deleted file mode 100644
> index 80219eeacfa..00000000000
> --- a/configs/omap35_logic_defconfig
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_SYS_TEXT_BASE=0x80100000
> -CONFIG_TI_COMMON_CMD_OPTIONS=y
> -# CONFIG_SPL_GPIO_SUPPORT is not set
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_TARGET_OMAP3_LOGIC=y
> -# CONFIG_SPL_OMAP3_ID_NAND is not set
> -CONFIG_SPL=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=2
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_INFO_QUIET=y
> -CONFIG_VERSION_VARIABLE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_MTD_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -CONFIG_SYS_PROMPT="OMAP Logic # "
> -# CONFIG_CMD_IMI is not set
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_SPL_NAND_OFS=0x240000
> -CONFIG_CMD_SPL_WRITE_SIZE=0x20000
> -# CONFIG_CMD_EEPROM is not set
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_NAND=y
> -CONFIG_CMD_NAND_LOCK_UNLOCK=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
> -CONFIG_CMD_UBI=y
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
> -# CONFIG_ENV_IS_IN_FAT is not set
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_SPL_DM=y
> -CONFIG_USB_FUNCTION_FASTBOOT=y
> -CONFIG_FASTBOOT_BUF_ADDR=0x82000000
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_NAND=y
> -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
> -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
> -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
> -CONFIG_SPL_NAND_SIMPLE=y
> -CONFIG_SMC911X=y
> -CONFIG_SMC911X_BASE=0x08000000
> -CONFIG_SMC911X_32_BIT=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_DM_PMIC=y
> -# CONFIG_SPL_PMIC_CHILDREN is not set
> -CONFIG_DM_REGULATOR=y
> -CONFIG_DM_REGULATOR_FIXED=y
> -CONFIG_DM_REGULATOR_GPIO=y
> -CONFIG_SPECIFY_CONSOLE_INDEX=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_OMAP3_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_MUSB_GADGET=y
> -CONFIG_USB_MUSB_OMAP2PLUS=y
> -CONFIG_TWL4030_USB=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="TI"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0451
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
> -CONFIG_USB_ETHER=y
> -CONFIG_BCH=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
> deleted file mode 100644
> index 8a8c7147c3a..00000000000
> --- a/configs/omap35_logic_somlv_defconfig
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_SYS_TEXT_BASE=0x80100000
> -CONFIG_TI_COMMON_CMD_OPTIONS=y
> -# CONFIG_SPL_GPIO_SUPPORT is not set
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_TARGET_OMAP3_LOGIC=y
> -# CONFIG_SPL_OMAP3_ID_NAND is not set
> -CONFIG_SPL=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=2
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_INFO_QUIET=y
> -CONFIG_VERSION_VARIABLE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_MTD_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -CONFIG_SYS_PROMPT="OMAP Logic # "
> -# CONFIG_CMD_IMI is not set
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_SPL_NAND_OFS=0x240000
> -CONFIG_CMD_SPL_WRITE_SIZE=0x20000
> -# CONFIG_CMD_EEPROM is not set
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_NAND=y
> -CONFIG_CMD_NAND_LOCK_UNLOCK=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
> -CONFIG_CMD_UBI=y
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
> -# CONFIG_ENV_IS_IN_FAT is not set
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_SPL_DM=y
> -CONFIG_USB_FUNCTION_FASTBOOT=y
> -CONFIG_FASTBOOT_BUF_ADDR=0x82000000
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_PROTECTION=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_NAND=y
> -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
> -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
> -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
> -CONFIG_SPL_NAND_SIMPLE=y
> -CONFIG_SMC911X=y
> -CONFIG_SMC911X_BASE=0x08000000
> -CONFIG_SMC911X_32_BIT=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_DM_PMIC=y
> -# CONFIG_SPL_PMIC_CHILDREN is not set
> -CONFIG_DM_REGULATOR=y
> -CONFIG_DM_REGULATOR_FIXED=y
> -CONFIG_DM_REGULATOR_GPIO=y
> -CONFIG_SPECIFY_CONSOLE_INDEX=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_OMAP3_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_MUSB_GADGET=y
> -CONFIG_USB_MUSB_OMAP2PLUS=y
> -CONFIG_TWL4030_USB=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="TI"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0451
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
> -CONFIG_USB_ETHER=y
> -CONFIG_BCH=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
> deleted file mode 100644
> index 969387a37cb..00000000000
> --- a/configs/omap3_logic_defconfig
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_SYS_TEXT_BASE=0x80100000
> -CONFIG_TI_COMMON_CMD_OPTIONS=y
> -# CONFIG_SPL_GPIO_SUPPORT is not set
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_TARGET_OMAP3_LOGIC=y
> -# CONFIG_SPL_OMAP3_ID_NAND is not set
> -CONFIG_SPL=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=2
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_INFO_QUIET=y
> -CONFIG_VERSION_VARIABLE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_MTD_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -CONFIG_SYS_PROMPT="OMAP Logic # "
> -# CONFIG_CMD_IMI is not set
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_SPL_NAND_OFS=0x240000
> -CONFIG_CMD_SPL_WRITE_SIZE=0x20000
> -# CONFIG_CMD_EEPROM is not set
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_NAND=y
> -CONFIG_CMD_NAND_LOCK_UNLOCK=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
> -CONFIG_CMD_UBI=y
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
> -# CONFIG_ENV_IS_IN_FAT is not set
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_SPL_DM=y
> -CONFIG_USB_FUNCTION_FASTBOOT=y
> -CONFIG_FASTBOOT_BUF_ADDR=0x82000000
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_MMC_OMAP36XX_PINS=y
> -CONFIG_NAND=y
> -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
> -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
> -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
> -CONFIG_SPL_NAND_SIMPLE=y
> -CONFIG_SMC911X=y
> -CONFIG_SMC911X_BASE=0x08000000
> -CONFIG_SMC911X_32_BIT=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_DM_PMIC=y
> -# CONFIG_SPL_PMIC_CHILDREN is not set
> -CONFIG_DM_REGULATOR=y
> -CONFIG_DM_REGULATOR_FIXED=y
> -CONFIG_DM_REGULATOR_GPIO=y
> -CONFIG_SPECIFY_CONSOLE_INDEX=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_OMAP3_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_MUSB_GADGET=y
> -CONFIG_USB_MUSB_OMAP2PLUS=y
> -CONFIG_TWL4030_USB=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="TI"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0451
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
> -CONFIG_USB_ETHER=y
> -CONFIG_BCH=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
> deleted file mode 100644
> index 396543e56bc..00000000000
> --- a/configs/omap3_logic_somlv_defconfig
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_SYS_TEXT_BASE=0x80100000
> -CONFIG_TI_COMMON_CMD_OPTIONS=y
> -# CONFIG_SPL_GPIO_SUPPORT is not set
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_TARGET_OMAP3_LOGIC=y
> -# CONFIG_SPL_OMAP3_ID_NAND is not set
> -CONFIG_SPL=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=2
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_INFO_QUIET=y
> -CONFIG_VERSION_VARIABLE=y
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_MTD_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -CONFIG_SYS_PROMPT="OMAP Logic # "
> -# CONFIG_CMD_IMI is not set
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_SPL_NAND_OFS=0x240000
> -CONFIG_CMD_SPL_WRITE_SIZE=0x20000
> -# CONFIG_CMD_EEPROM is not set
> -CONFIG_CMD_NAND=y
> -CONFIG_CMD_NAND_LOCK_UNLOCK=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
> -CONFIG_CMD_UBI=y
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
> -# CONFIG_ENV_IS_IN_FAT is not set
> -CONFIG_ENV_IS_IN_NAND=y
> -CONFIG_SPL_DM=y
> -CONFIG_USB_FUNCTION_FASTBOOT=y
> -CONFIG_FASTBOOT_BUF_ADDR=0x82000000
> -CONFIG_DM_I2C=y
> -CONFIG_DM_MMC=y
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_MMC_OMAP36XX_PINS=y
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_FLASH_CFI_MTD=y
> -CONFIG_SYS_FLASH_PROTECTION=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_NAND=y
> -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
> -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
> -CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
> -CONFIG_SPL_NAND_SIMPLE=y
> -CONFIG_SMC911X=y
> -CONFIG_SMC911X_BASE=0x08000000
> -CONFIG_SMC911X_32_BIT=y
> -CONFIG_PINCTRL=y
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_DM_PMIC=y
> -# CONFIG_SPL_PMIC_CHILDREN is not set
> -CONFIG_DM_REGULATOR=y
> -CONFIG_DM_REGULATOR_FIXED=y
> -CONFIG_DM_REGULATOR_GPIO=y
> -CONFIG_SPECIFY_CONSOLE_INDEX=y
> -CONFIG_SPI=y
> -CONFIG_DM_SPI=y
> -CONFIG_OMAP3_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_MUSB_GADGET=y
> -CONFIG_USB_MUSB_OMAP2PLUS=y
> -CONFIG_TWL4030_USB=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="TI"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0451
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
> -CONFIG_USB_ETHER=y
> -CONFIG_BCH=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> deleted file mode 100644
> index fe557f91caa..00000000000
> --- a/include/configs/omap3_logic.h
> +++ /dev/null
> @@ -1,210 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
> - * Peter Barada <peter.barada@logicpd.com>
> - *
> - * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
> - * reference boards.
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/* High Level Configuration Options */
> -
> -#include <configs/ti_omap3_common.h>
> -
> -/*
> - * We are only ever GP parts and will utilize all of the "downloaded image"
> - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
> - * order to allow for BCH8 to fit in.
> - */
> -#undef CONFIG_SPL_TEXT_BASE
> -#define CONFIG_SPL_TEXT_BASE 0x40200000
> -
> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> -#define CONFIG_SETUP_MEMORY_TAGS
> -#define CONFIG_INITRD_TAG
> -#define CONFIG_REVISION_TAG
> -
> -/* Hardware drivers */
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
> -
> -/* Board NAND Info. */
> -#ifdef CONFIG_NAND
> -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
> - /* NAND devices */
> -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> -#define CONFIG_SYS_NAND_PAGE_COUNT 64
> -#define CONFIG_SYS_NAND_PAGE_SIZE 2048
> -#define CONFIG_SYS_NAND_OOBSIZE 64
> -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
> -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
> -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
> - 13, 14, 16, 17, 18, 19, 20, 21, 22, \
> - 23, 24, 25, 26, 27, 28, 30, 31, 32, \
> - 33, 34, 35, 36, 37, 38, 39, 40, 41, \
> - 42, 44, 45, 46, 47, 48, 49, 50, 51, \
> - 52, 53, 54, 55, 56}
> -
> -#define CONFIG_SYS_NAND_ECCSIZE 512
> -#define CONFIG_SYS_NAND_ECCBYTES 13
> -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
> -#define CONFIG_SYS_NAND_MAX_OOBFREE 2
> -#define CONFIG_SYS_NAND_MAX_ECCPOS 56
> -#endif
> -
> -/* Environment information */
> -
> -#define CONFIG_PREBOOT \
> - "setenv preboot;" \
> - "saveenv;"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - DEFAULT_LINUX_BOOT_ENV \
> - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
> - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> - "mmcdev=0\0" \
> - "mmcroot=/dev/mmcblk0p2 rw\0" \
> - "mmcrootfstype=ext4 rootwait\0" \
> - "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
> - "nandrootfstype=ubifs rootwait\0" \
> - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
> - "if run loadbootscript; then " \
> - "run bootscript; " \
> - "else " \
> - "run defaultboot;" \
> - "fi; " \
> - "else run defaultboot; fi\0" \
> - "defaultboot=run mmcramboot\0" \
> - "consoledevice=ttyS0\0" \
> - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
> - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
> - "rotation=0\0" \
> - "vrfb_arg=if itest ${rotation} -ne 0; then " \
> - "setenv bootargs ${bootargs} omapfb.vrfb=y " \
> - "omapfb.rotate=${rotation}; " \
> - "fi\0" \
> - "optargs=ignore_loglevel early_printk no_console_suspend\0" \
> - "common_bootargs=run setconsole; setenv bootargs " \
> - "${bootargs} "\
> - "console=${console} " \
> - "${mtdparts} "\
> - "${optargs}; " \
> - "run vrfb_arg\0" \
> - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
> - "bootscript=echo 'Running bootscript from mmc ...'; " \
> - "source ${loadaddr}\0" \
> - "loadimage=mmc rescan; " \
> - "load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
> - "ramdisksize=64000\0" \
> - "ramdiskimage=rootfs.ext2.gz.uboot\0" \
> - "loadramdisk=mmc rescan; " \
> - "load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \
> - "ramargs=setenv bootargs "\
> - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
> - "mmcargs=setenv bootargs "\
> - "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
> - "nandargs=setenv bootargs "\
> - "root=${nandroot} " \
> - "rootfstype=${nandrootfstype}\0" \
> - "nfsargs=setenv serverip ${tftpserver}; " \
> - "setenv bootargs root=/dev/nfs " \
> - "nfsroot=${nfsrootpath} " \
> - "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \
> - "nfsrootpath=/opt/nfs-exports/omap\0" \
> - "autoload=no\0" \
> - "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> - "loadfdt=mmc rescan; " \
> - "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
> - "mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \
> - "run mmcargs; " \
> - "run common_bootargs; " \
> - "run dump_bootargs; " \
> - "run loadimage; " \
> - "run loadfdt;\0 " \
> - "mmcbootz=setenv bootfile zImage; " \
> - "run mmcbootcommon; "\
> - "bootz ${loadaddr} - ${fdtaddr}\0" \
> - "mmcboot=setenv bootfile uImage; "\
> - "run mmcbootcommon; "\
> - "bootm ${loadaddr} - ${fdtaddr}\0" \
> - "mmcrambootcommon=echo 'Booting kernel from MMC w/ramdisk...'; " \
> - "run ramargs; " \
> - "run common_bootargs; " \
> - "run dump_bootargs; " \
> - "run loadimage; " \
> - "run loadfdt; " \
> - "run loadramdisk\0" \
> - "mmcramboot=setenv bootfile uImage; " \
> - "run mmcrambootcommon; " \
> - "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
> - "mmcrambootz=setenv bootfile zImage; " \
> - "run mmcrambootcommon; " \
> - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
> - "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
> - "run ramargs; " \
> - "run common_bootargs; " \
> - "run dump_bootargs; " \
> - "tftpboot ${loadaddr} ${zimage}; " \
> - "tftpboot ${rdaddr} ${ramdiskimage}; " \
> - "bootm ${loadaddr} ${rdaddr}\0" \
> - "tftpbootz=echo 'Booting kernel NFS rootfs...'; " \
> - "dhcp;" \
> - "run nfsargs;" \
> - "run common_bootargs;" \
> - "run dump_bootargs;" \
> - "tftpboot $loadaddr zImage;" \
> - "bootz $loadaddr\0" \
> - "nandbootcommon=echo 'Booting kernel from NAND...';" \
> - "run nandargs;" \
> - "run common_bootargs;" \
> - "run dump_bootargs;" \
> - "nand read ${loadaddr} kernel;" \
> - "nand read ${fdtaddr} spl-os;\0" \
> - "nandbootz=run nandbootcommon; "\
> - "bootz ${loadaddr} - ${fdtaddr}\0"\
> - "nandboot=run nandbootcommon; "\
> - "bootm ${loadaddr} - ${fdtaddr}\0"\
> -
> -#define CONFIG_BOOTCOMMAND \
> - "run autoboot"
> -
> -/* Miscellaneous configurable options */
> -
> -/* memtest works on */
> -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
> -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> - 0x01F00000) /* 31MB */
> -
> -/* FLASH and environment organization */
> -
> -/* **** PISMO SUPPORT *** */
> -#if defined(CONFIG_CMD_NAND)
> -#define CONFIG_SYS_FLASH_BASE 0x10000000
> -#endif
> -
> -#define CONFIG_SYS_MAX_FLASH_SECT 256
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1
> -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> -#define CONFIG_SYS_FLASH_SIZE 0x4000000
> -
> -/* Monitor at start of flash */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
> -
> -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
> -
> -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
> -#define CONFIG_ENV_OFFSET 0x260000
> -#define CONFIG_ENV_ADDR 0x260000
> -
> -/* Defines for SPL */
> -
> -/* NAND: SPL falcon mode configs */
> -#ifdef CONFIG_SPL_OS_BOOT
> -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
> -#endif
> -
> -#endif /* __CONFIG_H */
> --
> 2.19.1.1215.g8438c0b245-goog
>
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 51/93] arm: Remove omap3_logic_somlv board
2018-11-19 18:07 ` Adam Ford
@ 2018-11-27 0:08 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-27 0:08 UTC (permalink / raw)
To: u-boot
Hi Adam,
On Mon, 19 Nov 2018 at 11:08, Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Nov 19, 2018 at 9:55 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> NAK! This board does support BLK. I think your algorithm is looking
> for CONFIG_DM_BLK when it should be looking for CONFIG_BLK which
> depends on DM.
>
> make omap3_logic_somlv_defconfig
> cat .config | grep BLK
>
>
> CONFIG_BLK=y
> CONFIG_SPL_BLK=y
Yes it is the latter one that changed, as per my other emails. I
changed the default for SPL to n, which fixed some boards but
unfortunately broke others.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 52/93] arm: Remove cm_t335 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (50 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 51/93] arm: Remove omap3_logic_somlv board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 53/93] arm: Remove liteboard board Simon Glass
` (45 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/Kconfig | 1 -
board/compulab/cm_t335/Kconfig | 15 ---
board/compulab/cm_t335/MAINTAINERS | 6 --
board/compulab/cm_t335/Makefile | 8 --
board/compulab/cm_t335/cm_t335.c | 162 -----------------------------
board/compulab/cm_t335/mux.c | 116 ---------------------
board/compulab/cm_t335/spl.c | 113 --------------------
board/compulab/cm_t335/u-boot.lds | 110 --------------------
configs/cm_t335_defconfig | 51 ---------
include/configs/cm_t335.h | 152 ---------------------------
10 files changed, 734 deletions(-)
delete mode 100644 board/compulab/cm_t335/Kconfig
delete mode 100644 board/compulab/cm_t335/MAINTAINERS
delete mode 100644 board/compulab/cm_t335/Makefile
delete mode 100644 board/compulab/cm_t335/cm_t335.c
delete mode 100644 board/compulab/cm_t335/mux.c
delete mode 100644 board/compulab/cm_t335/spl.c
delete mode 100644 board/compulab/cm_t335/u-boot.lds
delete mode 100644 configs/cm_t335_defconfig
delete mode 100644 include/configs/cm_t335.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3b4cb157d4d..271250b82ce 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -183,7 +183,6 @@ source "board/siemens/rut/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
-source "board/compulab/cm_t335/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig
deleted file mode 100644
index 683efde7644..00000000000
--- a/board/compulab/cm_t335/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CM_T335
-
-config SYS_BOARD
- default "cm_t335"
-
-config SYS_VENDOR
- default "compulab"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "cm_t335"
-
-endif
diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS
deleted file mode 100644
index 5fb922c68b0..00000000000
--- a/board/compulab/cm_t335/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM_T335 BOARD
-M: Igor Grinberg <grinberg@compulab.co.il>
-S: Maintained
-F: board/compulab/cm_t335/
-F: include/configs/cm_t335.h
-F: configs/cm_t335_defconfig
diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile
deleted file mode 100644
index 34f67131186..00000000000
--- a/board/compulab/cm_t335/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
-#
-# Author: Ilya Ledvich <ilya@compulab.co.il>
-
-obj-y += cm_t335.o
-obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
deleted file mode 100644
index 95cbb777538..00000000000
--- a/board/compulab/cm_t335/cm_t335.c
+++ /dev/null
@@ -1,162 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board functions for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#include <common.h>
-#include <environment.h>
-#include <errno.h>
-#include <miiphy.h>
-#include <cpsw.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware_am33xx.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-
-#include "../common/eeprom.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- gpmc_init();
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
-#endif
- return 0;
-}
-
-#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slave = {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = &cpsw_slave,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-/* PHY reset GPIO */
-#define GPIO_PHY_RST GPIO_PIN(3, 7)
-
-static void board_phy_init(void)
-{
- gpio_request(GPIO_PHY_RST, "phy_rst");
- gpio_direction_output(GPIO_PHY_RST, 0);
- mdelay(2);
- gpio_set_value(GPIO_PHY_RST, 1);
- mdelay(2);
-}
-
-static void get_efuse_mac_addr(uchar *enetaddr)
-{
- uint32_t mac_hi, mac_lo;
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- enetaddr[0] = mac_hi & 0xFF;
- enetaddr[1] = (mac_hi & 0xFF00) >> 8;
- enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
- enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
- enetaddr[4] = mac_lo & 0xFF;
- enetaddr[5] = (mac_lo & 0xFF00) >> 8;
-}
-
-/*
- * Routine: handle_mac_address
- * Description: prepare MAC address for on-board Ethernet.
- */
-static int handle_mac_address(void)
-{
- uchar enetaddr[6];
- int rv;
-
- rv = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (rv)
- return 0;
-
- rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
- if (rv)
- get_efuse_mac_addr(enetaddr);
-
- if (!is_valid_ethaddr(enetaddr))
- return -1;
-
- return eth_env_set_enetaddr("ethaddr", enetaddr);
-}
-
-#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
-#define AR8051_PHY_DEBUG_DATA_REG 0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
-#define AR8051_RGMII_TX_CLK_DLY 0x100
-
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- const char *devname;
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
- rv = handle_mac_address();
- if (rv)
- printf("No MAC address found!\n");
-
- writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
-
- board_phy_init();
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-
- /*
- * CPSW RGMII Internal Delay Mode is not supported in all PVT
- * operating points. So we must set the TX clock delay feature
- * in the AR8051 PHY. Since we only support a single ethernet
- * device, we only do this for the first instance.
- */
- devname = miiphy_get_current_dev();
-
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
- AR8051_DEBUG_RGMII_CLK_DLY_REG);
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
- AR8051_RGMII_TX_CLK_DLY);
- return n;
-}
-#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c
deleted file mode 100644
index 1c326bd1b6f..00000000000
--- a/board/compulab/cm_t335/mux.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinmux configuration for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
- {-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
- {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
- {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
- /* I2C_DATA */
- {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
- /* I2C_SCLK */
- {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-static struct module_pin_mux eth_phy_rst_pin_mux[] = {
- {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
- {-1},
-};
-
-static struct module_pin_mux status_led_pin_mux[] = {
- {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
- {-1},
-};
-
-void set_uart_mux_conf(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void set_mux_conf_regs(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(rgmii1_pin_mux);
- configure_module_pin_mux(eth_phy_rst_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(nand_pin_mux);
- configure_module_pin_mux(status_led_pin_mux);
-}
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
deleted file mode 100644
index 93f834f5125..00000000000
--- a/board/compulab/cm_t335/spl.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL specific code for Compulab CM-T335 board
- *
- * Board functions for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#include <common.h>
-#include <errno.h>
-
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clocks_am33xx.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware_am33xx.h>
-#include <linux/sizes.h>
-
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41J128MJT125_RD_DQS,
- .datawdsratio0 = MT41J128MJT125_WR_DQS,
- .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
- .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41J128MJT125_RATIO,
- .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J128MJT125_RATIO,
- .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J128MJT125_RATIO,
- .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41J128MJT125_EMIF_SDCFG,
- .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
- .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
- .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
- .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
- .zq_config = MT41J128MJT125_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-const struct dpll_params dpll_ddr = {
-/* M N M2 M3 M4 M5 M6 */
- 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr;
-}
-
-static void probe_sdram_size(long size)
-{
- switch (size) {
- case SZ_512M:
- ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
- break;
- case SZ_256M:
- ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
- break;
- case SZ_128M:
- ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
- break;
- default:
- puts("Failed configuring DRAM, resetting...\n\n");
- reset_cpu(0);
- }
- debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
- config_ddr(303, &ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-
-void sdram_init(void)
-{
- long size = SZ_1G;
-
- do {
- size = size / 2;
- probe_sdram_size(size);
- } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
-
- return;
-}
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
deleted file mode 100644
index b00e466d580..00000000000
--- a/board/compulab/cm_t335/u-boot.lds
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/compulab/cm_t335/built-in.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
deleted file mode 100644
index 134b093e542..00000000000
--- a/configs/cm_t335_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_CM_T335=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_SYS_PROMPT="CM-T335 # "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_EEPROM_LAYOUT=y
-CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:2m(spl),1m(u-boot),1m(u-boot-env),1m(dtb),4m(splash),6m(kernel),-(rootfs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_CMD_PCA953X=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=64
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
deleted file mode 100644
index 740bbd45a08..00000000000
--- a/include/configs/cm_t335.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Config file for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#ifndef __CONFIG_CM_T335_H
-#define __CONFIG_CM_T335_H
-
-#define CONFIG_CM_T335
-
-#include <configs/ti_am335x_common.h>
-
-#undef CONFIG_MAX_RAM_BANK_SIZE
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
-
-#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
-
-/* Clock Defines */
-#define V_OSCK 25000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-
-#ifndef CONFIG_SPL_BUILD
-#define MMCARGS \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
- "mmcrootfstype=ext4\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0"
-
-#define NANDARGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandroot=ubi0:rootfs rw\0" \
- "nandrootfstype=ubifs\0" \
- "nandargs=setenv bootargs console=${console} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype} " \
- "ubi.mtd=${rootfs_name}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nboot ${loadaddr} nand0 900000; " \
- "bootm ${loadaddr}\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=82000000\0" \
- "console=ttyO0,115200n8\0" \
- "rootfs_name=rootfs\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- MMCARGS \
- NANDARGS
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
-#endif /* CONFIG_SPL_BUILD */
-
-#define CONFIG_TIMESTAMP
-#define CONFIG_SYS_AUTOLOAD "no"
-
-/* Serial console configuration */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
-
-/* SPL */
-
-/* Network. */
-#define CONFIG_PHY_ATHEROS
-
-/* NAND support */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-
-#undef CONFIG_SYS_NAND_U_BOOT_OFFS
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-
-#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
-#endif
-
-/* GPIO pin + bank to pin ID mapping */
-#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
-
-/* Status LED */
-/* Status LED polarity is inversed, so init it in the "off" state */
-
-/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * Enable PCA9555@I2C0-0x26.
- * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
- */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
-#endif /* CONFIG_SPL_BUILD */
-
-#endif /* __CONFIG_CM_T335_H */
-
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 53/93] arm: Remove liteboard board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (51 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 52/93] arm: Remove cm_t335 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 54/93] arm: Remove am43xx_evm_usbhost_boot board Simon Glass
` (44 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/grinn/liteboard/Kconfig | 12 --
board/grinn/liteboard/MAINTAINERS | 6 -
board/grinn/liteboard/Makefile | 4 -
board/grinn/liteboard/README | 31 ----
board/grinn/liteboard/board.c | 286 ------------------------------
configs/liteboard_defconfig | 38 ----
include/configs/liteboard.h | 155 ----------------
8 files changed, 533 deletions(-)
delete mode 100644 board/grinn/liteboard/Kconfig
delete mode 100644 board/grinn/liteboard/MAINTAINERS
delete mode 100644 board/grinn/liteboard/Makefile
delete mode 100644 board/grinn/liteboard/README
delete mode 100644 board/grinn/liteboard/board.c
delete mode 100644 configs/liteboard_defconfig
delete mode 100644 include/configs/liteboard.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index c001aaf8cb6..ca7e60ee1cb 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -543,7 +543,6 @@ source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ullevk/Kconfig"
-source "board/grinn/liteboard/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/seco/Kconfig"
diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig
deleted file mode 100644
index e035872c996..00000000000
--- a/board/grinn/liteboard/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_LITEBOARD
-
-config SYS_BOARD
- default "liteboard"
-
-config SYS_VENDOR
- default "grinn"
-
-config SYS_CONFIG_NAME
- default "liteboard"
-
-endif
diff --git a/board/grinn/liteboard/MAINTAINERS b/board/grinn/liteboard/MAINTAINERS
deleted file mode 100644
index b4474f1b3b9..00000000000
--- a/board/grinn/liteboard/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LITEBOARD
-M: Marcin Niestroj <m.niestroj@grinn-global.com>
-S: Maintained
-F: board/grinn/liteboard/
-F: include/configs/liteboard.h
-F: configs/liteboard_defconfig
diff --git a/board/grinn/liteboard/Makefile b/board/grinn/liteboard/Makefile
deleted file mode 100644
index 06aa3eb562b..00000000000
--- a/board/grinn/liteboard/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2016 Grinn
-
-obj-y := board.o
diff --git a/board/grinn/liteboard/README b/board/grinn/liteboard/README
deleted file mode 100644
index bee0394429c..00000000000
--- a/board/grinn/liteboard/README
+++ /dev/null
@@ -1,31 +0,0 @@
-How to use U-Boot on Grinn's liteBoard
---------------------------------------
-
-- Build U-Boot for liteBoard:
-
-$ make mrproper
-$ make liteboard_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the u-boot.img image into the micro SD card:
-
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Jumper settings:
-
-S1: 0 1 0 1 1 1
-
-where 0 means bottom position and 1 means top position (from the
-switch label numbers reference).
-
-- Insert the micro SD card in the board.
-
-- Connect USB cable between liteBoard and the PC for the power and console.
-
-- U-Boot messages should come up.
diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c
deleted file mode 100644
index 18d152a3819..00000000000
--- a/board/grinn/liteboard/board.c
+++ /dev/null
@@ -1,286 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
- * Copyright (C) 2016 Grinn
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/litesom.h>
-#include <asm/arch/mx6ul_pins.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/io.h>
-#include <common.h>
-#include <fsl_esdhc.h>
-#include <linux/sizes.h>
-#include <linux/fb.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <netdev.h>
-#include <spl.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const sd_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /* CD */
- MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-}
-#endif
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
-
-#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
-
-static int mmc_get_env_devno(void)
-{
- u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- int dev_no;
- u32 bootsel;
-
- bootsel = (soc_sbmr & 0x000000FF) >> 6;
-
- /* If not boot from sd/mmc, use default value */
- if (bootsel != 1)
- return CONFIG_SYS_MMC_ENV_DEV;
-
- /* BOOT_CFG2[3] and BOOT_CFG2[4] */
- dev_no = (soc_sbmr & 0x00001800) >> 11;
-
- return dev_no;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(SD_CD_GPIO);
- break;
- case USDHC2_BASE_ADDR:
- ret = 1;
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- /* SD */
- imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
- gpio_direction_input(SD_CD_GPIO);
- sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- ret = fsl_esdhc_initialize(bis, &sd_cfg);
- if (ret) {
- printf("Warning: failed to initialize mmc dev 0 (SD)\n");
- return ret;
- }
-
- return litesom_mmc_init(bis);
-}
-
-static int check_mmc_autodetect(void)
-{
- char *autodetect_str = env_get("mmcautodetect");
-
- if ((autodetect_str != NULL) &&
- (strcmp(autodetect_str, "yes") == 0)) {
- return 1;
- }
-
- return 0;
-}
-
-void board_late_mmc_init(void)
-{
- char cmd[32];
- char mmcblk[32];
- u32 dev_no = mmc_get_env_devno();
-
- if (!check_mmc_autodetect())
- return;
-
- env_set_ulong("mmcdev", dev_no);
-
- /* Set mmcblk env */
- sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
- dev_no);
- env_set("mmcroot", mmcblk);
-
- sprintf(cmd, "mmc dev %d", dev_no);
- run_command(cmd, 0);
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return fecmxc_initialize(bis);
-}
-
-static int setup_fec(void)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
-
- /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
- set gpr1[17]*/
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
- IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
-
- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
- if (ret)
- return ret;
-
- enable_enet_clk(1);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-int board_usb_phy_mode(int port)
-{
- return USB_INIT_HOST;
-}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_FEC_MXC
- setup_fec();
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
- {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_MMC
- board_late_mmc_init();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Grinn liteBoard\n");
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void board_boot_order(u32 *spl_boot_list)
-{
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
- unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
- unsigned port = (reg >> 11) & 0x1;
-
- if (port == 0) {
- spl_boot_list[0] = BOOT_DEVICE_MMC1;
- spl_boot_list[1] = BOOT_DEVICE_MMC2;
- } else {
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
- }
-}
-
-void board_init_f(ulong dummy)
-{
- litesom_init_f();
-}
-#endif
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
deleted file mode 100644
index bdc99b0e0d6..00000000000
--- a/configs/liteboard_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_LITEBOARD=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=1
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
deleted file mode 100644
index a97ccb50b2f..00000000000
--- a/include/configs/liteboard.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- * Copyright (C) 2016 Grinn
- *
- * Configuration settings for the Grinn liteBoard (i.MX6UL).
- */
-#ifndef __LITEBOARD_CONFIG_H
-#define __LITEBOARD_CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-#include <linux/sizes.h>
-#include "mx6_common.h"
-
-/* SPL options */
-#include "imx6_spl.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* MMC Configs */
-#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
-#endif
-
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x83000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_HZ 1000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* FLASH and environment organization */
-#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_ENV_OFFSET (8 * SZ_64K)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_ENET_DEV 0
-
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-
-#define CONFIG_PHY_SMSC
-#endif
-
-#define CONFIG_IMX_THERMAL
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 54/93] arm: Remove am43xx_evm_usbhost_boot board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (52 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 53/93] arm: Remove liteboard board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 55/93] arm: Remove chiliboard board Simon Glass
` (43 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/Kconfig | 1 -
board/ti/am43xx/Kconfig | 17 -
board/ti/am43xx/MAINTAINERS | 11 -
board/ti/am43xx/Makefile | 11 -
board/ti/am43xx/board.c | 957 ----------------------
board/ti/am43xx/board.h | 62 --
board/ti/am43xx/mux.c | 153 ----
configs/am43xx_evm_defconfig | 61 --
configs/am43xx_evm_ethboot_defconfig | 65 --
configs/am43xx_evm_qspiboot_defconfig | 63 --
configs/am43xx_evm_rtconly_defconfig | 62 --
configs/am43xx_evm_usbhost_boot_defconfig | 75 --
configs/am43xx_hs_evm_defconfig | 72 --
include/configs/am43xx_evm.h | 292 -------
14 files changed, 1902 deletions(-)
delete mode 100644 board/ti/am43xx/Kconfig
delete mode 100644 board/ti/am43xx/MAINTAINERS
delete mode 100644 board/ti/am43xx/Makefile
delete mode 100644 board/ti/am43xx/board.c
delete mode 100644 board/ti/am43xx/board.h
delete mode 100644 board/ti/am43xx/mux.c
delete mode 100644 configs/am43xx_evm_defconfig
delete mode 100644 configs/am43xx_evm_ethboot_defconfig
delete mode 100644 configs/am43xx_evm_qspiboot_defconfig
delete mode 100644 configs/am43xx_evm_rtconly_defconfig
delete mode 100644 configs/am43xx_evm_usbhost_boot_defconfig
delete mode 100644 configs/am43xx_hs_evm_defconfig
delete mode 100644 include/configs/am43xx_evm.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 271250b82ce..5caf4bae6f8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -182,7 +182,6 @@ source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
-source "board/ti/am43xx/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig
deleted file mode 100644
index 9cb80cc3f1d..00000000000
--- a/board/ti/am43xx/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if TARGET_AM43XX_EVM
-
-config SYS_BOARD
- default "am43xx"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "am43xx_evm"
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
deleted file mode 100644
index bf098064bda..00000000000
--- a/board/ti/am43xx/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-AM43XX BOARD
-M: Lokesh Vutla <lokeshvutla@ti.com>
-S: Maintained
-F: board/ti/am43xx/
-F: include/configs/am43xx_evm.h
-F: configs/am43xx_evm_defconfig
-F: configs/am43xx_evm_ethboot_defconfig
-F: configs/am43xx_evm_qspiboot_defconfig
-F: configs/am43xx_evm_usbhost_boot_defconfig
-F: configs/am43xx_evm_rtconly_defconfig
-F: configs/am43xx_hs_evm_defconfig
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
deleted file mode 100644
index 60a11d8c04d..00000000000
--- a/board/ti/am43xx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
deleted file mode 100644
index 2a59b060351..00000000000
--- a/board/ti/am43xx/board.c
+++ /dev/null
@@ -1,957 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for TI AM43XX based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <environment.h>
-#include <i2c.h>
-#include <linux/errno.h>
-#include <spl.h>
-#include <usb.h>
-#include <asm/omap_sec_common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-#include "../common/board_detect.h"
-#include "board.h"
-#include <power/pmic.h>
-#include <power/tps65218.h>
-#include <power/tps62362.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <linux/usb/gadget.h>
-#include <dwc3-uboot.h>
-#include <dwc3-omap-uboot.h>
-#include <ti-usb-phy-uboot.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/*
- * Read header information from EEPROM into global structure.
- */
-#ifdef CONFIG_TI_I2C_BOARD_DETECT
-void do_board_detect(void)
-{
- if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS))
- printf("ti_i2c_eeprom_init failed\n");
-}
-#endif
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
- { /* 19.2 MHz */
- {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
- {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
- {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
- {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
- },
- { /* 24 MHz */
- {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
- {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
- {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
- {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
- },
- { /* 25 MHz */
- {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
- {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
- {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
- {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
- },
- { /* 26 MHz */
- {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
- {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
- {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
- {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
- },
-};
-
-const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
- {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
- {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
- {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
- {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
-};
-
-const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
- {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
- {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
- {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
-};
-
-const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
- {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
- {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
- {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
- {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
-};
-
-const struct dpll_params gp_evm_dpll_ddr = {
- 50, 2, 1, -1, 2, -1, -1};
-
-static const struct dpll_params idk_dpll_ddr = {
- 400, 23, 1, -1, 2, -1, -1
-};
-
-static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
- 0x00500050,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40001000,
- 0x08102040
-};
-
-const struct ctrl_ioregs ioregs_lpddr2 = {
- .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
- .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
- .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
- .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
- .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
- .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
- .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
- .emif_sdram_config_ext = 0x1,
-};
-
-const struct emif_regs emif_regs_lpddr2 = {
- .sdram_config = 0x808012BA,
- .ref_ctrl = 0x0000040D,
- .sdram_tim1 = 0xEA86B411,
- .sdram_tim2 = 0x103A094A,
- .sdram_tim3 = 0x0F6BA37F,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_rd_wr_lvl_rmp_win = 0x0,
- .emif_rd_wr_lvl_rmp_ctl = 0x0,
- .emif_rd_wr_lvl_ctl = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E284006,
- .emif_rd_wr_exec_thresh = 0x80000405,
- .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
- .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
- .emif_prio_class_serv_map = 0x80000001,
- .emif_connect_id_serv_1_map = 0x80000094,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x000FFFFF
-};
-
-const struct ctrl_ioregs ioregs_ddr3 = {
- .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
- .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
- .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
- .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
- .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
- .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .emif_sdram_config_ext = 0xc163,
-};
-
-const struct emif_regs ddr3_emif_regs_400Mhz = {
- .sdram_config = 0x638413B2,
- .ref_ctrl = 0x00000C30,
- .sdram_tim1 = 0xEAAAD4DB,
- .sdram_tim2 = 0x266B7FDA,
- .sdram_tim3 = 0x107F8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E004008,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
- .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
- .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
- .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
- .emif_rd_wr_lvl_rmp_win = 0x0,
- .emif_rd_wr_lvl_rmp_ctl = 0x0,
- .emif_rd_wr_lvl_ctl = 0x0,
- .emif_rd_wr_exec_thresh = 0x80000405,
- .emif_prio_class_serv_map = 0x80000001,
- .emif_connect_id_serv_1_map = 0x80000094,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x000FFFFF
-};
-
-/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
-const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
- .sdram_config = 0x638413B2,
- .ref_ctrl = 0x00000C30,
- .sdram_tim1 = 0xEAAAD4DB,
- .sdram_tim2 = 0x266B7FDA,
- .sdram_tim3 = 0x107F8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E004008,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
- .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
- .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
- .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
- .emif_rd_wr_exec_thresh = 0x80000405,
- .emif_prio_class_serv_map = 0x80000001,
- .emif_connect_id_serv_1_map = 0x80000094,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x000FFFFF
-};
-
-/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
-const struct emif_regs ddr3_emif_regs_400Mhz_production = {
- .sdram_config = 0x638413B2,
- .ref_ctrl = 0x00000C30,
- .sdram_tim1 = 0xEAAAD4DB,
- .sdram_tim2 = 0x266B7FDA,
- .sdram_tim3 = 0x107F8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E004008,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
- .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
- .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
- .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
- .emif_rd_wr_exec_thresh = 0x80000405,
- .emif_prio_class_serv_map = 0x80000001,
- .emif_connect_id_serv_1_map = 0x80000094,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x000FFFFF
-};
-
-static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
- .sdram_config = 0x638413b2,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00000c30,
- .sdram_tim1 = 0xeaaad4db,
- .sdram_tim2 = 0x266b7fda,
- .sdram_tim3 = 0x107f8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074be4,
- .temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0e084008,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x89,
- .emif_ddr_ext_phy_ctrl_3 = 0x90,
- .emif_ddr_ext_phy_ctrl_4 = 0x8e,
- .emif_ddr_ext_phy_ctrl_5 = 0x8d,
- .emif_rd_wr_lvl_rmp_win = 0x0,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x80000000,
- .emif_prio_class_serv_map = 0x80000001,
- .emif_connect_id_serv_1_map = 0x80000094,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x000FFFFF
-};
-
-static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
- .sdram_config = 0x61a11b32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00000c30,
- .sdram_tim1 = 0xeaaad4db,
- .sdram_tim2 = 0x266b7fda,
- .sdram_tim3 = 0x107f8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074be4,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1 = 0x00008009,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
- .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
- .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
- .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000405,
- .emif_prio_class_serv_map = 0x00000000,
- .emif_connect_id_serv_1_map = 0x00000000,
- .emif_connect_id_serv_2_map = 0x00000000,
- .emif_cos_config = 0x00ffffff
-};
-
-void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
- if (board_is_eposevm()) {
- *regs = ext_phy_ctrl_const_base_lpddr2;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
- }
-
- return;
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- int ind = get_sys_clk_index();
-
- if (board_is_eposevm())
- return &epos_evm_dpll_ddr[ind];
- else if (board_is_evm() || board_is_sk())
- return &gp_evm_dpll_ddr;
- else if (board_is_idk())
- return &idk_dpll_ddr;
-
- printf(" Board '%s' not supported\n", board_ti_get_name());
- return NULL;
-}
-
-
-/*
- * get_opp_offset:
- * Returns the index for safest OPP of the device to boot.
- * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
- * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
- * This data is read from dev_attribute register which is e-fused.
- * A'1' in bit indicates OPP disabled and not available, a '0' indicates
- * OPP available. Lowest OPP starts with min_off. So returning the
- * bit with rightmost '0'.
- */
-static int get_opp_offset(int max_off, int min_off)
-{
- struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
- int opp, offset, i;
-
- /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
- opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
-
- for (i = max_off; i >= min_off; i--) {
- offset = opp & (1 << i);
- if (!offset)
- return i;
- }
-
- return min_off;
-}
-
-const struct dpll_params *get_dpll_mpu_params(void)
-{
- int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
- u32 ind = get_sys_clk_index();
-
- return &dpll_mpu[ind][opp];
-}
-
-const struct dpll_params *get_dpll_core_params(void)
-{
- int ind = get_sys_clk_index();
-
- return &dpll_core[ind];
-}
-
-const struct dpll_params *get_dpll_per_params(void)
-{
- int ind = get_sys_clk_index();
-
- return &dpll_per[ind];
-}
-
-void scale_vcores_generic(u32 m)
-{
- int mpu_vdd, ddr_volt;
-
- if (i2c_probe(TPS65218_CHIP_PM))
- return;
-
- switch (m) {
- case 1000:
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
- break;
- case 800:
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
- break;
- case 720:
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
- break;
- case 600:
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
- break;
- case 300:
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
- break;
- default:
- puts("Unknown MPU clock, not scaling\n");
- return;
- }
-
- /* Set DCDC1 (CORE) voltage to 1.1V */
- if (tps65218_voltage_update(TPS65218_DCDC1,
- TPS65218_DCDC_VOLT_SEL_1100MV)) {
- printf("%s failure\n", __func__);
- return;
- }
-
- /* Set DCDC2 (MPU) voltage */
- if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
- printf("%s failure\n", __func__);
- return;
- }
-
- if (board_is_eposevm())
- ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
- else
- ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
-
- /* Set DCDC3 (DDR) voltage */
- if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
- printf("%s failure\n", __func__);
- return;
- }
-}
-
-void scale_vcores_idk(u32 m)
-{
- int mpu_vdd;
-
- if (i2c_probe(TPS62362_I2C_ADDR))
- return;
-
- switch (m) {
- case 1000:
- mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
- break;
- case 800:
- mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
- break;
- case 720:
- mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
- break;
- case 600:
- mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
- break;
- case 300:
- mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
- break;
- default:
- puts("Unknown MPU clock, not scaling\n");
- return;
- }
-
- /* Set VDD_MPU voltage */
- if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
- printf("%s failure\n", __func__);
- return;
- }
-}
-
-void gpi2c_init(void)
-{
- /* When needed to be invoked prior to BSS initialization */
- static bool first_time = true;
-
- if (first_time) {
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
- CONFIG_SYS_OMAP24_I2C_SLAVE);
- first_time = false;
- }
-}
-
-void scale_vcores(void)
-{
- const struct dpll_params *mpu_params;
-
- /* Ensure I2C is initialized for PMIC configuration */
- gpi2c_init();
-
- /* Get the frequency */
- mpu_params = get_dpll_mpu_params();
-
- if (board_is_idk())
- scale_vcores_idk(mpu_params->m);
- else
- scale_vcores_generic(mpu_params->m);
-}
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-static void enable_vtt_regulator(void)
-{
- u32 temp;
-
- /* enable module */
- writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
-
- /* enable output for GPIO5_7 */
- writel(GPIO_SETDATAOUT(7),
- AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
- temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
- temp = temp & ~(GPIO_OE_ENABLE(7));
- writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
-}
-
-enum {
- RTC_BOARD_EPOS = 1,
- RTC_BOARD_EVM14,
- RTC_BOARD_EVM12,
- RTC_BOARD_GPEVM,
- RTC_BOARD_SK,
-};
-
-/*
- * In the rtc_only+DRR in self-refresh boot path we have the board type info
- * in the rtc scratch pad register hence we bypass the costly i2c reads to
- * eeprom and directly programthe board name string
- */
-void rtc_only_update_board_type(u32 btype)
-{
- const char *name = "";
- const char *rev = "1.0";
-
- switch (btype) {
- case RTC_BOARD_EPOS:
- name = "AM43EPOS";
- break;
- case RTC_BOARD_EVM14:
- name = "AM43__GP";
- rev = "1.4";
- break;
- case RTC_BOARD_EVM12:
- name = "AM43__GP";
- rev = "1.2";
- break;
- case RTC_BOARD_GPEVM:
- name = "AM43__GP";
- break;
- case RTC_BOARD_SK:
- name = "AM43__SK";
- break;
- }
- ti_i2c_eeprom_am_set(name, rev);
-}
-
-u32 rtc_only_get_board_type(void)
-{
- if (board_is_eposevm())
- return RTC_BOARD_EPOS;
- else if (board_is_evm_14_or_later())
- return RTC_BOARD_EVM14;
- else if (board_is_evm_12_or_later())
- return RTC_BOARD_EVM12;
- else if (board_is_gpevm())
- return RTC_BOARD_GPEVM;
- else if (board_is_sk())
- return RTC_BOARD_SK;
-
- return 0;
-}
-
-void sdram_init(void)
-{
- /*
- * EPOS EVM has 1GB LPDDR2 connected to EMIF.
- * GP EMV has 1GB DDR3 connected to EMIF
- * along with VTT regulator.
- */
- if (board_is_eposevm()) {
- config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
- } else if (board_is_evm_14_or_later()) {
- enable_vtt_regulator();
- config_ddr(0, &ioregs_ddr3, NULL, NULL,
- &ddr3_emif_regs_400Mhz_production, 0);
- } else if (board_is_evm_12_or_later()) {
- enable_vtt_regulator();
- config_ddr(0, &ioregs_ddr3, NULL, NULL,
- &ddr3_emif_regs_400Mhz_beta, 0);
- } else if (board_is_evm()) {
- enable_vtt_regulator();
- config_ddr(0, &ioregs_ddr3, NULL, NULL,
- &ddr3_emif_regs_400Mhz, 0);
- } else if (board_is_sk()) {
- config_ddr(400, &ioregs_ddr3, NULL, NULL,
- &ddr3_sk_emif_regs_400Mhz, 0);
- } else if (board_is_idk()) {
- config_ddr(400, &ioregs_ddr3, NULL, NULL,
- &ddr3_idk_emif_regs_400Mhz, 0);
- }
-}
-#endif
-
-/* setup board specific PMIC */
-int power_init_board(void)
-{
- struct pmic *p;
-
- if (board_is_idk()) {
- power_tps62362_init(I2C_PMIC);
- p = pmic_get("TPS62362");
- if (p && !pmic_probe(p))
- puts("PMIC: TPS62362\n");
- } else {
- power_tps65218_init(I2C_PMIC);
- p = pmic_get("TPS65218_PMIC");
- if (p && !pmic_probe(p))
- puts("PMIC: TPS65218\n");
- }
-
- return 0;
-}
-
-int board_init(void)
-{
- struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
- u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
- modena_init0_bw_integer, modena_init0_watermark_0;
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gpmc_init();
-
- /*
- * Call this to initialize *ctrl again
- */
- hw_data_init();
-
- /* Clear all important bits for DSS errata that may need to be tweaked*/
- mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
- MREQPRIO_0_SAB_INIT0_MASK;
-
- mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
-
- modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
- BW_LIMITER_BW_FRAC_MASK;
-
- modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
- BW_LIMITER_BW_INT_MASK;
-
- modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
- BW_LIMITER_BW_WATERMARK_MASK;
-
- /* Setting MReq Priority of the DSS*/
- mreqprio_0 |= 0x77;
-
- /*
- * Set L3 Fast Configuration Register
- * Limiting bandwith for ARM core to 700 MBPS
- */
- modena_init0_bw_fractional |= 0x10;
- modena_init0_bw_integer |= 0x3;
-
- writel(mreqprio_0, &cdev->mreqprio_0);
- writel(mreqprio_1, &cdev->mreqprio_1);
-
- writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
- writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
- writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- set_board_info_env(NULL);
-
- /*
- * Default FIT boot on HS devices. Non FIT images are not allowed
- * on HS devices.
- */
- if (get_device_type() == HS_DEVICE)
- env_set("boot_fit", "1");
-#endif
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = USB_OTG_SS1_BASE,
- .tx_fifo_resize = false,
- .index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
- .base = (void *)USB_OTG_SS1_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
- .usb2_phy_power = (void *)USB2_PHY1_POWER,
- .index = 0,
-};
-
-static struct dwc3_device usb_otg_ss2 = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = USB_OTG_SS2_BASE,
- .tx_fifo_resize = false,
- .index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
- .base = (void *)USB_OTG_SS2_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
- .usb2_phy_power = (void *)USB2_PHY2_POWER,
- .index = 1,
-};
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif /* CONFIG_USB_DWC3 */
-
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-int board_usb_init(int index, enum usb_init_type init)
-{
- enable_usb_clocks(index);
-#ifdef CONFIG_USB_DWC3
- switch (index) {
- case 0:
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_uboot_init(&usb_otg_ss1);
- }
- break;
- case 1:
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
- }
- break;
- default:
- printf("Invalid Controller Index\n");
- }
-#endif
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-#ifdef CONFIG_USB_DWC3
- switch (index) {
- case 0:
- case 1:
- if (init == USB_INIT_DEVICE) {
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
- }
- break;
- default:
- printf("Invalid Controller Index\n");
- }
-#endif
- disable_usb_clocks(index);
-
- return 0;
-}
-#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-static void cpsw_control(int enabled)
-{
- /* Additional controls can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 16,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int rv;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("ethaddr")) {
- puts("<ethaddr> not set. Validating first E-fuse MAC\n");
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-
- if (board_is_eposevm()) {
- writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[0].phy_addr = 16;
- } else if (board_is_sk()) {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 4;
- cpsw_slaves[1].phy_addr = 5;
- } else if (board_is_idk()) {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 0;
- } else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 0;
- }
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
-
- return rv;
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
-int board_fit_config_name_match(const char *name)
-{
- bool eeprom_read = board_ti_was_eeprom_read();
-
- if (!strcmp(name, "am4372-generic") && !eeprom_read)
- return 0;
- else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
- return 0;
- else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
- return 0;
- else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
- return 0;
- else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
- return 0;
- else
- return -1;
-}
-#endif
-
-#ifdef CONFIG_DTB_RESELECT
-int embedded_dtb_select(void)
-{
- do_board_detect();
- fdtdec_setup();
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
-{
- secure_boot_verify_image(p_image, p_size);
-}
-
-void board_tee_image_process(ulong tee_image, size_t tee_size)
-{
- secure_tee_install((u32)tee_image);
-}
-
-U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
-#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
deleted file mode 100644
index 06b737445d4..00000000000
--- a/board/ti/am43xx/board.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * TI AM437x boards information header
- * Derived from AM335x board.
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include <asm/arch/omap.h>
-
-#define DEV_ATTR_MAX_OFFSET 5
-#define DEV_ATTR_MIN_OFFSET 0
-
-static inline int board_is_eposevm(void)
-{
- return board_ti_is("AM43EPOS");
-}
-
-static inline int board_is_gpevm(void)
-{
- return board_ti_is("AM43__GP");
-}
-
-static inline int board_is_sk(void)
-{
- return board_ti_is("AM43__SK");
-}
-
-static inline int board_is_idk(void)
-{
- return board_ti_is("AM43_IDK");
-}
-
-static inline int board_is_hsevm(void)
-{
- return board_ti_is("AM43XXHS");
-}
-
-static inline int board_is_evm(void)
-{
- return board_is_gpevm() || board_is_hsevm();
-}
-
-static inline int board_is_evm_14_or_later(void)
-{
- return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
-}
-
-static inline int board_is_evm_12_or_later(void)
-{
- return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
-}
-
-void enable_uart0_pin_mux(void);
-void enable_board_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
deleted file mode 100644
index a61987e4c6a..00000000000
--- a/board/ti/am43xx/mux.c
+++ /dev/null
@@ -1,153 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mux.c
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include "../common/board_detect.h"
-#include "board.h"
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
- {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
- {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
- {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
- {-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {-1},
-};
-
-static struct module_pin_mux mdio_pin_mux[] = {
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
- {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux gpio5_7_pin_mux[] = {
- {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
- {-1},
-};
-
-#ifdef CONFIG_NAND
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
- {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
- {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
- {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
- {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
- {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
- {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
- {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
-#endif
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
- {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
- {-1},
-};
-#endif
-
-static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
- {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
- {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
- {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
- {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
- {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
- {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(mdio_pin_mux);
-
- if (board_is_evm()) {
- configure_module_pin_mux(gpio5_7_pin_mux);
- configure_module_pin_mux(rgmii1_pin_mux);
-#if defined(CONFIG_NAND)
- configure_module_pin_mux(nand_pin_mux);
-#endif
- } else if (board_is_sk() || board_is_idk()) {
- configure_module_pin_mux(rgmii1_pin_mux);
-#if defined(CONFIG_NAND)
- printf("Error: NAND flash not present on this board\n");
-#endif
- configure_module_pin_mux(qspi_pin_mux);
- } else if (board_is_eposevm()) {
- configure_module_pin_mux(rmii1_pin_mux);
-#if defined(CONFIG_NAND)
- configure_module_pin_mux(nand_pin_mux);
-#else
- configure_module_pin_mux(qspi_pin_mux);
-#endif
- }
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
deleted file mode 100644
index 7601263be47..00000000000
--- a/configs/am43xx_evm_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_AM43XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x40000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-# CONFIG_BLK is not set
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
deleted file mode 100644
index ea46236bc43..00000000000
--- a/configs/am43xx_evm_ethboot_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_AM43XX=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x40000
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
deleted file mode 100644
index c38fdc19212..00000000000
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x30000000
-CONFIG_AM43XX=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI,QSPI_BOOT"
-CONFIG_QSPI_BOOT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
-CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm"
-CONFIG_DTB_RESELECT=y
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-# CONFIG_BLK is not set
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FAT_WRITE=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
deleted file mode 100644
index 2d54d1aaf0f..00000000000
--- a/configs/am43xx_evm_rtconly_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_AM43XX=y
-CONFIG_SPL_RTC_DDR_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x40000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-# CONFIG_BLK is not set
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
deleted file mode 100644
index 27138335441..00000000000
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_AM43XX=y
-CONFIG_ISW_ENTRY_ADDR=0x40300350
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00100000
-CONFIG_CMD_SPL_WRITE_SIZE=0x40000
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-# CONFIG_BLK is not set
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
deleted file mode 100644
index aaf8d10fecb..00000000000
--- a/configs/am43xx_hs_evm_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_AM43XX=y
-CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
-CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
-CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
-CONFIG_ISW_ENTRY_ADDR=0x403018e0
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT_IMAGE_POST_PROCESS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_ETHER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-# CONFIG_BLK is not set
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
deleted file mode 100644
index 9d0d3424786..00000000000
--- a/include/configs/am43xx_evm.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * am43xx_evm.h
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#ifndef __CONFIG_AM43XX_EVM_H
-#define __CONFIG_AM43XX_EVM_H
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-
-#include <asm/arch/omap.h>
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_CLK 48000000
-#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-/* I2C Configuration */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* Power */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_TPS65218
-#define CONFIG_POWER_TPS62362
-
-/* SPL defines. */
-#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
- (128 << 20))
-
-/* Enabling L2 Cache */
-#define CONFIG_SYS_L2_PL310
-#define CONFIG_SYS_PL310_BASE 0x48242000
-
-/*
- * Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * When building U-Boot such that there is no previous loader
- * we need to call board_early_init_f. This is taken care of in
- * s_init when we have SPL used.
- */
-
-/* Now bring in the rest of the common code. */
-#include <configs/ti_armv7_omap.h>
-
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE (64 << 10)
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-
-/* SPL USB Support */
-
-#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_AM437X_USB2PHY2_HOST
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER)
-#undef CONFIG_USB_DWC3_PHY_OMAP
-#undef CONFIG_USB_DWC3_OMAP
-#undef CONFIG_USB_DWC3
-#undef CONFIG_USB_DWC3_GADGET
-
-#undef CONFIG_USB_GADGET_DOWNLOAD
-#undef CONFIG_USB_GADGET_VBUS_DRAW
-#undef CONFIG_USB_GADGET_MANUFACTURER
-#undef CONFIG_USB_GADGET_VENDOR_NUM
-#undef CONFIG_USB_GADGET_PRODUCT_NUM
-#undef CONFIG_USB_GADGET_DUALSPEED
-#endif
-
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_TIMER
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/* USB Device Firmware Update support */
-#define DFUARGS \
- "dfu_bufsiz=0x10000\0" \
- DFU_ALT_INFO_MMC \
- DFU_ALT_INFO_EMMC \
- DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_QSPI_XIP
-#else
-#define DFUARGS
-#endif
-
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
-#define CONFIG_ENV_OFFSET 0x110000
-#define CONFIG_ENV_OFFSET_REDUND 0x120000
-#endif
-
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_SEL_GPIO 48
-#define CONFIG_SF_DEFAULT_SPEED 48000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_QSPI_QUAD_SUPPORT
-#define CONFIG_TI_EDMA3
-
-#ifndef CONFIG_SPL_BUILD
-#include <environment/ti/dfu.h>
-#include <environment/ti/mmc.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- DEFAULT_MMC_TI_ARGS \
- DEFAULT_FIT_TI_ARGS \
- "fdtfile=undefined\0" \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "console=ttyO0,115200n8\0" \
- "partitions=" \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
- "optargs=\0" \
- "usbroot=/dev/sda2 rw\0" \
- "usbrootfstype=ext4 rootwait\0" \
- "usbdev=0\0" \
- "ramroot=/dev/ram0 rw\0" \
- "ramrootfstype=ext2\0" \
- "usbargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${usbroot} " \
- "rootfstype=${usbrootfstype}\0" \
- "ramargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
- "usbboot=" \
- "setenv devnum ${usbdev}; " \
- "setenv devtype usb; " \
- "usb start ${usbdev}; " \
- "if usb dev ${usbdev}; then " \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt; " \
- "echo Booting from usb ${usbdev}...; " \
- "run usbargs;" \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
- "fi\0" \
- "fi;" \
- "usb stop ${usbdev};\0" \
- "findfdt="\
- "if test $board_name = AM43EPOS; then " \
- "setenv fdtfile am43x-epos-evm.dtb; fi; " \
- "if test $board_name = AM43__GP; then " \
- "setenv fdtfile am437x-gp-evm.dtb; fi; " \
- "if test $board_name = AM43XXHS; then " \
- "setenv fdtfile am437x-gp-evm.dtb; fi; " \
- "if test $board_name = AM43__SK; then " \
- "setenv fdtfile am437x-sk-evm.dtb; fi; " \
- "if test $board_name = AM43_IDK; then " \
- "setenv fdtfile am437x-idk-evm.dtb; fi; " \
- "if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree; fi; \0" \
- NANDARGS \
- NETARGS \
- DFUARGS \
-
-#define CONFIG_BOOTCOMMAND \
- "if test ${boot_fit} -eq 1; then " \
- "run update_to_fit;" \
- "fi;" \
- "run findfdt; " \
- "run envboot;" \
- "run mmcboot;" \
- "run usbboot;" \
- NANDBOOT \
-
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/* CPSW Ethernet */
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 64
-
-/* NAND support */
-#ifdef CONFIG_NAND
-/* NAND: device related configs */
-#define CONFIG_SYS_NAND_PAGE_SIZE 4096
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
- 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
- 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
- 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
- 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
- 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
- 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
- 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
- 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
- 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
- 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
- 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
- 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
- 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
- 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
- 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
- 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
- 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
- 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
- }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
-/* NAND: SPL related configs */
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
-#endif
-#define NANDARGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${fdtaddr} NAND.u-boot-spl-os; " \
- "nand read ${loadaddr} NAND.kernel; " \
- "bootz ${loadaddr} - ${fdtaddr}\0"
-#define NANDBOOT "run nandboot; "
-#else /* !CONFIG_NAND */
-#define NANDARGS
-#define NANDBOOT
-#endif /* CONFIG_NAND */
-
-#if defined(CONFIG_TI_SECURE_DEVICE)
-/* Avoid relocating onto firewalled area at end of DRAM */
-#define CONFIG_PRAM (64 * 1024)
-#endif /* CONFIG_TI_SECURE_DEVICE */
-
-#endif /* __CONFIG_AM43XX_EVM_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 55/93] arm: Remove chiliboard board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (53 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 54/93] arm: Remove am43xx_evm_usbhost_boot board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-21 13:02 ` Marcin Niestrój
2018-11-19 15:53 ` [U-Boot] [PATCH 56/93] arm: Remove am335x_baltos board Simon Glass
` (42 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
arch/arm/include/asm/arch-am33xx/chilisom.h | 14 --
arch/arm/mach-omap2/am33xx/chilisom.c | 184 ------------------
board/grinn/chiliboard/Kconfig | 15 --
board/grinn/chiliboard/MAINTAINERS | 8 -
board/grinn/chiliboard/Makefile | 4 -
board/grinn/chiliboard/README | 31 ---
board/grinn/chiliboard/board.c | 205 --------------------
configs/chiliboard_defconfig | 47 -----
include/configs/chiliboard.h | 180 -----------------
10 files changed, 689 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-am33xx/chilisom.h
delete mode 100644 arch/arm/mach-omap2/am33xx/chilisom.c
delete mode 100644 board/grinn/chiliboard/Kconfig
delete mode 100644 board/grinn/chiliboard/MAINTAINERS
delete mode 100644 board/grinn/chiliboard/Makefile
delete mode 100644 board/grinn/chiliboard/README
delete mode 100644 board/grinn/chiliboard/board.c
delete mode 100644 configs/chiliboard_defconfig
delete mode 100644 include/configs/chiliboard.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4cb32325ed3..b1eeb39d919 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1515,7 +1515,6 @@ source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
-source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h
deleted file mode 100644
index 493be643116..00000000000
--- a/arch/arm/include/asm/arch-am33xx/chilisom.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Grinn
- */
-
-#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
-#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-void chilisom_enable_pin_mux(void);
-void chilisom_spl_board_init(void);
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c
deleted file mode 100644
index 39423051088..00000000000
--- a/arch/arm/mach-omap2/am33xx/chilisom.c
+++ /dev/null
@@ -1,184 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- * Copyright (C) 2017, Grinn - http://grinn-global.com/
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk_synthesizer.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/emif.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <i2c.h>
-#include <power/tps65217.h>
-#include <spl.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-static void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void chilisom_enable_pin_mux(void)
-{
- /* chilisom pin mux */
- configure_module_pin_mux(nand_pin_mux);
-}
-
-static const struct ddr_data ddr3_chilisom_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_chilisom_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .ocp_config = 0x00141414,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-void chilisom_spl_board_init(void)
-{
- int mpu_vdd;
- int usb_cur_lim;
-
- enable_i2c0_pin_mux();
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
-
- if (i2c_probe(TPS65217_CHIP_PM))
- return;
-
- /*
- * Increase USB current limit to 1300mA or 1800mA and set
- * the MPU voltage controller as needed.
- */
- if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
- } else {
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
- }
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_POWER_PATH,
- usb_cur_lim,
- TPS65217_USB_INPUT_CUR_LIMIT_MASK))
- puts("tps65217_reg_write failure\n");
-
- /* Set DCDC3 (CORE) voltage to 1.125V */
- if (tps65217_voltage_update(TPS65217_DEFDCDC3,
- TPS65217_DCDC_VOLT_SEL_1125MV)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set DCDC2 (MPU) voltage */
- if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
-
- /* Set LDO3 to 1.8V and LDO4 to 3.3V */
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS1,
- TPS65217_LDO_VOLTAGE_OUT_1_8,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS2,
- TPS65217_LDO_VOLTAGE_OUT_3_3,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr_chilisom = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr_chilisom;
-}
-
-const struct ctrl_ioregs ioregs_chilisom = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
- config_ddr(400, &ioregs_chilisom,
- &ddr3_chilisom_data,
- &ddr3_chilisom_cmd_ctrl_data,
- &ddr3_chilisom_emif_reg_data, 0);
-}
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/board/grinn/chiliboard/Kconfig b/board/grinn/chiliboard/Kconfig
deleted file mode 100644
index 20056e81a14..00000000000
--- a/board/grinn/chiliboard/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CHILIBOARD
-
-config SYS_BOARD
- default "chiliboard"
-
-config SYS_VENDOR
- default "grinn"
-
-config SYS_CONFIG_NAME
- default "chiliboard"
-
-config SYS_SOC
- default "am33xx"
-
-endif
diff --git a/board/grinn/chiliboard/MAINTAINERS b/board/grinn/chiliboard/MAINTAINERS
deleted file mode 100644
index 5eaccb27915..00000000000
--- a/board/grinn/chiliboard/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-CHILIBOARD
-M: Marcin Niestroj <m.niestroj@grinn-global.com>
-S: Maintained
-F: arch/arm/include/asm/arch-am33xx/chilisom.h
-F: arch/arm/mach-omap2/am33xx/chilisom.c
-F: board/grinn/chiliboard/
-F: include/configs/chiliboard.h
-F: configs/chiliboard_defconfig
diff --git a/board/grinn/chiliboard/Makefile b/board/grinn/chiliboard/Makefile
deleted file mode 100644
index 2c33ccdbf2d..00000000000
--- a/board/grinn/chiliboard/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2017 Grinn
-
-obj-y := board.o
diff --git a/board/grinn/chiliboard/README b/board/grinn/chiliboard/README
deleted file mode 100644
index cea4c1d42e7..00000000000
--- a/board/grinn/chiliboard/README
+++ /dev/null
@@ -1,31 +0,0 @@
-How to use U-Boot on Grinn's chiliBoard
---------------------------------------
-
-- Build U-Boot for chiliBoard:
-
-$ make mrproper
-$ make chiliboard_defconfig
-$ make
-
-This will generate the SPL image called MLO and the u-boot.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=MLO of=/dev/mmcblk0 bs=128k; sync
-
-- Flash the u-boot.img image into the micro SD card:
-
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=128k seek=3; sync
-
-- Jumper settings:
-
-S2: 1 1 1 0 1 0
-
-where 0 means bottom position and 1 means top position (from the
-switch label numbers reference).
-
-- Insert the micro SD card in the board.
-
-- Connect USB cable between chiliBoard and the PC for the power and console.
-
-- U-Boot messages should come up.
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
deleted file mode 100644
index 73a7d8281cc..00000000000
--- a/board/grinn/chiliboard/board.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- * Copyright (C) 2017, Grinn - http://grinn-global.com/
- */
-
-#include <common.h>
-#include <asm/arch/chilisom.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/emif.h>
-#include <asm/io.h>
-#include <cpsw.h>
-#include <environment.h>
-#include <errno.h>
-#include <miiphy.h>
-#include <serial.h>
-#include <spl.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static __maybe_unused struct ctrl_dev *cdev =
- (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {-1},
-};
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
- {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
- {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
- {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
- {-1},
-};
-
-static void enable_board_pin_mux(void)
-{
- chilisom_enable_pin_mux();
-
- /* chiliboard pinmux */
- configure_module_pin_mux(rmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
-}
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_DM_SERIAL
-struct serial_device *default_serial_console(void)
-{
- return &eserial1_device;
-}
-#endif
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-void set_uart_mux_conf(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-void am33xx_spl_board_init(void)
-{
- chilisom_spl_board_init();
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gpmc_init();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#if !defined(CONFIG_SPL_BUILD)
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-#endif
-
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \
- !defined(CONFIG_SPL_BUILD)
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- }
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
-
- writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-
- return n;
-}
-#endif
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
deleted file mode 100644
index b6cde09d6f3..00000000000
--- a/configs/chiliboard_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_CHILIBOARD=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DM_GPIO=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
deleted file mode 100644
index 4372280d2bb..00000000000
--- a/include/configs/chiliboard.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Grinn - http://grinn-global.com/
- */
-
-#ifndef __CONFIG_CHILIBOARD_H
-#define __CONFIG_CHILIBOARD_H
-
-#include <configs/ti_am335x_common.h>
-
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_TIMESTAMP
-#endif
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#define NANDARGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} ${optargs} " \
- "${mtdparts} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${fdt_addr} NAND.u-boot-spl-os; " \
- "nand read ${loadaddr} NAND.kernel; " \
- "bootz ${loadaddr} - ${fdt_addr}\0"
-
-#define CONFIG_BOOTCOMMAND \
- "run mmcboot; " \
- "run nandboot; " \
- "run netboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "fdt_addr=0x87800000\0" \
- "boot_fdt=try\0" \
- "console=ttyO0,115200n8\0" \
- "image=zImage\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "ip_dyn=yes\0" \
- "optargs=\0" \
- "loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
- "${boot_dir}/${image}\0" \
- "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
- "${boot_dir}/${fdt_file}\0" \
- "mmcdev=0\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
- "${mtdparts} " \
- "root=${mmcroot}\0" \
- "mmcloados=run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadimage; then " \
- "run mmcloados;" \
- "fi;" \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
- "${mtdparts} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- NANDARGS
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65217
-
-/* SPL */
-/* Bootcount using the RTC block */
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-/* NAND: SPL related configs */
-
-/* USB configuration */
-#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_TIMER
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#define CONFIG_ENV_SIZE SZ_128K
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#else
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_OFFSET SZ_128K
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#endif
-
-/* Network. */
-#define CONFIG_PHY_SMSC
-
-#endif /* ! __CONFIG_CHILIBOARD_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 55/93] arm: Remove chiliboard board
2018-11-19 15:53 ` [U-Boot] [PATCH 55/93] arm: Remove chiliboard board Simon Glass
@ 2018-11-21 13:02 ` Marcin Niestrój
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Marcin Niestrój @ 2018-11-21 13:02 UTC (permalink / raw)
To: u-boot
Hi Simon, All,
Simon Glass <sjg@chromium.org> writes:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
I just got my hands on chiliboard to start using device-model
drivers. Unfortunately this board does not boot already on master
branch. `git bisect` returned d0851c8937067ad396f2bdafc46d0326bf3317db
("blk: Call part_init() in the post_probe() method") as the first bad
commit. It would not be a big problem if we would switch after 1-2 weeks
anyway, but I am not sure that will happen based on the
discussions. Anyway, it is better you know about that problem. Below you
can find logs from boot process.
After bad commit:
U-Boot SPL 2018.11 (Nov 21 2018 - 13:35:44 +0100)
Trying to boot from MMC1
U-Boot 2018.11 (Nov 21 2018 - 13:35:44 +0100)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 256 MiB
NAND: 256 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment
<ethaddr> not set. Validating first E-fuse MAC
Net: cpsw
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** No partition table - mmc 0 **
** No partition table - mmc 0 **
Booting from nand ...
Before bad commit:
U-Boot SPL 2018.11 (Nov 21 2018 - 13:36:26 +0100)
Trying to boot from MMC1
U-Boot 2018.11 (Nov 21 2018 - 13:36:26 +0100)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 256 MiB
NAND: 256 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment
<ethaddr> not set. Validating first E-fuse MAC
Net: cpsw
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
5892272 bytes read in 370 ms (15.2 MiB/s)
32494 bytes read in 4 ms (7.7 MiB/s)
## Flattened Device Tree blob at 87800000
Booting using the fdt blob at 0x87800000
Loading Device Tree to 8df48000, end 8df52eed ... OK
Starting kernel ...
--
Regards,
Marcin
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 55/93] arm: Remove chiliboard board
2018-11-21 13:02 ` Marcin Niestrój
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Marcin,
On Wed, 21 Nov 2018 at 06:05, Marcin Niestrój
<m.niestroj@grinn-global.com> wrote:
>
> Hi Simon, All,
>
> Simon Glass <sjg@chromium.org> writes:
>
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> I just got my hands on chiliboard to start using device-model
> drivers. Unfortunately this board does not boot already on master
> branch. `git bisect` returned d0851c8937067ad396f2bdafc46d0326bf3317db
> ("blk: Call part_init() in the post_probe() method") as the first bad
> commit. It would not be a big problem if we would switch after 1-2 weeks
> anyway, but I am not sure that will happen based on the
> discussions. Anyway, it is better you know about that problem. Below you
> can find logs from boot process.
>
> After bad commit:
>
> U-Boot SPL 2018.11 (Nov 21 2018 - 13:35:44 +0100)
> Trying to boot from MMC1
>
>
> U-Boot 2018.11 (Nov 21 2018 - 13:35:44 +0100)
>
> CPU : AM335X-GP rev 2.1
> I2C: ready
> DRAM: 256 MiB
> NAND: 256 MiB
> MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
> Loading Environment from MMC... *** Warning - bad CRC, using default environment
>
> <ethaddr> not set. Validating first E-fuse MAC
> Net: cpsw
> Hit any key to stop autoboot: 0
> switch to partitions #0, OK
> mmc0 is current device
> SD/MMC found on device 0
> ** No partition table - mmc 0 **
> ** No partition table - mmc 0 **
> Booting from nand ...
>
> Before bad commit:
>
> U-Boot SPL 2018.11 (Nov 21 2018 - 13:36:26 +0100)
> Trying to boot from MMC1
>
>
> U-Boot 2018.11 (Nov 21 2018 - 13:36:26 +0100)
>
> CPU : AM335X-GP rev 2.1
> I2C: ready
> DRAM: 256 MiB
> NAND: 256 MiB
> MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
> Loading Environment from MMC... *** Warning - bad CRC, using default environment
>
> <ethaddr> not set. Validating first E-fuse MAC
> Net: cpsw
> Hit any key to stop autoboot: 0
> switch to partitions #0, OK
> mmc0 is current device
> SD/MMC found on device 0
> 5892272 bytes read in 370 ms (15.2 MiB/s)
> 32494 bytes read in 4 ms (7.7 MiB/s)
> ## Flattened Device Tree blob at 87800000
> Booting using the fdt blob at 0x87800000
> Loading Device Tree to 8df48000, end 8df52eed ... OK
>
> Starting kernel ...
I am not sure what is wrong. Does it hang in part_init()? It looks
like you don't have a partition table, but it should still be OK to
probe for it.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 56/93] arm: Remove am335x_baltos board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (54 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 55/93] arm: Remove chiliboard board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-20 14:56 ` Yegor Yefremov
2018-11-19 15:53 ` [U-Boot] [PATCH 57/93] arm: Remove kp_imx6q_tpc board Simon Glass
` (41 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/vscom/baltos/Kconfig | 15 -
board/vscom/baltos/MAINTAINERS | 6 -
board/vscom/baltos/Makefile | 11 -
board/vscom/baltos/README | 1 -
board/vscom/baltos/board.c | 493 --------------------------------
board/vscom/baltos/board.h | 34 ---
board/vscom/baltos/mux.c | 125 --------
board/vscom/baltos/u-boot.lds | 128 ---------
configs/am335x_baltos_defconfig | 65 -----
include/configs/baltos.h | 276 ------------------
11 files changed, 1155 deletions(-)
delete mode 100644 board/vscom/baltos/Kconfig
delete mode 100644 board/vscom/baltos/MAINTAINERS
delete mode 100644 board/vscom/baltos/Makefile
delete mode 100644 board/vscom/baltos/README
delete mode 100644 board/vscom/baltos/board.c
delete mode 100644 board/vscom/baltos/board.h
delete mode 100644 board/vscom/baltos/mux.c
delete mode 100644 board/vscom/baltos/u-boot.lds
delete mode 100644 configs/am335x_baltos_defconfig
delete mode 100644 include/configs/baltos.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b1eeb39d919..6cadd96378b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1528,7 +1528,6 @@ source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/ucRobotics/bubblegum_96/Kconfig"
-source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig
deleted file mode 100644
index b721ed19d80..00000000000
--- a/board/vscom/baltos/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_AM335X_BALTOS
-
-config SYS_BOARD
- default "baltos"
-
-config SYS_VENDOR
- default "vscom"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "baltos"
-
-endif
diff --git a/board/vscom/baltos/MAINTAINERS b/board/vscom/baltos/MAINTAINERS
deleted file mode 100644
index e82acfed161..00000000000
--- a/board/vscom/baltos/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BALTOS BOARD
-M: Yegor Yefremov <yegorslists@googlemail.com>
-S: Maintained
-F: board/vscom/baltos/
-F: include/configs/baltos.h
-F: configs/am335x_baltos_defconfig
diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile
deleted file mode 100644
index c34b9b1dd8a..00000000000
--- a/board/vscom/baltos/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/board/vscom/baltos/README b/board/vscom/baltos/README
deleted file mode 100644
index f744ace9972..00000000000
--- a/board/vscom/baltos/README
+++ /dev/null
@@ -1 +0,0 @@
-BSP for VScom OnRISC Balios family devices, like Balios iR 5221.
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
deleted file mode 100644
index df0a2d2b7a6..00000000000
--- a/board/vscom/baltos/board.c
+++ /dev/null
@@ -1,493 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for TI AM335X based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <errno.h>
-#include <linux/libfdt.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <power/tps65217.h>
-#include <power/tps65910.h>
-#include <environment.h>
-#include <watchdog.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
-#define DIP_S1 44
-#define MPCIE_SW 100
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static int baltos_set_console(void)
-{
- int val, i, dips = 0;
- char buf[7];
-
- for (i = 0; i < 4; i++) {
- sprintf(buf, "dip_s%d", i + 1);
-
- if (gpio_request(DIP_S1 + i, buf)) {
- printf("failed to export GPIO %d\n", DIP_S1 + i);
- return 0;
- }
-
- if (gpio_direction_input(DIP_S1 + i)) {
- printf("failed to set GPIO %d direction\n", DIP_S1 + i);
- return 0;
- }
-
- val = gpio_get_value(DIP_S1 + i);
- dips |= val << i;
- }
-
- printf("DIPs: 0x%1x\n", (~dips) & 0xf);
-
- if ((dips & 0xf) == 0xe)
- env_set("console", "ttyUSB0,115200n8");
-
- return 0;
-}
-
-static int read_eeprom(BSP_VS_HWPARAM *header)
-{
- i2c_set_bus_num(1);
-
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally "
- "wrong on the I2C bus.\n");
- return -ENODEV;
- }
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
- sizeof(BSP_VS_HWPARAM))) {
- puts("Could not read the EEPROM; something fundamentally"
- " wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header->Magic != 0xDEADBEEF) {
-
- printf("Incorrect magic number (0x%x) in EEPROM\n",
- header->Magic);
-
- /* fill default values */
- header->SystemId = 211;
- header->MAC1[0] = 0x00;
- header->MAC1[1] = 0x00;
- header->MAC1[2] = 0x00;
- header->MAC1[3] = 0x00;
- header->MAC1[4] = 0x00;
- header->MAC1[5] = 0x01;
-
- header->MAC2[0] = 0x00;
- header->MAC2[1] = 0x00;
- header->MAC2[2] = 0x00;
- header->MAC2[3] = 0x00;
- header->MAC2[4] = 0x00;
- header->MAC2[5] = 0x02;
-
- header->MAC3[0] = 0x00;
- header->MAC3[1] = 0x00;
- header->MAC3[2] = 0x00;
- header->MAC3[3] = 0x00;
- header->MAC3[4] = 0x00;
- header->MAC3[5] = 0x03;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
-
-static const struct ddr_data ddr3_baltos_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_baltos_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return (serial_tstc() && serial_getc() == 'c');
-}
-#endif
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
- 266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
- 303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_baltos = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- int mpu_vdd;
- int sil_rev;
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- /*
- * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
- * MPU frequencies we support we use a CORE voltage of
- * 1.1375V. For MPU voltage we need to switch based on
- * the frequency we are running at.
- */
- i2c_set_bus_num(1);
-
- printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
-
- if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
- puts("i2c: cannot access TPS65910\n");
- return;
- }
-
- /*
- * Depending on MPU clock and PG we will need a different
- * VDD to drive at that speed.
- */
- sil_rev = readl(&cdev->deviceid) >> 28;
- mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
- dpll_mpu_opp100.m);
-
- /* Tell the TPS65910 to use i2c */
- tps65910_set_i2c_control();
-
- /* First update MPU voltage. */
- if (tps65910_voltage_update(MPU, mpu_vdd))
- return;
-
- /* Second, update the CORE voltage. */
- if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
- return;
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-
- writel(0x000010ff, PRM_DEVICE_INST + 4);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- enable_i2c1_pin_mux();
- i2c_set_bus_num(1);
-
- return &dpll_ddr_baltos;
-}
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-const struct ctrl_ioregs ioregs_baltos = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-
- config_ddr(400, &ioregs_baltos,
- &ddr3_baltos_data,
- &ddr3_baltos_cmd_ctrl_data,
- &ddr3_baltos_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
- gpmc_init();
-#endif
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- int node, ret;
- unsigned char mac_addr[6];
- BSP_VS_HWPARAM header;
-
- /* get production data */
- if (read_eeprom(&header))
- return 0;
-
- /* setup MAC1 */
- mac_addr[0] = header.MAC1[0];
- mac_addr[1] = header.MAC1[1];
- mac_addr[2] = header.MAC1[2];
- mac_addr[3] = header.MAC1[3];
- mac_addr[4] = header.MAC1[4];
- mac_addr[5] = header.MAC1[5];
-
-
- node = fdt_path_offset(blob, "/ocp/ethernet/slave at 4a100200");
- if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
- return -ENODEV;
- }
-
- ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
- if (ret) {
- printf("error setting local-mac-address property\n");
- return -ENODEV;
- }
-
- /* setup MAC2 */
- mac_addr[0] = header.MAC2[0];
- mac_addr[1] = header.MAC2[1];
- mac_addr[2] = header.MAC2[2];
- mac_addr[3] = header.MAC2[3];
- mac_addr[4] = header.MAC2[4];
- mac_addr[5] = header.MAC2[5];
-
- node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
- if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
- return -ENODEV;
- }
-
- ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
- if (ret) {
- printf("error setting local-mac-address property\n");
- return -ENODEV;
- }
-
- printf("\nFDT was successfully setup\n");
-
- return 0;
-}
-
-static struct module_pin_mux pcie_sw_pin_mux[] = {
- {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
- {-1},
-};
-
-static struct module_pin_mux dip_pin_mux[] = {
- {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
- {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
- {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
- {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
- {-1},
-};
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- BSP_VS_HWPARAM header;
- char model[4];
-
- /* get production data */
- if (read_eeprom(&header)) {
- strcpy(model, "211");
- } else {
- sprintf(model, "%d", header.SystemId);
- if (header.SystemId == 215) {
- configure_module_pin_mux(dip_pin_mux);
- baltos_set_console();
- }
- }
-
- /* turn power for the mPCIe slot */
- configure_module_pin_mux(pcie_sw_pin_mux);
- if (gpio_request(MPCIE_SW, "mpcie_sw")) {
- printf("failed to export GPIO %d\n", MPCIE_SW);
- return -ENODEV;
- }
- if (gpio_direction_output(MPCIE_SW, 1)) {
- printf("failed to set GPIO %d direction\n", MPCIE_SW);
- return -ENODEV;
- }
-
- env_set("board_name", model);
-#endif
-
- return 0;
-}
-#endif
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 7,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 2,
- .slave_data = cpsw_slaves,
- .active_slave = 1,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
- && defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /*
- * Note here that we're using CPSW1 since that has a 1Gbit PHY while
- * CSPW0 has a 100Mbit PHY.
- *
- * On product, CPSW1 maps to port labeled WAN.
- */
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
-#ifdef CONFIG_DRIVER_TI_CPSW
- writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-#endif
-
- /*
- *
- * CPSW RGMII Internal Delay Mode is not supported in all PVT
- * operating points. So we must set the TX clock delay feature
- * in the AR8051 PHY. Since we only support a single ethernet
- * device in U-Boot, we only do this for the first instance.
- */
-#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
-#define AR8051_PHY_DEBUG_DATA_REG 0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
-#define AR8051_RGMII_TX_CLK_DLY 0x100
- const char *devname;
- devname = miiphy_get_current_dev();
-
- miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
- AR8051_DEBUG_RGMII_CLK_DLY_REG);
- miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
- AR8051_RGMII_TX_CLK_DLY);
-#endif
- return n;
-}
-#endif
diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h
deleted file mode 100644
index 630c9bba73b..00000000000
--- a/board/vscom/baltos/board.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * TI AM335x boards information header
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-typedef struct _BSP_VS_HWPARAM // v1.0
-{
- uint32_t Magic;
- uint32_t HwRev;
- uint32_t SerialNumber;
- char PrdDate[11]; // as a string ie. "01.01.2006"
- uint16_t SystemId;
- uint8_t MAC1[6]; // internal EMAC
- uint8_t MAC2[6]; // SMSC9514
- uint8_t MAC3[6]; // WL1271 WLAN
-} __attribute__ ((packed)) BSP_VS_HWPARAM;
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c1_pin_mux(void);
-void enable_board_pin_mux(void);
-#endif
diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c
deleted file mode 100644
index 94410ae35e6..00000000000
--- a/board/vscom/baltos/mux.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
- {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux gpio0_7_pin_mux[] = {
- {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
- {-1},
-};
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
- {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
- {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
- {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux rgmii2_pin_mux[] = {
- {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c1_pin_mux(void)
-{
- configure_module_pin_mux(i2c1_pin_mux);
-}
-
-void enable_board_pin_mux()
-{
- configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(gpio0_7_pin_mux);
- configure_module_pin_mux(rgmii2_pin_mux);
- configure_module_pin_mux(rmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
-
-#if defined(CONFIG_NAND)
- configure_module_pin_mux(nand_pin_mux);
-#endif
-}
diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds
deleted file mode 100644
index 315ba5b99a7..00000000000
--- a/board/vscom/baltos/u-boot.lds
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/vscom/baltos/built-in.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
deleted file mode 100644
index a61b13b6fc9..00000000000
--- a/configs/am335x_baltos_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_TARGET_AM335X_BALTOS=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_OMAP24_I2C_SPEED=1000
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
deleted file mode 100644
index 006b049d09d..00000000000
--- a/include/configs/baltos.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * am335x_evm.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_BALTOS_H
-#define __CONFIG_BALTOS_H
-
-#include <linux/sizes.h>
-#include <configs/ti_am335x_common.h>
-
-#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-/* Custom script for NOR */
-#define CONFIG_SYS_LDSCRIPT "board/vscom/baltos/u-boot.lds"
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/* FIT support */
-#define CONFIG_SYS_BOOTM_LEN SZ_64M
-
-/* UBI Support */
-
-/* I2C configuration */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
-#endif
-#define NANDARGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "${mtdparts} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "setenv loadaddr 0x84000000; " \
- "ubi part UBI; " \
- "ubifsmount ubi0:kernel; " \
- "ubifsload $loadaddr kernel-fit.itb;" \
- "ubifsumount; " \
- "bootm ${loadaddr}#conf${board_name}; " \
- "if test $? -ne 0; then echo Using default FIT config; " \
- "bootm ${loadaddr}; fi;\0"
-#else
-#define NANDARGS ""
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "boot_fdt=try\0" \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "fdtfile=undefined\0" \
- "console=ttyO0,115200n8\0" \
- "partitions=" \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
- "optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 ro\0" \
- "usbroot=/dev/sda2 ro\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "usbrootfstype=ext4 rootwait\0" \
- "rootpath=/export/rootfs\0" \
- "nfsopts=nolock\0" \
- "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
- "::off\0" \
- "ramroot=/dev/ram0 rw\0" \
- "ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "${mtdparts} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "usbargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "${mtdparts} " \
- "root=${usbroot} " \
- "rootfstype=${usbrootfstype}\0" \
- "spiroot=/dev/mtdblock4 rw\0" \
- "spirootfstype=jffs2\0" \
- "spisrcaddr=0xe0000\0" \
- "spiimgsize=0x362000\0" \
- "spibusno=0\0" \
- "spiargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${spiroot} " \
- "rootfstype=${spirootfstype}\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "usbloadbootenv=load usb 0:1 ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "usbimportbootenv=echo Importing environment from USB ...; " \
- "env import -t $loadaddr $filesize\0" \
- "ramargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "usbloadimage=load usb 0:1 ${loadaddr} kernel-fit.itb\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "usbloados=run usbargs; " \
- "bootm ${loadaddr}#conf${board_name}; " \
- "if test $? -ne 0; then " \
- "echo Using default FIT configuration; " \
- "bootm ${loadaddr}; " \
- "fi;\0" \
- "mmcloados=run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "usbboot=usb reset; " \
- "if usb storage; then " \
- "echo USB drive found;" \
- "if run usbloadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run usbimportbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run usbloadimage; then " \
- "run usbloados;" \
- "fi;" \
- "fi;\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadimage; then " \
- "run mmcloados;" \
- "fi;" \
- "fi;\0" \
- "spiboot=echo Booting from spi ...; " \
- "run spiargs; " \
- "sf probe ${spibusno}:0; " \
- "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
- "bootz ${loadaddr}\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "tftp ${fdtaddr} ${fdtfile}; " \
- "run netargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
- "findfdt=setenv fdtfile am335x-baltos.dtb\0" \
- NANDARGS
- /*DFUARGS*/
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "run usbboot;" \
- "run mmcboot;" \
- "setenv mmcdev 1; " \
- "setenv bootpart 1:2; " \
- "run mmcboot;" \
- "run nandboot;"
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65910
-
-/* SPL */
-#ifndef CONFIG_NOR_BOOT
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#endif
-#endif
-
-/*
- * USB configuration. We enable MUSB support, both for host and for
- * gadget. We set USB0 as peripheral and USB1 as host, based on the
- * board schematic and physical port wired to each. Then for host we
- * add mass storage support and for gadget we add both RNDIS ethernet
- * and DFU.
- */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_HOST
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_OTG
-
-/* Network. */
-#define CONFIG_PHY_SMSC
-#define CONFIG_PHY_ATHEROS
-
-/* NAND support */
-#ifdef CONFIG_NAND
-#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
-#endif
-
-#endif /* ! __CONFIG_BALTOS_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 56/93] arm: Remove am335x_baltos board
2018-11-19 15:53 ` [U-Boot] [PATCH 56/93] arm: Remove am335x_baltos board Simon Glass
@ 2018-11-20 14:56 ` Yegor Yefremov
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Yegor Yefremov @ 2018-11-20 14:56 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Mon, Nov 19, 2018 at 4:55 PM Simon Glass <sjg@chromium.org> wrote:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
I've sent a fix:
https://lists.denx.de/pipermail/u-boot/2018-November/348319.html
Best Regards,
Yegor
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/Kconfig | 1 -
> board/vscom/baltos/Kconfig | 15 -
> board/vscom/baltos/MAINTAINERS | 6 -
> board/vscom/baltos/Makefile | 11 -
> board/vscom/baltos/README | 1 -
> board/vscom/baltos/board.c | 493 --------------------------------
> board/vscom/baltos/board.h | 34 ---
> board/vscom/baltos/mux.c | 125 --------
> board/vscom/baltos/u-boot.lds | 128 ---------
> configs/am335x_baltos_defconfig | 65 -----
> include/configs/baltos.h | 276 ------------------
> 11 files changed, 1155 deletions(-)
> delete mode 100644 board/vscom/baltos/Kconfig
> delete mode 100644 board/vscom/baltos/MAINTAINERS
> delete mode 100644 board/vscom/baltos/Makefile
> delete mode 100644 board/vscom/baltos/README
> delete mode 100644 board/vscom/baltos/board.c
> delete mode 100644 board/vscom/baltos/board.h
> delete mode 100644 board/vscom/baltos/mux.c
> delete mode 100644 board/vscom/baltos/u-boot.lds
> delete mode 100644 configs/am335x_baltos_defconfig
> delete mode 100644 include/configs/baltos.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b1eeb39d919..6cadd96378b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1528,7 +1528,6 @@ source "board/spear/x600/Kconfig"
> source "board/st/stv0991/Kconfig"
> source "board/tcl/sl50/Kconfig"
> source "board/ucRobotics/bubblegum_96/Kconfig"
> -source "board/vscom/baltos/Kconfig"
> source "board/woodburn/Kconfig"
> source "board/xilinx/Kconfig"
> source "board/xilinx/zynq/Kconfig"
> diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig
> deleted file mode 100644
> index b721ed19d80..00000000000
> --- a/board/vscom/baltos/Kconfig
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -if TARGET_AM335X_BALTOS
> -
> -config SYS_BOARD
> - default "baltos"
> -
> -config SYS_VENDOR
> - default "vscom"
> -
> -config SYS_SOC
> - default "am33xx"
> -
> -config SYS_CONFIG_NAME
> - default "baltos"
> -
> -endif
> diff --git a/board/vscom/baltos/MAINTAINERS b/board/vscom/baltos/MAINTAINERS
> deleted file mode 100644
> index e82acfed161..00000000000
> --- a/board/vscom/baltos/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -BALTOS BOARD
> -M: Yegor Yefremov <yegorslists@googlemail.com>
> -S: Maintained
> -F: board/vscom/baltos/
> -F: include/configs/baltos.h
> -F: configs/am335x_baltos_defconfig
> diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile
> deleted file mode 100644
> index c34b9b1dd8a..00000000000
> --- a/board/vscom/baltos/Makefile
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Makefile
> -#
> -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> -
> -ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
> -obj-y := mux.o
> -endif
> -
> -obj-y += board.o
> diff --git a/board/vscom/baltos/README b/board/vscom/baltos/README
> deleted file mode 100644
> index f744ace9972..00000000000
> --- a/board/vscom/baltos/README
> +++ /dev/null
> @@ -1 +0,0 @@
> -BSP for VScom OnRISC Balios family devices, like Balios iR 5221.
> diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
> deleted file mode 100644
> index df0a2d2b7a6..00000000000
> --- a/board/vscom/baltos/board.c
> +++ /dev/null
> @@ -1,493 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * board.c
> - *
> - * Board functions for TI AM335X based boards
> - *
> - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> - */
> -
> -#include <common.h>
> -#include <errno.h>
> -#include <linux/libfdt.h>
> -#include <spl.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/omap.h>
> -#include <asm/arch/ddr_defs.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/gpio.h>
> -#include <asm/arch/mmc_host_def.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/arch/mem.h>
> -#include <asm/arch/mux.h>
> -#include <asm/io.h>
> -#include <asm/emif.h>
> -#include <asm/gpio.h>
> -#include <i2c.h>
> -#include <miiphy.h>
> -#include <cpsw.h>
> -#include <power/tps65217.h>
> -#include <power/tps65910.h>
> -#include <environment.h>
> -#include <watchdog.h>
> -#include "board.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/* GPIO that controls power to DDR on EVM-SK */
> -#define GPIO_DDR_VTT_EN 7
> -#define DIP_S1 44
> -#define MPCIE_SW 100
> -
> -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
> -
> -static int baltos_set_console(void)
> -{
> - int val, i, dips = 0;
> - char buf[7];
> -
> - for (i = 0; i < 4; i++) {
> - sprintf(buf, "dip_s%d", i + 1);
> -
> - if (gpio_request(DIP_S1 + i, buf)) {
> - printf("failed to export GPIO %d\n", DIP_S1 + i);
> - return 0;
> - }
> -
> - if (gpio_direction_input(DIP_S1 + i)) {
> - printf("failed to set GPIO %d direction\n", DIP_S1 + i);
> - return 0;
> - }
> -
> - val = gpio_get_value(DIP_S1 + i);
> - dips |= val << i;
> - }
> -
> - printf("DIPs: 0x%1x\n", (~dips) & 0xf);
> -
> - if ((dips & 0xf) == 0xe)
> - env_set("console", "ttyUSB0,115200n8");
> -
> - return 0;
> -}
> -
> -static int read_eeprom(BSP_VS_HWPARAM *header)
> -{
> - i2c_set_bus_num(1);
> -
> - /* Check if baseboard eeprom is available */
> - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
> - puts("Could not probe the EEPROM; something fundamentally "
> - "wrong on the I2C bus.\n");
> - return -ENODEV;
> - }
> -
> - /* read the eeprom using i2c */
> - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
> - sizeof(BSP_VS_HWPARAM))) {
> - puts("Could not read the EEPROM; something fundamentally"
> - " wrong on the I2C bus.\n");
> - return -EIO;
> - }
> -
> - if (header->Magic != 0xDEADBEEF) {
> -
> - printf("Incorrect magic number (0x%x) in EEPROM\n",
> - header->Magic);
> -
> - /* fill default values */
> - header->SystemId = 211;
> - header->MAC1[0] = 0x00;
> - header->MAC1[1] = 0x00;
> - header->MAC1[2] = 0x00;
> - header->MAC1[3] = 0x00;
> - header->MAC1[4] = 0x00;
> - header->MAC1[5] = 0x01;
> -
> - header->MAC2[0] = 0x00;
> - header->MAC2[1] = 0x00;
> - header->MAC2[2] = 0x00;
> - header->MAC2[3] = 0x00;
> - header->MAC2[4] = 0x00;
> - header->MAC2[5] = 0x02;
> -
> - header->MAC3[0] = 0x00;
> - header->MAC3[1] = 0x00;
> - header->MAC3[2] = 0x00;
> - header->MAC3[3] = 0x00;
> - header->MAC3[4] = 0x00;
> - header->MAC3[5] = 0x03;
> - }
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
> -
> -static const struct ddr_data ddr3_baltos_data = {
> - .datardsratio0 = MT41K256M16HA125E_RD_DQS,
> - .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
> - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
> - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
> -};
> -
> -static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
> - .cmd0csratio = MT41K256M16HA125E_RATIO,
> - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
> -
> - .cmd1csratio = MT41K256M16HA125E_RATIO,
> - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
> -
> - .cmd2csratio = MT41K256M16HA125E_RATIO,
> - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
> -};
> -
> -static struct emif_regs ddr3_baltos_emif_reg_data = {
> - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
> - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
> - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
> - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
> - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
> - .zq_config = MT41K256M16HA125E_ZQ_CFG,
> - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
> -};
> -
> -#ifdef CONFIG_SPL_OS_BOOT
> -int spl_start_uboot(void)
> -{
> - /* break into full u-boot on 'c' */
> - return (serial_tstc() && serial_getc() == 'c');
> -}
> -#endif
> -
> -#define OSC (V_OSCK/1000000)
> -const struct dpll_params dpll_ddr = {
> - 266, OSC-1, 1, -1, -1, -1, -1};
> -const struct dpll_params dpll_ddr_evm_sk = {
> - 303, OSC-1, 1, -1, -1, -1, -1};
> -const struct dpll_params dpll_ddr_baltos = {
> - 400, OSC-1, 1, -1, -1, -1, -1};
> -
> -void am33xx_spl_board_init(void)
> -{
> - int mpu_vdd;
> - int sil_rev;
> -
> - /* Get the frequency */
> - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
> -
> - /*
> - * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
> - * MPU frequencies we support we use a CORE voltage of
> - * 1.1375V. For MPU voltage we need to switch based on
> - * the frequency we are running at.
> - */
> - i2c_set_bus_num(1);
> -
> - printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
> -
> - if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
> - puts("i2c: cannot access TPS65910\n");
> - return;
> - }
> -
> - /*
> - * Depending on MPU clock and PG we will need a different
> - * VDD to drive at that speed.
> - */
> - sil_rev = readl(&cdev->deviceid) >> 28;
> - mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
> - dpll_mpu_opp100.m);
> -
> - /* Tell the TPS65910 to use i2c */
> - tps65910_set_i2c_control();
> -
> - /* First update MPU voltage. */
> - if (tps65910_voltage_update(MPU, mpu_vdd))
> - return;
> -
> - /* Second, update the CORE voltage. */
> - if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
> - return;
> -
> - /* Set CORE Frequencies to OPP100 */
> - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
> -
> - /* Set MPU Frequency to what we detected now that voltages are set */
> - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
> -
> - writel(0x000010ff, PRM_DEVICE_INST + 4);
> -}
> -
> -const struct dpll_params *get_dpll_ddr_params(void)
> -{
> - enable_i2c1_pin_mux();
> - i2c_set_bus_num(1);
> -
> - return &dpll_ddr_baltos;
> -}
> -
> -void set_uart_mux_conf(void)
> -{
> - enable_uart0_pin_mux();
> -}
> -
> -void set_mux_conf_regs(void)
> -{
> - enable_board_pin_mux();
> -}
> -
> -const struct ctrl_ioregs ioregs_baltos = {
> - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
> - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
> - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
> - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
> - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
> -};
> -
> -void sdram_init(void)
> -{
> - gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
> - gpio_direction_output(GPIO_DDR_VTT_EN, 1);
> -
> - config_ddr(400, &ioregs_baltos,
> - &ddr3_baltos_data,
> - &ddr3_baltos_cmd_ctrl_data,
> - &ddr3_baltos_emif_reg_data, 0);
> -}
> -#endif
> -
> -/*
> - * Basic board specific setup. Pinmux has been handled already.
> - */
> -int board_init(void)
> -{
> -#if defined(CONFIG_HW_WATCHDOG)
> - hw_watchdog_init();
> -#endif
> -
> - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> -#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
> - gpmc_init();
> -#endif
> - return 0;
> -}
> -
> -int ft_board_setup(void *blob, bd_t *bd)
> -{
> - int node, ret;
> - unsigned char mac_addr[6];
> - BSP_VS_HWPARAM header;
> -
> - /* get production data */
> - if (read_eeprom(&header))
> - return 0;
> -
> - /* setup MAC1 */
> - mac_addr[0] = header.MAC1[0];
> - mac_addr[1] = header.MAC1[1];
> - mac_addr[2] = header.MAC1[2];
> - mac_addr[3] = header.MAC1[3];
> - mac_addr[4] = header.MAC1[4];
> - mac_addr[5] = header.MAC1[5];
> -
> -
> - node = fdt_path_offset(blob, "/ocp/ethernet/slave at 4a100200");
> - if (node < 0) {
> - printf("no /soc/fman/ethernet path offset\n");
> - return -ENODEV;
> - }
> -
> - ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
> - if (ret) {
> - printf("error setting local-mac-address property\n");
> - return -ENODEV;
> - }
> -
> - /* setup MAC2 */
> - mac_addr[0] = header.MAC2[0];
> - mac_addr[1] = header.MAC2[1];
> - mac_addr[2] = header.MAC2[2];
> - mac_addr[3] = header.MAC2[3];
> - mac_addr[4] = header.MAC2[4];
> - mac_addr[5] = header.MAC2[5];
> -
> - node = fdt_path_offset(blob, "/ocp/ethernet/slave at 4a100300");
> - if (node < 0) {
> - printf("no /soc/fman/ethernet path offset\n");
> - return -ENODEV;
> - }
> -
> - ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
> - if (ret) {
> - printf("error setting local-mac-address property\n");
> - return -ENODEV;
> - }
> -
> - printf("\nFDT was successfully setup\n");
> -
> - return 0;
> -}
> -
> -static struct module_pin_mux pcie_sw_pin_mux[] = {
> - {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
> - {-1},
> -};
> -
> -static struct module_pin_mux dip_pin_mux[] = {
> - {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
> - {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
> - {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
> - {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
> - {-1},
> -};
> -
> -#ifdef CONFIG_BOARD_LATE_INIT
> -int board_late_init(void)
> -{
> -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> - BSP_VS_HWPARAM header;
> - char model[4];
> -
> - /* get production data */
> - if (read_eeprom(&header)) {
> - strcpy(model, "211");
> - } else {
> - sprintf(model, "%d", header.SystemId);
> - if (header.SystemId == 215) {
> - configure_module_pin_mux(dip_pin_mux);
> - baltos_set_console();
> - }
> - }
> -
> - /* turn power for the mPCIe slot */
> - configure_module_pin_mux(pcie_sw_pin_mux);
> - if (gpio_request(MPCIE_SW, "mpcie_sw")) {
> - printf("failed to export GPIO %d\n", MPCIE_SW);
> - return -ENODEV;
> - }
> - if (gpio_direction_output(MPCIE_SW, 1)) {
> - printf("failed to set GPIO %d direction\n", MPCIE_SW);
> - return -ENODEV;
> - }
> -
> - env_set("board_name", model);
> -#endif
> -
> - return 0;
> -}
> -#endif
> -
> -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
> - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
> -static void cpsw_control(int enabled)
> -{
> - /* VTP can be added here */
> -
> - return;
> -}
> -
> -static struct cpsw_slave_data cpsw_slaves[] = {
> - {
> - .slave_reg_ofs = 0x208,
> - .sliver_reg_ofs = 0xd80,
> - .phy_addr = 0,
> - },
> - {
> - .slave_reg_ofs = 0x308,
> - .sliver_reg_ofs = 0xdc0,
> - .phy_addr = 7,
> - },
> -};
> -
> -static struct cpsw_platform_data cpsw_data = {
> - .mdio_base = CPSW_MDIO_BASE,
> - .cpsw_base = CPSW_BASE,
> - .mdio_div = 0xff,
> - .channels = 8,
> - .cpdma_reg_ofs = 0x800,
> - .slaves = 2,
> - .slave_data = cpsw_slaves,
> - .active_slave = 1,
> - .ale_reg_ofs = 0xd00,
> - .ale_entries = 1024,
> - .host_port_reg_ofs = 0x108,
> - .hw_stats_reg_ofs = 0x900,
> - .bd_ram_ofs = 0x2000,
> - .mac_control = (1 << 5),
> - .control = cpsw_control,
> - .host_port_num = 0,
> - .version = CPSW_CTRL_VERSION_2,
> -};
> -#endif
> -
> -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
> - && defined(CONFIG_SPL_BUILD)) || \
> - ((defined(CONFIG_DRIVER_TI_CPSW) || \
> - defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
> - !defined(CONFIG_SPL_BUILD))
> -int board_eth_init(bd_t *bis)
> -{
> - int rv, n = 0;
> - uint8_t mac_addr[6];
> - uint32_t mac_hi, mac_lo;
> -
> - /*
> - * Note here that we're using CPSW1 since that has a 1Gbit PHY while
> - * CSPW0 has a 100Mbit PHY.
> - *
> - * On product, CPSW1 maps to port labeled WAN.
> - */
> -
> - /* try reading mac address from efuse */
> - mac_lo = readl(&cdev->macid1l);
> - mac_hi = readl(&cdev->macid1h);
> - mac_addr[0] = mac_hi & 0xFF;
> - mac_addr[1] = (mac_hi & 0xFF00) >> 8;
> - mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
> - mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
> - mac_addr[4] = mac_lo & 0xFF;
> - mac_addr[5] = (mac_lo & 0xFF00) >> 8;
> -
> -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
> - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
> - if (!env_get("ethaddr")) {
> - printf("<ethaddr> not set. Validating first E-fuse MAC\n");
> -
> - if (is_valid_ethaddr(mac_addr))
> - eth_env_set_enetaddr("ethaddr", mac_addr);
> - }
> -
> -#ifdef CONFIG_DRIVER_TI_CPSW
> - writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
> - cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
> - rv = cpsw_register(&cpsw_data);
> - if (rv < 0)
> - printf("Error %d registering CPSW switch\n", rv);
> - else
> - n += rv;
> -#endif
> -
> - /*
> - *
> - * CPSW RGMII Internal Delay Mode is not supported in all PVT
> - * operating points. So we must set the TX clock delay feature
> - * in the AR8051 PHY. Since we only support a single ethernet
> - * device in U-Boot, we only do this for the first instance.
> - */
> -#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
> -#define AR8051_PHY_DEBUG_DATA_REG 0x1e
> -#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
> -#define AR8051_RGMII_TX_CLK_DLY 0x100
> - const char *devname;
> - devname = miiphy_get_current_dev();
> -
> - miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
> - AR8051_DEBUG_RGMII_CLK_DLY_REG);
> - miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
> - AR8051_RGMII_TX_CLK_DLY);
> -#endif
> - return n;
> -}
> -#endif
> diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h
> deleted file mode 100644
> index 630c9bba73b..00000000000
> --- a/board/vscom/baltos/board.h
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * board.h
> - *
> - * TI AM335x boards information header
> - *
> - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> - */
> -
> -#ifndef _BOARD_H_
> -#define _BOARD_H_
> -
> -typedef struct _BSP_VS_HWPARAM // v1.0
> -{
> - uint32_t Magic;
> - uint32_t HwRev;
> - uint32_t SerialNumber;
> - char PrdDate[11]; // as a string ie. "01.01.2006"
> - uint16_t SystemId;
> - uint8_t MAC1[6]; // internal EMAC
> - uint8_t MAC2[6]; // SMSC9514
> - uint8_t MAC3[6]; // WL1271 WLAN
> -} __attribute__ ((packed)) BSP_VS_HWPARAM;
> -
> -/*
> - * We have three pin mux functions that must exist. We must be able to enable
> - * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
> - * main pinmux function that can be overridden to enable all other pinmux that
> - * is required on the board.
> - */
> -void enable_uart0_pin_mux(void);
> -void enable_i2c1_pin_mux(void);
> -void enable_board_pin_mux(void);
> -#endif
> diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c
> deleted file mode 100644
> index 94410ae35e6..00000000000
> --- a/board/vscom/baltos/mux.c
> +++ /dev/null
> @@ -1,125 +0,0 @@
> -/*
> - * mux.c
> - *
> - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation version 2.
> - *
> - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> - * kind, whether express or implied; without even the implied warranty
> - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#include <common.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/arch/hardware.h>
> -#include <asm/arch/mux.h>
> -#include <asm/io.h>
> -#include <i2c.h>
> -#include "board.h"
> -
> -static struct module_pin_mux uart0_pin_mux[] = {
> - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
> - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
> - {-1},
> -};
> -
> -static struct module_pin_mux mmc0_pin_mux[] = {
> - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
> - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
> - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
> - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
> - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
> - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
> - //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
> - {-1},
> -};
> -
> -static struct module_pin_mux i2c1_pin_mux[] = {
> - {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
> - PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
> - {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
> - PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
> - {-1},
> -};
> -
> -static struct module_pin_mux gpio0_7_pin_mux[] = {
> - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
> - {-1},
> -};
> -
> -static struct module_pin_mux rmii1_pin_mux[] = {
> - {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
> - {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
> - {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
> - {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
> - {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
> - {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
> - {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */
> - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
> - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
> - {-1},
> -};
> -
> -static struct module_pin_mux rgmii2_pin_mux[] = {
> - {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
> - {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
> - {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
> - {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
> - {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
> - {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
> - {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */
> - {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
> - {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
> - {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
> - {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
> - {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
> - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
> - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
> - {-1},
> -};
> -
> -static struct module_pin_mux nand_pin_mux[] = {
> - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
> - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
> - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
> - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
> - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
> - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
> - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
> - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
> - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
> - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
> - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
> - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
> - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
> - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
> - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
> - {-1},
> -};
> -
> -void enable_uart0_pin_mux(void)
> -{
> - configure_module_pin_mux(uart0_pin_mux);
> -}
> -
> -void enable_i2c1_pin_mux(void)
> -{
> - configure_module_pin_mux(i2c1_pin_mux);
> -}
> -
> -void enable_board_pin_mux()
> -{
> - configure_module_pin_mux(i2c1_pin_mux);
> - configure_module_pin_mux(gpio0_7_pin_mux);
> - configure_module_pin_mux(rgmii2_pin_mux);
> - configure_module_pin_mux(rmii1_pin_mux);
> - configure_module_pin_mux(mmc0_pin_mux);
> -
> -#if defined(CONFIG_NAND)
> - configure_module_pin_mux(nand_pin_mux);
> -#endif
> -}
> diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds
> deleted file mode 100644
> index 315ba5b99a7..00000000000
> --- a/board/vscom/baltos/u-boot.lds
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -/*
> - * Copyright (c) 2004-2008 Texas Instruments
> - *
> - * (C) Copyright 2002
> - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> -OUTPUT_ARCH(arm)
> -ENTRY(_start)
> -SECTIONS
> -{
> - . = 0x00000000;
> -
> - . = ALIGN(4);
> - .text :
> - {
> - *(.__image_copy_start)
> - *(.vectors)
> - CPUDIR/start.o (.text*)
> - board/vscom/baltos/built-in.o (.text*)
> - *(.text*)
> - }
> -
> - . = ALIGN(4);
> - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> -
> - . = ALIGN(4);
> - .data : {
> - *(.data*)
> - }
> -
> - . = ALIGN(4);
> -
> - . = .;
> -
> - . = ALIGN(4);
> - .u_boot_list : {
> - KEEP(*(SORT(.u_boot_list*)));
> - }
> -
> - . = ALIGN(4);
> -
> - .image_copy_end :
> - {
> - *(.__image_copy_end)
> - }
> -
> - .rel_dyn_start :
> - {
> - *(.__rel_dyn_start)
> - }
> -
> - .rel.dyn : {
> - *(.rel*)
> - }
> -
> - .rel_dyn_end :
> - {
> - *(.__rel_dyn_end)
> - }
> -
> - .hash : { *(.hash*) }
> -
> - .end :
> - {
> - *(.__end)
> - }
> -
> - _image_binary_end = .;
> -
> - /*
> - * Deprecated: this MMU section is used by pxa at present but
> - * should not be used by new boards/CPUs.
> - */
> - . = ALIGN(4096);
> - .mmutable : {
> - *(.mmutable)
> - }
> -
> -/*
> - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
> - * __bss_base and __bss_limit are for linker only (overlay ordering)
> - */
> -
> - .bss_start __rel_dyn_start (OVERLAY) : {
> - KEEP(*(.__bss_start));
> - __bss_base = .;
> - }
> -
> - .bss __bss_base (OVERLAY) : {
> - *(.bss*)
> - . = ALIGN(4);
> - __bss_limit = .;
> - }
> -
> - .bss_end __bss_limit (OVERLAY) : {
> - KEEP(*(.__bss_end));
> - }
> -
> - .dynsym _image_binary_end : { *(.dynsym) }
> - .dynbss : { *(.dynbss) }
> - .dynstr : { *(.dynstr*) }
> - .dynamic : { *(.dynamic*) }
> - .gnu.hash : { *(.gnu.hash) }
> - .plt : { *(.plt*) }
> - .interp : { *(.interp*) }
> - .gnu : { *(.gnu*) }
> - .ARM.exidx : { *(.ARM.exidx*) }
> -}
> diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
> deleted file mode 100644
> index a61b13b6fc9..00000000000
> --- a/configs/am335x_baltos_defconfig
> +++ /dev/null
> @@ -1,65 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_AM33XX=y
> -CONFIG_TARGET_AM335X_BALTOS=y
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_FAT_SUPPORT=y
> -CONFIG_SPL_LIBDISK_SUPPORT=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_FIT_VERBOSE=y
> -CONFIG_OF_BOARD_SETUP=y
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_INFO_QUIET=y
> -CONFIG_VERSION_VARIABLE=y
> -CONFIG_ARCH_MISC_INIT=y
> -CONFIG_SPL_EXT_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_MTD_SUPPORT=y
> -CONFIG_SPL_POWER_SUPPORT=y
> -CONFIG_SPL_WATCHDOG_SUPPORT=y
> -CONFIG_SPL_YMODEM_SUPPORT=y
> -CONFIG_CMD_ASKENV=y
> -CONFIG_CMD_EEPROM=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_GPT=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_NAND=y
> -CONFIG_CMD_SPI=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_MTDPARTS=y
> -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
> -CONFIG_CMD_UBI=y
> -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_BOOTCOUNT_LIMIT=y
> -CONFIG_SYS_OMAP24_I2C_SPEED=1000
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_NAND=y
> -CONFIG_PHY_ADDR_ENABLE=y
> -CONFIG_DRIVER_TI_CPSW=y
> -CONFIG_MII=y
> -CONFIG_SPI=y
> -CONFIG_OMAP3_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_MUSB_HOST=y
> -CONFIG_USB_MUSB_GADGET=y
> -CONFIG_USB_MUSB_DSPS=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0403
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
> -CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_USB_ETHER=y
> -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
> -CONFIG_FAT_WRITE=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/baltos.h b/include/configs/baltos.h
> deleted file mode 100644
> index 006b049d09d..00000000000
> --- a/include/configs/baltos.h
> +++ /dev/null
> @@ -1,276 +0,0 @@
> -/*
> - * am335x_evm.h
> - *
> - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation version 2.
> - *
> - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> - * kind, whether express or implied; without even the implied warranty
> - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef __CONFIG_BALTOS_H
> -#define __CONFIG_BALTOS_H
> -
> -#include <linux/sizes.h>
> -#include <configs/ti_am335x_common.h>
> -
> -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
> -
> -/* Clock Defines */
> -#define V_OSCK 24000000 /* Clock output from T2 */
> -#define V_SCLK (V_OSCK)
> -
> -/* Custom script for NOR */
> -#define CONFIG_SYS_LDSCRIPT "board/vscom/baltos/u-boot.lds"
> -
> -/* Always 128 KiB env size */
> -#define CONFIG_ENV_SIZE (128 << 10)
> -
> -/* FIT support */
> -#define CONFIG_SYS_BOOTM_LEN SZ_64M
> -
> -/* UBI Support */
> -
> -/* I2C configuration */
> -
> -#ifdef CONFIG_NAND
> -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000
> -#ifdef CONFIG_SPL_OS_BOOT
> -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
> -#endif
> -#define NANDARGS \
> - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
> - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
> - "nandargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "${mtdparts} " \
> - "root=${nandroot} " \
> - "rootfstype=${nandrootfstype}\0" \
> - "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \
> - "nandrootfstype=ubifs rootwait=1\0" \
> - "nandboot=echo Booting from nand ...; " \
> - "run nandargs; " \
> - "setenv loadaddr 0x84000000; " \
> - "ubi part UBI; " \
> - "ubifsmount ubi0:kernel; " \
> - "ubifsload $loadaddr kernel-fit.itb;" \
> - "ubifsumount; " \
> - "bootm ${loadaddr}#conf${board_name}; " \
> - "if test $? -ne 0; then echo Using default FIT config; " \
> - "bootm ${loadaddr}; fi;\0"
> -#else
> -#define NANDARGS ""
> -#endif
> -
> -#ifndef CONFIG_SPL_BUILD
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - DEFAULT_LINUX_BOOT_ENV \
> - "boot_fdt=try\0" \
> - "bootpart=0:2\0" \
> - "bootdir=/boot\0" \
> - "bootfile=zImage\0" \
> - "fdtfile=undefined\0" \
> - "console=ttyO0,115200n8\0" \
> - "partitions=" \
> - "uuid_disk=${uuid_gpt_disk};" \
> - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
> - "optargs=\0" \
> - "mmcdev=0\0" \
> - "mmcroot=/dev/mmcblk0p2 ro\0" \
> - "usbroot=/dev/sda2 ro\0" \
> - "mmcrootfstype=ext4 rootwait\0" \
> - "usbrootfstype=ext4 rootwait\0" \
> - "rootpath=/export/rootfs\0" \
> - "nfsopts=nolock\0" \
> - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
> - "::off\0" \
> - "ramroot=/dev/ram0 rw\0" \
> - "ramrootfstype=ext2\0" \
> - "mmcargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "${mtdparts} " \
> - "root=${mmcroot} " \
> - "rootfstype=${mmcrootfstype}\0" \
> - "usbargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "${mtdparts} " \
> - "root=${usbroot} " \
> - "rootfstype=${usbrootfstype}\0" \
> - "spiroot=/dev/mtdblock4 rw\0" \
> - "spirootfstype=jffs2\0" \
> - "spisrcaddr=0xe0000\0" \
> - "spiimgsize=0x362000\0" \
> - "spibusno=0\0" \
> - "spiargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "root=${spiroot} " \
> - "rootfstype=${spirootfstype}\0" \
> - "netargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "root=/dev/nfs " \
> - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
> - "ip=dhcp\0" \
> - "bootenv=uEnv.txt\0" \
> - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
> - "usbloadbootenv=load usb 0:1 ${loadaddr} ${bootenv}\0" \
> - "importbootenv=echo Importing environment from mmc ...; " \
> - "env import -t $loadaddr $filesize\0" \
> - "usbimportbootenv=echo Importing environment from USB ...; " \
> - "env import -t $loadaddr $filesize\0" \
> - "ramargs=setenv bootargs console=${console} " \
> - "${optargs} " \
> - "root=${ramroot} " \
> - "rootfstype=${ramrootfstype}\0" \
> - "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
> - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
> - "usbloadimage=load usb 0:1 ${loadaddr} kernel-fit.itb\0" \
> - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
> - "usbloados=run usbargs; " \
> - "bootm ${loadaddr}#conf${board_name}; " \
> - "if test $? -ne 0; then " \
> - "echo Using default FIT configuration; " \
> - "bootm ${loadaddr}; " \
> - "fi;\0" \
> - "mmcloados=run mmcargs; " \
> - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> - "if run loadfdt; then " \
> - "bootz ${loadaddr} - ${fdtaddr}; " \
> - "else " \
> - "if test ${boot_fdt} = try; then " \
> - "bootz; " \
> - "else " \
> - "echo WARN: Cannot load the DT; " \
> - "fi; " \
> - "fi; " \
> - "else " \
> - "bootz; " \
> - "fi;\0" \
> - "usbboot=usb reset; " \
> - "if usb storage; then " \
> - "echo USB drive found;" \
> - "if run usbloadbootenv; then " \
> - "echo Loaded environment from ${bootenv};" \
> - "run usbimportbootenv;" \
> - "fi;" \
> - "if test -n $uenvcmd; then " \
> - "echo Running uenvcmd ...;" \
> - "run uenvcmd;" \
> - "fi;" \
> - "if run usbloadimage; then " \
> - "run usbloados;" \
> - "fi;" \
> - "fi;\0" \
> - "mmcboot=mmc dev ${mmcdev}; " \
> - "if mmc rescan; then " \
> - "echo SD/MMC found on device ${mmcdev};" \
> - "if run loadbootenv; then " \
> - "echo Loaded environment from ${bootenv};" \
> - "run importbootenv;" \
> - "fi;" \
> - "if test -n $uenvcmd; then " \
> - "echo Running uenvcmd ...;" \
> - "run uenvcmd;" \
> - "fi;" \
> - "if run loadimage; then " \
> - "run mmcloados;" \
> - "fi;" \
> - "fi;\0" \
> - "spiboot=echo Booting from spi ...; " \
> - "run spiargs; " \
> - "sf probe ${spibusno}:0; " \
> - "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
> - "bootz ${loadaddr}\0" \
> - "netboot=echo Booting from network ...; " \
> - "setenv autoload no; " \
> - "dhcp; " \
> - "tftp ${loadaddr} ${bootfile}; " \
> - "tftp ${fdtaddr} ${fdtfile}; " \
> - "run netargs; " \
> - "bootz ${loadaddr} - ${fdtaddr}\0" \
> - "ramboot=echo Booting from ramdisk ...; " \
> - "run ramargs; " \
> - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
> - "findfdt=setenv fdtfile am335x-baltos.dtb\0" \
> - NANDARGS
> - /*DFUARGS*/
> -#endif
> -
> -#define CONFIG_BOOTCOMMAND \
> - "run findfdt; " \
> - "run usbboot;" \
> - "run mmcboot;" \
> - "setenv mmcdev 1; " \
> - "setenv bootpart 1:2; " \
> - "run mmcboot;" \
> - "run nandboot;"
> -
> -/* NS16550 Configuration */
> -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
> -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
> -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
> -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
> -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
> -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
> -
> -#define CONFIG_ENV_EEPROM_IS_ON_I2C
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
> -
> -/* PMIC support */
> -#define CONFIG_POWER_TPS65910
> -
> -/* SPL */
> -#ifndef CONFIG_NOR_BOOT
> -
> -#ifdef CONFIG_NAND
> -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
> - CONFIG_SYS_NAND_PAGE_SIZE)
> -#define CONFIG_SYS_NAND_PAGE_SIZE 2048
> -#define CONFIG_SYS_NAND_OOBSIZE 64
> -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
> -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
> -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
> - 10, 11, 12, 13, 14, 15, 16, 17, \
> - 18, 19, 20, 21, 22, 23, 24, 25, \
> - 26, 27, 28, 29, 30, 31, 32, 33, \
> - 34, 35, 36, 37, 38, 39, 40, 41, \
> - 42, 43, 44, 45, 46, 47, 48, 49, \
> - 50, 51, 52, 53, 54, 55, 56, 57, }
> -
> -#define CONFIG_SYS_NAND_ECCSIZE 512
> -#define CONFIG_SYS_NAND_ECCBYTES 14
> -#define CONFIG_SYS_NAND_ONFI_DETECTION
> -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
> -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
> -#endif
> -#endif
> -
> -/*
> - * USB configuration. We enable MUSB support, both for host and for
> - * gadget. We set USB0 as peripheral and USB1 as host, based on the
> - * board schematic and physical port wired to each. Then for host we
> - * add mass storage support and for gadget we add both RNDIS ethernet
> - * and DFU.
> - */
> -#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
> -#define CONFIG_AM335X_USB0
> -#define CONFIG_AM335X_USB0_MODE MUSB_HOST
> -#define CONFIG_AM335X_USB1
> -#define CONFIG_AM335X_USB1_MODE MUSB_OTG
> -
> -/* Network. */
> -#define CONFIG_PHY_SMSC
> -#define CONFIG_PHY_ATHEROS
> -
> -/* NAND support */
> -#ifdef CONFIG_NAND
> -#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
> -#endif
> -
> -#endif /* ! __CONFIG_BALTOS_H */
> --
> 2.19.1.1215.g8438c0b245-goog
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 57/93] arm: Remove kp_imx6q_tpc board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (55 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 56/93] arm: Remove am335x_baltos board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 58/93] arm: Remove lsxhl board Simon Glass
` (40 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/k+p/kp_imx6q_tpc/Kconfig | 12 -
board/k+p/kp_imx6q_tpc/MAINTAINERS | 6 -
board/k+p/kp_imx6q_tpc/Makefile | 9 -
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 301 -------------------
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 337 ----------------------
configs/kp_imx6q_tpc_defconfig | 44 ---
include/configs/kp_imx6q_tpc.h | 134 ---------
8 files changed, 844 deletions(-)
delete mode 100644 board/k+p/kp_imx6q_tpc/Kconfig
delete mode 100644 board/k+p/kp_imx6q_tpc/MAINTAINERS
delete mode 100644 board/k+p/kp_imx6q_tpc/Makefile
delete mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
delete mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
delete mode 100644 configs/kp_imx6q_tpc_defconfig
delete mode 100644 include/configs/kp_imx6q_tpc.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ca7e60ee1cb..71e57690d6e 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -550,7 +550,6 @@ source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
-source "board/k+p/kp_imx6q_tpc/Kconfig"
source "board/udoo/Kconfig"
source "board/warp/Kconfig"
diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig
deleted file mode 100644
index 62e34978ecd..00000000000
--- a/board/k+p/kp_imx6q_tpc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KP_IMX6Q_TPC
-
-config SYS_BOARD
- default "kp_imx6q_tpc"
-
-config SYS_VENDOR
- default "k+p"
-
-config SYS_CONFIG_NAME
- default "kp_imx6q_tpc"
-
-endif
diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS
deleted file mode 100644
index 6c4c8dd28e3..00000000000
--- a/board/k+p/kp_imx6q_tpc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KP_IMX6Q_TPC BOARD
-M: Lukasz Majewski <lukma@denx.de>
-S: Maintained
-F: board/k+p/kp_imx6q_tpc/
-F: include/configs/kp_imx6q_tpc.h
-F: configs/kp_imx6q_tpc_defconfig
diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile
deleted file mode 100644
index 6551b2bfa2d..00000000000
--- a/board/k+p/kp_imx6q_tpc/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
-
-ifdef CONFIG_SPL_BUILD
-obj-y := kp_imx6q_tpc_spl.o
-else
-obj-y := kp_imx6q_tpc.o
-endif
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
deleted file mode 100644
index ace986fa050..00000000000
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
+++ /dev/null
@@ -1,301 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * K+P iMX6Q KP_IMX6Q_TPC board configuration
- *
- * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <errno.h>
-#include <fsl_esdhc.h>
-#include <fuse.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ENET_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8031 PHY Reset */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eth_phy_reset(void)
-{
- /* Reset AR8031 PHY */
- gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
- mdelay(10);
- gpio_set_value(IMX_GPIO_NR(1, 25), 1);
- udelay(100);
-}
-
-static int setup_fec_clock(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* set gpr1[21] to select anatop clock */
- clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
-
- return enable_fec_anatop_clock(0, ENET_50MHZ);
-}
-
-int board_eth_init(bd_t *bis)
-{
- SETUP_IOMUX_PADS(enet_pads);
- setup_fec_clock();
- eth_phy_reset();
-
- return cpu_eth_init(bis);
-}
-
-static int ar8031_phy_fixup(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 output a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- ar8031_phy_fixup(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
- { USDHC2_BASE_ADDR },
- { USDHC4_BASE_ADDR },
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- return !gpio_get_value(USDHC2_CD_GPIO);
- case USDHC4_BASE_ADDR:
- return 1; /* eMMC/uSDHC4 is always present */
- }
-
- return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 micro SD
- * mmc2 eMMC
- */
- gpio_direction_input(USDHC2_CD_GPIO);
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
-{
- /*
- * Set daisy chain for otg_pin_id on MX6Q.
- * For MX6DL, this bit is reserved.
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return USB_INIT_DEVICE;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
-
- return 0;
-}
-
-int board_init(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* Enable eim_slow clocks */
- setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
-
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
- env_set("boardname", "kp-tpc");
- env_set("boardsoc", "imx6q");
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
- return 0;
-}
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
deleted file mode 100644
index d89e1120a57..00000000000
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ /dev/null
@@ -1,337 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * K+P iMX6Q KP_IMX6Q_TPC board configuration
- *
- * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <fuse.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <spl.h>
-
-#define UART_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL \
- (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-/* onboard microSD */
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-/* eMMC */
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-/* SD */
-static void setup_iomux_sd(void)
-{
- SETUP_IOMUX_PADS(usdhc2_pads);
- SETUP_IOMUX_PADS(usdhc4_pads);
-}
-
-/* UART */
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-/* USB */
-static iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_usb(void)
-{
- SETUP_IOMUX_PADS(usb_pads);
-}
-
-/* DDR3 */
-static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00000030,
- .dram_sdclk_1 = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_reset = 0x00000030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00000030,
- .dram_sdodt1 = 0x00000030,
-
- .dram_sdqs0 = 0x00000018,
- .dram_sdqs1 = 0x00000018,
- .dram_sdqs2 = 0x00000018,
- .dram_sdqs3 = 0x00000018,
- .dram_sdqs4 = 0x00000018,
- .dram_sdqs5 = 0x00000018,
- .dram_sdqs6 = 0x00000018,
- .dram_sdqs7 = 0x00000018,
-
- .dram_dqm0 = 0x00000018,
- .dram_dqm1 = 0x00000018,
- .dram_dqm2 = 0x00000018,
- .dram_dqm3 = 0x00000018,
- .dram_dqm4 = 0x00000018,
- .dram_dqm5 = 0x00000018,
- .dram_dqm6 = 0x00000018,
- .dram_dqm7 = 0x00000018,
-};
-
-static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000018,
- .grp_b1ds = 0x00000018,
- .grp_b2ds = 0x00000018,
- .grp_b3ds = 0x00000018,
- .grp_b4ds = 0x00000018,
- .grp_b5ds = 0x00000018,
- .grp_b6ds = 0x00000018,
- .grp_b7ds = 0x00000018,
-};
-
-static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001F001F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x001F001F,
- .p1_mpwldectrl1 = 0x001F001F,
- .p0_mpdgctrl0 = 0x43270338,
- .p0_mpdgctrl1 = 0x03200314,
- .p1_mpdgctrl0 = 0x431A032F,
- .p1_mpdgctrl1 = 0x03200263,
- .p0_mprddlctl = 0x4B434748,
- .p1_mprddlctl = 0x4445404C,
- .p0_mpwrdlctl = 0x38444542,
- .p1_mpwrdlctl = 0x4935493A,
-};
-
-/* MT41K256M16 (4Gb density) */
-static const struct mx6_ddr3_cfg mt41k256m16 = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-#ifdef CONFIG_MX6_DDRCAL
-static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
-{
- struct mx6_mmdc_calibration calibration = {0};
-
- mmdc_read_calibration(sysinfo, &calibration);
-
- debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
- debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
- debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
- debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
- debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
- debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
- debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
- debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
- debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
- debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
- debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
- debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
-}
-
-static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
-{
- int ret;
-
- /* Perform DDR DRAM calibration */
- udelay(100);
- ret = mmdc_do_write_level_calibration(sysinfo);
- if (ret) {
- printf("DDR: Write level calibration error [%d]\n", ret);
- return;
- }
-
- ret = mmdc_do_dqs_calibration(sysinfo);
- if (ret) {
- printf("DDR: DQS calibration error [%d]\n", ret);
- return;
- }
-
- spl_dram_print_cal(sysinfo);
-}
-#endif /* CONFIG_MX6_DDRCAL */
-
-static void spl_dram_init(void)
-{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .pd_fast_exit = 1, /* enable precharge power-down fast exit */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
-
-#ifdef CONFIG_MX6_DDRCAL
- spl_dram_perform_cal(&sysinfo);
-#endif
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[] = {
- {USDHC2_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bd)
-{
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned int reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x3:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- }
-
- return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* setup GP timer */
- timer_init();
-
- setup_iomux_sd();
- setup_iomux_uart();
- setup_iomux_usb();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
deleted file mode 100644
index 5ebbe1dc7c6..00000000000
--- a/configs/kp_imx6q_tpc_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_KP_IMX6Q_TPC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR="."
-# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
deleted file mode 100644
index b6b27ee1d5e..00000000000
--- a/include/configs/kp_imx6q_tpc.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * K+P iMX6Q KP_IMX6Q_TPC board configuration
- *
- * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
- */
-
-#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_
-#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_
-
-#include <asm/arch/imx-regs.h>
-
-#include "mx6_common.h"
-
-/* SPL */
-#include "imx6_spl.h" /* common IMX6 SPL configuration */
-
-/* Miscellaneous configurable options */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
-
-/* FEC ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
-
-/* UART */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
-#endif
-
-/* Watchdog */
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200\0" \
- "fdt_addr=0x18000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x10008000\0" \
- "fdt_addr_r=0x13000000\0" \
- "ramdisk_addr_r=0x18000000\0" \
- "scriptaddr=0x14000000\0" \
- "kernel_file=fitImage\0"\
- "rdinit=/sbin/init\0" \
- "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
- "fit_config=mx6q_tpc70_conf\0" \
- "upd_image=st.4k\0" \
- "updargs=setenv bootargs console=${console} ${smp}"\
- "rdinit=${rdinit} ${debug} ${displayargs}\0" \
- "loadusb=usb start; " \
- "fatload usb 0 ${loadaddr} ${upd_image}\0" \
- "usbupd=echo Booting update from usb ...; " \
- "setenv bootargs; " \
- "run updargs; " \
- "run loadusb; " \
- "bootm ${loadaddr}#${fit_config}\0" \
- BOOTENV
-
-#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(USB, usb, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-#endif
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment */
-#define CONFIG_ENV_SIZE (SZ_8K)
-#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 58/93] arm: Remove lsxhl board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (56 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 57/93] arm: Remove kp_imx6q_tpc board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 59/93] arm: Remove udoo board Simon Glass
` (39 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/buffalo/lsxl/Kconfig | 12 --
board/buffalo/lsxl/MAINTAINERS | 7 -
board/buffalo/lsxl/Makefile | 6 -
board/buffalo/lsxl/README | 139 -------------
board/buffalo/lsxl/kwbimage-lschl.cfg | 211 -------------------
board/buffalo/lsxl/kwbimage-lsxhl.cfg | 211 -------------------
board/buffalo/lsxl/lsxl.c | 279 --------------------------
board/buffalo/lsxl/lsxl.h | 58 ------
configs/lschlv2_defconfig | 42 ----
configs/lsxhl_defconfig | 42 ----
include/configs/lsxl.h | 149 --------------
12 files changed, 1157 deletions(-)
delete mode 100644 board/buffalo/lsxl/Kconfig
delete mode 100644 board/buffalo/lsxl/MAINTAINERS
delete mode 100644 board/buffalo/lsxl/Makefile
delete mode 100644 board/buffalo/lsxl/README
delete mode 100644 board/buffalo/lsxl/kwbimage-lschl.cfg
delete mode 100644 board/buffalo/lsxl/kwbimage-lsxhl.cfg
delete mode 100644 board/buffalo/lsxl/lsxl.c
delete mode 100644 board/buffalo/lsxl/lsxl.h
delete mode 100644 configs/lschlv2_defconfig
delete mode 100644 configs/lsxhl_defconfig
delete mode 100644 include/configs/lsxl.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 299977c87d6..9261b606bb4 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -71,7 +71,6 @@ config SYS_SOC
default "kirkwood"
source "board/Marvell/openrd/Kconfig"
-source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
diff --git a/board/buffalo/lsxl/Kconfig b/board/buffalo/lsxl/Kconfig
deleted file mode 100644
index ef788963780..00000000000
--- a/board/buffalo/lsxl/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_LSXL
-
-config SYS_BOARD
- default "lsxl"
-
-config SYS_VENDOR
- default "buffalo"
-
-config SYS_CONFIG_NAME
- default "lsxl"
-
-endif
diff --git a/board/buffalo/lsxl/MAINTAINERS b/board/buffalo/lsxl/MAINTAINERS
deleted file mode 100644
index facc2dd7d94..00000000000
--- a/board/buffalo/lsxl/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-LSXL BOARD
-M: Michael Walle <michael@walle.cc>
-S: Maintained
-F: board/buffalo/lsxl/
-F: include/configs/lsxl.h
-F: configs/lschlv2_defconfig
-F: configs/lsxhl_defconfig
diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile
deleted file mode 100644
index 60babb0ded4..00000000000
--- a/board/buffalo/lsxl/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2012 Michael Walle
-# Michael Walle <michael@walle.cc>
-
-obj-y := lsxl.o
diff --git a/board/buffalo/lsxl/README b/board/buffalo/lsxl/README
deleted file mode 100644
index ef5ed428806..00000000000
--- a/board/buffalo/lsxl/README
+++ /dev/null
@@ -1,139 +0,0 @@
-Intro
------
-The Buffalo Linkstation Pro/Live, codename LS-XHL and LS-CHLv2, is a single
-disk NAS server. The PCBs of the LS-XHL and LS-CHLv2 are almost the same.
-The LS-XHL has a faster CPU and more RAM with a wider data bus, therefore
-the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell
-88F6281). The only on-board storage is a 4 Mbit SPI flash which stores the
-bootloader and its environment. The linux kernel and the initial ramdisk
-are loaded from the hard disk.
-
-
-Rescue Mode
------------
-These linkstations don't have a populated serial port. There is no way to
-access an (unmodified) board other than using the netconsole. If you want
-to recover from a bad environment setting or an empty environment, you can
-do this only with a working network connection.
-
-Therefore, on entering the resuce mode, a random ethernet address is
-generated if no valid address could be loaded from the environment variable
-'ethaddr' and a DHCP request is sent. After a successful DHCP response is
-received, the network settings are configured and the ncip is unset. Thus
-all netconsole packets are broadcasted and you can use the netconsole to
-access board from any host within the network segment. To determine the IP
-address assigned to the board, you either have to sniff the traffic or
-check the logs/leases of your DHCP server.
-
-The resuce mode is selected by holding the push button for at least one
-second, while powering-on the device. The status LED turns solid amber if
-the resuce mode is enabled, thus providing a visual feedback.
-
-Pressing the same button for at least 10 seconds on power-up will erase the
-environment and reset the board. In this case the visual indication will
-be:
-- blinking blue, for about one second
-- solid amber, for about nine seconds
-- blinking amber, until you release the button
-
-This ensures, that you still can recover a device with a broken
-environment by first erasing the environment and then entering the rescue
-mode.
-
-Once the rescue mode is started, use the ncb binary from the tools/
-directory to access your board. There is a helper script named
-'restore_env' to save your changes. It unsets all the network variables
-which were set by the rescue mode, saves your changes and then resets the
-board.
-
-The common use case for this is setting a MAC address. Let us assume you
-have an empty environment, the board comes up with the amber LED blinking.
-Then you enter the rescue mode, connect to the board with the ncb tool and
-use the following commands to set your MAC address:
-
- setenv ethaddr 00:00:00:00:00:00
- run restore_env
-
-Of course you need to replace the 00:00:00:00:00:00 with your valid MAC
-address, which can be found on a sticker on the bottom of your box.
-
-
-Status LED
-----------
-blinking blue
- Bootloader is running normally.
-
-blinking amber
- No ethaddr set. Use the `Rescue Mode` to set one.
-
-blinking red
- Something bad happend during loading the operating system.
-
-The default behavior of the linux kernel is to turn on the blue LED. So if
-the blinking blue LED changes to solid blue the kernel was loaded
-successfully.
-
-
-Power-on Switch
----------------
-The power-on switch is a software switch. If it is not in ON position when
-the bootloader starts, the bootloader will disable the HDD and USB power
-and stop the fan. Then it loops until the switch is in ON position again,
-enables the power and fan again and continue booting.
-
-
-Boot sources
-------------
-The environment defines several different boot sources:
-
-legacy
- This is the default boot source. It loads the kernel and ramdisk from the
- attached HDD using the original filenames. The load addresses were
- modified to support loading larger kernels. But it should behave the same
- as the original bootloader.
-
-hdd
- Use this for new-style booting. Loads three files /vmlinuz, /initrd.img
- and /dtb from the boot partition. This should work out of the box if you
- have debian and the flash-kernel package installed.
-
-usb
- Same as hdd expect, that the files are loaded from an attached USB mass
- storage device and the filename for the device tree is kirkwood-lsxhl.dtb
- (or kirkwood-lschlv2.dtb).
-
-net
- Same as usb expect, that the file are loaded from the network.
-
-rescue
- Automatically activated if the push button is pressed for at least one
- second on power-up. Does a DHCP request and enables the network console.
- See `Rescue Mode` for more information.
-
-You can change the boot source by setting the 'bootsource' variable to the
-corresponding value. Please note, that the restore_env script will the the
-bootsource back to 'legacy'.
-
-
-Flash map
----------
-00000 - 5ffff u-boot
-60000 - 6ffff reserved, may be used to store dtb
-70000 - 7ffff u-boot environment
-
-
-Compiling
----------
-make lsxhl_config (or lschlv2_config)
-make u-boot.kwb
-
-
-Update your board
------------------
-Just flash the resulting u-boot.kwb to the beginning of the SPI flash. If
-you already have a bootloader CLI, you can use the following commands:
-
- sf probe 0
- bootp ${loadaddr} u-boot.kwb
- sf erase 0 +${filelen}
- sf write 0 ${fileaddr} ${filesize}
diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg
deleted file mode 100644
index 4493307d87e..00000000000
--- a/board/buffalo/lsxl/kwbimage-lschl.cfg
+++ /dev/null
@@ -1,211 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2012 Michael Walle
-# Michael Walle <michael@walle.cc>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0/1 interface pad voltage to 1.8V
-DATA 0xFFD100E0 0x1B1B1B9B
-
-# L2 RAM Timing 0
-DATA 0xFFD20134 0xBBBBBBBB
-# not further specified in HW manual, timing taken from original vendor port
-
-# L2 RAM Timing 1
-DATA 0xFFD20138 0x00BBBBBB
-# not further specified in HW manual, timing taken from original vendor port
-
-# DDR Configuration register
-DATA 0xFFD01400 0x43000618
-# bit13-0: 0x618, 1560 DDR2 clks refresh rate
-# bit23-14: 0 required
-# bit24: 1, enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: 0 required
-# bit31-30: 0b01 required
-
-# DDR Controller Control Low
-DATA 0xFFD01404 0x39543000
-# bit3-0: 0 required
-# bit4: 0, addr/cmd in same cycle
-# bit5: 0, clk is driven during self refresh, we don't care for APX
-# bit6: 0, use recommended falling edge of clk for addr/cmd
-# bit11-7: 0 required
-# bit12: 1 required
-# bit13: 1 required
-# bit14: 0, input buffer always powered up
-# bit17-15: 0 required
-# bit18: 1, cpu lock transaction enabled
-# bit19: 0 required
-# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0, no additional STARTBURST delay
-
-# DDR Timing (Low)
-DATA 0xFFD01408 0x3302444F
-# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
-# bit7-4: 4, 5 cycle tRCD
-# bit11-8: 4, 5 cyle tRP
-# bit15-12: 4, 5 cyle tWR
-# bit19-16: 2, 3 cyle tWTR
-# bit20: 0, 16 cycle tRAS (tRAS[4])
-# bit23-21: 0 required
-# bit27-24: 3, 4 cycle tRRD
-# bit31-28: 3, 4 cyle tRTP
-
-# DDR Timing (High)
-DATA 0xFFD0140C 0x00000823
-# bit6-0: 0x23, 35 cycle tRFC
-# bit8-7: 0, 1 cycle tR2R
-# bit10-9: 0, 1 cyle tR2W
-# bit12-11: 1, 2 cylce tW2W
-# bit31-13: 0 required
-
-# DDR Address Control
-DATA 0xFFD01410 0x00000009
-# bit1-0: 1, Cs0width=x16
-# bit3-2: 2, Cs0size=512Mbit
-# bit5-4: 0, Cs1width=nonexistent
-# bit7-6: 0, Cs1size=nonexistent
-# bit9-8: 0, Cs2width=nonexistent
-# bit11-10: 0, Cs2size=nonexistent
-# bit13-12: 0, Cs3width=nonexistent
-# bit15-14: 0, Cs3size=nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-# DDR Open Pages Control
-DATA 0xFFD01414 0x00000000
-# bit0: 0, OPEn=OpenPage enabled
-# bit31-1: 0 required
-
-# DDR Operation
-DATA 0xFFD01418 0x00000000
-# bit3-0: 0, Cmd=Normal SDRAM Mode
-# bit31-4: 0 required
-
-# DDR Mode
-DATA 0xFFD0141C 0x00000652
-# bit2-0: 2, Burst Length (2 required)
-# bit3: 0, Burst Type (0 required)
-# bit6-4: 5, CAS Latency (CL) 5
-# bit7: 0, (Test Mode) Normal operation
-# bit8: 0, (Reset DLL) Normal operation
-# bit11-9: 3, Write recovery for auto-precharge (3 required)
-# bit12: 0, Fast Active power down exit time (0 required)
-# bit31-13: 0 required
-
-# DDR Extended Mode
-DATA 0xFFD01420 0x00000042
-# bit0: 0, DRAM DLL enabled
-# bit1: 1, DRAM drive strength reduced
-# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
-# bit5-3: 0 required
-# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
-# bit9-7: 0 required
-# bit10: 0, differential DQS enabled
-# bit11: 0 required
-# bit12: 0, DRAM output buffer enabled
-# bit31-13: 0 required
-
-# DDR Controller Control High
-DATA 0xFFD01424 0x0000F17F
-# bit2-0: 0x7 required
-# bit3: 1, MBUS Burst Chop disabled
-# bit6-4: 0x7 required
-# bit7: 0 required (???)
-# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9: 0, no half clock cycle addition to dataout
-# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11: 0, 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 0xf required
-# bit31-16: 0 required
-
-# DDR2 ODT Read Timing (default values)
-DATA 0xFFD01428 0x00085520
-# bit3-0: 0 required
-# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
-# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
-# bit31-20: 0 required
-
-# DDR2 ODT Write Timing (default values)
-DATA 0xFFD0147C 0x00008552
-# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
-# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
-# bit31-16: 0 required
-
-# CS[0]n Base address
-DATA 0xFFD01500 0x00000000
-# at 0x0
-
-# CS[0]n Size
-DATA 0xFFD01504 0x03FFFFF1
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 0x0, CS0 hit selected
-# bit23-4: 0xfffff required
-# bit31-24: 0x03, Size (i.e. 64MB)
-
-# CS[1]n Size
-DATA 0xFFD0150C 0x00000000
-# window disabled
-
-# CS[2]n Size
-DATA 0xFFD01514 0x00000000
-# window disabled
-
-# CS[3]n Size
-DATA 0xFFD0151C 0x00000000
-# window disabled
-
-# DDR ODT Control (Low)
-DATA 0xFFD01494 0x003C0000
-# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
-# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
-# bit15-8: 0 required
-# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
-# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
-# bit31-24: 0 required
-
-# DDR ODT Control (High)
-DATA 0xFFD01498 0x00000000
-# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
-# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
-# bit31-4 0 required
-
-# CPU ODT Control
-DATA 0xFFD0149C 0x0000E80F
-# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
-# bit9-8: 0, Internal ODT assertion is controlled by fiels
-# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
-# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT enabled
-# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
-# bit20-16: 0, Pad N channel driving strength for ODT
-# bit25-21: 0, Pad P channel driving strength for ODT
-# bit31-26: 0 required
-
-# DDR Initialization Control
-DATA 0xFFD01480 0x00000001
-# bit0: 1, enable DDR init upon this register write
-# bit31-1: 0, required
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
deleted file mode 100644
index 4335a663c97..00000000000
--- a/board/buffalo/lsxl/kwbimage-lsxhl.cfg
+++ /dev/null
@@ -1,211 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2012 Michael Walle
-# Michael Walle <michael@walle.cc>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0/1 interface pad voltage to 1.8V
-DATA 0xFFD100E0 0x1B1B9B9B
-
-# L2 RAM Timing 0
-DATA 0xFFD20134 0xBBBBBBBB
-# not further specified in HW manual, timing taken from original vendor port
-
-# L2 RAM Timing 1
-DATA 0xFFD20138 0x00BBBBBB
-# not further specified in HW manual, timing taken from original vendor port
-
-# DDR Configuration register
-DATA 0xFFD01400 0x43000618
-# bit13-0: 0x618, 1560 DDR2 clks refresh rate
-# bit23-14: 0 required
-# bit24: 1, enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: 0 required
-# bit31-30: 0b01 required
-
-# DDR Controller Control Low
-DATA 0xFFD01404 0x39543010
-# bit3-0: 0 required
-# bit4: 1, T2 mode, addr/cmd are driven for two cycles
-# bit5: 0, clk is driven during self refresh, we don't care for APX
-# bit6: 0, use recommended falling edge of clk for addr/cmd
-# bit11-7: 0 required
-# bit12: 1 required
-# bit13: 1 required
-# bit14: 0, input buffer always powered up
-# bit17-15: 0 required
-# bit18: 1, cpu lock transaction enabled
-# bit19: 0 required
-# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0, no additional STARTBURST delay
-
-# DDR Timing (Low)
-DATA 0xFFD01408 0x22125441
-# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
-# bit7-4: 4, 5 cycle tRCD
-# bit11-8: 4, 5 cyle tRP
-# bit15-12: 5, 6 cyle tWR
-# bit19-16: 2, 3 cyle tWTR
-# bit20: 1, 18 cycle tRAS (tRAS[4])
-# bit23-21: 0 required
-# bit27-24: 2, 3 cycle tRRD
-# bit31-28: 2, 3 cyle tRTP
-
-# DDR Timing (High)
-DATA 0xFFD0140C 0x00000832
-# bit6-0: 0x32, 50 cycle tRFC
-# bit8-7: 0, 1 cycle tR2R
-# bit10-9: 0, 1 cyle tR2W
-# bit12-11: 1, 2 cylce tW2W
-# bit31-13: 0 required
-
-# DDR Address Control
-DATA 0xFFD01410 0x0000000C
-# bit1-0: 0, Cs0width=x8
-# bit3-2: 3, Cs0size=1Gbit
-# bit5-4: 0, Cs1width=nonexistent
-# bit7-6: 0, Cs1size=nonexistent
-# bit9-8: 0, Cs2width=nonexistent
-# bit11-10: 0, Cs2size=nonexistent
-# bit13-12: 0, Cs3width=nonexistent
-# bit15-14: 0, Cs3size=nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-# DDR Open Pages Control
-DATA 0xFFD01414 0x00000000
-# bit0: 0, OPEn=OpenPage enabled
-# bit31-1: 0 required
-
-# DDR Operation
-DATA 0xFFD01418 0x00000000
-# bit3-0: 0, Cmd=Normal SDRAM Mode
-# bit31-4: 0 required
-
-# DDR Mode
-DATA 0xFFD0141C 0x00000652
-# bit2-0: 2, Burst Length (2 required)
-# bit3: 0, Burst Type (0 required)
-# bit6-4: 5, CAS Latency (CL) 5
-# bit7: 0, (Test Mode) Normal operation
-# bit8: 0, (Reset DLL) Normal operation
-# bit11-9: 3, Write recovery for auto-precharge (3 required)
-# bit12: 0, Fast Active power down exit time (0 required)
-# bit31-13: 0 required
-
-# DDR Extended Mode
-DATA 0xFFD01420 0x00000006
-# bit0: 0, DRAM DLL enabled
-# bit1: 1, DRAM drive strength reduced
-# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
-# bit5-3: 0 required
-# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
-# bit9-7: 0 required
-# bit10: 0, differential DQS enabled
-# bit11: 0 required
-# bit12: 0, DRAM output buffer enabled
-# bit31-13: 0 required
-
-# DDR Controller Control High
-DATA 0xFFD01424 0x0000F17F
-# bit2-0: 0x7 required
-# bit3: 1, MBUS Burst Chop disabled
-# bit6-4: 0x7 required
-# bit7: 0 required (???)
-# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9: 0, no half clock cycle addition to dataout
-# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11: 0, 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 0xf required
-# bit31-16: 0 required
-
-# DDR2 ODT Read Timing (default values)
-DATA 0xFFD01428 0x00085520
-# bit3-0: 0 required
-# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
-# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
-# bit31-20: 0 required
-
-# DDR2 ODT Write Timing (default values)
-DATA 0xFFD0147C 0x00008552
-# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
-# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
-# bit31-16: 0 required
-
-# CS[0]n Base address
-DATA 0xFFD01500 0x00000000
-# at 0x0
-
-# CS[0]n Size
-DATA 0xFFD01504 0x0FFFFFF1
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 0x0, CS0 hit selected
-# bit23-4: 0xfffff required
-# bit31-24: 0x0f, Size (i.e. 256MB)
-
-# CS[1]n Size
-DATA 0xFFD0150C 0x00000000
-# window disabled
-
-# CS[2]n Size
-DATA 0xFFD01514 0x00000000
-# window disabled
-
-# CS[3]n Size
-DATA 0xFFD0151C 0x00000000
-# window disabled
-
-# DDR ODT Control (Low)
-DATA 0xFFD01494 0x00010000
-# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
-# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
-# bit15-8: 0 required
-# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
-# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
-# bit31-24: 0 required
-
-# DDR ODT Control (High)
-DATA 0xFFD01498 0x00000000
-# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
-# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
-# bit31-4 0 required
-
-# CPU ODT Control
-DATA 0xFFD0149C 0x0000E80F
-# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
-# bit9-8: 0, Internal ODT assertion is controlled by fiels
-# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
-# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT enabled
-# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
-# bit20-16: 0, Pad N channel driving strength for ODT
-# bit25-21: 0, Pad P channel driving strength for ODT
-# bit31-26: 0 required
-
-# DDR Initialization Control
-DATA 0xFFD01480 0x00000001
-# bit0: 1, enable DDR init upon this register write
-# bit31-1: 0, required
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
deleted file mode 100644
index bf69a746e4d..00000000000
--- a/board/buffalo/lsxl/lsxl.c
+++ /dev/null
@@ -1,279 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2012 Michael Walle
- * Michael Walle <michael@walle.cc>
- *
- * Based on sheevaplug/sheevaplug.c by
- * Marvell Semiconductor <www.marvell.com>
- */
-
-#include <common.h>
-#include <environment.h>
-#include <net.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#include "lsxl.h"
-
-/*
- * Rescue mode
- *
- * Selected by holding the push button for 3 seconds, while powering on
- * the device.
- *
- * These linkstations don't have a (populated) serial port. There is no
- * way to access an (unmodified) board other than using the netconsole. If
- * you want to recover from a bad environment setting or an empty environment,
- * you can do this only with a working network connection. Therefore, a random
- * ethernet address is generated if none is set and a DHCP request is sent.
- * After a successful DHCP response is received, the network settings are
- * configured and the ncip is unset. Therefore, all netconsole packets are
- * broadcasted.
- * Additionally, the bootsource is set to 'rescue'.
- */
-
-#ifndef CONFIG_ENV_OVERWRITE
-# error "You need to set CONFIG_ENV_OVERWRITE"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(LSXL_OE_VAL_LOW,
- LSXL_OE_VAL_HIGH,
- LSXL_OE_LOW, LSXL_OE_HIGH);
-
- /*
- * Multi-Purpose Pins Functionality configuration
- * These strappings are taken from the original vendor uboot port.
- */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_UART0_RXD,
- MPP5_UART0_TXD,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_GPIO,
- MPP9_GPIO,
- MPP10_GPO, /* HDD power */
- MPP11_GPIO, /* USB Vbus enable */
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_GPO, /* fan speed high */
- MPP19_GPO, /* fan speed low */
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO, /* function LED */
- MPP37_GPIO, /* alarm LED */
- MPP38_GPIO, /* info LED */
- MPP39_GPIO, /* power LED */
- MPP40_GPIO, /* fan alarm */
- MPP41_GPIO, /* funtion button */
- MPP42_GPIO, /* power switch */
- MPP43_GPIO, /* power auto switch */
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO, /* function red LED */
- MPP49_GPIO,
- 0
- };
-
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-#define LED_OFF 0
-#define LED_ALARM_ON 1
-#define LED_ALARM_BLINKING 2
-#define LED_POWER_ON 3
-#define LED_POWER_BLINKING 4
-#define LED_INFO_ON 5
-#define LED_INFO_BLINKING 6
-
-static void __set_led(int blink_alarm, int blink_info, int blink_power,
- int value_alarm, int value_info, int value_power)
-{
- kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm);
- kw_gpio_set_blink(GPIO_INFO_LED, blink_info);
- kw_gpio_set_blink(GPIO_POWER_LED, blink_power);
- kw_gpio_set_value(GPIO_ALARM_LED, value_alarm);
- kw_gpio_set_value(GPIO_INFO_LED, value_info);
- kw_gpio_set_value(GPIO_POWER_LED, value_power);
-}
-
-static void set_led(int state)
-{
- switch (state) {
- case LED_OFF:
- __set_led(0, 0, 0, 1, 1, 1);
- break;
- case LED_ALARM_ON:
- __set_led(0, 0, 0, 0, 1, 1);
- break;
- case LED_ALARM_BLINKING:
- __set_led(1, 0, 0, 1, 1, 1);
- break;
- case LED_INFO_ON:
- __set_led(0, 0, 0, 1, 0, 1);
- break;
- case LED_INFO_BLINKING:
- __set_led(0, 1, 0, 1, 1, 1);
- break;
- case LED_POWER_ON:
- __set_led(0, 0, 0, 1, 1, 0);
- break;
- case LED_POWER_BLINKING:
- __set_led(0, 0, 1, 1, 1, 1);
- break;
- }
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- set_led(LED_POWER_BLINKING);
-
- return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-static void check_power_switch(void)
-{
- if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
- /* turn off fan, HDD and USB power */
- kw_gpio_set_value(GPIO_HDD_POWER, 0);
- kw_gpio_set_value(GPIO_USB_VBUS, 0);
- kw_gpio_set_value(GPIO_FAN_HIGH, 1);
- kw_gpio_set_value(GPIO_FAN_LOW, 1);
- set_led(LED_OFF);
-
- /* loop until released */
- while (kw_gpio_get_value(GPIO_POWER_SWITCH))
- ;
-
- /* turn power on again */
- kw_gpio_set_value(GPIO_HDD_POWER, 1);
- kw_gpio_set_value(GPIO_USB_VBUS, 1);
- kw_gpio_set_value(GPIO_FAN_HIGH, 0);
- kw_gpio_set_value(GPIO_FAN_LOW, 0);
- set_led(LED_POWER_BLINKING);
- }
-}
-
-void check_enetaddr(void)
-{
- uchar enetaddr[6];
-
- if (!eth_env_get_enetaddr("ethaddr", enetaddr)) {
- /* signal unset/invalid ethaddr to user */
- set_led(LED_INFO_BLINKING);
- }
-}
-
-static void erase_environment(void)
-{
- struct spi_flash *flash;
-
- printf("Erasing environment..\n");
- flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!flash) {
- printf("Erasing flash failed\n");
- return;
- }
-
- spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
- spi_flash_free(flash);
- do_reset(NULL, 0, 0, NULL);
-}
-
-static void rescue_mode(void)
-{
- printf("Entering rescue mode..\n");
- env_set("bootsource", "rescue");
-}
-
-static void check_push_button(void)
-{
- int i = 0;
-
- while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) {
- udelay(100000);
- i++;
-
- if (i == 10)
- set_led(LED_INFO_ON);
-
- if (i >= 100) {
- set_led(LED_INFO_BLINKING);
- break;
- }
- }
-
- if (i >= 100)
- erase_environment();
- else if (i >= 10)
- rescue_mode();
-}
-
-int misc_init_r(void)
-{
- check_power_switch();
- check_enetaddr();
- check_push_button();
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress(int progress)
-{
- if (progress > 0)
- return;
-
- /* this is not an error, eg. bootp with autoload=no will trigger this */
- if (progress == -BOOTSTAGE_ID_NET_LOADED)
- return;
-
- set_led(LED_ALARM_BLINKING);
-}
-#endif
diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h
deleted file mode 100644
index 8ff3f2f3a9b..00000000000
--- a/board/buffalo/lsxl/lsxl.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2012 Michael Walle
- * Michael Walle <michael@walle.cc>
- */
-
-#ifndef __LSXL_H
-#define __LSXL_H
-
-#define GPIO_HDD_POWER 10
-#define GPIO_USB_VBUS 11
-#define GPIO_FAN_HIGH 18
-#define GPIO_FAN_LOW 19
-#define GPIO_FUNC_LED 36
-#define GPIO_ALARM_LED 37
-#define GPIO_INFO_LED 38
-#define GPIO_POWER_LED 39
-#define GPIO_FAN_LOCK 40
-#define GPIO_FUNC_BUTTON 41
-#define GPIO_POWER_SWITCH 42
-#define GPIO_POWER_AUTO_SWITCH 43
-#define GPIO_FUNC_RED_LED 48
-
-#define _BIT(x) (1<<(x))
-
-#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \
- | _BIT(GPIO_USB_VBUS) \
- | _BIT(GPIO_FAN_HIGH) \
- | _BIT(GPIO_FAN_LOW)))
-
-#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \
- | _BIT(GPIO_ALARM_LED - 32) \
- | _BIT(GPIO_INFO_LED - 32) \
- | _BIT(GPIO_POWER_LED - 32) \
- | _BIT(GPIO_FUNC_RED_LED - 32)))
-
-#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \
- | _BIT(GPIO_USB_VBUS))
-
-#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
- | _BIT(GPIO_ALARM_LED - 32) \
- | _BIT(GPIO_INFO_LED - 32) \
- | _BIT(GPIO_POWER_LED - 32) \
- | _BIT(GPIO_FUNC_RED_LED - 32))
-
-#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \
- | _BIT(GPIO_FAN_LOW))
-
-#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
- | _BIT(GPIO_ALARM_LED - 32) \
- | _BIT(GPIO_INFO_LED - 32) \
- | _BIT(GPIO_POWER_LED - 32) \
- | _BIT(GPIO_FUNC_BUTTON - 32) \
- | _BIT(GPIO_POWER_SWITCH - 32) \
- | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
- | _BIT(GPIO_FUNC_RED_LED - 32))
-
-#endif /* __LSXL_H */
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
deleted file mode 100644
index 7466b6108df..00000000000
--- a/configs/lschlv2_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_LSXL=y
-CONFIG_IDENT_STRING=" LS-CHLv2"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
-CONFIG_API=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2"
-CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
deleted file mode 100644
index f55a69916ef..00000000000
--- a/configs/lsxhl_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_LSXL=y
-CONFIG_IDENT_STRING=" LS-XHL"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
-CONFIG_API=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2"
-CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
deleted file mode 100644
index 9d4be184131..00000000000
--- a/include/configs/lsxl.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2012 Michael Walle
- * Michael Walle <michael@walle.cc>
- */
-
-#ifndef _CONFIG_LSXL_H
-#define _CONFIG_LSXL_H
-
-/*
- * Version number information
- */
-#if defined(CONFIG_LSCHLV2)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
-#define CONFIG_MACH_TYPE 3006
-#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
-#elif defined(CONFIG_LSXHL)
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
-#define CONFIG_MACH_TYPE 2663
-/* CONFIG_SYS_TCLK is 200000000 by default */
-#else
-#error "unknown board"
-#endif
-
-/*
- * General configuration options
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_KIRKWOOD_GPIO
-
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* loading initramfs images without uimage header */
-
-/* ST M25P40 */
-#undef CONFIG_ENV_SPI_MAX_HZ
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#undef CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 8
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
-#endif
-
-#define CONFIG_ENV_SIZE 0x10000 /* 64k */
-#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_LOADADDR 0x00800000
-
-#if defined(CONFIG_LSXHL)
-#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb"
-#elif defined(CONFIG_LSCHLV2)
-#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb"
-#else
-#error "Unsupported board"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootsource=legacy\0" \
- "hdpart=0:1\0" \
- "kernel_addr=0x00800000\0" \
- "ramdisk_addr=0x01000000\0" \
- "fdt_addr=0x00ff0000\0" \
- "bootcmd_legacy=ide reset " \
- "&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \
- "&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\
- "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "bootcmd_net=bootp ${kernel_addr} vmlinuz " \
- "&& tftpboot ${ramdisk_addr} initrd.img " \
- "&& setenv ramdisk_len ${filesize} " \
- "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \
- "&& bootz ${kernel_addr} " \
- "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
- "bootcmd_hdd=ide reset " \
- "&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \
- "&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \
- "&& setenv ramdisk_len ${filesize} " \
- "&& load ide ${hdpart} ${fdt_addr} /dtb " \
- "&& bootz ${kernel_addr} " \
- "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
- "bootcmd_usb=usb start " \
- "&& load usb 0:1 ${kernel_addr} /vmlinuz " \
- "&& load usb 0:1 ${ramdisk_addr} /initrd.img " \
- "&& setenv ramdisk_len ${filesize} " \
- "&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \
- "&& bootz ${kernel_addr} " \
- "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
- "bootcmd_rescue=run config_nc_dhcp; run nc\0" \
- "eraseenv=sf probe 0 " \
- "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \
- " +" __stringify(CONFIG_ENV_SIZE) "\0" \
- "config_nc_dhcp=setenv autoload_old ${autoload}; " \
- "setenv autoload no " \
- "&& bootp " \
- "&& setenv ncip " \
- "&& setenv autoload ${autoload_old}; " \
- "setenv autoload_old\0" \
- "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
- "setenv ncip; setenv gatewayip; setenv ethact; " \
- "setenv bootfile; setenv dnsip; " \
- "setenv bootsource legacy; run ser\0" \
- "restore_env=run standard_env; saveenv; reset\0" \
- "ser=setenv stdin serial; setenv stdout serial; " \
- "setenv stderr serial\0" \
- "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */
-#define CONFIG_PHY_BASE_ADR 7
-#undef CONFIG_RESET_PHY_R
-#endif /* CONFIG_CMD_NET */
-
-#ifdef CONFIG_IDE
-#undef CONFIG_SYS_IDE_MAXBUS
-#define CONFIG_SYS_IDE_MAXBUS 1
-#undef CONFIG_SYS_IDE_MAXDEVICE
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_64BIT_LBA
-#endif
-
-#endif /* _CONFIG_LSXL_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 59/93] arm: Remove udoo board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (57 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 58/93] arm: Remove lsxhl board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 60/93] arm: Remove marsboard board Simon Glass
` (38 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/udoo/Kconfig | 9 --
board/udoo/MAINTAINERS | 6 -
board/udoo/Makefile | 5 -
board/udoo/README | 21 ---
board/udoo/udoo.c | 271 ----------------------------------
board/udoo/udoo_spl.c | 254 -------------------------------
configs/udoo_defconfig | 36 -----
include/configs/udoo.h | 95 ------------
9 files changed, 698 deletions(-)
delete mode 100644 board/udoo/Kconfig
delete mode 100644 board/udoo/MAINTAINERS
delete mode 100644 board/udoo/Makefile
delete mode 100644 board/udoo/README
delete mode 100644 board/udoo/udoo.c
delete mode 100644 board/udoo/udoo_spl.c
delete mode 100644 configs/udoo_defconfig
delete mode 100644 include/configs/udoo.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 71e57690d6e..ba7284a8bde 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -550,7 +550,6 @@ source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
-source "board/udoo/Kconfig"
source "board/warp/Kconfig"
endif
diff --git a/board/udoo/Kconfig b/board/udoo/Kconfig
deleted file mode 100644
index 78617a21383..00000000000
--- a/board/udoo/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_UDOO
-
-config SYS_BOARD
- default "udoo"
-
-config SYS_CONFIG_NAME
- default "udoo"
-
-endif
diff --git a/board/udoo/MAINTAINERS b/board/udoo/MAINTAINERS
deleted file mode 100644
index b05243c429d..00000000000
--- a/board/udoo/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-UDOO BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/udoo/
-F: include/configs/udoo.h
-F: configs/udoo_defconfig
diff --git a/board/udoo/Makefile b/board/udoo/Makefile
deleted file mode 100644
index 66f67f7c154..00000000000
--- a/board/udoo/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y := udoo.o udoo_spl.o
diff --git a/board/udoo/README b/board/udoo/README
deleted file mode 100644
index 6fbcc598f77..00000000000
--- a/board/udoo/README
+++ /dev/null
@@ -1,21 +0,0 @@
-How to use U-Boot on MX6Q/DL Udoo boards
-----------------------------------------
-
-- Build U-Boot for MX6Q/DL Udoo boards:
-
-$ make mrproper
-$ make udoo_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the u-boot.img image into the SD card:
-
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Insert the SD card in the board, power it up and U-Boot messages should
-come up.
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
deleted file mode 100644
index 491e9be1c22..00000000000
--- a/board/udoo/udoo.c
+++ /dev/null
@@ -1,271 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <malloc.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define WDT_EN IMX_GPIO_NR(5, 4)
-#define WDT_TRG IMX_GPIO_NR(3, 19)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart2_pads[] = {
- IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
-};
-
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- /*
- * Bug: Apparently uDoo does not works with Gigabit switches...
- * Limiting speed to 10/100Mbps, and setting master mode, seems to
- * be the only way to have a successfull PHY auto negotiation.
- * How to fix: Understand why Linux kernel do not have this issue.
- */
- phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
-
- /* control data pad skew - devaddr = 0x02, register = 0x04 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* rx data pad skew - devaddr = 0x02, register = 0x05 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* tx data pad skew - devaddr = 0x02, register = 0x05 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
- /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
- ksz9031_phy_extended_write(phydev, 0x02,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
- return 0;
-}
-
-static iomux_v3_cfg_t const enet_pads1[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* RGMII reset */
- IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* Ethernet power supply */
- IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 32 - 1 - (MODE0) all */
- IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 31 - 1 - (MODE1) all */
- IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 28 - 1 - (MODE2) all */
- IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 27 - 1 - (MODE3) all */
- IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads2[] = {
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-};
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads1);
- udelay(20);
- gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
-
- gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
-
- gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
- gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
- udelay(1000);
-
- gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
-
- /* Need 100ms delay to exit from reset. */
- udelay(1000 * 100);
-
- gpio_free(IMX_GPIO_NR(6, 24));
- gpio_free(IMX_GPIO_NR(6, 25));
- gpio_free(IMX_GPIO_NR(6, 27));
- gpio_free(IMX_GPIO_NR(6, 28));
- gpio_free(IMX_GPIO_NR(6, 29));
-
- SETUP_IOMUX_PADS(enet_pads2);
-}
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart2_pads);
-}
-
-static void setup_iomux_wdog(void)
-{
- SETUP_IOMUX_PADS(wdog_pads);
- gpio_direction_output(WDT_TRG, 0);
- gpio_direction_output(WDT_EN, 1);
- gpio_direction_input(WDT_TRG);
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return 1; /* Always present */
-}
-
-int board_eth_init(bd_t *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
- /* scan phy 4,5,6,7 */
- phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
-
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
- printf("using phy@%d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret)
- goto free_phydev;
-#endif
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg.max_bus_width = 4;
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_wdog();
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_cpu_type(MXC_CPU_MX6Q))
- env_set("board_rev", "MX6Q");
- else
- env_set("board_rev", "MX6DL");
-#endif
- return 0;
-}
-
-int checkboard(void)
-{
- if (is_cpu_type(MXC_CPU_MX6Q))
- puts("Board: Udoo Quad\n");
- else
- puts("Board: Udoo DualLite\n");
-
- return 0;
-}
diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
deleted file mode 100644
index 30663e20251..00000000000
--- a/board/udoo/udoo_spl.c
+++ /dev/null
@@ -1,254 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Udoo
- * Author: Tungyi Lin <tungyilin1127@gmail.com>
- * Richard Hu <hakahu@gmail.com>
- * Based on board/wandboard/spl.c
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-
-#if defined(CONFIG_SPL_BUILD)
-#include <asm/arch/mx6-ddr.h>
-
-/*
- * Driving strength:
- * 0x30 == 40 Ohm
- * 0x28 == 48 Ohm
- */
-#define IMX6DQ_DRIVE_STRENGTH 0x30
-#define IMX6SDL_DRIVE_STRENGTH 0x28
-
-/* configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
- .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_cas = IMX6DQ_DRIVE_STRENGTH,
- .dram_ras = IMX6DQ_DRIVE_STRENGTH,
- .dram_reset = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
-};
-
-/* configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
- .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
- /* quad = 1066, duallite = 800 */
- .mem_speed = 1066,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 0,
-};
-
-static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x00350035,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x00010001,
- .p1_mpwldectrl1 = 0x00010001,
- .p0_mpdgctrl0 = 0x43510360,
- .p0_mpdgctrl1 = 0x0342033F,
- .p1_mpdgctrl0 = 0x033F033F,
- .p1_mpdgctrl1 = 0x03290266,
- .p0_mprddlctl = 0x4B3E4141,
- .p1_mprddlctl = 0x47413B4A,
- .p0_mpwrdlctl = 0x42404843,
- .p1_mpwrdlctl = 0x4C3F4C45,
-};
-
-static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x002F0038,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x001F001F,
- .p1_mpwldectrl1 = 0x001F001F,
- .p0_mpdgctrl0 = 0x425C0251,
- .p0_mpdgctrl1 = 0x021B021E,
- .p1_mpdgctrl0 = 0x021B021E,
- .p1_mpdgctrl1 = 0x01730200,
- .p0_mprddlctl = 0x45474C45,
- .p1_mprddlctl = 0x44464744,
- .p0_mpwrdlctl = 0x3F3F3336,
- .p1_mpwrdlctl = 0x32383630,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_qdl = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- /* quad = 2, duallite = 1 */
- .rtt_nom = 2,
- /* quad = 2, duallite = 1 */
- .rtt_wr = 2,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* set the default clock gate to save power */
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
- if (is_cpu_type(MXC_CPU_MX6DL)) {
- mt41k128m16jt_125.mem_speed = 800;
- mem_qdl.rtt_nom = 1;
- mem_qdl.rtt_wr = 1;
-
- mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
- } else if (is_cpu_type(MXC_CPU_MX6Q)) {
- mt41k128m16jt_125.mem_speed = 1066;
- mem_qdl.rtt_nom = 2;
- mem_qdl.rtt_wr = 2;
-
- mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
- mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
- }
-
- udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- gpr_init();
-
- /* iomux */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-}
-#endif
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
deleted file mode 100644
index c9a860c20f5..00000000000
--- a/configs/udoo_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_UDOO=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
deleted file mode 100644
index 3378b4a601c..00000000000
--- a/include/configs/udoo.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * Configuration settings for Udoo board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#include "imx6_spl.h"
-
-/* Provide the MACH_TYPE value that the vendor kernel requires. */
-#define CONFIG_MACH_TYPE 4800
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-/* SATA Configs */
-
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* Network support */
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 6
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-
-/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc1,115200\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdtfile=undefined\0" \
- "fdt_addr=0x18000000\0" \
- "fdt_addr_r=0x18000000\0" \
- "ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcrootfstype=ext4\0" \
- "findfdt="\
- "if test ${board_rev} = MX6Q; then " \
- "setenv fdtfile imx6q-udoo.dtb; fi; " \
- "if test ${board_rev} = MX6DL; then " \
- "setenv fdtfile imx6dl-udoo.dtb; fi; " \
- "if test ${fdtfile} = undefined; then " \
- "echo WARNING: Could not determine dtb to use; fi\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_addr_r=0x13000000\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(SATA, sata, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-#endif /* __CONFIG_H * */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 60/93] arm: Remove marsboard board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (58 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 59/93] arm: Remove udoo board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 61/93] arm: Remove mx6sabresd board Simon Glass
` (37 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/embest/mx6boards/Kconfig | 12 -
board/embest/mx6boards/MAINTAINERS | 7 -
board/embest/mx6boards/Makefile | 7 -
board/embest/mx6boards/mx6boards.c | 610 -----------------------------
configs/marsboard_defconfig | 37 --
configs/riotboard_defconfig | 37 --
include/configs/embestmx6boards.h | 150 -------
8 files changed, 861 deletions(-)
delete mode 100644 board/embest/mx6boards/Kconfig
delete mode 100644 board/embest/mx6boards/MAINTAINERS
delete mode 100644 board/embest/mx6boards/Makefile
delete mode 100644 board/embest/mx6boards/mx6boards.c
delete mode 100644 configs/marsboard_defconfig
delete mode 100644 configs/riotboard_defconfig
delete mode 100644 include/configs/embestmx6boards.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ba7284a8bde..0859619af3b 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -531,7 +531,6 @@ source "board/boundary/nitrogen6x/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
-source "board/embest/mx6boards/Kconfig"
source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
diff --git a/board/embest/mx6boards/Kconfig b/board/embest/mx6boards/Kconfig
deleted file mode 100644
index 24d01f22664..00000000000
--- a/board/embest/mx6boards/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_EMBESTMX6BOARDS
-
-config SYS_BOARD
- default "mx6boards"
-
-config SYS_VENDOR
- default "embest"
-
-config SYS_CONFIG_NAME
- default "embestmx6boards"
-
-endif
diff --git a/board/embest/mx6boards/MAINTAINERS b/board/embest/mx6boards/MAINTAINERS
deleted file mode 100644
index 0ffd4668b42..00000000000
--- a/board/embest/mx6boards/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MX6BOARDS BOARD
-M: Eric Bénard <eric@eukrea.com>
-S: Maintained
-F: board/embest/mx6boards/
-F: include/configs/embestmx6boards.h
-F: configs/marsboard_defconfig
-F: configs/riotboard_defconfig
diff --git a/board/embest/mx6boards/Makefile b/board/embest/mx6boards/Makefile
deleted file mode 100644
index a032a3df9f7..00000000000
--- a/board/embest/mx6boards/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx6boards.o
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
deleted file mode 100644
index 8930c36fe66..00000000000
--- a/board/embest/mx6boards/mx6boards.c
+++ /dev/null
@@ -1,610 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Eukréa Electromatique
- * Author: Eric Bénard <eric@eukrea.com>
- * Fabio Estevam <fabio.estevam@freescale.com>
- * Jon Nettleton <jon.nettleton@gmail.com>
- *
- * based on sabresd.c which is :
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * and on hummingboard.c which is :
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
-#include <asm/mach-imx/video.h>
-#include <i2c.h>
-#include <input.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
- PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-static int board_type = -1;
-#define BOARD_IS_MARSBOARD 0
-#define BOARD_IS_RIOTBOARD 1
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-}
-
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* GPIO16 -> AR8035 25MHz */
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- /* AR8035 PHY Reset */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- /* AR8035 PHY Interrupt */
- MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
- /* Reset AR8035 PHY */
- gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
- mdelay(2);
- gpio_set_value(IMX_GPIO_NR(3, 31), 1);
-}
-
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- /* from linux/arch/arm/mach-imx/mach-imx6q.c :
- * Ar803x phy SmartEEE feature cause link status generates glitch,
- * which cause ethernet link down/up issue, so disable SmartEEE
- */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
- MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* eMMC RST */
- MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- if (board_type == BOARD_IS_RIOTBOARD)
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- else if (board_type == BOARD_IS_MARSBOARD)
- ret = 1; /* eMMC/uSDHC3 is always present */
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- int i;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * ** RiOTboard :
- * mmc0 SDCard slot (bottom)
- * mmc1 uSDCard slot (top)
- * mmc2 eMMC
- * ** MarSBoard :
- * mmc0 uSDCard slot (bottom)
- * mmc1 eMMC
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[0].max_bus_width = 4;
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- if (board_type == BOARD_IS_RIOTBOARD) {
- imx_iomux_v3_setup_multiple_pads(
- riotboard_usdhc3_pads,
- ARRAY_SIZE(riotboard_usdhc3_pads));
- gpio_direction_input(USDHC3_CD_GPIO);
- } else {
- gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
- udelay(250);
- gpio_set_value(IMX_GPIO_NR(7, 8), 1);
- }
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[1].max_bus_width = 4;
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- usdhc_cfg[2].max_bus_width = 4;
- gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
- udelay(250);
- gpio_set_value(IMX_GPIO_NR(6, 8), 1);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t const ecspi1_pads[] = {
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
-}
-
-static void setup_spi(void)
-{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
-struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(1, 5)
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
- | MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-iomux_v3_cfg_t const tft_pads_riot[] = {
- /* LCD_PWR_EN */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* TOUCH_INT */
- MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LED_PWR_EN */
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* BL LEVEL */
- MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const tft_pads_mars[] = {
- /* LCD_PWR_EN */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* TOUCH_INT */
- MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LED_PWR_EN */
- MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* BL LEVEL (PWM4) */
- MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- setbits_le32(&iomux->gpr[2],
- IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
- /* set backlight level to ON */
- if (board_type == BOARD_IS_RIOTBOARD)
- gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
- else if (board_type == BOARD_IS_MARSBOARD)
- gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
-}
-
-static void disable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* set backlight level to OFF */
- if (board_type == BOARD_IS_RIOTBOARD)
- gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
- else if (board_type == BOARD_IS_MARSBOARD)
- gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
-
- clrbits_le32(&iomux->gpr[2],
- IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
-}
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- disable_lvds(dev);
- imx_enable_hdmi_phy();
-}
-
-static int detect_i2c(struct display_info_t const *dev)
-{
- return (0 == i2c_set_bus_num(dev->bus)) &&
- (0 == i2c_probe(dev->addr));
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 2,
- .addr = 0x1,
- .pixfmt = IPU_PIX_FMT_LVDS666,
- .detect = detect_i2c,
- .enable = enable_lvds,
- .mode = {
- .name = "LCD8000-97C",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15385,
- .left_margin = 100,
- .right_margin = 200,
- .upper_margin = 10,
- .lower_margin = 20,
- .hsync_len = 20,
- .vsync_len = 8,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* Turn on LDB0, IPU,IPU DI0 clocks */
- setbits_le32(&mxc_ccm->CCGR3,
- MXC_CCM_CCGR3_LDB_DI0_MASK);
-
- /* set LDB0 clk select to 011/011 */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
- (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
-
- setbits_le32(&mxc_ccm->cscmr2,
- MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-
- setbits_le32(&mxc_ccm->chsccdr,
- (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
- | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
- | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- clrsetbits_le32(&iomux->gpr[3],
- IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
- IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
- IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
- u32 cputype = cpu_type(get_cpu_rev());
-
- switch (cputype) {
- case MXC_CPU_MX6SOLO:
- board_type = BOARD_IS_RIOTBOARD;
- break;
- case MXC_CPU_MX6D:
- board_type = BOARD_IS_MARSBOARD;
- break;
- }
-
- setup_iomux_uart();
-
- if (board_type == BOARD_IS_RIOTBOARD)
- imx_iomux_v3_setup_multiple_pads(
- tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
- else if (board_type == BOARD_IS_MARSBOARD)
- imx_iomux_v3_setup_multiple_pads(
- tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
-#if defined(CONFIG_VIDEO_IPUV3)
- /* power ON LCD */
- gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
- /* touch interrupt is an input */
- gpio_direction_input(IMX_GPIO_NR(6, 14));
- /* power ON backlight */
- gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
- /* set backlight level to off */
- if (board_type == BOARD_IS_RIOTBOARD)
- gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
- else if (board_type == BOARD_IS_MARSBOARD)
- gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
- setup_display();
-#endif
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- /* i2c2 : HDMI EDID */
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- /* i2c3 : LVDS, Expansion connector */
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode riotboard_boot_modes[] = {
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
- {NULL, 0},
-};
-static const struct boot_mode marsboard_boot_modes[] = {
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- if (board_type == BOARD_IS_RIOTBOARD)
- add_board_boot_modes(riotboard_boot_modes);
- else if (board_type == BOARD_IS_RIOTBOARD)
- add_board_boot_modes(marsboard_boot_modes);
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: ");
- if (board_type == BOARD_IS_MARSBOARD)
- puts("MarSBoard\n");
- else if (board_type == BOARD_IS_RIOTBOARD)
- puts("RIoTboard\n");
- else
- printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
-
- return 0;
-}
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
deleted file mode 100644
index 1bc8894cfc4..00000000000
--- a/configs/marsboard_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_EMBESTMX6BOARDS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
-CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
deleted file mode 100644
index 1f00263bb4f..00000000000
--- a/configs/riotboard_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_EMBESTMX6BOARDS=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
-CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
deleted file mode 100644
index 71217f07e22..00000000000
--- a/include/configs/embestmx6boards.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Eukréa Electromatique
- * Author: Eric Bénard <eric@eukrea.com>
- *
- * Configuration settings for the Embest RIoTboard
- *
- * based on mx6*sabre*.h which are :
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __RIOTBOARD_CONFIG_H
-#define __RIOTBOARD_CONFIG_H
-
-#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONSOLE_DEV "ttymxc1"
-
-#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-
-#define CONFIG_IMX_THERMAL
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-
-#define CONFIG_MXC_UART
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 4
-
-#define CONFIG_PHY_ATHEROS
-
-#ifdef CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 20000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#endif
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-/* RiOTboard */
-#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-/* MarSBoard */
-#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_ENV_OFFSET (768 * 1024)
-#define CONFIG_ENV_SECT_SIZE (8 * 1024)
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
-
-/* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-#include "mx6_common.h"
-
-/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- * 1M script, 1M pxe and the ramdisk at the end */
-#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0x10000000\0" \
- "kernel_addr_r=0x12000000\0" \
- "fdt_addr_r=0x13000000\0" \
- "scriptaddr=0x13100000\0" \
- "pxefile_addr_r=0x13200000\0" \
- "ramdisk_addr_r=0x13300000\0"
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 2) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#define CONSOLE_STDIN_SETTINGS \
- "stdin=serial\0"
-
-#define CONSOLE_STDOUT_SETTINGS \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-#define CONSOLE_ENV_SETTINGS \
- CONSOLE_STDIN_SETTINGS \
- CONSOLE_STDOUT_SETTINGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONSOLE_ENV_SETTINGS \
- MEM_LAYOUT_ENV_SETTINGS \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "finduuid=part uuid mmc 0:1 uuid\0" \
- BOOTENV
-
-#endif /* __RIOTBOARD_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 61/93] arm: Remove mx6sabresd board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (59 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 60/93] arm: Remove marsboard board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 23:58 ` Peng Fan
2018-11-19 15:53 ` [U-Boot] [PATCH 62/93] arm: Remove dh_imx6 board Simon Glass
` (36 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/freescale/mx6sabresd/Kconfig | 12 -
board/freescale/mx6sabresd/MAINTAINERS | 6 -
board/freescale/mx6sabresd/Makefile | 7 -
board/freescale/mx6sabresd/README | 114 ---
board/freescale/mx6sabresd/mx6sabresd.c | 1064 -----------------------
configs/mx6sabresd_defconfig | 75 --
include/configs/mx6sabresd.h | 67 --
8 files changed, 1346 deletions(-)
delete mode 100644 board/freescale/mx6sabresd/Kconfig
delete mode 100644 board/freescale/mx6sabresd/MAINTAINERS
delete mode 100644 board/freescale/mx6sabresd/Makefile
delete mode 100644 board/freescale/mx6sabresd/README
delete mode 100644 board/freescale/mx6sabresd/mx6sabresd.c
delete mode 100644 configs/mx6sabresd_defconfig
delete mode 100644 include/configs/mx6sabresd.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 0859619af3b..e96deadf72d 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -535,7 +535,6 @@ source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6memcal/Kconfig"
-source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sllevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig
deleted file mode 100644
index e87dea0d7a2..00000000000
--- a/board/freescale/mx6sabresd/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6SABRESD
-
-config SYS_BOARD
- default "mx6sabresd"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "mx6sabresd"
-
-endif
diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS
deleted file mode 100644
index 95752619e78..00000000000
--- a/board/freescale/mx6sabresd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX6SABRESD BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/freescale/mx6sabresd/
-F: include/configs/mx6sabresd.h
-F: configs/mx6sabresd_defconfig
diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile
deleted file mode 100644
index 92e1ff72a4f..00000000000
--- a/board/freescale/mx6sabresd/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx6sabresd.o
diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README
deleted file mode 100644
index 4b4df063300..00000000000
--- a/board/freescale/mx6sabresd/README
+++ /dev/null
@@ -1,114 +0,0 @@
-How to use and build U-Boot on mx6sabresd
------------------------------------------
-
-The following methods can be used for booting mx6sabresd boards:
-
-1. Booting from SD card
-
-2. Booting from eMMC
-
-3. Booting via Falcon mode (SPL launches the kernel directly)
-
-
-1. Booting from SD card via SPL
--------------------------------
-
-mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
-
-In order to build it:
-
-$ make mx6sabresd_defconfig
-
-$ make
-
-This will generate the SPL and u-boot.img binaries.
-
-- Flash the SPL binary into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-
-- Flash the u-boot.img binary into the SD card:
-
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
-
-
-2. Booting from eMMC
---------------------
-
-$ make mx6sabresd_defconfig
-
-$ make
-
-This will generate the SPL and u-boot.img binaries.
-
-- Boot first from SD card as shown in the previous section
-
-In U-boot change the eMMC partition config:
-
-=> mmc partconf 2 1 0 0
-
-Mount the eMMC in the host PC:
-
-=> ums 0 mmc 2
-
-- Flash SPL and u-boot.img binaries into the eMMC:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
-
-Set SW6 to eMMC 8-bit boot: 11010110
-
-
-3. Booting via Falcon mode
---------------------------
-
-$ make mx6sabresd_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the SD card:
-
-$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
-
-- Flash the u-boot.img image into the SD card:
-
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
-
-Create a partition for root file system and extract it there:
-
-$ sudo tar xvf rootfs.tar.gz -C /media/root
-
-The SD card must have enough space for raw "args" and "kernel".
-To configure Falcon mode for the first time, on U-Boot do the following commands:
-
-- Setup the IP server:
-
-# setenv serverip <server_ip_address>
-
-- Download dtb file:
-
-# dhcp ${fdt_addr} imx6q-sabresd.dtb
-
-- Download kernel image:
-
-# dhcp ${loadaddr} uImage
-
-- Write kernel at 2MB offset:
-
-# mmc write ${loadaddr} 0x1000 0x4000
-
-- Setup kernel bootargs:
-
-# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
-
-- Prepare args:
-
-# spl export fdt ${loadaddr} - ${fdt_addr}
-
-- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
-
-# mmc write 18000000 0x800 0x800
-
-- Press KEY_VOL_UP key, power up the board and then SPL binary will
-launch the kernel directly.
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
deleted file mode 100644
index 0183ede148c..00000000000
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/spi.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <input.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include "../common/pfuze.h"
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC 1
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
-
-#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8031 PHY Reset */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- /* Reset AR8031 PHY */
- gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
- mdelay(10);
- gpio_set_value(IMX_GPIO_NR(1, 25), 1);
- udelay(100);
-}
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
- IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const rgb_pads[] = {
- IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const bl_pads[] = {
- IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void enable_backlight(void)
-{
- SETUP_IOMUX_PADS(bl_pads);
- gpio_direction_output(DISP0_PWR_EN, 1);
-}
-
-static void enable_rgb(struct display_info_t const *dev)
-{
- SETUP_IOMUX_PADS(rgb_pads);
- enable_backlight();
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
- enable_backlight();
-}
-
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static void setup_spi(void)
-{
- SETUP_IOMUX_PADS(ecspi1_pads);
-}
-
-iomux_v3_cfg_t const pcie_pads[] = {
- IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
- IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
-};
-
-static void setup_pcie(void)
-{
- SETUP_IOMUX_PADS(pcie_pads);
-}
-
-iomux_v3_cfg_t const di0_pads[] = {
- IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
- IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
- IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
-
-int board_mmc_get_env_dev(int devno)
-{
- return devno - 1;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- int ret;
- int i;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 SD2
- * mmc1 SD3
- * mmc2 eMMC
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc2_pads);
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc3_pads);
- gpio_direction_input(USDHC3_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 2:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-#else
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x2 SD2
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x2:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x3:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- }
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-#endif
-
-static int ar8031_phy_fixup(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- ar8031_phy_fixup(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static void disable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- int reg = readl(&iomux->gpr[2]);
-
- reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
- IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
-
- writel(reg, &iomux->gpr[2]);
-}
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- disable_lvds(dev);
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {{
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB666,
- .detect = NULL,
- .enable = enable_lvds,
- .mode = {
- .name = "Hannstar-XGA",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15384,
- .left_margin = 160,
- .right_margin = 24,
- .upper_margin = 29,
- .lower_margin = 3,
- .hsync_len = 136,
- .vsync_len = 6,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15384,
- .left_margin = 160,
- .right_margin = 24,
- .upper_margin = 29,
- .lower_margin = 3,
- .hsync_len = 136,
- .vsync_len = 6,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
-} }, {
- .bus = 0,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = NULL,
- .enable = enable_rgb,
- .mode = {
- .name = "SEIKO-WVGA",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 29850,
- .left_margin = 89,
- .right_margin = 164,
- .upper_margin = 23,
- .lower_margin = 10,
- .hsync_len = 10,
- .vsync_len = 10,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int reg;
-
- /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
- SETUP_IOMUX_PADS(di0_pads);
-
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
- writel(reg, &mxc_ccm->CCGR3);
-
- /* set LDB0, LDB1 clk select to 011/011 */
- reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->cs2cdr);
-
- reg = readl(&mxc_ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
- | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
- | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
- | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
- | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
- | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
- setup_pcie();
-
- return cpu_eth_init(bis);
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET 0x800
-#define UCTRL_PWR_POL (1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usb_hc1_pads[] = {
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_usb(void)
-{
- SETUP_IOMUX_PADS(usb_otg_pads);
-
- /*
- * set daisy chain for otg_pin_id on 6q.
- * for 6dl, this bit is reserved
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
-
- SETUP_IOMUX_PADS(usb_hc1_pads);
-}
-
-int board_ehci_hcd_init(int port)
-{
- u32 *usbnc_usb_ctrl;
-
- if (port > 1)
- return -EINVAL;
-
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
-
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
- return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- if (on)
- gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
- else
- gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
- if (is_mx6dq() || is_mx6dqp())
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
- else
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
-#endif
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
-
- return 0;
-}
-
-int power_init_board(void)
-{
- struct pmic *p;
- unsigned int reg;
- int ret;
-
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
-
- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
- return ret;
-
- /* Increase VGEN3 from 2.5 to 2.8V */
- pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
- reg &= ~LDO_VOL_MASK;
- reg |= LDOB_2_80V;
- pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
-
- /* Increase VGEN5 from 2.8 to 3V */
- pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
- reg &= ~LDO_VOL_MASK;
- reg |= LDOB_3_00V;
- pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
-
- return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
-#endif
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- env_set("board_name", "SABRESD");
-
- if (is_mx6dqp())
- env_set("board_rev", "MX6QP");
- else if (is_mx6dq())
- env_set("board_rev", "MX6Q");
- else if (is_mx6sdl())
- env_set("board_rev", "MX6DL");
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: MX6-SabreSD\n");
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-#include <spl.h>
-#include <linux/libfdt.h>
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- gpio_direction_input(KEY_VOL_UP);
-
- /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
- return gpio_get_value(KEY_VOL_UP);
-}
-#endif
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static int mx6q_dcd_table[] = {
- 0x020e0798, 0x000C0000,
- 0x020e0758, 0x00000000,
- 0x020e0588, 0x00000030,
- 0x020e0594, 0x00000030,
- 0x020e056c, 0x00000030,
- 0x020e0578, 0x00000030,
- 0x020e074c, 0x00000030,
- 0x020e057c, 0x00000030,
- 0x020e058c, 0x00000000,
- 0x020e059c, 0x00000030,
- 0x020e05a0, 0x00000030,
- 0x020e078c, 0x00000030,
- 0x020e0750, 0x00020000,
- 0x020e05a8, 0x00000030,
- 0x020e05b0, 0x00000030,
- 0x020e0524, 0x00000030,
- 0x020e051c, 0x00000030,
- 0x020e0518, 0x00000030,
- 0x020e050c, 0x00000030,
- 0x020e05b8, 0x00000030,
- 0x020e05c0, 0x00000030,
- 0x020e0774, 0x00020000,
- 0x020e0784, 0x00000030,
- 0x020e0788, 0x00000030,
- 0x020e0794, 0x00000030,
- 0x020e079c, 0x00000030,
- 0x020e07a0, 0x00000030,
- 0x020e07a4, 0x00000030,
- 0x020e07a8, 0x00000030,
- 0x020e0748, 0x00000030,
- 0x020e05ac, 0x00000030,
- 0x020e05b4, 0x00000030,
- 0x020e0528, 0x00000030,
- 0x020e0520, 0x00000030,
- 0x020e0514, 0x00000030,
- 0x020e0510, 0x00000030,
- 0x020e05bc, 0x00000030,
- 0x020e05c4, 0x00000030,
- 0x021b0800, 0xa1390003,
- 0x021b080c, 0x001F001F,
- 0x021b0810, 0x001F001F,
- 0x021b480c, 0x001F001F,
- 0x021b4810, 0x001F001F,
- 0x021b083c, 0x43270338,
- 0x021b0840, 0x03200314,
- 0x021b483c, 0x431A032F,
- 0x021b4840, 0x03200263,
- 0x021b0848, 0x4B434748,
- 0x021b4848, 0x4445404C,
- 0x021b0850, 0x38444542,
- 0x021b4850, 0x4935493A,
- 0x021b081c, 0x33333333,
- 0x021b0820, 0x33333333,
- 0x021b0824, 0x33333333,
- 0x021b0828, 0x33333333,
- 0x021b481c, 0x33333333,
- 0x021b4820, 0x33333333,
- 0x021b4824, 0x33333333,
- 0x021b4828, 0x33333333,
- 0x021b08b8, 0x00000800,
- 0x021b48b8, 0x00000800,
- 0x021b0004, 0x00020036,
- 0x021b0008, 0x09444040,
- 0x021b000c, 0x555A7975,
- 0x021b0010, 0xFF538F64,
- 0x021b0014, 0x01FF00DB,
- 0x021b0018, 0x00001740,
- 0x021b001c, 0x00008000,
- 0x021b002c, 0x000026d2,
- 0x021b0030, 0x005A1023,
- 0x021b0040, 0x00000027,
- 0x021b0000, 0x831A0000,
- 0x021b001c, 0x04088032,
- 0x021b001c, 0x00008033,
- 0x021b001c, 0x00048031,
- 0x021b001c, 0x09408030,
- 0x021b001c, 0x04008040,
- 0x021b0020, 0x00005800,
- 0x021b0818, 0x00011117,
- 0x021b4818, 0x00011117,
- 0x021b0004, 0x00025576,
- 0x021b0404, 0x00011006,
- 0x021b001c, 0x00000000,
-};
-
-static int mx6qp_dcd_table[] = {
- 0x020e0798, 0x000c0000,
- 0x020e0758, 0x00000000,
- 0x020e0588, 0x00000030,
- 0x020e0594, 0x00000030,
- 0x020e056c, 0x00000030,
- 0x020e0578, 0x00000030,
- 0x020e074c, 0x00000030,
- 0x020e057c, 0x00000030,
- 0x020e058c, 0x00000000,
- 0x020e059c, 0x00000030,
- 0x020e05a0, 0x00000030,
- 0x020e078c, 0x00000030,
- 0x020e0750, 0x00020000,
- 0x020e05a8, 0x00000030,
- 0x020e05b0, 0x00000030,
- 0x020e0524, 0x00000030,
- 0x020e051c, 0x00000030,
- 0x020e0518, 0x00000030,
- 0x020e050c, 0x00000030,
- 0x020e05b8, 0x00000030,
- 0x020e05c0, 0x00000030,
- 0x020e0774, 0x00020000,
- 0x020e0784, 0x00000030,
- 0x020e0788, 0x00000030,
- 0x020e0794, 0x00000030,
- 0x020e079c, 0x00000030,
- 0x020e07a0, 0x00000030,
- 0x020e07a4, 0x00000030,
- 0x020e07a8, 0x00000030,
- 0x020e0748, 0x00000030,
- 0x020e05ac, 0x00000030,
- 0x020e05b4, 0x00000030,
- 0x020e0528, 0x00000030,
- 0x020e0520, 0x00000030,
- 0x020e0514, 0x00000030,
- 0x020e0510, 0x00000030,
- 0x020e05bc, 0x00000030,
- 0x020e05c4, 0x00000030,
- 0x021b0800, 0xa1390003,
- 0x021b080c, 0x001b001e,
- 0x021b0810, 0x002e0029,
- 0x021b480c, 0x001b002a,
- 0x021b4810, 0x0019002c,
- 0x021b083c, 0x43240334,
- 0x021b0840, 0x0324031a,
- 0x021b483c, 0x43340344,
- 0x021b4840, 0x03280276,
- 0x021b0848, 0x44383A3E,
- 0x021b4848, 0x3C3C3846,
- 0x021b0850, 0x2e303230,
- 0x021b4850, 0x38283E34,
- 0x021b081c, 0x33333333,
- 0x021b0820, 0x33333333,
- 0x021b0824, 0x33333333,
- 0x021b0828, 0x33333333,
- 0x021b481c, 0x33333333,
- 0x021b4820, 0x33333333,
- 0x021b4824, 0x33333333,
- 0x021b4828, 0x33333333,
- 0x021b08c0, 0x24912249,
- 0x021b48c0, 0x24914289,
- 0x021b08b8, 0x00000800,
- 0x021b48b8, 0x00000800,
- 0x021b0004, 0x00020036,
- 0x021b0008, 0x24444040,
- 0x021b000c, 0x555A7955,
- 0x021b0010, 0xFF320F64,
- 0x021b0014, 0x01ff00db,
- 0x021b0018, 0x00001740,
- 0x021b001c, 0x00008000,
- 0x021b002c, 0x000026d2,
- 0x021b0030, 0x005A1023,
- 0x021b0040, 0x00000027,
- 0x021b0400, 0x14420000,
- 0x021b0000, 0x831A0000,
- 0x021b0890, 0x00400C58,
- 0x00bb0008, 0x00000000,
- 0x00bb000c, 0x2891E41A,
- 0x00bb0038, 0x00000564,
- 0x00bb0014, 0x00000040,
- 0x00bb0028, 0x00000020,
- 0x00bb002c, 0x00000020,
- 0x021b001c, 0x04088032,
- 0x021b001c, 0x00008033,
- 0x021b001c, 0x00048031,
- 0x021b001c, 0x09408030,
- 0x021b001c, 0x04008040,
- 0x021b0020, 0x00005800,
- 0x021b0818, 0x00011117,
- 0x021b4818, 0x00011117,
- 0x021b0004, 0x00025576,
- 0x021b0404, 0x00011006,
- 0x021b001c, 0x00000000,
-};
-
-static int mx6dl_dcd_table[] = {
- 0x020e0774, 0x000C0000,
- 0x020e0754, 0x00000000,
- 0x020e04ac, 0x00000030,
- 0x020e04b0, 0x00000030,
- 0x020e0464, 0x00000030,
- 0x020e0490, 0x00000030,
- 0x020e074c, 0x00000030,
- 0x020e0494, 0x00000030,
- 0x020e04a0, 0x00000000,
- 0x020e04b4, 0x00000030,
- 0x020e04b8, 0x00000030,
- 0x020e076c, 0x00000030,
- 0x020e0750, 0x00020000,
- 0x020e04bc, 0x00000030,
- 0x020e04c0, 0x00000030,
- 0x020e04c4, 0x00000030,
- 0x020e04c8, 0x00000030,
- 0x020e04cc, 0x00000030,
- 0x020e04d0, 0x00000030,
- 0x020e04d4, 0x00000030,
- 0x020e04d8, 0x00000030,
- 0x020e0760, 0x00020000,
- 0x020e0764, 0x00000030,
- 0x020e0770, 0x00000030,
- 0x020e0778, 0x00000030,
- 0x020e077c, 0x00000030,
- 0x020e0780, 0x00000030,
- 0x020e0784, 0x00000030,
- 0x020e078c, 0x00000030,
- 0x020e0748, 0x00000030,
- 0x020e0470, 0x00000030,
- 0x020e0474, 0x00000030,
- 0x020e0478, 0x00000030,
- 0x020e047c, 0x00000030,
- 0x020e0480, 0x00000030,
- 0x020e0484, 0x00000030,
- 0x020e0488, 0x00000030,
- 0x020e048c, 0x00000030,
- 0x021b0800, 0xa1390003,
- 0x021b080c, 0x001F001F,
- 0x021b0810, 0x001F001F,
- 0x021b480c, 0x001F001F,
- 0x021b4810, 0x001F001F,
- 0x021b083c, 0x4220021F,
- 0x021b0840, 0x0207017E,
- 0x021b483c, 0x4201020C,
- 0x021b4840, 0x01660172,
- 0x021b0848, 0x4A4D4E4D,
- 0x021b4848, 0x4A4F5049,
- 0x021b0850, 0x3F3C3D31,
- 0x021b4850, 0x3238372B,
- 0x021b081c, 0x33333333,
- 0x021b0820, 0x33333333,
- 0x021b0824, 0x33333333,
- 0x021b0828, 0x33333333,
- 0x021b481c, 0x33333333,
- 0x021b4820, 0x33333333,
- 0x021b4824, 0x33333333,
- 0x021b4828, 0x33333333,
- 0x021b08b8, 0x00000800,
- 0x021b48b8, 0x00000800,
- 0x021b0004, 0x0002002D,
- 0x021b0008, 0x00333030,
- 0x021b000c, 0x3F435313,
- 0x021b0010, 0xB66E8B63,
- 0x021b0014, 0x01FF00DB,
- 0x021b0018, 0x00001740,
- 0x021b001c, 0x00008000,
- 0x021b002c, 0x000026d2,
- 0x021b0030, 0x00431023,
- 0x021b0040, 0x00000027,
- 0x021b0000, 0x831A0000,
- 0x021b001c, 0x04008032,
- 0x021b001c, 0x00008033,
- 0x021b001c, 0x00048031,
- 0x021b001c, 0x05208030,
- 0x021b001c, 0x04008040,
- 0x021b0020, 0x00005800,
- 0x021b0818, 0x00011117,
- 0x021b4818, 0x00011117,
- 0x021b0004, 0x0002556D,
- 0x021b0404, 0x00011006,
- 0x021b001c, 0x00000000,
-};
-
-static void ddr_init(int *table, int size)
-{
- int i;
-
- for (i = 0; i < size / 2 ; i++)
- writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
- if (is_mx6dq())
- ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
- else if (is_mx6dqp())
- ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
- else if (is_mx6sdl())
- ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
-}
-
-void board_init_f(ulong dummy)
-{
- /* DDR initialization */
- spl_dram_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
deleted file mode 100644
index e0202ef57db..00000000000
--- a/configs/mx6sabresd_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6SABRESD=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FASTBOOT_BUF_SIZE=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=2
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
deleted file mode 100644
index 555942a2c2a..00000000000
--- a/include/configs/mx6sabresd.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Freescale i.MX6Q SabreSD board.
- */
-
-#ifndef __MX6SABRESD_CONFIG_H
-#define __MX6SABRESD_CONFIG_H
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_MACH_TYPE 3980
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONSOLE_DEV "ttymxc0"
-
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
-#include "mx6sabre_common.h"
-
-/* Falcon Mode */
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
-
-/* Falcon Mode - MMC support: args at 1MB kernel@2MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
-
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
-#endif
-
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
-#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
-#endif
-
-#endif /* __MX6SABRESD_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 61/93] arm: Remove mx6sabresd board
2018-11-19 15:53 ` [U-Boot] [PATCH 61/93] arm: Remove mx6sabresd board Simon Glass
@ 2018-11-19 23:58 ` Peng Fan
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Peng Fan @ 2018-11-19 23:58 UTC (permalink / raw)
To: u-boot
Hi Simon,
Please not remove this board, we will work to support DM_BLK.
Thanks,
Peng.
> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Simon
> Glass
> Sent: 2018年11月19日 23:54
> To: U-Boot Mailing List <u-boot@lists.denx.de>
> Cc: Peter Howard <phoward@gme.net.au>; Marcus Cooper
> <codekipper@gmail.com>; Icenowy Zheng <icenowy@aosc.xyz>; Stefan
> Roese <sr@denx.de>; Chander Kashyap <k.chander@samsung.com>; Tom
> Rini <trini@konsulko.com>; Akshay Saraswat <akshay.s@samsung.com>;
> Sumit Garg <sumit.garg@nxp.com>; egnite GmbH <info@egnite.de>; Rask
> Ingemann Lambertsen <rask@formelder.dk>; Ian Campbell
> <ijc@hellion.org.uk>; Feng Li <feng.li_2@nxp.com>; Alison Wang
> <alison.wang@nxp.com>; Vitaly Andrianov <vitalya@ti.com>; Jelle van der
> Waa <jelle@vdwaa.nl>; Hans de Goede <hdegoede@redhat.com>; Roger
> Meier <r.meier@siemens.com>; Zoltan Herpai <wigyori@uid0.hu>; Gregory
> CLEMENT <gregory.clement@free-electrons.com>; Stefan Mavrodiev
> <stefan.mavrodiev@gmail.com>; Aleksei Mamlin <mamlinav@gmail.com>;
> Priit Laes <plaes@plaes.org>; Stelian Pop <stelian@popies.net>; Pavel
> Machek <pavel@denx.de>; Quentin Schulz
> <quentin.schulz@free-electrons.com>; Fabio Estevam
> <fabio.estevam@nxp.com>; Jelle de Jong <jelledejong@powercraft.nl>
> Subject: [U-Boot] [PATCH 61/93] arm: Remove mx6sabresd board
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-imx/mx6/Kconfig | 1 -
> board/freescale/mx6sabresd/Kconfig | 12 -
> board/freescale/mx6sabresd/MAINTAINERS | 6 -
> board/freescale/mx6sabresd/Makefile | 7 -
> board/freescale/mx6sabresd/README | 114 ---
> board/freescale/mx6sabresd/mx6sabresd.c | 1064 -----------------------
> configs/mx6sabresd_defconfig | 75 --
> include/configs/mx6sabresd.h | 67 --
> 8 files changed, 1346 deletions(-)
> delete mode 100644 board/freescale/mx6sabresd/Kconfig
> delete mode 100644 board/freescale/mx6sabresd/MAINTAINERS
> delete mode 100644 board/freescale/mx6sabresd/Makefile
> delete mode 100644 board/freescale/mx6sabresd/README delete mode
> 100644 board/freescale/mx6sabresd/mx6sabresd.c
> delete mode 100644 configs/mx6sabresd_defconfig delete mode 100644
> include/configs/mx6sabresd.h
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig
> b/arch/arm/mach-imx/mx6/Kconfig index 0859619af3b..e96deadf72d
> 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -535,7 +535,6 @@ source "board/engicam/imx6q/Kconfig"
> source "board/engicam/imx6ul/Kconfig"
> source "board/freescale/mx6qarm2/Kconfig"
> source "board/freescale/mx6memcal/Kconfig"
> -source "board/freescale/mx6sabresd/Kconfig"
> source "board/freescale/mx6slevk/Kconfig"
> source "board/freescale/mx6sllevk/Kconfig"
> source "board/freescale/mx6sxsabresd/Kconfig"
> diff --git a/board/freescale/mx6sabresd/Kconfig
> b/board/freescale/mx6sabresd/Kconfig
> deleted file mode 100644
> index e87dea0d7a2..00000000000
> --- a/board/freescale/mx6sabresd/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MX6SABRESD
> -
> -config SYS_BOARD
> - default "mx6sabresd"
> -
> -config SYS_VENDOR
> - default "freescale"
> -
> -config SYS_CONFIG_NAME
> - default "mx6sabresd"
> -
> -endif
> diff --git a/board/freescale/mx6sabresd/MAINTAINERS
> b/board/freescale/mx6sabresd/MAINTAINERS
> deleted file mode 100644
> index 95752619e78..00000000000
> --- a/board/freescale/mx6sabresd/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MX6SABRESD BOARD
> -M: Fabio Estevam <fabio.estevam@nxp.com>
> -S: Maintained
> -F: board/freescale/mx6sabresd/
> -F: include/configs/mx6sabresd.h
> -F: configs/mx6sabresd_defconfig
> diff --git a/board/freescale/mx6sabresd/Makefile
> b/board/freescale/mx6sabresd/Makefile
> deleted file mode 100644
> index 92e1ff72a4f..00000000000
> --- a/board/freescale/mx6sabresd/Makefile
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C)
> Copyright 2011 Freescale Semiconductor, Inc.
> -
> -obj-y := mx6sabresd.o
> diff --git a/board/freescale/mx6sabresd/README
> b/board/freescale/mx6sabresd/README
> deleted file mode 100644
> index 4b4df063300..00000000000
> --- a/board/freescale/mx6sabresd/README
> +++ /dev/null
> @@ -1,114 +0,0 @@
> -How to use and build U-Boot on mx6sabresd
> ------------------------------------------
> -
> -The following methods can be used for booting mx6sabresd boards:
> -
> -1. Booting from SD card
> -
> -2. Booting from eMMC
> -
> -3. Booting via Falcon mode (SPL launches the kernel directly)
> -
> -
> -1. Booting from SD card via SPL
> --------------------------------
> -
> -mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
> -
> -In order to build it:
> -
> -$ make mx6sabresd_defconfig
> -
> -$ make
> -
> -This will generate the SPL and u-boot.img binaries.
> -
> -- Flash the SPL binary into the SD card:
> -
> -$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
> -
> -- Flash the u-boot.img binary into the SD card:
> -
> -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
> -
> -
> -2. Booting from eMMC
> ---------------------
> -
> -$ make mx6sabresd_defconfig
> -
> -$ make
> -
> -This will generate the SPL and u-boot.img binaries.
> -
> -- Boot first from SD card as shown in the previous section
> -
> -In U-boot change the eMMC partition config:
> -
> -=> mmc partconf 2 1 0 0
> -
> -Mount the eMMC in the host PC:
> -
> -=> ums 0 mmc 2
> -
> -- Flash SPL and u-boot.img binaries into the eMMC:
> -
> -$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync -$ sudo dd if=u-boot.img
> of=/dev/sdX bs=1K seek=69 && sync
> -
> -Set SW6 to eMMC 8-bit boot: 11010110
> -
> -
> -3. Booting via Falcon mode
> ---------------------------
> -
> -$ make mx6sabresd_defconfig
> -$ make
> -
> -This will generate the SPL image called SPL and the u-boot.img.
> -
> -- Flash the SPL image into the SD card:
> -
> -$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
> -
> -- Flash the u-boot.img image into the SD card:
> -
> -$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none
> && sync
> -
> -Create a partition for root file system and extract it there:
> -
> -$ sudo tar xvf rootfs.tar.gz -C /media/root
> -
> -The SD card must have enough space for raw "args" and "kernel".
> -To configure Falcon mode for the first time, on U-Boot do the following
> commands:
> -
> -- Setup the IP server:
> -
> -# setenv serverip <server_ip_address>
> -
> -- Download dtb file:
> -
> -# dhcp ${fdt_addr} imx6q-sabresd.dtb
> -
> -- Download kernel image:
> -
> -# dhcp ${loadaddr} uImage
> -
> -- Write kernel at 2MB offset:
> -
> -# mmc write ${loadaddr} 0x1000 0x4000
> -
> -- Setup kernel bootargs:
> -
> -# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1
> rootfstype=ext4 rootwait quiet rw"
> -
> -- Prepare args:
> -
> -# spl export fdt ${loadaddr} - ${fdt_addr}
> -
> -- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
> -
> -# mmc write 18000000 0x800 0x800
> -
> -- Press KEY_VOL_UP key, power up the board and then SPL binary will
> -launch the kernel directly.
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
> b/board/freescale/mx6sabresd/mx6sabresd.c
> deleted file mode 100644
> index 0183ede148c..00000000000
> --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ /dev/null
> @@ -1,1064 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2012 Freescale Semiconductor, Inc.
> - *
> - * Author: Fabio Estevam <fabio.estevam@freescale.com>
> - */
> -
> -#include <asm/arch/clock.h>
> -#include <asm/arch/imx-regs.h>
> -#include <asm/arch/iomux.h>
> -#include <asm/arch/mx6-pins.h>
> -#include <asm/mach-imx/spi.h>
> -#include <linux/errno.h>
> -#include <asm/gpio.h>
> -#include <asm/mach-imx/mxc_i2c.h>
> -#include <asm/mach-imx/iomux-v3.h>
> -#include <asm/mach-imx/boot_mode.h>
> -#include <asm/mach-imx/video.h>
> -#include <mmc.h>
> -#include <fsl_esdhc.h>
> -#include <miiphy.h>
> -#include <netdev.h>
> -#include <asm/arch/mxc_hdmi.h>
> -#include <asm/arch/crm_regs.h>
> -#include <asm/io.h>
> -#include <asm/arch/sys_proto.h>
> -#include <i2c.h>
> -#include <input.h>
> -#include <power/pmic.h>
> -#include <power/pfuze100_pmic.h>
> -#include "../common/pfuze.h"
> -#include <usb.h>
> -#include <usb/ehci-ci.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
> - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> -
> -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
> - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> -
> -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> - PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> -
> -#define I2C_PMIC 1
> -
> -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
> -
> -#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
> -
> -#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
> -
> -int dram_init(void)
> -{
> - gd->ram_size = imx_ddr_size();
> - return 0;
> -}
> -
> -static iomux_v3_cfg_t const uart1_pads[] = {
> - IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA |
> MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA |
> MUX_PAD_CTRL(UART_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const enet_pads[] = {
> - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
> MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* AR8031 PHY Reset */
> - IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_enet(void)
> -{
> - SETUP_IOMUX_PADS(enet_pads);
> -
> - /* Reset AR8031 PHY */
> - gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
> - mdelay(10);
> - gpio_set_value(IMX_GPIO_NR(1, 25), 1);
> - udelay(100);
> -}
> -
> -static iomux_v3_cfg_t const usdhc2_pads[] = {
> - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 |
> MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
> -};
> -
> -static iomux_v3_cfg_t const usdhc3_pads[] = {
> - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 |
> MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
> -};
> -
> -static iomux_v3_cfg_t const usdhc4_pads[] = {
> - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 |
> MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const ecspi1_pads[] = {
> - IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK |
> MUX_PAD_CTRL(SPI_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO |
> MUX_PAD_CTRL(SPI_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI |
> MUX_PAD_CTRL(SPI_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const rgb_pads[] = {
> - IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const bl_pads[] = {
> - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void enable_backlight(void)
> -{
> - SETUP_IOMUX_PADS(bl_pads);
> - gpio_direction_output(DISP0_PWR_EN, 1);
> -}
> -
> -static void enable_rgb(struct display_info_t const *dev) -{
> - SETUP_IOMUX_PADS(rgb_pads);
> - enable_backlight();
> -}
> -
> -static void enable_lvds(struct display_info_t const *dev) -{
> - enable_backlight();
> -}
> -
> -static struct i2c_pads_info mx6q_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
> - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 12)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
> - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
> - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 12)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
> - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -static void setup_spi(void)
> -{
> - SETUP_IOMUX_PADS(ecspi1_pads);
> -}
> -
> -iomux_v3_cfg_t const pcie_pads[] = {
> - IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 |
> MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
> - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 |
> MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
> -};
> -
> -static void setup_pcie(void)
> -{
> - SETUP_IOMUX_PADS(pcie_pads);
> -}
> -
> -iomux_v3_cfg_t const di0_pads[] = {
> - IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /*
> DISP0_CLK */
> - IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /*
> DISP0_HSYNC */
> - IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /*
> DISP0_VSYNC */
> -};
> -
> -static void setup_iomux_uart(void)
> -{
> - SETUP_IOMUX_PADS(uart1_pads);
> -}
> -
> -#ifdef CONFIG_FSL_ESDHC
> -struct fsl_esdhc_cfg usdhc_cfg[3] = {
> - {USDHC2_BASE_ADDR},
> - {USDHC3_BASE_ADDR},
> - {USDHC4_BASE_ADDR},
> -};
> -
> -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
> -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
> -
> -int board_mmc_get_env_dev(int devno)
> -{
> - return devno - 1;
> -}
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> - int ret = 0;
> -
> - switch (cfg->esdhc_base) {
> - case USDHC2_BASE_ADDR:
> - ret = !gpio_get_value(USDHC2_CD_GPIO);
> - break;
> - case USDHC3_BASE_ADDR:
> - ret = !gpio_get_value(USDHC3_CD_GPIO);
> - break;
> - case USDHC4_BASE_ADDR:
> - ret = 1; /* eMMC/uSDHC4 is always present */
> - break;
> - }
> -
> - return ret;
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> -#ifndef CONFIG_SPL_BUILD
> - int ret;
> - int i;
> -
> - /*
> - * According to the board_mmc_init() the following map is done:
> - * (U-Boot device node) (Physical Port)
> - * mmc0 SD2
> - * mmc1 SD3
> - * mmc2 eMMC
> - */
> - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> - switch (i) {
> - case 0:
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - gpio_direction_input(USDHC2_CD_GPIO);
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - break;
> - case 1:
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - gpio_direction_input(USDHC3_CD_GPIO);
> - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - break;
> - case 2:
> - SETUP_IOMUX_PADS(usdhc4_pads);
> - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> - break;
> - default:
> - printf("Warning: you configured more USDHC controllers"
> - "(%d) then supported by the board (%d)\n",
> - i + 1, CONFIG_SYS_FSL_USDHC_NUM);
> - return -EINVAL;
> - }
> -
> - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -#else
> - struct src *psrc = (struct src *)SRC_BASE_ADDR;
> - unsigned reg = readl(&psrc->sbmr1) >> 11;
> - /*
> - * Upon reading BOOT_CFG register the following map is done:
> - * Bit 11 and 12 of BOOT_CFG register can determine the current
> - * mmc port
> - * 0x1 SD1
> - * 0x2 SD2
> - * 0x3 SD4
> - */
> -
> - switch (reg & 0x3) {
> - case 0x1:
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> - break;
> - case 0x2:
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> - break;
> - case 0x3:
> - SETUP_IOMUX_PADS(usdhc4_pads);
> - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> - break;
> - }
> -
> - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> -#endif
> -}
> -#endif
> -
> -static int ar8031_phy_fixup(struct phy_device *phydev) -{
> - unsigned short val;
> -
> - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> -
> - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> - val &= 0xffe3;
> - val |= 0x18;
> - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
> -
> - /* introduce tx clock delay */
> - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
> - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
> - val |= 0x0100;
> - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
> -
> - return 0;
> -}
> -
> -int board_phy_config(struct phy_device *phydev) -{
> - ar8031_phy_fixup(phydev);
> -
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_VIDEO_IPUV3)
> -static void disable_lvds(struct display_info_t const *dev) -{
> - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> -
> - int reg = readl(&iomux->gpr[2]);
> -
> - reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
> - IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
> -
> - writel(reg, &iomux->gpr[2]);
> -}
> -
> -static void do_enable_hdmi(struct display_info_t const *dev) -{
> - disable_lvds(dev);
> - imx_enable_hdmi_phy();
> -}
> -
> -struct display_info_t const displays[] = {{
> - .bus = -1,
> - .addr = 0,
> - .pixfmt = IPU_PIX_FMT_RGB666,
> - .detect = NULL,
> - .enable = enable_lvds,
> - .mode = {
> - .name = "Hannstar-XGA",
> - .refresh = 60,
> - .xres = 1024,
> - .yres = 768,
> - .pixclock = 15384,
> - .left_margin = 160,
> - .right_margin = 24,
> - .upper_margin = 29,
> - .lower_margin = 3,
> - .hsync_len = 136,
> - .vsync_len = 6,
> - .sync = FB_SYNC_EXT,
> - .vmode = FB_VMODE_NONINTERLACED
> -} }, {
> - .bus = -1,
> - .addr = 0,
> - .pixfmt = IPU_PIX_FMT_RGB24,
> - .detect = detect_hdmi,
> - .enable = do_enable_hdmi,
> - .mode = {
> - .name = "HDMI",
> - .refresh = 60,
> - .xres = 1024,
> - .yres = 768,
> - .pixclock = 15384,
> - .left_margin = 160,
> - .right_margin = 24,
> - .upper_margin = 29,
> - .lower_margin = 3,
> - .hsync_len = 136,
> - .vsync_len = 6,
> - .sync = FB_SYNC_EXT,
> - .vmode = FB_VMODE_NONINTERLACED
> -} }, {
> - .bus = 0,
> - .addr = 0,
> - .pixfmt = IPU_PIX_FMT_RGB24,
> - .detect = NULL,
> - .enable = enable_rgb,
> - .mode = {
> - .name = "SEIKO-WVGA",
> - .refresh = 60,
> - .xres = 800,
> - .yres = 480,
> - .pixclock = 29850,
> - .left_margin = 89,
> - .right_margin = 164,
> - .upper_margin = 23,
> - .lower_margin = 10,
> - .hsync_len = 10,
> - .vsync_len = 10,
> - .sync = 0,
> - .vmode = FB_VMODE_NONINTERLACED
> -} } };
> -size_t display_count = ARRAY_SIZE(displays);
> -
> -static void setup_display(void)
> -{
> - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg
> *)CCM_BASE_ADDR;
> - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> - int reg;
> -
> - /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
> - SETUP_IOMUX_PADS(di0_pads);
> -
> - enable_ipu_clock();
> - imx_setup_hdmi();
> -
> - /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
> - reg = readl(&mxc_ccm->CCGR3);
> - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK |
> MXC_CCM_CCGR3_LDB_DI1_MASK;
> - writel(reg, &mxc_ccm->CCGR3);
> -
> - /* set LDB0, LDB1 clk select to 011/011 */
> - reg = readl(&mxc_ccm->cs2cdr);
> - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
> - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
> - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
> - | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
> - writel(reg, &mxc_ccm->cs2cdr);
> -
> - reg = readl(&mxc_ccm->cscmr2);
> - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
> MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
> - writel(reg, &mxc_ccm->cscmr2);
> -
> - reg = readl(&mxc_ccm->chsccdr);
> - reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
> - reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> - << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
> - writel(reg, &mxc_ccm->chsccdr);
> -
> - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
> - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
> - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
> - | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
> - | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
> - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
> - | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
> - | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
> - | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
> - writel(reg, &iomux->gpr[2]);
> -
> - reg = readl(&iomux->gpr[3]);
> - reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
> - | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
> - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
> - << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
> - writel(reg, &iomux->gpr[3]);
> -}
> -#endif /* CONFIG_VIDEO_IPUV3 */
> -
> -/*
> - * Do not overwrite the console
> - * Use always serial for U-Boot console
> - */
> -int overwrite_console(void)
> -{
> - return 1;
> -}
> -
> -int board_eth_init(bd_t *bis)
> -{
> - setup_iomux_enet();
> - setup_pcie();
> -
> - return cpu_eth_init(bis);
> -}
> -
> -#ifdef CONFIG_USB_EHCI_MX6
> -#define USB_OTHERREGS_OFFSET 0x800
> -#define UCTRL_PWR_POL (1 << 9)
> -
> -static iomux_v3_cfg_t const usb_otg_pads[] = {
> - IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const usb_hc1_pads[] = {
> - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 |
> MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void setup_usb(void)
> -{
> - SETUP_IOMUX_PADS(usb_otg_pads);
> -
> - /*
> - * set daisy chain for otg_pin_id on 6q.
> - * for 6dl, this bit is reserved
> - */
> - imx_iomux_set_gpr_register(1, 13, 1, 0);
> -
> - SETUP_IOMUX_PADS(usb_hc1_pads);
> -}
> -
> -int board_ehci_hcd_init(int port)
> -{
> - u32 *usbnc_usb_ctrl;
> -
> - if (port > 1)
> - return -EINVAL;
> -
> - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET
> +
> - port * 4);
> -
> - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
> -
> - return 0;
> -}
> -
> -int board_ehci_power(int port, int on)
> -{
> - switch (port) {
> - case 0:
> - break;
> - case 1:
> - if (on)
> - gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
> - else
> - gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
> - break;
> - default:
> - printf("MXC USB port %d not yet supported\n", port);
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -#endif
> -
> -int board_early_init_f(void)
> -{
> - setup_iomux_uart();
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* address of boot parameters */
> - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> -
> -#ifdef CONFIG_MXC_SPI
> - setup_spi();
> -#endif
> - if (is_mx6dq() || is_mx6dqp())
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
> - else
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f,
> &mx6dl_i2c_pad_info1);
> -#if defined(CONFIG_VIDEO_IPUV3)
> - setup_display();
> -#endif
> -#ifdef CONFIG_USB_EHCI_MX6
> - setup_usb();
> -#endif
> -
> - return 0;
> -}
> -
> -int power_init_board(void)
> -{
> - struct pmic *p;
> - unsigned int reg;
> - int ret;
> -
> - p = pfuze_common_init(I2C_PMIC);
> - if (!p)
> - return -ENODEV;
> -
> - ret = pfuze_mode_init(p, APS_PFM);
> - if (ret < 0)
> - return ret;
> -
> - /* Increase VGEN3 from 2.5 to 2.8V */
> - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
> - reg &= ~LDO_VOL_MASK;
> - reg |= LDOB_2_80V;
> - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
> -
> - /* Increase VGEN5 from 2.8 to 3V */
> - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
> - reg &= ~LDO_VOL_MASK;
> - reg |= LDOB_3_00V;
> - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_MXC_SPI
> -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{
> - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
> -}
> -#endif
> -
> -#ifdef CONFIG_CMD_BMODE
> -static const struct boot_mode board_boot_modes[] = {
> - /* 4 bit bus width */
> - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> - {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> - /* 8 bit bus width */
> - {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
> - {NULL, 0},
> -};
> -#endif
> -
> -int board_late_init(void)
> -{
> -#ifdef CONFIG_CMD_BMODE
> - add_board_boot_modes(board_boot_modes);
> -#endif
> -
> -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> - env_set("board_name", "SABRESD");
> -
> - if (is_mx6dqp())
> - env_set("board_rev", "MX6QP");
> - else if (is_mx6dq())
> - env_set("board_rev", "MX6Q");
> - else if (is_mx6sdl())
> - env_set("board_rev", "MX6DL");
> -#endif
> -
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - puts("Board: MX6-SabreSD\n");
> - return 0;
> -}
> -
> -#ifdef CONFIG_SPL_BUILD
> -#include <asm/arch/mx6-ddr.h>
> -#include <spl.h>
> -#include <linux/libfdt.h>
> -
> -#ifdef CONFIG_SPL_OS_BOOT
> -int spl_start_uboot(void)
> -{
> - gpio_direction_input(KEY_VOL_UP);
> -
> - /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
> - return gpio_get_value(KEY_VOL_UP);
> -}
> -#endif
> -
> -static void ccgr_init(void)
> -{
> - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -
> - writel(0x00C03F3F, &ccm->CCGR0);
> - writel(0x0030FC03, &ccm->CCGR1);
> - writel(0x0FFFC000, &ccm->CCGR2);
> - writel(0x3FF00000, &ccm->CCGR3);
> - writel(0x00FFF300, &ccm->CCGR4);
> - writel(0x0F0000C3, &ccm->CCGR5);
> - writel(0x000003FF, &ccm->CCGR6);
> -}
> -
> -static int mx6q_dcd_table[] = {
> - 0x020e0798, 0x000C0000,
> - 0x020e0758, 0x00000000,
> - 0x020e0588, 0x00000030,
> - 0x020e0594, 0x00000030,
> - 0x020e056c, 0x00000030,
> - 0x020e0578, 0x00000030,
> - 0x020e074c, 0x00000030,
> - 0x020e057c, 0x00000030,
> - 0x020e058c, 0x00000000,
> - 0x020e059c, 0x00000030,
> - 0x020e05a0, 0x00000030,
> - 0x020e078c, 0x00000030,
> - 0x020e0750, 0x00020000,
> - 0x020e05a8, 0x00000030,
> - 0x020e05b0, 0x00000030,
> - 0x020e0524, 0x00000030,
> - 0x020e051c, 0x00000030,
> - 0x020e0518, 0x00000030,
> - 0x020e050c, 0x00000030,
> - 0x020e05b8, 0x00000030,
> - 0x020e05c0, 0x00000030,
> - 0x020e0774, 0x00020000,
> - 0x020e0784, 0x00000030,
> - 0x020e0788, 0x00000030,
> - 0x020e0794, 0x00000030,
> - 0x020e079c, 0x00000030,
> - 0x020e07a0, 0x00000030,
> - 0x020e07a4, 0x00000030,
> - 0x020e07a8, 0x00000030,
> - 0x020e0748, 0x00000030,
> - 0x020e05ac, 0x00000030,
> - 0x020e05b4, 0x00000030,
> - 0x020e0528, 0x00000030,
> - 0x020e0520, 0x00000030,
> - 0x020e0514, 0x00000030,
> - 0x020e0510, 0x00000030,
> - 0x020e05bc, 0x00000030,
> - 0x020e05c4, 0x00000030,
> - 0x021b0800, 0xa1390003,
> - 0x021b080c, 0x001F001F,
> - 0x021b0810, 0x001F001F,
> - 0x021b480c, 0x001F001F,
> - 0x021b4810, 0x001F001F,
> - 0x021b083c, 0x43270338,
> - 0x021b0840, 0x03200314,
> - 0x021b483c, 0x431A032F,
> - 0x021b4840, 0x03200263,
> - 0x021b0848, 0x4B434748,
> - 0x021b4848, 0x4445404C,
> - 0x021b0850, 0x38444542,
> - 0x021b4850, 0x4935493A,
> - 0x021b081c, 0x33333333,
> - 0x021b0820, 0x33333333,
> - 0x021b0824, 0x33333333,
> - 0x021b0828, 0x33333333,
> - 0x021b481c, 0x33333333,
> - 0x021b4820, 0x33333333,
> - 0x021b4824, 0x33333333,
> - 0x021b4828, 0x33333333,
> - 0x021b08b8, 0x00000800,
> - 0x021b48b8, 0x00000800,
> - 0x021b0004, 0x00020036,
> - 0x021b0008, 0x09444040,
> - 0x021b000c, 0x555A7975,
> - 0x021b0010, 0xFF538F64,
> - 0x021b0014, 0x01FF00DB,
> - 0x021b0018, 0x00001740,
> - 0x021b001c, 0x00008000,
> - 0x021b002c, 0x000026d2,
> - 0x021b0030, 0x005A1023,
> - 0x021b0040, 0x00000027,
> - 0x021b0000, 0x831A0000,
> - 0x021b001c, 0x04088032,
> - 0x021b001c, 0x00008033,
> - 0x021b001c, 0x00048031,
> - 0x021b001c, 0x09408030,
> - 0x021b001c, 0x04008040,
> - 0x021b0020, 0x00005800,
> - 0x021b0818, 0x00011117,
> - 0x021b4818, 0x00011117,
> - 0x021b0004, 0x00025576,
> - 0x021b0404, 0x00011006,
> - 0x021b001c, 0x00000000,
> -};
> -
> -static int mx6qp_dcd_table[] = {
> - 0x020e0798, 0x000c0000,
> - 0x020e0758, 0x00000000,
> - 0x020e0588, 0x00000030,
> - 0x020e0594, 0x00000030,
> - 0x020e056c, 0x00000030,
> - 0x020e0578, 0x00000030,
> - 0x020e074c, 0x00000030,
> - 0x020e057c, 0x00000030,
> - 0x020e058c, 0x00000000,
> - 0x020e059c, 0x00000030,
> - 0x020e05a0, 0x00000030,
> - 0x020e078c, 0x00000030,
> - 0x020e0750, 0x00020000,
> - 0x020e05a8, 0x00000030,
> - 0x020e05b0, 0x00000030,
> - 0x020e0524, 0x00000030,
> - 0x020e051c, 0x00000030,
> - 0x020e0518, 0x00000030,
> - 0x020e050c, 0x00000030,
> - 0x020e05b8, 0x00000030,
> - 0x020e05c0, 0x00000030,
> - 0x020e0774, 0x00020000,
> - 0x020e0784, 0x00000030,
> - 0x020e0788, 0x00000030,
> - 0x020e0794, 0x00000030,
> - 0x020e079c, 0x00000030,
> - 0x020e07a0, 0x00000030,
> - 0x020e07a4, 0x00000030,
> - 0x020e07a8, 0x00000030,
> - 0x020e0748, 0x00000030,
> - 0x020e05ac, 0x00000030,
> - 0x020e05b4, 0x00000030,
> - 0x020e0528, 0x00000030,
> - 0x020e0520, 0x00000030,
> - 0x020e0514, 0x00000030,
> - 0x020e0510, 0x00000030,
> - 0x020e05bc, 0x00000030,
> - 0x020e05c4, 0x00000030,
> - 0x021b0800, 0xa1390003,
> - 0x021b080c, 0x001b001e,
> - 0x021b0810, 0x002e0029,
> - 0x021b480c, 0x001b002a,
> - 0x021b4810, 0x0019002c,
> - 0x021b083c, 0x43240334,
> - 0x021b0840, 0x0324031a,
> - 0x021b483c, 0x43340344,
> - 0x021b4840, 0x03280276,
> - 0x021b0848, 0x44383A3E,
> - 0x021b4848, 0x3C3C3846,
> - 0x021b0850, 0x2e303230,
> - 0x021b4850, 0x38283E34,
> - 0x021b081c, 0x33333333,
> - 0x021b0820, 0x33333333,
> - 0x021b0824, 0x33333333,
> - 0x021b0828, 0x33333333,
> - 0x021b481c, 0x33333333,
> - 0x021b4820, 0x33333333,
> - 0x021b4824, 0x33333333,
> - 0x021b4828, 0x33333333,
> - 0x021b08c0, 0x24912249,
> - 0x021b48c0, 0x24914289,
> - 0x021b08b8, 0x00000800,
> - 0x021b48b8, 0x00000800,
> - 0x021b0004, 0x00020036,
> - 0x021b0008, 0x24444040,
> - 0x021b000c, 0x555A7955,
> - 0x021b0010, 0xFF320F64,
> - 0x021b0014, 0x01ff00db,
> - 0x021b0018, 0x00001740,
> - 0x021b001c, 0x00008000,
> - 0x021b002c, 0x000026d2,
> - 0x021b0030, 0x005A1023,
> - 0x021b0040, 0x00000027,
> - 0x021b0400, 0x14420000,
> - 0x021b0000, 0x831A0000,
> - 0x021b0890, 0x00400C58,
> - 0x00bb0008, 0x00000000,
> - 0x00bb000c, 0x2891E41A,
> - 0x00bb0038, 0x00000564,
> - 0x00bb0014, 0x00000040,
> - 0x00bb0028, 0x00000020,
> - 0x00bb002c, 0x00000020,
> - 0x021b001c, 0x04088032,
> - 0x021b001c, 0x00008033,
> - 0x021b001c, 0x00048031,
> - 0x021b001c, 0x09408030,
> - 0x021b001c, 0x04008040,
> - 0x021b0020, 0x00005800,
> - 0x021b0818, 0x00011117,
> - 0x021b4818, 0x00011117,
> - 0x021b0004, 0x00025576,
> - 0x021b0404, 0x00011006,
> - 0x021b001c, 0x00000000,
> -};
> -
> -static int mx6dl_dcd_table[] = {
> - 0x020e0774, 0x000C0000,
> - 0x020e0754, 0x00000000,
> - 0x020e04ac, 0x00000030,
> - 0x020e04b0, 0x00000030,
> - 0x020e0464, 0x00000030,
> - 0x020e0490, 0x00000030,
> - 0x020e074c, 0x00000030,
> - 0x020e0494, 0x00000030,
> - 0x020e04a0, 0x00000000,
> - 0x020e04b4, 0x00000030,
> - 0x020e04b8, 0x00000030,
> - 0x020e076c, 0x00000030,
> - 0x020e0750, 0x00020000,
> - 0x020e04bc, 0x00000030,
> - 0x020e04c0, 0x00000030,
> - 0x020e04c4, 0x00000030,
> - 0x020e04c8, 0x00000030,
> - 0x020e04cc, 0x00000030,
> - 0x020e04d0, 0x00000030,
> - 0x020e04d4, 0x00000030,
> - 0x020e04d8, 0x00000030,
> - 0x020e0760, 0x00020000,
> - 0x020e0764, 0x00000030,
> - 0x020e0770, 0x00000030,
> - 0x020e0778, 0x00000030,
> - 0x020e077c, 0x00000030,
> - 0x020e0780, 0x00000030,
> - 0x020e0784, 0x00000030,
> - 0x020e078c, 0x00000030,
> - 0x020e0748, 0x00000030,
> - 0x020e0470, 0x00000030,
> - 0x020e0474, 0x00000030,
> - 0x020e0478, 0x00000030,
> - 0x020e047c, 0x00000030,
> - 0x020e0480, 0x00000030,
> - 0x020e0484, 0x00000030,
> - 0x020e0488, 0x00000030,
> - 0x020e048c, 0x00000030,
> - 0x021b0800, 0xa1390003,
> - 0x021b080c, 0x001F001F,
> - 0x021b0810, 0x001F001F,
> - 0x021b480c, 0x001F001F,
> - 0x021b4810, 0x001F001F,
> - 0x021b083c, 0x4220021F,
> - 0x021b0840, 0x0207017E,
> - 0x021b483c, 0x4201020C,
> - 0x021b4840, 0x01660172,
> - 0x021b0848, 0x4A4D4E4D,
> - 0x021b4848, 0x4A4F5049,
> - 0x021b0850, 0x3F3C3D31,
> - 0x021b4850, 0x3238372B,
> - 0x021b081c, 0x33333333,
> - 0x021b0820, 0x33333333,
> - 0x021b0824, 0x33333333,
> - 0x021b0828, 0x33333333,
> - 0x021b481c, 0x33333333,
> - 0x021b4820, 0x33333333,
> - 0x021b4824, 0x33333333,
> - 0x021b4828, 0x33333333,
> - 0x021b08b8, 0x00000800,
> - 0x021b48b8, 0x00000800,
> - 0x021b0004, 0x0002002D,
> - 0x021b0008, 0x00333030,
> - 0x021b000c, 0x3F435313,
> - 0x021b0010, 0xB66E8B63,
> - 0x021b0014, 0x01FF00DB,
> - 0x021b0018, 0x00001740,
> - 0x021b001c, 0x00008000,
> - 0x021b002c, 0x000026d2,
> - 0x021b0030, 0x00431023,
> - 0x021b0040, 0x00000027,
> - 0x021b0000, 0x831A0000,
> - 0x021b001c, 0x04008032,
> - 0x021b001c, 0x00008033,
> - 0x021b001c, 0x00048031,
> - 0x021b001c, 0x05208030,
> - 0x021b001c, 0x04008040,
> - 0x021b0020, 0x00005800,
> - 0x021b0818, 0x00011117,
> - 0x021b4818, 0x00011117,
> - 0x021b0004, 0x0002556D,
> - 0x021b0404, 0x00011006,
> - 0x021b001c, 0x00000000,
> -};
> -
> -static void ddr_init(int *table, int size) -{
> - int i;
> -
> - for (i = 0; i < size / 2 ; i++)
> - writel(table[2 * i + 1], table[2 * i]);
> -}
> -
> -static void spl_dram_init(void)
> -{
> - if (is_mx6dq())
> - ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
> - else if (is_mx6dqp())
> - ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
> - else if (is_mx6sdl())
> - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> - /* DDR initialization */
> - spl_dram_init();
> -
> - /* setup AIPS and disable watchdog */
> - arch_cpu_init();
> -
> - ccgr_init();
> - gpr_init();
> -
> - /* iomux and setup of i2c */
> - board_early_init_f();
> -
> - /* setup GP timer */
> - timer_init();
> -
> - /* UART clocks enabled and gd valid - init serial console */
> - preloader_console_init();
> -
> - /* Clear the BSS. */
> - memset(__bss_start, 0, __bss_end - __bss_start);
> -
> - /* load/boot image from boot device */
> - board_init_r(NULL, 0);
> -}
> -#endif
> diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
> deleted file mode 100644 index e0202ef57db..00000000000
> --- a/configs/mx6sabresd_defconfig
> +++ /dev/null
> @@ -1,75 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_MX6=y
> -CONFIG_SYS_TEXT_BASE=0x17800000
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_TARGET_MX6SABRESD=y
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_LIBDISK_SUPPORT=y
> -CONFIG_NR_DRAM_BANKS=1
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.c
> fg"
> -# CONFIG_CONSOLE_MUX is not set
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> -CONFIG_SUPPORT_RAW_INITRD=y
> -CONFIG_SPL_EXT_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -CONFIG_SPL_USB_HOST_SUPPORT=y
> -CONFIG_SPL_USB_GADGET_SUPPORT=y
> -CONFIG_SPL_USB_SDP_SUPPORT=y
> -CONFIG_SPL_WATCHDOG_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_BOOTZ=y
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_SPL_WRITE_SIZE=0x20000
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_PART=y
> -CONFIG_CMD_PCI=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_USB_SDP=y
> -CONFIG_CMD_USB_MASS_STORAGE=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_EXT4=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_FAT=y
> -CONFIG_CMD_FS_GENERIC=y
> -CONFIG_EFI_PARTITION=y
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_USB_FUNCTION_FASTBOOT=y
> -CONFIG_FASTBOOT_BUF_ADDR=0x12000000
> -CONFIG_FASTBOOT_BUF_SIZE=0x10000000
> -CONFIG_FASTBOOT_FLASH=y
> -CONFIG_FASTBOOT_FLASH_MMC_DEV=2
> -CONFIG_FSL_ESDHC=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_STMICRO=y
> -CONFIG_PHYLIB=y
> -CONFIG_MII=y
> -CONFIG_PCI=y
> -CONFIG_SPI=y
> -CONFIG_MXC_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="FSL"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> -CONFIG_CI_UDC=y
> -CONFIG_USB_HOST_ETHER=y
> -CONFIG_USB_ETHER_ASIX=y
> -CONFIG_VIDEO=y
> -# CONFIG_VIDEO_SW_CURSOR is not set
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
> deleted file mode 100644 index 555942a2c2a..00000000000
> --- a/include/configs/mx6sabresd.h
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright (C) 2012 Freescale Semiconductor, Inc.
> - *
> - * Configuration settings for the Freescale i.MX6Q SabreSD board.
> - */
> -
> -#ifndef __MX6SABRESD_CONFIG_H
> -#define __MX6SABRESD_CONFIG_H
> -
> -#ifdef CONFIG_SPL
> -#include "imx6_spl.h"
> -#endif
> -
> -#define CONFIG_MACH_TYPE 3980
> -#define CONFIG_MXC_UART_BASE UART1_BASE
> -#define CONSOLE_DEV "ttymxc0"
> -
> -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> -
> -#include "mx6sabre_common.h"
> -
> -/* Falcon Mode */
> -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
> -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
> -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
> -
> -/* Falcon Mode - MMC support: args at 1MB kernel at 2MB */
> -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /*
> 1MB */
> -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
> (CONFIG_CMD_SPL_WRITE_SIZE / 512)
> -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
> 0x1000 /* 2MB */
> -
> -#define CONFIG_SYS_FSL_USDHC_NUM 3
> -#if defined(CONFIG_ENV_IS_IN_MMC)
> -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
> -#endif
> -
> -#ifdef CONFIG_CMD_PCI
> -#define CONFIG_PCI_SCAN_SHOW
> -#define CONFIG_PCIE_IMX
> -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
> -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
> -#endif
> -
> -/* I2C Configs */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_MXC
> -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> -#define CONFIG_SYS_I2C_SPEED 100000
> -
> -/* PMIC */
> -#define CONFIG_POWER
> -#define CONFIG_POWER_I2C
> -#define CONFIG_POWER_PFUZE100
> -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
> -
> -/* USB Configs */
> -#ifdef CONFIG_CMD_USB
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI |
> PORT_PTS_PTW)
> -#define CONFIG_MXC_USB_FLAGS 0
> -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB
> controller number */
> -#endif
> -
> -#endif /* __MX6SABRESD_CONFIG_H */
> --
> 2.19.1.1215.g8438c0b245-goog
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7CPeng.Fan%40nxp.co
> m%7C1d3ae10ebc6749142c7508d64e436ddf%7C686ea1d3bc2b4c6fa92cd99
> c5c301635%7C0%7C0%7C636782448860055887&sdata=KSONyk6yAMy
> 8TBxHQIGArB98XFf52W6DJ%2FKv1sS%2FRik%3D&reserved=0
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 62/93] arm: Remove dh_imx6 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (60 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 61/93] arm: Remove mx6sabresd board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-20 12:15 ` Ludwig Zenz
2018-11-19 15:53 ` [U-Boot] [PATCH 63/93] arm: Remove vinco board Simon Glass
` (35 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 2 -
board/dhelectronics/dh_imx6/Kconfig | 12 -
board/dhelectronics/dh_imx6/MAINTAINERS | 7 -
board/dhelectronics/dh_imx6/Makefile | 9 -
board/dhelectronics/dh_imx6/dh_imx6.c | 431 ----------------
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 591 ----------------------
configs/dh_imx6_defconfig | 63 ---
include/configs/dh_imx6.h | 178 -------
8 files changed, 1293 deletions(-)
delete mode 100644 board/dhelectronics/dh_imx6/Kconfig
delete mode 100644 board/dhelectronics/dh_imx6/MAINTAINERS
delete mode 100644 board/dhelectronics/dh_imx6/Makefile
delete mode 100644 board/dhelectronics/dh_imx6/dh_imx6.c
delete mode 100644 board/dhelectronics/dh_imx6/dh_imx6_spl.c
delete mode 100644 configs/dh_imx6_defconfig
delete mode 100644 include/configs/dh_imx6.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index e96deadf72d..d05a3fa7ccf 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -524,13 +524,11 @@ source "board/ge/bx50v3/Kconfig"
source "board/advantech/dms-ba16/Kconfig"
source "board/aristainetos/Kconfig"
source "board/armadeus/opos6uldev/Kconfig"
-source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
-source "board/dhelectronics/dh_imx6/Kconfig"
source "board/engicam/imx6q/Kconfig"
source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
diff --git a/board/dhelectronics/dh_imx6/Kconfig b/board/dhelectronics/dh_imx6/Kconfig
deleted file mode 100644
index 0cfef9b0971..00000000000
--- a/board/dhelectronics/dh_imx6/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DHCOMIMX6
-
-config SYS_BOARD
- default "dh_imx6"
-
-config SYS_VENDOR
- default "dhelectronics"
-
-config SYS_CONFIG_NAME
- default "dh_imx6"
-
-endif
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS
deleted file mode 100644
index ab4e16bd5df..00000000000
--- a/board/dhelectronics/dh_imx6/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-DH_IMX6 BOARD
-M: Andreas Geisreiter <ageisreiter@dh-electronics.de>
-M: Ludwig Zenz <lzenz@dh-electronics.de>
-S: Maintained
-F: board/dhelectronics/dh_imx6/
-F: include/configs/dh_imx6.h
-F: configs/dh_imx6_defconfig
diff --git a/board/dhelectronics/dh_imx6/Makefile b/board/dhelectronics/dh_imx6/Makefile
deleted file mode 100644
index 70ca30d3971..00000000000
--- a/board/dhelectronics/dh_imx6/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2017 Marek Vasut <marex@denx.de>
-
-ifdef CONFIG_SPL_BUILD
-obj-y := dh_imx6_spl.o
-else
-obj-y := dh_imx6.o
-endif
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
deleted file mode 100644
index f9ac5c10e1d..00000000000
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ /dev/null
@@ -1,431 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * DHCOM DH-iMX6 PDK board support
- *
- * Copyright (C) 2017 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/sata.h>
-#include <environment.h>
-#include <errno.h>
-#include <fsl_esdhc.h>
-#include <fuse.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define I2C_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define EEPROM_I2C_ADDRESS 0x50
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-#ifdef CONFIG_FEC_MXC
-static void eth_phy_reset(void)
-{
- /* Reset PHY */
- gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
- udelay(500);
- gpio_set_value(IMX_GPIO_NR(5, 0), 1);
-
- /* Enable VIO */
- gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
-
- /*
- * KSZ9021 PHY needs at least 10 mSec after PHY reset
- * is released to stabilize
- */
- mdelay(10);
-}
-
-static int setup_fec_clock(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* set gpr1[21] to select anatop clock */
- clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
-
- return enable_fec_anatop_clock(0, ENET_50MHZ);
-}
-
-int board_eth_init(bd_t *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
-
- setup_fec_clock();
-
- eth_phy_reset();
-
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
-
- /* Scan PHY 0 */
- phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- printf("Ethernet PHY not found!\n");
- return -EINVAL;
- }
-
- return fec_probe(bis, -1, base, bus, phydev);
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
- { USDHC2_BASE_ADDR },
- { USDHC3_BASE_ADDR },
- { USDHC4_BASE_ADDR },
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- return gpio_get_value(USDHC2_CD_GPIO);
- case USDHC3_BASE_ADDR:
- return !gpio_get_value(USDHC3_CD_GPIO);
- case USDHC4_BASE_ADDR:
- return 1; /* eMMC/uSDHC4 is always present */
- }
-
- return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 SD interface
- * mmc1 micro SD
- * mmc2 eMMC
- */
- gpio_direction_input(USDHC2_CD_GPIO);
- gpio_direction_input(USDHC3_CD_GPIO);
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
-{
- /*
- * Set daisy chain for otg_pin_id on MX6Q.
- * For MX6DL, this bit is reserved.
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return USB_INIT_DEVICE;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
-
-static int setup_dhcom_mac_from_fuse(void)
-{
- unsigned char enetaddr[6];
- int ret;
-
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret) /* ethaddr is already set */
- return 0;
-
- imx_get_mac_from_fuse(0, enetaddr);
-
- if (is_valid_ethaddr(enetaddr)) {
- eth_env_set_enetaddr("ethaddr", enetaddr);
- return 0;
- }
-
- ret = i2c_set_bus_num(2);
- if (ret) {
- printf("Error switching I2C bus!\n");
- return ret;
- }
-
- ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
- if (ret) {
- printf("Error reading configuration EEPROM!\n");
- return ret;
- }
-
- if (is_valid_ethaddr(enetaddr))
- eth_env_set_enetaddr("ethaddr", enetaddr);
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- if (bus == 0 && cs == 0)
- return IMX_GPIO_NR(2, 30);
- else
- return -1;
-}
-#endif
-
-int board_init(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* Enable eim_slow clocks */
- setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
-
-#ifdef CONFIG_SYS_I2C_MXC
- if (is_mx6dq()) {
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
- } else {
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
- }
-#endif
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
-
- setup_dhcom_mac_from_fuse();
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-#define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
-#define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
-#define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
-
-static int board_get_hwcode(void)
-{
- int hw_code;
-
- gpio_direction_input(HW_CODE_BIT_0);
- gpio_direction_input(HW_CODE_BIT_1);
- gpio_direction_input(HW_CODE_BIT_2);
-
- /* HW 100 + HW 200 = 00b; HW 300 = 01b */
- hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
- (gpio_get_value(HW_CODE_BIT_1) << 1) |
- gpio_get_value(HW_CODE_BIT_0)) + 2;
-
- return hw_code;
-}
-
-int board_late_init(void)
-{
- u32 hw_code;
- char buf[16];
-
- hw_code = board_get_hwcode();
-
- switch (get_cpu_type()) {
- case MXC_CPU_MX6SOLO:
- snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
- break;
- case MXC_CPU_MX6DL:
- snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
- break;
- case MXC_CPU_MX6D:
- snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
- break;
- case MXC_CPU_MX6Q:
- snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
- break;
- default:
- snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
- break;
- }
-
- env_set("dhcom", buf);
-
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: DHCOM i.MX6\n");
- return 0;
-}
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
deleted file mode 100644
index 04e9eab272a..00000000000
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ /dev/null
@@ -1,591 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * DHCOM DH-iMX6 PDK SPL support
- *
- * Copyright (C) 2017 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <fuse.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <spl.h>
-
-#define ENET_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS)
-
-#define GPIO_PAD_CTRL \
- (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
-
-#define SPI_PAD_CTRL \
- (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST)
-
-#define UART_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL \
- (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
- .p0_mpwldectrl0 = 0x00150019,
- .p0_mpwldectrl1 = 0x001C000B,
- .p1_mpwldectrl0 = 0x00020018,
- .p1_mpwldectrl1 = 0x0002000C,
- .p0_mpdgctrl0 = 0x43140320,
- .p0_mpdgctrl1 = 0x03080304,
- .p1_mpdgctrl0 = 0x43180320,
- .p1_mpdgctrl1 = 0x03100254,
- .p0_mprddlctl = 0x4830383C,
- .p1_mprddlctl = 0x3836323E,
- .p0_mpwrdlctl = 0x3E444642,
- .p1_mpwrdlctl = 0x42344442,
-};
-
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
- .p0_mpwldectrl0 = 0x0040003C,
- .p0_mpwldectrl1 = 0x0032003E,
- .p0_mpdgctrl0 = 0x42350231,
- .p0_mpdgctrl1 = 0x021A0218,
- .p0_mprddlctl = 0x4B4B4E49,
- .p0_mpwrdlctl = 0x3F3F3035,
-};
-
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
- .p0_mpwldectrl0 = 0x0011000E,
- .p0_mpwldectrl1 = 0x000E001B,
- .p1_mpwldectrl0 = 0x00190015,
- .p1_mpwldectrl1 = 0x00070018,
- .p0_mpdgctrl0 = 0x42720306,
- .p0_mpdgctrl1 = 0x026F0266,
- .p1_mpdgctrl0 = 0x4273030A,
- .p1_mpdgctrl1 = 0x02740240,
- .p0_mprddlctl = 0x45393B3E,
- .p1_mprddlctl = 0x403A3747,
- .p0_mpwrdlctl = 0x40434541,
- .p1_mpwrdlctl = 0x473E4A3B,
-};
-
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
- .p0_mpwldectrl0 = 0x003A003A,
- .p0_mpwldectrl1 = 0x0030002F,
- .p1_mpwldectrl0 = 0x002F0038,
- .p1_mpwldectrl1 = 0x00270039,
- .p0_mpdgctrl0 = 0x420F020F,
- .p0_mpdgctrl1 = 0x01760175,
- .p1_mpdgctrl0 = 0x41640171,
- .p1_mpdgctrl1 = 0x015E0160,
- .p0_mprddlctl = 0x45464B4A,
- .p1_mprddlctl = 0x49484A46,
- .p0_mpwrdlctl = 0x40402E32,
- .p1_mpwrdlctl = 0x3A3A3231,
-};
-
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
- .p0_mpwldectrl0 = 0x0040003C,
- .p0_mpwldectrl1 = 0x0032003E,
- .p0_mpdgctrl0 = 0x42350231,
- .p0_mpdgctrl1 = 0x021A0218,
- .p0_mprddlctl = 0x4B4B4E49,
- .p0_mpwrdlctl = 0x3F3F3035,
-};
-
-/*
- * 2 Gbit DDR3 memory
- * - NANYA #NT5CC128M16IP-DII
- * - NANYA #NT5CB128M16FP-DII
- */
-static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 5863,
- .trasmin = 3750,
-};
-
-/*
- * 4 Gbit DDR3 memory
- * - Intelligent Memory #IM4G16D3EABG-125I
- */
-static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-/* DDR3 64bit */
-static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- .cs_density = 32,
- .ncs = 1, /* single chip select */
- .cs1_mirror = 1,
- .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
- .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 3, /* 4 refresh commands per refresh cycle */
-};
-
-/* DDR3 32bit */
-static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 1,
- .cs_density = 32,
- .ncs = 1, /* single chip select */
- .cs1_mirror = 1,
- .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
- .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 3, /* 4 refresh commands per refresh cycle */
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-/* Board ID */
-static iomux_v3_cfg_t const hwcode_pads[] = {
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
-};
-
-static void setup_iomux_boardid(void)
-{
- /* HW code pins: Setup alternate function and configure pads */
- SETUP_IOMUX_PADS(hwcode_pads);
-}
-
-/* DDR Code */
-static iomux_v3_cfg_t const ddrcode_pads[] = {
- IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
-};
-
-static void setup_iomux_ddrcode(void)
-{
- /* ddr code pins */
- SETUP_IOMUX_PADS(ddrcode_pads);
-}
-
-enum dhcom_ddr3_code {
- DH_DDR3_SIZE_256MIB = 0x00,
- DH_DDR3_SIZE_512MIB = 0x01,
- DH_DDR3_SIZE_1GIB = 0x02,
- DH_DDR3_SIZE_2GIB = 0x03
-};
-
-#define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
-#define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
-
-enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
-{
- enum dhcom_ddr3_code ddr3_code;
-
- gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
- gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
-
- gpio_direction_input(DDR3_CODE_BIT_0);
- gpio_direction_input(DDR3_CODE_BIT_1);
-
- /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
- ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
- | (!!gpio_get_value(DDR3_CODE_BIT_0));
-
- return ddr3_code;
-}
-
-/* GPIO */
-static iomux_v3_cfg_t const gpio_pads[] = {
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
-};
-
-static void setup_iomux_gpio(void)
-{
- SETUP_IOMUX_PADS(gpio_pads);
-}
-
-/* Ethernet */
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* SMSC PHY Reset */
- IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* ENET_VIO_GPIO */
- IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* ENET_Interrupt - (not used) */
- IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-}
-
-/* SD interface */
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-/* onboard microSD */
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-/* eMMC */
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-/* SD */
-static void setup_iomux_sd(void)
-{
- SETUP_IOMUX_PADS(usdhc2_pads);
- SETUP_IOMUX_PADS(usdhc3_pads);
- SETUP_IOMUX_PADS(usdhc4_pads);
-}
-
-/* SPI */
-static iomux_v3_cfg_t const ecspi1_pads[] = {
- /* SS0 */
- IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
-};
-
-static void setup_iomux_spi(void)
-{
- SETUP_IOMUX_PADS(ecspi1_pads);
-}
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- if (bus == 0 && cs == 0)
- return IMX_GPIO_NR(2, 30);
- else
- return -1;
-}
-
-/* UART */
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-/* USB */
-static iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_usb(void)
-{
- SETUP_IOMUX_PADS(usb_pads);
-}
-
-
-/* DRAM */
-static void dhcom_spl_dram_init(void)
-{
- enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
-
- if (is_mx6dq()) {
- mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
- &dhcom6dq_grp_ioregs);
- switch (ddr3_code) {
- default:
- printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
- printf(" choosing 1024 MB\n");
- /* fall through */
- case DH_DDR3_SIZE_1GIB:
- mx6_dram_cfg(&dhcom_ddr_64bit,
- &dhcom_mmdc_calib_4x2g_1066,
- &dhcom_mem_ddr_2g);
- break;
- case DH_DDR3_SIZE_2GIB:
- mx6_dram_cfg(&dhcom_ddr_64bit,
- &dhcom_mmdc_calib_4x4g_1066,
- &dhcom_mem_ddr_4g);
- break;
- }
-
- /* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
-
- } else if (is_cpu_type(MXC_CPU_MX6DL)) {
- mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
- &dhcom6sdl_grp_ioregs);
- switch (ddr3_code) {
- default:
- printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
- printf(" choosing 1024 MB\n");
- /* fall through */
- case DH_DDR3_SIZE_1GIB:
- mx6_dram_cfg(&dhcom_ddr_64bit,
- &dhcom_mmdc_calib_4x2g_800,
- &dhcom_mem_ddr_2g);
- break;
- }
-
- /* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
-
- } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
- mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
- &dhcom6sdl_grp_ioregs);
- switch (ddr3_code) {
- default:
- printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
- printf(" choosing 512 MB\n");
- /* fall through */
- case DH_DDR3_SIZE_512MIB:
- mx6_dram_cfg(&dhcom_ddr_32bit,
- &dhcom_mmdc_calib_2x2g_800,
- &dhcom_mem_ddr_2g);
- break;
- case DH_DDR3_SIZE_1GIB:
- mx6_dram_cfg(&dhcom_ddr_32bit,
- &dhcom_mmdc_calib_2x4g_800,
- &dhcom_mem_ddr_4g);
- break;
- }
-
- /* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
- }
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* setup GP timer */
- timer_init();
-
- setup_iomux_boardid();
- setup_iomux_ddrcode();
- setup_iomux_gpio();
- setup_iomux_enet();
- setup_iomux_sd();
- setup_iomux_spi();
- setup_iomux_uart();
- setup_iomux_usb();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR3 initialization */
- dhcom_spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
deleted file mode 100644
index 92b23778ef0..00000000000
--- a/configs/dh_imx6_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_DHCOMIMX6=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DWC_AHSATA=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="dh"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
deleted file mode 100644
index 9231bd853f4..00000000000
--- a/include/configs/dh_imx6.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * DHCOM DH-iMX6 PDK board configuration
- *
- * Copyright (C) 2017 Marek Vasut <marex@denx.de>
- */
-
-#ifndef __DH_IMX6_CONFIG_H
-#define __DH_IMX6_CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-#include "mx6_common.h"
-
-/*
- * SPI NOR layout:
- * 0x00_0000-0x00_ffff ... U-Boot SPL
- * 0x01_0000-0x0f_ffff ... U-Boot
- * 0x10_0000-0x10_ffff ... U-Boot env #1
- * 0x11_0000-0x11_ffff ... U-Boot env #2
- * 0x12_0000-0x1f_ffff ... UNUSED
- */
-
-/* SPL */
-#include "imx6_spl.h" /* common IMX6 SPL configuration */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
-#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_BZIP2
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
-
-/* Bootcounter */
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-/* FEC ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* MMC Configs */
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
-
-/* SATA Configs */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* SPI Flash Configs */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-#endif
-
-/* UART */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_BAUDRATE 115200
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
-
-/* USB Gadget (DFU, UMS) */
-#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-
-/* USB IDs */
-#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#endif
-#endif
-
-/* Watchdog */
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200\0" \
- "fdt_addr=0x18000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x10008000\0" \
- "fdt_addr_r=0x13000000\0" \
- "ramdisk_addr_r=0x18000000\0" \
- "scriptaddr=0x14000000\0" \
- "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
- BOOTENV
-
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 2) \
- func(USB, usb, 1) \
- func(SATA, sata, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-#endif
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x20000000
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-/* Environment */
-#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-#define CONFIG_ENV_OFFSET (1024 * 1024)
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
-
-#endif /* __DH_IMX6_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 62/93] arm: Remove dh_imx6 board
2018-11-19 15:53 ` [U-Boot] [PATCH 62/93] arm: Remove dh_imx6 board Simon Glass
@ 2018-11-20 12:15 ` Ludwig Zenz
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Ludwig Zenz @ 2018-11-20 12:15 UTC (permalink / raw)
To: u-boot
On 19.11.2018 16:53, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
Hi Simon,
CONFIG_DM_BLK does not exist. Did you mean CONFIG_BLK?
I didn't know about any deadline or necessary change. I will have a look
at it.
NAK. The board is used.
Regards,
Ludwig Zenz
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-imx/mx6/Kconfig | 2 -
> board/dhelectronics/dh_imx6/Kconfig | 12 -
> board/dhelectronics/dh_imx6/MAINTAINERS | 7 -
> board/dhelectronics/dh_imx6/Makefile | 9 -
> board/dhelectronics/dh_imx6/dh_imx6.c | 431 ----------------
> board/dhelectronics/dh_imx6/dh_imx6_spl.c | 591 ----------------------
> configs/dh_imx6_defconfig | 63 ---
> include/configs/dh_imx6.h | 178 -------
> 8 files changed, 1293 deletions(-)
> delete mode 100644 board/dhelectronics/dh_imx6/Kconfig
> delete mode 100644 board/dhelectronics/dh_imx6/MAINTAINERS
> delete mode 100644 board/dhelectronics/dh_imx6/Makefile
> delete mode 100644 board/dhelectronics/dh_imx6/dh_imx6.c
> delete mode 100644 board/dhelectronics/dh_imx6/dh_imx6_spl.c
> delete mode 100644 configs/dh_imx6_defconfig
> delete mode 100644 include/configs/dh_imx6.h
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index e96deadf72d..d05a3fa7ccf 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -524,13 +524,11 @@ source "board/ge/bx50v3/Kconfig"
> source "board/advantech/dms-ba16/Kconfig"
> source "board/aristainetos/Kconfig"
> source "board/armadeus/opos6uldev/Kconfig"
> -source "board/bachmann/ot1200/Kconfig"
> source "board/barco/platinum/Kconfig"
> source "board/barco/titanium/Kconfig"
> source "board/boundary/nitrogen6x/Kconfig"
> source "board/compulab/cm_fx6/Kconfig"
> source "board/congatec/cgtqmx6eval/Kconfig"
> -source "board/dhelectronics/dh_imx6/Kconfig"
> source "board/engicam/imx6q/Kconfig"
> source "board/engicam/imx6ul/Kconfig"
> source "board/freescale/mx6qarm2/Kconfig"
> diff --git a/board/dhelectronics/dh_imx6/Kconfig b/board/dhelectronics/dh_imx6/Kconfig
> deleted file mode 100644
> index 0cfef9b0971..00000000000
> --- a/board/dhelectronics/dh_imx6/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_DHCOMIMX6
> -
> -config SYS_BOARD
> - default "dh_imx6"
> -
> -config SYS_VENDOR
> - default "dhelectronics"
> -
> -config SYS_CONFIG_NAME
> - default "dh_imx6"
> -
> -endif
> diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS
> deleted file mode 100644
> index ab4e16bd5df..00000000000
> --- a/board/dhelectronics/dh_imx6/MAINTAINERS
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -DH_IMX6 BOARD
> -M: Andreas Geisreiter <ageisreiter@dh-electronics.de>
> -M: Ludwig Zenz <lzenz@dh-electronics.de>
> -S: Maintained
> -F: board/dhelectronics/dh_imx6/
> -F: include/configs/dh_imx6.h
> -F: configs/dh_imx6_defconfig
> diff --git a/board/dhelectronics/dh_imx6/Makefile b/board/dhelectronics/dh_imx6/Makefile
> deleted file mode 100644
> index 70ca30d3971..00000000000
> --- a/board/dhelectronics/dh_imx6/Makefile
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2017 Marek Vasut <marex@denx.de>
> -
> -ifdef CONFIG_SPL_BUILD
> -obj-y := dh_imx6_spl.o
> -else
> -obj-y := dh_imx6.o
> -endif
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
> deleted file mode 100644
> index f9ac5c10e1d..00000000000
> --- a/board/dhelectronics/dh_imx6/dh_imx6.c
> +++ /dev/null
> @@ -1,431 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * DHCOM DH-iMX6 PDK board support
> - *
> - * Copyright (C) 2017 Marek Vasut <marex@denx.de>
> - */
> -
> -#include <common.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/crm_regs.h>
> -#include <asm/arch/imx-regs.h>
> -#include <asm/arch/iomux.h>
> -#include <asm/arch/mx6-pins.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/gpio.h>
> -#include <asm/io.h>
> -#include <asm/mach-imx/boot_mode.h>
> -#include <asm/mach-imx/iomux-v3.h>
> -#include <asm/mach-imx/mxc_i2c.h>
> -#include <asm/mach-imx/sata.h>
> -#include <environment.h>
> -#include <errno.h>
> -#include <fsl_esdhc.h>
> -#include <fuse.h>
> -#include <i2c.h>
> -#include <miiphy.h>
> -#include <mmc.h>
> -#include <net.h>
> -#include <netdev.h>
> -#include <usb.h>
> -#include <usb/ehci-ci.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define I2C_PAD_CTRL \
> - (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> -
> -#define EEPROM_I2C_ADDRESS 0x50
> -
> -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> -
> -static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
> - .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
> - .gp = IMX_GPIO_NR(3, 21)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
> - .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
> - .gp = IMX_GPIO_NR(3, 28)
> - }
> -};
> -
> -static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
> - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
> - .gp = IMX_GPIO_NR(4, 12)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
> - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
> - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
> - .gp = IMX_GPIO_NR(1, 3)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
> - .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
> - .gp = IMX_GPIO_NR(1, 6)
> - }
> -};
> -
> -static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
> - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
> - .gp = IMX_GPIO_NR(3, 21)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
> - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
> - .gp = IMX_GPIO_NR(3, 28)
> - }
> -};
> -
> -static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
> - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
> - .gp = IMX_GPIO_NR(4, 12)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
> - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
> - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
> - .gp = IMX_GPIO_NR(1, 3)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
> - .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
> - .gp = IMX_GPIO_NR(1, 6)
> - }
> -};
> -
> -int dram_init(void)
> -{
> - gd->ram_size = imx_ddr_size();
> - return 0;
> -}
> -
> -/*
> - * Do not overwrite the console
> - * Use always serial for U-Boot console
> - */
> -int overwrite_console(void)
> -{
> - return 1;
> -}
> -
> -#ifdef CONFIG_FEC_MXC
> -static void eth_phy_reset(void)
> -{
> - /* Reset PHY */
> - gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
> - udelay(500);
> - gpio_set_value(IMX_GPIO_NR(5, 0), 1);
> -
> - /* Enable VIO */
> - gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
> -
> - /*
> - * KSZ9021 PHY needs at least 10 mSec after PHY reset
> - * is released to stabilize
> - */
> - mdelay(10);
> -}
> -
> -static int setup_fec_clock(void)
> -{
> - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> -
> - /* set gpr1[21] to select anatop clock */
> - clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
> -
> - return enable_fec_anatop_clock(0, ENET_50MHZ);
> -}
> -
> -int board_eth_init(bd_t *bis)
> -{
> - uint32_t base = IMX_FEC_BASE;
> - struct mii_dev *bus = NULL;
> - struct phy_device *phydev = NULL;
> -
> - setup_fec_clock();
> -
> - eth_phy_reset();
> -
> - bus = fec_get_miibus(base, -1);
> - if (!bus)
> - return -EINVAL;
> -
> - /* Scan PHY 0 */
> - phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
> - if (!phydev) {
> - printf("Ethernet PHY not found!\n");
> - return -EINVAL;
> - }
> -
> - return fec_probe(bis, -1, base, bus, phydev);
> -}
> -#endif
> -
> -#ifdef CONFIG_FSL_ESDHC
> -
> -#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
> -#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
> -
> -static struct fsl_esdhc_cfg usdhc_cfg[3] = {
> - { USDHC2_BASE_ADDR },
> - { USDHC3_BASE_ADDR },
> - { USDHC4_BASE_ADDR },
> -};
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> -
> - switch (cfg->esdhc_base) {
> - case USDHC2_BASE_ADDR:
> - return gpio_get_value(USDHC2_CD_GPIO);
> - case USDHC3_BASE_ADDR:
> - return !gpio_get_value(USDHC3_CD_GPIO);
> - case USDHC4_BASE_ADDR:
> - return 1; /* eMMC/uSDHC4 is always present */
> - }
> -
> - return 0;
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> - int i, ret;
> -
> - /*
> - * According to the board_mmc_init() the following map is done:
> - * (U-Boot device node) (Physical Port)
> - * mmc0 SD interface
> - * mmc1 micro SD
> - * mmc2 eMMC
> - */
> - gpio_direction_input(USDHC2_CD_GPIO);
> - gpio_direction_input(USDHC3_CD_GPIO);
> -
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> -
> - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -#endif
> -
> -#ifdef CONFIG_USB_EHCI_MX6
> -static void setup_usb(void)
> -{
> - /*
> - * Set daisy chain for otg_pin_id on MX6Q.
> - * For MX6DL, this bit is reserved.
> - */
> - imx_iomux_set_gpr_register(1, 13, 1, 0);
> -}
> -
> -int board_usb_phy_mode(int port)
> -{
> - if (port == 1)
> - return USB_INIT_HOST;
> - else
> - return USB_INIT_DEVICE;
> -}
> -
> -int board_ehci_power(int port, int on)
> -{
> - switch (port) {
> - case 0:
> - break;
> - case 1:
> - gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
> - break;
> - default:
> - printf("MXC USB port %d not yet supported\n", port);
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -#endif
> -
> -static int setup_dhcom_mac_from_fuse(void)
> -{
> - unsigned char enetaddr[6];
> - int ret;
> -
> - ret = eth_env_get_enetaddr("ethaddr", enetaddr);
> - if (ret) /* ethaddr is already set */
> - return 0;
> -
> - imx_get_mac_from_fuse(0, enetaddr);
> -
> - if (is_valid_ethaddr(enetaddr)) {
> - eth_env_set_enetaddr("ethaddr", enetaddr);
> - return 0;
> - }
> -
> - ret = i2c_set_bus_num(2);
> - if (ret) {
> - printf("Error switching I2C bus!\n");
> - return ret;
> - }
> -
> - ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
> - if (ret) {
> - printf("Error reading configuration EEPROM!\n");
> - return ret;
> - }
> -
> - if (is_valid_ethaddr(enetaddr))
> - eth_env_set_enetaddr("ethaddr", enetaddr);
> -
> - return 0;
> -}
> -
> -int board_early_init_f(void)
> -{
> -#ifdef CONFIG_USB_EHCI_MX6
> - setup_usb();
> -#endif
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_MXC_SPI
> -int board_spi_cs_gpio(unsigned bus, unsigned cs)
> -{
> - if (bus == 0 && cs == 0)
> - return IMX_GPIO_NR(2, 30);
> - else
> - return -1;
> -}
> -#endif
> -
> -int board_init(void)
> -{
> - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -
> - /* address of boot parameters */
> - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> -
> - /* Enable eim_slow clocks */
> - setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
> -
> -#ifdef CONFIG_SYS_I2C_MXC
> - if (is_mx6dq()) {
> - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
> - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
> - } else {
> - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
> - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
> - }
> -#endif
> -
> -#ifdef CONFIG_SATA
> - setup_sata();
> -#endif
> -
> - setup_dhcom_mac_from_fuse();
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_CMD_BMODE
> -static const struct boot_mode board_boot_modes[] = {
> - /* 4 bit bus width */
> - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> - {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> - /* 8 bit bus width */
> - {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
> - {NULL, 0},
> -};
> -#endif
> -
> -#define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
> -#define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
> -#define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
> -
> -static int board_get_hwcode(void)
> -{
> - int hw_code;
> -
> - gpio_direction_input(HW_CODE_BIT_0);
> - gpio_direction_input(HW_CODE_BIT_1);
> - gpio_direction_input(HW_CODE_BIT_2);
> -
> - /* HW 100 + HW 200 = 00b; HW 300 = 01b */
> - hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
> - (gpio_get_value(HW_CODE_BIT_1) << 1) |
> - gpio_get_value(HW_CODE_BIT_0)) + 2;
> -
> - return hw_code;
> -}
> -
> -int board_late_init(void)
> -{
> - u32 hw_code;
> - char buf[16];
> -
> - hw_code = board_get_hwcode();
> -
> - switch (get_cpu_type()) {
> - case MXC_CPU_MX6SOLO:
> - snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
> - break;
> - case MXC_CPU_MX6DL:
> - snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
> - break;
> - case MXC_CPU_MX6D:
> - snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
> - break;
> - case MXC_CPU_MX6Q:
> - snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
> - break;
> - default:
> - snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
> - break;
> - }
> -
> - env_set("dhcom", buf);
> -
> -#ifdef CONFIG_CMD_BMODE
> - add_board_boot_modes(board_boot_modes);
> -#endif
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - puts("Board: DHCOM i.MX6\n");
> - return 0;
> -}
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> deleted file mode 100644
> index 04e9eab272a..00000000000
> --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
> +++ /dev/null
> @@ -1,591 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * DHCOM DH-iMX6 PDK SPL support
> - *
> - * Copyright (C) 2017 Marek Vasut <marex@denx.de>
> - */
> -
> -#include <common.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/crm_regs.h>
> -#include <asm/arch/imx-regs.h>
> -#include <asm/arch/iomux.h>
> -#include <asm/arch/mx6-ddr.h>
> -#include <asm/arch/mx6-pins.h>
> -#include <asm/arch/sys_proto.h>
> -#include <asm/gpio.h>
> -#include <asm/mach-imx/boot_mode.h>
> -#include <asm/mach-imx/iomux-v3.h>
> -#include <asm/mach-imx/mxc_i2c.h>
> -#include <asm/io.h>
> -#include <errno.h>
> -#include <fuse.h>
> -#include <fsl_esdhc.h>
> -#include <i2c.h>
> -#include <mmc.h>
> -#include <spl.h>
> -
> -#define ENET_PAD_CTRL \
> - (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_HYS)
> -
> -#define GPIO_PAD_CTRL \
> - (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
> -
> -#define SPI_PAD_CTRL \
> - (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_SRE_FAST)
> -
> -#define UART_PAD_CTRL \
> - (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define USDHC_PAD_CTRL \
> - (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
> - .dram_sdclk_0 = 0x00020030,
> - .dram_sdclk_1 = 0x00020030,
> - .dram_cas = 0x00020030,
> - .dram_ras = 0x00020030,
> - .dram_reset = 0x00020030,
> - .dram_sdcke0 = 0x00003000,
> - .dram_sdcke1 = 0x00003000,
> - .dram_sdba2 = 0x00000000,
> - .dram_sdodt0 = 0x00003030,
> - .dram_sdodt1 = 0x00003030,
> - .dram_sdqs0 = 0x00000030,
> - .dram_sdqs1 = 0x00000030,
> - .dram_sdqs2 = 0x00000030,
> - .dram_sdqs3 = 0x00000030,
> - .dram_sdqs4 = 0x00000030,
> - .dram_sdqs5 = 0x00000030,
> - .dram_sdqs6 = 0x00000030,
> - .dram_sdqs7 = 0x00000030,
> - .dram_dqm0 = 0x00020030,
> - .dram_dqm1 = 0x00020030,
> - .dram_dqm2 = 0x00020030,
> - .dram_dqm3 = 0x00020030,
> - .dram_dqm4 = 0x00020030,
> - .dram_dqm5 = 0x00020030,
> - .dram_dqm6 = 0x00020030,
> - .dram_dqm7 = 0x00020030,
> -};
> -
> -static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
> - .grp_ddr_type = 0x000C0000,
> - .grp_ddrmode_ctl = 0x00020000,
> - .grp_ddrpke = 0x00000000,
> - .grp_addds = 0x00000030,
> - .grp_ctlds = 0x00000030,
> - .grp_ddrmode = 0x00020000,
> - .grp_b0ds = 0x00000030,
> - .grp_b1ds = 0x00000030,
> - .grp_b2ds = 0x00000030,
> - .grp_b3ds = 0x00000030,
> - .grp_b4ds = 0x00000030,
> - .grp_b5ds = 0x00000030,
> - .grp_b6ds = 0x00000030,
> - .grp_b7ds = 0x00000030,
> -};
> -
> -static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
> - .dram_sdclk_0 = 0x00020030,
> - .dram_sdclk_1 = 0x00020030,
> - .dram_cas = 0x00020030,
> - .dram_ras = 0x00020030,
> - .dram_reset = 0x00020030,
> - .dram_sdcke0 = 0x00003000,
> - .dram_sdcke1 = 0x00003000,
> - .dram_sdba2 = 0x00000000,
> - .dram_sdodt0 = 0x00003030,
> - .dram_sdodt1 = 0x00003030,
> - .dram_sdqs0 = 0x00000030,
> - .dram_sdqs1 = 0x00000030,
> - .dram_sdqs2 = 0x00000030,
> - .dram_sdqs3 = 0x00000030,
> - .dram_sdqs4 = 0x00000030,
> - .dram_sdqs5 = 0x00000030,
> - .dram_sdqs6 = 0x00000030,
> - .dram_sdqs7 = 0x00000030,
> - .dram_dqm0 = 0x00020030,
> - .dram_dqm1 = 0x00020030,
> - .dram_dqm2 = 0x00020030,
> - .dram_dqm3 = 0x00020030,
> - .dram_dqm4 = 0x00020030,
> - .dram_dqm5 = 0x00020030,
> - .dram_dqm6 = 0x00020030,
> - .dram_dqm7 = 0x00020030,
> -};
> -
> -static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
> - .grp_ddr_type = 0x000C0000,
> - .grp_ddrmode_ctl = 0x00020000,
> - .grp_ddrpke = 0x00000000,
> - .grp_addds = 0x00000030,
> - .grp_ctlds = 0x00000030,
> - .grp_ddrmode = 0x00020000,
> - .grp_b0ds = 0x00000030,
> - .grp_b1ds = 0x00000030,
> - .grp_b2ds = 0x00000030,
> - .grp_b3ds = 0x00000030,
> - .grp_b4ds = 0x00000030,
> - .grp_b5ds = 0x00000030,
> - .grp_b6ds = 0x00000030,
> - .grp_b7ds = 0x00000030,
> -};
> -
> -static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
> - .p0_mpwldectrl0 = 0x00150019,
> - .p0_mpwldectrl1 = 0x001C000B,
> - .p1_mpwldectrl0 = 0x00020018,
> - .p1_mpwldectrl1 = 0x0002000C,
> - .p0_mpdgctrl0 = 0x43140320,
> - .p0_mpdgctrl1 = 0x03080304,
> - .p1_mpdgctrl0 = 0x43180320,
> - .p1_mpdgctrl1 = 0x03100254,
> - .p0_mprddlctl = 0x4830383C,
> - .p1_mprddlctl = 0x3836323E,
> - .p0_mpwrdlctl = 0x3E444642,
> - .p1_mpwrdlctl = 0x42344442,
> -};
> -
> -static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
> - .p0_mpwldectrl0 = 0x0040003C,
> - .p0_mpwldectrl1 = 0x0032003E,
> - .p0_mpdgctrl0 = 0x42350231,
> - .p0_mpdgctrl1 = 0x021A0218,
> - .p0_mprddlctl = 0x4B4B4E49,
> - .p0_mpwrdlctl = 0x3F3F3035,
> -};
> -
> -static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
> - .p0_mpwldectrl0 = 0x0011000E,
> - .p0_mpwldectrl1 = 0x000E001B,
> - .p1_mpwldectrl0 = 0x00190015,
> - .p1_mpwldectrl1 = 0x00070018,
> - .p0_mpdgctrl0 = 0x42720306,
> - .p0_mpdgctrl1 = 0x026F0266,
> - .p1_mpdgctrl0 = 0x4273030A,
> - .p1_mpdgctrl1 = 0x02740240,
> - .p0_mprddlctl = 0x45393B3E,
> - .p1_mprddlctl = 0x403A3747,
> - .p0_mpwrdlctl = 0x40434541,
> - .p1_mpwrdlctl = 0x473E4A3B,
> -};
> -
> -static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
> - .p0_mpwldectrl0 = 0x003A003A,
> - .p0_mpwldectrl1 = 0x0030002F,
> - .p1_mpwldectrl0 = 0x002F0038,
> - .p1_mpwldectrl1 = 0x00270039,
> - .p0_mpdgctrl0 = 0x420F020F,
> - .p0_mpdgctrl1 = 0x01760175,
> - .p1_mpdgctrl0 = 0x41640171,
> - .p1_mpdgctrl1 = 0x015E0160,
> - .p0_mprddlctl = 0x45464B4A,
> - .p1_mprddlctl = 0x49484A46,
> - .p0_mpwrdlctl = 0x40402E32,
> - .p1_mpwrdlctl = 0x3A3A3231,
> -};
> -
> -static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
> - .p0_mpwldectrl0 = 0x0040003C,
> - .p0_mpwldectrl1 = 0x0032003E,
> - .p0_mpdgctrl0 = 0x42350231,
> - .p0_mpdgctrl1 = 0x021A0218,
> - .p0_mprddlctl = 0x4B4B4E49,
> - .p0_mpwrdlctl = 0x3F3F3035,
> -};
> -
> -/*
> - * 2 Gbit DDR3 memory
> - * - NANYA #NT5CC128M16IP-DII
> - * - NANYA #NT5CB128M16FP-DII
> - */
> -static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
> - .mem_speed = 1600,
> - .density = 2,
> - .width = 16,
> - .banks = 8,
> - .rowaddr = 14,
> - .coladdr = 10,
> - .pagesz = 2,
> - .trcd = 1375,
> - .trcmin = 5863,
> - .trasmin = 3750,
> -};
> -
> -/*
> - * 4 Gbit DDR3 memory
> - * - Intelligent Memory #IM4G16D3EABG-125I
> - */
> -static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
> - .mem_speed = 1600,
> - .density = 4,
> - .width = 16,
> - .banks = 8,
> - .rowaddr = 15,
> - .coladdr = 10,
> - .pagesz = 2,
> - .trcd = 1375,
> - .trcmin = 4875,
> - .trasmin = 3500,
> -};
> -
> -/* DDR3 64bit */
> -static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
> - /* width of data bus:0=16,1=32,2=64 */
> - .dsize = 2,
> - .cs_density = 32,
> - .ncs = 1, /* single chip select */
> - .cs1_mirror = 1,
> - .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
> - .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
> - .walat = 1, /* Write additional latency */
> - .ralat = 5, /* Read additional latency */
> - .mif3_mode = 3, /* Command prediction working mode */
> - .bi_on = 1, /* Bank interleaving enabled */
> - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
> - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
> - .refsel = 1, /* Refresh cycles at 32KHz */
> - .refr = 3, /* 4 refresh commands per refresh cycle */
> -};
> -
> -/* DDR3 32bit */
> -static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
> - /* width of data bus:0=16,1=32,2=64 */
> - .dsize = 1,
> - .cs_density = 32,
> - .ncs = 1, /* single chip select */
> - .cs1_mirror = 1,
> - .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
> - .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
> - .walat = 1, /* Write additional latency */
> - .ralat = 5, /* Read additional latency */
> - .mif3_mode = 3, /* Command prediction working mode */
> - .bi_on = 1, /* Bank interleaving enabled */
> - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
> - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
> - .refsel = 1, /* Refresh cycles at 32KHz */
> - .refr = 3, /* 4 refresh commands per refresh cycle */
> -};
> -
> -static void ccgr_init(void)
> -{
> - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -
> - writel(0x00C03F3F, &ccm->CCGR0);
> - writel(0x0030FC03, &ccm->CCGR1);
> - writel(0x0FFFC000, &ccm->CCGR2);
> - writel(0x3FF00000, &ccm->CCGR3);
> - writel(0x00FFF300, &ccm->CCGR4);
> - writel(0x0F0000C3, &ccm->CCGR5);
> - writel(0x000003FF, &ccm->CCGR6);
> -}
> -
> -/* Board ID */
> -static iomux_v3_cfg_t const hwcode_pads[] = {
> - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_boardid(void)
> -{
> - /* HW code pins: Setup alternate function and configure pads */
> - SETUP_IOMUX_PADS(hwcode_pads);
> -}
> -
> -/* DDR Code */
> -static iomux_v3_cfg_t const ddrcode_pads[] = {
> - IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_ddrcode(void)
> -{
> - /* ddr code pins */
> - SETUP_IOMUX_PADS(ddrcode_pads);
> -}
> -
> -enum dhcom_ddr3_code {
> - DH_DDR3_SIZE_256MIB = 0x00,
> - DH_DDR3_SIZE_512MIB = 0x01,
> - DH_DDR3_SIZE_1GIB = 0x02,
> - DH_DDR3_SIZE_2GIB = 0x03
> -};
> -
> -#define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
> -#define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
> -
> -enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
> -{
> - enum dhcom_ddr3_code ddr3_code;
> -
> - gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
> - gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
> -
> - gpio_direction_input(DDR3_CODE_BIT_0);
> - gpio_direction_input(DDR3_CODE_BIT_1);
> -
> - /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
> - ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
> - | (!!gpio_get_value(DDR3_CODE_BIT_0));
> -
> - return ddr3_code;
> -}
> -
> -/* GPIO */
> -static iomux_v3_cfg_t const gpio_pads[] = {
> - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_gpio(void)
> -{
> - SETUP_IOMUX_PADS(gpio_pads);
> -}
> -
> -/* Ethernet */
> -static iomux_v3_cfg_t const enet_pads[] = {
> - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* SMSC PHY Reset */
> - IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - /* ENET_VIO_GPIO */
> - IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - /* ENET_Interrupt - (not used) */
> - IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_enet(void)
> -{
> - SETUP_IOMUX_PADS(enet_pads);
> -}
> -
> -/* SD interface */
> -static iomux_v3_cfg_t const usdhc2_pads[] = {
> - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
> -};
> -
> -/* onboard microSD */
> -static iomux_v3_cfg_t const usdhc3_pads[] = {
> - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
> -};
> -
> -/* eMMC */
> -static iomux_v3_cfg_t const usdhc4_pads[] = {
> - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> -};
> -
> -/* SD */
> -static void setup_iomux_sd(void)
> -{
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - SETUP_IOMUX_PADS(usdhc4_pads);
> -}
> -
> -/* SPI */
> -static iomux_v3_cfg_t const ecspi1_pads[] = {
> - /* SS0 */
> - IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_spi(void)
> -{
> - SETUP_IOMUX_PADS(ecspi1_pads);
> -}
> -
> -int board_spi_cs_gpio(unsigned bus, unsigned cs)
> -{
> - if (bus == 0 && cs == 0)
> - return IMX_GPIO_NR(2, 30);
> - else
> - return -1;
> -}
> -
> -/* UART */
> -static iomux_v3_cfg_t const uart1_pads[] = {
> - IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_uart(void)
> -{
> - SETUP_IOMUX_PADS(uart1_pads);
> -}
> -
> -/* USB */
> -static iomux_v3_cfg_t const usb_pads[] = {
> - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_usb(void)
> -{
> - SETUP_IOMUX_PADS(usb_pads);
> -}
> -
> -
> -/* DRAM */
> -static void dhcom_spl_dram_init(void)
> -{
> - enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
> -
> - if (is_mx6dq()) {
> - mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
> - &dhcom6dq_grp_ioregs);
> - switch (ddr3_code) {
> - default:
> - printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
> - printf(" choosing 1024 MB\n");
> - /* fall through */
> - case DH_DDR3_SIZE_1GIB:
> - mx6_dram_cfg(&dhcom_ddr_64bit,
> - &dhcom_mmdc_calib_4x2g_1066,
> - &dhcom_mem_ddr_2g);
> - break;
> - case DH_DDR3_SIZE_2GIB:
> - mx6_dram_cfg(&dhcom_ddr_64bit,
> - &dhcom_mmdc_calib_4x4g_1066,
> - &dhcom_mem_ddr_4g);
> - break;
> - }
> -
> - /* Perform DDR DRAM calibration */
> - udelay(100);
> - mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
> -
> - } else if (is_cpu_type(MXC_CPU_MX6DL)) {
> - mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
> - &dhcom6sdl_grp_ioregs);
> - switch (ddr3_code) {
> - default:
> - printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
> - printf(" choosing 1024 MB\n");
> - /* fall through */
> - case DH_DDR3_SIZE_1GIB:
> - mx6_dram_cfg(&dhcom_ddr_64bit,
> - &dhcom_mmdc_calib_4x2g_800,
> - &dhcom_mem_ddr_2g);
> - break;
> - }
> -
> - /* Perform DDR DRAM calibration */
> - udelay(100);
> - mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
> -
> - } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
> - mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
> - &dhcom6sdl_grp_ioregs);
> - switch (ddr3_code) {
> - default:
> - printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
> - printf(" choosing 512 MB\n");
> - /* fall through */
> - case DH_DDR3_SIZE_512MIB:
> - mx6_dram_cfg(&dhcom_ddr_32bit,
> - &dhcom_mmdc_calib_2x2g_800,
> - &dhcom_mem_ddr_2g);
> - break;
> - case DH_DDR3_SIZE_1GIB:
> - mx6_dram_cfg(&dhcom_ddr_32bit,
> - &dhcom_mmdc_calib_2x4g_800,
> - &dhcom_mem_ddr_4g);
> - break;
> - }
> -
> - /* Perform DDR DRAM calibration */
> - udelay(100);
> - mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
> - }
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> - /* setup AIPS and disable watchdog */
> - arch_cpu_init();
> -
> - ccgr_init();
> - gpr_init();
> -
> - /* setup GP timer */
> - timer_init();
> -
> - setup_iomux_boardid();
> - setup_iomux_ddrcode();
> - setup_iomux_gpio();
> - setup_iomux_enet();
> - setup_iomux_sd();
> - setup_iomux_spi();
> - setup_iomux_uart();
> - setup_iomux_usb();
> -
> - /* UART clocks enabled and gd valid - init serial console */
> - preloader_console_init();
> -
> - /* DDR3 initialization */
> - dhcom_spl_dram_init();
> -
> - /* Clear the BSS. */
> - memset(__bss_start, 0, __bss_end - __bss_start);
> -
> - /* load/boot image from boot device */
> - board_init_r(NULL, 0);
> -}
> diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
> deleted file mode 100644
> index 92b23778ef0..00000000000
> --- a/configs/dh_imx6_defconfig
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_MX6=y
> -CONFIG_SYS_TEXT_BASE=0x17800000
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_MX6_DDRCAL=y
> -CONFIG_TARGET_DHCOMIMX6=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_SPI_FLASH_SUPPORT=y
> -CONFIG_SPL_SPI_SUPPORT=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> -CONFIG_FIT=y
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> -CONFIG_BOOTDELAY=3
> -# CONFIG_USE_BOOTCOMMAND is not set
> -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_SPI_LOAD=y
> -CONFIG_SPL_WATCHDOG_SUPPORT=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_CMD_UNZIP=y
> -CONFIG_CMD_DFU=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SATA=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_USB_MASS_STORAGE=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_TIME=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_DWC_AHSATA=y
> -CONFIG_BOOTCOUNT_LIMIT=y
> -CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
> -CONFIG_FSL_ESDHC=y
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_GIGADEVICE=y
> -CONFIG_SPI_FLASH_MACRONIX=y
> -CONFIG_SPI_FLASH_SPANSION=y
> -CONFIG_SPI_FLASH_WINBOND=y
> -CONFIG_PHYLIB=y
> -CONFIG_PHY_MICREL=y
> -CONFIG_PHY_MICREL_KSZ90X1=y
> -CONFIG_FEC_MXC=y
> -CONFIG_MII=y
> -CONFIG_SPI=y
> -CONFIG_MXC_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_GADGET=y
> -CONFIG_USB_GADGET_MANUFACTURER="dh"
> -CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> -CONFIG_CI_UDC=y
> -CONFIG_USB_GADGET_DOWNLOAD=y
> -CONFIG_IMX_WATCHDOG=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
> deleted file mode 100644
> index 9231bd853f4..00000000000
> --- a/include/configs/dh_imx6.h
> +++ /dev/null
> @@ -1,178 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * DHCOM DH-iMX6 PDK board configuration
> - *
> - * Copyright (C) 2017 Marek Vasut <marex@denx.de>
> - */
> -
> -#ifndef __DH_IMX6_CONFIG_H
> -#define __DH_IMX6_CONFIG_H
> -
> -#include <asm/arch/imx-regs.h>
> -
> -#include "mx6_common.h"
> -
> -/*
> - * SPI NOR layout:
> - * 0x00_0000-0x00_ffff ... U-Boot SPL
> - * 0x01_0000-0x0f_ffff ... U-Boot
> - * 0x10_0000-0x10_ffff ... U-Boot env #1
> - * 0x11_0000-0x11_ffff ... U-Boot env #2
> - * 0x12_0000-0x1f_ffff ... UNUSED
> - */
> -
> -/* SPL */
> -#include "imx6_spl.h" /* common IMX6 SPL configuration */
> -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
> -#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
> -
> -/* Miscellaneous configurable options */
> -
> -#define CONFIG_CMDLINE_TAG
> -#define CONFIG_SETUP_MEMORY_TAGS
> -#define CONFIG_INITRD_TAG
> -#define CONFIG_REVISION_TAG
> -
> -#define CONFIG_BZIP2
> -
> -/* Size of malloc() pool */
> -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
> -
> -/* Bootcounter */
> -#define CONFIG_SYS_BOOTCOUNT_BE
> -
> -/* FEC ethernet */
> -#define IMX_FEC_BASE ENET_BASE_ADDR
> -#define CONFIG_FEC_XCV_TYPE RMII
> -#define CONFIG_ETHPRIME "FEC"
> -#define CONFIG_FEC_MXC_PHYADDR 0
> -#define CONFIG_ARP_TIMEOUT 200UL
> -
> -/* Fuses */
> -#ifdef CONFIG_CMD_FUSE
> -#define CONFIG_MXC_OCOTP
> -#endif
> -
> -/* I2C Configs */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_MXC
> -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> -#define CONFIG_SYS_I2C_SPEED 100000
> -
> -/* MMC Configs */
> -#define CONFIG_FSL_USDHC
> -#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> -#define CONFIG_SYS_FSL_USDHC_NUM 3
> -#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
> -
> -/* SATA Configs */
> -#ifdef CONFIG_CMD_SATA
> -#define CONFIG_SYS_SATA_MAX_DEVICE 1
> -#define CONFIG_DWC_AHSATA_PORT_ID 0
> -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
> -#define CONFIG_LBA48
> -#endif
> -
> -/* SPI Flash Configs */
> -#ifdef CONFIG_CMD_SF
> -#define CONFIG_SF_DEFAULT_BUS 0
> -#define CONFIG_SF_DEFAULT_CS 0
> -#define CONFIG_SF_DEFAULT_SPEED 25000000
> -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
> -#endif
> -
> -/* UART */
> -#define CONFIG_MXC_UART
> -#define CONFIG_MXC_UART_BASE UART1_BASE
> -#define CONFIG_BAUDRATE 115200
> -
> -/* USB Configs */
> -#ifdef CONFIG_CMD_USB
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -#define CONFIG_USB_HOST_ETHER
> -#define CONFIG_USB_ETHER_ASIX
> -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> -#define CONFIG_MXC_USB_FLAGS 0
> -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
> -
> -/* USB Gadget (DFU, UMS) */
> -#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
> -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
> -#define DFU_DEFAULT_POLL_TIMEOUT 300
> -
> -/* USB IDs */
> -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
> -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
> -#endif
> -#endif
> -
> -/* Watchdog */
> -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
> -
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_LOADADDR 0x12000000
> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> -
> -#ifndef CONFIG_SPL_BUILD
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "console=ttymxc0,115200\0" \
> - "fdt_addr=0x18000000\0" \
> - "fdt_high=0xffffffff\0" \
> - "initrd_high=0xffffffff\0" \
> - "kernel_addr_r=0x10008000\0" \
> - "fdt_addr_r=0x13000000\0" \
> - "ramdisk_addr_r=0x18000000\0" \
> - "scriptaddr=0x14000000\0" \
> - "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
> - BOOTENV
> -
> -#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
> -
> -#define BOOT_TARGET_DEVICES(func) \
> - func(MMC, mmc, 0) \
> - func(MMC, mmc, 2) \
> - func(USB, usb, 1) \
> - func(SATA, sata, 0) \
> - func(DHCP, dhcp, na)
> -
> -#include <config_distro_bootcmd.h>
> -#endif
> -
> -/* Physical Memory Map */
> -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> -
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> -
> -#define CONFIG_SYS_INIT_SP_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -
> -#define CONFIG_SYS_INIT_SP_ADDR \
> - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> -
> -#define CONFIG_SYS_MEMTEST_START 0x10000000
> -#define CONFIG_SYS_MEMTEST_END 0x20000000
> -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
> -
> -/* Environment */
> -#define CONFIG_ENV_SIZE (16 * 1024)
> -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> -
> -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> -#define CONFIG_ENV_OFFSET (1024 * 1024)
> -#define CONFIG_ENV_SECT_SIZE (64 * 1024)
> -#define CONFIG_ENV_OFFSET_REDUND \
> - (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
> -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
> -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
> -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
> -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
> -#endif
> -
> -#endif /* __DH_IMX6_CONFIG_H */
>
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 62/93] arm: Remove dh_imx6 board
2018-11-20 12:15 ` Ludwig Zenz
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Ludwig,
On Tue, 20 Nov 2018 at 05:15, Ludwig Zenz <lzenz@dh-electronics.de> wrote:
>
> On 19.11.2018 16:53, Simon Glass wrote:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> Hi Simon,
>
> CONFIG_DM_BLK does not exist. Did you mean CONFIG_BLK?
>
Yes that's right.
> I didn't know about any deadline or necessary change. I will have a look
> at it.
Please do look at the release emails for each release. These typically
have useful information for maintainers.
I am going to add a Makefile warning.
>
> NAK. The board is used.
OK, I look forward to the patch!
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 63/93] arm: Remove vinco board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (61 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 62/93] arm: Remove dh_imx6 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 64/93] arm: Remove ls1021atwr_sdcard_ifc_SECURE_BOOT board Simon Glass
` (34 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-at91/Kconfig | 1 -
board/l+g/vinco/Kconfig | 12 --
board/l+g/vinco/MAINTAINERS | 6 -
board/l+g/vinco/Makefile | 1 -
board/l+g/vinco/vinco.c | 212 ------------------------------------
configs/vinco_defconfig | 40 -------
include/configs/vinco.h | 118 --------------------
7 files changed, 390 deletions(-)
delete mode 100644 board/l+g/vinco/Kconfig
delete mode 100644 board/l+g/vinco/MAINTAINERS
delete mode 100644 board/l+g/vinco/Makefile
delete mode 100644 board/l+g/vinco/vinco.c
delete mode 100644 configs/vinco_defconfig
delete mode 100644 include/configs/vinco.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a879e79af2d..5c1791681fb 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -281,7 +281,6 @@ source "board/atmel/sama5d4ek/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
-source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig
deleted file mode 100644
index 229b5ea129f..00000000000
--- a/board/l+g/vinco/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_VINCO
-
-config SYS_BOARD
- default "vinco"
-
-config SYS_VENDOR
- default "l+g"
-
-config SYS_CONFIG_NAME
- default "vinco"
-
-endif
diff --git a/board/l+g/vinco/MAINTAINERS b/board/l+g/vinco/MAINTAINERS
deleted file mode 100644
index 0cd6044172a..00000000000
--- a/board/l+g/vinco/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VInCo Platform
-M: Gregory CLEMENT <gregory.clement@free-electrons.com>
-S: Maintained
-F: board/l+g/vinco
-F: include/configs/vinco.h
-F: configs/vinco_defconfig
diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile
deleted file mode 100644
index a2b8a2bc4a4..00000000000
--- a/board/l+g/vinco/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += vinco.o
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
deleted file mode 100644
index 029ab123918..00000000000
--- a/board/l+g/vinco/vinco.c
+++ /dev/null
@@ -1,212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board file for the VInCo platform
- * Based on the the SAMA5-EK board file
- * Configuration settings for the VInCo platform.
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- * Copyright (C) 2015 Free Electrons
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/sama5d3_smc.h>
-#include <asm/arch/sama5d4.h>
-#include <atmel_hlcdc.h>
-#include <atmel_mci.h>
-#include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-#include <spi.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* FIXME gpio code here need to handle through DM_GPIO */
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void vinco_spi0_hw_init(void)
-{
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
- at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
-
- at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_ATMEL_SPI */
-
-
-#ifdef CONFIG_CMD_USB
-static void vinco_usb_hw_init(void)
-{
- at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
- at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
- at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
-}
-#endif
-
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void vinco_mci0_hw_init(void)
-{
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
- at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
-
- /*
- * As the mci io internal pull down is too strong, so if the io needs
- * external pull up, the pull up resistor will be very small, if so
- * the power consumption will increase, so disable the interanl pull
- * down to save the power.
- */
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
- at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_MCI0);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- /* Enable power for MCI0 interface */
- at91_set_pio_output(AT91_PIO_PORTE, 7, 1);
-
- return atmel_mci_init((void *)ATMEL_BASE_MCI0);
-}
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
-
-#ifdef CONFIG_MACB
-void vinco_macb0_hw_init(void)
-{
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
- at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_GMAC0);
-
- /* Enable Phy*/
- at91_set_pio_output(AT91_PIO_PORTE, 8, 1);
-}
-#endif
-
-static void vinco_serial3_hw_init(void)
-{
- at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
- at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART3);
-}
-
-int board_early_init_f(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIOD);
- at91_periph_clk_enable(ATMEL_ID_PIOE);
-
- vinco_serial3_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifndef CONFIG_DM_SPI
- vinco_spi0_hw_init();
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
- vinco_mci0_hw_init();
-#endif
-#ifdef CONFIG_MACB
- vinco_macb0_hw_init();
-#endif
-#ifdef CONFIG_CMD_USB
- vinco_usb_hw_init();
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- at91_udp_hw_init();
-#endif
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
- usb_eth_initialize(bis);
-#endif
-#endif
-
- return rc;
-}
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
deleted file mode 100644
index 0130ad43377..00000000000
--- a/configs/vinco_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x20f00000
-CONFIG_TARGET_VINCO=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="vinco => "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPT=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="L+G VInCo"
-CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
deleted file mode 100644
index 9d6001ff03c..00000000000
--- a/include/configs/vinco.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for the VInCo platform.
- *
- * Based on the settings for the SAMA5-EK board
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- * Copyright (C) 2015 Free Electrons
- * Gregory CLEMENT gregory.clement at free-electrons.com
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "at91-sama5_common.h"
-
-/* The value in the common file is too far away for the VInCo platform */
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE 0xfc00c000
-#define CONFIG_USART_ID 30
-
-/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x4000000
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
-/* SerialFlash */
-
-#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 50000000
-#define CONFIG_ENV_SPI_MAX_HZ 50000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
-#endif
-
-/* MMC */
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_GENERIC_ATMEL_MCI
-#define ATMEL_BASE_MMCI 0xfc000000
-#define CONFIG_SYS_MMC_CLK_OD 500000
-
-/* For generating MMC partitions */
-
-#endif
-
-/* USB device */
-
-/* Ethernet Hardware */
-#define CONFIG_PHY_SMSC
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-
-#ifdef CONFIG_SPI_BOOT
-/* bootstrap + u-boot + env + linux in serial flash */
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-/* Use our own mapping for the VInCo platform */
-#undef CONFIG_ENV_OFFSET
-#undef CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x10000
-
-/* Update the bootcommand according to our mapping for the VInCo platform */
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "mmc dev 0 0;" \
- "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \
- "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \
- "bootz ${loadaddr} - ${oftaddr}"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_start=0x20000\0" \
- "kernel_size=0x800000\0" \
- "mmcblksize=0x200\0" \
- "oftaddr=0x21000000\0" \
- "loadaddr=0x22000000\0" \
- "update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \
- "sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \
- "create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \
- "setexpr rootfs_start ${kernel_start} + ${kernel_size};" \
- "setenv partitions 'name=kernel,size=${kernel_size}," \
- "start=${kernel_start};name=rootfs,size=-';" \
- "gpt write mmc 0 ${partitions} \0"\
- "f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \
- "setexpr fileblksize ${fileblksize} + 1\0" \
- "store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \
- "setexpr k_blksize ${fileblksize};" \
- "setexpr k_offset ${kernel_start} / ${mmcblksize};" \
- "mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \
- "store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \
- "setexpr dtb_blksize ${fileblksize};" \
- "setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \
- "mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \
- "store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \
- "setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \
- "mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \
- "bootdelay=0\0"
-
-#endif
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 64/93] arm: Remove ls1021atwr_sdcard_ifc_SECURE_BOOT board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (62 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 63/93] arm: Remove vinco board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 65/93] arm: Remove mx6cuboxi board Simon Glass
` (33 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/freescale/ls1021atwr/Kconfig | 17 -
board/freescale/ls1021atwr/MAINTAINERS | 15 -
board/freescale/ls1021atwr/Makefile | 9 -
board/freescale/ls1021atwr/README | 115 ---
board/freescale/ls1021atwr/dcu.c | 46 --
board/freescale/ls1021atwr/ls1021atwr.c | 764 ------------------
board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 -
.../ls1021atwr/ls102xa_rcw_sd_ifc.cfg | 8 -
.../ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 8 -
board/freescale/ls1021atwr/psci.S | 24 -
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 56 --
configs/ls1021atwr_nor_defconfig | 59 --
configs/ls1021atwr_nor_lpuart_defconfig | 57 --
configs/ls1021atwr_qspi_defconfig | 60 --
...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 70 --
configs/ls1021atwr_sdcard_ifc_defconfig | 67 --
configs/ls1021atwr_sdcard_qspi_defconfig | 70 --
include/configs/ls1021atwr.h | 505 ------------
19 files changed, 1963 deletions(-)
delete mode 100644 board/freescale/ls1021atwr/Kconfig
delete mode 100644 board/freescale/ls1021atwr/MAINTAINERS
delete mode 100644 board/freescale/ls1021atwr/Makefile
delete mode 100644 board/freescale/ls1021atwr/README
delete mode 100644 board/freescale/ls1021atwr/dcu.c
delete mode 100644 board/freescale/ls1021atwr/ls1021atwr.c
delete mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg
delete mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
delete mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
delete mode 100644 board/freescale/ls1021atwr/psci.S
delete mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1021atwr_nor_defconfig
delete mode 100644 configs/ls1021atwr_nor_lpuart_defconfig
delete mode 100644 configs/ls1021atwr_qspi_defconfig
delete mode 100644 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1021atwr_sdcard_ifc_defconfig
delete mode 100644 configs/ls1021atwr_sdcard_qspi_defconfig
delete mode 100644 include/configs/ls1021atwr.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6cadd96378b..97faf09e916 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1508,7 +1508,6 @@ source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
-source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
deleted file mode 100644
index a4641cbca09..00000000000
--- a/board/freescale/ls1021atwr/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if TARGET_LS1021ATWR
-
-config SYS_BOARD
- default "ls1021atwr"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "ls102xa"
-
-config SYS_CONFIG_NAME
- default "ls1021atwr"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
deleted file mode 100644
index c8b93c64697..00000000000
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-LS1021ATWR BOARD
-M: Alison Wang <alison.wang@nxp.com>
-S: Maintained
-F: board/freescale/ls1021atwr/
-F: include/configs/ls1021atwr.h
-F: configs/ls1021atwr_nor_defconfig
-F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
-F: configs/ls1021atwr_nor_lpuart_defconfig
-F: configs/ls1021atwr_sdcard_ifc_defconfig
-F: configs/ls1021atwr_sdcard_qspi_defconfig
-F: configs/ls1021atwr_qspi_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
-F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
deleted file mode 100644
index d9a2f52f2b6..00000000000
--- a/board/freescale/ls1021atwr/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ls1021atwr.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
-obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README
deleted file mode 100644
index 896a6594768..00000000000
--- a/board/freescale/ls1021atwr/README
+++ /dev/null
@@ -1,115 +0,0 @@
-Overview
---------
-The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
-
-LS1021A SoC Overview
-------------------
-The QorIQ LS1 family, which includes the LS1021A communications processor,
-is built on Layerscape architecture, the industry's first software-aware,
-core-agnostic networking architecture to offer unprecedented efficiency
-and scale.
-
-A member of the value-performance tier, the QorIQ LS1021A processor provides
-extensive integration and power efficiency for fanless, small form factor
-enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
-running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
-performance of over 6,000, as well as virtualization support, advanced
-security features and the broadest array of high-speed interconnects and
-optimized peripheral features ever offered in a sub-3 W processor.
-
-The QorIQ LS1021A processor features an integrated LCD controller,
-CAN controller for implementing industrial protocols, DDR3L/4 running
-up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
-protection on both L1 and L2 caches. The LS1021A processor is pin- and
-software-compatible with the QorIQ LS1020A and LS1022A processors.
-
-The LS1021A SoC includes the following function and features:
-
- - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
- - Dual high-preformance ARM Cortex-A7 cores, each core includes:
- - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
- - 512 Kbyte shared coherent L2 Cache (with ECC protection)
- - NEON Co-processor (per core)
- - 40-bit physical addressing
- - Vector floating-point support
- - ARM Core-Link CCI-400 Cache Coherent Interconnect
- - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
- supporting speeds up to 1600Mtps
- - ECC and interleaving support
- - VeTSEC Ethernet complex
- - Up to 3x virtualized 10/100/1000 Ethernet controllers
- - MII, RMII, RGMII, and SGMII support
- - QoS, lossless flow control, and IEEE 1588 support
- - 4-lane 6GHz SerDes
- - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
- - Two PCI Express Gen2 controllers running at up to 5 GHz
- - One Serial ATA 3.0 supporting 6 GT/s operation
- - Two SGMII interfaces supporting 1000 Mbps
- - Additional peripheral interfaces
- - One high-speed USB 3.0 controller with integrated PHY and one high-speed
- USB 2.00 controller with ULPI
- - Integrated flash controller (IFC) with 16-bit interface
- - Quad SPI NOR Flash
- - One enhanced Secure digital host controller
- - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
- - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
- UARTs
- - Three I2C controllers
- - Eight FlexTimers four supporting PWM and four FlexCAN ports
- - Four GPIO controllers supporting up to 109 general purpose I/O signals
- - Integrated advanced audio block:
- - Four synchronous audio interfaces (SAI)
- - Sony/Philips Digital Interconnect Format (SPDIF)
- - Asynchronous Sample Rate Converter (ASRC)
- - Hardware based crypto offload engine
- - IPSec forwarding at up to 1Gbps
- - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
- - Public key hardware accelerator
- - True Random Number Generator (NIST Certified)
- - Advanced Encryption Standard Accelerators (AESA)
- - Data Encryption Standard Accelerators
- - QUICC Engine ULite block
- - Two universal communication controllers (TDM and HDLC) supporting 64
- multichannels, each running at 64 Kbps
- - Support for 256 channels of HDLC
- - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
-
-LS1021ATWR board Overview
--------------------------
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP SDRAM.
- - IFC/Local Bus
- - NOR: 128MB 16-bit NOR Flash
- - Ethernet
- - Three on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
- - System and DDR clock (SYSCLK, DDRCLK)
- - SERDES clocks
- - Power Supplies
- - SDHC
- - SDHC/SDXC connector
- - Other IO
- - One Serial port
- - Three I2C ports
-
-Memory map
------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
-0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
-0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
-0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
-0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
-0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
-
-LS1021a rev1.0 Soc specific Options/Settings
---------------------------------------------
-If the LS1021a Soc is rev1.0, you need modify the configure file.
-Add the following define in include/configs/ls1021atwr.h:
-#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
deleted file mode 100644
index e1191f134cb..00000000000
--- a/board/freescale/ls1021atwr/dcu.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * FSL DCU Framebuffer driver
- */
-
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include "div64.h"
-#include "../common/dcu_sii9022a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned int dcu_set_pixel_clock(unsigned int pixclock)
-{
- unsigned long long div;
-
- div = (unsigned long long)(gd->bus_clk / 1000);
- div *= (unsigned long long)pixclock;
- do_div(div, 1000000000);
-
- return div;
-}
-
-int platform_dcu_init(unsigned int xres, unsigned int yres,
- const char *port,
- struct fb_videomode *dcu_fb_videomode)
-{
- const char *name;
- unsigned int pixel_format;
-
- if (strncmp(port, "twr_lcd", 4) == 0) {
- name = "TWR_LCD_RGB card";
- } else {
- name = "HDMI";
- dcu_set_dvi_encoder(dcu_fb_videomode);
- }
-
- printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
-
- pixel_format = 32;
- fsl_dcu_init(xres, yres, pixel_format);
-
- return 0;
-}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
deleted file mode 100644
index dcd6d933ea8..00000000000
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ /dev/null
@@ -1,764 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ls102xa_devdis.h>
-#include <asm/arch/ls102xa_soc.h>
-#include <hwconfig.h>
-#include <mmc.h>
-#include <fsl_csu.h>
-#include <fsl_esdhc.h>
-#include <fsl_ifc.h>
-#include <fsl_immap.h>
-#include <netdev.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <fsl_sec.h>
-#include <fsl_devdis.h>
-#include <spl.h>
-#include "../common/sleep.h"
-#ifdef CONFIG_U_QE
-#include <fsl_qe.h>
-#endif
-#include <fsl_validate.h>
-
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define VERSION_MASK 0x00FF
-#define BANK_MASK 0x0001
-#define CONFIG_RESET 0x1
-#define INIT_RESET 0x1
-
-#define CPLD_SET_MUX_SERDES 0x20
-#define CPLD_SET_BOOT_BANK 0x40
-
-#define BOOT_FROM_UPPER_BANK 0x0
-#define BOOT_FROM_LOWER_BANK 0x1
-
-#define LANEB_SATA (0x01)
-#define LANEB_SGMII1 (0x02)
-#define LANEC_SGMII1 (0x04)
-#define LANEC_PCIEX1 (0x08)
-#define LANED_PCIEX2 (0x10)
-#define LANED_SGMII2 (0x20)
-
-#define MASK_LANE_B 0x1
-#define MASK_LANE_C 0x2
-#define MASK_LANE_D 0x4
-#define MASK_SGMII 0x8
-
-#define KEEP_STATUS 0x0
-#define NEED_RESET 0x1
-
-#define SOFT_MUX_ON_I2C3_IFC 0x2
-#define SOFT_MUX_ON_CAN3_USB2 0x8
-#define SOFT_MUX_ON_QE_LCD 0x10
-
-#define PIN_I2C3_IFC_MUX_I2C3 0x0
-#define PIN_I2C3_IFC_MUX_IFC 0x1
-#define PIN_CAN3_USB2_MUX_USB2 0x0
-#define PIN_CAN3_USB2_MUX_CAN3 0x1
-#define PIN_QE_LCD_MUX_LCD 0x0
-#define PIN_QE_LCD_MUX_QE 0x1
-
-struct cpld_data {
- u8 cpld_ver; /* cpld revision */
- u8 cpld_ver_sub; /* cpld sub revision */
- u8 pcba_ver; /* pcb revision number */
- u8 system_rst; /* reset system by cpld */
- u8 soft_mux_on; /* CPLD override physical switches Enable */
- u8 cfg_rcw_src1; /* Reset config word 1 */
- u8 cfg_rcw_src2; /* Reset config word 2 */
- u8 vbank; /* Flash bank selection Control */
- u8 gpio; /* GPIO for TWR-ELEV */
- u8 i2c3_ifc_mux;
- u8 mux_spi2;
- u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
- u8 qe_lcd_mux; /* QE and LCD Selection */
- u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
- u8 global_rst; /* reset with init CPLD reg to default */
- u8 rev1; /* Reserved */
- u8 rev2; /* Reserved */
-};
-
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-static void cpld_show(void)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
- in_8(&cpld_data->cpld_ver) & VERSION_MASK,
- in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
- in_8(&cpld_data->pcba_ver) & VERSION_MASK,
- in_8(&cpld_data->vbank) & BANK_MASK);
-
-#ifdef CONFIG_DEBUG
- printf("soft_mux_on =%x\n",
- in_8(&cpld_data->soft_mux_on));
- printf("cfg_rcw_src1 =%x\n",
- in_8(&cpld_data->cfg_rcw_src1));
- printf("cfg_rcw_src2 =%x\n",
- in_8(&cpld_data->cfg_rcw_src2));
- printf("vbank =%x\n",
- in_8(&cpld_data->vbank));
- printf("gpio =%x\n",
- in_8(&cpld_data->gpio));
- printf("i2c3_ifc_mux =%x\n",
- in_8(&cpld_data->i2c3_ifc_mux));
- printf("mux_spi2 =%x\n",
- in_8(&cpld_data->mux_spi2));
- printf("can3_usb2_mux =%x\n",
- in_8(&cpld_data->can3_usb2_mux));
- printf("qe_lcd_mux =%x\n",
- in_8(&cpld_data->qe_lcd_mux));
- printf("serdes_mux =%x\n",
- in_8(&cpld_data->serdes_mux));
-#endif
-}
-#endif
-
-int checkboard(void)
-{
- puts("Board: LS1021ATWR\n");
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
- cpld_show();
-#endif
-
- return 0;
-}
-
-void ddrmc_init(void)
-{
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
- u32 temp_sdram_cfg, tmp;
-
- out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
-
- out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
- out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
-
- out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
- out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
- out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
- out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
- out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
- out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
-
-#ifdef CONFIG_DEEP_SLEEP
- if (is_warm_boot()) {
- out_be32(&ddr->sdram_cfg_2,
- DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
- out_be32(&ddr->init_ext_addr, (1 << 31));
-
- /* DRAM VRef will not be trained */
- out_be32(&ddr->ddr_cdr2,
- DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
- } else
-#endif
- {
- out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
- out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
- }
-
- out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
- out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
-
- out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
-
- out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
-
- out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
- out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
-
- out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
-
- out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
- out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
-
- out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
-
- /* DDR erratum A-009942 */
- tmp = in_be32(&ddr->debug[28]);
- out_be32(&ddr->debug[28], tmp | 0x0070006f);
-
- udelay(1);
-
-#ifdef CONFIG_DEEP_SLEEP
- if (is_warm_boot()) {
- /* enter self-refresh */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
- temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
- out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
-
- temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
- } else
-#endif
- temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
-
- out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
-
-#ifdef CONFIG_DEEP_SLEEP
- if (is_warm_boot()) {
- /* exit self-refresh */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
- temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
- out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
- }
-#endif
-}
-
-int dram_init(void)
-{
-#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- ddrmc_init();
-#endif
-
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
- fsl_dp_resume();
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {CONFIG_SYS_FSL_ESDHC_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-static void convert_serdes_mux(int type, int need_reset)
-{
- char current_serdes;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- current_serdes = cpld_data->serdes_mux;
-
- switch (type) {
- case LANEB_SATA:
- current_serdes &= ~MASK_LANE_B;
- break;
- case LANEB_SGMII1:
- current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
- break;
- case LANEC_SGMII1:
- current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
- break;
- case LANED_SGMII2:
- current_serdes |= MASK_LANE_D;
- break;
- case LANEC_PCIEX1:
- current_serdes |= MASK_LANE_C;
- break;
- case (LANED_PCIEX2 | LANEC_PCIEX1):
- current_serdes |= MASK_LANE_C;
- current_serdes &= ~MASK_LANE_D;
- break;
- default:
- printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
- return;
- }
-
- cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
- cpld_data->serdes_mux = current_serdes;
-
- if (need_reset == 1) {
- printf("Reset board to enable configuration\n");
- cpld_data->system_rst = CONFIG_RESET;
- }
-}
-
-int config_serdes_mux(void)
-{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
-
- protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
- switch (protocol) {
- case 0x10:
- convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
- convert_serdes_mux(LANED_PCIEX2 |
- LANEC_PCIEX1, KEEP_STATUS);
- break;
- case 0x20:
- convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
- convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
- convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
- break;
- case 0x30:
- convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
- convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
- convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
- break;
- case 0x70:
- convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
- convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
- convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
- break;
- }
-
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-int config_board_mux(void)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- int conflict_flag;
-
- conflict_flag = 0;
- if (hwconfig("i2c3")) {
- conflict_flag++;
- cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
- cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
- }
-
- if (hwconfig("ifc")) {
- conflict_flag++;
- /* some signals can not enable simultaneous*/
- if (conflict_flag > 1)
- goto conflict;
- cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
- cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
- }
-
- conflict_flag = 0;
- if (hwconfig("usb2")) {
- conflict_flag++;
- cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
- cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
- }
-
- if (hwconfig("can3")) {
- conflict_flag++;
- /* some signals can not enable simultaneous*/
- if (conflict_flag > 1)
- goto conflict;
- cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
- cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
- }
-
- conflict_flag = 0;
- if (hwconfig("lcd")) {
- conflict_flag++;
- cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
- cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
- }
-
- if (hwconfig("qe")) {
- conflict_flag++;
- /* some signals can not enable simultaneous*/
- if (conflict_flag > 1)
- goto conflict;
- cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
- cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
- }
-
- return 0;
-
-conflict:
- printf("WARNING: pin conflict! MUX setting may failed!\n");
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-#ifdef CONFIG_TSEC_ENET
- /* clear BD & FR bits for BE BD's and frame data */
- clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
-#endif
-
-#ifdef CONFIG_FSL_IFC
- init_early_memctl_regs();
-#endif
-
- arch_soc_init();
-
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot()) {
- timer_init();
- dram_init();
- }
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
- void (*second_uboot)(void);
-
- /* Clear the BSS */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- get_clocks();
-
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- preloader_console_init();
-
- dram_init();
-
- /* Allow OCRAM access permission as R/W */
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
-
- /*
- * if it is woken up from deep sleep, then jump to second
- * stage uboot and continue executing without recopying
- * it from SD since it has already been reserved in memeory
- * in last boot.
- */
- if (is_warm_boot()) {
- second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
- second_uboot();
- }
-
- board_init_r(NULL, 0);
-}
-#endif
-
-#ifdef CONFIG_DEEP_SLEEP
-/* program the regulator (MC34VR500) to support deep sleep */
-void ls1twr_program_regulator(void)
-{
- unsigned int i2c_bus;
- u8 i2c_device_id;
-
-#define LS1TWR_I2C_BUS_MC34VR500 1
-#define MC34VR500_ADDR 0x8
-#define MC34VR500_DEVICEID 0x4
-#define MC34VR500_DEVICEID_MASK 0x0f
-
- i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
- i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
- MC34VR500_DEVICEID_MASK;
- if (i2c_device_id != MC34VR500_DEVICEID) {
- printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
- return;
- }
-
- i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
- i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
- i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
- i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
- i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
-
- i2c_set_bus_num(i2c_bus);
-}
-#endif
-
-int board_init(void)
-{
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
- erratum_a010315();
-#endif
-
-#ifndef CONFIG_SYS_FSL_NO_SERDES
- fsl_serdes_init();
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
- config_serdes_mux();
-#endif
-#endif
-
- ls102xa_smmu_stream_id_init();
-
-#ifdef CONFIG_U_QE
- u_qe_init();
-#endif
-
-#ifdef CONFIG_DEEP_SLEEP
- ls1twr_program_regulator();
-#endif
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD)
-void spl_board_init(void)
-{
- ls102xa_smmu_stream_id_init();
-}
-#endif
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_CHAIN_OF_TRUST
- fsl_setenv_chain_of_trust();
-#endif
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
-#ifdef CONFIG_FSL_DEVICE_DISABLE
- device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
- config_board_mux();
-#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
-}
-#endif
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_sleep_prepare(void)
-{
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
-}
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-
-u8 flash_read8(void *addr)
-{
- return __raw_readb(addr + 1);
-}
-
-void flash_write16(u16 val, void *addr)
-{
- u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
-
- __raw_writew(shftval, addr);
-}
-
-u16 flash_read16(void *addr)
-{
- u16 val = __raw_readw(addr);
-
- return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
-}
-
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
- && !defined(CONFIG_SPL_BUILD)
-static void convert_flash_bank(char bank)
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- printf("Now switch to boot from flash bank %d.\n", bank);
- cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
- cpld_data->vbank = bank;
-
- printf("Reset board to enable configuration.\n");
- cpld_data->system_rst = CONFIG_RESET;
-}
-
-static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- if (argc != 2)
- return CMD_RET_USAGE;
- if (strcmp(argv[1], "0") == 0)
- convert_flash_bank(BOOT_FROM_UPPER_BANK);
- else if (strcmp(argv[1], "1") == 0)
- convert_flash_bank(BOOT_FROM_LOWER_BANK);
- else
- return CMD_RET_USAGE;
-
- return 0;
-}
-
-U_BOOT_CMD(
- boot_bank, 2, 0, flash_bank_cmd,
- "Flash bank Selection Control",
- "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
-);
-
-static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- if (argc > 2)
- return CMD_RET_USAGE;
- if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
- cpld_data->system_rst = CONFIG_RESET;
- else if (strcmp(argv[1], "init") == 0)
- cpld_data->global_rst = INIT_RESET;
- else
- return CMD_RET_USAGE;
-
- return 0;
-}
-
-U_BOOT_CMD(
- cpld_reset, 2, 0, cpld_reset_cmd,
- "Reset via CPLD",
- "conf\n"
- " -reset with current CPLD configuration\n"
- "init\n"
- " -reset and initial CPLD configuration with default value"
-
-);
-
-static void print_serdes_mux(void)
-{
- char current_serdes;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
- current_serdes = cpld_data->serdes_mux;
-
- printf("Serdes Lane B: ");
- if ((current_serdes & MASK_LANE_B) == 0)
- printf("SATA,\n");
- else
- printf("SGMII 1,\n");
-
- printf("Serdes Lane C: ");
- if ((current_serdes & MASK_LANE_C) == 0)
- printf("SGMII 1,\n");
- else
- printf("PCIe,\n");
-
- printf("Serdes Lane D: ");
- if ((current_serdes & MASK_LANE_D) == 0)
- printf("PCIe,\n");
- else
- printf("SGMII 2,\n");
-
- printf("SGMII 1 is on lane ");
- if ((current_serdes & MASK_SGMII) == 0)
- printf("C.\n");
- else
- printf("B.\n");
-}
-
-static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- if (argc != 2)
- return CMD_RET_USAGE;
- if (strcmp(argv[1], "sata") == 0) {
- printf("Set serdes lane B to SATA.\n");
- convert_serdes_mux(LANEB_SATA, NEED_RESET);
- } else if (strcmp(argv[1], "sgmii1b") == 0) {
- printf("Set serdes lane B to SGMII 1.\n");
- convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
- } else if (strcmp(argv[1], "sgmii1c") == 0) {
- printf("Set serdes lane C to SGMII 1.\n");
- convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
- } else if (strcmp(argv[1], "sgmii2") == 0) {
- printf("Set serdes lane D to SGMII 2.\n");
- convert_serdes_mux(LANED_SGMII2, NEED_RESET);
- } else if (strcmp(argv[1], "pciex1") == 0) {
- printf("Set serdes lane C to PCIe X1.\n");
- convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
- } else if (strcmp(argv[1], "pciex2") == 0) {
- printf("Set serdes lane C & lane D to PCIe X2.\n");
- convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
- } else if (strcmp(argv[1], "show") == 0) {
- print_serdes_mux();
- } else {
- return CMD_RET_USAGE;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- lane_bank, 2, 0, serdes_mux_cmd,
- "Multiplexed function setting for SerDes Lanes",
- "sata\n"
- " -change lane B to sata\n"
- "lane_bank sgmii1b\n"
- " -change lane B to SGMII1\n"
- "lane_bank sgmii1c\n"
- " -change lane C to SGMII1\n"
- "lane_bank sgmii2\n"
- " -change lane D to SGMII2\n"
- "lane_bank pciex1\n"
- " -change lane C to PCIeX1\n"
- "lane_bank pciex2\n"
- " -change lane C & lane D to PCIeX2\n"
- "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
-);
-#endif
diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
deleted file mode 100644
index f1a1b63ab77..00000000000
--- a/board/freescale/ls1021atwr/ls102xa_pbi.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#PBI commands
-
-09570200 ffffffff
-09570158 00000300
-8940007c 21f47300
-
-#Configure Scratch register
-09ee0200 10000000
-#Configure alternate space
-09570158 00001000
-#Flush PBL data
-096100c0 000FFFFF
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
deleted file mode 100644
index f94997d5384..00000000000
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-
-#enable IFC, disable QSPI and DSPI
-0608000c 00000000 00000000 00000000
-30000000 00007900 60040a00 21046000
-00000000 00000000 00000000 20000000
-00080000 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
deleted file mode 100644
index 541b604cffc..00000000000
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-
-#disable IFC, enable QSPI and DSPI
-0608000c 00000000 00000000 00000000
-30000000 00007900 60040a00 21046000
-00000000 00000000 00000000 20000000
-20024800 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S
deleted file mode 100644
index 3c093aa33cb..00000000000
--- a/board/freescale/ls1021atwr/psci.S
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 NXP Semiconductor.
- * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-#include <asm/armv7.h>
-#include <asm/psci.h>
-
- .pushsection ._secure.text, "ax"
-
- .arch_extension sec
-
- .align 5
-
-.globl psci_system_off
-psci_system_off:
-1: wfi
- b 1b
-
- .popsection
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
deleted file mode 100644
index 97ffa21228e..00000000000
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_BMP=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
deleted file mode 100644
index 582f52151fa..00000000000
--- a/configs/ls1021atwr_nor_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_BMP=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_DM=y
-CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_DM_SCSI=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
deleted file mode 100644
index a567c07062c..00000000000
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_BMP=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
deleted file mode 100644
index 1bcf56aa5d6..00000000000
--- a/configs/ls1021atwr_qspi_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_BMP=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
deleted file mode 100644
index 44e59d2acc0..00000000000
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_BOOTDELAY=0
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_BMP=y
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
deleted file mode 100644
index 4824a83fb46..00000000000
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_BMP=y
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
deleted file mode 100644
index 4b01bc42f0e..00000000000
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021ATWR=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_BMP=y
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
deleted file mode 100644
index 2c91ae783b5..00000000000
--- a/include/configs/ls1021atwr.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ARMV7_PSCI_1_0
-
-#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-
-#define CONFIG_SYS_FSL_CLK
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_DEEP_SLEEP
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-
-#define DDR_SDRAM_CFG 0x470c0008
-#define DDR_CS0_BNDS 0x008000bf
-#define DDR_CS0_CONFIG 0x80014302
-#define DDR_TIMING_CFG_0 0x50550004
-#define DDR_TIMING_CFG_1 0xbcb38c56
-#define DDR_TIMING_CFG_2 0x0040d120
-#define DDR_TIMING_CFG_3 0x010e1000
-#define DDR_TIMING_CFG_4 0x00000001
-#define DDR_TIMING_CFG_5 0x03401400
-#define DDR_SDRAM_CFG_2 0x00401010
-#define DDR_SDRAM_MODE 0x00061c60
-#define DDR_SDRAM_MODE_2 0x00180000
-#define DDR_SDRAM_INTERVAL 0x18600618
-#define DDR_DDR_WRLVL_CNTL 0x8655f605
-#define DDR_DDR_WRLVL_CNTL_2 0x05060607
-#define DDR_DDR_WRLVL_CNTL_3 0x05050505
-#define DDR_DDR_CDR1 0x80040000
-#define DDR_DDR_CDR2 0x00000001
-#define DDR_SDRAM_CLK_CNTL 0x02000000
-#define DDR_DDR_ZQ_CNTL 0x89080600
-#define DDR_CS0_CONFIG_2 0
-#define DDR_SDRAM_CFG_MEM_EN 0x80000000
-#define SDRAM_CFG2_D_INIT 0x00000010
-#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
-#define SDRAM_CFG2_FRC_SR 0x80000000
-#define SDRAM_CFG_BI 0x00000001
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_SD_BOOT_QSPI
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
-#endif
-
-#ifdef CONFIG_SECURE_BOOT
-/*
- * HDR would be appended at end of image and copied to DDR along
- * with U-Boot image.
- */
-#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-#endif /* ifdef CONFIG_SECURE_BOOT */
-
-#define CONFIG_SPL_TEXT_BASE 0x10000000
-#define CONFIG_SPL_MAX_SIZE 0x1a000
-#define CONFIG_SPL_STACK 0x1001d000
-#define CONFIG_SPL_PAD_TO 0x1c000
-
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-#define CONFIG_SPL_BSS_START_ADDR 0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
-#ifdef CONFIG_U_BOOT_HDR_SIZE
-/*
- * HDR would be appended@end of image and copied to DDR along
- * with U-Boot image. Here u-boot max. size is 512K. So if binary
- * size increases then increase this size in case of secure boot as
- * it uses raw u-boot image instead of fit image.
- */
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
-#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
-#endif
-
-#define PHYS_SDRAM 0x80000000
-#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
- !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#endif
-
-/*
- * IFC Definitions
- */
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_FSL_IFC
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
- CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TAVDS(0x0) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) | \
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWP(0x1c) | \
- FTIM2_NOR_TWPH(0x0e))
-#define CONFIG_SYS_NOR_FTIM3 0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
-
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
-#endif
-
-/* CPLD */
-
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
-
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
- CSPR_PORT_SIZE_8 | \
- CSPR_MSEL_GPCM | \
- CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
- CSOR_NOR_NOR_MODE_AVD_NOR | \
- CSOR_NOR_TRHZ_80)
-
-/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
- FTIM0_GPCM_TEADC(0xf) | \
- FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
- FTIM2_GPCM_TCH(0xf) | \
- FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
-
-/*
- * Serial Port
- */
-#ifdef CONFIG_LPUART
-#define CONFIG_LPUART_32B_REG
-#else
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#endif
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * MMC
- */
-
-/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-/* QSPI */
-#define QSPI0_AMBA_BASE 0x40000000
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-
-/* DSPI */
-#endif
-
-/* DM SPI */
-#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_DM_SPI_FLASH
-#endif
-
-/*
- * Video
- */
-#ifdef CONFIG_VIDEO_FSL_DCU_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-
-#define CONFIG_FSL_DCU_SII9022A
-#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
-#define CONFIG_SYS_I2C_DVI_ADDR 0x39
-#endif
-
-/*
- * eTSEC
- */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC 1
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_ATHEROS
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#define CONFIG_CMDLINE_TAG
-
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 12500000
-
-#define CONFIG_HWCONFIG
-#define HWCONFIG_BUFFER_SIZE 256
-
-#define CONFIG_FSL_DEVICE_DISABLE
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0)
-#include <config_distro_bootcmd.h>
-
-#ifdef CONFIG_LPUART
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_high=0xffffffff\0" \
- "fdt_addr=0x64f00000\0" \
- "kernel_addr=0x65000000\0" \
- "scriptaddr=0x80000000\0" \
- "scripthdraddr=0x80080000\0" \
- "fdtheader_addr_r=0x80100000\0" \
- "kernelheader_addr_r=0x80200000\0" \
- "kernel_addr_r=0x81000000\0" \
- "fdt_addr_r=0x90000000\0" \
- "ramdisk_addr_r=0xa0000000\0" \
- "load_addr=0xa0000000\0" \
- "kernel_size=0x2800000\0" \
- "kernel_addr_sd=0x8000\0" \
- "kernel_size_sd=0x14000\0" \
- BOOTENV \
- "boot_scripts=ls1021atwr_boot.scr\0" \
- "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
- "scan_dev_for_boot_part=" \
- "part list ${devtype} ${devnum} devplist; " \
- "env exists devplist || setenv devplist 1; " \
- "for distro_bootpart in ${devplist}; do " \
- "if fstype ${devtype} " \
- "${devnum}:${distro_bootpart} " \
- "bootfstype; then " \
- "run scan_dev_for_boot; " \
- "fi; " \
- "done\0" \
- "scan_dev_for_boot=" \
- "echo Scanning ${devtype} " \
- "${devnum}:${distro_bootpart}...; " \
- "for prefix in ${boot_prefixes}; do " \
- "run scan_dev_for_scripts; " \
- "done;" \
- "\0" \
- "boot_a_script=" \
- "load ${devtype} ${devnum}:${distro_bootpart} " \
- "${scriptaddr} ${prefix}${script}; " \
- "env exists secureboot && load ${devtype} " \
- "${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
- "&& esbc_validate ${scripthdraddr};" \
- "source ${scriptaddr}\0" \
- "installer=load mmc 0:2 $load_addr " \
- "/flex_installer_arm32.itb; " \
- "bootm $load_addr#ls1021atwr\0" \
- "qspi_bootcmd=echo Trying load from qspi..;" \
- "sf probe && sf read $load_addr " \
- "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
- "nor_bootcmd=echo Trying load from nor..;" \
- "cp.b $kernel_addr $load_addr " \
- "$kernel_size && bootm $load_addr#$board\0"
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_high=0xffffffff\0" \
- "fdt_addr=0x64f00000\0" \
- "kernel_addr=0x61000000\0" \
- "kernelheader_addr=0x60800000\0" \
- "scriptaddr=0x80000000\0" \
- "scripthdraddr=0x80080000\0" \
- "fdtheader_addr_r=0x80100000\0" \
- "kernelheader_addr_r=0x80200000\0" \
- "kernel_addr_r=0x81000000\0" \
- "kernelheader_size=0x40000\0" \
- "fdt_addr_r=0x90000000\0" \
- "ramdisk_addr_r=0xa0000000\0" \
- "load_addr=0xa0000000\0" \
- "kernel_size=0x2800000\0" \
- "kernel_addr_sd=0x8000\0" \
- "kernel_size_sd=0x14000\0" \
- "kernelhdr_addr_sd=0x4000\0" \
- "kernelhdr_size_sd=0x10\0" \
- BOOTENV \
- "boot_scripts=ls1021atwr_boot.scr\0" \
- "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
- "scan_dev_for_boot_part=" \
- "part list ${devtype} ${devnum} devplist; " \
- "env exists devplist || setenv devplist 1; " \
- "for distro_bootpart in ${devplist}; do " \
- "if fstype ${devtype} " \
- "${devnum}:${distro_bootpart} " \
- "bootfstype; then " \
- "run scan_dev_for_boot; " \
- "fi; " \
- "done\0" \
- "scan_dev_for_boot=" \
- "echo Scanning ${devtype} " \
- "${devnum}:${distro_bootpart}...; " \
- "for prefix in ${boot_prefixes}; do " \
- "run scan_dev_for_scripts; " \
- "done;" \
- "\0" \
- "boot_a_script=" \
- "load ${devtype} ${devnum}:${distro_bootpart} " \
- "${scriptaddr} ${prefix}${script}; " \
- "env exists secureboot && load ${devtype} " \
- "${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
- "&& esbc_validate ${scripthdraddr};" \
- "source ${scriptaddr}\0" \
- "qspi_bootcmd=echo Trying load from qspi..;" \
- "sf probe && sf read $load_addr " \
- "$kernel_addr $kernel_size; env exists secureboot " \
- "&& sf read $kernelheader_addr_r $kernelheader_addr " \
- "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
- "bootm $load_addr#$board\0" \
- "nor_bootcmd=echo Trying load from nor..;" \
- "cp.b $kernel_addr $load_addr " \
- "$kernel_size; env exists secureboot " \
- "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
- "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
- "bootm $load_addr#$board\0" \
- "sd_bootcmd=echo Trying load from SD ..;" \
- "mmcinfo && mmc read $load_addr " \
- "$kernel_addr_sd $kernel_size_sd && " \
- "env exists secureboot && mmc read $kernelheader_addr_r " \
- "$kernelhdr_addr_sd $kernelhdr_size_sd " \
- " && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0"
-#endif
-
-#undef CONFIG_BOOTCOMMAND
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
- "env exists secureboot && esbc_halt"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#else
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
- "env exists secureboot && esbc_halt;"
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
-#define CONFIG_LS102XA_STREAM_ID
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
-
-/*
- * Environment
- */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x20000
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-#include <asm/fsl_secure_boot.h>
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 65/93] arm: Remove mx6cuboxi board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (63 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 64/93] arm: Remove ls1021atwr_sdcard_ifc_SECURE_BOOT board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-20 7:52 ` Mark Kettenis
2018-11-19 15:53 ` [U-Boot] [PATCH 66/93] arm: Remove ot1200 board Simon Glass
` (32 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/solidrun/mx6cuboxi/Kconfig | 12 -
board/solidrun/mx6cuboxi/MAINTAINERS | 6 -
board/solidrun/mx6cuboxi/Makefile | 7 -
board/solidrun/mx6cuboxi/README | 21 -
board/solidrun/mx6cuboxi/mx6cuboxi.c | 857 ---------------------------
configs/mx6cuboxi_defconfig | 43 --
include/configs/mx6cuboxi.h | 149 -----
8 files changed, 1096 deletions(-)
delete mode 100644 board/solidrun/mx6cuboxi/Kconfig
delete mode 100644 board/solidrun/mx6cuboxi/MAINTAINERS
delete mode 100644 board/solidrun/mx6cuboxi/Makefile
delete mode 100644 board/solidrun/mx6cuboxi/README
delete mode 100644 board/solidrun/mx6cuboxi/mx6cuboxi.c
delete mode 100644 configs/mx6cuboxi_defconfig
delete mode 100644 include/configs/mx6cuboxi.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index d05a3fa7ccf..19e259af057 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -542,7 +542,6 @@ source "board/freescale/mx6ullevk/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/seco/Kconfig"
-source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
diff --git a/board/solidrun/mx6cuboxi/Kconfig b/board/solidrun/mx6cuboxi/Kconfig
deleted file mode 100644
index 741c1754f81..00000000000
--- a/board/solidrun/mx6cuboxi/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6CUBOXI
-
-config SYS_BOARD
- default "mx6cuboxi"
-
-config SYS_VENDOR
- default "solidrun"
-
-config SYS_CONFIG_NAME
- default "mx6cuboxi"
-
-endif
diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS
deleted file mode 100644
index 81f82bc9b5e..00000000000
--- a/board/solidrun/mx6cuboxi/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX6CUBOXI BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/solidrun/mx6cuboxi/
-F: include/configs/mx6cuboxi.h
-F: configs/mx6cuboxi_defconfig
diff --git a/board/solidrun/mx6cuboxi/Makefile b/board/solidrun/mx6cuboxi/Makefile
deleted file mode 100644
index 6e5becbd27b..00000000000
--- a/board/solidrun/mx6cuboxi/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx6cuboxi.o
diff --git a/board/solidrun/mx6cuboxi/README b/board/solidrun/mx6cuboxi/README
deleted file mode 100644
index 5d0a45d9299..00000000000
--- a/board/solidrun/mx6cuboxi/README
+++ /dev/null
@@ -1,21 +0,0 @@
-How to use U-Boot on Solid-run mx6 Hummingboard and Cubox-i
------------------------------------------------------------
-
-- Build U-Boot for Hummingboard/Cubox-i:
-
-$ make mrproper
-$ make mx6cuboxi_defconfig
-$ make
-
-This will generate the SPL image called SPL and the u-boot.img.
-
-- Flash the SPL image into the SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the u-boot.img image into the SD card:
-
-sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Insert the SD card in the board, power it up and U-Boot messages should
-come up.
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
deleted file mode 100644
index cf63427e52f..00000000000
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ /dev/null
@@ -1,857 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * Based on SPL code from Solidrun tree, which is:
- * Author: Tungyi Lin <tungyilin1127@gmail.com>
- *
- * Derived from EDM_CF_IMX6 code by TechNexion,Inc
- * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
-#define USB_H1_VBUS IMX_GPIO_NR(1, 0)
-
-enum board_type {
- CUBOXI = 0x00,
- HUMMINGBOARD = 0x01,
- HUMMINGBOARD2 = 0x02,
- UNKNOWN = 0x03,
-};
-
-#define MEM_STRIDE 0x4000000
-static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
-{
- volatile u32 *addr;
- u32 save[64];
- u32 cnt;
- u32 size;
- int i = 0;
-
- /* First save the data */
- for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
- addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
- sync ();
- save[i++] = *addr;
- sync ();
- }
-
- /* First write a signature */
- * (volatile u32 *)base = 0x12345678;
- for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
- * (volatile u32 *)((u32)base + size) = size;
- sync ();
- if (* (volatile u32 *)((u32)base) == size) { /* We reached the overlapping address */
- break;
- }
- }
-
- /* Restore the data */
- for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
- addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
- sync ();
- *addr = save[i--];
- sync ();
- }
-
- return (size);
-}
-
-int dram_init(void)
-{
- u32 max_size = imx_ddr_size();
-
- gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
- (u32)max_size);
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const board_detect[] = {
- /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
- IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const som_rev_detect[] = {
- /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
- IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00 | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-static struct fsl_esdhc_cfg usdhc_cfg = {
- .esdhc_base = USDHC2_BASE_ADDR,
- .max_bus_width = 4,
-};
-
-static struct fsl_esdhc_cfg emmc_cfg = {
- .esdhc_base = USDHC3_BASE_ADDR,
- .max_bus_width = 8,
-};
-
-int board_mmc_get_env_dev(int devno)
-{
- return devno - 1;
-}
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
- break;
- }
-
- return ret;
-}
-
-static int mmc_init_main(bd_t *bis)
-{
- int ret;
-
- /*
- * Following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 Carrier board MicroSD
- * mmc1 SOM eMMC
- */
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg);
- if (ret)
- return ret;
-
- SETUP_IOMUX_PADS(usdhc3_pads);
- emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &emmc_cfg);
-}
-
-static int mmc_init_spl(bd_t *bis)
-{
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
-
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD2
- * 0x2 SD3
- */
- switch (reg & 0x3) {
- case 0x1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
- return fsl_esdhc_initialize(bis, &usdhc_cfg);
- case 0x2:
- SETUP_IOMUX_PADS(usdhc3_pads);
- emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
- return fsl_esdhc_initialize(bis, &emmc_cfg);
- }
-
- return -ENODEV;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
- return mmc_init_spl(bis);
-
- return mmc_init_main(bis);
-}
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 reset */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- /* AR8035 interrupt */
- IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* GPIO16 -> AR8035 25MHz */
- IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
- IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-};
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
- gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(ETH_PHY_RESET, 1);
- udelay(100);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
-/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
-#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
-
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct mii_dev *bus;
- struct phy_device *phydev;
-
- int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
- if (ret)
- return ret;
-
- /* set gpr1[ENET_CLK_SEL] */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(IMX_FEC_BASE, -1);
- if (!bus)
- return -EINVAL;
-
- phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
-
- debug("using phy at address %d\n", phydev->addr);
- ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
- if (ret)
- goto free_phydev;
-
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
-#ifdef CONFIG_VIDEO_IPUV3
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
- imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {
- {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_hdmi,
- .enable = do_enable_hdmi,
- .mode = {
- .name = "HDMI",
- /* 1024x768 at 60Hz (VESA)*/
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 15384,
- .left_margin = 160,
- .right_margin = 24,
- .upper_margin = 29,
- .lower_margin = 3,
- .hsync_len = 136,
- .vsync_len = 6,
- .sync = FB_SYNC_EXT,
- .vmode = FB_VMODE_NONINTERLACED
- }
- }
-};
-
-size_t display_count = ARRAY_SIZE(displays);
-
-static int setup_display(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- int timeout = 100000;
-
- enable_ipu_clock();
- imx_setup_hdmi();
-
- /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
- setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
-
- reg = readl(&ccm->analog_pll_video);
- reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
- reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
- writel(reg, &ccm->analog_pll_video);
-
- writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
- writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
-
- reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
- writel(reg, &ccm->analog_pll_video);
-
- while (timeout--)
- if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
- break;
- if (timeout < 0) {
- printf("Warning: video pll lock timeout!\n");
- return -ETIMEDOUT;
- }
-
- reg = readl(&ccm->analog_pll_video);
- reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
- reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
- writel(reg, &ccm->analog_pll_video);
-
- /* gate ipu1_di0_clk */
- clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-
- /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
- reg = readl(&ccm->chsccdr);
- reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
- MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
- MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
- reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
- (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
- (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &ccm->chsccdr);
-
- /* enable ipu1_di0_clk */
- setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-
- return 0;
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-#ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
-{
- SETUP_IOMUX_PADS(usb_pads);
-}
-
-int board_ehci_hcd_init(int port)
-{
- if (port == 1)
- gpio_direction_output(USB_H1_VBUS, 1);
-
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
-#ifdef CONFIG_CMD_SATA
- setup_sata();
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- int ret = 0;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_VIDEO_IPUV3
- ret = setup_display();
-#endif
-
- return ret;
-}
-
-static enum board_type board_type(void)
-{
- int val1, val2, val3;
-
- SETUP_IOMUX_PADS(board_detect);
-
- /*
- * Machine selection -
- * Machine val1, val2, val3
- * ----------------------------
- * HB2 x x 0
- * HB rev 3.x x 0 x
- * CBi 0 1 x
- * HB 1 1 x
- */
-
- gpio_direction_input(IMX_GPIO_NR(2, 8));
- val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
-
- if (val3 == 0)
- return HUMMINGBOARD2;
-
- gpio_direction_input(IMX_GPIO_NR(3, 4));
- val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
-
- if (val2 == 0)
- return HUMMINGBOARD;
-
- gpio_direction_input(IMX_GPIO_NR(4, 9));
- val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
-
- if (val1 == 0) {
- return CUBOXI;
- } else {
- return HUMMINGBOARD;
- }
-}
-
-static bool is_rev_15_som(void)
-{
- int val1, val2;
- SETUP_IOMUX_PADS(som_rev_detect);
-
- val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
- val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
-
- if (val1 == 1 && val2 == 0)
- return true;
-
- return false;
-}
-
-static bool has_emmc(void)
-{
- struct mmc *mmc;
- mmc = find_mmc_device(1);
- if (!mmc)
- return 0;
- return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
-}
-
-int checkboard(void)
-{
- switch (board_type()) {
- case CUBOXI:
- puts("Board: MX6 Cubox-i");
- break;
- case HUMMINGBOARD:
- puts("Board: MX6 HummingBoard");
- break;
- case HUMMINGBOARD2:
- puts("Board: MX6 HummingBoard2");
- break;
- case UNKNOWN:
- default:
- puts("Board: Unknown\n");
- goto out;
- }
-
- if (is_rev_15_som())
- puts(" (som rev 1.5)\n");
- else
- puts("\n");
-
-out:
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- switch (board_type()) {
- case CUBOXI:
- env_set("board_name", "CUBOXI");
- break;
- case HUMMINGBOARD:
- env_set("board_name", "HUMMINGBOARD");
- break;
- case HUMMINGBOARD2:
- env_set("board_name", "HUMMINGBOARD2");
- break;
- case UNKNOWN:
- default:
- env_set("board_name", "CUBOXI");
- }
-
- if (is_mx6dq())
- env_set("board_rev", "MX6Q");
- else
- env_set("board_rev", "MX6DL");
-
- if (is_rev_15_som())
- env_set("som_rev", "V15");
-
- if (has_emmc())
- env_set("has_emmc", "yes");
-
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x000c0030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
- .dram_sdclk_0 = 0x00000028,
- .dram_sdclk_1 = 0x00000028,
- .dram_cas = 0x00000028,
- .dram_ras = 0x00000028,
- .dram_reset = 0x000c0028,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000028,
- .dram_sdqs1 = 0x00000028,
- .dram_sdqs2 = 0x00000028,
- .dram_sdqs3 = 0x00000028,
- .dram_sdqs4 = 0x00000028,
- .dram_sdqs5 = 0x00000028,
- .dram_sdqs6 = 0x00000028,
- .dram_sdqs7 = 0x00000028,
- .dram_dqm0 = 0x00000028,
- .dram_dqm1 = 0x00000028,
- .dram_dqm2 = 0x00000028,
- .dram_dqm3 = 0x00000028,
- .dram_dqm4 = 0x00000028,
- .dram_dqm5 = 0x00000028,
- .dram_dqm6 = 0x00000028,
- .dram_dqm7 = 0x00000028,
-};
-
-static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000028,
- .grp_ctlds = 0x00000028,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000028,
- .grp_b1ds = 0x00000028,
- .grp_b2ds = 0x00000028,
- .grp_b3ds = 0x00000028,
- .grp_b4ds = 0x00000028,
- .grp_b5ds = 0x00000028,
- .grp_b6ds = 0x00000028,
- .grp_b7ds = 0x00000028,
-};
-
-/* microSOM with Dual processor and 1GB memory */
-static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpwldectrl1 = 0x00000000,
- .p1_mpwldectrl0 = 0x00000000,
- .p1_mpwldectrl1 = 0x00000000,
- .p0_mpdgctrl0 = 0x0314031c,
- .p0_mpdgctrl1 = 0x023e0304,
- .p1_mpdgctrl0 = 0x03240330,
- .p1_mpdgctrl1 = 0x03180260,
- .p0_mprddlctl = 0x3630323c,
- .p1_mprddlctl = 0x3436283a,
- .p0_mpwrdlctl = 0x36344038,
- .p1_mpwrdlctl = 0x422a423c,
-};
-
-/* microSOM with Quad processor and 2GB memory */
-static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpwldectrl1 = 0x00000000,
- .p1_mpwldectrl0 = 0x00000000,
- .p1_mpwldectrl1 = 0x00000000,
- .p0_mpdgctrl0 = 0x0314031c,
- .p0_mpdgctrl1 = 0x023e0304,
- .p1_mpdgctrl0 = 0x03240330,
- .p1_mpdgctrl1 = 0x03180260,
- .p0_mprddlctl = 0x3630323c,
- .p1_mprddlctl = 0x3436283a,
- .p0_mpwrdlctl = 0x36344038,
- .p1_mpwrdlctl = 0x422a423c,
-};
-
-/* microSOM with Solo processor and 512MB memory */
-static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
- .p0_mpwldectrl0 = 0x0045004D,
- .p0_mpwldectrl1 = 0x003A0047,
- .p0_mpdgctrl0 = 0x023C0224,
- .p0_mpdgctrl1 = 0x02000220,
- .p0_mprddlctl = 0x44444846,
- .p0_mpwrdlctl = 0x32343032,
-};
-
-/* microSOM with Dual lite processor and 1GB memory */
-static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
- .p0_mpwldectrl0 = 0x0045004D,
- .p0_mpwldectrl1 = 0x003A0047,
- .p1_mpwldectrl0 = 0x001F001F,
- .p1_mpwldectrl1 = 0x00210035,
- .p0_mpdgctrl0 = 0x023C0224,
- .p0_mpdgctrl1 = 0x02000220,
- .p1_mpdgctrl0 = 0x02200220,
- .p1_mpdgctrl1 = 0x02040208,
- .p0_mprddlctl = 0x44444846,
- .p1_mprddlctl = 0x4042463C,
- .p0_mpwrdlctl = 0x32343032,
- .p1_mpwrdlctl = 0x36363430,
-};
-
-static struct mx6_ddr3_cfg mem_ddr_2g = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-static struct mx6_ddr3_cfg mem_ddr_4g = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 16,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(int width)
-{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus: 0=16, 1=32, 2=64 */
- .dsize = width / 32,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- .ncs = 1, /* single chip select */
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- if (is_mx6dq())
- mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
- else
- mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
-
- if (is_cpu_type(MXC_CPU_MX6D))
- mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
- else if (is_cpu_type(MXC_CPU_MX6Q))
- mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
- else if (is_cpu_type(MXC_CPU_MX6DL))
- mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
- else if (is_cpu_type(MXC_CPU_MX6SOLO))
- mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- if (is_cpu_type(MXC_CPU_MX6SOLO))
- spl_dram_init(32);
- else
- spl_dram_init(64);
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
deleted file mode 100644
index 6e73a9752c3..00000000000
--- a/configs/mx6cuboxi_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_MX6CUBOXI=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
deleted file mode 100644
index a62e14f7c61..00000000000
--- a/include/configs/mx6cuboxi.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the SolidRun mx6 based boards
- */
-#ifndef __MX6CUBOXI_CONFIG_H
-#define __MX6CUBOXI_CONFIG_H
-
-#include "mx6_common.h"
-
-#include "imx6_spl.h"
-
-#define CONFIG_IMX_THERMAL
-
-#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-#define CONFIG_MXC_UART
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-
-/* SATA Configuration */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* Ethernet Configuration */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_PHY_ATHEROS
-
-/* Framebuffer */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-/* USB */
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_PREBOOT \
- "if hdmidet; then " \
- "usb start; " \
- "setenv stdin serial,usbkbd; "\
- "setenv stdout serial,vga; " \
- "setenv stderr serial,vga; " \
- "else " \
- "setenv stdin serial; " \
- "setenv stdout serial; " \
- "setenv stderr serial; " \
- "fi;"
-
-/* Command definition */
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONSOLE_DEV "ttymxc0"
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "som_rev=undefined\0" \
- "has_emmc=undefined\0" \
- "fdtfile=undefined\0" \
- "fdt_addr_r=0x18000000\0" \
- "fdt_addr=0x18000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_addr_r=0x13000000\0" \
- "ramdiskaddr=0x13000000\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_high=0xffffffff\0" \
- "ip_dyn=yes\0" \
- "console=" CONSOLE_DEV ",115200\0" \
- "bootm_size=0x10000000\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "finduuid=part uuid mmc 0:1 uuid\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "findfdt="\
- "if test ${board_rev} = MX6Q; then " \
- "setenv fdtprefix imx6q; fi; " \
- "if test ${board_rev} = MX6DL; then " \
- "setenv fdtprefix imx6dl; fi; " \
- "if test ${som_rev} = V15; then " \
- "setenv fdtsuffix -som-v15; fi; " \
- "if test ${has_emmc} = yes; then " \
- "setenv emmcsuffix -emmc; fi; " \
- "if test ${board_name} = HUMMINGBOARD2 ; then " \
- "setenv fdtfile ${fdtprefix}-hummingboard2${emmcsuffix}${fdtsuffix}.dtb; fi; " \
- "if test ${board_name} = HUMMINGBOARD ; then " \
- "setenv fdtfile ${fdtprefix}-hummingboard${emmcsuffix}${fdtsuffix}.dtb; fi; " \
- "if test ${board_name} = CUBOXI ; then " \
- "setenv fdtfile ${fdtprefix}-cubox-i${emmcsuffix}${fdtsuffix}.dtb; fi; " \
- "if test ${fdtfile} = undefined; then " \
- "echo WARNING: Could not determine dtb to use; fi; \0" \
- BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(SATA, sata, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS
-#endif /* CONFIG_SPL_BUILD */
-
-/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE)
-
-#endif /* __MX6CUBOXI_CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 65/93] arm: Remove mx6cuboxi board
2018-11-19 15:53 ` [U-Boot] [PATCH 65/93] arm: Remove mx6cuboxi board Simon Glass
@ 2018-11-20 7:52 ` Mark Kettenis
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Mark Kettenis @ 2018-11-20 7:52 UTC (permalink / raw)
To: u-boot
> Date: Mon, 19 Nov 2018 08:53:45 -0700
> From: Simon Glass <sjg@chromium.org>
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
Hmm, isn't there something going wrong if a maintained board is
getting removed? Especially ones that are still on the market? Just
happened to pick this one since there we use these a lot in the
OpenBSD project for building stuff.
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-imx/mx6/Kconfig | 1 -
> board/solidrun/mx6cuboxi/Kconfig | 12 -
> board/solidrun/mx6cuboxi/MAINTAINERS | 6 -
> board/solidrun/mx6cuboxi/Makefile | 7 -
> board/solidrun/mx6cuboxi/README | 21 -
> board/solidrun/mx6cuboxi/mx6cuboxi.c | 857 ---------------------------
> configs/mx6cuboxi_defconfig | 43 --
> include/configs/mx6cuboxi.h | 149 -----
> 8 files changed, 1096 deletions(-)
> delete mode 100644 board/solidrun/mx6cuboxi/Kconfig
> delete mode 100644 board/solidrun/mx6cuboxi/MAINTAINERS
> delete mode 100644 board/solidrun/mx6cuboxi/Makefile
> delete mode 100644 board/solidrun/mx6cuboxi/README
> delete mode 100644 board/solidrun/mx6cuboxi/mx6cuboxi.c
> delete mode 100644 configs/mx6cuboxi_defconfig
> delete mode 100644 include/configs/mx6cuboxi.h
>
> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
> index d05a3fa7ccf..19e259af057 100644
> --- a/arch/arm/mach-imx/mx6/Kconfig
> +++ b/arch/arm/mach-imx/mx6/Kconfig
> @@ -542,7 +542,6 @@ source "board/freescale/mx6ullevk/Kconfig"
> source "board/kosagi/novena/Kconfig"
> source "board/liebherr/display5/Kconfig"
> source "board/seco/Kconfig"
> -source "board/solidrun/mx6cuboxi/Kconfig"
> source "board/technexion/pico-imx6ul/Kconfig"
> source "board/tqc/tqma6/Kconfig"
> source "board/toradex/colibri-imx6ull/Kconfig"
> diff --git a/board/solidrun/mx6cuboxi/Kconfig b/board/solidrun/mx6cuboxi/Kconfig
> deleted file mode 100644
> index 741c1754f81..00000000000
> --- a/board/solidrun/mx6cuboxi/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_MX6CUBOXI
> -
> -config SYS_BOARD
> - default "mx6cuboxi"
> -
> -config SYS_VENDOR
> - default "solidrun"
> -
> -config SYS_CONFIG_NAME
> - default "mx6cuboxi"
> -
> -endif
> diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS
> deleted file mode 100644
> index 81f82bc9b5e..00000000000
> --- a/board/solidrun/mx6cuboxi/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -MX6CUBOXI BOARD
> -M: Fabio Estevam <fabio.estevam@nxp.com>
> -S: Maintained
> -F: board/solidrun/mx6cuboxi/
> -F: include/configs/mx6cuboxi.h
> -F: configs/mx6cuboxi_defconfig
> diff --git a/board/solidrun/mx6cuboxi/Makefile b/board/solidrun/mx6cuboxi/Makefile
> deleted file mode 100644
> index 6e5becbd27b..00000000000
> --- a/board/solidrun/mx6cuboxi/Makefile
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> -#
> -# (C) Copyright 2011 Freescale Semiconductor, Inc.
> -
> -obj-y := mx6cuboxi.o
> diff --git a/board/solidrun/mx6cuboxi/README b/board/solidrun/mx6cuboxi/README
> deleted file mode 100644
> index 5d0a45d9299..00000000000
> --- a/board/solidrun/mx6cuboxi/README
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -How to use U-Boot on Solid-run mx6 Hummingboard and Cubox-i
> ------------------------------------------------------------
> -
> -- Build U-Boot for Hummingboard/Cubox-i:
> -
> -$ make mrproper
> -$ make mx6cuboxi_defconfig
> -$ make
> -
> -This will generate the SPL image called SPL and the u-boot.img.
> -
> -- Flash the SPL image into the SD card:
> -
> -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
> -
> -- Flash the u-boot.img image into the SD card:
> -
> -sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
> -
> -- Insert the SD card in the board, power it up and U-Boot messages should
> -come up.
> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> deleted file mode 100644
> index cf63427e52f..00000000000
> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> +++ /dev/null
> @@ -1,857 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2015 Freescale Semiconductor, Inc.
> - *
> - * Author: Fabio Estevam <fabio.estevam@freescale.com>
> - *
> - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
> - *
> - * Based on SPL code from Solidrun tree, which is:
> - * Author: Tungyi Lin <tungyilin1127@gmail.com>
> - *
> - * Derived from EDM_CF_IMX6 code by TechNexion,Inc
> - * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
> - */
> -
> -#include <asm/arch/clock.h>
> -#include <asm/arch/imx-regs.h>
> -#include <asm/arch/iomux.h>
> -#include <asm/arch/mx6-pins.h>
> -#include <asm/arch/mxc_hdmi.h>
> -#include <linux/errno.h>
> -#include <asm/gpio.h>
> -#include <asm/mach-imx/iomux-v3.h>
> -#include <asm/mach-imx/sata.h>
> -#include <asm/mach-imx/video.h>
> -#include <mmc.h>
> -#include <fsl_esdhc.h>
> -#include <malloc.h>
> -#include <miiphy.h>
> -#include <netdev.h>
> -#include <asm/arch/crm_regs.h>
> -#include <asm/io.h>
> -#include <asm/arch/sys_proto.h>
> -#include <spl.h>
> -#include <usb.h>
> -#include <usb/ehci-ci.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
> - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
> - PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> -
> -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> -
> -#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> -
> -#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> -
> -#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
> -#define USB_H1_VBUS IMX_GPIO_NR(1, 0)
> -
> -enum board_type {
> - CUBOXI = 0x00,
> - HUMMINGBOARD = 0x01,
> - HUMMINGBOARD2 = 0x02,
> - UNKNOWN = 0x03,
> -};
> -
> -#define MEM_STRIDE 0x4000000
> -static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
> -{
> - volatile u32 *addr;
> - u32 save[64];
> - u32 cnt;
> - u32 size;
> - int i = 0;
> -
> - /* First save the data */
> - for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
> - addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
> - sync ();
> - save[i++] = *addr;
> - sync ();
> - }
> -
> - /* First write a signature */
> - * (volatile u32 *)base = 0x12345678;
> - for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
> - * (volatile u32 *)((u32)base + size) = size;
> - sync ();
> - if (* (volatile u32 *)((u32)base) == size) { /* We reached the overlapping address */
> - break;
> - }
> - }
> -
> - /* Restore the data */
> - for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
> - addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
> - sync ();
> - *addr = save[i--];
> - sync ();
> - }
> -
> - return (size);
> -}
> -
> -int dram_init(void)
> -{
> - u32 max_size = imx_ddr_size();
> -
> - gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
> - (u32)max_size);
> -
> - return 0;
> -}
> -
> -static iomux_v3_cfg_t const uart1_pads[] = {
> - IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const usdhc2_pads[] = {
> - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const usdhc3_pads[] = {
> - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const board_detect[] = {
> - /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
> - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(UART_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const som_rev_detect[] = {
> - /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
> - IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00 | MUX_PAD_CTRL(UART_PAD_CTRL)),
> - IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
> -};
> -
> -static iomux_v3_cfg_t const usb_pads[] = {
> - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> -};
> -
> -static void setup_iomux_uart(void)
> -{
> - SETUP_IOMUX_PADS(uart1_pads);
> -}
> -
> -static struct fsl_esdhc_cfg usdhc_cfg = {
> - .esdhc_base = USDHC2_BASE_ADDR,
> - .max_bus_width = 4,
> -};
> -
> -static struct fsl_esdhc_cfg emmc_cfg = {
> - .esdhc_base = USDHC3_BASE_ADDR,
> - .max_bus_width = 8,
> -};
> -
> -int board_mmc_get_env_dev(int devno)
> -{
> - return devno - 1;
> -}
> -
> -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> -
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - struct fsl_esdhc_cfg *cfg = mmc->priv;
> - int ret = 0;
> -
> - switch (cfg->esdhc_base) {
> - case USDHC2_BASE_ADDR:
> - ret = !gpio_get_value(USDHC2_CD_GPIO);
> - break;
> - case USDHC3_BASE_ADDR:
> - ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
> - break;
> - }
> -
> - return ret;
> -}
> -
> -static int mmc_init_main(bd_t *bis)
> -{
> - int ret;
> -
> - /*
> - * Following map is done:
> - * (U-Boot device node) (Physical Port)
> - * mmc0 Carrier board MicroSD
> - * mmc1 SOM eMMC
> - */
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - ret = fsl_esdhc_initialize(bis, &usdhc_cfg);
> - if (ret)
> - return ret;
> -
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - return fsl_esdhc_initialize(bis, &emmc_cfg);
> -}
> -
> -static int mmc_init_spl(bd_t *bis)
> -{
> - struct src *psrc = (struct src *)SRC_BASE_ADDR;
> - unsigned reg = readl(&psrc->sbmr1) >> 11;
> -
> - /*
> - * Upon reading BOOT_CFG register the following map is done:
> - * Bit 11 and 12 of BOOT_CFG register can determine the current
> - * mmc port
> - * 0x1 SD2
> - * 0x2 SD3
> - */
> - switch (reg & 0x3) {
> - case 0x1:
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
> - return fsl_esdhc_initialize(bis, &usdhc_cfg);
> - case 0x2:
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
> - return fsl_esdhc_initialize(bis, &emmc_cfg);
> - }
> -
> - return -ENODEV;
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> - if (IS_ENABLED(CONFIG_SPL_BUILD))
> - return mmc_init_spl(bis);
> -
> - return mmc_init_main(bis);
> -}
> -
> -static iomux_v3_cfg_t const enet_pads[] = {
> - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* AR8035 reset */
> - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - /* AR8035 interrupt */
> - IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - /* GPIO16 -> AR8035 25MHz */
> - IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
> - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
> - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> - IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
> -};
> -
> -static void setup_iomux_enet(void)
> -{
> - SETUP_IOMUX_PADS(enet_pads);
> -
> - gpio_direction_output(ETH_PHY_RESET, 0);
> - mdelay(10);
> - gpio_set_value(ETH_PHY_RESET, 1);
> - udelay(100);
> -}
> -
> -int board_phy_config(struct phy_device *phydev)
> -{
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> -
> - return 0;
> -}
> -
> -/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
> -#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
> -
> -int board_eth_init(bd_t *bis)
> -{
> - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> - struct mii_dev *bus;
> - struct phy_device *phydev;
> -
> - int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
> - if (ret)
> - return ret;
> -
> - /* set gpr1[ENET_CLK_SEL] */
> - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> -
> - setup_iomux_enet();
> -
> - bus = fec_get_miibus(IMX_FEC_BASE, -1);
> - if (!bus)
> - return -EINVAL;
> -
> - phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
> - if (!phydev) {
> - ret = -EINVAL;
> - goto free_bus;
> - }
> -
> - debug("using phy at address %d\n", phydev->addr);
> - ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
> - if (ret)
> - goto free_phydev;
> -
> - return 0;
> -
> -free_phydev:
> - free(phydev);
> -free_bus:
> - free(bus);
> - return ret;
> -}
> -
> -#ifdef CONFIG_VIDEO_IPUV3
> -static void do_enable_hdmi(struct display_info_t const *dev)
> -{
> - imx_enable_hdmi_phy();
> -}
> -
> -struct display_info_t const displays[] = {
> - {
> - .bus = -1,
> - .addr = 0,
> - .pixfmt = IPU_PIX_FMT_RGB24,
> - .detect = detect_hdmi,
> - .enable = do_enable_hdmi,
> - .mode = {
> - .name = "HDMI",
> - /* 1024x768 at 60Hz (VESA)*/
> - .refresh = 60,
> - .xres = 1024,
> - .yres = 768,
> - .pixclock = 15384,
> - .left_margin = 160,
> - .right_margin = 24,
> - .upper_margin = 29,
> - .lower_margin = 3,
> - .hsync_len = 136,
> - .vsync_len = 6,
> - .sync = FB_SYNC_EXT,
> - .vmode = FB_VMODE_NONINTERLACED
> - }
> - }
> -};
> -
> -size_t display_count = ARRAY_SIZE(displays);
> -
> -static int setup_display(void)
> -{
> - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> - int reg;
> - int timeout = 100000;
> -
> - enable_ipu_clock();
> - imx_setup_hdmi();
> -
> - /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
> - setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
> -
> - reg = readl(&ccm->analog_pll_video);
> - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
> - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
> - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
> - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
> - writel(reg, &ccm->analog_pll_video);
> -
> - writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
> - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
> -
> - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
> - writel(reg, &ccm->analog_pll_video);
> -
> - while (timeout--)
> - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
> - break;
> - if (timeout < 0) {
> - printf("Warning: video pll lock timeout!\n");
> - return -ETIMEDOUT;
> - }
> -
> - reg = readl(&ccm->analog_pll_video);
> - reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
> - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
> - writel(reg, &ccm->analog_pll_video);
> -
> - /* gate ipu1_di0_clk */
> - clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
> -
> - /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
> - reg = readl(&ccm->chsccdr);
> - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
> - MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
> - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
> - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
> - (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
> - (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
> - writel(reg, &ccm->chsccdr);
> -
> - /* enable ipu1_di0_clk */
> - setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
> -
> - return 0;
> -}
> -#endif /* CONFIG_VIDEO_IPUV3 */
> -
> -#ifdef CONFIG_USB_EHCI_MX6
> -static void setup_usb(void)
> -{
> - SETUP_IOMUX_PADS(usb_pads);
> -}
> -
> -int board_ehci_hcd_init(int port)
> -{
> - if (port == 1)
> - gpio_direction_output(USB_H1_VBUS, 1);
> -
> - return 0;
> -}
> -#endif
> -
> -int board_early_init_f(void)
> -{
> - setup_iomux_uart();
> -
> -#ifdef CONFIG_CMD_SATA
> - setup_sata();
> -#endif
> -
> -#ifdef CONFIG_USB_EHCI_MX6
> - setup_usb();
> -#endif
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - int ret = 0;
> -
> - /* address of boot parameters */
> - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> -
> -#ifdef CONFIG_VIDEO_IPUV3
> - ret = setup_display();
> -#endif
> -
> - return ret;
> -}
> -
> -static enum board_type board_type(void)
> -{
> - int val1, val2, val3;
> -
> - SETUP_IOMUX_PADS(board_detect);
> -
> - /*
> - * Machine selection -
> - * Machine val1, val2, val3
> - * ----------------------------
> - * HB2 x x 0
> - * HB rev 3.x x 0 x
> - * CBi 0 1 x
> - * HB 1 1 x
> - */
> -
> - gpio_direction_input(IMX_GPIO_NR(2, 8));
> - val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
> -
> - if (val3 == 0)
> - return HUMMINGBOARD2;
> -
> - gpio_direction_input(IMX_GPIO_NR(3, 4));
> - val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
> -
> - if (val2 == 0)
> - return HUMMINGBOARD;
> -
> - gpio_direction_input(IMX_GPIO_NR(4, 9));
> - val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
> -
> - if (val1 == 0) {
> - return CUBOXI;
> - } else {
> - return HUMMINGBOARD;
> - }
> -}
> -
> -static bool is_rev_15_som(void)
> -{
> - int val1, val2;
> - SETUP_IOMUX_PADS(som_rev_detect);
> -
> - val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
> - val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
> -
> - if (val1 == 1 && val2 == 0)
> - return true;
> -
> - return false;
> -}
> -
> -static bool has_emmc(void)
> -{
> - struct mmc *mmc;
> - mmc = find_mmc_device(1);
> - if (!mmc)
> - return 0;
> - return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
> -}
> -
> -int checkboard(void)
> -{
> - switch (board_type()) {
> - case CUBOXI:
> - puts("Board: MX6 Cubox-i");
> - break;
> - case HUMMINGBOARD:
> - puts("Board: MX6 HummingBoard");
> - break;
> - case HUMMINGBOARD2:
> - puts("Board: MX6 HummingBoard2");
> - break;
> - case UNKNOWN:
> - default:
> - puts("Board: Unknown\n");
> - goto out;
> - }
> -
> - if (is_rev_15_som())
> - puts(" (som rev 1.5)\n");
> - else
> - puts("\n");
> -
> -out:
> - return 0;
> -}
> -
> -int board_late_init(void)
> -{
> -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> - switch (board_type()) {
> - case CUBOXI:
> - env_set("board_name", "CUBOXI");
> - break;
> - case HUMMINGBOARD:
> - env_set("board_name", "HUMMINGBOARD");
> - break;
> - case HUMMINGBOARD2:
> - env_set("board_name", "HUMMINGBOARD2");
> - break;
> - case UNKNOWN:
> - default:
> - env_set("board_name", "CUBOXI");
> - }
> -
> - if (is_mx6dq())
> - env_set("board_rev", "MX6Q");
> - else
> - env_set("board_rev", "MX6DL");
> -
> - if (is_rev_15_som())
> - env_set("som_rev", "V15");
> -
> - if (has_emmc())
> - env_set("has_emmc", "yes");
> -
> -#endif
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_SPL_BUILD
> -#include <asm/arch/mx6-ddr.h>
> -static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
> - .dram_sdclk_0 = 0x00020030,
> - .dram_sdclk_1 = 0x00020030,
> - .dram_cas = 0x00020030,
> - .dram_ras = 0x00020030,
> - .dram_reset = 0x000c0030,
> - .dram_sdcke0 = 0x00003000,
> - .dram_sdcke1 = 0x00003000,
> - .dram_sdba2 = 0x00000000,
> - .dram_sdodt0 = 0x00003030,
> - .dram_sdodt1 = 0x00003030,
> - .dram_sdqs0 = 0x00000030,
> - .dram_sdqs1 = 0x00000030,
> - .dram_sdqs2 = 0x00000030,
> - .dram_sdqs3 = 0x00000030,
> - .dram_sdqs4 = 0x00000030,
> - .dram_sdqs5 = 0x00000030,
> - .dram_sdqs6 = 0x00000030,
> - .dram_sdqs7 = 0x00000030,
> - .dram_dqm0 = 0x00020030,
> - .dram_dqm1 = 0x00020030,
> - .dram_dqm2 = 0x00020030,
> - .dram_dqm3 = 0x00020030,
> - .dram_dqm4 = 0x00020030,
> - .dram_dqm5 = 0x00020030,
> - .dram_dqm6 = 0x00020030,
> - .dram_dqm7 = 0x00020030,
> -};
> -
> -static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
> - .dram_sdclk_0 = 0x00000028,
> - .dram_sdclk_1 = 0x00000028,
> - .dram_cas = 0x00000028,
> - .dram_ras = 0x00000028,
> - .dram_reset = 0x000c0028,
> - .dram_sdcke0 = 0x00003000,
> - .dram_sdcke1 = 0x00003000,
> - .dram_sdba2 = 0x00000000,
> - .dram_sdodt0 = 0x00003030,
> - .dram_sdodt1 = 0x00003030,
> - .dram_sdqs0 = 0x00000028,
> - .dram_sdqs1 = 0x00000028,
> - .dram_sdqs2 = 0x00000028,
> - .dram_sdqs3 = 0x00000028,
> - .dram_sdqs4 = 0x00000028,
> - .dram_sdqs5 = 0x00000028,
> - .dram_sdqs6 = 0x00000028,
> - .dram_sdqs7 = 0x00000028,
> - .dram_dqm0 = 0x00000028,
> - .dram_dqm1 = 0x00000028,
> - .dram_dqm2 = 0x00000028,
> - .dram_dqm3 = 0x00000028,
> - .dram_dqm4 = 0x00000028,
> - .dram_dqm5 = 0x00000028,
> - .dram_dqm6 = 0x00000028,
> - .dram_dqm7 = 0x00000028,
> -};
> -
> -static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
> - .grp_ddr_type = 0x000C0000,
> - .grp_ddrmode_ctl = 0x00020000,
> - .grp_ddrpke = 0x00000000,
> - .grp_addds = 0x00000030,
> - .grp_ctlds = 0x00000030,
> - .grp_ddrmode = 0x00020000,
> - .grp_b0ds = 0x00000030,
> - .grp_b1ds = 0x00000030,
> - .grp_b2ds = 0x00000030,
> - .grp_b3ds = 0x00000030,
> - .grp_b4ds = 0x00000030,
> - .grp_b5ds = 0x00000030,
> - .grp_b6ds = 0x00000030,
> - .grp_b7ds = 0x00000030,
> -};
> -
> -static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
> - .grp_ddr_type = 0x000c0000,
> - .grp_ddrmode_ctl = 0x00020000,
> - .grp_ddrpke = 0x00000000,
> - .grp_addds = 0x00000028,
> - .grp_ctlds = 0x00000028,
> - .grp_ddrmode = 0x00020000,
> - .grp_b0ds = 0x00000028,
> - .grp_b1ds = 0x00000028,
> - .grp_b2ds = 0x00000028,
> - .grp_b3ds = 0x00000028,
> - .grp_b4ds = 0x00000028,
> - .grp_b5ds = 0x00000028,
> - .grp_b6ds = 0x00000028,
> - .grp_b7ds = 0x00000028,
> -};
> -
> -/* microSOM with Dual processor and 1GB memory */
> -static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
> - .p0_mpwldectrl0 = 0x00000000,
> - .p0_mpwldectrl1 = 0x00000000,
> - .p1_mpwldectrl0 = 0x00000000,
> - .p1_mpwldectrl1 = 0x00000000,
> - .p0_mpdgctrl0 = 0x0314031c,
> - .p0_mpdgctrl1 = 0x023e0304,
> - .p1_mpdgctrl0 = 0x03240330,
> - .p1_mpdgctrl1 = 0x03180260,
> - .p0_mprddlctl = 0x3630323c,
> - .p1_mprddlctl = 0x3436283a,
> - .p0_mpwrdlctl = 0x36344038,
> - .p1_mpwrdlctl = 0x422a423c,
> -};
> -
> -/* microSOM with Quad processor and 2GB memory */
> -static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
> - .p0_mpwldectrl0 = 0x00000000,
> - .p0_mpwldectrl1 = 0x00000000,
> - .p1_mpwldectrl0 = 0x00000000,
> - .p1_mpwldectrl1 = 0x00000000,
> - .p0_mpdgctrl0 = 0x0314031c,
> - .p0_mpdgctrl1 = 0x023e0304,
> - .p1_mpdgctrl0 = 0x03240330,
> - .p1_mpdgctrl1 = 0x03180260,
> - .p0_mprddlctl = 0x3630323c,
> - .p1_mprddlctl = 0x3436283a,
> - .p0_mpwrdlctl = 0x36344038,
> - .p1_mpwrdlctl = 0x422a423c,
> -};
> -
> -/* microSOM with Solo processor and 512MB memory */
> -static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
> - .p0_mpwldectrl0 = 0x0045004D,
> - .p0_mpwldectrl1 = 0x003A0047,
> - .p0_mpdgctrl0 = 0x023C0224,
> - .p0_mpdgctrl1 = 0x02000220,
> - .p0_mprddlctl = 0x44444846,
> - .p0_mpwrdlctl = 0x32343032,
> -};
> -
> -/* microSOM with Dual lite processor and 1GB memory */
> -static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
> - .p0_mpwldectrl0 = 0x0045004D,
> - .p0_mpwldectrl1 = 0x003A0047,
> - .p1_mpwldectrl0 = 0x001F001F,
> - .p1_mpwldectrl1 = 0x00210035,
> - .p0_mpdgctrl0 = 0x023C0224,
> - .p0_mpdgctrl1 = 0x02000220,
> - .p1_mpdgctrl0 = 0x02200220,
> - .p1_mpdgctrl1 = 0x02040208,
> - .p0_mprddlctl = 0x44444846,
> - .p1_mprddlctl = 0x4042463C,
> - .p0_mpwrdlctl = 0x32343032,
> - .p1_mpwrdlctl = 0x36363430,
> -};
> -
> -static struct mx6_ddr3_cfg mem_ddr_2g = {
> - .mem_speed = 1600,
> - .density = 2,
> - .width = 16,
> - .banks = 8,
> - .rowaddr = 14,
> - .coladdr = 10,
> - .pagesz = 2,
> - .trcd = 1375,
> - .trcmin = 4875,
> - .trasmin = 3500,
> -};
> -
> -static struct mx6_ddr3_cfg mem_ddr_4g = {
> - .mem_speed = 1600,
> - .density = 4,
> - .width = 16,
> - .banks = 8,
> - .rowaddr = 16,
> - .coladdr = 10,
> - .pagesz = 2,
> - .trcd = 1375,
> - .trcmin = 4875,
> - .trasmin = 3500,
> -};
> -
> -static void ccgr_init(void)
> -{
> - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -
> - writel(0x00C03F3F, &ccm->CCGR0);
> - writel(0x0030FC03, &ccm->CCGR1);
> - writel(0x0FFFC000, &ccm->CCGR2);
> - writel(0x3FF00000, &ccm->CCGR3);
> - writel(0x00FFF300, &ccm->CCGR4);
> - writel(0x0F0000C3, &ccm->CCGR5);
> - writel(0x000003FF, &ccm->CCGR6);
> -}
> -
> -static void spl_dram_init(int width)
> -{
> - struct mx6_ddr_sysinfo sysinfo = {
> - /* width of data bus: 0=16, 1=32, 2=64 */
> - .dsize = width / 32,
> - /* config for full 4GB range so that get_mem_size() works */
> - .cs_density = 32, /* 32Gb per CS */
> - .ncs = 1, /* single chip select */
> - .cs1_mirror = 0,
> - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
> - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
> - .walat = 1, /* Write additional latency */
> - .ralat = 5, /* Read additional latency */
> - .mif3_mode = 3, /* Command prediction working mode */
> - .bi_on = 1, /* Bank interleaving enabled */
> - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
> - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
> - .ddr_type = DDR_TYPE_DDR3,
> - .refsel = 1, /* Refresh cycles at 32KHz */
> - .refr = 7, /* 8 refresh commands per refresh cycle */
> - };
> -
> - if (is_mx6dq())
> - mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
> - else
> - mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
> -
> - if (is_cpu_type(MXC_CPU_MX6D))
> - mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
> - else if (is_cpu_type(MXC_CPU_MX6Q))
> - mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
> - else if (is_cpu_type(MXC_CPU_MX6DL))
> - mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
> - else if (is_cpu_type(MXC_CPU_MX6SOLO))
> - mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
> -}
> -
> -void board_init_f(ulong dummy)
> -{
> - /* setup AIPS and disable watchdog */
> - arch_cpu_init();
> -
> - ccgr_init();
> - gpr_init();
> -
> - /* iomux and setup of i2c */
> - board_early_init_f();
> -
> - /* setup GP timer */
> - timer_init();
> -
> - /* UART clocks enabled and gd valid - init serial console */
> - preloader_console_init();
> -
> - /* DDR initialization */
> - if (is_cpu_type(MXC_CPU_MX6SOLO))
> - spl_dram_init(32);
> - else
> - spl_dram_init(64);
> -
> - /* Clear the BSS. */
> - memset(__bss_start, 0, __bss_end - __bss_start);
> -
> - /* load/boot image from boot device */
> - board_init_r(NULL, 0);
> -}
> -#endif
> diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
> deleted file mode 100644
> index 6e73a9752c3..00000000000
> --- a/configs/mx6cuboxi_defconfig
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_MX6=y
> -CONFIG_SYS_TEXT_BASE=0x17800000
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_TARGET_MX6CUBOXI=y
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL=y
> -CONFIG_SPL_LIBDISK_SUPPORT=y
> -# CONFIG_CMD_BMODE is not set
> -CONFIG_CMD_HDMIDETECT=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=1
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
> -CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
> -CONFIG_BOARD_EARLY_INIT_F=y
> -CONFIG_SPL_EXT_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_WATCHDOG_SUPPORT=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_SATA=y
> -CONFIG_CMD_USB=y
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT4_WRITE=y
> -# CONFIG_SPL_PARTITION_UUIDS is not set
> -CONFIG_ENV_IS_IN_MMC=y
> -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> -CONFIG_DM=y
> -CONFIG_DWC_AHSATA=y
> -CONFIG_FSL_ESDHC=y
> -CONFIG_PHYLIB=y
> -CONFIG_MII=y
> -CONFIG_DM_THERMAL=y
> -CONFIG_USB=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_USB_KEYBOARD=y
> -CONFIG_VIDEO=y
> -# CONFIG_VIDEO_SW_CURSOR is not set
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
> deleted file mode 100644
> index a62e14f7c61..00000000000
> --- a/include/configs/mx6cuboxi.h
> +++ /dev/null
> @@ -1,149 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright (C) 2015 Freescale Semiconductor, Inc.
> - *
> - * Configuration settings for the SolidRun mx6 based boards
> - */
> -#ifndef __MX6CUBOXI_CONFIG_H
> -#define __MX6CUBOXI_CONFIG_H
> -
> -#include "mx6_common.h"
> -
> -#include "imx6_spl.h"
> -
> -#define CONFIG_IMX_THERMAL
> -
> -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
> -#define CONFIG_MXC_UART
> -
> -/* MMC Configs */
> -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
> -
> -/* SATA Configuration */
> -#ifdef CONFIG_CMD_SATA
> -#define CONFIG_SYS_SATA_MAX_DEVICE 1
> -#define CONFIG_DWC_AHSATA_PORT_ID 0
> -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
> -#define CONFIG_LBA48
> -#endif
> -
> -/* Ethernet Configuration */
> -#define CONFIG_FEC_MXC
> -#define IMX_FEC_BASE ENET_BASE_ADDR
> -#define CONFIG_FEC_XCV_TYPE RGMII
> -#define CONFIG_FEC_MXC_PHYADDR 0
> -#define CONFIG_PHY_ATHEROS
> -
> -/* Framebuffer */
> -#define CONFIG_VIDEO_IPUV3
> -#define CONFIG_VIDEO_BMP_RLE8
> -#define CONFIG_SPLASH_SCREEN
> -#define CONFIG_SPLASH_SCREEN_ALIGN
> -#define CONFIG_BMP_16BPP
> -#define CONFIG_VIDEO_LOGO
> -#define CONFIG_VIDEO_BMP_LOGO
> -#define CONFIG_IMX_HDMI
> -#define CONFIG_IMX_VIDEO_SKIP
> -
> -/* USB */
> -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> -#define CONFIG_MXC_USB_FLAGS 0
> -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> -#define CONFIG_PREBOOT \
> - "if hdmidet; then " \
> - "usb start; " \
> - "setenv stdin serial,usbkbd; "\
> - "setenv stdout serial,vga; " \
> - "setenv stderr serial,vga; " \
> - "else " \
> - "setenv stdin serial; " \
> - "setenv stdout serial; " \
> - "setenv stderr serial; " \
> - "fi;"
> -
> -/* Command definition */
> -
> -#define CONFIG_MXC_UART_BASE UART1_BASE
> -#define CONSOLE_DEV "ttymxc0"
> -#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
> -
> -#ifndef CONFIG_SPL_BUILD
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "som_rev=undefined\0" \
> - "has_emmc=undefined\0" \
> - "fdtfile=undefined\0" \
> - "fdt_addr_r=0x18000000\0" \
> - "fdt_addr=0x18000000\0" \
> - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
> - "ramdisk_addr_r=0x13000000\0" \
> - "ramdiskaddr=0x13000000\0" \
> - "initrd_high=0xffffffff\0" \
> - "fdt_high=0xffffffff\0" \
> - "ip_dyn=yes\0" \
> - "console=" CONSOLE_DEV ",115200\0" \
> - "bootm_size=0x10000000\0" \
> - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
> - "finduuid=part uuid mmc 0:1 uuid\0" \
> - "update_sd_firmware=" \
> - "if test ${ip_dyn} = yes; then " \
> - "setenv get_cmd dhcp; " \
> - "else " \
> - "setenv get_cmd tftp; " \
> - "fi; " \
> - "if mmc dev ${mmcdev}; then " \
> - "if ${get_cmd} ${update_sd_firmware_filename}; then " \
> - "setexpr fw_sz ${filesize} / 0x200; " \
> - "setexpr fw_sz ${fw_sz} + 1; " \
> - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
> - "fi; " \
> - "fi\0" \
> - "findfdt="\
> - "if test ${board_rev} = MX6Q; then " \
> - "setenv fdtprefix imx6q; fi; " \
> - "if test ${board_rev} = MX6DL; then " \
> - "setenv fdtprefix imx6dl; fi; " \
> - "if test ${som_rev} = V15; then " \
> - "setenv fdtsuffix -som-v15; fi; " \
> - "if test ${has_emmc} = yes; then " \
> - "setenv emmcsuffix -emmc; fi; " \
> - "if test ${board_name} = HUMMINGBOARD2 ; then " \
> - "setenv fdtfile ${fdtprefix}-hummingboard2${emmcsuffix}${fdtsuffix}.dtb; fi; " \
> - "if test ${board_name} = HUMMINGBOARD ; then " \
> - "setenv fdtfile ${fdtprefix}-hummingboard${emmcsuffix}${fdtsuffix}.dtb; fi; " \
> - "if test ${board_name} = CUBOXI ; then " \
> - "setenv fdtfile ${fdtprefix}-cubox-i${emmcsuffix}${fdtsuffix}.dtb; fi; " \
> - "if test ${fdtfile} = undefined; then " \
> - "echo WARNING: Could not determine dtb to use; fi; \0" \
> - BOOTENV
> -
> -#define BOOT_TARGET_DEVICES(func) \
> - func(MMC, mmc, 0) \
> - func(SATA, sata, 0) \
> - func(USB, usb, 0) \
> - func(PXE, pxe, na) \
> - func(DHCP, dhcp, na)
> -
> -#include <config_distro_bootcmd.h>
> -
> -#else
> -#define CONFIG_EXTRA_ENV_SETTINGS
> -#endif /* CONFIG_SPL_BUILD */
> -
> -/* Physical Memory Map */
> -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
> -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> -
> -#define CONFIG_SYS_INIT_SP_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_ADDR \
> - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> -
> -/* Environment organization */
> -#define CONFIG_ENV_SIZE (8 * 1024)
> -#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE)
> -
> -#endif /* __MX6CUBOXI_CONFIG_H */
> --
> 2.19.1.1215.g8438c0b245-goog
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 65/93] arm: Remove mx6cuboxi board
2018-11-20 7:52 ` Mark Kettenis
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Mark,
On Tue, 20 Nov 2018 at 00:52, Mark Kettenis <mark.kettenis@xs4all.nl> wrote:
>
> > Date: Mon, 19 Nov 2018 08:53:45 -0700
> > From: Simon Glass <sjg@chromium.org>
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
>
> Hmm, isn't there something going wrong if a maintained board is
> getting removed? Especially ones that are still on the market? Just
> happened to pick this one since there we use these a lot in the
> OpenBSD project for building stuff.
Yes, it looks like Fabio is the maintainer, so hopefully he will take a look.
>
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > arch/arm/mach-imx/mx6/Kconfig | 1 -
> > board/solidrun/mx6cuboxi/Kconfig | 12 -
> > board/solidrun/mx6cuboxi/MAINTAINERS | 6 -
> > board/solidrun/mx6cuboxi/Makefile | 7 -
> > board/solidrun/mx6cuboxi/README | 21 -
> > board/solidrun/mx6cuboxi/mx6cuboxi.c | 857 ---------------------------
> > configs/mx6cuboxi_defconfig | 43 --
> > include/configs/mx6cuboxi.h | 149 -----
> > 8 files changed, 1096 deletions(-)
> > delete mode 100644 board/solidrun/mx6cuboxi/Kconfig
> > delete mode 100644 board/solidrun/mx6cuboxi/MAINTAINERS
> > delete mode 100644 board/solidrun/mx6cuboxi/Makefile
> > delete mode 100644 board/solidrun/mx6cuboxi/README
> > delete mode 100644 board/solidrun/mx6cuboxi/mx6cuboxi.c
> > delete mode 100644 configs/mx6cuboxi_defconfig
> > delete mode 100644 include/configs/mx6cuboxi.h
> >
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (64 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 65/93] arm: Remove mx6cuboxi board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-22 9:25 ` Christian Gmeiner
2018-11-19 15:53 ` [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board Simon Glass
` (31 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/bachmann/ot1200/Kconfig | 12 -
board/bachmann/ot1200/MAINTAINERS | 6 -
board/bachmann/ot1200/Makefile | 11 -
board/bachmann/ot1200/README | 20 --
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg | 154 ---------
board/bachmann/ot1200/ot1200.c | 356 ---------------------
board/bachmann/ot1200/ot1200_spl.c | 151 ---------
configs/ot1200_defconfig | 46 ---
configs/ot1200_spl_defconfig | 55 ----
include/configs/ot1200.h | 114 -------
10 files changed, 925 deletions(-)
delete mode 100644 board/bachmann/ot1200/Kconfig
delete mode 100644 board/bachmann/ot1200/MAINTAINERS
delete mode 100644 board/bachmann/ot1200/Makefile
delete mode 100644 board/bachmann/ot1200/README
delete mode 100644 board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
delete mode 100644 board/bachmann/ot1200/ot1200.c
delete mode 100644 board/bachmann/ot1200/ot1200_spl.c
delete mode 100644 configs/ot1200_defconfig
delete mode 100644 configs/ot1200_spl_defconfig
delete mode 100644 include/configs/ot1200.h
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
deleted file mode 100644
index 4ccb60a97fe..00000000000
--- a/board/bachmann/ot1200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OT1200
-
-config SYS_BOARD
- default "ot1200"
-
-config SYS_VENDOR
- default "bachmann"
-
-config SYS_CONFIG_NAME
- default "ot1200"
-
-endif
diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS
deleted file mode 100644
index ad75c24ee46..00000000000
--- a/board/bachmann/ot1200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BACHMANN ELECTRONIC OT1200 BOARD
-M: Christian Gmeiner <christian.gmeiner@gmail.com>
-S: Maintained
-F: board/bachmann/ot1200
-F: include/configs/ot1200.h
-F: configs/ot1200*_defconfig
diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
deleted file mode 100644
index 73000e3d3ce..00000000000
--- a/board/bachmann/ot1200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
-# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
-# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
-
-ifdef CONFIG_SPL_BUILD
-obj-y := ot1200.o ot1200_spl.o
-else
-obj-y := ot1200.o
-endif
diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README
deleted file mode 100644
index c03d44e458a..00000000000
--- a/board/bachmann/ot1200/README
+++ /dev/null
@@ -1,20 +0,0 @@
-U-Boot for the Bachmann electronic GmbH OT1200 devices
-
-There are two different versions of the base board, which differ
-in the way ethernet is done. The variant detection is done during
-runtime based on the address of the found phy.
-
-- "mr" variant
-FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
-port is always up and auto-negotiation is not possible.
-
-- normal variant
-FEC is connected to a normal phy and auto-negotiation is possible.
-
-
-The variant name is part of the dtb file name loaded by u-boot. This
-make is possible to boot the linux kernel and make use variant specific
-devicetree (fixed-phy link).
-
-In order to support different display resoltuions/sizes the OT1200 devices
-are making use of EDID data stored in an i2c EEPROM.
diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
deleted file mode 100644
index ba5c0747979..00000000000
--- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
+++ /dev/null
@@ -1,154 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7974
-DATA 4 0x021b0010 0xDB538F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005A1023
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19308030
-DATA 4 0x021b001c 0x19308038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
-
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
deleted file mode 100644
index 2d734416203..00000000000
--- a/board/bachmann/ot1200/ot1200.c
+++ /dev/null
@@ -1,356 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014, Bachmann electronic GmbH
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <malloc.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <pca953x.h>
-#include <asm/gpio.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
- PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
- PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
- PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
- MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
-static void setup_iomux_spi(void)
-{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
-}
-
-static iomux_v3_cfg_t const feature_pads[] = {
- /* SD card detect */
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
-
- /* eMMC soldered? */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
-};
-
-static void setup_iomux_features(void)
-{
- imx_iomux_v3_setup_multiple_pads(feature_pads,
- ARRAY_SIZE(feature_pads));
-}
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C2 - EEPROM */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
- .gp = IMX_GPIO_NR(2, 30)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
- .gp = IMX_GPIO_NR(3, 16)
- }
-};
-
-/* I2C3 - IO expander */
-static struct i2c_pads_info i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
- .gp = IMX_GPIO_NR(3, 17)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-
-static void setup_iomux_i2c(void)
-{
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-}
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC33, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-int board_early_init_f(void)
-{
- ccgr_init();
- gpr_init();
-
- setup_iomux_uart();
- setup_iomux_spi();
- setup_iomux_i2c();
- setup_iomux_features();
-
- return 0;
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret;
-
- if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
- gpio_direction_input(IMX_GPIO_NR(4, 5));
- ret = gpio_get_value(IMX_GPIO_NR(4, 5));
- } else {
- gpio_direction_input(IMX_GPIO_NR(1, 5));
- ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
- }
-
- return ret;
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- u32 index = 0;
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
- usdhc_cfg[0].max_bus_width = 8;
- usdhc_cfg[1].max_bus_width = 4;
-
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static void leds_on(void)
-{
- /* turn on all possible leds connected via GPIO expander */
- i2c_set_bus_num(2);
- pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
- pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
-}
-
-static void backlight_lcd_off(void)
-{
- unsigned gpio = IMX_GPIO_NR(2, 0);
- gpio_direction_output(gpio, 0);
-
- gpio = IMX_GPIO_NR(2, 3);
- gpio_direction_output(gpio, 0);
-}
-
-int board_eth_init(bd_t *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
-
- /* scan phy 0 and 5 */
- phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
-
- /* depending on the phy address we can detect our board version */
- if (phydev->addr == 0)
- env_set("boardver", "");
- else
- env_set("boardver", "mr");
-
- printf("using phy at %d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret)
- goto free_phydev;
-
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- backlight_lcd_off();
-
- leds_on();
-
-#ifdef CONFIG_SATA
- setup_sata();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: "CONFIG_SYS_BOARD"\n");
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
- return 0;
-}
diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c
deleted file mode 100644
index a3a822f65a1..00000000000
--- a/board/bachmann/ot1200/ot1200_spl.c
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015, Bachmann electronic GmbH
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/arch/mx6-ddr.h>
-
-/* Configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
- /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
- .dram_sdclk_0 = 0x00000028,
- .dram_sdclk_1 = 0x00000028,
- .dram_cas = 0x00000028,
- .dram_ras = 0x00000028,
- .dram_reset = 0x00000028,
- /* SDCKE[0:1]: 100k pull-up */
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- /* SDBA2: pull-up disabled */
- .dram_sdba2 = 0x00000000,
- /* SDODT[0:1]: 100k pull-up, 48 ohm */
- .dram_sdodt0 = 0x00000028,
- .dram_sdodt1 = 0x00000028,
- /* SDQS[0:7]: Differential input, 48 ohm */
- .dram_sdqs0 = 0x00000028,
- .dram_sdqs1 = 0x00000028,
- .dram_sdqs2 = 0x00000028,
- .dram_sdqs3 = 0x00000028,
- .dram_sdqs4 = 0x00000028,
- .dram_sdqs5 = 0x00000028,
- .dram_sdqs6 = 0x00000028,
- .dram_sdqs7 = 0x00000028,
- /* DQM[0:7]: Differential input, 48 ohm */
- .dram_dqm0 = 0x00000028,
- .dram_dqm1 = 0x00000028,
- .dram_dqm2 = 0x00000028,
- .dram_dqm3 = 0x00000028,
- .dram_dqm4 = 0x00000028,
- .dram_dqm5 = 0x00000028,
- .dram_dqm6 = 0x00000028,
- .dram_dqm7 = 0x00000028,
-};
-
-/* Configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
- /* DDR3 */
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- /* Disable DDR pullups */
- .grp_ddrpke = 0x00000000,
- /* ADDR[00:16], SDBA[0:1]: 48 ohm */
- .grp_addds = 0x00000028,
- /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
- .grp_ctlds = 0x00000028,
- /* DATA[00:63]: Differential input, 48 ohm */
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000028,
- .grp_b1ds = 0x00000028,
- .grp_b2ds = 0x00000028,
- .grp_b3ds = 0x00000028,
- .grp_b4ds = 0x00000028,
- .grp_b5ds = 0x00000028,
- .grp_b6ds = 0x00000028,
- .grp_b7ds = 0x00000028,
-};
-
-static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
- /* Width of data bus: 0=16, 1=32, 2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* Single chip select */
- .ncs = 1,
- .cs1_mirror = 0, /* war 0 */
- .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
- .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg micron_2gib_1600 = {
- .mem_speed = 1600,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 1,
-};
-
-static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
- /* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00260025,
- .p0_mpwldectrl1 = 0x00270021,
- .p1_mpwldectrl0 = 0x00180034,
- .p1_mpwldectrl1 = 0x00180024,
- /* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x04380344,
- .p0_mpdgctrl1 = 0x0330032C,
- .p1_mpdgctrl0 = 0x0338033C,
- .p1_mpdgctrl1 = 0x032C0300,
- /* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x3C2E3238,
- .p1_mprddlctl = 0x3A2E303C,
- /* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x36384036,
- .p1_mpwrdlctl = 0x442E4438,
-};
-
-static void ot1200_spl_dram_init(void)
-{
- mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
- mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib,
- µn_2gib_1600);
-}
-
-/*
- * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
- * - we have a stack and a place to store GD, both in SRAM
- * - no variable global data is available
- */
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- /* iomux and setup of i2c */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* configure MMDC for SDRAM width/size and per-model calibration */
- ot1200_spl_dram_init();
-}
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
deleted file mode 100644
index b70f44df8ea..00000000000
--- a/configs/ot1200_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_OT1200=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
deleted file mode 100644
index d5962e64564..00000000000
--- a/configs/ot1200_spl_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_OT1200=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=3
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_DWC_AHSATA=y
-CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
deleted file mode 100644
index 776835a766e..00000000000
--- a/include/configs/ot1200.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014 Bachmann electronic GmbH
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/* UART Configs */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* SF Configs */
-#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-
-/* IO expander */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* OCOTP Configs */
-#define CONFIG_IMX_OTP
-#define IMX_OTP_BASE OCOTP_BASE_ADDR
-#define IMX_OTP_ADDR_MAX 0x7F
-#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
-#define IMX_OTPWRITE_ENABLED
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-/* USB Configs */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_DWC_AHSATA_PORT_ID 0
-#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* SPL */
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#endif
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE MII100
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0x5
-#define CONFIG_PHY_SMSC
-
-#ifndef CONFIG_SPL
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_BUS 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
-
-#define CONFIG_PREBOOT ""
-
-/* Thermal support */
-#define CONFIG_IMX_THERMAL
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
-#define CONFIG_ENV_OFFSET (1024 * 1024)
-/* M25P16 has an erase size of 64 KiB */
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_BOOTP_BOOTFILE
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-19 15:53 ` [U-Boot] [PATCH 66/93] arm: Remove ot1200 board Simon Glass
@ 2018-11-22 9:25 ` Christian Gmeiner
2018-11-22 12:52 ` Tom Rini
2018-11-23 0:33 ` Fabio Estevam
0 siblings, 2 replies; 211+ messages in thread
From: Christian Gmeiner @ 2018-11-22 9:25 UTC (permalink / raw)
To: u-boot
Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
As the board is still mainted I will NAK it for the moment. Are there
any hints want needs to be done
to port thie board over to new DM stuff?
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 9:25 ` Christian Gmeiner
@ 2018-11-22 12:52 ` Tom Rini
2018-11-22 13:24 ` Marek Vasut
2018-11-23 0:33 ` Fabio Estevam
1 sibling, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-22 12:52 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
>
> As the board is still mainted I will NAK it for the moment. Are there
> any hints want needs to be done
> to port thie board over to new DM stuff?
Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
needs more work, but this is the board-level work that needs doing.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 12:52 ` Tom Rini
@ 2018-11-22 13:24 ` Marek Vasut
2018-11-22 13:28 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Marek Vasut @ 2018-11-22 13:24 UTC (permalink / raw)
To: u-boot
On 11/22/2018 01:52 PM, Tom Rini wrote:
> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
>
>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
>>>
>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
>>> Remove it.
>>>
>>
>> As the board is still mainted I will NAK it for the moment. Are there
>> any hints want needs to be done
>> to port thie board over to new DM stuff?
>
> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> needs more work, but this is the board-level work that needs doing.
Wasn't there a possibility to use platform data in board file instead of
DT ? Or is DT mandatory now , including the libfdt overhead ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 13:24 ` Marek Vasut
@ 2018-11-22 13:28 ` Tom Rini
2018-11-22 13:30 ` Marek Vasut
2018-11-22 14:44 ` Simon Goldschmidt
0 siblings, 2 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-22 13:28 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> On 11/22/2018 01:52 PM, Tom Rini wrote:
> > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> >
> >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
> >>>
> >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> >>> Remove it.
> >>>
> >>
> >> As the board is still mainted I will NAK it for the moment. Are there
> >> any hints want needs to be done
> >> to port thie board over to new DM stuff?
> >
> > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > needs more work, but this is the board-level work that needs doing.
>
> Wasn't there a possibility to use platform data in board file instead of
> DT ? Or is DT mandatory now , including the libfdt overhead ?
In short, DT for U-Boot and platform data for SPL is what's recommended,
yes.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 13:28 ` Tom Rini
@ 2018-11-22 13:30 ` Marek Vasut
2018-11-22 13:32 ` Tom Rini
2018-11-22 14:44 ` Simon Goldschmidt
1 sibling, 1 reply; 211+ messages in thread
From: Marek Vasut @ 2018-11-22 13:30 UTC (permalink / raw)
To: u-boot
On 11/22/2018 02:28 PM, Tom Rini wrote:
> On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
>> On 11/22/2018 01:52 PM, Tom Rini wrote:
>>> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
>>>
>>>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
>>>>>
>>>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
>>>>> Remove it.
>>>>>
>>>>
>>>> As the board is still mainted I will NAK it for the moment. Are there
>>>> any hints want needs to be done
>>>> to port thie board over to new DM stuff?
>>>
>>> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
>>> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
>>> needs more work, but this is the board-level work that needs doing.
>>
>> Wasn't there a possibility to use platform data in board file instead of
>> DT ? Or is DT mandatory now , including the libfdt overhead ?
>
> In short, DT for U-Boot and platform data for SPL is what's recommended,
> yes.
If the board is limited, can it use only platdata ? Some platforms don't
even have DT support at all.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 13:30 ` Marek Vasut
@ 2018-11-22 13:32 ` Tom Rini
2018-11-22 13:40 ` Marek Vasut
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-22 13:32 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 02:30:11PM +0100, Marek Vasut wrote:
> On 11/22/2018 02:28 PM, Tom Rini wrote:
> > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> >> On 11/22/2018 01:52 PM, Tom Rini wrote:
> >>> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> >>>
> >>>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
> >>>>>
> >>>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> >>>>> Remove it.
> >>>>>
> >>>>
> >>>> As the board is still mainted I will NAK it for the moment. Are there
> >>>> any hints want needs to be done
> >>>> to port thie board over to new DM stuff?
> >>>
> >>> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> >>> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> >>> needs more work, but this is the board-level work that needs doing.
> >>
> >> Wasn't there a possibility to use platform data in board file instead of
> >> DT ? Or is DT mandatory now , including the libfdt overhead ?
> >
> > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > yes.
>
> If the board is limited, can it use only platdata ? Some platforms don't
> even have DT support at all.
I'm sorry, I don't quite follow you. If the board has limited resources
prior to full U-Boot then yes, platform data. If the board has so
limited resources during full U-Boot that we can't have a DT, what
platform are we talking about?
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 13:32 ` Tom Rini
@ 2018-11-22 13:40 ` Marek Vasut
0 siblings, 0 replies; 211+ messages in thread
From: Marek Vasut @ 2018-11-22 13:40 UTC (permalink / raw)
To: u-boot
On 11/22/2018 02:32 PM, Tom Rini wrote:
> On Thu, Nov 22, 2018 at 02:30:11PM +0100, Marek Vasut wrote:
>> On 11/22/2018 02:28 PM, Tom Rini wrote:
>>> On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
>>>> On 11/22/2018 01:52 PM, Tom Rini wrote:
>>>>> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
>>>>>
>>>>>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <sjg@chromium.org>:
>>>>>>>
>>>>>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
>>>>>>> Remove it.
>>>>>>>
>>>>>>
>>>>>> As the board is still mainted I will NAK it for the moment. Are there
>>>>>> any hints want needs to be done
>>>>>> to port thie board over to new DM stuff?
>>>>>
>>>>> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
>>>>> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
>>>>> needs more work, but this is the board-level work that needs doing.
>>>>
>>>> Wasn't there a possibility to use platform data in board file instead of
>>>> DT ? Or is DT mandatory now , including the libfdt overhead ?
>>>
>>> In short, DT for U-Boot and platform data for SPL is what's recommended,
>>> yes.
>>
>> If the board is limited, can it use only platdata ? Some platforms don't
>> even have DT support at all.
>
> I'm sorry, I don't quite follow you. If the board has limited resources
> prior to full U-Boot then yes, platform data. If the board has so
> limited resources during full U-Boot that we can't have a DT, what
> platform are we talking about?
I don't have one in mind, but I don't think the DT/platdata selection is
specific to SPL. If a platform doesn't have DT support, it can very well
use platdata throughout the whole process.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 13:28 ` Tom Rini
2018-11-22 13:30 ` Marek Vasut
@ 2018-11-22 14:44 ` Simon Goldschmidt
2018-11-22 17:01 ` Tom Rini
1 sibling, 1 reply; 211+ messages in thread
From: Simon Goldschmidt @ 2018-11-22 14:44 UTC (permalink / raw)
To: u-boot
Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > >
> > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> sjg at chromium.org>:
> > >>>
> > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > >>> Remove it.
> > >>>
> > >>
> > >> As the board is still mainted I will NAK it for the moment. Are there
> > >> any hints want needs to be done
> > >> to port thie board over to new DM stuff?
> > >
> > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > needs more work, but this is the board-level work that needs doing.
> >
> > Wasn't there a possibility to use platform data in board file instead of
> > DT ? Or is DT mandatory now , including the libfdt overhead ?
>
> In short, DT for U-Boot and platform data for SPL is what's recommended,
> yes.
>
This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
seems a little strange or outdated overall.
Would there be some kind of reference architecture or mach to look at
what's the suggested/up-to-date way to implement SPL? Also regarding code
flow?
Simon
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 14:44 ` Simon Goldschmidt
@ 2018-11-22 17:01 ` Tom Rini
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-22 17:01 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
>
> > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > >
> > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > sjg at chromium.org>:
> > > >>>
> > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > >>> Remove it.
> > > >>>
> > > >>
> > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > >> any hints want needs to be done
> > > >> to port thie board over to new DM stuff?
> > > >
> > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > needs more work, but this is the board-level work that needs doing.
> > >
> > > Wasn't there a possibility to use platform data in board file instead of
> > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> >
> > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > yes.
> >
>
> This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> seems a little strange or outdated overall.
>
> Would there be some kind of reference architecture or mach to look at
> what's the suggested/up-to-date way to implement SPL? Also regarding code
> flow?
So, SPL is where things get, ahem, fuzzy. While I don't want to
encourage boundless growth in U-Boot proper, we aren't exactly size
constrained (but rather, functional/logical constrained). But in SPL,
yes, we have many platforms with 32/64/128 kilobyte hard limits (and
some smaller) and we can't always shove in a "TPL" before SPL either.
So in SPL we do make use of platform data instead. While not the
smallest size constraint, am335x_hs_evm is a reasonable thing to look at
in this case.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 17:01 ` Tom Rini
@ 2018-11-22 20:50 ` Simon Glass
2018-11-25 21:09 ` Simon Goldschmidt
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi,
On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> >
> > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > >
> > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > sjg at chromium.org>:
> > > > >>>
> > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > >>> Remove it.
> > > > >>>
> > > > >>
> > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > >> any hints want needs to be done
> > > > >> to port thie board over to new DM stuff?
> > > > >
> > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > needs more work, but this is the board-level work that needs doing.
> > > >
> > > > Wasn't there a possibility to use platform data in board file instead of
> > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > >
> > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > yes.
> > >
> >
> > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > seems a little strange or outdated overall.
> >
> > Would there be some kind of reference architecture or mach to look at
> > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > flow?
>
> So, SPL is where things get, ahem, fuzzy. While I don't want to
> encourage boundless growth in U-Boot proper, we aren't exactly size
> constrained (but rather, functional/logical constrained). But in SPL,
> yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> some smaller) and we can't always shove in a "TPL" before SPL either.
> So in SPL we do make use of platform data instead. While not the
> smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> in this case.
Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
still uses DT, but it gets converted into C structs so saves code
space.
firefly-rk3288 is a pretty good DM/DT example, including SPL.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 20:50 ` Simon Glass
@ 2018-11-25 21:09 ` Simon Goldschmidt
2018-11-26 3:00 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Simon Goldschmidt @ 2018-11-25 21:09 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
>
> Hi,
>
> On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> > >
> > > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > > >
> > > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > > sjg at chromium.org>:
> > > > > >>>
> > > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > >>> Remove it.
> > > > > >>>
> > > > > >>
> > > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > > >> any hints want needs to be done
> > > > > >> to port thie board over to new DM stuff?
> > > > > >
> > > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > > needs more work, but this is the board-level work that needs doing.
> > > > >
> > > > > Wasn't there a possibility to use platform data in board file instead of
> > > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > > >
> > > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > > yes.
> > > >
> > >
> > > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > > seems a little strange or outdated overall.
> > >
> > > Would there be some kind of reference architecture or mach to look at
> > > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > > flow?
> >
> > So, SPL is where things get, ahem, fuzzy. While I don't want to
> > encourage boundless growth in U-Boot proper, we aren't exactly size
> > constrained (but rather, functional/logical constrained). But in SPL,
> > yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> > some smaller) and we can't always shove in a "TPL" before SPL either.
> > So in SPL we do make use of platform data instead. While not the
> > smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> > in this case.
>
> Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> still uses DT, but it gets converted into C structs so saves code
> space.
>
> firefly-rk3288 is a pretty good DM/DT example, including SPL.
I've currently got an issue on socfpga gen5 that could be solved best
by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
problem for CRC calculation). However, it could probably also solve by
using platform data (but that doesn't work out of the box, yet). The
problem with CONFIG_OF_EMBED is that I think it's OK to enable this
for SPL but I don't like enabling it for U-Boot, so:
Would it make sense to duplicate the whole "Provider of DTB for OF
control" choice so that it can be OF_EMBED for SPL but different for
U-Boot? Or does it make more sense to convert socfpga gen5 to use
OF_PLATDATA?
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-25 21:09 ` Simon Goldschmidt
@ 2018-11-26 3:00 ` Simon Glass
2018-11-26 6:05 ` Simon Goldschmidt
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-26 3:00 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi,
> >
> > On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > > > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> > > >
> > > > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > > > >
> > > > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > > > sjg at chromium.org>:
> > > > > > >>>
> > > > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > > >>> Remove it.
> > > > > > >>>
> > > > > > >>
> > > > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > > > >> any hints want needs to be done
> > > > > > >> to port thie board over to new DM stuff?
> > > > > > >
> > > > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > > > needs more work, but this is the board-level work that needs doing.
> > > > > >
> > > > > > Wasn't there a possibility to use platform data in board file instead of
> > > > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > > > >
> > > > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > > > yes.
> > > > >
> > > >
> > > > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > > > seems a little strange or outdated overall.
> > > >
> > > > Would there be some kind of reference architecture or mach to look at
> > > > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > > > flow?
> > >
> > > So, SPL is where things get, ahem, fuzzy. While I don't want to
> > > encourage boundless growth in U-Boot proper, we aren't exactly size
> > > constrained (but rather, functional/logical constrained). But in SPL,
> > > yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> > > some smaller) and we can't always shove in a "TPL" before SPL either.
> > > So in SPL we do make use of platform data instead. While not the
> > > smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> > > in this case.
> >
> > Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> > still uses DT, but it gets converted into C structs so saves code
> > space.
> >
> > firefly-rk3288 is a pretty good DM/DT example, including SPL.
>
> I've currently got an issue on socfpga gen5 that could be solved best
> by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
> problem for CRC calculation). However, it could probably also solve by
> using platform data (but that doesn't work out of the box, yet). The
> problem with CONFIG_OF_EMBED is that I think it's OK to enable this
> for SPL but I don't like enabling it for U-Boot, so:
>
> Would it make sense to duplicate the whole "Provider of DTB for OF
> control" choice so that it can be OF_EMBED for SPL but different for
> U-Boot? Or does it make more sense to convert socfpga gen5 to use
> OF_PLATDATA?
We should not be using OF_EMBED in in-tree boards or production code.
Can you please explain the issue a bit more?
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-26 3:00 ` Simon Glass
@ 2018-11-26 6:05 ` Simon Goldschmidt
2018-12-05 13:21 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Simon Goldschmidt @ 2018-11-26 6:05 UTC (permalink / raw)
To: u-boot
[I've cut down the CC list a bit due to some gmail warnings]
On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Simon,
>
> On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com> wrote:
> >
> > On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi,
> > >
> > > On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > > > > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> > > > >
> > > > > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > > > > >
> > > > > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > > > > sjg at chromium.org>:
> > > > > > > >>>
> > > > > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > > > >>> Remove it.
> > > > > > > >>>
> > > > > > > >>
> > > > > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > > > > >> any hints want needs to be done
> > > > > > > >> to port thie board over to new DM stuff?
> > > > > > > >
> > > > > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > > > > needs more work, but this is the board-level work that needs doing.
> > > > > > >
> > > > > > > Wasn't there a possibility to use platform data in board file instead of
> > > > > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > > > > >
> > > > > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > > > > yes.
> > > > > >
> > > > >
> > > > > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > > > > seems a little strange or outdated overall.
> > > > >
> > > > > Would there be some kind of reference architecture or mach to look at
> > > > > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > > > > flow?
> > > >
> > > > So, SPL is where things get, ahem, fuzzy. While I don't want to
> > > > encourage boundless growth in U-Boot proper, we aren't exactly size
> > > > constrained (but rather, functional/logical constrained). But in SPL,
> > > > yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> > > > some smaller) and we can't always shove in a "TPL" before SPL either.
> > > > So in SPL we do make use of platform data instead. While not the
> > > > smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> > > > in this case.
> > >
> > > Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> > > still uses DT, but it gets converted into C structs so saves code
> > > space.
> > >
> > > firefly-rk3288 is a pretty good DM/DT example, including SPL.
> >
> > I've currently got an issue on socfpga gen5 that could be solved best
> > by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
> > problem for CRC calculation). However, it could probably also solve by
> > using platform data (but that doesn't work out of the box, yet). The
> > problem with CONFIG_OF_EMBED is that I think it's OK to enable this
> > for SPL but I don't like enabling it for U-Boot, so:
> >
> > Would it make sense to duplicate the whole "Provider of DTB for OF
> > control" choice so that it can be OF_EMBED for SPL but different for
> > U-Boot? Or does it make more sense to convert socfpga gen5 to use
> > OF_PLATDATA?
>
> We should not be using OF_EMBED in in-tree boards or production code.
What's the reason for this? I can understand this for U-Boot, and I
can understand that it's at least theoretically a bit cleaner for SPL,
too. But there are some drawbacks when doing this in SPL where code is
not relocated:
- you lose the ability to check total size in linker file (which is
bad for size-constrained platforms: sometimes you notice failure only
when booting)
- you get an inconsistent memory layout regarding read/write: the
linker places bss at the end but then, DTB follows as const data
- binary size "on disk" grows due to this inconsistent memory layout
(since the flat binary includes the DTB, it needs to include the
zeroed-out bss, too)
- "spl/u-boot-spl.hex" created by the default Makefiles does not seem
to include the DTB
> Can you please explain the issue a bit more?
Of course: socfpga gen5 has a feature where the boot rom can jump to
SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
the boot rom can check its consistency by calculating a CRC over one
specified range in SRAM. On first boot, SPL stores its start, length
and CRC value to special registers for the boot rom. Since the
contents of bss changes while SPL is running, bss cannot be included
in this CRC range. (Same goes for the '.data' region, but it's
possible to build SPL without actually using it.)
So to ensure the DTB is untouched, I have to make sure it has a lower
address than the bss section. Using OF_EMBED does this for me. And I
expect using platform data would work too. Do you have another idea
how to achieve my goal of combining all write-only sections in SPL
into one block?
Oh, and I currently count 109 defconfig files containing "OF_EMBED",
so I wasn't aware that this should not be used. Maybe these platforms
have similar reasons like I have and would enable OF_EMBED only for
SPL if they could. At least for socfpga_stratix10 that should work.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-26 6:05 ` Simon Goldschmidt
@ 2018-12-05 13:21 ` Simon Glass
2018-12-05 13:38 ` Simon Goldschmidt
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-12-05 13:21 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Sun, 25 Nov 2018 at 23:05, Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> [I've cut down the CC list a bit due to some gmail warnings]
> On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Simon,
> >
> > On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
> > <simon.k.r.goldschmidt@gmail.com> wrote:
> > >
> > > On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Hi,
> > > >
> > > > On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > > > > > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> > > > > >
> > > > > > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > > > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > > > > > >
> > > > > > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > > > > > sjg at chromium.org>:
> > > > > > > > >>>
> > > > > > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > > > > >>> Remove it.
> > > > > > > > >>>
> > > > > > > > >>
> > > > > > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > > > > > >> any hints want needs to be done
> > > > > > > > >> to port thie board over to new DM stuff?
> > > > > > > > >
> > > > > > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > > > > > needs more work, but this is the board-level work that needs doing.
> > > > > > > >
> > > > > > > > Wasn't there a possibility to use platform data in board file instead of
> > > > > > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > > > > > >
> > > > > > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > > > > > yes.
> > > > > > >
> > > > > >
> > > > > > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > > > > > seems a little strange or outdated overall.
> > > > > >
> > > > > > Would there be some kind of reference architecture or mach to look at
> > > > > > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > > > > > flow?
> > > > >
> > > > > So, SPL is where things get, ahem, fuzzy. While I don't want to
> > > > > encourage boundless growth in U-Boot proper, we aren't exactly size
> > > > > constrained (but rather, functional/logical constrained). But in SPL,
> > > > > yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> > > > > some smaller) and we can't always shove in a "TPL" before SPL either.
> > > > > So in SPL we do make use of platform data instead. While not the
> > > > > smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> > > > > in this case.
> > > >
> > > > Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> > > > still uses DT, but it gets converted into C structs so saves code
> > > > space.
> > > >
> > > > firefly-rk3288 is a pretty good DM/DT example, including SPL.
> > >
> > > I've currently got an issue on socfpga gen5 that could be solved best
> > > by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
> > > problem for CRC calculation). However, it could probably also solve by
> > > using platform data (but that doesn't work out of the box, yet). The
> > > problem with CONFIG_OF_EMBED is that I think it's OK to enable this
> > > for SPL but I don't like enabling it for U-Boot, so:
> > >
> > > Would it make sense to duplicate the whole "Provider of DTB for OF
> > > control" choice so that it can be OF_EMBED for SPL but different for
> > > U-Boot? Or does it make more sense to convert socfpga gen5 to use
> > > OF_PLATDATA?
> >
> > We should not be using OF_EMBED in in-tree boards or production code.
>
> What's the reason for this? I can understand this for U-Boot, and I
> can understand that it's at least theoretically a bit cleaner for SPL,
> too. But there are some drawbacks when doing this in SPL where code is
> not relocated:
> - you lose the ability to check total size in linker file (which is
> bad for size-constrained platforms: sometimes you notice failure only
> when booting)
You can add an SPL size check in Makefile.spl if you like.
> - you get an inconsistent memory layout regarding read/write: the
> linker places bss at the end but then, DTB follows as const data
This should be handled by the $(SPL-BIN)-pad.bin file (or by binman if
you are using that).
> - binary size "on disk" grows due to this inconsistent memory layout
> (since the flat binary includes the DTB, it needs to include the
> zeroed-out bss, too)
Right, but this is a few bytes. Why does it matter?
> - "spl/u-boot-spl.hex" created by the default Makefiles does not seem
> to include the DTB
That might just be a bug.
>
> > Can you please explain the issue a bit more?
>
> Of course: socfpga gen5 has a feature where the boot rom can jump to
> SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
> the boot rom can check its consistency by calculating a CRC over one
> specified range in SRAM. On first boot, SPL stores its start, length
> and CRC value to special registers for the boot rom. Since the
> contents of bss changes while SPL is running, bss cannot be included
> in this CRC range. (Same goes for the '.data' region, but it's
> possible to build SPL without actually using it.)
How about calculating that checksum at build time instead? You could
use binman to do that.
>
> So to ensure the DTB is untouched, I have to make sure it has a lower
> address than the bss section. Using OF_EMBED does this for me. And I
> expect using platform data would work too. Do you have another idea
> how to achieve my goal of combining all write-only sections in SPL
> into one block?
Yes, do it at build time. Or calculate your CRC before you write any
BSS variables.
>
> Oh, and I currently count 109 defconfig files containing "OF_EMBED",
> so I wasn't aware that this should not be used. Maybe these platforms
> have similar reasons like I have and would enable OF_EMBED only for
> SPL if they could. At least for socfpga_stratix10 that should work.
That is very bad news. I'll see about adding a Makefile warning.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-12-05 13:21 ` Simon Glass
@ 2018-12-05 13:38 ` Simon Goldschmidt
2018-12-05 13:54 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Simon Goldschmidt @ 2018-12-05 13:38 UTC (permalink / raw)
To: u-boot
On Wed, Dec 5, 2018 at 2:21 PM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Simon,
>
> On Sun, 25 Nov 2018 at 23:05, Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com> wrote:
> >
> > [I've cut down the CC list a bit due to some gmail warnings]
> > On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
> > > <simon.k.r.goldschmidt@gmail.com> wrote:
> > > >
> > > > On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> > > > > >
> > > > > > On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > > > > > > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> > > > > > >
> > > > > > > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > > > > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > > > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > > > > > > >
> > > > > > > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > > > > > > sjg at chromium.org>:
> > > > > > > > > >>>
> > > > > > > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > > > > > >>> Remove it.
> > > > > > > > > >>>
> > > > > > > > > >>
> > > > > > > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > > > > > > >> any hints want needs to be done
> > > > > > > > > >> to port thie board over to new DM stuff?
> > > > > > > > > >
> > > > > > > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > > > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > > > > > > needs more work, but this is the board-level work that needs doing.
> > > > > > > > >
> > > > > > > > > Wasn't there a possibility to use platform data in board file instead of
> > > > > > > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > > > > > > >
> > > > > > > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > > > > > > yes.
> > > > > > > >
> > > > > > >
> > > > > > > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > > > > > > seems a little strange or outdated overall.
> > > > > > >
> > > > > > > Would there be some kind of reference architecture or mach to look at
> > > > > > > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > > > > > > flow?
> > > > > >
> > > > > > So, SPL is where things get, ahem, fuzzy. While I don't want to
> > > > > > encourage boundless growth in U-Boot proper, we aren't exactly size
> > > > > > constrained (but rather, functional/logical constrained). But in SPL,
> > > > > > yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> > > > > > some smaller) and we can't always shove in a "TPL" before SPL either.
> > > > > > So in SPL we do make use of platform data instead. While not the
> > > > > > smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> > > > > > in this case.
> > > > >
> > > > > Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> > > > > still uses DT, but it gets converted into C structs so saves code
> > > > > space.
> > > > >
> > > > > firefly-rk3288 is a pretty good DM/DT example, including SPL.
> > > >
> > > > I've currently got an issue on socfpga gen5 that could be solved best
> > > > by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
> > > > problem for CRC calculation). However, it could probably also solve by
> > > > using platform data (but that doesn't work out of the box, yet). The
> > > > problem with CONFIG_OF_EMBED is that I think it's OK to enable this
> > > > for SPL but I don't like enabling it for U-Boot, so:
> > > >
> > > > Would it make sense to duplicate the whole "Provider of DTB for OF
> > > > control" choice so that it can be OF_EMBED for SPL but different for
> > > > U-Boot? Or does it make more sense to convert socfpga gen5 to use
> > > > OF_PLATDATA?
> > >
> > > We should not be using OF_EMBED in in-tree boards or production code.
> >
> > What's the reason for this? I can understand this for U-Boot, and I
> > can understand that it's at least theoretically a bit cleaner for SPL,
> > too. But there are some drawbacks when doing this in SPL where code is
> > not relocated:
> > - you lose the ability to check total size in linker file (which is
> > bad for size-constrained platforms: sometimes you notice failure only
> > when booting)
>
> You can add an SPL size check in Makefile.spl if you like.
That might be required, yes.
> > - you get an inconsistent memory layout regarding read/write: the
> > linker places bss at the end but then, DTB follows as const data
>
> This should be handled by the $(SPL-BIN)-pad.bin file (or by binman if
> you are using that).
I don't understand that. How does the padding help? I have these
sections (roughly):
- text: readonly
- bss: writable
- DTB: readonly, added as post build step after linking
How does $(SPL-BIN)-pad.bin help?
> > - binary size "on disk" grows due to this inconsistent memory layout
> > (since the flat binary includes the DTB, it needs to include the
> > zeroed-out bss, too)
>
> Right, but this is a few bytes. Why does it matter?
>
> > - "spl/u-boot-spl.hex" created by the default Makefiles does not seem
> > to include the DTB
>
> That might just be a bug.
It might, yes. The hex file is currently built from the elf file, so
there's no DTB in there.
> >
> > > Can you please explain the issue a bit more?
> >
> > Of course: socfpga gen5 has a feature where the boot rom can jump to
> > SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
> > the boot rom can check its consistency by calculating a CRC over one
> > specified range in SRAM. On first boot, SPL stores its start, length
> > and CRC value to special registers for the boot rom. Since the
> > contents of bss changes while SPL is running, bss cannot be included
> > in this CRC range. (Same goes for the '.data' region, but it's
> > possible to build SPL without actually using it.)
>
> How about calculating that checksum at build time instead? You could
> use binman to do that.
>
> >
> > So to ensure the DTB is untouched, I have to make sure it has a lower
> > address than the bss section. Using OF_EMBED does this for me. And I
> > expect using platform data would work too. Do you have another idea
> > how to achieve my goal of combining all write-only sections in SPL
> > into one block?
>
> Yes, do it at build time. Or calculate your CRC before you write any
> BSS variables.
Creating the correct checksum is not the point. I can do that before using bss.
The problem is that on the next boot, this checksum is not valid any
more because bss might have changed.
> >
> > Oh, and I currently count 109 defconfig files containing "OF_EMBED",
> > so I wasn't aware that this should not be used. Maybe these platforms
> > have similar reasons like I have and would enable OF_EMBED only for
> > SPL if they could. At least for socfpga_stratix10 that should work.
>
> That is very bad news. I'll see about adding a Makefile warning.
OK. Looking forward to the discussion that starts then :-)
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-12-05 13:38 ` Simon Goldschmidt
@ 2018-12-05 13:54 ` Simon Glass
2018-12-05 14:16 ` Simon Goldschmidt
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-12-05 13:54 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Wed, 5 Dec 2018 at 06:38, Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> On Wed, Dec 5, 2018 at 2:21 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Simon,
> >
> > On Sun, 25 Nov 2018 at 23:05, Simon Goldschmidt
> > <simon.k.r.goldschmidt@gmail.com> wrote:
> > >
> > > [I've cut down the CC list a bit due to some gmail warnings]
> > > On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
> > > > <simon.k.r.goldschmidt@gmail.com> wrote:
> > > > >
> > > > > On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> > > > > > >
> > > > > > > On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> > > > > > > > Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> > > > > > > >
> > > > > > > > > On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> > > > > > > > > > On 11/22/2018 01:52 PM, Tom Rini wrote:
> > > > > > > > > > > On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> > > > > > > > > > >
> > > > > > > > > > >> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> > > > > > > > > sjg at chromium.org>:
> > > > > > > > > > >>>
> > > > > > > > > > >>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > > > > > > >>> Remove it.
> > > > > > > > > > >>>
> > > > > > > > > > >>
> > > > > > > > > > >> As the board is still mainted I will NAK it for the moment. Are there
> > > > > > > > > > >> any hints want needs to be done
> > > > > > > > > > >> to port thie board over to new DM stuff?
> > > > > > > > > > >
> > > > > > > > > > > Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> > > > > > > > > > > selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> > > > > > > > > > > needs more work, but this is the board-level work that needs doing.
> > > > > > > > > >
> > > > > > > > > > Wasn't there a possibility to use platform data in board file instead of
> > > > > > > > > > DT ? Or is DT mandatory now , including the libfdt overhead ?
> > > > > > > > >
> > > > > > > > > In short, DT for U-Boot and platform data for SPL is what's recommended,
> > > > > > > > > yes.
> > > > > > > > >
> > > > > > > >
> > > > > > > > This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> > > > > > > > seems a little strange or outdated overall.
> > > > > > > >
> > > > > > > > Would there be some kind of reference architecture or mach to look at
> > > > > > > > what's the suggested/up-to-date way to implement SPL? Also regarding code
> > > > > > > > flow?
> > > > > > >
> > > > > > > So, SPL is where things get, ahem, fuzzy. While I don't want to
> > > > > > > encourage boundless growth in U-Boot proper, we aren't exactly size
> > > > > > > constrained (but rather, functional/logical constrained). But in SPL,
> > > > > > > yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> > > > > > > some smaller) and we can't always shove in a "TPL" before SPL either.
> > > > > > > So in SPL we do make use of platform data instead. While not the
> > > > > > > smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> > > > > > > in this case.
> > > > > >
> > > > > > Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> > > > > > still uses DT, but it gets converted into C structs so saves code
> > > > > > space.
> > > > > >
> > > > > > firefly-rk3288 is a pretty good DM/DT example, including SPL.
> > > > >
> > > > > I've currently got an issue on socfpga gen5 that could be solved best
> > > > > by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
> > > > > problem for CRC calculation). However, it could probably also solve by
> > > > > using platform data (but that doesn't work out of the box, yet). The
> > > > > problem with CONFIG_OF_EMBED is that I think it's OK to enable this
> > > > > for SPL but I don't like enabling it for U-Boot, so:
> > > > >
> > > > > Would it make sense to duplicate the whole "Provider of DTB for OF
> > > > > control" choice so that it can be OF_EMBED for SPL but different for
> > > > > U-Boot? Or does it make more sense to convert socfpga gen5 to use
> > > > > OF_PLATDATA?
> > > >
> > > > We should not be using OF_EMBED in in-tree boards or production code.
> > >
> > > What's the reason for this? I can understand this for U-Boot, and I
> > > can understand that it's at least theoretically a bit cleaner for SPL,
> > > too. But there are some drawbacks when doing this in SPL where code is
> > > not relocated:
> > > - you lose the ability to check total size in linker file (which is
> > > bad for size-constrained platforms: sometimes you notice failure only
> > > when booting)
> >
> > You can add an SPL size check in Makefile.spl if you like.
>
> That might be required, yes.
>
> > > - you get an inconsistent memory layout regarding read/write: the
> > > linker places bss at the end but then, DTB follows as const data
> >
> > This should be handled by the $(SPL-BIN)-pad.bin file (or by binman if
> > you are using that).
>
> I don't understand that. How does the padding help? I have these
> sections (roughly):
> - text: readonly
> - bss: writable
> - DTB: readonly, added as post build step after linking
>
> How does $(SPL-BIN)-pad.bin help?
It covers over the BSS section so that the image ends where the DTB
starts, thus fixing the addressing issue you mentioned. It allows you
to do this:
cat u-boot-spl-nodtb.bin u-boot-spl.dtn >-u-boot-spl.bin
>
> > > - binary size "on disk" grows due to this inconsistent memory layout
> > > (since the flat binary includes the DTB, it needs to include the
> > > zeroed-out bss, too)
> >
> > Right, but this is a few bytes. Why does it matter?
> >
> > > - "spl/u-boot-spl.hex" created by the default Makefiles does not seem
> > > to include the DTB
> >
> > That might just be a bug.
>
> It might, yes. The hex file is currently built from the elf file, so
> there's no DTB in there.
OK. Could be worth a patch.
>
> > >
> > > > Can you please explain the issue a bit more?
> > >
> > > Of course: socfpga gen5 has a feature where the boot rom can jump to
> > > SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
> > > the boot rom can check its consistency by calculating a CRC over one
> > > specified range in SRAM. On first boot, SPL stores its start, length
> > > and CRC value to special registers for the boot rom. Since the
> > > contents of bss changes while SPL is running, bss cannot be included
> > > in this CRC range. (Same goes for the '.data' region, but it's
> > > possible to build SPL without actually using it.)
> >
> > How about calculating that checksum at build time instead? You could
> > use binman to do that.
> >
> > >
> > > So to ensure the DTB is untouched, I have to make sure it has a lower
> > > address than the bss section. Using OF_EMBED does this for me. And I
> > > expect using platform data would work too. Do you have another idea
> > > how to achieve my goal of combining all write-only sections in SPL
> > > into one block?
> >
> > Yes, do it at build time. Or calculate your CRC before you write any
> > BSS variables.
>
> Creating the correct checksum is not the point. I can do that before using bss.
>
> The problem is that on the next boot, this checksum is not valid any
> more because bss might have changed.
Right, but just skip the BSS section when checksumming - i.e. checksum
the code and then the DT but omit the BSS.
>
> > >
> > > Oh, and I currently count 109 defconfig files containing "OF_EMBED",
> > > so I wasn't aware that this should not be used. Maybe these platforms
> > > have similar reasons like I have and would enable OF_EMBED only for
> > > SPL if they could. At least for socfpga_stratix10 that should work.
> >
> > That is very bad news. I'll see about adding a Makefile warning.
>
> OK. Looking forward to the discussion that starts then :-)
Yes...
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-12-05 13:54 ` Simon Glass
@ 2018-12-05 14:16 ` Simon Goldschmidt
2018-12-05 15:55 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Simon Goldschmidt @ 2018-12-05 14:16 UTC (permalink / raw)
To: u-boot
Am 05.12.2018 um 14:54 schrieb Simon Glass:
> Hi Simon,
>
> On Wed, 5 Dec 2018 at 06:38, Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com> wrote:
>>
>> On Wed, Dec 5, 2018 at 2:21 PM Simon Glass <sjg@chromium.org> wrote:
>>>
>>> Hi Simon,
>>>
>>> On Sun, 25 Nov 2018 at 23:05, Simon Goldschmidt
>>> <simon.k.r.goldschmidt@gmail.com> wrote:
>>>>
>>>> [I've cut down the CC list a bit due to some gmail warnings]
>>>> On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
>>>>>
>>>>> Hi Simon,
>>>>>
>>>>> On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
>>>>> <simon.k.r.goldschmidt@gmail.com> wrote:
>>>>>>
>>>>>> On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
>>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
>>>>>>>>
>>>>>>>> On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
>>>>>>>>> Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
>>>>>>>>>
>>>>>>>>>> On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
>>>>>>>>>>> On 11/22/2018 01:52 PM, Tom Rini wrote:
>>>>>>>>>>>> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
>>>>>>>>>> sjg at chromium.org>:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
>>>>>>>>>>>>>> Remove it.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> As the board is still mainted I will NAK it for the moment. Are there
>>>>>>>>>>>>> any hints want needs to be done
>>>>>>>>>>>>> to port thie board over to new DM stuff?
>>>>>>>>>>>>
>>>>>>>>>>>> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
>>>>>>>>>>>> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
>>>>>>>>>>>> needs more work, but this is the board-level work that needs doing.
>>>>>>>>>>>
>>>>>>>>>>> Wasn't there a possibility to use platform data in board file instead of
>>>>>>>>>>> DT ? Or is DT mandatory now , including the libfdt overhead ?
>>>>>>>>>>
>>>>>>>>>> In short, DT for U-Boot and platform data for SPL is what's recommended,
>>>>>>>>>> yes.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
>>>>>>>>> seems a little strange or outdated overall.
>>>>>>>>>
>>>>>>>>> Would there be some kind of reference architecture or mach to look at
>>>>>>>>> what's the suggested/up-to-date way to implement SPL? Also regarding code
>>>>>>>>> flow?
>>>>>>>>
>>>>>>>> So, SPL is where things get, ahem, fuzzy. While I don't want to
>>>>>>>> encourage boundless growth in U-Boot proper, we aren't exactly size
>>>>>>>> constrained (but rather, functional/logical constrained). But in SPL,
>>>>>>>> yes, we have many platforms with 32/64/128 kilobyte hard limits (and
>>>>>>>> some smaller) and we can't always shove in a "TPL" before SPL either.
>>>>>>>> So in SPL we do make use of platform data instead. While not the
>>>>>>>> smallest size constraint, am335x_hs_evm is a reasonable thing to look at
>>>>>>>> in this case.
>>>>>>>
>>>>>>> Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
>>>>>>> still uses DT, but it gets converted into C structs so saves code
>>>>>>> space.
>>>>>>>
>>>>>>> firefly-rk3288 is a pretty good DM/DT example, including SPL.
>>>>>>
>>>>>> I've currently got an issue on socfpga gen5 that could be solved best
>>>>>> by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
>>>>>> problem for CRC calculation). However, it could probably also solve by
>>>>>> using platform data (but that doesn't work out of the box, yet). The
>>>>>> problem with CONFIG_OF_EMBED is that I think it's OK to enable this
>>>>>> for SPL but I don't like enabling it for U-Boot, so:
>>>>>>
>>>>>> Would it make sense to duplicate the whole "Provider of DTB for OF
>>>>>> control" choice so that it can be OF_EMBED for SPL but different for
>>>>>> U-Boot? Or does it make more sense to convert socfpga gen5 to use
>>>>>> OF_PLATDATA?
>>>>>
>>>>> We should not be using OF_EMBED in in-tree boards or production code.
>>>>
>>>> What's the reason for this? I can understand this for U-Boot, and I
>>>> can understand that it's at least theoretically a bit cleaner for SPL,
>>>> too. But there are some drawbacks when doing this in SPL where code is
>>>> not relocated:
>>>> - you lose the ability to check total size in linker file (which is
>>>> bad for size-constrained platforms: sometimes you notice failure only
>>>> when booting)
>>>
>>> You can add an SPL size check in Makefile.spl if you like.
>>
>> That might be required, yes.
>>
>>>> - you get an inconsistent memory layout regarding read/write: the
>>>> linker places bss at the end but then, DTB follows as const data
>>>
>>> This should be handled by the $(SPL-BIN)-pad.bin file (or by binman if
>>> you are using that).
>>
>> I don't understand that. How does the padding help? I have these
>> sections (roughly):
>> - text: readonly
>> - bss: writable
>> - DTB: readonly, added as post build step after linking
>>
>> How does $(SPL-BIN)-pad.bin help?
>
> It covers over the BSS section so that the image ends where the DTB
> starts, thus fixing the addressing issue you mentioned. It allows you
> to do this:
>
> cat u-boot-spl-nodtb.bin u-boot-spl.dtn >-u-boot-spl.bin
>
>>
>>>> - binary size "on disk" grows due to this inconsistent memory layout
>>>> (since the flat binary includes the DTB, it needs to include the
>>>> zeroed-out bss, too)
>>>
>>> Right, but this is a few bytes. Why does it matter?
>>>
>>>> - "spl/u-boot-spl.hex" created by the default Makefiles does not seem
>>>> to include the DTB
>>>
>>> That might just be a bug.
>>
>> It might, yes. The hex file is currently built from the elf file, so
>> there's no DTB in there.
>
> OK. Could be worth a patch.
>
>>
>>>>
>>>>> Can you please explain the issue a bit more?
>>>>
>>>> Of course: socfpga gen5 has a feature where the boot rom can jump to
>>>> SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
>>>> the boot rom can check its consistency by calculating a CRC over one
>>>> specified range in SRAM. On first boot, SPL stores its start, length
>>>> and CRC value to special registers for the boot rom. Since the
>>>> contents of bss changes while SPL is running, bss cannot be included
>>>> in this CRC range. (Same goes for the '.data' region, but it's
>>>> possible to build SPL without actually using it.)
>>>
>>> How about calculating that checksum at build time instead? You could
>>> use binman to do that.
>>>
>>>>
>>>> So to ensure the DTB is untouched, I have to make sure it has a lower
>>>> address than the bss section. Using OF_EMBED does this for me. And I
>>>> expect using platform data would work too. Do you have another idea
>>>> how to achieve my goal of combining all write-only sections in SPL
>>>> into one block?
>>>
>>> Yes, do it at build time. Or calculate your CRC before you write any
>>> BSS variables.
>>
>> Creating the correct checksum is not the point. I can do that before using bss.
>>
>> The problem is that on the next boot, this checksum is not valid any
>> more because bss might have changed.
>
> Right, but just skip the BSS section when checksumming - i.e. checksum
> the code and then the DT but omit the BSS.
Yeah, well, good idea but that's not possible. The boot rom checks this
checksum on warm restart and it can only check the CRC of one block. And
of course I canno change the boot rom.
So the only option I have without using OF_EMBED is to drop the CRC of
the DT, which is not really an option...
Regards,
Simon
>>>> Oh, and I currently count 109 defconfig files containing "OF_EMBED",
>>>> so I wasn't aware that this should not be used. Maybe these platforms
>>>> have similar reasons like I have and would enable OF_EMBED only for
>>>> SPL if they could. At least for socfpga_stratix10 that should work.
>>>
>>> That is very bad news. I'll see about adding a Makefile warning.
>>
>> OK. Looking forward to the discussion that starts then :-)
>
> Yes...
>
> Regards,
> Simon
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-12-05 14:16 ` Simon Goldschmidt
@ 2018-12-05 15:55 ` Simon Glass
2018-12-05 16:11 ` Simon Goldschmidt
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-12-05 15:55 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Wed, 5 Dec 2018 at 07:17, Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> Am 05.12.2018 um 14:54 schrieb Simon Glass:
> > Hi Simon,
> >
> > On Wed, 5 Dec 2018 at 06:38, Simon Goldschmidt
> > <simon.k.r.goldschmidt@gmail.com> wrote:
> >>
> >> On Wed, Dec 5, 2018 at 2:21 PM Simon Glass <sjg@chromium.org> wrote:
> >>>
> >>> Hi Simon,
> >>>
> >>> On Sun, 25 Nov 2018 at 23:05, Simon Goldschmidt
> >>> <simon.k.r.goldschmidt@gmail.com> wrote:
> >>>>
> >>>> [I've cut down the CC list a bit due to some gmail warnings]
> >>>> On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
> >>>>>
> >>>>> Hi Simon,
> >>>>>
> >>>>> On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
> >>>>> <simon.k.r.goldschmidt@gmail.com> wrote:
> >>>>>>
> >>>>>> On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
> >>>>>>>
> >>>>>>> Hi,
> >>>>>>>
> >>>>>>> On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
> >>>>>>>>
> >>>>>>>> On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
> >>>>>>>>> Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
> >>>>>>>>>
> >>>>>>>>>> On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
> >>>>>>>>>>> On 11/22/2018 01:52 PM, Tom Rini wrote:
> >>>>>>>>>>>> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
> >>>>>>>>>>>>
> >>>>>>>>>>>>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
> >>>>>>>>>> sjg at chromium.org>:
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
> >>>>>>>>>>>>>> Remove it.
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> As the board is still mainted I will NAK it for the moment. Are there
> >>>>>>>>>>>>> any hints want needs to be done
> >>>>>>>>>>>>> to port thie board over to new DM stuff?
> >>>>>>>>>>>>
> >>>>>>>>>>>> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
> >>>>>>>>>>>> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
> >>>>>>>>>>>> needs more work, but this is the board-level work that needs doing.
> >>>>>>>>>>>
> >>>>>>>>>>> Wasn't there a possibility to use platform data in board file instead of
> >>>>>>>>>>> DT ? Or is DT mandatory now , including the libfdt overhead ?
> >>>>>>>>>>
> >>>>>>>>>> In short, DT for U-Boot and platform data for SPL is what's recommended,
> >>>>>>>>>> yes.
> >>>>>>>>>>
> >>>>>>>>>
> >>>>>>>>> This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
> >>>>>>>>> seems a little strange or outdated overall.
> >>>>>>>>>
> >>>>>>>>> Would there be some kind of reference architecture or mach to look at
> >>>>>>>>> what's the suggested/up-to-date way to implement SPL? Also regarding code
> >>>>>>>>> flow?
> >>>>>>>>
> >>>>>>>> So, SPL is where things get, ahem, fuzzy. While I don't want to
> >>>>>>>> encourage boundless growth in U-Boot proper, we aren't exactly size
> >>>>>>>> constrained (but rather, functional/logical constrained). But in SPL,
> >>>>>>>> yes, we have many platforms with 32/64/128 kilobyte hard limits (and
> >>>>>>>> some smaller) and we can't always shove in a "TPL" before SPL either.
> >>>>>>>> So in SPL we do make use of platform data instead. While not the
> >>>>>>>> smallest size constraint, am335x_hs_evm is a reasonable thing to look at
> >>>>>>>> in this case.
> >>>>>>>
> >>>>>>> Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
> >>>>>>> still uses DT, but it gets converted into C structs so saves code
> >>>>>>> space.
> >>>>>>>
> >>>>>>> firefly-rk3288 is a pretty good DM/DT example, including SPL.
> >>>>>>
> >>>>>> I've currently got an issue on socfpga gen5 that could be solved best
> >>>>>> by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
> >>>>>> problem for CRC calculation). However, it could probably also solve by
> >>>>>> using platform data (but that doesn't work out of the box, yet). The
> >>>>>> problem with CONFIG_OF_EMBED is that I think it's OK to enable this
> >>>>>> for SPL but I don't like enabling it for U-Boot, so:
> >>>>>>
> >>>>>> Would it make sense to duplicate the whole "Provider of DTB for OF
> >>>>>> control" choice so that it can be OF_EMBED for SPL but different for
> >>>>>> U-Boot? Or does it make more sense to convert socfpga gen5 to use
> >>>>>> OF_PLATDATA?
> >>>>>
> >>>>> We should not be using OF_EMBED in in-tree boards or production code.
> >>>>
> >>>> What's the reason for this? I can understand this for U-Boot, and I
> >>>> can understand that it's at least theoretically a bit cleaner for SPL,
> >>>> too. But there are some drawbacks when doing this in SPL where code is
> >>>> not relocated:
> >>>> - you lose the ability to check total size in linker file (which is
> >>>> bad for size-constrained platforms: sometimes you notice failure only
> >>>> when booting)
> >>>
> >>> You can add an SPL size check in Makefile.spl if you like.
> >>
> >> That might be required, yes.
> >>
> >>>> - you get an inconsistent memory layout regarding read/write: the
> >>>> linker places bss at the end but then, DTB follows as const data
> >>>
> >>> This should be handled by the $(SPL-BIN)-pad.bin file (or by binman if
> >>> you are using that).
> >>
> >> I don't understand that. How does the padding help? I have these
> >> sections (roughly):
> >> - text: readonly
> >> - bss: writable
> >> - DTB: readonly, added as post build step after linking
> >>
> >> How does $(SPL-BIN)-pad.bin help?
> >
> > It covers over the BSS section so that the image ends where the DTB
> > starts, thus fixing the addressing issue you mentioned. It allows you
> > to do this:
> >
> > cat u-boot-spl-nodtb.bin u-boot-spl.dtn >-u-boot-spl.bin
> >
> >>
> >>>> - binary size "on disk" grows due to this inconsistent memory layout
> >>>> (since the flat binary includes the DTB, it needs to include the
> >>>> zeroed-out bss, too)
> >>>
> >>> Right, but this is a few bytes. Why does it matter?
> >>>
> >>>> - "spl/u-boot-spl.hex" created by the default Makefiles does not seem
> >>>> to include the DTB
> >>>
> >>> That might just be a bug.
> >>
> >> It might, yes. The hex file is currently built from the elf file, so
> >> there's no DTB in there.
> >
> > OK. Could be worth a patch.
> >
> >>
> >>>>
> >>>>> Can you please explain the issue a bit more?
> >>>>
> >>>> Of course: socfpga gen5 has a feature where the boot rom can jump to
> >>>> SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
> >>>> the boot rom can check its consistency by calculating a CRC over one
> >>>> specified range in SRAM. On first boot, SPL stores its start, length
> >>>> and CRC value to special registers for the boot rom. Since the
> >>>> contents of bss changes while SPL is running, bss cannot be included
> >>>> in this CRC range. (Same goes for the '.data' region, but it's
> >>>> possible to build SPL without actually using it.)
> >>>
> >>> How about calculating that checksum at build time instead? You could
> >>> use binman to do that.
> >>>
> >>>>
> >>>> So to ensure the DTB is untouched, I have to make sure it has a lower
> >>>> address than the bss section. Using OF_EMBED does this for me. And I
> >>>> expect using platform data would work too. Do you have another idea
> >>>> how to achieve my goal of combining all write-only sections in SPL
> >>>> into one block?
> >>>
> >>> Yes, do it at build time. Or calculate your CRC before you write any
> >>> BSS variables.
> >>
> >> Creating the correct checksum is not the point. I can do that before using bss.
> >>
> >> The problem is that on the next boot, this checksum is not valid any
> >> more because bss might have changed.
> >
> > Right, but just skip the BSS section when checksumming - i.e. checksum
> > the code and then the DT but omit the BSS.
>
> Yeah, well, good idea but that's not possible. The boot rom checks this
> checksum on warm restart and it can only check the CRC of one block. And
> of course I canno change the boot rom.
>
> So the only option I have without using OF_EMBED is to drop the CRC of
> the DT, which is not really an option...
Really it sounds like you want to move the BSS after the DT. We don't
have a way of doing that at present.
But I suppose it would be easy enough to arrange, by putting a
placeholder for the DT in the link script. We just need a variable
which holds the DT size and then can use '. = . + DT_SIZE' to reserve
the space.
Regards,
Simon
>
> Regards,
> Simon
>
> >>>> Oh, and I currently count 109 defconfig files containing "OF_EMBED",
> >>>> so I wasn't aware that this should not be used. Maybe these platforms
> >>>> have similar reasons like I have and would enable OF_EMBED only for
> >>>> SPL if they could. At least for socfpga_stratix10 that should work.
> >>>
> >>> That is very bad news. I'll see about adding a Makefile warning.
> >>
> >> OK. Looking forward to the discussion that starts then :-)
> >
> > Yes...
> >
> > Regards,
> > Simon
> >
>
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-12-05 15:55 ` Simon Glass
@ 2018-12-05 16:11 ` Simon Goldschmidt
0 siblings, 0 replies; 211+ messages in thread
From: Simon Goldschmidt @ 2018-12-05 16:11 UTC (permalink / raw)
To: u-boot
Am 05.12.2018 um 16:55 schrieb Simon Glass:
> Hi Simon,
>
> On Wed, 5 Dec 2018 at 07:17, Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com> wrote:
>>
>> Am 05.12.2018 um 14:54 schrieb Simon Glass:
>>> Hi Simon,
>>>
>>> On Wed, 5 Dec 2018 at 06:38, Simon Goldschmidt
>>> <simon.k.r.goldschmidt@gmail.com> wrote:
>>>>
>>>> On Wed, Dec 5, 2018 at 2:21 PM Simon Glass <sjg@chromium.org> wrote:
>>>>>
>>>>> Hi Simon,
>>>>>
>>>>> On Sun, 25 Nov 2018 at 23:05, Simon Goldschmidt
>>>>> <simon.k.r.goldschmidt@gmail.com> wrote:
>>>>>>
>>>>>> [I've cut down the CC list a bit due to some gmail warnings]
>>>>>> On Mon, Nov 26, 2018 at 4:00 AM Simon Glass <sjg@chromium.org> wrote:
>>>>>>>
>>>>>>> Hi Simon,
>>>>>>>
>>>>>>> On Sun, 25 Nov 2018 at 14:09, Simon Goldschmidt
>>>>>>> <simon.k.r.goldschmidt@gmail.com> wrote:
>>>>>>>>
>>>>>>>> On Thu, Nov 22, 2018 at 9:50 PM Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>
>>>>>>>>> Hi,
>>>>>>>>>
>>>>>>>>> On Thu, 22 Nov 2018 at 10:02, Tom Rini <trini@konsulko.com> wrote:
>>>>>>>>>>
>>>>>>>>>> On Thu, Nov 22, 2018 at 03:44:28PM +0100, Simon Goldschmidt wrote:
>>>>>>>>>>> Am Do., 22. Nov. 2018, 14:44 hat Tom Rini <trini@konsulko.com> geschrieben:
>>>>>>>>>>>
>>>>>>>>>>>> On Thu, Nov 22, 2018 at 02:24:49PM +0100, Marek Vasut wrote:
>>>>>>>>>>>>> On 11/22/2018 01:52 PM, Tom Rini wrote:
>>>>>>>>>>>>>> On Thu, Nov 22, 2018 at 10:25:14AM +0100, Christian Gmeiner wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Am Mo., 19. Nov. 2018 um 16:56 Uhr schrieb Simon Glass <
>>>>>>>>>>>> sjg at chromium.org>:
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> This board has not been converted to CONFIG_DM_BLK by the deadline.
>>>>>>>>>>>>>>>> Remove it.
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> As the board is still mainted I will NAK it for the moment. Are there
>>>>>>>>>>>>>>> any hints want needs to be done
>>>>>>>>>>>>>>> to port thie board over to new DM stuff?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Yes, as a start you need to switch over to using CONFIG_OF_CONTROL and
>>>>>>>>>>>>>> selecting/providing a dtb file. I see ot1200 is using DWC_AHSATA which
>>>>>>>>>>>>>> needs more work, but this is the board-level work that needs doing.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Wasn't there a possibility to use platform data in board file instead of
>>>>>>>>>>>>> DT ? Or is DT mandatory now , including the libfdt overhead ?
>>>>>>>>>>>>
>>>>>>>>>>>> In short, DT for U-Boot and platform data for SPL is what's recommended,
>>>>>>>>>>>> yes.
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> This is a little confusing for me. Socfpga gen5 SPL doesn't do that. And it
>>>>>>>>>>> seems a little strange or outdated overall.
>>>>>>>>>>>
>>>>>>>>>>> Would there be some kind of reference architecture or mach to look at
>>>>>>>>>>> what's the suggested/up-to-date way to implement SPL? Also regarding code
>>>>>>>>>>> flow?
>>>>>>>>>>
>>>>>>>>>> So, SPL is where things get, ahem, fuzzy. While I don't want to
>>>>>>>>>> encourage boundless growth in U-Boot proper, we aren't exactly size
>>>>>>>>>> constrained (but rather, functional/logical constrained). But in SPL,
>>>>>>>>>> yes, we have many platforms with 32/64/128 kilobyte hard limits (and
>>>>>>>>>> some smaller) and we can't always shove in a "TPL" before SPL either.
>>>>>>>>>> So in SPL we do make use of platform data instead. While not the
>>>>>>>>>> smallest size constraint, am335x_hs_evm is a reasonable thing to look at
>>>>>>>>>> in this case.
>>>>>>>>>
>>>>>>>>> Also 'rock' uses CONFIG_OF_PLATDATA which provides a halfway house -
>>>>>>>>> still uses DT, but it gets converted into C structs so saves code
>>>>>>>>> space.
>>>>>>>>>
>>>>>>>>> firefly-rk3288 is a pretty good DM/DT example, including SPL.
>>>>>>>>
>>>>>>>> I've currently got an issue on socfpga gen5 that could be solved best
>>>>>>>> by enabling CONFIG_OF_EMBED (mixing const and non-const sections is a
>>>>>>>> problem for CRC calculation). However, it could probably also solve by
>>>>>>>> using platform data (but that doesn't work out of the box, yet). The
>>>>>>>> problem with CONFIG_OF_EMBED is that I think it's OK to enable this
>>>>>>>> for SPL but I don't like enabling it for U-Boot, so:
>>>>>>>>
>>>>>>>> Would it make sense to duplicate the whole "Provider of DTB for OF
>>>>>>>> control" choice so that it can be OF_EMBED for SPL but different for
>>>>>>>> U-Boot? Or does it make more sense to convert socfpga gen5 to use
>>>>>>>> OF_PLATDATA?
>>>>>>>
>>>>>>> We should not be using OF_EMBED in in-tree boards or production code.
>>>>>>
>>>>>> What's the reason for this? I can understand this for U-Boot, and I
>>>>>> can understand that it's at least theoretically a bit cleaner for SPL,
>>>>>> too. But there are some drawbacks when doing this in SPL where code is
>>>>>> not relocated:
>>>>>> - you lose the ability to check total size in linker file (which is
>>>>>> bad for size-constrained platforms: sometimes you notice failure only
>>>>>> when booting)
>>>>>
>>>>> You can add an SPL size check in Makefile.spl if you like.
>>>>
>>>> That might be required, yes.
>>>>
>>>>>> - you get an inconsistent memory layout regarding read/write: the
>>>>>> linker places bss at the end but then, DTB follows as const data
>>>>>
>>>>> This should be handled by the $(SPL-BIN)-pad.bin file (or by binman if
>>>>> you are using that).
>>>>
>>>> I don't understand that. How does the padding help? I have these
>>>> sections (roughly):
>>>> - text: readonly
>>>> - bss: writable
>>>> - DTB: readonly, added as post build step after linking
>>>>
>>>> How does $(SPL-BIN)-pad.bin help?
>>>
>>> It covers over the BSS section so that the image ends where the DTB
>>> starts, thus fixing the addressing issue you mentioned. It allows you
>>> to do this:
>>>
>>> cat u-boot-spl-nodtb.bin u-boot-spl.dtn >-u-boot-spl.bin
>>>
>>>>
>>>>>> - binary size "on disk" grows due to this inconsistent memory layout
>>>>>> (since the flat binary includes the DTB, it needs to include the
>>>>>> zeroed-out bss, too)
>>>>>
>>>>> Right, but this is a few bytes. Why does it matter?
>>>>>
>>>>>> - "spl/u-boot-spl.hex" created by the default Makefiles does not seem
>>>>>> to include the DTB
>>>>>
>>>>> That might just be a bug.
>>>>
>>>> It might, yes. The hex file is currently built from the elf file, so
>>>> there's no DTB in there.
>>>
>>> OK. Could be worth a patch.
>>>
>>>>
>>>>>>
>>>>>>> Can you please explain the issue a bit more?
>>>>>>
>>>>>> Of course: socfpga gen5 has a feature where the boot rom can jump to
>>>>>> SPL in SRAM on warm boot. To ensure SPL is still valid after a reboot,
>>>>>> the boot rom can check its consistency by calculating a CRC over one
>>>>>> specified range in SRAM. On first boot, SPL stores its start, length
>>>>>> and CRC value to special registers for the boot rom. Since the
>>>>>> contents of bss changes while SPL is running, bss cannot be included
>>>>>> in this CRC range. (Same goes for the '.data' region, but it's
>>>>>> possible to build SPL without actually using it.)
>>>>>
>>>>> How about calculating that checksum at build time instead? You could
>>>>> use binman to do that.
>>>>>
>>>>>>
>>>>>> So to ensure the DTB is untouched, I have to make sure it has a lower
>>>>>> address than the bss section. Using OF_EMBED does this for me. And I
>>>>>> expect using platform data would work too. Do you have another idea
>>>>>> how to achieve my goal of combining all write-only sections in SPL
>>>>>> into one block?
>>>>>
>>>>> Yes, do it at build time. Or calculate your CRC before you write any
>>>>> BSS variables.
>>>>
>>>> Creating the correct checksum is not the point. I can do that before using bss.
>>>>
>>>> The problem is that on the next boot, this checksum is not valid any
>>>> more because bss might have changed.
>>>
>>> Right, but just skip the BSS section when checksumming - i.e. checksum
>>> the code and then the DT but omit the BSS.
>>
>> Yeah, well, good idea but that's not possible. The boot rom checks this
>> checksum on warm restart and it can only check the CRC of one block. And
>> of course I canno change the boot rom.
>>
>> So the only option I have without using OF_EMBED is to drop the CRC of
>> the DT, which is not really an option...
>
> Really it sounds like you want to move the BSS after the DT. We don't
> have a way of doing that at present.
>
> But I suppose it would be easy enough to arrange, by putting a
> placeholder for the DT in the link script. We just need a variable
> which holds the DT size and then can use '. = . + DT_SIZE' to reserve
> the space.
That's a good idea. I might try that as soon as I find the time to
continue working on that boot-crc issue.
Thanks,
Simon
>
> Regards,
> Simon
>
>>
>> Regards,
>> Simon
>>
>>>>>> Oh, and I currently count 109 defconfig files containing "OF_EMBED",
>>>>>> so I wasn't aware that this should not be used. Maybe these platforms
>>>>>> have similar reasons like I have and would enable OF_EMBED only for
>>>>>> SPL if they could. At least for socfpga_stratix10 that should work.
>>>>>
>>>>> That is very bad news. I'll see about adding a Makefile warning.
>>>>
>>>> OK. Looking forward to the discussion that starts then :-)
>>>
>>> Yes...
>>>
>>> Regards,
>>> Simon
>>>
>>
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 66/93] arm: Remove ot1200 board
2018-11-22 9:25 ` Christian Gmeiner
2018-11-22 12:52 ` Tom Rini
@ 2018-11-23 0:33 ` Fabio Estevam
1 sibling, 0 replies; 211+ messages in thread
From: Fabio Estevam @ 2018-11-23 0:33 UTC (permalink / raw)
To: u-boot
Hi Christian,
On Thu, Nov 22, 2018 at 11:00 AM Christian Gmeiner
<christian.gmeiner@gmail.com> wrote:
> As the board is still mainted I will NAK it for the moment. Are there
> any hints want needs to be done
> to port thie board over to new DM stuff?
There are some imx boards that use DM:
git grep CONFIG_OF_CONTROL configs/ | grep mx
You can use them as a reference for converting ot1200.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (65 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 66/93] arm: Remove ot1200 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-21 1:01 ` Ley Foon Tan
2018-11-19 15:53 ` [U-Boot] [PATCH 68/93] arm: Remove am65x_evm_a53 board Simon Glass
` (30 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/altera/stratix10-socdk/MAINTAINERS | 7 -
board/altera/stratix10-socdk/Makefile | 7 -
board/altera/stratix10-socdk/socfpga.c | 7 -
configs/socfpga_stratix10_defconfig | 59 ------
include/configs/socfpga_stratix10_socdk.h | 221 ----------------------
5 files changed, 301 deletions(-)
delete mode 100644 board/altera/stratix10-socdk/MAINTAINERS
delete mode 100644 board/altera/stratix10-socdk/Makefile
delete mode 100644 board/altera/stratix10-socdk/socfpga.c
delete mode 100644 configs/socfpga_stratix10_defconfig
delete mode 100644 include/configs/socfpga_stratix10_socdk.h
diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS
deleted file mode 100644
index 6192bc91746..00000000000
--- a/board/altera/stratix10-socdk/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-SOCFPGA BOARD
-M: Chin-Liang See <chin.liang.see@intel.com>
-M: Dinh Nguyen <dinh.nguyen@intel.com>
-S: Maintained
-F: board/altera/stratix10-socdk/
-F: include/configs/socfpga_stratix10_socdk.h
-F: configs/socfpga_stratix10_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
deleted file mode 100644
index 02a9cadf769..00000000000
--- a/board/altera/stratix10-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
deleted file mode 100644
index 043fc543f1d..00000000000
--- a/board/altera/stratix10-socdk/socfpga.c
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#include <common.h>
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
deleted file mode 100644
index 5f3d733a8bc..00000000000
--- a/configs/socfpga_stratix10_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
-CONFIG_SPL=y
-CONFIG_IDENT_STRING="socfpga_stratix10"
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_BOOTDELAY=5
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
-CONFIG_CMD_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
deleted file mode 100644
index e190b3d9889..00000000000
--- a/include/configs/socfpga_stratix10_socdk.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
-#define __CONFIG_SOCFGPA_STRATIX10_H__
-
-#include <asm/arch/base_addr_s10.h>
-#include <asm/arch/handoff_s10.h>
-
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_LOADADDR 0x2000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_REMAKE_ELF
-/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
-#define CPU_RELEASE_ADDR 0xFFD12210
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
-
-/*
- * U-Boot console configurations
- */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_CBSIZE 2048
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
-
-/*
- * U-Boot run time memory configurations
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
- + CONFIG_SYS_INIT_RAM_SIZE \
- - S10_HANDOFF_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
-
-/*
- * U-Boot environment configurations
- */
-#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/*
- * QSPI support
- */
- #ifdef CONFIG_CADENCE_QSPI
-/* Enable it if you want to use dual-stacked mode */
-#undef CONFIG_SF_DUAL_FLASH
-/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
-
-/* Flash device info */
-#define CONFIG_SF_DEFAULT_SPEED (50000000)
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_3 | SPI_RX_QUAD)
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-
-/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#undef CONFIG_ENV_OFFSET
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET 0x710000
-#define CONFIG_ENV_SIZE (4 * 1024)
-#define CONFIG_ENV_SECT_SIZE (4 * 1024)
-#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
-#endif /* CONFIG_SPL_BUILD */
-
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
-#endif
-
-#endif /* CONFIG_CADENCE_QSPI */
-
-/*
- * Boot arguments passed to the boot command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will override also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "earlycon"
-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
- "run mmcboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "bootfile=Image\0" \
- "fdt_addr=8000000\0" \
- "fdtimage=socfpga_stratix10_socdk.dtb\0" \
- "mmcroot=/dev/mmcblk0p2\0" \
- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${mmcroot} rw rootwait;" \
- "booti ${loadaddr} - ${fdt_addr}\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:1 ${loadaddr} ${bootfile};" \
- "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "linux_qspi_enable=if sf probe; then " \
- "echo Enabling QSPI at Linux DTB...;" \
- "fdt addr ${fdt_addr}; fdt resize;" \
- "fdt set /soc/spi at ff8d2000 status okay;" \
- "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
- " ${qspi_clock}; fi; \0" \
- "scriptaddr=0x02100000\0" \
- "scriptfile=u-boot.scr\0" \
- "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
- "then source ${scriptaddr}; fi\0"
-
-/*
- * Generic Interrupt Controller Definitions
- */
-#define CONFIG_GICV2
-
-/*
- * External memory configurations
- */
-#define PHYS_SDRAM_1 0x0
-#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_MEMTEST_START 0
-#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
-
-/*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
- * Serial / UART configurations
- */
-#define CONFIG_SYS_NS16550_CLK 100000000
-#define CONFIG_SYS_NS16550_MEM32
-
-/*
- * Timer & watchdog configurations
- */
-#define COUNTER_FREQUENCY 400000000
-
-/*
- * SDMMC configurations
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-#endif
-/*
- * Flash configurations
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_DW_ALTDESCRIPTOR
-#endif /* CONFIG_CMD_NET */
-
-/*
- * L4 Watchdog
- */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
-#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
-#ifndef __ASSEMBLY__
-unsigned int cm_get_l4_sys_free_clk_hz(void);
-#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
-#endif
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000
-#endif
-
-/*
- * SPL memory layout
- *
- * On chip RAM
- * 0xFFE0_0000 ...... Start of OCRAM
- * SPL code, rwdata
- * empty space
- * 0xFFEx_xxxx ...... Top of stack (grows down)
- * 0xFFEy_yyyy ...... Global Data
- * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
- * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
- * 0xFFE3_FFFF ...... End of OCRAM
- *
- * SDRAM
- * 0x0000_0000 ...... Start of SDRAM_1
- * unused / empty space for image loading
- * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
- * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
- * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
- *
- */
-#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
-#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
-#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
- - CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
- - CONFIG_SYS_SPL_MALLOC_SIZE)
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000
-
-/* SPL SDMMC boot support */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board
2018-11-19 15:53 ` [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board Simon Glass
@ 2018-11-21 1:01 ` Ley Foon Tan
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Ley Foon Tan @ 2018-11-21 1:01 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 1:27 AM Simon Glass <sjg@chromium.org> wrote:
>
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> board/altera/stratix10-socdk/MAINTAINERS | 7 -
> board/altera/stratix10-socdk/Makefile | 7 -
> board/altera/stratix10-socdk/socfpga.c | 7 -
> configs/socfpga_stratix10_defconfig | 59 ------
> include/configs/socfpga_stratix10_socdk.h | 221 ----------------------
> 5 files changed, 301 deletions(-)
> delete mode 100644 board/altera/stratix10-socdk/MAINTAINERS
> delete mode 100644 board/altera/stratix10-socdk/Makefile
> delete mode 100644 board/altera/stratix10-socdk/socfpga.c
> delete mode 100644 configs/socfpga_stratix10_defconfig
> delete mode 100644 include/configs/socfpga_stratix10_socdk.h
>
NAK
Are you refer to CONFIG_BLK?
After "make socfpga_stratix10_defconfig", CONFIG_BLK and CONIF_DM are enabled.
$ make socfpga_stratix10_defconfig
#
# configuration written to .config
#
$ cat .config | grep CONFIG_BLK
CONFIG_BLK=y
$ cat .config | grep -w CONFIG_DM
CONFIG_DM=y
$ cat .config | grep -w CONFIG_DM_MMC
CONFIG_DM_MMC=y
CONFIG_BLK is not in socfpga_stratix10_defconfig because it is enabled
by default if CONFIG_DM_MMC is enabled.
In drivers/block/Kconfig:
config BLK
bool "Support block devices"
depends on DM
default y if DM_MMC
Regards
Ley Foon
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board
2018-11-21 1:01 ` Ley Foon Tan
@ 2018-11-22 20:50 ` Simon Glass
2018-11-22 23:25 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi,
On Tue, 20 Nov 2018 at 18:01, Ley Foon Tan <lftan.linux@gmail.com> wrote:
>
> On Tue, Nov 20, 2018 at 1:27 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > board/altera/stratix10-socdk/MAINTAINERS | 7 -
> > board/altera/stratix10-socdk/Makefile | 7 -
> > board/altera/stratix10-socdk/socfpga.c | 7 -
> > configs/socfpga_stratix10_defconfig | 59 ------
> > include/configs/socfpga_stratix10_socdk.h | 221 ----------------------
> > 5 files changed, 301 deletions(-)
> > delete mode 100644 board/altera/stratix10-socdk/MAINTAINERS
> > delete mode 100644 board/altera/stratix10-socdk/Makefile
> > delete mode 100644 board/altera/stratix10-socdk/socfpga.c
> > delete mode 100644 configs/socfpga_stratix10_defconfig
> > delete mode 100644 include/configs/socfpga_stratix10_socdk.h
> >
> NAK
>
> Are you refer to CONFIG_BLK?
>
Yes that's right
> After "make socfpga_stratix10_defconfig", CONFIG_BLK and CONIF_DM are enabled.
>
>
> $ make socfpga_stratix10_defconfig
> #
> # configuration written to .config
> #
>
> $ cat .config | grep CONFIG_BLK
> CONFIG_BLK=y
>
> $ cat .config | grep -w CONFIG_DM
> CONFIG_DM=y
>
> $ cat .config | grep -w CONFIG_DM_MMC
> CONFIG_DM_MMC=y
>
>
>
> CONFIG_BLK is not in socfpga_stratix10_defconfig because it is enabled
> by default if CONFIG_DM_MMC is enabled.
>
> In drivers/block/Kconfig:
>
> config BLK
> bool "Support block devices"
> depends on DM
> default y if DM_MMC
>
The problem here is in SPL - I removed the 'default y' for SPL_BLK.
This was because it created a lot more breakages.
However, I think it is best that I put that back, and require boards
that doesn't support CONFIG_BLK in SPL to remove it themselves. It
will require more work now, but in the long run, defaulting to on in
SPL seems better.
So your board will be fine, sorry for the trouble.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board
2018-11-22 20:50 ` Simon Glass
@ 2018-11-22 23:25 ` Tom Rini
2018-11-23 12:04 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-22 23:25 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 01:50:26PM -0700, Simon Glass wrote:
> Hi,
>
> On Tue, 20 Nov 2018 at 18:01, Ley Foon Tan <lftan.linux@gmail.com> wrote:
> >
> > On Tue, Nov 20, 2018 at 1:27 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > Remove it.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > board/altera/stratix10-socdk/MAINTAINERS | 7 -
> > > board/altera/stratix10-socdk/Makefile | 7 -
> > > board/altera/stratix10-socdk/socfpga.c | 7 -
> > > configs/socfpga_stratix10_defconfig | 59 ------
> > > include/configs/socfpga_stratix10_socdk.h | 221 ----------------------
> > > 5 files changed, 301 deletions(-)
> > > delete mode 100644 board/altera/stratix10-socdk/MAINTAINERS
> > > delete mode 100644 board/altera/stratix10-socdk/Makefile
> > > delete mode 100644 board/altera/stratix10-socdk/socfpga.c
> > > delete mode 100644 configs/socfpga_stratix10_defconfig
> > > delete mode 100644 include/configs/socfpga_stratix10_socdk.h
> > >
> > NAK
> >
> > Are you refer to CONFIG_BLK?
> >
>
> Yes that's right
>
> > After "make socfpga_stratix10_defconfig", CONFIG_BLK and CONIF_DM are enabled.
> >
> >
> > $ make socfpga_stratix10_defconfig
> > #
> > # configuration written to .config
> > #
> >
> > $ cat .config | grep CONFIG_BLK
> > CONFIG_BLK=y
> >
> > $ cat .config | grep -w CONFIG_DM
> > CONFIG_DM=y
> >
> > $ cat .config | grep -w CONFIG_DM_MMC
> > CONFIG_DM_MMC=y
> >
> >
> >
> > CONFIG_BLK is not in socfpga_stratix10_defconfig because it is enabled
> > by default if CONFIG_DM_MMC is enabled.
> >
> > In drivers/block/Kconfig:
> >
> > config BLK
> > bool "Support block devices"
> > depends on DM
> > default y if DM_MMC
> >
> The problem here is in SPL - I removed the 'default y' for SPL_BLK.
> This was because it created a lot more breakages.
>
> However, I think it is best that I put that back, and require boards
> that doesn't support CONFIG_BLK in SPL to remove it themselves. It
> will require more work now, but in the long run, defaulting to on in
> SPL seems better.
>
> So your board will be fine, sorry for the trouble.
Note that we're going to need to come up with some sort of compromise
for what we do in SPL as we do have serious size constraints to worry
about.
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board
2018-11-22 23:25 ` Tom Rini
@ 2018-11-23 12:04 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-23 12:04 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Thu, 22 Nov 2018 at 16:25, Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, Nov 22, 2018 at 01:50:26PM -0700, Simon Glass wrote:
> > Hi,
> >
> > On Tue, 20 Nov 2018 at 18:01, Ley Foon Tan <lftan.linux@gmail.com> wrote:
> > >
> > > On Tue, Nov 20, 2018 at 1:27 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > Remove it.
> > > >
> > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > ---
> > > >
> > > > board/altera/stratix10-socdk/MAINTAINERS | 7 -
> > > > board/altera/stratix10-socdk/Makefile | 7 -
> > > > board/altera/stratix10-socdk/socfpga.c | 7 -
> > > > configs/socfpga_stratix10_defconfig | 59 ------
> > > > include/configs/socfpga_stratix10_socdk.h | 221 ----------------------
> > > > 5 files changed, 301 deletions(-)
> > > > delete mode 100644 board/altera/stratix10-socdk/MAINTAINERS
> > > > delete mode 100644 board/altera/stratix10-socdk/Makefile
> > > > delete mode 100644 board/altera/stratix10-socdk/socfpga.c
> > > > delete mode 100644 configs/socfpga_stratix10_defconfig
> > > > delete mode 100644 include/configs/socfpga_stratix10_socdk.h
> > > >
> > > NAK
> > >
> > > Are you refer to CONFIG_BLK?
> > >
> >
> > Yes that's right
> >
> > > After "make socfpga_stratix10_defconfig", CONFIG_BLK and CONIF_DM are enabled.
> > >
> > >
> > > $ make socfpga_stratix10_defconfig
> > > #
> > > # configuration written to .config
> > > #
> > >
> > > $ cat .config | grep CONFIG_BLK
> > > CONFIG_BLK=y
> > >
> > > $ cat .config | grep -w CONFIG_DM
> > > CONFIG_DM=y
> > >
> > > $ cat .config | grep -w CONFIG_DM_MMC
> > > CONFIG_DM_MMC=y
> > >
> > >
> > >
> > > CONFIG_BLK is not in socfpga_stratix10_defconfig because it is enabled
> > > by default if CONFIG_DM_MMC is enabled.
> > >
> > > In drivers/block/Kconfig:
> > >
> > > config BLK
> > > bool "Support block devices"
> > > depends on DM
> > > default y if DM_MMC
> > >
> > The problem here is in SPL - I removed the 'default y' for SPL_BLK.
> > This was because it created a lot more breakages.
> >
> > However, I think it is best that I put that back, and require boards
> > that doesn't support CONFIG_BLK in SPL to remove it themselves. It
> > will require more work now, but in the long run, defaulting to on in
> > SPL seems better.
> >
> > So your board will be fine, sorry for the trouble.
>
> Note that we're going to need to come up with some sort of compromise
> for what we do in SPL as we do have serious size constraints to worry
> about.
Indeed. I think I might need to dig into this a bit. SPL_BLK itself is
about the same size as the legacy code (or was when I do the
conversion) as I was very concerned about size. However if we have
anything using the legacy block stuff, we cannot remove it. This might
need more thought.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 68/93] arm: Remove am65x_evm_a53 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (66 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 67/93] arm: Remove socfpga_stratix10 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 16:58 ` Lokesh Vutla
2018-11-19 15:53 ` [U-Boot] [PATCH 69/93] arm: Remove ap143 board Simon Glass
` (29 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-k3/Kconfig | 1 -
board/ti/am65x/Kconfig | 52 --------
board/ti/am65x/MAINTAINERS | 7 --
board/ti/am65x/Makefile | 8 --
board/ti/am65x/README | 211 --------------------------------
board/ti/am65x/evm.c | 68 ----------
configs/am65x_evm_a53_defconfig | 71 -----------
configs/am65x_evm_r5_defconfig | 87 -------------
include/configs/am65x_evm.h | 75 ------------
9 files changed, 580 deletions(-)
delete mode 100644 board/ti/am65x/Kconfig
delete mode 100644 board/ti/am65x/MAINTAINERS
delete mode 100644 board/ti/am65x/Makefile
delete mode 100644 board/ti/am65x/README
delete mode 100644 board/ti/am65x/evm.c
delete mode 100644 configs/am65x_evm_a53_defconfig
delete mode 100644 configs/am65x_evm_r5_defconfig
delete mode 100644 include/configs/am65x_evm.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index e677a2e01b8..6b55b3c8c1f 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -65,5 +65,4 @@ config SYS_K3_SPL_ATF
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
-source "board/ti/am65x/Kconfig"
endif
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
deleted file mode 100644
index d4b36dbb42f..00000000000
--- a/board/ti/am65x/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
-# Lokesh Vutla <lokeshvutla@ti.com>
-
-choice
- prompt "K3 AM65 based boards"
- optional
-
-config TARGET_AM654_A53_EVM
- bool "TI K3 based AM654 EVM running on A53"
- select ARM64
- select SOC_K3_AM6
-
-config TARGET_AM654_R5_EVM
- bool "TI K3 based AM654 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select SOC_K3_AM6
- select K3_AM654_DDRSS
- imply SYS_K3_SPL_ATF
-
-endchoice
-
-if TARGET_AM654_A53_EVM
-
-config SYS_BOARD
- default "am65x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "am65x_evm"
-
-endif
-
-if TARGET_AM654_R5_EVM
-
-config SYS_BOARD
- default "am65x"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "am65x_evm"
-
-config SPL_LDSCRIPT
- default "arch/arm/mach-omap2/u-boot-spl.lds"
-
-endif
diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS
deleted file mode 100644
index 7c52e7599e0..00000000000
--- a/board/ti/am65x/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-AM65x BOARD
-M: Lokesh Vutla <lokeshvutla@ti.com>
-S: Maintained
-F: board/ti/am65x/
-F: include/configs/am65x_evm.h
-F: configs/am65x_evm_a53_defconfig
-F: configs/am65x_evm_r5_defconfig
diff --git a/board/ti/am65x/Makefile b/board/ti/am65x/Makefile
deleted file mode 100644
index 94dddfcc4a5..00000000000
--- a/board/ti/am65x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
-# Lokesh Vutla <lokeshvutla@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := evm.o
diff --git a/board/ti/am65x/README b/board/ti/am65x/README
deleted file mode 100644
index 0b82bd557b5..00000000000
--- a/board/ti/am65x/README
+++ /dev/null
@@ -1,211 +0,0 @@
-Introduction:
--------------
-The AM65x family of SoCs is the first device family from K3 Multicore
-SoC architecture, targeted for broad market and industrial control with
-aim to meet the complex processing needs of modern embedded products.
-
-The device is built over three domains, each containing specific processing
-cores, voltage domains and peripherals:
-1. Wake-up (WKUP) domain:
- - Device Management and Security Controller (DMSC)
-2. Microcontroller (MCU) domain:
- - Dual Core ARM Cortex-R5F processor
-3. MAIN domain:
- - Quad core 64-bit ARM Cortex-A53
-
-More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
-
-Boot Flow:
-----------
-On AM65x family devices, ROM supports boot only via MCU(R5). This means that
-bootloader has to run on R5 core. In order to meet this constraint, and for
-the following reasons the boot flow is designed as mentioned:
-1. Need to move away from R5 asap, so that we want to start *any*
-firmware on the r5 cores like.... autosar can be loaded to receive CAN
-response and other safety operations to be started. This operation is
-very time critical and is applicable for all automotive use cases.
-2. U-Boot on A53 should start other remotecores for various
-applications. This should happen before running Linux.
-3. In production boot flow, we might not like to use full u-boot,
-instead use Flacon boot flow to reduce boot time.
-
-+------------------------------------------------------------------------+
-| DMSC | R5 | A53 |
-+------------------------------------------------------------------------+
-| +--------+ | | |
-| | Reset | | | |
-| +--------+ | | |
-| : | | |
-| +--------+ | +-----------+ | |
-| | *ROM* |----------|-->| Reset rls | | |
-| +--------+ | +-----------+ | |
-| | | | : | |
-| | ROM | | : | |
-| |services| | : | |
-| | | | +-------------+ | |
-| | | | | *R5 ROM* | | |
-| | | | +-------------+ | |
-| | |<---------|---|Load and auth| | |
-| | | | | tiboot3.bin | | |
-| | | | +-------------+ | |
-| | | | : | |
-| | | | : | |
-| | | | : | |
-| | | | +-------------+ | |
-| | | | | *R5 SPL* | | |
-| | | | +-------------+ | |
-| | | | | Load | | |
-| | | | | sysfw.itb | | |
-| | Start | | +-------------+ | |
-| | System |<---------|---| Start | | |
-| |Firmware| | | SYSFW | | |
-| +--------+ | +-------------+ | |
-| : | | | | |
-| +---------+ | | Load | | |
-| | *SYSFW* | | | system | | |
-| +---------+ | | Config data | | |
-| | |<--------|---| | | |
-| | | | +-------------+ | |
-| | | | | | | |
-| | | | | DDR | | |
-| | | | | config | | |
-| | | | +-------------+ | |
-| | | | | | | |
-| | |<--------|---| Start A53 | | |
-| | | | | and Reset | | |
-| | | | +-------------+ | |
-| | | | | +-----------+ |
-| | |---------|-----------------------|---->| Reset rls | |
-| | | | | +-----------+ |
-| | DMSC | | | : |
-| |Services | | | +-----------+ |
-| | |<--------|-----------------------|---->|*ATF/OPTEE*| |
-| | | | | +-----------+ |
-| | | | | : |
-| | | | | +-----------+ |
-| | |<--------|-----------------------|---->| *A53 SPL* | |
-| | | | | +-----------+ |
-| | | | | | Load | |
-| | | | | | u-boot.img| |
-| | | | | +-----------+ |
-| | | | | : |
-| | | | | +-----------+ |
-| | |<--------|-----------------------|---->| *U-Boot* | |
-| | | | | +-----------+ |
-| | | | | | prompt | |
-| | | | | +-----------+ |
-| +---------+ | | |
-| | | |
-+------------------------------------------------------------------------+
-
-- Here DMSC acts as master and provides all the critical services. R5/A53
-requests DMSC to get these services done as shown in the above diagram.
-
-Sources:
---------
-1. SYSFW:
- Tree: git://git.ti.com/processor-firmware/system-firmware-image-gen.git
- Branch: master
-
-2. ATF:
- Tree: https://github.com/ARM-software/arm-trusted-firmware.git
- Branch: master
-
-3. OPTEE:
- Tree: https://github.com/OP-TEE/optee_os.git
- Branch: master
-
-4. U-Boot:
- Tree: http://git.denx.de/u-boot.git
- Branch: master
-
-Build procedure:
-----------------
-1. SYSFW:
-$ make CROSS_COMPILE=arm-linux-gnueabihf-
-
-2. ATF:
-$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
-
-3. OPTEE:
-$ make PLATFORM=k3-am65x CFG_ARM64_core=y
-
-4. U-Boot:
-
-4.1. R5:
-$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
-$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
-
-4.2. A53:
-$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
-$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53
-
-Target Images
---------------
-Copy the below images to an SD card and boot:
-- sysfw.itb from step 1
-- tiboot3.bin from step 4.1
-- tispl.bin, u-boot.img from 4.2
-
-Image formats:
---------------
-
-- tiboot3.bin:
- +-----------------------+
- | X.509 |
- | Certificate |
- | +-------------------+ |
- | | | |
- | | R5 | |
- | | u-boot-spl.bin | |
- | | | |
- | +-------------------+ |
- | | | |
- | | FIT header | |
- | | +---------------+ | |
- | | | | | |
- | | | DTB 1...N | | |
- | | +---------------+ | |
- | +-------------------+ |
- +-----------------------+
-
-- tispl.bin
- +-----------------------+
- | |
- | FIT HEADER |
- | +-------------------+ |
- | | | |
- | | A53 ATF | |
- | +-------------------+ |
- | | | |
- | | A53 OPTEE | |
- | +-------------------+ |
- | | | |
- | | A53 SPL | |
- | +-------------------+ |
- | | | |
- | | SPL DTB 1...N | |
- | +-------------------+ |
- +-----------------------+
-
-- sysfw.itb
- +-----------------------+
- | |
- | FIT HEADER |
- | +-------------------+ |
- | | | |
- | | sysfw.bin | |
- | +-------------------+ |
- | | | |
- | | board config | |
- | +-------------------+ |
- | | | |
- | | PM config | |
- | +-------------------+ |
- | | | |
- | | RM config | |
- | +-------------------+ |
- | | | |
- | | Secure config | |
- | +-------------------+ |
- +-----------------------+
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
deleted file mode 100644
index 784b2b0191d..00000000000
--- a/board/ti/am65x/evm.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board specific initialization for AM654 EVM
- *
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <spl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
-#ifdef CONFIG_PHYS_64BIT
- gd->ram_size = 0x100000000;
-#else
- gd->ram_size = 0x80000000;
-#endif
-
- return 0;
-}
-
-ulong board_get_usable_ram_top(ulong total_size)
-{
-#ifdef CONFIG_PHYS_64BIT
- /* Limit RAM used by U-Boot to the DDR low region */
- if (gd->ram_top > 0x100000000)
- return 0x100000000;
-#endif
-
- return gd->ram_top;
-}
-
-int dram_init_banksize(void)
-{
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x80000000;
-
-#ifdef CONFIG_PHYS_64BIT
- /* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
- gd->bd->bi_dram[1].size = 0x80000000;
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-#ifdef CONFIG_TARGET_AM654_A53_EVM
- if (!strcmp(name, "k3-am654-base-board"))
- return 0;
-#endif
-
- return -1;
-}
-#endif
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
deleted file mode 100644
index a17cf7cb504..00000000000
--- a/configs/am65x_evm_a53_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SOC_K3_AM6=y
-CONFIG_TARGET_AM654_A53_EVM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_K3=y
-CONFIG_DM_RESET=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
deleted file mode 100644
index 237b9e8229b..00000000000
--- a/configs/am65x_evm_r5_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SOC_K3_AM6=y
-CONFIG_TARGET_AM654_R5_EVM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DM_GPIO=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_K3=y
-CONFIG_DM_RESET=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
deleted file mode 100644
index 484c5ef2fe1..00000000000
--- a/include/configs/am65x_evm.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration header file for K3 AM654 EVM
- *
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
- * Lokesh Vutla <lokeshvutla@ti.com>
- */
-
-#ifndef __CONFIG_AM654_EVM_H
-#define __CONFIG_AM654_EVM_H
-
-#include <linux/sizes.h>
-#include <config_distro_bootcmd.h>
-#include <environment/ti/mmc.h>
-
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
-
-/* SPL Loader Configuration */
-#ifdef CONFIG_TARGET_AM654_A53_EVM
-#define CONFIG_SPL_TEXT_BASE 0x80080000
-#else
-#define CONFIG_SPL_TEXT_BASE 0x41c00000
-#endif
-
-#ifdef CONFIG_SYS_K3_SPL_ATF
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
-#endif
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
- CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
-
-/* U-Boot general configuration */
-#define EXTRA_ENV_AM65X_BOARD_SETTINGS \
- "findfdt=" \
- "if test $board_name = am65x; then " \
- "setenv name_fdt k3-am654-base-board.dtb; " \
- "else if test $name_fdt = undefined; then " \
- "echo WARNING: Could not determine device tree to use;"\
- "fi; fi; " \
- "setenv fdtfile ${name_fdt}\0" \
- "loadaddr=0x80080000\0" \
- "fdtaddr=0x82000000\0" \
- "name_kern=Image\0" \
- "console=ttyS2,115200n8\0" \
- "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
- "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
-
-/* U-Boot MMC-specific configuration */
-#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \
- "boot=mmc\0" \
- "mmcdev=1\0" \
- "bootpart=1:2\0" \
- "bootdir=/boot\0" \
- "rd_spec=-\0" \
- "init_mmc=run args_all args_mmc\0" \
- "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
- "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
- "${bootdir}/${name_kern}\0"
-
-/* Incorporate settings into the U-Boot environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_MMC_TI_ARGS \
- EXTRA_ENV_AM65X_BOARD_SETTINGS \
- EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
-
-/* Now for the remaining common defines */
-#include <configs/ti_armv7_common.h>
-
-#endif /* __CONFIG_AM654_EVM_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 68/93] arm: Remove am65x_evm_a53 board
2018-11-19 15:53 ` [U-Boot] [PATCH 68/93] arm: Remove am65x_evm_a53 board Simon Glass
@ 2018-11-19 16:58 ` Lokesh Vutla
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Lokesh Vutla @ 2018-11-19 16:58 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 11/19/2018 9:23 PM, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Not sure if this is by mistake, but I see CONFIG_BLK is enabled in both
the configs. Am I missing something?
➜ u-boot git:(master) make am65x_evm_r5_defconfig;cat .config | grep BLK
#
# configuration written to .config
#
CONFIG_BLK=y
CONFIG_SPL_BLK=y
➜ u-boot git:(master) make am65x_evm_a53_defconfig;cat .config | grep BLK
#
# configuration written to .config
#
CONFIG_BLK=y
CONFIG_SPL_BLK=y
Thanks and regards,
Lokesh
> ---
>
> arch/arm/mach-k3/Kconfig | 1 -
> board/ti/am65x/Kconfig | 52 --------
> board/ti/am65x/MAINTAINERS | 7 --
> board/ti/am65x/Makefile | 8 --
> board/ti/am65x/README | 211 --------------------------------
> board/ti/am65x/evm.c | 68 ----------
> configs/am65x_evm_a53_defconfig | 71 -----------
> configs/am65x_evm_r5_defconfig | 87 -------------
> include/configs/am65x_evm.h | 75 ------------
> 9 files changed, 580 deletions(-)
> delete mode 100644 board/ti/am65x/Kconfig
> delete mode 100644 board/ti/am65x/MAINTAINERS
> delete mode 100644 board/ti/am65x/Makefile
> delete mode 100644 board/ti/am65x/README
> delete mode 100644 board/ti/am65x/evm.c
> delete mode 100644 configs/am65x_evm_a53_defconfig
> delete mode 100644 configs/am65x_evm_r5_defconfig
> delete mode 100644 include/configs/am65x_evm.h
>
> diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
> index e677a2e01b8..6b55b3c8c1f 100644
> --- a/arch/arm/mach-k3/Kconfig
> +++ b/arch/arm/mach-k3/Kconfig
> @@ -65,5 +65,4 @@ config SYS_K3_SPL_ATF
> Enabling this will try to start Cortex-A (typically with ATF)
> after SPL from R5.
>
> -source "board/ti/am65x/Kconfig"
> endif
> diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
> deleted file mode 100644
> index d4b36dbb42f..00000000000
> --- a/board/ti/am65x/Kconfig
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
> -# Lokesh Vutla <lokeshvutla@ti.com>
> -
> -choice
> - prompt "K3 AM65 based boards"
> - optional
> -
> -config TARGET_AM654_A53_EVM
> - bool "TI K3 based AM654 EVM running on A53"
> - select ARM64
> - select SOC_K3_AM6
> -
> -config TARGET_AM654_R5_EVM
> - bool "TI K3 based AM654 EVM running on R5"
> - select CPU_V7R
> - select SYS_THUMB_BUILD
> - select SOC_K3_AM6
> - select K3_AM654_DDRSS
> - imply SYS_K3_SPL_ATF
> -
> -endchoice
> -
> -if TARGET_AM654_A53_EVM
> -
> -config SYS_BOARD
> - default "am65x"
> -
> -config SYS_VENDOR
> - default "ti"
> -
> -config SYS_CONFIG_NAME
> - default "am65x_evm"
> -
> -endif
> -
> -if TARGET_AM654_R5_EVM
> -
> -config SYS_BOARD
> - default "am65x"
> -
> -config SYS_VENDOR
> - default "ti"
> -
> -config SYS_CONFIG_NAME
> - default "am65x_evm"
> -
> -config SPL_LDSCRIPT
> - default "arch/arm/mach-omap2/u-boot-spl.lds"
> -
> -endif
> diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS
> deleted file mode 100644
> index 7c52e7599e0..00000000000
> --- a/board/ti/am65x/MAINTAINERS
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -AM65x BOARD
> -M: Lokesh Vutla <lokeshvutla@ti.com>
> -S: Maintained
> -F: board/ti/am65x/
> -F: include/configs/am65x_evm.h
> -F: configs/am65x_evm_a53_defconfig
> -F: configs/am65x_evm_r5_defconfig
> diff --git a/board/ti/am65x/Makefile b/board/ti/am65x/Makefile
> deleted file mode 100644
> index 94dddfcc4a5..00000000000
> --- a/board/ti/am65x/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -#
> -# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
> -# Lokesh Vutla <lokeshvutla@ti.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := evm.o
> diff --git a/board/ti/am65x/README b/board/ti/am65x/README
> deleted file mode 100644
> index 0b82bd557b5..00000000000
> --- a/board/ti/am65x/README
> +++ /dev/null
> @@ -1,211 +0,0 @@
> -Introduction:
> --------------
> -The AM65x family of SoCs is the first device family from K3 Multicore
> -SoC architecture, targeted for broad market and industrial control with
> -aim to meet the complex processing needs of modern embedded products.
> -
> -The device is built over three domains, each containing specific processing
> -cores, voltage domains and peripherals:
> -1. Wake-up (WKUP) domain:
> - - Device Management and Security Controller (DMSC)
> -2. Microcontroller (MCU) domain:
> - - Dual Core ARM Cortex-R5F processor
> -3. MAIN domain:
> - - Quad core 64-bit ARM Cortex-A53
> -
> -More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
> -
> -Boot Flow:
> -----------
> -On AM65x family devices, ROM supports boot only via MCU(R5). This means that
> -bootloader has to run on R5 core. In order to meet this constraint, and for
> -the following reasons the boot flow is designed as mentioned:
> -1. Need to move away from R5 asap, so that we want to start *any*
> -firmware on the r5 cores like.... autosar can be loaded to receive CAN
> -response and other safety operations to be started. This operation is
> -very time critical and is applicable for all automotive use cases.
> -2. U-Boot on A53 should start other remotecores for various
> -applications. This should happen before running Linux.
> -3. In production boot flow, we might not like to use full u-boot,
> -instead use Flacon boot flow to reduce boot time.
> -
> -+------------------------------------------------------------------------+
> -| DMSC | R5 | A53 |
> -+------------------------------------------------------------------------+
> -| +--------+ | | |
> -| | Reset | | | |
> -| +--------+ | | |
> -| : | | |
> -| +--------+ | +-----------+ | |
> -| | *ROM* |----------|-->| Reset rls | | |
> -| +--------+ | +-----------+ | |
> -| | | | : | |
> -| | ROM | | : | |
> -| |services| | : | |
> -| | | | +-------------+ | |
> -| | | | | *R5 ROM* | | |
> -| | | | +-------------+ | |
> -| | |<---------|---|Load and auth| | |
> -| | | | | tiboot3.bin | | |
> -| | | | +-------------+ | |
> -| | | | : | |
> -| | | | : | |
> -| | | | : | |
> -| | | | +-------------+ | |
> -| | | | | *R5 SPL* | | |
> -| | | | +-------------+ | |
> -| | | | | Load | | |
> -| | | | | sysfw.itb | | |
> -| | Start | | +-------------+ | |
> -| | System |<---------|---| Start | | |
> -| |Firmware| | | SYSFW | | |
> -| +--------+ | +-------------+ | |
> -| : | | | | |
> -| +---------+ | | Load | | |
> -| | *SYSFW* | | | system | | |
> -| +---------+ | | Config data | | |
> -| | |<--------|---| | | |
> -| | | | +-------------+ | |
> -| | | | | | | |
> -| | | | | DDR | | |
> -| | | | | config | | |
> -| | | | +-------------+ | |
> -| | | | | | | |
> -| | |<--------|---| Start A53 | | |
> -| | | | | and Reset | | |
> -| | | | +-------------+ | |
> -| | | | | +-----------+ |
> -| | |---------|-----------------------|---->| Reset rls | |
> -| | | | | +-----------+ |
> -| | DMSC | | | : |
> -| |Services | | | +-----------+ |
> -| | |<--------|-----------------------|---->|*ATF/OPTEE*| |
> -| | | | | +-----------+ |
> -| | | | | : |
> -| | | | | +-----------+ |
> -| | |<--------|-----------------------|---->| *A53 SPL* | |
> -| | | | | +-----------+ |
> -| | | | | | Load | |
> -| | | | | | u-boot.img| |
> -| | | | | +-----------+ |
> -| | | | | : |
> -| | | | | +-----------+ |
> -| | |<--------|-----------------------|---->| *U-Boot* | |
> -| | | | | +-----------+ |
> -| | | | | | prompt | |
> -| | | | | +-----------+ |
> -| +---------+ | | |
> -| | | |
> -+------------------------------------------------------------------------+
> -
> -- Here DMSC acts as master and provides all the critical services. R5/A53
> -requests DMSC to get these services done as shown in the above diagram.
> -
> -Sources:
> ---------
> -1. SYSFW:
> - Tree: git://git.ti.com/processor-firmware/system-firmware-image-gen.git
> - Branch: master
> -
> -2. ATF:
> - Tree: https://github.com/ARM-software/arm-trusted-firmware.git
> - Branch: master
> -
> -3. OPTEE:
> - Tree: https://github.com/OP-TEE/optee_os.git
> - Branch: master
> -
> -4. U-Boot:
> - Tree: http://git.denx.de/u-boot.git
> - Branch: master
> -
> -Build procedure:
> -----------------
> -1. SYSFW:
> -$ make CROSS_COMPILE=arm-linux-gnueabihf-
> -
> -2. ATF:
> -$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
> -
> -3. OPTEE:
> -$ make PLATFORM=k3-am65x CFG_ARM64_core=y
> -
> -4. U-Boot:
> -
> -4.1. R5:
> -$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
> -$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
> -
> -4.2. A53:
> -$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
> -$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53
> -
> -Target Images
> ---------------
> -Copy the below images to an SD card and boot:
> -- sysfw.itb from step 1
> -- tiboot3.bin from step 4.1
> -- tispl.bin, u-boot.img from 4.2
> -
> -Image formats:
> ---------------
> -
> -- tiboot3.bin:
> - +-----------------------+
> - | X.509 |
> - | Certificate |
> - | +-------------------+ |
> - | | | |
> - | | R5 | |
> - | | u-boot-spl.bin | |
> - | | | |
> - | +-------------------+ |
> - | | | |
> - | | FIT header | |
> - | | +---------------+ | |
> - | | | | | |
> - | | | DTB 1...N | | |
> - | | +---------------+ | |
> - | +-------------------+ |
> - +-----------------------+
> -
> -- tispl.bin
> - +-----------------------+
> - | |
> - | FIT HEADER |
> - | +-------------------+ |
> - | | | |
> - | | A53 ATF | |
> - | +-------------------+ |
> - | | | |
> - | | A53 OPTEE | |
> - | +-------------------+ |
> - | | | |
> - | | A53 SPL | |
> - | +-------------------+ |
> - | | | |
> - | | SPL DTB 1...N | |
> - | +-------------------+ |
> - +-----------------------+
> -
> -- sysfw.itb
> - +-----------------------+
> - | |
> - | FIT HEADER |
> - | +-------------------+ |
> - | | | |
> - | | sysfw.bin | |
> - | +-------------------+ |
> - | | | |
> - | | board config | |
> - | +-------------------+ |
> - | | | |
> - | | PM config | |
> - | +-------------------+ |
> - | | | |
> - | | RM config | |
> - | +-------------------+ |
> - | | | |
> - | | Secure config | |
> - | +-------------------+ |
> - +-----------------------+
> diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
> deleted file mode 100644
> index 784b2b0191d..00000000000
> --- a/board/ti/am65x/evm.c
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Board specific initialization for AM654 EVM
> - *
> - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
> - * Lokesh Vutla <lokeshvutla@ti.com>
> - *
> - */
> -
> -#include <common.h>
> -#include <asm/io.h>
> -#include <spl.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_init(void)
> -{
> - return 0;
> -}
> -
> -int dram_init(void)
> -{
> -#ifdef CONFIG_PHYS_64BIT
> - gd->ram_size = 0x100000000;
> -#else
> - gd->ram_size = 0x80000000;
> -#endif
> -
> - return 0;
> -}
> -
> -ulong board_get_usable_ram_top(ulong total_size)
> -{
> -#ifdef CONFIG_PHYS_64BIT
> - /* Limit RAM used by U-Boot to the DDR low region */
> - if (gd->ram_top > 0x100000000)
> - return 0x100000000;
> -#endif
> -
> - return gd->ram_top;
> -}
> -
> -int dram_init_banksize(void)
> -{
> - /* Bank 0 declares the memory available in the DDR low region */
> - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> - gd->bd->bi_dram[0].size = 0x80000000;
> -
> -#ifdef CONFIG_PHYS_64BIT
> - /* Bank 1 declares the memory available in the DDR high region */
> - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
> - gd->bd->bi_dram[1].size = 0x80000000;
> -#endif
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_SPL_LOAD_FIT
> -int board_fit_config_name_match(const char *name)
> -{
> -#ifdef CONFIG_TARGET_AM654_A53_EVM
> - if (!strcmp(name, "k3-am654-base-board"))
> - return 0;
> -#endif
> -
> - return -1;
> -}
> -#endif
> diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
> deleted file mode 100644
> index a17cf7cb504..00000000000
> --- a/configs/am65x_evm_a53_defconfig
> +++ /dev/null
> @@ -1,71 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_K3=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_SOC_K3_AM6=y
> -CONFIG_TARGET_AM654_A53_EVM=y
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL_STACK_R_ADDR=0x82000000
> -CONFIG_SPL_FAT_SUPPORT=y
> -CONFIG_SPL_LIBDISK_SUPPORT=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_NR_DRAM_BANKS=2
> -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> -CONFIG_SPL_LOAD_FIT=y
> -CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
> -# CONFIG_DISPLAY_CPUINFO is not set
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> -CONFIG_SPL_SEPARATE_BSS=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_DM_MAILBOX=y
> -CONFIG_SPL_DM_RESET=y
> -CONFIG_SPL_POWER_DOMAIN=y
> -CONFIG_SPL_REMOTEPROC=y
> -CONFIG_SPL_YMODEM_SUPPORT=y
> -CONFIG_CMD_ASKENV=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_REMOTEPROC=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_TIME=y
> -# CONFIG_ISO_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -CONFIG_OF_CONTROL=y
> -CONFIG_SPL_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
> -CONFIG_SPL_MULTI_DTB_FIT=y
> -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
> -CONFIG_ENV_IS_IN_FAT=y
> -CONFIG_ENV_FAT_INTERFACE="mmc"
> -CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
> -CONFIG_DM=y
> -CONFIG_SPL_DM=y
> -CONFIG_SPL_DM_SEQ_ALIAS=y
> -CONFIG_CLK=y
> -CONFIG_SPL_CLK=y
> -CONFIG_CLK_TI_SCI=y
> -CONFIG_TI_SCI_PROTOCOL=y
> -CONFIG_DM_MAILBOX=y
> -CONFIG_K3_SEC_PROXY=y
> -CONFIG_MISC=y
> -CONFIG_DM_MMC=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_K3_ARASAN=y
> -CONFIG_PINCTRL=y
> -# CONFIG_PINCTRL_GENERIC is not set
> -CONFIG_SPL_PINCTRL=y
> -# CONFIG_SPL_PINCTRL_GENERIC is not set
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_POWER_DOMAIN=y
> -CONFIG_TI_SCI_POWER_DOMAIN=y
> -CONFIG_K3_SYSTEM_CONTROLLER=y
> -CONFIG_REMOTEPROC_K3=y
> -CONFIG_DM_RESET=y
> -CONFIG_RESET_TI_SCI=y
> -CONFIG_DM_SERIAL=y
> -CONFIG_SYSRESET=y
> -CONFIG_SYSRESET_TI_SCI=y
> diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
> deleted file mode 100644
> index 237b9e8229b..00000000000
> --- a/configs/am65x_evm_r5_defconfig
> +++ /dev/null
> @@ -1,87 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_K3=y
> -CONFIG_SPL_GPIO_SUPPORT=y
> -CONFIG_SPL_LIBCOMMON_SUPPORT=y
> -CONFIG_SPL_LIBGENERIC_SUPPORT=y
> -CONFIG_SYS_MALLOC_F_LEN=0x2000
> -CONFIG_SOC_K3_AM6=y
> -CONFIG_TARGET_AM654_R5_EVM=y
> -CONFIG_SPL_MMC_SUPPORT=y
> -CONFIG_SPL_SERIAL_SUPPORT=y
> -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> -CONFIG_SPL_STACK_R_ADDR=0x82000000
> -CONFIG_SPL_FAT_SUPPORT=y
> -CONFIG_SPL_LIBDISK_SUPPORT=y
> -CONFIG_NR_DRAM_BANKS=2
> -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> -CONFIG_SPL_LOAD_FIT=y
> -CONFIG_USE_BOOTCOMMAND=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> -CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> -CONFIG_SPL_STACK_R=y
> -CONFIG_SPL_SEPARATE_BSS=y
> -CONFIG_SPL_I2C_SUPPORT=y
> -CONFIG_SPL_DM_MAILBOX=y
> -CONFIG_SPL_DM_RESET=y
> -CONFIG_SPL_POWER_SUPPORT=y
> -CONFIG_SPL_POWER_DOMAIN=y
> -CONFIG_SPL_RAM_SUPPORT=y
> -CONFIG_SPL_RAM_DEVICE=y
> -CONFIG_SPL_REMOTEPROC=y
> -CONFIG_SPL_YMODEM_SUPPORT=y
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_BOOTZ=y
> -CONFIG_CMD_ASKENV=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_REMOTEPROC=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_TIME=y
> -CONFIG_CMD_FAT=y
> -CONFIG_OF_CONTROL=y
> -CONFIG_SPL_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
> -CONFIG_SPL_MULTI_DTB_FIT=y
> -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
> -CONFIG_ENV_IS_IN_FAT=y
> -CONFIG_ENV_FAT_INTERFACE="mmc"
> -CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
> -CONFIG_DM=y
> -CONFIG_SPL_DM=y
> -CONFIG_SPL_DM_SEQ_ALIAS=y
> -CONFIG_SPL_OF_TRANSLATE=y
> -CONFIG_CLK=y
> -CONFIG_SPL_CLK=y
> -CONFIG_CLK_TI_SCI=y
> -CONFIG_TI_SCI_PROTOCOL=y
> -CONFIG_DM_GPIO=y
> -CONFIG_DA8XX_GPIO=y
> -CONFIG_DM_MAILBOX=y
> -CONFIG_K3_SEC_PROXY=y
> -CONFIG_MISC=y
> -CONFIG_DM_MMC=y
> -CONFIG_MMC_SDHCI=y
> -CONFIG_MMC_SDHCI_K3_ARASAN=y
> -CONFIG_PINCTRL=y
> -# CONFIG_PINCTRL_GENERIC is not set
> -CONFIG_SPL_PINCTRL=y
> -# CONFIG_SPL_PINCTRL_GENERIC is not set
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_POWER_DOMAIN=y
> -CONFIG_TI_SCI_POWER_DOMAIN=y
> -CONFIG_DM_REGULATOR=y
> -CONFIG_SPL_DM_REGULATOR=y
> -CONFIG_DM_REGULATOR_GPIO=y
> -CONFIG_SPL_DM_REGULATOR_GPIO=y
> -CONFIG_RAM=y
> -CONFIG_SPL_RAM=y
> -CONFIG_K3_SYSTEM_CONTROLLER=y
> -CONFIG_REMOTEPROC_K3=y
> -CONFIG_DM_RESET=y
> -CONFIG_RESET_TI_SCI=y
> -CONFIG_DM_SERIAL=y
> -CONFIG_SYSRESET=y
> -CONFIG_SYSRESET_TI_SCI=y
> -CONFIG_TIMER=y
> -CONFIG_SPL_TIMER=y
> -CONFIG_OMAP_TIMER=y
> diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
> deleted file mode 100644
> index 484c5ef2fe1..00000000000
> --- a/include/configs/am65x_evm.h
> +++ /dev/null
> @@ -1,75 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Configuration header file for K3 AM654 EVM
> - *
> - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
> - * Lokesh Vutla <lokeshvutla@ti.com>
> - */
> -
> -#ifndef __CONFIG_AM654_EVM_H
> -#define __CONFIG_AM654_EVM_H
> -
> -#include <linux/sizes.h>
> -#include <config_distro_bootcmd.h>
> -#include <environment/ti/mmc.h>
> -
> -#define CONFIG_ENV_SIZE (128 << 10)
> -
> -/* DDR Configuration */
> -#define CONFIG_SYS_SDRAM_BASE1 0x880000000
> -
> -/* SPL Loader Configuration */
> -#ifdef CONFIG_TARGET_AM654_A53_EVM
> -#define CONFIG_SPL_TEXT_BASE 0x80080000
> -#else
> -#define CONFIG_SPL_TEXT_BASE 0x41c00000
> -#endif
> -
> -#ifdef CONFIG_SYS_K3_SPL_ATF
> -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
> -#endif
> -
> -#define CONFIG_SKIP_LOWLEVEL_INIT
> -
> -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
> -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
> - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
> -
> -/* U-Boot general configuration */
> -#define EXTRA_ENV_AM65X_BOARD_SETTINGS \
> - "findfdt=" \
> - "if test $board_name = am65x; then " \
> - "setenv name_fdt k3-am654-base-board.dtb; " \
> - "else if test $name_fdt = undefined; then " \
> - "echo WARNING: Could not determine device tree to use;"\
> - "fi; fi; " \
> - "setenv fdtfile ${name_fdt}\0" \
> - "loadaddr=0x80080000\0" \
> - "fdtaddr=0x82000000\0" \
> - "name_kern=Image\0" \
> - "console=ttyS2,115200n8\0" \
> - "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
> - "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
> -
> -/* U-Boot MMC-specific configuration */
> -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \
> - "boot=mmc\0" \
> - "mmcdev=1\0" \
> - "bootpart=1:2\0" \
> - "bootdir=/boot\0" \
> - "rd_spec=-\0" \
> - "init_mmc=run args_all args_mmc\0" \
> - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
> - "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
> - "${bootdir}/${name_kern}\0"
> -
> -/* Incorporate settings into the U-Boot environment */
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - DEFAULT_MMC_TI_ARGS \
> - EXTRA_ENV_AM65X_BOARD_SETTINGS \
> - EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
> -
> -/* Now for the remaining common defines */
> -#include <configs/ti_armv7_common.h>
> -
> -#endif /* __CONFIG_AM654_EVM_H */
>
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 68/93] arm: Remove am65x_evm_a53 board
2018-11-19 16:58 ` Lokesh Vutla
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Lokesh,
On Mon, 19 Nov 2018 at 09:58, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>
> Hi Simon,
>
> On 11/19/2018 9:23 PM, Simon Glass wrote:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
>
> Not sure if this is by mistake, but I see CONFIG_BLK is enabled in both
> the configs. Am I missing something?
>
> ➜ u-boot git:(master) make am65x_evm_r5_defconfig;cat .config | grep BLK
> #
> # configuration written to .config
> #
> CONFIG_BLK=y
> CONFIG_SPL_BLK=y
>
> ➜ u-boot git:(master) make am65x_evm_a53_defconfig;cat .config | grep BLK
> #
> # configuration written to .config
> #
> CONFIG_BLK=y
> CONFIG_SPL_BLK=y
>
This was the result of my removing the default CONFIG_SPL_BLK=y in the
Kconfig, since it produced a smaller list of broken boards. But having
thought about it, it is not the right thing to do.
So your board should be fine. Sorry for the trouble.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 69/93] arm: Remove ap143 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (67 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 68/93] arm: Remove am65x_evm_a53 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 70/93] arm: Remove ap121 board Simon Glass
` (28 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/mips/mach-ath79/Kconfig | 1 -
board/qca/ap143/Kconfig | 27 ----------------
board/qca/ap143/MAINTAINERS | 6 ----
board/qca/ap143/Makefile | 3 --
board/qca/ap143/ap143.c | 62 ------------------------------------
configs/ap143_defconfig | 55 --------------------------------
include/configs/ap143.h | 50 -----------------------------
7 files changed, 204 deletions(-)
delete mode 100644 board/qca/ap143/Kconfig
delete mode 100644 board/qca/ap143/MAINTAINERS
delete mode 100644 board/qca/ap143/Makefile
delete mode 100644 board/qca/ap143/ap143.c
delete mode 100644 configs/ap143_defconfig
delete mode 100644 include/configs/ap143.h
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index bc86f591df8..1553aabcea7 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -51,7 +51,6 @@ config BOARD_TPLINK_WDR4300
endchoice
source "board/qca/ap121/Kconfig"
-source "board/qca/ap143/Kconfig"
source "board/tplink/wdr4300/Kconfig"
endmenu
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
deleted file mode 100644
index 74c632a03e7..00000000000
--- a/board/qca/ap143/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if TARGET_AP143
-
-config SYS_VENDOR
- default "qca"
-
-config SYS_BOARD
- default "ap143"
-
-config SYS_CONFIG_NAME
- default "ap143"
-
-config SYS_TEXT_BASE
- default 0x9f000000
-
-config SYS_DCACHE_SIZE
- default 32768
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 65536
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-endif
diff --git a/board/qca/ap143/MAINTAINERS b/board/qca/ap143/MAINTAINERS
deleted file mode 100644
index 11cb14fc74d..00000000000
--- a/board/qca/ap143/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-AP143 BOARD
-M: Wills Wang <wills.wang@live.com>
-S: Maintained
-F: board/qca/ap143/
-F: include/configs/ap143.h
-F: configs/ap143_defconfig
diff --git a/board/qca/ap143/Makefile b/board/qca/ap143/Makefile
deleted file mode 100644
index bf9fd83af9b..00000000000
--- a/board/qca/ap143/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y = ap143.o
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
deleted file mode 100644
index 8ee26ababaa..00000000000
--- a/board/qca/ap143/ap143.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/addrspace.h>
-#include <asm/types.h>
-#include <mach/ar71xx_regs.h>
-#include <mach/ddr.h>
-#include <mach/ath79.h>
-#include <debug_uart.h>
-
-#ifdef CONFIG_DEBUG_UART_BOARD_INIT
-void board_debug_uart_init(void)
-{
- void __iomem *regs;
- u32 val;
-
- regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
- MAP_NOCACHE);
-
- /*
- * GPIO9 as input, GPIO10 as output
- */
- val = readl(regs + AR71XX_GPIO_REG_OE);
- val |= QCA953X_GPIO(9);
- val &= ~QCA953X_GPIO(10);
- writel(val, regs + AR71XX_GPIO_REG_OE);
-
- /*
- * Enable GPIO10 as UART0_SOUT
- */
- val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
- val &= ~QCA953X_GPIO_MUX_MASK(16);
- val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
- writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
-
- /*
- * Enable GPIO9 as UART0_SIN
- */
- val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
- val &= ~QCA953X_GPIO_MUX_MASK(8);
- val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
- writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
-
- /*
- * Enable GPIO10 output
- */
- val = readl(regs + AR71XX_GPIO_REG_OUT);
- val |= QCA953X_GPIO(10);
- writel(val, regs + AR71XX_GPIO_REG_OUT);
-}
-#endif
-
-int board_early_init_f(void)
-{
- ddr_init();
- ath79_eth_reset();
- return 0;
-}
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
deleted file mode 100644
index 83eb583b563..00000000000
--- a/configs/ap143_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x9F000000
-CONFIG_SYS_MALLOC_F_LEN=0x800
-CONFIG_DEBUG_UART_BOARD_INIT=y
-CONFIG_DEBUG_UART_BASE=0xb8020000
-CONFIG_DEBUG_UART_CLOCK=25000000
-CONFIG_ARCH_ATH79=y
-CONFIG_TARGET_AP143=y
-CONFIG_DEBUG_UART=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
-CONFIG_DISPLAY_CPUINFO=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_PROMPT="ap143 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1472k(uImage),64k(ART)"
-# CONFIG_ISO_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="ap143"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-# CONFIG_NET is not set
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_DATAFLASH=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PINCTRL=y
-CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_ATH79_SPI=y
-CONFIG_LZMA=y
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
deleted file mode 100644
index 4dbca917e39..00000000000
--- a/include/configs/ap143.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_MHZ 325
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MALLOC_LEN 0x40000
-#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_CLK 25000000
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_BOOTCOMMAND "sf probe;" \
- "mtdparts default;" \
- "bootm 0x9f680000"
-
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_SIZE 0x10000
-
-/* Miscellaneous configurable options */
-
-/*
- * Diagnostics
- */
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x83f00000
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (68 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 69/93] arm: Remove ap143 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-22 0:47 ` Daniel Schwierzeck
2018-11-19 15:53 ` [U-Boot] [PATCH 71/93] arm: Remove imgtec_xilfpga board Simon Glass
` (27 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/mips/mach-ath79/Kconfig | 1 -
board/qca/ap121/Kconfig | 27 ----------------
board/qca/ap121/MAINTAINERS | 6 ----
board/qca/ap121/Makefile | 3 --
board/qca/ap121/ap121.c | 46 ---------------------------
configs/ap121_defconfig | 60 ------------------------------------
include/configs/ap121.h | 46 ---------------------------
7 files changed, 189 deletions(-)
delete mode 100644 board/qca/ap121/Kconfig
delete mode 100644 board/qca/ap121/MAINTAINERS
delete mode 100644 board/qca/ap121/Makefile
delete mode 100644 board/qca/ap121/ap121.c
delete mode 100644 configs/ap121_defconfig
delete mode 100644 include/configs/ap121.h
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 1553aabcea7..3d9c616bc0e 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -50,7 +50,6 @@ config BOARD_TPLINK_WDR4300
endchoice
-source "board/qca/ap121/Kconfig"
source "board/tplink/wdr4300/Kconfig"
endmenu
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
deleted file mode 100644
index 4fd6a7167a5..00000000000
--- a/board/qca/ap121/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if TARGET_AP121
-
-config SYS_VENDOR
- default "qca"
-
-config SYS_BOARD
- default "ap121"
-
-config SYS_CONFIG_NAME
- default "ap121"
-
-config SYS_TEXT_BASE
- default 0x9f000000
-
-config SYS_DCACHE_SIZE
- default 32768
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 65536
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-endif
diff --git a/board/qca/ap121/MAINTAINERS b/board/qca/ap121/MAINTAINERS
deleted file mode 100644
index 8b02988d605..00000000000
--- a/board/qca/ap121/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-AP121 BOARD
-M: Wills Wang <wills.wang@live.com>
-S: Maintained
-F: board/qca/ap121/
-F: include/configs/ap121.h
-F: configs/ap121_defconfig
diff --git a/board/qca/ap121/Makefile b/board/qca/ap121/Makefile
deleted file mode 100644
index 7cdf53cf9ec..00000000000
--- a/board/qca/ap121/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y = ap121.o
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
deleted file mode 100644
index 24acdcb2e6f..00000000000
--- a/board/qca/ap121/ap121.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/addrspace.h>
-#include <asm/types.h>
-#include <mach/ar71xx_regs.h>
-#include <mach/ddr.h>
-#include <mach/ath79.h>
-#include <debug_uart.h>
-
-#ifdef CONFIG_DEBUG_UART_BOARD_INIT
-void board_debug_uart_init(void)
-{
- void __iomem *regs;
- u32 val;
-
- regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
- MAP_NOCACHE);
-
- /*
- * GPIO9 as input, GPIO10 as output
- */
- val = readl(regs + AR71XX_GPIO_REG_OE);
- val &= ~AR933X_GPIO(9);
- val |= AR933X_GPIO(10);
- writel(val, regs + AR71XX_GPIO_REG_OE);
-
- /*
- * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
- */
- val = readl(regs + AR71XX_GPIO_REG_FUNC);
- val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
- writel(val, regs + AR71XX_GPIO_REG_FUNC);
-}
-#endif
-
-int board_early_init_f(void)
-{
- ddr_init();
- ath79_eth_reset();
- return 0;
-}
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
deleted file mode 100644
index 5d54267cd34..00000000000
--- a/configs/ap121_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0x9F000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_DEBUG_UART_BOARD_INIT=y
-CONFIG_DEBUG_UART_BASE=0xb8020000
-CONFIG_DEBUG_UART_CLOCK=25000000
-CONFIG_ARCH_ATH79=y
-CONFIG_DEBUG_UART=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
-CONFIG_DISPLAY_CPUINFO=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_PROMPT="ap121 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6144k(rootfs),1600k(uImage),64k(NVRAM),64k(ART)"
-# CONFIG_ISO_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="ap121"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_DATAFLASH=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_DM_ETH=y
-CONFIG_AG7XXX=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_AR933X=y
-CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_AR933X=y
-CONFIG_AR933X_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_ATH79_SPI=y
-CONFIG_LZMA=y
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
deleted file mode 100644
index 96850b5761c..00000000000
--- a/include/configs/ap121.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_MHZ 200
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MALLOC_LEN 0x40000
-#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_BOOTCOMMAND "sf probe;" \
- "mtdparts default;" \
- "bootm 0x9f650000"
-
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_SIZE 0x10000
-
-/* Miscellaneous configurable options */
-
-/*
- * Diagnostics
- */
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x83f00000
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-19 15:53 ` [U-Boot] [PATCH 70/93] arm: Remove ap121 board Simon Glass
@ 2018-11-22 0:47 ` Daniel Schwierzeck
2018-11-22 0:53 ` Tom Rini
2018-11-22 20:50 ` Simon Glass
0 siblings, 2 replies; 211+ messages in thread
From: Daniel Schwierzeck @ 2018-11-22 0:47 UTC (permalink / raw)
To: u-boot
Hi Simon,
Am 19.11.18 um 16:53 schrieb Simon Glass:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/mips/mach-ath79/Kconfig | 1 -
> board/qca/ap121/Kconfig | 27 ----------------
> board/qca/ap121/MAINTAINERS | 6 ----
> board/qca/ap121/Makefile | 3 --
> board/qca/ap121/ap121.c | 46 ---------------------------
> configs/ap121_defconfig | 60 ------------------------------------
> include/configs/ap121.h | 46 ---------------------------
> 7 files changed, 189 deletions(-)
> delete mode 100644 board/qca/ap121/Kconfig
> delete mode 100644 board/qca/ap121/MAINTAINERS
> delete mode 100644 board/qca/ap121/Makefile
> delete mode 100644 board/qca/ap121/ap121.c
> delete mode 100644 configs/ap121_defconfig
> delete mode 100644 include/configs/ap121.h
your approach with simply forcing CONFIG_BLK is flawed. This board
doesn't use any block devices. If I enable CONFIG_BLK manually via
menuconfig, I get this link error:
LD u-boot
drivers/built-in.o: In function `blk_post_probe':
drivers/block/blk-uclass.c:(.text.blk_post_probe+0x10): undefined
reference to `part_init'
make: *** [Makefile:1381: u-boot] Error 1
But part_init() is defined in disk/part.c and guarded by
CONFIG_HAVE_BLOCK_DEVICE. If I enable that too, the board will build fine.
So the actual bug is that CONFIG_BLK doesn't do a SELECT PARTITIONS or
that drivers/block/blk-uclass.c doesn't guard the call to part_init()
with CONFIG_HAVE_BLOCK_DEVICE. Maybe you should fix that and then try
again. I guess you will have much less failing boards.
--
- Daniel
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-22 0:47 ` Daniel Schwierzeck
@ 2018-11-22 0:53 ` Tom Rini
2018-11-22 20:50 ` Simon Glass
1 sibling, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-22 0:53 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 01:47:24AM +0100, Daniel Schwierzeck wrote:
> Hi Simon,
>
> Am 19.11.18 um 16:53 schrieb Simon Glass:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > arch/mips/mach-ath79/Kconfig | 1 -
> > board/qca/ap121/Kconfig | 27 ----------------
> > board/qca/ap121/MAINTAINERS | 6 ----
> > board/qca/ap121/Makefile | 3 --
> > board/qca/ap121/ap121.c | 46 ---------------------------
> > configs/ap121_defconfig | 60 ------------------------------------
> > include/configs/ap121.h | 46 ---------------------------
> > 7 files changed, 189 deletions(-)
> > delete mode 100644 board/qca/ap121/Kconfig
> > delete mode 100644 board/qca/ap121/MAINTAINERS
> > delete mode 100644 board/qca/ap121/Makefile
> > delete mode 100644 board/qca/ap121/ap121.c
> > delete mode 100644 configs/ap121_defconfig
> > delete mode 100644 include/configs/ap121.h
>
> your approach with simply forcing CONFIG_BLK is flawed. This board
> doesn't use any block devices. If I enable CONFIG_BLK manually via
> menuconfig, I get this link error:
>
> LD u-boot
> drivers/built-in.o: In function `blk_post_probe':
> drivers/block/blk-uclass.c:(.text.blk_post_probe+0x10): undefined
> reference to `part_init'
> make: *** [Makefile:1381: u-boot] Error 1
>
> But part_init() is defined in disk/part.c and guarded by
> CONFIG_HAVE_BLOCK_DEVICE. If I enable that too, the board will build fine.
>
> So the actual bug is that CONFIG_BLK doesn't do a SELECT PARTITIONS or
> that drivers/block/blk-uclass.c doesn't guard the call to part_init()
> with CONFIG_HAVE_BLOCK_DEVICE. Maybe you should fix that and then try
> again. I guess you will have much less failing boards.
There's a few different parts to the problem of switching more globally
to BLK being enabled. And yes, you're right, we need to do something to
ensure that disk/part.o is linked in or drivers/block/blk-uclass.c only
calls part_init() in fewer cases. Thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-22 0:47 ` Daniel Schwierzeck
2018-11-22 0:53 ` Tom Rini
@ 2018-11-22 20:50 ` Simon Glass
2018-11-22 23:23 ` Tom Rini
1 sibling, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Daniel,
On Wed, 21 Nov 2018 at 17:47, Daniel Schwierzeck
<daniel.schwierzeck@gmail.com> wrote:
>
> Hi Simon,
>
> Am 19.11.18 um 16:53 schrieb Simon Glass:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > arch/mips/mach-ath79/Kconfig | 1 -
> > board/qca/ap121/Kconfig | 27 ----------------
> > board/qca/ap121/MAINTAINERS | 6 ----
> > board/qca/ap121/Makefile | 3 --
> > board/qca/ap121/ap121.c | 46 ---------------------------
> > configs/ap121_defconfig | 60 ------------------------------------
> > include/configs/ap121.h | 46 ---------------------------
> > 7 files changed, 189 deletions(-)
> > delete mode 100644 board/qca/ap121/Kconfig
> > delete mode 100644 board/qca/ap121/MAINTAINERS
> > delete mode 100644 board/qca/ap121/Makefile
> > delete mode 100644 board/qca/ap121/ap121.c
> > delete mode 100644 configs/ap121_defconfig
> > delete mode 100644 include/configs/ap121.h
>
> your approach with simply forcing CONFIG_BLK is flawed. This board
> doesn't use any block devices. If I enable CONFIG_BLK manually via
> menuconfig, I get this link error:
>
> LD u-boot
> drivers/built-in.o: In function `blk_post_probe':
> drivers/block/blk-uclass.c:(.text.blk_post_probe+0x10): undefined
> reference to `part_init'
> make: *** [Makefile:1381: u-boot] Error 1
>
> But part_init() is defined in disk/part.c and guarded by
> CONFIG_HAVE_BLOCK_DEVICE. If I enable that too, the board will build fine.
>
> So the actual bug is that CONFIG_BLK doesn't do a SELECT PARTITIONS or
> that drivers/block/blk-uclass.c doesn't guard the call to part_init()
> with CONFIG_HAVE_BLOCK_DEVICE. Maybe you should fix that and then try
> again. I guess you will have much less failing boards.
Unfortunately there are many things that can go wrong.
CONFIG_HAVE_BLOCK_DEVICE should be removed, I think, and the 5 boards
that use it updated. With DM we can just use CONFIG_BLK.
If CONFIG_BLK is enabled, that means we have block devices. Ideally we
would not enable it by default, and perhaps there is some Kconfig
magic that can enable it only when USB/MMC/etc, are enabled in
Kconfig? But that will not cause us to detect all boards that need
updating, since boards that don't use DM for the subsystem would then
get CONFIG_BLK enabled.
Here I think the best solution is for you to send a patch which
disables CONFIG_BLK for your boards (either in Kconfig or defconfig).
That should take precedence over CONFIG_BLK becoming the default.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-22 20:50 ` Simon Glass
@ 2018-11-22 23:23 ` Tom Rini
2018-11-24 19:42 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-22 23:23 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 01:50:08PM -0700, Simon Glass wrote:
> Hi Daniel,
>
> On Wed, 21 Nov 2018 at 17:47, Daniel Schwierzeck
> <daniel.schwierzeck@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > Am 19.11.18 um 16:53 schrieb Simon Glass:
> > > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > Remove it.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > arch/mips/mach-ath79/Kconfig | 1 -
> > > board/qca/ap121/Kconfig | 27 ----------------
> > > board/qca/ap121/MAINTAINERS | 6 ----
> > > board/qca/ap121/Makefile | 3 --
> > > board/qca/ap121/ap121.c | 46 ---------------------------
> > > configs/ap121_defconfig | 60 ------------------------------------
> > > include/configs/ap121.h | 46 ---------------------------
> > > 7 files changed, 189 deletions(-)
> > > delete mode 100644 board/qca/ap121/Kconfig
> > > delete mode 100644 board/qca/ap121/MAINTAINERS
> > > delete mode 100644 board/qca/ap121/Makefile
> > > delete mode 100644 board/qca/ap121/ap121.c
> > > delete mode 100644 configs/ap121_defconfig
> > > delete mode 100644 include/configs/ap121.h
> >
> > your approach with simply forcing CONFIG_BLK is flawed. This board
> > doesn't use any block devices. If I enable CONFIG_BLK manually via
> > menuconfig, I get this link error:
> >
> > LD u-boot
> > drivers/built-in.o: In function `blk_post_probe':
> > drivers/block/blk-uclass.c:(.text.blk_post_probe+0x10): undefined
> > reference to `part_init'
> > make: *** [Makefile:1381: u-boot] Error 1
> >
> > But part_init() is defined in disk/part.c and guarded by
> > CONFIG_HAVE_BLOCK_DEVICE. If I enable that too, the board will build fine.
> >
> > So the actual bug is that CONFIG_BLK doesn't do a SELECT PARTITIONS or
> > that drivers/block/blk-uclass.c doesn't guard the call to part_init()
> > with CONFIG_HAVE_BLOCK_DEVICE. Maybe you should fix that and then try
> > again. I guess you will have much less failing boards.
>
> Unfortunately there are many things that can go wrong.
>
> CONFIG_HAVE_BLOCK_DEVICE should be removed, I think, and the 5 boards
> that use it updated. With DM we can just use CONFIG_BLK.
>
> If CONFIG_BLK is enabled, that means we have block devices. Ideally we
> would not enable it by default, and perhaps there is some Kconfig
> magic that can enable it only when USB/MMC/etc, are enabled in
> Kconfig? But that will not cause us to detect all boards that need
> updating, since boards that don't use DM for the subsystem would then
> get CONFIG_BLK enabled.
>
> Here I think the best solution is for you to send a patch which
> disables CONFIG_BLK for your boards (either in Kconfig or defconfig).
> That should take precedence over CONFIG_BLK becoming the default.
No, the problem we have right here is that the logic in
drivers/block/blk-uclass.c to call part_init() doesn't match the logic
we have around when we build disk/part.c that defines part_init().
Locally I've made disk/part.o be built with CONFIG_BLK (and SPL/TPL).
Once we've got the transition done we can see what clean-ups follow from
it.
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-22 23:23 ` Tom Rini
@ 2018-11-24 19:42 ` Simon Glass
2018-11-24 21:22 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-24 19:42 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Thu, 22 Nov 2018 at 16:23, Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, Nov 22, 2018 at 01:50:08PM -0700, Simon Glass wrote:
> > Hi Daniel,
> >
> > On Wed, 21 Nov 2018 at 17:47, Daniel Schwierzeck
> > <daniel.schwierzeck@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > Am 19.11.18 um 16:53 schrieb Simon Glass:
> > > > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > Remove it.
> > > >
> > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > ---
> > > >
> > > > arch/mips/mach-ath79/Kconfig | 1 -
> > > > board/qca/ap121/Kconfig | 27 ----------------
> > > > board/qca/ap121/MAINTAINERS | 6 ----
> > > > board/qca/ap121/Makefile | 3 --
> > > > board/qca/ap121/ap121.c | 46 ---------------------------
> > > > configs/ap121_defconfig | 60 ------------------------------------
> > > > include/configs/ap121.h | 46 ---------------------------
> > > > 7 files changed, 189 deletions(-)
> > > > delete mode 100644 board/qca/ap121/Kconfig
> > > > delete mode 100644 board/qca/ap121/MAINTAINERS
> > > > delete mode 100644 board/qca/ap121/Makefile
> > > > delete mode 100644 board/qca/ap121/ap121.c
> > > > delete mode 100644 configs/ap121_defconfig
> > > > delete mode 100644 include/configs/ap121.h
> > >
> > > your approach with simply forcing CONFIG_BLK is flawed. This board
> > > doesn't use any block devices. If I enable CONFIG_BLK manually via
> > > menuconfig, I get this link error:
> > >
> > > LD u-boot
> > > drivers/built-in.o: In function `blk_post_probe':
> > > drivers/block/blk-uclass.c:(.text.blk_post_probe+0x10): undefined
> > > reference to `part_init'
> > > make: *** [Makefile:1381: u-boot] Error 1
> > >
> > > But part_init() is defined in disk/part.c and guarded by
> > > CONFIG_HAVE_BLOCK_DEVICE. If I enable that too, the board will build fine.
> > >
> > > So the actual bug is that CONFIG_BLK doesn't do a SELECT PARTITIONS or
> > > that drivers/block/blk-uclass.c doesn't guard the call to part_init()
> > > with CONFIG_HAVE_BLOCK_DEVICE. Maybe you should fix that and then try
> > > again. I guess you will have much less failing boards.
> >
> > Unfortunately there are many things that can go wrong.
> >
> > CONFIG_HAVE_BLOCK_DEVICE should be removed, I think, and the 5 boards
> > that use it updated. With DM we can just use CONFIG_BLK.
> >
> > If CONFIG_BLK is enabled, that means we have block devices. Ideally we
> > would not enable it by default, and perhaps there is some Kconfig
> > magic that can enable it only when USB/MMC/etc, are enabled in
> > Kconfig? But that will not cause us to detect all boards that need
> > updating, since boards that don't use DM for the subsystem would then
> > get CONFIG_BLK enabled.
> >
> > Here I think the best solution is for you to send a patch which
> > disables CONFIG_BLK for your boards (either in Kconfig or defconfig).
> > That should take precedence over CONFIG_BLK becoming the default.
>
> No, the problem we have right here is that the logic in
> drivers/block/blk-uclass.c to call part_init() doesn't match the logic
> we have around when we build disk/part.c that defines part_init().
> Locally I've made disk/part.o be built with CONFIG_BLK (and SPL/TPL).
> Once we've got the transition done we can see what clean-ups follow from
> it.
Oh wow I see.
But it seems to me that CONFIG_HAVE_BLOCK_DEVICE could be dropped and
we could just use CONFIG_BLK?
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 70/93] arm: Remove ap121 board
2018-11-24 19:42 ` Simon Glass
@ 2018-11-24 21:22 ` Tom Rini
0 siblings, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-24 21:22 UTC (permalink / raw)
To: u-boot
On Sat, Nov 24, 2018 at 12:42:21PM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Thu, 22 Nov 2018 at 16:23, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, Nov 22, 2018 at 01:50:08PM -0700, Simon Glass wrote:
> > > Hi Daniel,
> > >
> > > On Wed, 21 Nov 2018 at 17:47, Daniel Schwierzeck
> > > <daniel.schwierzeck@gmail.com> wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > Am 19.11.18 um 16:53 schrieb Simon Glass:
> > > > > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > > > > Remove it.
> > > > >
> > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > ---
> > > > >
> > > > > arch/mips/mach-ath79/Kconfig | 1 -
> > > > > board/qca/ap121/Kconfig | 27 ----------------
> > > > > board/qca/ap121/MAINTAINERS | 6 ----
> > > > > board/qca/ap121/Makefile | 3 --
> > > > > board/qca/ap121/ap121.c | 46 ---------------------------
> > > > > configs/ap121_defconfig | 60 ------------------------------------
> > > > > include/configs/ap121.h | 46 ---------------------------
> > > > > 7 files changed, 189 deletions(-)
> > > > > delete mode 100644 board/qca/ap121/Kconfig
> > > > > delete mode 100644 board/qca/ap121/MAINTAINERS
> > > > > delete mode 100644 board/qca/ap121/Makefile
> > > > > delete mode 100644 board/qca/ap121/ap121.c
> > > > > delete mode 100644 configs/ap121_defconfig
> > > > > delete mode 100644 include/configs/ap121.h
> > > >
> > > > your approach with simply forcing CONFIG_BLK is flawed. This board
> > > > doesn't use any block devices. If I enable CONFIG_BLK manually via
> > > > menuconfig, I get this link error:
> > > >
> > > > LD u-boot
> > > > drivers/built-in.o: In function `blk_post_probe':
> > > > drivers/block/blk-uclass.c:(.text.blk_post_probe+0x10): undefined
> > > > reference to `part_init'
> > > > make: *** [Makefile:1381: u-boot] Error 1
> > > >
> > > > But part_init() is defined in disk/part.c and guarded by
> > > > CONFIG_HAVE_BLOCK_DEVICE. If I enable that too, the board will build fine.
> > > >
> > > > So the actual bug is that CONFIG_BLK doesn't do a SELECT PARTITIONS or
> > > > that drivers/block/blk-uclass.c doesn't guard the call to part_init()
> > > > with CONFIG_HAVE_BLOCK_DEVICE. Maybe you should fix that and then try
> > > > again. I guess you will have much less failing boards.
> > >
> > > Unfortunately there are many things that can go wrong.
> > >
> > > CONFIG_HAVE_BLOCK_DEVICE should be removed, I think, and the 5 boards
> > > that use it updated. With DM we can just use CONFIG_BLK.
> > >
> > > If CONFIG_BLK is enabled, that means we have block devices. Ideally we
> > > would not enable it by default, and perhaps there is some Kconfig
> > > magic that can enable it only when USB/MMC/etc, are enabled in
> > > Kconfig? But that will not cause us to detect all boards that need
> > > updating, since boards that don't use DM for the subsystem would then
> > > get CONFIG_BLK enabled.
> > >
> > > Here I think the best solution is for you to send a patch which
> > > disables CONFIG_BLK for your boards (either in Kconfig or defconfig).
> > > That should take precedence over CONFIG_BLK becoming the default.
> >
> > No, the problem we have right here is that the logic in
> > drivers/block/blk-uclass.c to call part_init() doesn't match the logic
> > we have around when we build disk/part.c that defines part_init().
> > Locally I've made disk/part.o be built with CONFIG_BLK (and SPL/TPL).
> > Once we've got the transition done we can see what clean-ups follow from
> > it.
>
> Oh wow I see.
>
> But it seems to me that CONFIG_HAVE_BLOCK_DEVICE could be dropped and
> we could just use CONFIG_BLK?
Now? Not sure. Eventually? Yes.
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 71/93] arm: Remove imgtec_xilfpga board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (69 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 70/93] arm: Remove ap121 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 72/93] arm: Remove socfpga_de0_nano_soc board Simon Glass
` (26 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/mips/Kconfig | 1 -
board/imgtec/xilfpga/Kconfig | 15 ---------
board/imgtec/xilfpga/MAINTAINERS | 6 ----
board/imgtec/xilfpga/Makefile | 7 ----
board/imgtec/xilfpga/README | 55 --------------------------------
board/imgtec/xilfpga/xilfpga.c | 23 -------------
configs/imgtec_xilfpga_defconfig | 27 ----------------
7 files changed, 134 deletions(-)
delete mode 100644 board/imgtec/xilfpga/Kconfig
delete mode 100644 board/imgtec/xilfpga/MAINTAINERS
delete mode 100644 board/imgtec/xilfpga/Makefile
delete mode 100644 board/imgtec/xilfpga/README
delete mode 100644 board/imgtec/xilfpga/xilfpga.c
delete mode 100644 configs/imgtec_xilfpga_defconfig
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6d646ef9997..b19cb51677b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -131,7 +131,6 @@ endchoice
source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
-source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
diff --git a/board/imgtec/xilfpga/Kconfig b/board/imgtec/xilfpga/Kconfig
deleted file mode 100644
index b0782780f64..00000000000
--- a/board/imgtec/xilfpga/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_XILFPGA
-
-config SYS_BOARD
- default "xilfpga"
-
-config SYS_VENDOR
- default "imgtec"
-
-config SYS_CONFIG_NAME
- default "imgtec_xilfpga"
-
-config SYS_TEXT_BASE
- default 0x80C00000
-
-endif
diff --git a/board/imgtec/xilfpga/MAINTAINERS b/board/imgtec/xilfpga/MAINTAINERS
deleted file mode 100644
index aa045325eac..00000000000
--- a/board/imgtec/xilfpga/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XILFPGA BOARD
-M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
-S: Maintained
-F: board/imgtec/xilfpga
-F: include/configs/xilfpga.h
-F: configs/imgtec_xilfpga_defconfig
diff --git a/board/imgtec/xilfpga/Makefile b/board/imgtec/xilfpga/Makefile
deleted file mode 100644
index 9aaf9ce263f..00000000000
--- a/board/imgtec/xilfpga/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2016, Imagination Technologies Ltd.
-# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-obj-y := xilfpga.o
diff --git a/board/imgtec/xilfpga/README b/board/imgtec/xilfpga/README
deleted file mode 100644
index ac19d485d4a..00000000000
--- a/board/imgtec/xilfpga/README
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2016, Imagination Technologies Ltd.
- *
- * Zubair Lutfullah Kakakhel, Zubair.Kakakhel at imgtec.com
- */
-
-MIPSfpga
-=======================================
-
-MIPSfpga is an FPGA based development platform by Imagination Technologies
-As we are dealing with a MIPS core instantiated on an FPGA, specifications
-are fluid and can be varied in RTL.
-
-The example project provided by IMGTEC runs on the Nexys4DDR board by
-Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
-the example project and the Nexys4DDR board:
-
-- microAptiv UP core m14Kc
-- 50MHz clock speed
-- 128Mbyte DDR RAM at 0x0000_0000
-- 8Kbyte RAM at 0x1000_0000
-- axi_intc at 0x1020_0000
-- axi_uart16550 at 0x1040_0000
-- axi_gpio at 0x1060_0000
-- axi_i2c at 0x10A0_0000
-- custom_gpio at 0x10C0_0000
-- axi_ethernetlite at 0x10E0_0000
-- 8Kbyte BootRAM at 0x1FC0_0000
-- 16Mbyte QPI at 0x1D00_0000
-
-Boot protocol:
---------------
-
-The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
-This is for easy reprogrammibility via JTAG.
-
-DDR initialization is already handled by a HW IP block.
-
-When the example project bitstream is loaded, the cpu_reset button
-needs to be pressed.
-
-The bootram initializes the cache and axi_uart
-Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
-
-If there is, then that is considered as u-boot. u-boot is copied from
-0x1D40_0000 to memory and the bootram jumps into u-boot code.
-
-At this point, the board is ready to load the Linux kernel + buildroot initramfs
-
-This can be done in multiple ways:
-
-1- JTAG load the binary and jump into it.
-2- Load kernel stored in the QSPI flash at 0x1D80_0000
-3- Load uImage via tftp. Ethernet works in u-boot.
- e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
deleted file mode 100644
index 86645155e64..00000000000
--- a/board/imgtec/xilfpga/xilfpga.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Imagination Technologies MIPSfpga platform code
- *
- * Copyright (C) 2016, Imagination Technologies Ltd.
- *
- * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
- *
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* initialize the DDR Controller and PHY */
-int dram_init(void)
-{
- /* MIG IP block is smart and doesn't need SW
- * to do any init */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */
-
- return 0;
-}
diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig
deleted file mode 100644
index 4fe75311de2..00000000000
--- a/configs/imgtec_xilfpga_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_MALLOC_F_LEN=0x600
-CONFIG_TARGET_XILFPGA=y
-# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
-CONFIG_MIPS_BOOT_FDT=y
-CONFIG_BOOTDELAY=5
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="MIPSfpga # "
-# CONFIG_CMD_SAVEENV is not set
-CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_CLK=y
-CONFIG_XILINX_EMACLITE=y
-CONFIG_SYS_NS16550=y
-CONFIG_CMD_DHRYSTONE=y
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 72/93] arm: Remove socfpga_de0_nano_soc board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (70 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 71/93] arm: Remove imgtec_xilfpga board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 73/93] arm: Remove clearfog board Simon Glass
` (25 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/socfpga_de0_nano_soc_defconfig | 72 --------------------------
include/configs/socfpga_de0_nano_soc.h | 22 --------
2 files changed, 94 deletions(-)
delete mode 100644 configs/socfpga_de0_nano_soc_defconfig
delete mode 100644 include/configs/socfpga_de0_nano_soc.h
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
deleted file mode 100644
index 1a9f2b60388..00000000000
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="terasic"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
deleted file mode 100644
index d3224d5bd31..00000000000
--- a/include/configs/socfpga_de0_nano_soc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_TERASIC_DE0_H__
-#define __CONFIG_TERASIC_DE0_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_TERASIC_DE0_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 73/93] arm: Remove clearfog board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (71 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 72/93] arm: Remove socfpga_de0_nano_soc board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 74/93] arm: Remove socfpga_arria10 board Simon Glass
` (24 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/solidrun/clearfog/MAINTAINERS | 6 --
board/solidrun/clearfog/Makefile | 5 -
board/solidrun/clearfog/README | 51 ---------
board/solidrun/clearfog/clearfog.c | 141 -------------------------
configs/clearfog_defconfig | 66 ------------
include/configs/clearfog.h | 157 ----------------------------
6 files changed, 426 deletions(-)
delete mode 100644 board/solidrun/clearfog/MAINTAINERS
delete mode 100644 board/solidrun/clearfog/Makefile
delete mode 100644 board/solidrun/clearfog/README
delete mode 100644 board/solidrun/clearfog/clearfog.c
delete mode 100644 configs/clearfog_defconfig
delete mode 100644 include/configs/clearfog.h
diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS
deleted file mode 100644
index 6d0c3ef58bd..00000000000
--- a/board/solidrun/clearfog/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CLEARFOG BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/solidrun/clearfog/
-F: include/configs/clearfog.h
-F: configs/clearfog_defconfig
diff --git a/board/solidrun/clearfog/Makefile b/board/solidrun/clearfog/Makefile
deleted file mode 100644
index 5cfda3283c5..00000000000
--- a/board/solidrun/clearfog/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-
-obj-y := clearfog.o
diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README
deleted file mode 100644
index a7bc0d4e23f..00000000000
--- a/board/solidrun/clearfog/README
+++ /dev/null
@@ -1,51 +0,0 @@
-Update from original Marvell U-Boot to mainline U-Boot:
--------------------------------------------------------
-
-Generate the U-Boot image with these commands:
-
-$ make clearfog_defconfig
-$ make
-
-The resulting image including the SPL binary with the
-full DDR setup is "u-boot-spl.kwb".
-
-Now all you need to do is copy this image on a SD card.
-For example with this command:
-
-$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
-
-Please use the correct device node for your setup instead
-of "/dev/sdX" here!
-
-Boot selection:
----------------
-
-Before powering up the board, boot selection should be done via the SW1 dip
-switch (0: OFF, 1: ON):
-
- - SPI: 00010
- - SD/eMMC: 00111
- - M.2 SSD: 11100
- - UART: 01001 [1]
-
-[1]: According to SolidRun's manual, 11110 should be used for UART booting on
- the ClearFog 'Pro' variant.
- However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as
- mentionend for the 'Base' variant does).
-
-Boot from UART:
----------------
-
-Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
-to your host.
-
-Set the SW1 DIP switches to UART boot (see above).
-
-Run the following command to initiate U-Boot download:
-
- ./tools/kwboot -b u-boot-spl.kwb /dev/ttyUSBX
-
-Use the correct UART device node for /dev/ttyUSBX.
-
-When download finishes start your favorite terminal emulator
-on /dev/ttyUSBX.
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
deleted file mode 100644
index 4e1386c8a22..00000000000
--- a/board/solidrun/clearfog/clearfog.c
+++ /dev/null
@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
-#include <../serdes/a38x/high_speed_env_spec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
-/*
- * Those values and defines are taken from the Marvell U-Boot version
- * "u-boot-2013.01-15t1-clearfog"
- */
-#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
-#define BOARD_GPP_OUT_ENA_MID 0xffffffff
-
-#define BOARD_GPP_OUT_VAL_LOW 0x0
-#define BOARD_GPP_OUT_VAL_MID 0x0
-#define BOARD_GPP_POL_LOW 0x0
-#define BOARD_GPP_POL_MID 0x0
-
-static struct serdes_map board_serdes_map[] = {
- {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
- {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
- {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
-};
-
-int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
-{
- *serdes_map_array = board_serdes_map;
- *count = ARRAY_SIZE(board_serdes_map);
- return 0;
-}
-
-/*
- * Define the DDR layout / topology here in the board file. This will
- * be used by the DDR3 init code in the SPL U-Boot version to configure
- * the DDR3 controller.
- */
-static struct mv_ddr_topology_map board_topology_map = {
- DEBUG_LEVEL_ERROR,
- 0x1, /* active interfaces */
- /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
- { { { {0x1, 0, 0, 0},
- {0x1, 0, 0, 0},
- {0x1, 0, 0, 0},
- {0x1, 0, 0, 0},
- {0x1, 0, 0, 0} },
- SPEED_BIN_DDR_1600K, /* speed_bin */
- MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
- MV_DDR_DIE_CAP_4GBIT, /* mem_size */
- DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_LOW, /* temperature */
- MV_DDR_TIM_DEFAULT} }, /* timing */
- BUS_MASK_32BIT, /* Busses mask */
- MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
- { {0} }, /* raw spd data */
- {0} /* timing parameters */
-};
-
-struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
-{
- /* Return the board topology as defined in the board code */
- return &board_topology_map;
-}
-
-int board_early_init_f(void)
-{
- /* Configure MPP */
- writel(0x11111111, MVEBU_MPP_BASE + 0x00);
- writel(0x11111111, MVEBU_MPP_BASE + 0x04);
- writel(0x10400011, MVEBU_MPP_BASE + 0x08);
- writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
- writel(0x44400002, MVEBU_MPP_BASE + 0x10);
- writel(0x41144004, MVEBU_MPP_BASE + 0x14);
- writel(0x40333333, MVEBU_MPP_BASE + 0x18);
- writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
-
- /* Set GPP Out value */
- writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
- writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
-
- /* Set GPP Polarity */
- writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
- writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
-
- /* Set GPP Out Enable */
- writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
- writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- /* Toggle GPIO41 to reset onboard switch and phy */
- clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
- clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
- /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
- clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
- clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
- mdelay(1);
- setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
- setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
- mdelay(10);
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: SolidRun ClearFog\n");
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in controller(s) come first */
- return pci_eth_init(bis);
-}
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
deleted file mode 100644
index 2e59686291b..00000000000
--- a/configs/clearfog_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_TEXT_BASE=0x00800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_CLEARFOG=y
-CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI_AHCI=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MVTWSI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_MV=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_MVNETA=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_SCSI=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
deleted file mode 100644
index 77ab6caf52c..00000000000
--- a/include/configs/clearfog.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- */
-
-#ifndef _CONFIG_CLEARFOG_H
-#define _CONFIG_CLEARFOG_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-/*
- * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
- * for DDR ECC byte filling in the SPL before loading the main
- * U-Boot into it.
- */
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-
-/*
- * Commands configuration
- */
-
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_BUS 1
-
-/*
- * SDIO/MMC Card Configuration
- */
-#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-#endif
-
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
-#define CONFIG_ENV_MIN_ENTRIES 128
-
-/* Environment in MMC */
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SECT_SIZE 0x200
-#define CONFIG_ENV_SIZE 0x10000
-/*
- * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
- * boot image starts @ LBA-0.
- * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
- * image and environment
- */
-#define CONFIG_ENV_OFFSET 0xf0000
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
-
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
-/* PCIe support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-/* SATA support */
-#ifdef CONFIG_SCSI
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-/* Keep device tree and initrd in lower memory so the kernel can access them */
-#define RELOCATION_LIMITS_ENV_SETTINGS \
- "fdt_high=0x10000000\0" \
- "initrd_high=0x10000000\0"
-
-/* SPL */
-
-/* Defines for SPL */
-#define CONFIG_SPL_SIZE (140 << 10)
-#define CONFIG_SPL_TEXT_BASE 0x40000030
-#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
-
-#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
-#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-
-#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
-/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC)
-/* SPL related MMC defines */
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
-#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
-#endif
-#endif
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Include the common distro boot environment */
-#ifndef CONFIG_SPL_BUILD
-
-#ifdef CONFIG_MMC
-#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
-#else
-#define BOOT_TARGET_DEVICES_MMC(func)
-#endif
-
-#ifdef CONFIG_USB_STORAGE
-#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
-#else
-#define BOOT_TARGET_DEVICES_USB(func)
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
- BOOT_TARGET_DEVICES_MMC(func) \
- BOOT_TARGET_DEVICES_USB(func) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#define KERNEL_ADDR_R __stringify(0x800000)
-#define FDT_ADDR_R __stringify(0x100000)
-#define RAMDISK_ADDR_R __stringify(0x1800000)
-#define SCRIPT_ADDR_R __stringify(0x200000)
-#define PXEFILE_ADDR_R __stringify(0x300000)
-
-#define LOAD_ADDRESS_ENV_SETTINGS \
- "kernel_addr_r=" KERNEL_ADDR_R "\0" \
- "fdt_addr_r=" FDT_ADDR_R "\0" \
- "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
- "scriptaddr=" SCRIPT_ADDR_R "\0" \
- "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
-
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- RELOCATION_LIMITS_ENV_SETTINGS \
- LOAD_ADDRESS_ENV_SETTINGS \
- "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "console=ttyS0,115200\0" \
- BOOTENV
-
-#endif /* CONFIG_SPL_BUILD */
-
-#endif /* _CONFIG_CLEARFOG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 74/93] arm: Remove socfpga_arria10 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (72 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 73/93] arm: Remove clearfog board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 75/93] arm: Remove omap3_beagle board Simon Glass
` (23 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/altera/arria10-socdk/Kconfig | 18 ---------
board/altera/arria10-socdk/MAINTAINERS | 7 ----
board/altera/arria10-socdk/Makefile | 5 ---
board/altera/arria10-socdk/socfpga.c | 6 ---
configs/socfpga_arria10_defconfig | 44 ----------------------
include/configs/socfpga_arria10_socdk.h | 50 -------------------------
6 files changed, 130 deletions(-)
delete mode 100644 board/altera/arria10-socdk/Kconfig
delete mode 100644 board/altera/arria10-socdk/MAINTAINERS
delete mode 100644 board/altera/arria10-socdk/Makefile
delete mode 100644 board/altera/arria10-socdk/socfpga.c
delete mode 100644 configs/socfpga_arria10_defconfig
delete mode 100644 include/configs/socfpga_arria10_socdk.h
diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
deleted file mode 100644
index b80cc6d6f93..00000000000
--- a/board/altera/arria10-socdk/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-if TARGET_SOCFPGA_ARRIA10
-
-config SYS_CPU
- default "armv7"
-
-config SYS_BOARD
- default "socfpga_arria10"
-
-config SYS_VENDOR
- default "altera"
-
-config SYS_SOC
- default "socfpga_arria10"
-
-config SYS_CONFIG_NAME
- default "socfpga_arria10"
-
-endif
diff --git a/board/altera/arria10-socdk/MAINTAINERS b/board/altera/arria10-socdk/MAINTAINERS
deleted file mode 100644
index 5a76efb54ba..00000000000
--- a/board/altera/arria10-socdk/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@kernel.org>
-M: Chin-Liang See <clsee@altera.com>
-S: Maintained
-F: board/altera/arria10-socdk/
-F: include/configs/socfpga_arria10_socdk.h
-F: configs/socfpga_arria10_defconfig
diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile
deleted file mode 100644
index 80d00043464..00000000000
--- a/board/altera/arria10-socdk/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright (C) 2015 Altera Corporation <www.altera.com>
-
-obj-y := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c
deleted file mode 100644
index 4c466cb9444..00000000000
--- a/board/altera/arria10-socdk/socfpga.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2015 Altera Corporation <www.altera.com>
- */
-
-#include <common.h>
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
deleted file mode 100644
index 6ebda811355..00000000000
--- a/configs/socfpga_arria10_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_SPL=y
-CONFIG_IDENT_STRING="socfpga_arria10"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_FPGA_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_MTD_DEVICE=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_DESIGNWARE_APB_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
deleted file mode 100644
index 58e446b60a9..00000000000
--- a/include/configs/socfpga_arria10_socdk.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
- */
-
-#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
-#define __CONFIG_SOCFGPA_ARRIA10_H__
-
-#include <asm/arch/base_addr_a10.h>
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * U-Boot general configurations
- */
-/* Cache options */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000
-
-/* Ethernet on SoC (EMAC) */
-
-/*
- * U-Boot environment configurations
- */
-
-/*
- * Serial / UART configurations
- */
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * L4 OSC1 Timer 0
- */
-/* reload value when timer count to zero */
-#define TIMER_LOAD_VAL 0xFFFFFFFF
-
-/*
- * Flash configurations
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 75/93] arm: Remove omap3_beagle board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (73 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 74/93] arm: Remove socfpga_arria10 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 76/93] arm: Remove helios4 board Simon Glass
` (22 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap3/Kconfig | 1 -
board/ti/beagle/Kconfig | 12 -
board/ti/beagle/MAINTAINERS | 6 -
board/ti/beagle/Makefile | 7 -
board/ti/beagle/beagle.c | 591 ------------------------------
board/ti/beagle/beagle.h | 545 ---------------------------
board/ti/beagle/led.c | 71 ----
configs/omap3_beagle_defconfig | 82 -----
include/configs/omap3_beagle.h | 233 ------------
9 files changed, 1548 deletions(-)
delete mode 100644 board/ti/beagle/Kconfig
delete mode 100644 board/ti/beagle/MAINTAINERS
delete mode 100644 board/ti/beagle/Makefile
delete mode 100644 board/ti/beagle/beagle.c
delete mode 100644 board/ti/beagle/beagle.h
delete mode 100644 board/ti/beagle/led.c
delete mode 100644 configs/omap3_beagle_defconfig
delete mode 100644 include/configs/omap3_beagle.h
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 6e3942ad2d3..6f6ad424f84 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -195,7 +195,6 @@ config SYS_SOC
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
source "board/ti/evm/Kconfig"
diff --git a/board/ti/beagle/Kconfig b/board/ti/beagle/Kconfig
deleted file mode 100644
index c2eff9e71b0..00000000000
--- a/board/ti/beagle/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_BEAGLE
-
-config SYS_BOARD
- default "beagle"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap3_beagle"
-
-endif
diff --git a/board/ti/beagle/MAINTAINERS b/board/ti/beagle/MAINTAINERS
deleted file mode 100644
index c1d81d4174e..00000000000
--- a/board/ti/beagle/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BEAGLE BOARD
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-F: board/ti/beagle/
-F: include/configs/omap3_beagle.h
-F: configs/omap3_beagle_defconfig
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
deleted file mode 100644
index fc9288cf186..00000000000
--- a/board/ti/beagle/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := beagle.o
-obj-$(CONFIG_LED_STATUS) += led.o
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
deleted file mode 100644
index 826aace3fba..00000000000
--- a/board/ti/beagle/beagle.c
+++ /dev/null
@@ -1,591 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004-2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- */
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#ifdef CONFIG_LED_STATUS
-#include <status_led.h>
-#endif
-#include <twl4030.h>
-#include <linux/mtd/rawnand.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/omap_musb.h>
-#include <linux/errno.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <linux/usb/musb.h>
-#include "beagle.h"
-#include <command.h>
-
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-
-#define TWL4030_I2C_BUS 0
-#define EXPANSION_EEPROM_I2C_BUS 1
-#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
-
-#define TINCANTOOLS_ZIPPY 0x01000100
-#define TINCANTOOLS_ZIPPY2 0x02000100
-#define TINCANTOOLS_TRAINER 0x04000100
-#define TINCANTOOLS_SHOWDOG 0x03000100
-#define KBADC_BEAGLEFPGA 0x01000600
-#define LW_BEAGLETOUCH 0x01000700
-#define BRAINMUX_LCDOG 0x01000800
-#define BRAINMUX_LCDOGTOUCH 0x02000800
-#define BBTOYS_WIFI 0x01000B00
-#define BBTOYS_VGA 0x02000B00
-#define BBTOYS_LCD 0x03000B00
-#define BCT_BRETTL3 0x01000F00
-#define BCT_BRETTL4 0x02000F00
-#define LSR_COM6L_ADPT 0x01001300
-#define BEAGLE_NO_EEPROM 0xffffffff
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct {
- unsigned int device_vendor;
- unsigned char revision;
- unsigned char content;
- char fab_revision[8];
- char env_var[16];
- char env_setting[64];
-} expansion_config;
-
-static const struct ns16550_platdata beagle_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(beagle_uart) = {
- "ns16550_serial",
- &beagle_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
-
-/*
- * Routine: get_board_revision
- * Description: Detect if we are running on a Beagle revision Ax/Bx,
- * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
- * the level of GPIO173, GPIO172 and GPIO171. This should
- * result in
- * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
- * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
- * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
- * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
- */
-static int get_board_revision(void)
-{
- static int revision = -1;
-
- if (revision == -1) {
- if (!gpio_request(171, "rev0") &&
- !gpio_request(172, "rev1") &&
- !gpio_request(173, "rev2")) {
- gpio_direction_input(171);
- gpio_direction_input(172);
- gpio_direction_input(173);
-
- revision = gpio_get_value(173) << 2 |
- gpio_get_value(172) << 1 |
- gpio_get_value(171);
- } else {
- printf("Error: unable to acquire board revision GPIOs\n");
- }
- }
-
- return revision;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int pop_mfr, pop_id;
-
- /*
- * We need to identify what PoP memory is on the board so that
- * we know what timings to use. If we can't identify it then
- * we know it's an xM. To map the ID values please see nand_ids.c
- */
- identify_nand_chip(&pop_mfr, &pop_id);
-
- timings->mr = MICRON_V_MR_165;
- switch (get_board_revision()) {
- case REVISION_C4:
- if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
- /* 512MB DDR */
- timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
- /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
- /* Beagleboard Rev C5, 256MB DDR */
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- break;
- }
- case REVISION_XM_AB:
- case REVISION_XM_C:
- if (pop_mfr == 0) {
- /* 256MB DDR */
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- } else {
- /* 512MB DDR */
- timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
- break;
- default:
- /* Assume 128MB and Micron/165MHz timings to be safe */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
-}
-#endif
-
-/*
- * Routine: get_expansion_id
- * Description: This function checks for expansion board by checking I2C
- * bus 1 for the availability of an AT24C01B serial EEPROM.
- * returns the device_vendor field from the EEPROM
- */
-static unsigned int get_expansion_id(void)
-{
- i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
-
- /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
- if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
- i2c_set_bus_num(TWL4030_I2C_BUS);
- return BEAGLE_NO_EEPROM;
- }
-
- /* read configuration data */
- i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
- sizeof(expansion_config));
-
- /* retry reading configuration data with 16bit addressing */
- if ((expansion_config.device_vendor == 0xFFFFFF00) ||
- (expansion_config.device_vendor == 0xFFFFFFFF)) {
- printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
- i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
- sizeof(expansion_config));
- }
-
- i2c_set_bus_num(TWL4030_I2C_BUS);
-
- return expansion_config.device_vendor;
-}
-
-#ifdef CONFIG_VIDEO_OMAP3
-/*
- * Configure DSS to display background color on DVID
- * Configure VENC to display color bar on S-Video
- */
-static void beagle_display_init(void)
-{
- omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
- switch (get_board_revision()) {
- case REVISION_AXBX:
- case REVISION_CX:
- case REVISION_C4:
- omap3_dss_panel_config(&dvid_cfg);
- break;
- case REVISION_XM_AB:
- case REVISION_XM_C:
- default:
- omap3_dss_panel_config(&dvid_cfg_xm);
- break;
- }
-}
-
-/*
- * Enable DVI power
- */
-static void beagle_dvi_pup(void)
-{
- uchar val;
-
- switch (get_board_revision()) {
- case REVISION_AXBX:
- case REVISION_CX:
- case REVISION_C4:
- gpio_request(170, "dvi");
- gpio_direction_output(170, 0);
- gpio_set_value(170, 1);
- break;
- case REVISION_XM_AB:
- case REVISION_XM_C:
- default:
- #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
- #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
-
- i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
- val |= 4;
- i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
-
- i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
- val |= 4;
- i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_USB_MUSB_OMAP2PLUS
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
-#endif
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
- struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
- bool generate_fake_mac = false;
- u32 value;
-
- /* Enable i2c2 pullup resisters */
- value = readl(&prog_io_base->io1);
- value &= ~(PRG_I2C2_PULLUPRESX);
- writel(value, &prog_io_base->io1);
-
- switch (get_board_revision()) {
- case REVISION_AXBX:
- printf("Beagle Rev Ax/Bx\n");
- env_set("beaglerev", "AxBx");
- break;
- case REVISION_CX:
- printf("Beagle Rev C1/C2/C3\n");
- env_set("beaglerev", "Cx");
- MUX_BEAGLE_C();
- break;
- case REVISION_C4:
- printf("Beagle Rev C4\n");
- env_set("beaglerev", "C4");
- MUX_BEAGLE_C();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- break;
- case REVISION_XM_AB:
- printf("Beagle xM Rev A/B\n");
- env_set("beaglerev", "xMAB");
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- generate_fake_mac = true;
- break;
- case REVISION_XM_C:
- printf("Beagle xM Rev C\n");
- env_set("beaglerev", "xMC");
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- generate_fake_mac = true;
- break;
- default:
- printf("Beagle unknown 0x%02x\n", get_board_revision());
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- generate_fake_mac = true;
- }
-
- switch (get_expansion_id()) {
- case TINCANTOOLS_ZIPPY:
- printf("Recognized Tincantools Zippy board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_TINCANTOOLS_ZIPPY();
- env_set("buddy", "zippy");
- break;
- case TINCANTOOLS_ZIPPY2:
- printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_TINCANTOOLS_ZIPPY();
- env_set("buddy", "zippy2");
- break;
- case TINCANTOOLS_TRAINER:
- printf("Recognized Tincantools Trainer board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_TINCANTOOLS_ZIPPY();
- MUX_TINCANTOOLS_TRAINER();
- env_set("buddy", "trainer");
- break;
- case TINCANTOOLS_SHOWDOG:
- printf("Recognized Tincantools Showdow board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- /* Place holder for DSS2 definition for showdog lcd */
- env_set("defaultdisplay", "showdoglcd");
- env_set("buddy", "showdog");
- break;
- case KBADC_BEAGLEFPGA:
- printf("Recognized KBADC Beagle FPGA board\n");
- MUX_KBADC_BEAGLEFPGA();
- env_set("buddy", "beaglefpga");
- break;
- case LW_BEAGLETOUCH:
- printf("Recognized Liquidware BeagleTouch board\n");
- env_set("buddy", "beagletouch");
- break;
- case BRAINMUX_LCDOG:
- printf("Recognized Brainmux LCDog board\n");
- env_set("buddy", "lcdog");
- break;
- case BRAINMUX_LCDOGTOUCH:
- printf("Recognized Brainmux LCDog Touch board\n");
- env_set("buddy", "lcdogtouch");
- break;
- case BBTOYS_WIFI:
- printf("Recognized BeagleBoardToys WiFi board\n");
- MUX_BBTOYS_WIFI()
- env_set("buddy", "bbtoys-wifi");
- break;
- case BBTOYS_VGA:
- printf("Recognized BeagleBoardToys VGA board\n");
- break;
- case BBTOYS_LCD:
- printf("Recognized BeagleBoardToys LCD board\n");
- break;
- case BCT_BRETTL3:
- printf("Recognized bct electronic GmbH brettl3 board\n");
- break;
- case BCT_BRETTL4:
- printf("Recognized bct electronic GmbH brettl4 board\n");
- break;
- case LSR_COM6L_ADPT:
- printf("Recognized LSR COM6L Adapter Board\n");
- MUX_BBTOYS_WIFI()
- env_set("buddy", "lsr-com6l-adpt");
- break;
- case BEAGLE_NO_EEPROM:
- printf("No EEPROM on expansion board\n");
- env_set("buddy", "none");
- break;
- default:
- printf("Unrecognized expansion board: %x\n",
- expansion_config.device_vendor);
- env_set("buddy", "unknown");
- }
-
- if (expansion_config.content == 1)
- env_set(expansion_config.env_var, expansion_config.env_setting);
-
- twl4030_power_init();
- switch (get_board_revision()) {
- case REVISION_XM_AB:
- twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
- break;
- default:
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
- break;
- }
-
- /* Set GPIO states before they are made outputs */
- writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
- &gpio6_base->setdataout);
- writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
- GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
-
- /* Configure GPIOs to output */
- writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
- writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
- GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
-
- omap_die_id_display();
-
-#ifdef CONFIG_VIDEO_OMAP3
- beagle_dvi_pup();
- beagle_display_init();
- omap3_dss_enable();
-#endif
-
-#ifdef CONFIG_USB_MUSB_OMAP2PLUS
- musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
-#endif
-
- if (generate_fake_mac)
- omap_die_id_usbethaddr();
-
-#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
- if (strlen(CONFIG_MTDIDS_DEFAULT))
- env_set("mtdids", CONFIG_MTDIDS_DEFAULT);
-
- if (strlen(CONFIG_MTDPARTS_DEFAULT))
- env_set("mtdparts", CONFIG_MTDPARTS_DEFAULT);
-#endif
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_BEAGLE();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
-/* Call usb_stop() before starting the kernel */
-void show_boot_progress(int val)
-{
- if (val == BOOTSTAGE_ID_RUN_OS)
- usb_stop();
-}
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-
-#endif /* CONFIG_USB_EHCI_HCD */
-
-#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
-int board_eth_init(bd_t *bis)
-{
- return usb_eth_initialize(bis);
-}
-#endif
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
deleted file mode 100644
index ce78ea661b9..00000000000
--- a/board/ti/beagle/beagle.h
+++ /dev/null
@@ -1,545 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- */
-#ifndef _BEAGLE_H_
-#define _BEAGLE_H_
-
-#include <asm/arch/dss.h>
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 Beagle board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#else
- "NAND",
-#endif
-};
-
-/* BeagleBoard revisions */
-#define REVISION_AXBX 0x7
-#define REVISION_CX 0x6
-#define REVISION_C4 0x5
-#define REVISION_XM_AB 0x0
-#define REVISION_XM_C 0x2
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_BEAGLE() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
- /* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-#define MUX_BEAGLE_C() \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
- MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/
-
-#define MUX_BEAGLE_XM() \
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\
- MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)) /*GPIO_63*/\
- MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
- MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
- MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
- MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
- MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
- MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
-
-#define MUX_TINCANTOOLS_ZIPPY() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/
-
-#define MUX_TINCANTOOLS_TRAINER() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/
-
-#define MUX_KBADC_BEAGLEFPGA() \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
-
-#define MUX_BBTOYS_WIFI() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\
- MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
-
-/*
- * Display Configuration
- */
-
-#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
-#define VENC_HEIGHT 0x00ef
-#define VENC_WIDTH 0x027f
-
-/*
- * Configure VENC in DSS for Beagle to generate Color Bar
- *
- * Kindly refer to OMAP TRM for definition of these values.
- */
-static const struct venc_regs venc_config_std_tv = {
- .status = 0x0000001B,
- .f_control = 0x00000040,
- .vidout_ctrl = 0x00000000,
- .sync_ctrl = 0x00008000,
- .llen = 0x00008359,
- .flens = 0x0000020C,
- .hfltr_ctrl = 0x00000000,
- .cc_carr_wss_carr = 0x043F2631,
- .c_phase = 0x00000024,
- .gain_u = 0x00000130,
- .gain_v = 0x00000198,
- .gain_y = 0x000001C0,
- .black_level = 0x0000006A,
- .blank_level = 0x0000005C,
- .x_color = 0x00000000,
- .m_control = 0x00000001,
- .bstamp_wss_data = 0x0000003F,
- .s_carr = 0x21F07C1F,
- .line21 = 0x00000000,
- .ln_sel = 0x00000015,
- .l21__wc_ctl = 0x00001400,
- .htrigger_vtrigger = 0x00000000,
- .savid__eavid = 0x069300F4,
- .flen__fal = 0x0016020C,
- .lal__phase_reset = 0x00060107,
- .hs_int_start_stop_x = 0x008D034E,
- .hs_ext_start_stop_x = 0x000F0359,
- .vs_int_start_x = 0x01A00000,
- .vs_int_stop_x__vs_int_start_y = 0x020501A0,
- .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
- .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
- .vs_ext_stop_y = 0x00000006,
- .avid_start_stop_x = 0x03480079,
- .avid_start_stop_y = 0x02040024,
- .fid_int_start_x__fid_int_start_y = 0x0001008A,
- .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
- .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
- .tvdetgp_int_start_stop_x = 0x00140001,
- .tvdetgp_int_start_stop_y = 0x00010001,
- .gen_ctrl = 0x00FF0000,
- .output_control = 0x0000000D,
- .dac_b__dac_c = 0x00000000
-};
-
-/*
- * Configure Timings for DVI D
- */
-static const struct panel_config dvid_cfg = {
- .timing_h = 0x0ff03f31, /* Horizontal timing */
- .timing_v = 0x01400504, /* Vertical timing */
- .pol_freq = 0x00007028, /* Pol Freq */
- .divisor = 0x00010006, /* 72Mhz Pixel Clock */
- .lcd_size = 0x02ff03ff, /* 1024x768 */
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
-};
-
-static const struct panel_config dvid_cfg_xm = {
- .timing_h = 0x1a4024c9, /* Horizontal timing */
- .timing_v = 0x02c00509, /* Vertical timing */
- .pol_freq = 0x00007028, /* Pol Freq */
- .divisor = 0x00010001, /* 96MHz Pixel Clock */
- .lcd_size = 0x02ff03ff, /* 1024x768 */
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
-};
-#endif
diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c
deleted file mode 100644
index e21c0169db7..00000000000
--- a/board/ti/beagle/led.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2010 Texas Instruments, Inc.
- * Jason Kridner <jkridner@beagleboard.org>
- */
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-
-/* GPIO pins for the LEDs */
-#define BEAGLE_LED_USR0 150
-#define BEAGLE_LED_USR1 149
-
-#ifdef CONFIG_LED_STATUS_GREEN
-void green_led_off(void)
-{
- __led_set(CONFIG_LED_STATUS_GREEN, 0);
-}
-
-void green_led_on(void)
-{
- __led_set(CONFIG_LED_STATUS_GREEN, 1);
-}
-#endif
-
-static int get_led_gpio(led_id_t mask)
-{
-#ifdef CONFIG_LED_STATUS0
- if (CONFIG_LED_STATUS_BIT & mask)
- return BEAGLE_LED_USR0;
-#endif
-#ifdef CONFIG_LED_STATUS1
- if (CONFIG_LED_STATUS_BIT1 & mask)
- return BEAGLE_LED_USR1;
-#endif
-
- return 0;
-}
-
-void __led_init (led_id_t mask, int state)
-{
- int toggle_gpio;
-
- toggle_gpio = get_led_gpio(mask);
-
- if (toggle_gpio && !gpio_request(toggle_gpio, "led"))
- __led_set(mask, state);
-}
-
-void __led_toggle (led_id_t mask)
-{
- int state, toggle_gpio;
-
- toggle_gpio = get_led_gpio(mask);
- if (toggle_gpio) {
- state = gpio_get_value(toggle_gpio);
- gpio_direction_output(toggle_gpio, !state);
- }
-}
-
-void __led_set (led_id_t mask, int state)
-{
- int toggle_gpio;
-
- toggle_gpio = get_led_gpio(mask);
- if (toggle_gpio)
- gpio_direction_output(toggle_gpio, state);
-}
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
deleted file mode 100644
index 4fb8aec57db..00000000000
--- a/configs/omap3_beagle_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TARGET_OMAP3_BEAGLE=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="BeagleBoard # "
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x280000
-CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SPL_DM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=1
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS1=y
-CONFIG_LED_STATUS_BIT1=2
-CONFIG_LED_STATUS_STATE1=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=1
-CONFIG_LED_STATUS_GREEN_ENABLE=y
-CONFIG_LED_STATUS_GREEN=2
-CONFIG_LED_STATUS_CMD=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_OMAP3=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_OMAP2PLUS=y
-CONFIG_TWL4030_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="TI"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_USB_ETHER=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_MCS7830=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO_OMAP3=y
-CONFIG_FAT_WRITE=y
-CONFIG_BCH=y
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
deleted file mode 100644
index 7698a90c4e9..00000000000
--- a/include/configs/omap3_beagle.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the TI OMAP3530 Beagle board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/ti_omap3_common.h>
-
-/*
- * We are only ever GP parts and will utilize all of the "downloaded image"
- * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
- */
-#undef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_TEXT_BASE 0x40200000
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* NAND */
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-#define CONFIG_ENV_OVERWRITE
-/* NAND: SPL falcon mode configs */
-#if defined(CONFIG_SPL_OS_BOOT)
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
-#endif /* CONFIG_SPL_OS_BOOT */
-#endif /* CONFIG_NAND */
-
-/* USB EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-
-/* Enable Multi Bus support for I2C */
-#define CONFIG_I2C_MULTI_BUS
-
-/* DSS Support */
-
-/* TWL4030 LED Support */
-
-/* Environment */
-#define CONFIG_ENV_SIZE SZ_128K
-
-#define CONFIG_PREBOOT "usb start"
-
-#define MEM_LAYOUT_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV
-
-#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "setenv mmcdev " #instance "; " \
- "run mmcboot\0"
-#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#if defined(CONFIG_NAND)
-
-#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
- "echo NAND boot disabled: No mtdids and/or mtdparts; " \
- "else " \
- "run nandboot; " \
- "fi\0"
-#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(LEGACY_MMC, legacy_mmc, 0) \
- func(UBIFS, ubifs, 0) \
- func(NAND, nand, 0)
-
-#else /* !CONFIG_NAND */
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(LEGACY_MMC, legacy_mmc, 0)
-
-#endif /* CONFIG_NAND */
-
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- MEM_LAYOUT_ENV_SETTINGS \
- "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_high=0xffffffff\0" \
- "console=ttyO2,115200n8\0" \
- "bootdir=/boot\0" \
- "bootenv=uEnv.txt\0" \
- "bootfile=zImage\0" \
- "bootpart=0:2\0" \
- "bootubivol=rootfs\0" \
- "bootubipart=rootfs\0" \
- "usbtty=cdc_acm\0" \
- "mpurate=auto\0" \
- "buddy=none\0" \
- "camera=none\0" \
- "vram=12M\0" \
- "dvimode=640x480MR-16 at 60\0" \
- "defaultdisplay=dvi\0" \
- "defaultargs=setenv defargs " \
- "mpurate=${mpurate} " \
- "buddy=${buddy} "\
- "camera=${camera} "\
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay}\0" \
- "optargs=\0" \
- "findfdt=" \
- "if test $beaglerev = AxBx; then " \
- "setenv fdtfile omap3-beagle.dtb; fi; " \
- "if test $beaglerev = Cx; then " \
- "setenv fdtfile omap3-beagle.dtb; fi; " \
- "if test $beaglerev = C4; then " \
- "setenv fdtfile omap3-beagle.dtb; fi; " \
- "if test $beaglerev = xMAB; then " \
- "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \
- "if test $beaglerev = xMC; then " \
- "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
- "if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree to use; fi\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "mmcargs=run defaultargs; setenv bootargs console=${console} " \
- "${mtdparts} " \
- "${defargs} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "userbutton_xm=gpio input 4;\0" \
- "userbutton_nonxm=gpio input 7;\0" \
- "userbutton=if gpio input 173; then " \
- "run userbutton_xm; " \
- "else " \
- "run userbutton_nonxm; " \
- "fi;\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
- "env import -t ${loadaddr} ${filesize}\0" \
- "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "if run userbutton; then " \
- "setenv bootenv uEnv.txt;" \
- "else " \
- "setenv bootenv user.txt;" \
- "fi;" \
- "run loadbootenv && run importbootenv; " \
- "run ext4bootenv && run importbootenv; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
- "fi; " \
- "fi\0" \
- "validatefdt=" \
- "if test $beaglerev = xMAB; then " \
- "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
- "setenv fdtfile omap3-beagle-xm.dtb; " \
- "fi; " \
- "fi; \0" \
- "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loaddtb=run validatefdt; ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=run mmcbootenv; " \
- "if run loadimage && run loaddtb; then " \
- "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
- "run mmcargs; " \
- "if test ${bootfile} = uImage; then " \
- "bootm ${loadaddr} - ${fdtaddr}; " \
- "fi; " \
- "if test ${bootfile} = zImage; then " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi; " \
- "fi\0" \
- "nandroot=ubi0:rootfs ubi.mtd=rootfs rw\0" \
- "nandrootfstype=ubifs rootwait\0" \
- "nandargs=run defaultargs; setenv bootargs console=${console} " \
- "${mtdparts} " \
- "${defargs} " \
- "${optargs} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
- "echo Booting uImage from NAND MTD 'kernel' partition ...; " \
- "run nandargs; " \
- "bootm ${loadaddr} - ${fdtaddr}; " \
- "fi\0" \
- "loadramdisk=ext4load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
- "ramdisk=rootfs.ext2.gz.uboot\0" \
- "ramdisk_size=16384\0" \
- "ramroot=/dev/ram rw\0" \
- "ramrootfstype=ext2\0" \
- "ramargs=run defaultargs; setenv bootargs console=${console} " \
- "${mtdparts} " \
- "${defargs} " \
- "${optargs} " \
- "root=${ramroot} ramdisk_size=${ramdisk_size} " \
- "rootfstype=${ramrootfstype}\0" \
- "ramboot=run mmcbootenv; " \
- "if run loadimage && run loaddtb && run loadramdisk; then " \
- "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \
- "run ramargs; " \
- "bootz ${loadaddr} ${rdaddr} ${fdtaddr}; " \
- "fi\0" \
- BOOTENV
-
-#endif /* __CONFIG_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 76/93] arm: Remove helios4 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (74 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 75/93] arm: Remove omap3_beagle board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 77/93] arm: Remove socfpga_socrates board Simon Glass
` (21 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/kobol/helios4/MAINTAINERS | 6 --
board/kobol/helios4/Makefile | 5 -
board/kobol/helios4/README | 46 ---------
board/kobol/helios4/helios4.c | 163 ------------------------------
configs/helios4_defconfig | 60 -----------
include/configs/helios4.h | 172 --------------------------------
6 files changed, 452 deletions(-)
delete mode 100644 board/kobol/helios4/MAINTAINERS
delete mode 100644 board/kobol/helios4/Makefile
delete mode 100644 board/kobol/helios4/README
delete mode 100644 board/kobol/helios4/helios4.c
delete mode 100644 configs/helios4_defconfig
delete mode 100644 include/configs/helios4.h
diff --git a/board/kobol/helios4/MAINTAINERS b/board/kobol/helios4/MAINTAINERS
deleted file mode 100644
index c9610deee76..00000000000
--- a/board/kobol/helios4/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HELIOS4 BOARD
-M: Dennis Gilmore <dgilmore@redhat.com>
-S: Maintained
-F: board/kobol/helios4/
-F: include/configs/helios4.h
-F: configs/helios4_defconfig
diff --git a/board/kobol/helios4/Makefile b/board/kobol/helios4/Makefile
deleted file mode 100644
index 63f0796397c..00000000000
--- a/board/kobol/helios4/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
-
-obj-y := helios4.o
diff --git a/board/kobol/helios4/README b/board/kobol/helios4/README
deleted file mode 100644
index 749f0482782..00000000000
--- a/board/kobol/helios4/README
+++ /dev/null
@@ -1,46 +0,0 @@
-Update from original Marvell U-Boot to mainline U-Boot:
--------------------------------------------------------
-
-Generate the U-Boot image with these commands:
-
-$ make helios4_defconfig
-$ make
-
-The resulting image including the SPL binary with the
-full DDR setup is "u-boot-spl.kwb".
-
-Now all you need to do is copy this image on a SD card.
-For example with this command:
-
-$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
-
-Please use the correct device node for your setup instead
-of "/dev/sdX" here!
-
-Boot selection:
----------------
-
-Before powering up the board, boot selection should be done via the SW1 dip
-switch (0: OFF, 1: ON):
-
- - SPI: 00010
- - SD/eMMC: 00111
- - SATA1: 11100
- - UART: 11110
-
-Boot from UART:
----------------
-
-Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
-to your host.
-
-Set the SW1 DIP switches to UART boot (see above).
-
-Run the following command to initiate U-Boot download:
-
- ./tools/kwboot -p -b u-boot-spl.kwb /dev/ttyUSBX
-
-Use the correct UART device node for /dev/ttyUSBX.
-
-When download finishes start your favorite terminal emulator
-on /dev/ttyUSBX.
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
deleted file mode 100644
index 341678319a4..00000000000
--- a/board/kobol/helios4/helios4.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
- * based on board/solidrun/clearfog/clearfog.c
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
-#include <../serdes/a38x/high_speed_env_spec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK BIT(ETH_PHY_CTRL_POWER_DOWN_BIT)
-
-/*
- * Those values and defines are taken from the Marvell U-Boot version
- * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
- */
-#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
-#define BOARD_GPP_OUT_ENA_MID 0xffffffff
-
-#define BOARD_GPP_OUT_VAL_LOW 0x0
-#define BOARD_GPP_OUT_VAL_MID 0x0
-#define BOARD_GPP_POL_LOW 0x0
-#define BOARD_GPP_POL_MID 0x0
-
-/* IO expander on Marvell GP board includes e.g. fan enabling */
-struct marvell_io_exp {
- u8 addr;
- u8 val;
-};
-
-static struct marvell_io_exp io_exp[] = {
- {6, 0xf9},
- {2, 0x46}, /* Assert reset signals and enable USB3 current limiter */
- {6, 0xb9}
-};
-
-static struct serdes_map board_serdes_map[] = {
- {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
- {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
-};
-
-int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
-{
- *serdes_map_array = board_serdes_map;
- *count = ARRAY_SIZE(board_serdes_map);
- return 0;
-}
-
-/*
- * Define the DDR layout / topology here in the board file. This will
- * be used by the DDR3 init code in the SPL U-Boot version to configure
- * the DDR3 controller.
- */
-static struct mv_ddr_topology_map board_topology_map = {
- DEBUG_LEVEL_ERROR,
- 0x1, /* active interfaces */
- /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
- { { { {0x1, 0, 0, 0},
- {0x1, 0, 0, 0},
- {0x1, 0, 0, 0},
- {0x1, 0, 0, 0},
- {0x1, 0, 0, 0} },
- SPEED_BIN_DDR_1600K, /* speed_bin */
- MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
- MV_DDR_DIE_CAP_8GBIT, /* mem_size */
- DDR_FREQ_800, /* frequency */
- 0, 0, /* cas_wl cas_l */
- MV_DDR_TEMP_LOW, /* temperature */
- MV_DDR_TIM_DEFAULT} }, /* timing */
- BUS_MASK_32BIT_ECC, /* Busses mask */
- MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
- { {0} }, /* raw spd data */
- {0} /* timing parameters */
-};
-
-struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
-{
- /* Return the board topology as defined in the board code */
- return &board_topology_map;
-}
-
-int board_early_init_f(void)
-{
- /* Configure MPP */
- writel(0x11111111, MVEBU_MPP_BASE + 0x00);
- writel(0x11111111, MVEBU_MPP_BASE + 0x04);
- writel(0x10400011, MVEBU_MPP_BASE + 0x08);
- writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
- writel(0x44400002, MVEBU_MPP_BASE + 0x10);
- writel(0x41144004, MVEBU_MPP_BASE + 0x14);
- writel(0x40333333, MVEBU_MPP_BASE + 0x18);
- writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
-
- /* Set GPP Out value */
- writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
- writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
-
- /* Set GPP Polarity */
- writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
- writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
-
- /* Set GPP Out Enable */
- writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
- writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
-
- return 0;
-}
-
-int board_init(void)
-{
- int i;
-
- /* Address of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- /* Init I2C IO expanders */
- for (i = 0; i < ARRAY_SIZE(io_exp); i++) {
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev);
- if (ret) {
- printf("Cannot find I2C: %d\n", ret);
- return 0;
- }
-
- ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1);
- if (ret) {
- printf("Failed to set IO expander via I2C\n");
- return -EIO;
- }
- }
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Helios4\n");
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in controller(s) come first */
- return pci_eth_init(bis);
-}
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
deleted file mode 100644
index e30eb3d41cc..00000000000
--- a/configs/helios4_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_TEXT_BASE=0x00800000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_HELIOS4=y
-CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI_AHCI=y
-CONFIG_DM_I2C=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_MV=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_GIGE=y
-CONFIG_MVNETA=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_SCSI=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
deleted file mode 100644
index ce912ea3241..00000000000
--- a/include/configs/helios4.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
- */
-
-#ifndef _CONFIG_HELIOS4_H
-#define _CONFIG_HELIOS4_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-/*
- * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
- * for DDR ECC byte filling in the SPL before loading the main
- * U-Boot into it.
- */
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-
-/*
- * Commands configuration
- */
-
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_BUS 1
-
-/*
- * SDIO/MMC Card Configuration
- */
-#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
-
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-
-#define CONFIG_ENV_MIN_ENTRIES 128
-
-/*
- * SATA/SCSI/AHCI configuration
- */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 2
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
-/* Environment in MMC */
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SECT_SIZE 0x200
-#define CONFIG_ENV_SIZE 0x10000
-/*
- * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
- * boot image starts @ LBA-0.
- * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
- * image and environment
- */
-#define CONFIG_ENV_OFFSET 0xf0000
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
-
-#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
-/* PCIe support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-/* Keep device tree and initrd in lower memory so the kernel can access them */
-#define RELOCATION_LIMITS_ENV_SETTINGS \
- "fdt_high=0x10000000\0" \
- "initrd_high=0x10000000\0"
-
-/* SPL */
-/*
- * Select the boot device here
- *
- * Currently supported are:
- * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
- * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
- */
-#define SPL_BOOT_SPI_NOR_FLASH 1
-#define SPL_BOOT_SDIO_MMC_CARD 2
-#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
-
-/* Defines for SPL */
-#define CONFIG_SPL_SIZE (140 << 10)
-#define CONFIG_SPL_TEXT_BASE 0x40000030
-#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
-
-#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
-#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-
-#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
-/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-#endif
-
-#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
-/* SPL related MMC defines */
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
-#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
-#endif
-#endif
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Include the common distro boot environment */
-#ifndef CONFIG_SPL_BUILD
-
-#ifdef CONFIG_MMC
-#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
-#else
-#define BOOT_TARGET_DEVICES_MMC(func)
-#endif
-
-#ifdef CONFIG_USB_STORAGE
-#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
-#else
-#define BOOT_TARGET_DEVICES_USB(func)
-#endif
-
-#ifdef CONFIG_SATA
-#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0)
-#else
-#define BOOT_TARGET_DEVICES_SATA(func)
-#endif
-
-#define BOOT_TARGET_DEVICES(func) \
- BOOT_TARGET_DEVICES_MMC(func) \
- BOOT_TARGET_DEVICES_USB(func) \
- BOOT_TARGET_DEVICES_SATA(func) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-
-#define KERNEL_ADDR_R __stringify(0x800000)
-#define FDT_ADDR_R __stringify(0x100000)
-#define RAMDISK_ADDR_R __stringify(0x1800000)
-#define SCRIPT_ADDR_R __stringify(0x200000)
-#define PXEFILE_ADDR_R __stringify(0x300000)
-
-#define LOAD_ADDRESS_ENV_SETTINGS \
- "kernel_addr_r=" KERNEL_ADDR_R "\0" \
- "fdt_addr_r=" FDT_ADDR_R "\0" \
- "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
- "scriptaddr=" SCRIPT_ADDR_R "\0" \
- "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
-
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- RELOCATION_LIMITS_ENV_SETTINGS \
- LOAD_ADDRESS_ENV_SETTINGS \
- "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- "console=ttyS0,115200\0" \
- BOOTENV
-
-#endif /* CONFIG_SPL_BUILD */
-
-#endif /* _CONFIG_HELIOS4_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 77/93] arm: Remove socfpga_socrates board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (75 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 76/93] arm: Remove helios4 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 78/93] arm: Remove socfpga_sr1500 board Simon Glass
` (20 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/altera/cyclone5-socdk/MAINTAINERS | 12 -
board/altera/cyclone5-socdk/Makefile | 7 -
.../altera/cyclone5-socdk/qts/iocsr_config.h | 659 ------------------
.../altera/cyclone5-socdk/qts/pinmux_config.h | 218 ------
board/altera/cyclone5-socdk/qts/pll_config.h | 84 ---
.../altera/cyclone5-socdk/qts/sdram_config.h | 344 ---------
board/altera/cyclone5-socdk/socfpga.c | 5 -
board/ebv/socrates/MAINTAINERS | 6 -
board/ebv/socrates/Makefile | 7 -
board/ebv/socrates/qts/iocsr_config.h | 659 ------------------
board/ebv/socrates/qts/pinmux_config.h | 218 ------
board/ebv/socrates/qts/pll_config.h | 84 ---
board/ebv/socrates/qts/sdram_config.h | 343 ---------
board/ebv/socrates/socfpga.c | 5 -
configs/socfpga_cyclone5_defconfig | 78 ---
configs/socfpga_socrates_defconfig | 78 ---
include/configs/socfpga_cyclone5_socdk.h | 22 -
include/configs/socfpga_socrates.h | 22 -
18 files changed, 2851 deletions(-)
delete mode 100644 board/altera/cyclone5-socdk/MAINTAINERS
delete mode 100644 board/altera/cyclone5-socdk/Makefile
delete mode 100644 board/altera/cyclone5-socdk/qts/iocsr_config.h
delete mode 100644 board/altera/cyclone5-socdk/qts/pinmux_config.h
delete mode 100644 board/altera/cyclone5-socdk/qts/pll_config.h
delete mode 100644 board/altera/cyclone5-socdk/qts/sdram_config.h
delete mode 100644 board/altera/cyclone5-socdk/socfpga.c
delete mode 100644 board/ebv/socrates/MAINTAINERS
delete mode 100644 board/ebv/socrates/Makefile
delete mode 100644 board/ebv/socrates/qts/iocsr_config.h
delete mode 100644 board/ebv/socrates/qts/pinmux_config.h
delete mode 100644 board/ebv/socrates/qts/pll_config.h
delete mode 100644 board/ebv/socrates/qts/sdram_config.h
delete mode 100644 board/ebv/socrates/socfpga.c
delete mode 100644 configs/socfpga_cyclone5_defconfig
delete mode 100644 configs/socfpga_socrates_defconfig
delete mode 100644 include/configs/socfpga_cyclone5_socdk.h
delete mode 100644 include/configs/socfpga_socrates.h
diff --git a/board/altera/cyclone5-socdk/MAINTAINERS b/board/altera/cyclone5-socdk/MAINTAINERS
deleted file mode 100644
index ecf1d04f768..00000000000
--- a/board/altera/cyclone5-socdk/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@kernel.org>
-M: Chin-Liang See <clsee@altera.com>
-S: Maintained
-F: board/altera/cyclone5-socdk/
-F: include/configs/socfpga_cyclone5_socdk.h
-F: configs/socfpga_cyclone5_defconfig
-
-SOCRATES BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: configs/socfpga_socrates_defconfig
diff --git a/board/altera/cyclone5-socdk/Makefile b/board/altera/cyclone5-socdk/Makefile
deleted file mode 100644
index e1c8a6b3c7c..00000000000
--- a/board/altera/cyclone5-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h
deleted file mode 100644
index 81c507b842b..00000000000
--- a/board/altera/cyclone5-socdk/qts/iocsr_config.h
+++ /dev/null
@@ -1,659 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA IOCSR configuration
- */
-
-#ifndef __SOCFPGA_IOCSR_CONFIG_H__
-#define __SOCFPGA_IOCSR_CONFIG_H__
-
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
-
-const unsigned long iocsr_scan_chain0_table[] = {
- 0x00000000,
- 0x00000000,
- 0x0FF00000,
- 0xC0000000,
- 0x0000003F,
- 0x00008000,
- 0x00020080,
- 0x08020000,
- 0x08000000,
- 0x00018020,
- 0x00000000,
- 0x00004000,
- 0x00010040,
- 0x04010000,
- 0x04000000,
- 0x00000010,
- 0x00004010,
- 0x00002000,
- 0x00020000,
- 0x02008000,
- 0x02000000,
- 0x00000008,
- 0x00002008,
- 0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[] = {
- 0x000C0300,
- 0x10040000,
- 0x100000C0,
- 0x00000040,
- 0x00010040,
- 0x00008000,
- 0x00080000,
- 0x18060000,
- 0x18000000,
- 0x00000060,
- 0x00018060,
- 0x00004000,
- 0x00010040,
- 0x10000000,
- 0x04000000,
- 0x00000010,
- 0x00004010,
- 0x00002000,
- 0x06008020,
- 0x02008000,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x00001000,
- 0x00004010,
- 0x01004000,
- 0x01000000,
- 0x00003004,
- 0x00001004,
- 0x00000800,
- 0x00000000,
- 0x00000000,
- 0x00800000,
- 0x00000002,
- 0x00002000,
- 0x00000400,
- 0x00000000,
- 0x00401000,
- 0x00000003,
- 0x00000000,
- 0x00000000,
- 0x00000200,
- 0x00600802,
- 0x00000000,
- 0x80200000,
- 0x80000600,
- 0x00000200,
- 0x00000100,
- 0x00300401,
- 0xC0100400,
- 0x40100000,
- 0x40000300,
- 0x000C0100,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[] = {
- 0x80040100,
- 0x00000000,
- 0x0FF00000,
- 0x00000000,
- 0x0C010040,
- 0x00008000,
- 0x18020080,
- 0x00000000,
- 0x08000000,
- 0x00040020,
- 0x06018060,
- 0x00004000,
- 0x0C010040,
- 0x04010000,
- 0x00000030,
- 0x00000000,
- 0x03004010,
- 0x00002000,
- 0x06008020,
- 0x02008000,
- 0x02000018,
- 0x00006008,
- 0x01802008,
- 0x00001000,
- 0x03004010,
- 0x01004000,
- 0x0100000C,
- 0x00003004,
- 0x00C01004,
- 0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[] = {
- 0x2C420D80,
- 0x082000FF,
- 0x0A804001,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0xE4400000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000070,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00A28,
- 0xA20D0000,
- 0x24906808,
- 0x00A28340,
- 0xD000001A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000FF0,
- 0x72200000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x6A1C0000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x1A870001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000070,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00040,
- 0xA20D0002,
- 0x24906808,
- 0x00A28340,
- 0xD005141A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x000001C1,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x04510680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00600391,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x8341D348,
- 0x821A0124,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x40120800,
- 0x00000070,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F1690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0x00489800,
- 0x001A1A1A,
- 0x085506A0,
- 0x0000E1D4,
- 0x045506A0,
- 0x0000E1D4,
- 0x085506A0,
- 0x8000E1D4,
- 0x00000200,
- 0x00000004,
- 0x04000000,
- 0x00000009,
- 0x00002410,
- 0x00000040,
- 0x41000000,
- 0x00002082,
- 0x00000350,
- 0x000000DA,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x022A8350,
- 0x000070EA,
- 0x86000000,
- 0x08000004,
- 0x00000000,
- 0x00482000,
- 0x21800000,
- 0x00101061,
- 0x021541A8,
- 0x00003875,
- 0x011541A8,
- 0x00003875,
- 0x021541A8,
- 0x20003875,
- 0x00000080,
- 0x00000001,
- 0x41000000,
- 0x00000002,
- 0x00FF0904,
- 0x00000000,
- 0x90400000,
- 0x00000820,
- 0xC0000001,
- 0x38D612AF,
- 0x86F8E38E,
- 0x0A0A78B4,
- 0x000D020A,
- 0x00006800,
- 0x028A4320,
- 0xEC2CB23D,
- 0x8F5D1451,
- 0xA47A88A2,
- 0x0001A0E9,
- 0x00410D00,
- 0x40000068,
- 0x3D000003,
- 0x51EC2CB2,
- 0xA28F5D14,
- 0xE9A47A88,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000540,
- 0x000003A8,
- 0x08AA0D40,
- 0x8001C3A8,
- 0x0000007F,
- 0x00000000,
- 0x00004060,
- 0xE1208000,
- 0x0000001F,
- 0x00004100,
-};
-
-
-#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
deleted file mode 100644
index ec64ae17a16..00000000000
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA PinMux configuration
- */
-
-#ifndef __SOCFPGA_PINMUX_CONFIG_H__
-#define __SOCFPGA_PINMUX_CONFIG_H__
-
-const u8 sys_mgr_init_table[] = {
- 0, /* EMACIO0 */
- 2, /* EMACIO1 */
- 2, /* EMACIO2 */
- 2, /* EMACIO3 */
- 2, /* EMACIO4 */
- 2, /* EMACIO5 */
- 2, /* EMACIO6 */
- 2, /* EMACIO7 */
- 2, /* EMACIO8 */
- 0, /* EMACIO9 */
- 2, /* EMACIO10 */
- 2, /* EMACIO11 */
- 2, /* EMACIO12 */
- 2, /* EMACIO13 */
- 0, /* EMACIO14 */
- 0, /* EMACIO15 */
- 0, /* EMACIO16 */
- 0, /* EMACIO17 */
- 0, /* EMACIO18 */
- 0, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 0, /* FLASHIO4 */
- 0, /* FLASHIO5 */
- 0, /* FLASHIO6 */
- 0, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 3, /* GENERALIO0 */
- 3, /* GENERALIO1 */
- 3, /* GENERALIO2 */
- 3, /* GENERALIO3 */
- 3, /* GENERALIO4 */
- 3, /* GENERALIO5 */
- 3, /* GENERALIO6 */
- 3, /* GENERALIO7 */
- 3, /* GENERALIO8 */
- 3, /* GENERALIO9 */
- 3, /* GENERALIO10 */
- 3, /* GENERALIO11 */
- 3, /* GENERALIO12 */
- 2, /* GENERALIO13 */
- 2, /* GENERALIO14 */
- 3, /* GENERALIO15 */
- 3, /* GENERALIO16 */
- 2, /* GENERALIO17 */
- 2, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 0, /* GENERALIO23 */
- 0, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 2, /* MIXED1IO0 */
- 2, /* MIXED1IO1 */
- 2, /* MIXED1IO2 */
- 2, /* MIXED1IO3 */
- 2, /* MIXED1IO4 */
- 2, /* MIXED1IO5 */
- 2, /* MIXED1IO6 */
- 2, /* MIXED1IO7 */
- 2, /* MIXED1IO8 */
- 2, /* MIXED1IO9 */
- 2, /* MIXED1IO10 */
- 2, /* MIXED1IO11 */
- 2, /* MIXED1IO12 */
- 2, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 3, /* MIXED1IO15 */
- 3, /* MIXED1IO16 */
- 3, /* MIXED1IO17 */
- 3, /* MIXED1IO18 */
- 3, /* MIXED1IO19 */
- 3, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 0, /* MIXED2IO0 */
- 0, /* MIXED2IO1 */
- 0, /* MIXED2IO2 */
- 0, /* MIXED2IO3 */
- 0, /* MIXED2IO4 */
- 0, /* MIXED2IO5 */
- 0, /* MIXED2IO6 */
- 0, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 1, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 1, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 1, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 1, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 1, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 1, /* GPLMUX40 */
- 1, /* GPLMUX41 */
- 1, /* GPLMUX42 */
- 1, /* GPLMUX43 */
- 1, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 1, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 1, /* GPLMUX53 */
- 1, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 1, /* GPLMUX57 */
- 1, /* GPLMUX58 */
- 1, /* GPLMUX59 */
- 1, /* GPLMUX60 */
- 1, /* GPLMUX61 */
- 1, /* GPLMUX62 */
- 1, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 1, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 0, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
deleted file mode 100644
index ae5cfab0cf7..00000000000
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA Clock and PLL configuration
- */
-
-#ifndef __SOCFPGA_PLL_CONFIG_H__
-#define __SOCFPGA_PLL_CONFIG_H__
-
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
-
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
-
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
-
-
-#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
deleted file mode 100644
index 8adbfec11f9..00000000000
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA SDRAM configuration
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE 0x48
-#define RW_MGR_GUARANTEED_READ 0x4B
-#define RW_MGR_GUARANTEED_READ_CONT 0x53
-#define RW_MGR_GUARANTEED_WRITE 0x17
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_IDLE_LOOP1 0x7C
-#define RW_MGR_IDLE_LOOP2 0x7B
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
-#define RW_MGR_INIT_RESET_1_CKE_0 0x73
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_READ_B2B 0x58
-#define RW_MGR_READ_B2B_WAIT1 0x60
-#define RW_MGR_READ_B2B_WAIT2 0x6A
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_SGLE_READ 0x7E
-#define RW_MGR_ZQCL 0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 7
-#define CALIB_VFIFO_OFFSET 5
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 312
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 31
-#define IO_DQS_EN_DELAY_OFFSET 0
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 6
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_MEM_DATA_WIDTH 40
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
-#define TINIT_CNTR0_VAL 132
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TRESET_CNTR0_VAL 132
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] ={
- 0x20700000,
- 0x20780000,
- 0x10080431,
- 0x10080530,
- 0x10090004,
- 0x100a0008,
- 0x100b0000,
- 0x10380400,
- 0x10080449,
- 0x100804c8,
- 0x100a0004,
- 0x10090010,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] ={
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x0,
- 0xa000,
- 0x8000,
- 0x80000,
- 0x80,
- 0x80,
- 0x80,
- 0x80,
- 0xa080,
- 0x8080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c
deleted file mode 100644
index 48bfe329517..00000000000
--- a/board/altera/cyclone5-socdk/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/board/ebv/socrates/MAINTAINERS b/board/ebv/socrates/MAINTAINERS
deleted file mode 100644
index e48236fc8fc..00000000000
--- a/board/ebv/socrates/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SOCRATES BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/ebv/socrates/
-F: include/configs/socfpga_socrates.h
-F: configs/socfpga_socrates_defconfig
diff --git a/board/ebv/socrates/Makefile b/board/ebv/socrates/Makefile
deleted file mode 100644
index e1c8a6b3c7c..00000000000
--- a/board/ebv/socrates/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h
deleted file mode 100644
index 011fa2bac3f..00000000000
--- a/board/ebv/socrates/qts/iocsr_config.h
+++ /dev/null
@@ -1,659 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA IOCSR configuration
- */
-
-#ifndef __SOCFPGA_IOCSR_CONFIG_H__
-#define __SOCFPGA_IOCSR_CONFIG_H__
-
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
-
-const unsigned long iocsr_scan_chain0_table[] = {
- 0x00000000,
- 0x00000000,
- 0x0FF00000,
- 0xC0000000,
- 0x0000003F,
- 0x00008000,
- 0x00004824,
- 0x01209000,
- 0x82400000,
- 0x00018004,
- 0x00000000,
- 0x00004000,
- 0x00002412,
- 0x00904800,
- 0x41200000,
- 0x80000002,
- 0x00000904,
- 0x00002000,
- 0x00001209,
- 0x00482400,
- 0x20900000,
- 0x40000001,
- 0x00000482,
- 0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[] = {
- 0x00009048,
- 0x02412000,
- 0x048000C0,
- 0x00000009,
- 0x00002412,
- 0x00008000,
- 0x00004824,
- 0x01209000,
- 0x82400000,
- 0x00000004,
- 0x00001209,
- 0x00004000,
- 0x00002412,
- 0x00904800,
- 0x41200000,
- 0x80000002,
- 0x00000904,
- 0x00002000,
- 0x06001209,
- 0x00482400,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x80001000,
- 0x00000904,
- 0x00241200,
- 0x90480000,
- 0x20003000,
- 0x00000241,
- 0x00000800,
- 0x00000000,
- 0x00000000,
- 0x48240000,
- 0x90000000,
- 0x00000120,
- 0x00000400,
- 0x00000000,
- 0x00090480,
- 0x00000003,
- 0x00000000,
- 0x00000000,
- 0x90000200,
- 0x00600120,
- 0x00000000,
- 0x12090000,
- 0x24000600,
- 0x00000048,
- 0x48000100,
- 0x00300090,
- 0xC0024120,
- 0x09048000,
- 0x12000300,
- 0x000C0024,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[] = {
- 0x30009048,
- 0x00000000,
- 0x0FF00000,
- 0x00000000,
- 0x0C002412,
- 0x00008000,
- 0x18004824,
- 0x00000000,
- 0x82400000,
- 0x00018004,
- 0x06001209,
- 0x00004000,
- 0x20002412,
- 0x00904800,
- 0x00000030,
- 0x80000000,
- 0x03000904,
- 0x00002000,
- 0x10001209,
- 0x00482400,
- 0x20900000,
- 0x40010001,
- 0x00000482,
- 0x80001000,
- 0x00000904,
- 0x00000000,
- 0x90480000,
- 0x20008000,
- 0x00C00241,
- 0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[] = {
- 0x0CC20D80,
- 0x0C3000FF,
- 0x0A804001,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x20430000,
- 0x0C003001,
- 0x00C00481,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x90218000,
- 0x86001800,
- 0x00600240,
- 0x80090218,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x4810C000,
- 0x43000C00,
- 0x00300120,
- 0xC004810C,
- 0x12043000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000010,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0xC0680A28,
- 0x45034030,
- 0x12481A01,
- 0x80A280D0,
- 0x34030C06,
- 0x01A01450,
- 0x280D0000,
- 0x30C0680A,
- 0x02490340,
- 0xD000001A,
- 0x0680A280,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x18000000,
- 0x01800902,
- 0x00240860,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x20430000,
- 0x0C003001,
- 0x00C00481,
- 0x00000FF0,
- 0x4810C000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x90218000,
- 0x86001800,
- 0x00600240,
- 0x80090218,
- 0x24086001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x4810C000,
- 0x43000C00,
- 0x00300120,
- 0xC004810C,
- 0x12043000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000010,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0xC0680A28,
- 0x49034030,
- 0x12481A02,
- 0x80A280D0,
- 0x34030C06,
- 0x01A00040,
- 0x280D0002,
- 0x30C0680A,
- 0x02490340,
- 0xD00A281A,
- 0x0680A280,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x18000000,
- 0x01800902,
- 0x00240860,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x01000000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x2043090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x18864000,
- 0x49247A06,
- 0xF228A3D5,
- 0xF6D1451E,
- 0x0342E388,
- 0x821A0000,
- 0x0000D000,
- 0x05140680,
- 0xD949247A,
- 0x1EF228A3,
- 0x88F6D145,
- 0x000352E3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x86120800,
- 0x00600240,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x18864000,
- 0x49247A06,
- 0xF3CF23D5,
- 0xF4D1451E,
- 0x034A9248,
- 0x821A038E,
- 0x0000D000,
- 0x00000680,
- 0xD949247A,
- 0x1EF3CF23,
- 0x88F4D145,
- 0x000352E3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x2043090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x18864000,
- 0x49247A06,
- 0xF228A3D9,
- 0xF4D1451E,
- 0x034A9248,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD949247A,
- 0x1EF228A3,
- 0x88F4D145,
- 0x000352E3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00400000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F1690D,
- 0x1A041414,
- 0x00D00000,
- 0x08864000,
- 0x49247A02,
- 0xF3CF23D9,
- 0xF4D1451E,
- 0x0342E388,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD949247A,
- 0x1EF3CF23,
- 0x88F4DE79,
- 0x000342A2,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0x00489800,
- 0x801A1A1A,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x00000004,
- 0x00040000,
- 0x10000000,
- 0x00000000,
- 0x00000040,
- 0x00010000,
- 0x40002000,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x00020000,
- 0x08000000,
- 0x00000000,
- 0x00000020,
- 0x00008000,
- 0x20001000,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x00000001,
- 0x00010000,
- 0x04000000,
- 0x00FF0000,
- 0x00000000,
- 0x00004000,
- 0x00000800,
- 0xC0000001,
- 0x00041419,
- 0x40000000,
- 0x04000816,
- 0x000D0000,
- 0x00006800,
- 0x00000340,
- 0xD000001A,
- 0x06800000,
- 0x00340000,
- 0x0001A000,
- 0x00000D00,
- 0x40000068,
- 0x1A000003,
- 0x00D00000,
- 0x00068000,
- 0x00003400,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x80000008,
- 0x0000007F,
- 0x20000000,
- 0x00000000,
- 0xE0000080,
- 0x0000001F,
- 0x00004000,
-};
-
-
-#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/pinmux_config.h b/board/ebv/socrates/qts/pinmux_config.h
deleted file mode 100644
index 41b634315bf..00000000000
--- a/board/ebv/socrates/qts/pinmux_config.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA PinMux configuration
- */
-
-#ifndef __SOCFPGA_PINMUX_CONFIG_H__
-#define __SOCFPGA_PINMUX_CONFIG_H__
-
-const u8 sys_mgr_init_table[] = {
- 0, /* EMACIO0 */
- 2, /* EMACIO1 */
- 2, /* EMACIO2 */
- 2, /* EMACIO3 */
- 2, /* EMACIO4 */
- 2, /* EMACIO5 */
- 2, /* EMACIO6 */
- 2, /* EMACIO7 */
- 2, /* EMACIO8 */
- 0, /* EMACIO9 */
- 2, /* EMACIO10 */
- 2, /* EMACIO11 */
- 2, /* EMACIO12 */
- 2, /* EMACIO13 */
- 0, /* EMACIO14 */
- 0, /* EMACIO15 */
- 0, /* EMACIO16 */
- 0, /* EMACIO17 */
- 0, /* EMACIO18 */
- 0, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 0, /* FLASHIO4 */
- 0, /* FLASHIO5 */
- 0, /* FLASHIO6 */
- 0, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 0, /* GENERALIO0 */
- 1, /* GENERALIO1 */
- 1, /* GENERALIO2 */
- 1, /* GENERALIO3 */
- 1, /* GENERALIO4 */
- 0, /* GENERALIO5 */
- 0, /* GENERALIO6 */
- 1, /* GENERALIO7 */
- 1, /* GENERALIO8 */
- 3, /* GENERALIO9 */
- 3, /* GENERALIO10 */
- 3, /* GENERALIO11 */
- 3, /* GENERALIO12 */
- 2, /* GENERALIO13 */
- 2, /* GENERALIO14 */
- 1, /* GENERALIO15 */
- 1, /* GENERALIO16 */
- 1, /* GENERALIO17 */
- 1, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 0, /* GENERALIO23 */
- 0, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 2, /* MIXED1IO0 */
- 2, /* MIXED1IO1 */
- 2, /* MIXED1IO2 */
- 2, /* MIXED1IO3 */
- 2, /* MIXED1IO4 */
- 2, /* MIXED1IO5 */
- 2, /* MIXED1IO6 */
- 2, /* MIXED1IO7 */
- 2, /* MIXED1IO8 */
- 2, /* MIXED1IO9 */
- 2, /* MIXED1IO10 */
- 2, /* MIXED1IO11 */
- 2, /* MIXED1IO12 */
- 2, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 3, /* MIXED1IO15 */
- 3, /* MIXED1IO16 */
- 3, /* MIXED1IO17 */
- 3, /* MIXED1IO18 */
- 3, /* MIXED1IO19 */
- 3, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 0, /* MIXED2IO0 */
- 0, /* MIXED2IO1 */
- 0, /* MIXED2IO2 */
- 0, /* MIXED2IO3 */
- 0, /* MIXED2IO4 */
- 0, /* MIXED2IO5 */
- 0, /* MIXED2IO6 */
- 0, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 1, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 1, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 1, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 1, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 1, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 1, /* GPLMUX40 */
- 1, /* GPLMUX41 */
- 1, /* GPLMUX42 */
- 1, /* GPLMUX43 */
- 1, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 1, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 1, /* GPLMUX53 */
- 1, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 1, /* GPLMUX57 */
- 1, /* GPLMUX58 */
- 1, /* GPLMUX59 */
- 1, /* GPLMUX60 */
- 1, /* GPLMUX61 */
- 1, /* GPLMUX62 */
- 1, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 1, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 0, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h
deleted file mode 100644
index 71d3674758f..00000000000
--- a/board/ebv/socrates/qts/pll_config.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA Clock and PLL configuration
- */
-
-#ifndef __SOCFPGA_PLL_CONFIG_H__
-#define __SOCFPGA_PLL_CONFIG_H__
-
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
-
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
-
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
-
-
-#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
deleted file mode 100644
index 2f8465bf77c..00000000000
--- a/board/ebv/socrates/qts/sdram_config.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA SDRAM configuration
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE 0x49
-#define RW_MGR_GUARANTEED_READ 0x4C
-#define RW_MGR_GUARANTEED_READ_CONT 0x54
-#define RW_MGR_GUARANTEED_WRITE 0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_IDLE_LOOP1 0x7B
-#define RW_MGR_IDLE_LOOP2 0x7A
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
-#define RW_MGR_INIT_RESET_1_CKE_0 0x74
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_READ_B2B 0x59
-#define RW_MGR_READ_B2B_WAIT1 0x61
-#define RW_MGR_READ_B2B_WAIT2 0x6B
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_SGLE_READ 0x7D
-#define RW_MGR_ZQCL 0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 7
-#define CALIB_VFIFO_OFFSET 5
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 375
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 31
-#define IO_DQS_EN_DELAY_OFFSET 0
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 4
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_DATA_MASK_WIDTH 4
-#define RW_MGR_MEM_DATA_WIDTH 32
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
-#define TINIT_CNTR0_VAL 82
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TRESET_CNTR0_VAL 82
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] = {
- 0x20700000,
- 0x20780000,
- 0x10080221,
- 0x10080320,
- 0x10090044,
- 0x100a0008,
- 0x100b0000,
- 0x10380400,
- 0x10080241,
- 0x100802c0,
- 0x100a0024,
- 0x10090010,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] = {
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x8000,
- 0xa000,
- 0xc000,
- 0x80000,
- 0x80,
- 0x8080,
- 0xa080,
- 0xc080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c
deleted file mode 100644
index 48bfe329517..00000000000
--- a/board/ebv/socrates/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
deleted file mode 100644
index 8989c4dc96c..00000000000
--- a/configs/socfpga_cyclone5_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="altera"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
deleted file mode 100644
index 05f38cbcd22..00000000000
--- a/configs/socfpga_socrates_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="ebv"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
deleted file mode 100644
index 18da8496ef8..00000000000
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
deleted file mode 100644
index f0d93478912..00000000000
--- a/include/configs/socfpga_socrates.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_SOCFPGA_SOCRATES_H__
-#define __CONFIG_SOCFPGA_SOCRATES_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 78/93] arm: Remove socfpga_sr1500 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (76 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 77/93] arm: Remove socfpga_socrates board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:53 ` [U-Boot] [PATCH 79/93] arm: Remove ls1021aiot_sdcard board Simon Glass
` (19 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/sr1500/MAINTAINERS | 6 -
board/sr1500/Makefile | 5 -
board/sr1500/qts/iocsr_config.h | 659 -------------------------------
board/sr1500/qts/pinmux_config.h | 218 ----------
board/sr1500/qts/pll_config.h | 84 ----
board/sr1500/qts/sdram_config.h | 343 ----------------
board/sr1500/socfpga.c | 26 --
configs/socfpga_sr1500_defconfig | 67 ----
include/configs/socfpga_sr1500.h | 56 ---
9 files changed, 1464 deletions(-)
delete mode 100644 board/sr1500/MAINTAINERS
delete mode 100644 board/sr1500/Makefile
delete mode 100644 board/sr1500/qts/iocsr_config.h
delete mode 100644 board/sr1500/qts/pinmux_config.h
delete mode 100644 board/sr1500/qts/pll_config.h
delete mode 100644 board/sr1500/qts/sdram_config.h
delete mode 100644 board/sr1500/socfpga.c
delete mode 100644 configs/socfpga_sr1500_defconfig
delete mode 100644 include/configs/socfpga_sr1500.h
diff --git a/board/sr1500/MAINTAINERS b/board/sr1500/MAINTAINERS
deleted file mode 100644
index ed013a85243..00000000000
--- a/board/sr1500/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SOCFPGA SR1500 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/sr1500/
-F: include/configs/socfpga_sr1500.h
-F: configs/socfpga_sr1500_defconfig
diff --git a/board/sr1500/Makefile b/board/sr1500/Makefile
deleted file mode 100644
index e499116b676..00000000000
--- a/board/sr1500/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-
-obj-y := socfpga.o
diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h
deleted file mode 100644
index b3b167fa7fc..00000000000
--- a/board/sr1500/qts/iocsr_config.h
+++ /dev/null
@@ -1,659 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA IOCSR configuration
- */
-
-#ifndef __SOCFPGA_IOCSR_CONFIG_H__
-#define __SOCFPGA_IOCSR_CONFIG_H__
-
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
-
-const unsigned long iocsr_scan_chain0_table[] = {
- 0x00100000,
- 0x40000000,
- 0x0FF00000,
- 0xC0000000,
- 0x0000003F,
- 0x00008000,
- 0x000E0180,
- 0x18060000,
- 0x18000000,
- 0x00018060,
- 0x00020000,
- 0x00004000,
- 0x000700C0,
- 0x1C030000,
- 0x0C000000,
- 0x00000070,
- 0x0001C030,
- 0x00002000,
- 0x00018060,
- 0x0E018000,
- 0x06000000,
- 0x00000038,
- 0x0000E018,
- 0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[] = {
- 0x001C0300,
- 0x300C0000,
- 0x300000C0,
- 0x000000C0,
- 0x000300C0,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000000,
- 0x000000E0,
- 0x00018060,
- 0x00004000,
- 0x000300C0,
- 0x1C030000,
- 0x0C000000,
- 0x00000030,
- 0x0000C030,
- 0x00002000,
- 0x06018060,
- 0x06018000,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x00001000,
- 0x0000C030,
- 0x0300C000,
- 0x03000000,
- 0x0000300C,
- 0x0000300C,
- 0x00000800,
- 0x00000000,
- 0x00000000,
- 0x01800000,
- 0x00000006,
- 0x00001806,
- 0x00000400,
- 0x00000000,
- 0x00C03000,
- 0x00000003,
- 0x00000000,
- 0x00000000,
- 0x00000200,
- 0x00601806,
- 0x00000000,
- 0x80600000,
- 0x80000601,
- 0x00000601,
- 0x00000100,
- 0x00300C03,
- 0xC0300C00,
- 0xC0300000,
- 0xC0000300,
- 0x000C0300,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[] = {
- 0x000C0300,
- 0x700C0000,
- 0x0FF00000,
- 0x00000000,
- 0x000700C0,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000000,
- 0x00000060,
- 0x00018060,
- 0x00004000,
- 0x200300C0,
- 0x0C030000,
- 0x0C000000,
- 0x00000070,
- 0x0001C030,
- 0x00002000,
- 0x10018060,
- 0x0E018000,
- 0x06000000,
- 0x00010018,
- 0x0000E018,
- 0x00001000,
- 0x0001C030,
- 0x04000000,
- 0x03000000,
- 0x0000800C,
- 0x00C0300C,
- 0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[] = {
- 0x0C420D80,
- 0x0C3000FF,
- 0x0A804001,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x20430000,
- 0x0C003001,
- 0x00C00481,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x90218000,
- 0x86001800,
- 0x00600240,
- 0x80090218,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x4810C000,
- 0x43000C00,
- 0x00300120,
- 0xC004810C,
- 0x12043000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000010,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0xC0680618,
- 0x45034071,
- 0x0A281A01,
- 0x806180D0,
- 0x34071C06,
- 0x01A034D0,
- 0x180D0000,
- 0x71C06806,
- 0x01450340,
- 0xD000001A,
- 0x0680E380,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x18000000,
- 0x01800902,
- 0x00240860,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x20430000,
- 0x0C003001,
- 0x00C00481,
- 0x00000FF0,
- 0x4810C000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x90218000,
- 0x86001800,
- 0x00600240,
- 0x80090218,
- 0x24086001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x4810C000,
- 0x43000C00,
- 0x00300120,
- 0xC004810C,
- 0x12043000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000010,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0xC0680618,
- 0x45034071,
- 0x0A281A01,
- 0x80E380D0,
- 0x34071C06,
- 0x01A00040,
- 0x180D0002,
- 0x71C06806,
- 0x01450340,
- 0xD00A281A,
- 0x06806180,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x18000000,
- 0x01800902,
- 0x00240860,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x01000000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x2043090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xCB2CA3DD,
- 0xF5D5551E,
- 0x034AD348,
- 0x821A0000,
- 0x0000D000,
- 0x030C0680,
- 0xDD59647A,
- 0x1ECB2CA3,
- 0x48F5D555,
- 0x00035AD3,
- 0x00080000,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x10000000,
- 0x00000010,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040000,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00808000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x86120800,
- 0x00600240,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xCB2CA3DD,
- 0xF5D9651E,
- 0x035AB2C8,
- 0x821A0041,
- 0x0000D000,
- 0x00000680,
- 0xDD59647A,
- 0x1ECB2CA3,
- 0x48F5D965,
- 0x00035AD3,
- 0x00080000,
- 0x00001000,
- 0x00080000,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x10000000,
- 0x00000010,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820004,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040000,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00808000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x2043090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010000,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00202000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xCB2CA3D5,
- 0xF6D9651E,
- 0x035AB2C8,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xDD59647A,
- 0x1ECB2CA3,
- 0x48F5D965,
- 0x00034AD3,
- 0x00080000,
- 0x00001000,
- 0x00080000,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x00000000,
- 0x00000010,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820004,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040000,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00800000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020000,
- 0x00000400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x0000090C,
- 0x00001000,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00400000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F1690D,
- 0x1A041414,
- 0x00D00000,
- 0x04864000,
- 0x69A47A01,
- 0xCB2CA3D5,
- 0xF6D9651E,
- 0x034AD348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD559647A,
- 0x1ECB2CA3,
- 0x48F6D965,
- 0x00034A92,
- 0x00080000,
- 0x00001000,
- 0x00080000,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x00000000,
- 0x00000010,
- 0x0080C000,
- 0x41000000,
- 0x00000002,
- 0x00820004,
- 0x00489800,
- 0x801A1A1A,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x00000004,
- 0x00000200,
- 0x00000004,
- 0x00040000,
- 0x10000000,
- 0x00000000,
- 0x00004000,
- 0x00010000,
- 0x40002080,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x00020000,
- 0x08000000,
- 0x00000008,
- 0x00000020,
- 0x00008000,
- 0x20001040,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x00000001,
- 0x00010000,
- 0x04000000,
- 0x00FF0000,
- 0x00000000,
- 0x00004000,
- 0x00000800,
- 0xC0000001,
- 0x00041419,
- 0x40000000,
- 0x04000816,
- 0x000D0000,
- 0x00006800,
- 0x00000340,
- 0xD000001A,
- 0x06800000,
- 0x00340000,
- 0x0001A000,
- 0x00000D00,
- 0x40000068,
- 0x1A000003,
- 0x00D00000,
- 0x00068000,
- 0x00003400,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x80000008,
- 0x0000007F,
- 0x20000000,
- 0x00000000,
- 0xE0000080,
- 0x0000001F,
- 0x00004000,
-};
-
-
-#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/sr1500/qts/pinmux_config.h b/board/sr1500/qts/pinmux_config.h
deleted file mode 100644
index a8b8dbadeff..00000000000
--- a/board/sr1500/qts/pinmux_config.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA PinMux configuration
- */
-
-#ifndef __SOCFPGA_PINMUX_CONFIG_H__
-#define __SOCFPGA_PINMUX_CONFIG_H__
-
-const u8 sys_mgr_init_table[] = {
- 0, /* EMACIO0 */
- 2, /* EMACIO1 */
- 2, /* EMACIO2 */
- 2, /* EMACIO3 */
- 2, /* EMACIO4 */
- 2, /* EMACIO5 */
- 2, /* EMACIO6 */
- 2, /* EMACIO7 */
- 2, /* EMACIO8 */
- 0, /* EMACIO9 */
- 2, /* EMACIO10 */
- 2, /* EMACIO11 */
- 2, /* EMACIO12 */
- 2, /* EMACIO13 */
- 0, /* EMACIO14 */
- 0, /* EMACIO15 */
- 0, /* EMACIO16 */
- 0, /* EMACIO17 */
- 0, /* EMACIO18 */
- 0, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 0, /* FLASHIO4 */
- 0, /* FLASHIO5 */
- 0, /* FLASHIO6 */
- 0, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 0, /* GENERALIO0 */
- 1, /* GENERALIO1 */
- 1, /* GENERALIO2 */
- 1, /* GENERALIO3 */
- 1, /* GENERALIO4 */
- 0, /* GENERALIO5 */
- 0, /* GENERALIO6 */
- 1, /* GENERALIO7 */
- 1, /* GENERALIO8 */
- 0, /* GENERALIO9 */
- 0, /* GENERALIO10 */
- 0, /* GENERALIO11 */
- 0, /* GENERALIO12 */
- 0, /* GENERALIO13 */
- 0, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
- 0, /* GENERALIO17 */
- 0, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 0, /* GENERALIO23 */
- 0, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 2, /* MIXED1IO0 */
- 2, /* MIXED1IO1 */
- 2, /* MIXED1IO2 */
- 2, /* MIXED1IO3 */
- 2, /* MIXED1IO4 */
- 2, /* MIXED1IO5 */
- 2, /* MIXED1IO6 */
- 2, /* MIXED1IO7 */
- 2, /* MIXED1IO8 */
- 2, /* MIXED1IO9 */
- 2, /* MIXED1IO10 */
- 2, /* MIXED1IO11 */
- 2, /* MIXED1IO12 */
- 2, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 3, /* MIXED1IO15 */
- 3, /* MIXED1IO16 */
- 3, /* MIXED1IO17 */
- 3, /* MIXED1IO18 */
- 3, /* MIXED1IO19 */
- 3, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 0, /* MIXED2IO0 */
- 0, /* MIXED2IO1 */
- 0, /* MIXED2IO2 */
- 0, /* MIXED2IO3 */
- 0, /* MIXED2IO4 */
- 0, /* MIXED2IO5 */
- 0, /* MIXED2IO6 */
- 0, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 0, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 0, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 0, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 0, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 0, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 0, /* GPLMUX40 */
- 0, /* GPLMUX41 */
- 0, /* GPLMUX42 */
- 0, /* GPLMUX43 */
- 0, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 0, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 0, /* GPLMUX53 */
- 0, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 0, /* GPLMUX57 */
- 0, /* GPLMUX58 */
- 0, /* GPLMUX59 */
- 0, /* GPLMUX60 */
- 0, /* GPLMUX61 */
- 0, /* GPLMUX62 */
- 1, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 1, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 0, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h
deleted file mode 100644
index 02f068f7424..00000000000
--- a/board/sr1500/qts/pll_config.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA Clock and PLL configuration
- */
-
-#ifndef __SOCFPGA_PLL_CONFIG_H__
-#define __SOCFPGA_PLL_CONFIG_H__
-
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
-
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
-
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
-
-
-#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
deleted file mode 100644
index d25354bb49c..00000000000
--- a/board/sr1500/qts/sdram_config.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA SDRAM configuration
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE 0x49
-#define RW_MGR_GUARANTEED_READ 0x4C
-#define RW_MGR_GUARANTEED_READ_CONT 0x54
-#define RW_MGR_GUARANTEED_WRITE 0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_IDLE_LOOP1 0x7B
-#define RW_MGR_IDLE_LOOP2 0x7A
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
-#define RW_MGR_INIT_RESET_1_CKE_0 0x74
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_READ_B2B 0x59
-#define RW_MGR_READ_B2B_WAIT1 0x61
-#define RW_MGR_READ_B2B_WAIT2 0x6B
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_SGLE_READ 0x7D
-#define RW_MGR_ZQCL 0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 7
-#define CALIB_VFIFO_OFFSET 5
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 312
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 31
-#define IO_DQS_EN_DELAY_OFFSET 0
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 4
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_DATA_MASK_WIDTH 4
-#define RW_MGR_MEM_DATA_WIDTH 32
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
-#define TINIT_CNTR0_VAL 99
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TRESET_CNTR0_VAL 99
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] = {
- 0x20700000,
- 0x20780000,
- 0x10080421,
- 0x10080520,
- 0x10090044,
- 0x100a0008,
- 0x100b0000,
- 0x10380400,
- 0x10080441,
- 0x100804c0,
- 0x100a0024,
- 0x10090010,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] = {
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x8000,
- 0xa000,
- 0xc000,
- 0x80000,
- 0x80,
- 0x8080,
- 0xa080,
- 0xc080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c
deleted file mode 100644
index c9e32e39603..00000000000
--- a/board/sr1500/socfpga.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-
-int board_early_init_f(void)
-{
- int ret;
-
- /* Reset the Marvell PHY 88E1510 */
- ret = gpio_request(63, "PHY reset");
- if (ret)
- return ret;
-
- gpio_direction_output(63, 0);
- mdelay(1);
- gpio_set_value(63, 1);
- mdelay(10);
-
- return 0;
-}
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
deleted file mode 100644
index 97366cdfff0..00000000000
--- a/configs/socfpga_sr1500_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_SR1500=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
deleted file mode 100644
index 984f1183fdd..00000000000
--- a/include/configs/socfpga_sr1500.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- */
-#ifndef __CONFIG_SOCFPGA_SR1500_H__
-#define __CONFIG_SOCFPGA_SR1500_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
-/* The PHY is autodetected, so no MII PHY address is needed here */
-#define PHY_ANEG_TIMEOUT 8000
-
-/* Environment */
-
-/* Enable SPI NOR flash reset, needed for SPI booting */
-#define CONFIG_SPI_N25Q256A_RESET
-
-/*
- * Bootcounter
- */
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-/* Environment setting for SPI flash */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_OFFSET 0x000e0000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MODE SPI_MODE_3
-#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
-#define CONFIG_SF_DEFAULT_SPEED 100000000
-
-/*
- * The QSPI NOR flash layout on SR1500:
- *
- * 0000.0000 - 0003.ffff: SPL (4 times)
- * 0004.0000 - 000d.ffff: U-Boot
- * 000e.0000 - 000e.ffff: env1
- * 000f.0000 - 000f.ffff: env2
- */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFPGA_SR1500_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 79/93] arm: Remove ls1021aiot_sdcard board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (77 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 78/93] arm: Remove socfpga_sr1500 board Simon Glass
@ 2018-11-19 15:53 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 80/93] arm: Remove socfpga_de10_nano board Simon Glass
` (18 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:53 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/Kconfig | 1 -
board/freescale/ls1021aiot/Kconfig | 17 --
board/freescale/ls1021aiot/MAINTAINERS | 7 -
board/freescale/ls1021aiot/Makefile | 7 -
board/freescale/ls1021aiot/README | 58 ----
board/freescale/ls1021aiot/dcu.c | 46 ----
board/freescale/ls1021aiot/ls1021aiot.c | 249 -----------------
board/freescale/ls1021aiot/ls102xa_pbi.cfg | 14 -
board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | 27 --
board/freescale/ls1021aiot/psci.S | 27 --
configs/ls1021aiot_qspi_defconfig | 39 ---
configs/ls1021aiot_sdcard_defconfig | 44 ---
include/configs/ls1021aiot.h | 251 ------------------
13 files changed, 787 deletions(-)
delete mode 100644 board/freescale/ls1021aiot/Kconfig
delete mode 100644 board/freescale/ls1021aiot/MAINTAINERS
delete mode 100644 board/freescale/ls1021aiot/Makefile
delete mode 100644 board/freescale/ls1021aiot/README
delete mode 100644 board/freescale/ls1021aiot/dcu.c
delete mode 100644 board/freescale/ls1021aiot/ls1021aiot.c
delete mode 100644 board/freescale/ls1021aiot/ls102xa_pbi.cfg
delete mode 100644 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
delete mode 100644 board/freescale/ls1021aiot/psci.S
delete mode 100644 configs/ls1021aiot_qspi_defconfig
delete mode 100644 configs/ls1021aiot_sdcard_defconfig
delete mode 100644 include/configs/ls1021aiot.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 97faf09e916..92b65b5bc40 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1508,7 +1508,6 @@ source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
-source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
deleted file mode 100644
index c6b16063a4a..00000000000
--- a/board/freescale/ls1021aiot/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if TARGET_LS1021AIOT
-
-config SYS_BOARD
- default "ls1021aiot"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "ls102xa"
-
-config SYS_CONFIG_NAME
- default "ls1021aiot"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS
deleted file mode 100644
index 2dab7988eeb..00000000000
--- a/board/freescale/ls1021aiot/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-LS1021AIOT BOARD
-M: Feng Li <feng.li_2@nxp.com>
-S: Maintained
-F: board/freescale/ls1021aiot/
-F: include/configs/ls1021aiot.h
-F: configs/ls1021aiot_sdcard_defconfig
-F: configs/ls1021aiot_qspi_defconfig
diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile
deleted file mode 100644
index bec151fd2ac..00000000000
--- a/board/freescale/ls1021aiot/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2016 Freescale Semiconductor, Inc.
-
-obj-y += ls1021aiot.o
-obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
-obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README
deleted file mode 100644
index 08b0268b9bd..00000000000
--- a/board/freescale/ls1021aiot/README
+++ /dev/null
@@ -1,58 +0,0 @@
-Overview
---------
-The LS1021A-IOT is a Freescale reference board that hosts
-the LS1021A SoC.
-
-LS1021AIOT board Overview
--------------------------
- - DDR Controller
- - Supports 1GB un-buffered DDR3L SDRAM discrete
- devices(32-bit bus) with 4 bit ECC
- - DDR power supplies 1.35V to all devices with
- automatic tracking of VTT
- - Soldered DDR chip
- - Supprot one fixed speed
- - Ethernet
- - Two on-board SGMII 10/100/1G ethernet ports
- - One Gbit Etherent RGMII interface to 4-ports switch
- with 4x 10/100/1000 RJ145 ports
- - CPLD
- - 8-bit registers in CPLD for system configuration
- - connected to IFC_AD[0:7]
- - Power Supplies
- - 12V at 5A DC
- - SDHC
- - SDHC port connects directly to a full 8-bit SD/MMC slot
- - Support for SDIO devices
- - USB
- - Two on-board USB 3.0
- - One on-board USB k22
- - PCIe
- - Two MiniPCIe Solts
- - SATA
- - Support SATA Connector
- - AUDIO
- - AUDIO in and out
- - I/O Expansion
- - Arduino Shield Connector
- - Port0 - CAN/GPIO/Flextimer
- - Port1 - GPIO/CPLD Expansion
- - Port2 - SPI/I2C/UART
-
-Memory map
------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB
-0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB
-0x00_6000_0000 0x00_6000_FFFF CPLD 64K
-0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB
-
-Boot description
------------------
-LS1021A-IOT support two ways of boot:
-Qspi boot and SD boot
-The board doesn't support boot from another
-source without changing any switch/jumper.
diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c
deleted file mode 100644
index 9aeee0eac9a..00000000000
--- a/board/freescale/ls1021aiot/dcu.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * FSL DCU Framebuffer driver
- */
-
-#include <common.h>
-#include <fsl_dcu_fb.h>
-#include "div64.h"
-#include "../common/dcu_sii9022a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned int dcu_set_pixel_clock(unsigned int pixclock)
-{
- unsigned long long div;
-
- div = (unsigned long long)(gd->bus_clk / 1000);
- div *= (unsigned long long)pixclock;
- do_div(div, 1000000000);
-
- return div;
-}
-
-int platform_dcu_init(unsigned int xres, unsigned int yres,
- const char *port,
- struct fb_videomode *dcu_fb_videomode)
-{
- const char *name;
- unsigned int pixel_format;
-
- if (strncmp(port, "twr_lcd", 4) == 0) {
- name = "TWR_LCD_RGB card";
- } else {
- name = "HDMI";
- dcu_set_dvi_encoder(dcu_fb_videomode);
- }
-
- printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
-
- pixel_format = 32;
- fsl_dcu_init(xres, yres, pixel_format);
-
- return 0;
-}
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
deleted file mode 100644
index fb05b55b5c5..00000000000
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ls102xa_stream_id.h>
-
-#include <asm/arch/ls102xa_devdis.h>
-#include <asm/arch/ls102xa_soc.h>
-#include <fsl_csu.h>
-#include <fsl_esdhc.h>
-#include <fsl_immap.h>
-#include <netdev.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <spl.h>
-
-#include <fsl_validate.h>
-#include "../common/sleep.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DDR_SIZE 0x40000000
-
-
-int checkboard(void)
-{
- puts("Board: LS1021AIOT\n");
-
-#ifndef CONFIG_QSPI_BOOT
- struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
- u32 cpldrev;
-
- cpldrev = in_be32(&dcfg->gpporcr1);
-
- printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
- 0xf));
-#endif
- return 0;
-}
-
-void ddrmc_init(void)
-{
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
- u32 temp_sdram_cfg, tmp;
-
- out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
-
- out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
- out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
-
- out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
- out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
- out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
- out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
- out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
- out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
-
- out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
- out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
-
- out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
- out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
-
- out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
-
- out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
-
- out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
- out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
-
- out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
-
- out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
- out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
-
- out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
-
- /* DDR erratum A-009942 */
- tmp = in_be32(&ddr->debug[28]);
- out_be32(&ddr->debug[28], tmp | 0x0070006f);
-
- udelay(500);
-
- temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
-
- out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
-}
-
-int dram_init(void)
-{
-#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- ddrmc_init();
-#endif
-
- gd->ram_size = DDR_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {CONFIG_SYS_FSL_ESDHC_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-
-#endif
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-int board_early_init_f(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-#ifdef CONFIG_TSEC_ENET
- /* clear BD & FR bits for BE BD's and frame data */
- clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
-
-#endif
-
- arch_soc_init();
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
- /* Clear the BSS */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- get_clocks();
-
- preloader_console_init();
-
- dram_init();
-
- /* Allow OCRAM access permission as R/W */
-
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
-
- board_init_r(NULL, 0);
-}
-#endif
-
-int board_init(void)
-{
-#ifndef CONFIG_SYS_FSL_NO_SERDES
- fsl_serdes_init();
-#endif
-
- ls102xa_smmu_stream_id_init();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
-#ifdef CONFIG_FSL_DEVICE_DISABLE
- device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-
-#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
-}
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-
-void flash_write16(u16 val, void *addr)
-{
- u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
-
- __raw_writew(shftval, addr);
-}
-
-u16 flash_read16(void *addr)
-{
- u16 val = __raw_readw(addr);
-
- return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
-}
diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
deleted file mode 100644
index b5ac5e27e9d..00000000000
--- a/board/freescale/ls1021aiot/ls102xa_pbi.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#PBI commands
-
-09570200 ffffffff
-09570158 00000300
-8940007c 21f47300
-
-#Configure Scratch register
-09ee0200 10000000
-#Configure alternate space
-09570158 00001000
-#Flush PBL data
-096100c0 000FFFFF
-
-09ea085c 00502880
diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
deleted file mode 100644
index a1984c713d5..00000000000
--- a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# serdes protocol
-
-#Default with 2 x SGMII (no SATA)
-0608000a 00000000 00000000 00000000
-20000000 08407900 60025a00 21046000
-00000000 00000000 00000000 20038000
-20024800 881b1340 00000000 00000000
-
-#SATA set-up
-#0608000a 00000000 00000000 00000000
-#70000000 08007900 60025a00 21046000
-#00000000 00000000 00000000 20038000
-#20024800 881b1340 00000000 00000000
-
-#HDMI set-up
-#0608000a 00000000 00000000 00000000
-#20000000 08407900 60025a00 21046000
-#00000000 00000000 00000000 20038000
-#00000000 881b1340 00000000 00000000
-
-#QE testing
-#0608000a 00000000 00000000 00000000
-#20000000 08407900 60025a00 21046000
-#00000000 00000000 00000000 00038000
-#20094800 881b1340 00000000 00000000
diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S
deleted file mode 100644
index d0106ba3905..00000000000
--- a/board/freescale/ls1021aiot/psci.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 NXP Semiconductor.
- * Author: Feng Li <feng.li_2@nxp.com>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-#include <asm/armv7.h>
-#include <asm/psci.h>
-
- .pushsection ._secure.text, "ax"
-
- .arch_extension sec
-
- .align 5
-
-.globl psci_system_off
-psci_system_off:
-1: wfi
- b 1b
-
-.globl psci_text_end
-psci_text_end:
- nop
- .popsection
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
deleted file mode 100644
index 0cafb5f2947..00000000000
--- a/configs/ls1021aiot_qspi_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021AIOT=y
-CONFIG_SYS_TEXT_BASE=0x40010000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-CONFIG_MISC_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
deleted file mode 100644
index 0b15353bac5..00000000000
--- a/configs/ls1021aiot_sdcard_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1021AIOT=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
-CONFIG_MISC_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
deleted file mode 100644
index 10dc0c68435..00000000000
--- a/include/configs/ls1021aiot.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-
-#define CONFIG_SYS_FSL_CLK
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-
-/*
- * DDR: 800 MHz ( 1600 MT/s data rate )
- */
-
-#define DDR_SDRAM_CFG 0x470c0008
-#define DDR_CS0_BNDS 0x008000bf
-#define DDR_CS0_CONFIG 0x80014302
-#define DDR_TIMING_CFG_0 0x50550004
-#define DDR_TIMING_CFG_1 0xbcb38c56
-#define DDR_TIMING_CFG_2 0x0040d120
-#define DDR_TIMING_CFG_3 0x010e1000
-#define DDR_TIMING_CFG_4 0x00000001
-#define DDR_TIMING_CFG_5 0x03401400
-#define DDR_SDRAM_CFG_2 0x00401010
-#define DDR_SDRAM_MODE 0x00061c60
-#define DDR_SDRAM_MODE_2 0x00180000
-#define DDR_SDRAM_INTERVAL 0x18600618
-#define DDR_DDR_WRLVL_CNTL 0x8655f605
-#define DDR_DDR_WRLVL_CNTL_2 0x05060607
-#define DDR_DDR_WRLVL_CNTL_3 0x05050505
-#define DDR_DDR_CDR1 0x80040000
-#define DDR_DDR_CDR2 0x00000001
-#define DDR_SDRAM_CLK_CNTL 0x02000000
-#define DDR_DDR_ZQ_CNTL 0x89080600
-#define DDR_CS0_CONFIG_2 0
-#define DDR_SDRAM_CFG_MEM_EN 0x80000000
-#define SDRAM_CFG2_D_INIT 0x00000010
-#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
-#define SDRAM_CFG2_FRC_SR 0x80000000
-#define SDRAM_CFG_BI 0x00000001
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI \
- board/freescale/ls1021aiot/ls102xa_pbi.cfg
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
-
-#define CONFIG_SPL_TEXT_BASE 0x10000000
-#define CONFIG_SPL_MAX_SIZE 0x1a000
-#define CONFIG_SPL_STACK 0x1001d000
-#define CONFIG_SPL_PAD_TO 0x1c000
-
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-#define CONFIG_SPL_BSS_START_ADDR 0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#endif
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-/*
- * I2C
- */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * MMC
- */
-#define CONFIG_CMD_MMC
-
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
-#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
-#endif
-#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
- PCI_DEVICE_ID_FREESCALE_AHCI}
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
-/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SPI_FLASH_SPANSION
-
-/* QSPI */
-#define QSPI0_AMBA_BASE 0x40000000
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_BAR
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
-
-/* DM SPI */
-#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_CMD_SF
-#define CONFIG_DM_SPI_FLASH
-#endif
-
-/*
- * eTSEC
- */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC 1
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-
-#define TSEC1_PHY_ADDR 1
-#define TSEC2_PHY_ADDR 3
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC2"
-
-#define CONFIG_PHY_ATHEROS
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controler 1 */
-#define CONFIG_PCIE2 /* PCIE controler 2 */
-
-#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#define CONFIG_CMD_MII
-
-#define CONFIG_CMDLINE_TAG
-
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 12500000
-
-#define CONFIG_HWCONFIG
-#define HWCONFIG_BUFFER_SIZE 256
-
-#define CONFIG_FSL_DEVICE_DISABLE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
-"initrd_high=0xffffffff\0" \
-"fdt_high=0xffffffff\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MEMINFO
-
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
-#define CONFIG_LS102XA_STREAM_ID
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-/* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
-
-/*
- * Environment
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#endif
-
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-#include <asm/fsl_secure_boot.h>
-
-#endif
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 80/93] arm: Remove socfpga_de10_nano board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (78 preceding siblings ...)
2018-11-19 15:53 ` [U-Boot] [PATCH 79/93] arm: Remove ls1021aiot_sdcard board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 81/93] arm: Remove socfpga_dbm_soc1 board Simon Glass
` (17 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/socfpga_de10_nano_defconfig | 68 -----------------------------
include/configs/socfpga_de10_nano.h | 22 ----------
2 files changed, 90 deletions(-)
delete mode 100644 configs/socfpga_de10_nano_defconfig
delete mode 100644 include/configs/socfpga_de10_nano.h
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
deleted file mode 100644
index c9490d47a49..00000000000
--- a/configs/socfpga_de10_nano_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="terasic"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h
deleted file mode 100644
index 2fcabff8afb..00000000000
--- a/include/configs/socfpga_de10_nano.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017, Intel Corporation
- */
-#ifndef __CONFIG_TERASIC_DE10_H__
-#define __CONFIG_TERASIC_DE10_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_TERASIC_DE10_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 81/93] arm: Remove socfpga_dbm_soc1 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (79 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 80/93] arm: Remove socfpga_de10_nano board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 21:17 ` Marek Vasut
2018-11-19 15:54 ` [U-Boot] [PATCH 82/93] arm: Remove socfpga_de1_soc board Simon Glass
` (16 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/socfpga_dbm_soc1_defconfig | 70 ----------------------
include/configs/socfpga_dbm_soc1.h | 95 ------------------------------
2 files changed, 165 deletions(-)
delete mode 100644 configs/socfpga_dbm_soc1_defconfig
delete mode 100644 include/configs/socfpga_dbm_soc1.h
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
deleted file mode 100644
index b6f4f8a3dd2..00000000000
--- a/configs/socfpga_dbm_soc1_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="devboards"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h
deleted file mode 100644
index b36d7e56fb1..00000000000
--- a/include/configs/socfpga_dbm_soc1.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_DEVBOARDS_DBM_SOC1_H__
-#define __CONFIG_DEVBOARDS_DBM_SOC1_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-
-/* Booting Linux */
-#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_PREBOOT "run try_bootscript"
-#define CONFIG_BOOTCOMMAND "run mmc_mmc"
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Environment is in MMC */
-#define CONFIG_ENV_OVERWRITE
-
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "consdev=ttyS0\0" \
- "baudrate=115200\0" \
- "bootscript=boot.scr\0" \
- "bootdev=/dev/mmcblk0p2\0" \
- "rootdev=/dev/mmcblk0p3\0" \
- "netdev=eth0\0" \
- "hostname=dbm_soc1\0" \
- "kernel_addr_r=0x10000000\0" \
- "dfu_alt_info=mmc raw 0 3867148288\0" \
- "update_filename=u-boot-with-spl.sfp\0" \
- "update_sd_offset=0x800\0" \
- "update_sd=" /* Update the SD firmware partition */ \
- "if mmc rescan ; then " \
- "if tftp ${update_filename} ; then " \
- "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
- "setexpr fw_sz ${fw_sz} + 1 ; " \
- "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \
- "fi ; " \
- "fi\0" \
- "fpga_filename=output_file.rbf\0" \
- "load_fpga=" /* Load FPGA bitstream */ \
- "if tftp ${fpga_filename} ; then " \
- "fpga load 0 $loadaddr $filesize ; " \
- "bridge enable ; " \
- "fi\0" \
- "addcons=" \
- "setenv bootargs ${bootargs} " \
- "console=${consdev},${baudrate}\0" \
- "addip=" \
- "setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=" \
- "setenv bootargs ${bootargs} ${miscargs}\0" \
- "addargs=run addcons addmisc\0" \
- "mmcload=" \
- "mmc rescan ; " \
- "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
- "netload=" \
- "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
- "miscargs=nohlt panic=1\0" \
- "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
- "nfsargs=" \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
- "mmc_mmc=" \
- "run mmcload mmcargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "mmc_nfs=" \
- "run mmcload nfsargs addip addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "net_mmc=" \
- "run netload mmcargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "net_nfs=" \
- "run netload nfsargs addip addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "try_bootscript=" \
- "mmc rescan;" \
- "if test -e mmc 0:2 ${bootscript} ; then " \
- "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
- "then ; " \
- "echo Running bootscript... ; " \
- "source ${kernel_addr_r} ; " \
- "fi ; " \
- "fi\0"
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_DEVBOARDS_DBM_SOC1_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 82/93] arm: Remove socfpga_de1_soc board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (80 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 81/93] arm: Remove socfpga_dbm_soc1 board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 83/93] arm: Remove socfpga_sockit board Simon Glass
` (15 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/socfpga_de1_soc_defconfig | 60 -------------------------------
include/configs/socfpga_de1_soc.h | 22 ------------
2 files changed, 82 deletions(-)
delete mode 100644 configs/socfpga_de1_soc_defconfig
delete mode 100644 include/configs/socfpga_de1_soc.h
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
deleted file mode 100644
index b6c8e6c84d6..00000000000
--- a/configs/socfpga_de1_soc_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USE_TINY_PRINTF=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h
deleted file mode 100644
index f37099c58f8..00000000000
--- a/include/configs/socfpga_de1_soc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_TERASIC_DE1_SOC_H__
-#define __CONFIG_TERASIC_DE1_SOC_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_TERASIC_DE1_SOC_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 83/93] arm: Remove socfpga_sockit board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (81 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 82/93] arm: Remove socfpga_de1_soc board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 20:54 ` Marek Vasut
2018-11-19 15:54 ` [U-Boot] [PATCH 84/93] arm: Remove dns325 board Simon Glass
` (14 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/socfpga_sockit_defconfig | 78 --------------------------------
include/configs/socfpga_sockit.h | 22 ---------
2 files changed, 100 deletions(-)
delete mode 100644 configs/socfpga_sockit_defconfig
delete mode 100644 include/configs/socfpga_sockit.h
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
deleted file mode 100644
index 66f7733ee86..00000000000
--- a/configs/socfpga_sockit_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="terasic"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
deleted file mode 100644
index 3a7f354914a..00000000000
--- a/include/configs/socfpga_sockit.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_TERASIC_SOCKIT_H__
-#define __CONFIG_TERASIC_SOCKIT_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_TERASIC_SOCKIT_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 84/93] arm: Remove dns325 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (82 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 83/93] arm: Remove socfpga_sockit board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 85/93] arm: Remove socfpga_is1 board Simon Glass
` (13 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-kirkwood/Kconfig | 1 -
board/d-link/dns325/Kconfig | 12 --
board/d-link/dns325/MAINTAINERS | 6 -
board/d-link/dns325/Makefile | 11 --
board/d-link/dns325/dns325.c | 131 ---------------------
board/d-link/dns325/dns325.h | 31 -----
board/d-link/dns325/kwbimage.cfg | 190 -------------------------------
configs/dns325_defconfig | 41 -------
include/configs/dns325.h | 118 -------------------
9 files changed, 541 deletions(-)
delete mode 100644 board/d-link/dns325/Kconfig
delete mode 100644 board/d-link/dns325/MAINTAINERS
delete mode 100644 board/d-link/dns325/Makefile
delete mode 100644 board/d-link/dns325/dns325.c
delete mode 100644 board/d-link/dns325/dns325.h
delete mode 100644 board/d-link/dns325/kwbimage.cfg
delete mode 100644 configs/dns325_defconfig
delete mode 100644 include/configs/dns325.h
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 9261b606bb4..e592d07d797 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -72,7 +72,6 @@ config SYS_SOC
source "board/Marvell/openrd/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
-source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
diff --git a/board/d-link/dns325/Kconfig b/board/d-link/dns325/Kconfig
deleted file mode 100644
index f6341ada607..00000000000
--- a/board/d-link/dns325/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DNS325
-
-config SYS_BOARD
- default "dns325"
-
-config SYS_VENDOR
- default "d-link"
-
-config SYS_CONFIG_NAME
- default "dns325"
-
-endif
diff --git a/board/d-link/dns325/MAINTAINERS b/board/d-link/dns325/MAINTAINERS
deleted file mode 100644
index a37b7990e08..00000000000
--- a/board/d-link/dns325/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DNS325 BOARD
-M: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
-S: Maintained
-F: board/d-link/dns325/
-F: include/configs/dns325.h
-F: configs/dns325_defconfig
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dns325/Makefile
deleted file mode 100644
index e78f6d9c337..00000000000
--- a/board/d-link/dns325/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011
-# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-
-obj-y := dns325.o
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c
deleted file mode 100644
index a1d987bedaa..00000000000
--- a/board/d-link/dns325/dns325.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011
- * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-#include "dns325.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* Gpio configuration */
- mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
- DNS325_OE_LOW, DNS325_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_SATA1_ACTn, /* sata1(left) status led */
- MPP21_SATA0_ACTn, /* sata0(right) status led */
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO, /* power off out */
- MPP25_GPIO,
- MPP26_GPIO, /* power led */
- MPP27_GPIO, /* sata0(right) error led */
- MPP28_GPIO, /* sata1(left) error led */
- MPP29_GPIO, /* usb error led */
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO, /* power key */
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO, /* enable sata 0 */
- MPP40_GPIO, /* enable sata 1 */
- MPP41_GPIO, /* hdd0 present */
- MPP42_GPIO, /* hdd1 present */
- MPP43_GPIO, /* usb status led */
- MPP44_GPIO, /* fan status */
- MPP45_GPIO, /* fan high speed */
- MPP46_GPIO, /* fan low speed */
- MPP47_GPIO, /* usb umount */
- MPP48_GPIO, /* factory reset */
- MPP49_GPIO, /* thermal sensor */
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
-
- kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
- return 0;
-}
-
-int board_init(void)
-{
- /* Boot parameters address */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..(%s) could not read PHY dev address\n", __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- debug("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dns325/dns325.h
deleted file mode 100644
index 62ced6814e4..00000000000
--- a/board/d-link/dns325/dns325.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __DNS325_H
-#define __DNS325_H
-
-/* GPIO configuration */
-#define DNS325_OE_LOW 0x00000000
-#define DNS325_OE_HIGH 0x00039604
-#define DNS325_OE_VAL_LOW 0x38000000 /* disable leds */
-#define DNS325_OE_VAL_HIGH 0x00000800 /* disable leds */
-
-#define DNS325_GPIO_LED_POWER 26
-#define DNS325_GPIO_SATA0_EN 39
-#define DNS325_GPIO_SATA1_EN 40
-
-/* PHY related */
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DNS325_H */
diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg
deleted file mode 100644
index dc2a34513e9..00000000000
--- a/board/d-link/dns325/kwbimage.cfg
+++ /dev/null
@@ -1,190 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011
-# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30, 3120 DDR2 clks refresh rate
-# bit23-14: 0 required
-# bit24: 1, enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: 0 required
-# bit31-30: 0b01 required
-
-DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
-# bit3-0: 0 required
-# bit4: 0, addr/cmd in smame cycle
-# bit5: 0, clk is driven during self refresh, we don't care for APX
-# bit6: 0, use recommended falling edge of clk for addr/cmd
-# bit11-7: 0 required
-# bit12: 1 required
-# bit13: 1 required
-# bit14: 0, input buffer always powered up
-# bit17-15: 0 required
-# bit18: 1, cpu lock transaction enabled
-# bit19: 0 required
-# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0, no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
-# bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
-# bit7-4: 5, 6 cycle tRCD
-# bit11-8: 4, 5 cyle tRP
-# bit15-12: 5, 6 cyle tWR
-# bit19-16: 2, 3 cyle tWTR
-# bit20: 1, 18 cycle tRAS (tRAS[4])
-# bit23-21: 0 required
-# bit27-24: 2, 3 cycle tRRD
-# bit31-28: 2, 3 cyle tRTP
-
-DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
-# bit6-0: 0x33, 33 cycle tRFC
-# bit8-7: 0, 1 cycle tR2R
-# bit10-9: 0, 1 cyle tR2W
-# bit12-11: 1, 2 cylce tW2W
-# bit31-13: 0 required
-
-DATA 0xFFD01410 0x0000000c # DDR Address Control
-# bit1-0: 0, Cs0width=x8
-# bit3-2: 3, Cs0size=1Gb
-# bit5-4: 0, Cs1width=nonexistent
-# bit7-6: 0, Cs1size=nonexistent
-# bit9-8: 0, Cs2width=nonexistent
-# bit11-10: 0, Cs2size=nonexistent
-# bit13-12: 0, Cs3width=nonexistent
-# bit15-14: 0, Cs3size=nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OPEn=OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0, Cmd=Normal SDRAM Mode
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, Burst Length (2 required)
-# bit3: 0, Burst Type (0 required)
-# bit6-4: 5, CAS Latency (CL) 5
-# bit7: 0, (Test Mode) Normal operation
-# bit8: 0, (Reset DLL) Normal operation
-# bit11-9: 0, Write recovery for auto-precharge (3 required ??)
-# bit12: 0, Fast Active power down exit time (0 required)
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DRAM DLL enabled
-# bit1: 0, DRAM drive strength normal
-# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
-# bit5-3: 0 required
-# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
-# bit9-7: 0 required
-# bit10: 0, differential DQS enabled
-# bit11: 0 required
-# bit12: 0, DRAM output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 0x7 required
-# bit3: 1, MBUS Burst Chop disabled
-# bit6-4: 0x7 required
-# bit7: 0 required
-# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9: 0, no half clock cycle addition to dataout
-# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11: 0, 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 0xf required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
-# bit3-0: 0 required
-# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
-# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
-# bit31-20: 0 required
-
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
-# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
-# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
-# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
-# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
-# bit31-16: 0 required
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 0x0, CS0 hit selected
-# bit23-4: 0xfffff required
-# bit31-24: 0x0f, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 1, CS1 hit selected
-# bit23-4: 0xfffff required
-# bit31-24: 0x0f, Size (i.e. 256MB)
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
-# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
-# bit15-8: 0 required
-# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
-# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
-# bit31-24: 0 required
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
-# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
-# bit31-4 0 required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
-# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
-# bit9-8: 0, Internal ODT assertion is controlled by fiels
-# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
-# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT enabled
-# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
-# bit20-16: 0, Pad N channel driving strength for ODT
-# bit25-21: 0, Pad P channel driving strength for ODT
-# bit31-26: 0 required
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-# bit0: 1, enable DDR init upon this register write
-# bit31-1: 0, required
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
deleted file mode 100644
index 5a766981603..00000000000
--- a/configs/dns325_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_DNS325=y
-CONFIG_IDENT_STRING="\nD-Link DNS-325"
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-CONFIG_CONSOLE_MUX=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
deleted file mode 100644
index f72ee90ab57..00000000000
--- a/include/configs/dns325.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef _CONFIG_DNS325_H
-#define _CONFIG_DNS325_H
-
-/*
- * Machine number definition
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_DNS325
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-#define CONFIG_KW88F6281 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Remove or override few declarations from mv-common.h */
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_NETCONSOLE
-#endif
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif
-
-/*
- * Enable GPI0 support
- */
-#define CONFIG_KIRKWOOD_GPIO
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
-#endif
-
-#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
-#define CONFIG_ENV_ADDR 0xe0000
-#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */
-
-/*
- * Default environment variables
- */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "loadaddr=0x800000\0" \
- "autoload=no\0" \
- "console=ttyS0,115200\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT \
- "optargs=\0" \
- "bootenv=uEnv.txt\0" \
- "importbootenv=echo Importing environment ...; " \
- "env import -t ${loadaddr} ${filesize}\0" \
- "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \
- "setbootargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "${mtdparts} " \
- "root=${bootenvroot} " \
- "rootfstype=${bootenvrootfstype}\0" \
- "subbootcmd=run setbootargs; " \
- "if run bootenvloadimage; then " \
- "bootm ${loadaddr};" \
- "fi;\0" \
- "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \
- "nandrootfstype=ubifs\0" \
- "nandloadimage=nand read ${loadaddr} kernel\0" \
- "setnandbootenv=echo Booting from nand ...; " \
- "setenv bootenvroot ${nandroot}; " \
- "setenv bootenvrootfstype ${nandrootfstype}; " \
- "setenv bootenvloadimage ${nandloadimage}\0"
-
-#define CONFIG_BOOTCOMMAND \
- "if test -n ${bootenv} && usb start; then " \
- "if run loadbootenv; then " \
- "echo Loaded environment ${bootenv} from usb;" \
- "run importbootenv;" \
- "fi;" \
- "if test -n ${bootenvcmd}; then " \
- "echo Running bootenvcmd ...;" \
- "run bootenvcmd;" \
- "fi;" \
- "fi;" \
- "run setnandbootenv subbootcmd;"
-
-#endif /* _CONFIG_DNS325_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 85/93] arm: Remove socfpga_is1 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (83 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 84/93] arm: Remove dns325 board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 86/93] arm: Remove brppt1_mmc board Simon Glass
` (12 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/is1/MAINTAINERS | 6 -
board/is1/Makefile | 5 -
board/is1/qts/iocsr_config.h | 659 ----------------------------------
board/is1/qts/pinmux_config.h | 218 -----------
board/is1/qts/pll_config.h | 84 -----
board/is1/qts/sdram_config.h | 343 ------------------
board/is1/socfpga.c | 4 -
configs/socfpga_is1_defconfig | 60 ----
include/configs/socfpga_is1.h | 34 --
9 files changed, 1413 deletions(-)
delete mode 100644 board/is1/MAINTAINERS
delete mode 100644 board/is1/Makefile
delete mode 100644 board/is1/qts/iocsr_config.h
delete mode 100644 board/is1/qts/pinmux_config.h
delete mode 100644 board/is1/qts/pll_config.h
delete mode 100644 board/is1/qts/sdram_config.h
delete mode 100644 board/is1/socfpga.c
delete mode 100644 configs/socfpga_is1_defconfig
delete mode 100644 include/configs/socfpga_is1.h
diff --git a/board/is1/MAINTAINERS b/board/is1/MAINTAINERS
deleted file mode 100644
index a737e13f834..00000000000
--- a/board/is1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SOCFPGA IS1 BOARD
-M: Pavel Machek <pavel@denx.de>
-S: Maintained
-F: board/is1/
-F: include/configs/socfpga_is1.h
-F: configs/socfpga_is1_defconfig
diff --git a/board/is1/Makefile b/board/is1/Makefile
deleted file mode 100644
index e499116b676..00000000000
--- a/board/is1/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-
-obj-y := socfpga.o
diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h
deleted file mode 100644
index 1d2774aa41a..00000000000
--- a/board/is1/qts/iocsr_config.h
+++ /dev/null
@@ -1,659 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA IOCSR configuration
- */
-
-#ifndef __SOCFPGA_IOCSR_CONFIG_H__
-#define __SOCFPGA_IOCSR_CONFIG_H__
-
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
-
-const unsigned long iocsr_scan_chain0_table[] = {
- 0x00000000,
- 0x00000000,
- 0x0FF00000,
- 0xC0000000,
- 0x0000003F,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000000,
- 0x00018060,
- 0x00000000,
- 0x00004000,
- 0x000300C0,
- 0x0C030000,
- 0x0C000000,
- 0x00000030,
- 0x0000C030,
- 0x00002000,
- 0x00020000,
- 0x06018000,
- 0x06000000,
- 0x00000018,
- 0x00006018,
- 0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[] = {
- 0x000C0300,
- 0x300C0000,
- 0x30000000,
- 0x000000C0,
- 0x000300C0,
- 0x80008000,
- 0x0000007F,
- 0x0001FE00,
- 0x07F80000,
- 0xE0000000,
- 0x0000001F,
- 0x00004000,
- 0x000300C0,
- 0x0C030000,
- 0x0C000000,
- 0x00000030,
- 0x0000C030,
- 0x00002000,
- 0x06018060,
- 0x00007F80,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x00001000,
- 0x0000C030,
- 0x0300C000,
- 0x03000000,
- 0x0000300C,
- 0x0000300C,
- 0x00000800,
- 0x00000000,
- 0x00000000,
- 0x01800000,
- 0x00000006,
- 0x00601806,
- 0x00000400,
- 0x00000000,
- 0x00C03000,
- 0x00000003,
- 0x00000000,
- 0x00000000,
- 0x00000200,
- 0x00601806,
- 0x00000000,
- 0x80600000,
- 0x80000601,
- 0x00000601,
- 0x00000100,
- 0x00300C03,
- 0xC0300C00,
- 0xC0300000,
- 0xC0000300,
- 0x000C0300,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[] = {
- 0x00100000,
- 0x300C0000,
- 0x0FF00000,
- 0x00000000,
- 0x00040000,
- 0x00008000,
- 0x00080000,
- 0x00000000,
- 0x18000000,
- 0x00000060,
- 0x06018060,
- 0x00004000,
- 0x0C0300C0,
- 0x0C030000,
- 0x0C000000,
- 0x00000030,
- 0x0000C030,
- 0x00002000,
- 0x06018060,
- 0x06018000,
- 0x06000018,
- 0x00006018,
- 0x01806018,
- 0x00001000,
- 0x0300C030,
- 0x0300C000,
- 0x0300000C,
- 0x0000300C,
- 0x00C0300C,
- 0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[] = {
- 0x0C420D80,
- 0x082000FF,
- 0x08024001,
- 0x00100000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x00000000,
- 0x00000010,
- 0x00C00722,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0xE4400000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000010,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0xC0680A28,
- 0x41034030,
- 0x02081A00,
- 0x80A280D0,
- 0x34051406,
- 0x01A02490,
- 0x280D0000,
- 0x30C0680A,
- 0x00000340,
- 0xD000001A,
- 0x0680A280,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000FF0,
- 0x72200000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x6A1C0000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x1A870001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000010,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0xC0680A28,
- 0x49034030,
- 0x12481A02,
- 0x80A280D0,
- 0x34030C06,
- 0x01A00040,
- 0x280D0002,
- 0x30C0680A,
- 0x02490340,
- 0xD012481A,
- 0x0680A280,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x01000000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x69A47A05,
- 0xF228A3D5,
- 0xF6D1451E,
- 0x0352D348,
- 0x821A0000,
- 0x0000D000,
- 0x05140680,
- 0xD569A47A,
- 0x1E8A28A3,
- 0x48F6D145,
- 0x00035292,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x0000FF00,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0xAA0D4000,
- 0x01C3A800,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0xF8482000,
- 0x00000007,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D400,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x2A835000,
- 0x0070EA00,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00600391,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC0D5F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x04864000,
- 0x69A47A01,
- 0x8A28A3D5,
- 0xF4D1451E,
- 0x0352D348,
- 0x821A028A,
- 0x0000D000,
- 0x00000680,
- 0xD559647A,
- 0x1E8A28A3,
- 0x48F6D145,
- 0x00034AD3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875001,
- 0x0000FF00,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0x00040100,
- 0x00000800,
- 0x00040100,
- 0x00000800,
- 0x00040100,
- 0x00000800,
- 0x00040100,
- 0x00000800,
- 0x08000000,
- 0x00000000,
- 0xF8000020,
- 0x00000007,
- 0x02000000,
- 0x00400000,
- 0x00020080,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x00020080,
- 0x00000400,
- 0x04000000,
- 0xC8800000,
- 0x00003001,
- 0x00004000,
- 0x01000000,
- 0x00200000,
- 0x00010040,
- 0x00000200,
- 0x00010040,
- 0x00000200,
- 0x00010040,
- 0x00000200,
- 0x00010040,
- 0x00000200,
- 0x02000000,
- 0x00000000,
- 0xFE000008,
- 0x00000001,
- 0x00800000,
- 0x00100000,
- 0x00000200,
- 0x08283380,
- 0x00000000,
- 0x00122C80,
- 0x1A000008,
- 0x00D00000,
- 0x00068000,
- 0x00003400,
- 0x000001A0,
- 0x6800000D,
- 0x03400000,
- 0x001A0000,
- 0x0000D000,
- 0x00000680,
- 0xA0000034,
- 0x0D000001,
- 0x00680000,
- 0x00034000,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x0000FF00,
- 0x00000000,
- 0x00000040,
- 0x00010000,
- 0x00003FC0,
- 0x00800000,
- 0x00040100,
- 0x00000800,
- 0x00040100,
- 0x00000800,
- 0x00040100,
- 0x00000800,
- 0x00040100,
- 0x00000800,
- 0x08000000,
- 0x00000000,
- 0xF8000020,
- 0x00000007,
- 0x02000000,
- 0x00400000,
- 0x00020080,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x04000000,
- 0x00FF0000,
- 0x00000000,
- 0x00004000,
- 0x01000000,
- 0x00200000,
- 0x00010040,
- 0x00000200,
- 0x00010040,
- 0x00000200,
- 0x00010040,
- 0x00000200,
- 0x00010040,
- 0x00000200,
- 0x02000000,
- 0x00000004,
- 0x00001008,
- 0x00402000,
- 0x00800000,
- 0x00100001,
- 0x00000200,
- 0x08283380,
- 0x00000000,
- 0x00102C80,
- 0x1A000008,
- 0x00D00000,
- 0x00068000,
- 0x00003400,
- 0x000001A0,
- 0x6800000D,
- 0x03400000,
- 0x001A0000,
- 0x0000D000,
- 0x00000680,
- 0xA0000034,
- 0x0D000001,
- 0x00680000,
- 0x00034000,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x0000FF00,
- 0x00000000,
- 0x00000040,
- 0x00010000,
- 0x00003FC0,
- 0x00800000,
- 0x00489800,
- 0x9E1A0000,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0x80000004,
- 0x00000200,
- 0xC0000004,
- 0x0000003F,
- 0x0000FF00,
- 0x03FC0000,
- 0xF0000000,
- 0x0000000F,
- 0x40002000,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0xE0000002,
- 0x0000001F,
- 0x00007F80,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x20001000,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0x20000001,
- 0x00000080,
- 0xF0000001,
- 0x0000000F,
- 0x00003FC0,
- 0x00FF0000,
- 0xFC000000,
- 0x00000003,
- 0x00000800,
- 0xC0000001,
- 0x00041419,
- 0x40000000,
- 0x04000816,
- 0x000D0000,
- 0x00006800,
- 0x00000340,
- 0xD000001A,
- 0x06800000,
- 0x00340000,
- 0x0001A000,
- 0x00000D00,
- 0x40000068,
- 0x1A000003,
- 0x00D00000,
- 0x00068000,
- 0x00003400,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x80000008,
- 0x0000007F,
- 0x0001FE00,
- 0x07F80000,
- 0xE0000000,
- 0x0000001F,
- 0x00004000,
-};
-
-
-#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/is1/qts/pinmux_config.h b/board/is1/qts/pinmux_config.h
deleted file mode 100644
index bf79975b918..00000000000
--- a/board/is1/qts/pinmux_config.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA PinMux configuration
- */
-
-#ifndef __SOCFPGA_PINMUX_CONFIG_H__
-#define __SOCFPGA_PINMUX_CONFIG_H__
-
-const u8 sys_mgr_init_table[] = {
- 0, /* EMACIO0 */
- 2, /* EMACIO1 */
- 2, /* EMACIO2 */
- 2, /* EMACIO3 */
- 2, /* EMACIO4 */
- 2, /* EMACIO5 */
- 2, /* EMACIO6 */
- 2, /* EMACIO7 */
- 2, /* EMACIO8 */
- 0, /* EMACIO9 */
- 2, /* EMACIO10 */
- 2, /* EMACIO11 */
- 2, /* EMACIO12 */
- 2, /* EMACIO13 */
- 0, /* EMACIO14 */
- 0, /* EMACIO15 */
- 0, /* EMACIO16 */
- 0, /* EMACIO17 */
- 0, /* EMACIO18 */
- 0, /* EMACIO19 */
- 0, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 0, /* FLASHIO2 */
- 0, /* FLASHIO3 */
- 0, /* FLASHIO4 */
- 0, /* FLASHIO5 */
- 0, /* FLASHIO6 */
- 0, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 0, /* FLASHIO9 */
- 0, /* FLASHIO10 */
- 0, /* FLASHIO11 */
- 3, /* GENERALIO0 */
- 3, /* GENERALIO1 */
- 3, /* GENERALIO2 */
- 3, /* GENERALIO3 */
- 3, /* GENERALIO4 */
- 3, /* GENERALIO5 */
- 3, /* GENERALIO6 */
- 3, /* GENERALIO7 */
- 3, /* GENERALIO8 */
- 0, /* GENERALIO9 */
- 0, /* GENERALIO10 */
- 0, /* GENERALIO11 */
- 0, /* GENERALIO12 */
- 3, /* GENERALIO13 */
- 3, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
- 0, /* GENERALIO17 */
- 0, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 0, /* GENERALIO23 */
- 0, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 2, /* MIXED1IO0 */
- 2, /* MIXED1IO1 */
- 2, /* MIXED1IO2 */
- 2, /* MIXED1IO3 */
- 2, /* MIXED1IO4 */
- 2, /* MIXED1IO5 */
- 2, /* MIXED1IO6 */
- 2, /* MIXED1IO7 */
- 2, /* MIXED1IO8 */
- 2, /* MIXED1IO9 */
- 2, /* MIXED1IO10 */
- 2, /* MIXED1IO11 */
- 2, /* MIXED1IO12 */
- 2, /* MIXED1IO13 */
- 2, /* MIXED1IO14 */
- 3, /* MIXED1IO15 */
- 3, /* MIXED1IO16 */
- 3, /* MIXED1IO17 */
- 3, /* MIXED1IO18 */
- 3, /* MIXED1IO19 */
- 3, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 0, /* MIXED2IO0 */
- 0, /* MIXED2IO1 */
- 0, /* MIXED2IO2 */
- 0, /* MIXED2IO3 */
- 0, /* MIXED2IO4 */
- 0, /* MIXED2IO5 */
- 0, /* MIXED2IO6 */
- 0, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 1, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 0, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 1, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 1, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 1, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 1, /* GPLMUX40 */
- 1, /* GPLMUX41 */
- 1, /* GPLMUX42 */
- 1, /* GPLMUX43 */
- 1, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 1, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 1, /* GPLMUX53 */
- 1, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 0, /* GPLMUX57 */
- 0, /* GPLMUX58 */
- 1, /* GPLMUX59 */
- 1, /* GPLMUX60 */
- 1, /* GPLMUX61 */
- 1, /* GPLMUX62 */
- 0, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 0, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 1, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h
deleted file mode 100644
index 218ab35c042..00000000000
--- a/board/is1/qts/pll_config.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA Clock and PLL configuration
- */
-
-#ifndef __SOCFPGA_PLL_CONFIG_H__
-#define __SOCFPGA_PLL_CONFIG_H__
-
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
-
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 375000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
-
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
-
-
-#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
deleted file mode 100644
index 2573171abeb..00000000000
--- a/board/is1/qts/sdram_config.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA SDRAM configuration
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE 0x49
-#define RW_MGR_GUARANTEED_READ 0x4C
-#define RW_MGR_GUARANTEED_READ_CONT 0x54
-#define RW_MGR_GUARANTEED_WRITE 0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_IDLE_LOOP1 0x7B
-#define RW_MGR_IDLE_LOOP2 0x7A
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
-#define RW_MGR_INIT_RESET_1_CKE_0 0x74
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_READ_B2B 0x59
-#define RW_MGR_READ_B2B_WAIT1 0x61
-#define RW_MGR_READ_B2B_WAIT2 0x6B
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_SGLE_READ 0x7D
-#define RW_MGR_ZQCL 0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 8
-#define CALIB_VFIFO_OFFSET 6
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 312
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 31
-#define IO_DQS_EN_DELAY_OFFSET 0
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 4
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_DATA_MASK_WIDTH 2
-#define RW_MGR_MEM_DATA_WIDTH 16
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 2
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 2
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 2
-#define TINIT_CNTR0_VAL 99
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TRESET_CNTR0_VAL 99
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] = {
- 0x20700000,
- 0x20780000,
- 0x10080431,
- 0x10080530,
- 0x10090044,
- 0x100a00c8,
- 0x100b0000,
- 0x10380400,
- 0x10080449,
- 0x100804c8,
- 0x100a0024,
- 0x10090130,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] = {
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x8000,
- 0xa000,
- 0xc000,
- 0x80000,
- 0x80,
- 0x8080,
- 0xa080,
- 0xc080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/is1/socfpga.c b/board/is1/socfpga.c
deleted file mode 100644
index 2a543bf7bad..00000000000
--- a/board/is1/socfpga.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * Currently nothing special is needed on this board, empty file to
- * make build scripts happy
- */
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
deleted file mode 100644
index 682e58fdb8b..00000000000
--- a/configs/socfpga_is1_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_IS1=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-# CONFIG_MMC is not set
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h
deleted file mode 100644
index c233c208a53..00000000000
--- a/include/configs/socfpga_is1.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- * Copyright (C) 2016 Pavel Machek <pavel@denx.de>
- */
-#ifndef __CONFIG_SOCFPGA_IS1_H__
-#define __CONFIG_SOCFPGA_IS1_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x10000000
-
-/* Booting Linux */
-#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_ARP_TIMEOUT 500UL
-
-/* PHY */
-#endif
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-/*
- * Bootcounter
- */
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-#endif /* __CONFIG_SOCFPGA_IS1_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 86/93] arm: Remove brppt1_mmc board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (84 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 85/93] arm: Remove socfpga_is1 board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-20 11:08 ` Hannes Schmelzer
2018-11-19 15:54 ` [U-Boot] [PATCH 87/93] arm: Remove db-mv784mp-gp board Simon Glass
` (11 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/Kconfig | 1 -
board/BuR/brppt1/Kconfig | 15 --
board/BuR/brppt1/MAINTAINERS | 8 --
board/BuR/brppt1/Makefile | 12 --
board/BuR/brppt1/board.c | 190 -------------------------
board/BuR/brppt1/config.mk | 36 -----
board/BuR/brppt1/mux.c | 253 ----------------------------------
configs/brppt1_mmc_defconfig | 95 -------------
configs/brppt1_nand_defconfig | 99 -------------
configs/brppt1_spi_defconfig | 109 ---------------
include/configs/brppt1.h | 214 ----------------------------
11 files changed, 1032 deletions(-)
delete mode 100644 board/BuR/brppt1/Kconfig
delete mode 100644 board/BuR/brppt1/MAINTAINERS
delete mode 100644 board/BuR/brppt1/Makefile
delete mode 100644 board/BuR/brppt1/board.c
delete mode 100644 board/BuR/brppt1/config.mk
delete mode 100644 board/BuR/brppt1/mux.c
delete mode 100644 configs/brppt1_mmc_defconfig
delete mode 100644 configs/brppt1_nand_defconfig
delete mode 100644 configs/brppt1_spi_defconfig
delete mode 100644 include/configs/brppt1.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 5caf4bae6f8..7ccbe2db227 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -176,7 +176,6 @@ source "arch/arm/mach-omap2/omap5/Kconfig"
source "arch/arm/mach-omap2/am33xx/Kconfig"
source "board/BuR/brxre1/Kconfig"
-source "board/BuR/brppt1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
diff --git a/board/BuR/brppt1/Kconfig b/board/BuR/brppt1/Kconfig
deleted file mode 100644
index e006c80e6ed..00000000000
--- a/board/BuR/brppt1/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_BRPPT1
-
-config SYS_BOARD
- default "brppt1"
-
-config SYS_VENDOR
- default "BuR"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "brppt1"
-
-endif
diff --git a/board/BuR/brppt1/MAINTAINERS b/board/BuR/brppt1/MAINTAINERS
deleted file mode 100644
index 9eddab42089..00000000000
--- a/board/BuR/brppt1/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BRPPT1 BOARD
-M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
-S: Maintained
-F: board/BuR/brppt1/
-F: include/configs/brppt1.h
-F: configs/brppt1_mmc_defconfig
-F: configs/brppt1_nand_defconfig
-F: configs/brppt1_spi_defconfig
diff --git a/board/BuR/brppt1/Makefile b/board/BuR/brppt1/Makefile
deleted file mode 100644
index 3dec0e6522a..00000000000
--- a/board/BuR/brppt1/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
-# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
-
-ifeq ($(CONFIG_SPL_BUILD),y)
-obj-y := mux.o
-endif
-obj-y += ../common/common.o
-obj-y += board.o
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
deleted file mode 100644
index d2e7c722423..00000000000
--- a/board/BuR/brppt1/board.c
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for B&R BRPPT1
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <power/tps65217.h>
-#include "../common/bur_common.h"
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* --------------------------------------------------------------------------*/
-/* -- defines for GPIO -- */
-#define REPSWITCH (0+20) /* GPIO0_20 */
-
-#if defined(CONFIG_SPL_BUILD)
-/* TODO: check ram-timing ! */
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-static const struct ctrl_ioregs ddr3_ioregs = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-#define OSC (V_OSCK/1000000)
-static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- int rc;
-
- struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
- /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
- struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
-
- /*
- * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
- * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
- * the source of timer6 clk to CLK_M_OSC
- */
- writel(0x01, &cmdpll->clktimer6clk);
-
- /* enable additional clocks of modules which are accessed later */
- u32 *const clk_domains[] = {
- &cmper->lcdcclkstctrl,
- 0
- };
-
- u32 *const clk_modules_tsspecific[] = {
- &cmper->lcdclkctrl,
- &cmper->timer5clkctrl,
- &cmper->timer6clkctrl,
- 0
- };
- do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
-
- /* setup I2C */
- enable_i2c_pin_mux();
- i2c_set_bus_num(0);
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- pmicsetup(0);
-
- /* peripheral reset */
- rc = gpio_request(64 + 29, "GPMC_WAIT1");
- if (rc != 0)
- printf("cannot request GPMC_WAIT1 GPIO!\n");
- rc = gpio_direction_output(64 + 29, 1);
- if (rc != 0)
- printf("cannot set GPMC_WAIT1 GPIO!\n");
-
- rc = gpio_request(64 + 28, "GPMC_WAIT0");
- if (rc != 0)
- printf("cannot request GPMC_WAIT0 GPIO!\n");
- rc = gpio_direction_output(64 + 28, 1);
- if (rc != 0)
- printf("cannot set GPMC_WAIT0 GPIO!\n");
-
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- return &dpll_ddr3;
-}
-
-void sdram_init(void)
-{
- config_ddr(400, &ddr3_ioregs,
- &ddr3_data,
- &ddr3_cmd_ctrl_data,
- &ddr3_emif_reg_data, 0);
-}
-#endif /* CONFIG_SPL_BUILD */
-
-/* Basic board specific setup. Pinmux has been handled already. */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_NAND
- gpmc_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-static char *bootmodeascii[16] = {
- "BOOT", "reserved", "reserved", "reserved",
- "RUN", "reserved", "reserved", "reserved",
- "reserved", "reserved", "reserved", "reserved",
- "PME", "reserved", "reserved", "DIAG",
-};
-
-int board_late_init(void)
-{
- unsigned char bmode = 0;
- ulong bootcount = 0;
- int rc;
-
- bootcount = bootcount_load() & 0xF;
-
- rc = gpio_request(REPSWITCH, "REPSWITCH");
-
- if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
- bmode = 12;
- else if (bootcount > 0)
- bmode = 0;
- else
- bmode = 4;
-
- printf("Mode: %s\n", bootmodeascii[bmode & 0x0F]);
- env_set_ulong("b_mode", bmode);
-
- /* get sure that bootcmd isn't affected by any bootcount value */
- env_set_ulong("bootlimit", 0);
-
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/brppt1/config.mk b/board/BuR/brppt1/config.mk
deleted file mode 100644
index b11b544c37c..00000000000
--- a/board/BuR/brppt1/config.mk
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# Copyright (C) 2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
-# B&R Industrial Automation GmbH - http://www.br-automation.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
-
-payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
-
-quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
-cmd_prodbin = \
- dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
- dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
- dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
-
-quiet_cmd_prodzip = SAPZIP $@
-cmd_prodzip = \
- test -d misc && rm -r misc; \
- mkdir misc && \
- cp MLO.byteswap misc/ && \
- cp spl/u-boot-spl.bin misc/ && \
- cp u-boot-dtb.img misc/ && \
- zip -9 -r $@ misc/* >/dev/null $<
-
-ifeq ($(hw-platform-y),brppt1-spi)
-ALL-y += $(hw-platform-y)_prog.bin
-ALL-y += $(hw-platform-y)_prod.zip
-endif
-
-$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
- $(call if_changed,prodbin)
-
-$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
- $(call if_changed,prodzip)
diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c
deleted file mode 100644
index 87eee709fd4..00000000000
--- a/board/BuR/brppt1/mux.c
+++ /dev/null
@@ -1,253 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mux.c
- *
- * Pinmux Setting for B&R BRPPT1 Board(s)
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-static struct module_pin_mux uart0_pin_mux[] = {
- /* UART0_RTS */
- {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
- /* UART0_CTS */
- {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* UART0_RXD */
- {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* UART0_TXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
- {-1},
-};
-static struct module_pin_mux uart1_pin_mux[] = {
- /* UART1_RTS as I2C2-SCL */
- {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* UART1_CTS as I2C2-SDA */
- {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* UART1_RXD */
- {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* UART1_TXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
- {-1},
-};
-#ifdef CONFIG_MMC
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
- {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
- {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
- {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
-
- {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
- {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
- {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
- {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
- {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
- {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
- {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
- {-1},
-};
-#endif
-static struct module_pin_mux i2c0_pin_mux[] = {
- /* I2C_DATA */
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
- /* I2C_SCLK */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux spi0_pin_mux[] = {
- /* SPI0_SCLK */
- {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
- /* SPI0_D0 */
- {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
- /* SPI0_D1 */
- {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
- /* SPI0_CS0 */
- {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
- {-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
- {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
- {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
- {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
- {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux mii2_pin_mux[] = {
- {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
- {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
- {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
- {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
- {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
- {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
- {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
- {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
- {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
- {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
- {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
- {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
- {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
- {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
- /*
- * MII2_CRS is shared with
- * NAND_WAIT0
- */
- {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
- {-1},
-};
-#ifdef CONFIG_NAND
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-#endif
-static struct module_pin_mux gpIOs[] = {
- /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
- {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
- {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
- /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
- {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
- /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
- {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
- {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
- {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
- {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
- {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
- {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
- {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* GPIO2_0 (GPMC_nCS3) - DCOK */
- {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
- /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
- {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
- /*
- * GPIO0_7 (PWW0 OUT)
- * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
- */
- {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
- {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
- /* GPIO0_20 (DMA_INTR1) - REP-Switch */
- {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
- /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
- {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
- /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
- {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
- /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
- {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
- /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
- {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
-#ifndef CONFIG_NAND
- /* GPIO2_3 - NAND_OE */
- {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
- /* GPIO2_4 - NAND_WEN */
- {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
- /* GPIO2_5 - NAND_BE_CLE */
- {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-#endif
- {-1},
-};
-
-static struct module_pin_mux lcd_pin_mux[] = {
- {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
- {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
- {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
- {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
- {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
- {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
- {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
- {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
- {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
- {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
- {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
- {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
- {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
- {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
- {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
- {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
-
- {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
- {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
- {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
- {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
- {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
- {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
- {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
- {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
-
- {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
- {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
- {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
- {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
-
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mii2_pin_mux);
-#ifdef CONFIG_NAND
- configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_MMC)
- configure_module_pin_mux(mmc1_pin_mux);
-#endif
- configure_module_pin_mux(spi0_pin_mux);
- configure_module_pin_mux(lcd_pin_mux);
- configure_module_pin_mux(uart1_pin_mux);
- configure_module_pin_mux(gpIOs);
-}
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
deleted file mode 100644
index 3296a74a0ae..00000000000
--- a/configs/brppt1_mmc_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_AM33XX=y
-CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
-# CONFIG_EXPERT is not set
-# CONFIG_FIT is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=0
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run b_default"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc"
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_OF_TRANSLATE is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_COMPAT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-# CONFIG_NETDEVICES is not set
-CONFIG_DM_SERIAL=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
deleted file mode 100644
index e03eb37dfe2..00000000000
--- a/configs/brppt1_nand_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_AM33XX=y
-CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
-# CONFIG_EXPERT is not set
-# CONFIG_FIT is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=0
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run b_default"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(MLO),128k(cfgscr),128k(dtb),128k(u-boot-env),512k(u-boot),4m(kernel),128m(rootfs),-(user)"
-# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-nand"
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_OF_TRANSLATE is not set
-CONFIG_BLK=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_COMPAT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_PHY_NATSEMI=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-# CONFIG_NETDEVICES is not set
-CONFIG_DM_SERIAL=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
deleted file mode 100644
index 2fa5dacd7a0..00000000000
--- a/configs/brppt1_spi_defconfig
+++ /dev/null
@@ -1,109 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_AM33XX=y
-CONFIG_TARGET_BRPPT1=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
-# CONFIG_EXPERT is not set
-# CONFIG_FIT is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTDELAY=0
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run b_default"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SPL_I2C_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_SPL_DOS_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi"
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_OF_TRANSLATE is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_COMPAT=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_DEVICE=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_NATSEMI=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-# CONFIG_NETDEVICES is not set
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_TI=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_FAT_WRITE=y
-CONFIG_LZO=y
-# CONFIG_OF_LIBFDT_OVERLAY is not set
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
deleted file mode 100644
index 5badd2da8b6..00000000000
--- a/include/configs/brppt1.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * brtpp1.h
- *
- * specific parts for B&R T-Series Motherboard
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- */
-
-#ifndef __CONFIG_BRPPT1_H__
-#define __CONFIG_BRPPT1_H__
-
-#include <configs/bur_cfg_common.h>
-#include <configs/bur_am335x_common.h>
-/* ------------------------------------------------------------------------- */
-/* memory */
-#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
-#define CONFIG_SYS_BOOTM_LEN SZ_32M
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK)
-
-#define CONFIG_POWER_TPS65217
-
-/* Support both device trees and ATAGs. */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-/*#define CONFIG_MACH_TYPE 3589*/
-#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
-
-/* MMC/SD IP block */
-#if defined(CONFIG_EMMC_BOOT)
- #define CONFIG_SUPPORT_EMMC_BOOT
-#endif /* CONFIG_EMMC_BOOT */
-
-/*
- * When we have NAND flash we expect to be making use of mtdparts,
- * both for ease of use in U-Boot and for passing information on to
- * the Linux kernel.
- */
-
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-
-/* NAND */
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
-#endif /* CONFIG_NAND */
-#endif /* CONFIG_SPL_OS_BOOT */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#endif /* CONFIG_NAND */
-
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE (64 << 10)
-
-#ifdef CONFIG_NAND
-#define NANDTGTS \
-"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
-"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-"cfgscr=nand read ${cfgaddr} cfgscr && source ${cfgaddr}\0" \
-"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
- "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
-"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
- "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
-"b_tgts_std=usb0 nand net\0" \
-"b_tgts_rcy=net usb0 nand\0" \
-"b_tgts_pme=usb0 nand net\0"
-#else
-#define NANDTGTS ""
-#endif /* CONFIG_NAND */
-
-#define MMCSPI_TGTS \
-"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
- "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
-"b_t30lgcy#0=" \
- "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
- "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
- "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
- "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
- "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
-"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
- "b_mode=${b_mode}\0" \
-"b_t30lgcy#1=" \
- "load ${loaddev}:1 ${loadaddr} zImage && " \
- "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
- "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
- "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
-"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
-"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
-"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
-"b_tgts_rcy=t30lgcy#1 usb0 net\0" \
-"b_tgts_pme=net usb0 mmc0 mmc1\0" \
-"loaddev=mmc 1\0"
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-#define MMCTGTS \
-MMCSPI_TGTS \
-"cfgscr=mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr}\0"
-#else
-#define MMCTGTS ""
-#endif /* CONFIG_MMC */
-
-#ifdef CONFIG_SPI
-#define SPITGTS \
-MMCSPI_TGTS \
-"cfgscr=sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr}\0"
-#else
-#define SPITGTS ""
-#endif /* CONFIG_SPI */
-
-#define LOAD_OFFSET(x) 0x8##x
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
-BUR_COMMON_ENV \
-"verify=no\0" \
-"autoload=0\0" \
-"scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
-"cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
-"dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
-"loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
-"ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
-"console=ttyO0,115200n8\0" \
-"optargs=consoleblank=0 quiet panic=2\0" \
-"b_break=0\0" \
-"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
-"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
-MMCTGTS \
-SPITGTS \
-NANDTGTS \
-"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
-" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
-" else setenv b_tgts ${b_tgts_std}; fi\0" \
-"b_default=run b_deftgts; for target in ${b_tgts};"\
-" do echo \"### booting ${target} ###\"; run b_${target};" \
-" if test ${b_break} = 1; then; exit; fi; done\0"
-#endif /* !CONFIG_SPL_BUILD*/
-
-#ifdef CONFIG_NAND
-/*
- * GPMC block. We support 1 device and the physical address to
- * access CS0@is 0x8000000.
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x8000000
-/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_NAND_OMAP_GPMC_WSCFG 1
-#endif /* CONFIG_NAND */
-
-/* USB configuration */
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-
-#if defined(CONFIG_SPI)
-/* SPI Flash */
-#define CONFIG_SF_DEFAULT_SPEED 24000000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
-/* Environment */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET 0x20000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#elif defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV 1
-#define CONFIG_SYS_MMC_ENV_PART 2
-#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-/* No NAND env support in SPL */
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#else
-#error "no storage for Environment defined!"
-#endif
-
-#endif /* ! __CONFIG_BRPPT1_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 86/93] arm: Remove brppt1_mmc board
2018-11-19 15:54 ` [U-Boot] [PATCH 86/93] arm: Remove brppt1_mmc board Simon Glass
@ 2018-11-20 11:08 ` Hannes Schmelzer
2018-11-22 20:50 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Hannes Schmelzer @ 2018-11-20 11:08 UTC (permalink / raw)
To: u-boot
On 11/19/18 4:54 PM, Simon Glass wrote:
> This board has not been converted to CONFIG_DM_BLK by the deadline.
> Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-omap2/Kconfig | 1 -
> board/BuR/brppt1/Kconfig | 15 --
> board/BuR/brppt1/MAINTAINERS | 8 --
> board/BuR/brppt1/Makefile | 12 --
> board/BuR/brppt1/board.c | 190 -------------------------
> board/BuR/brppt1/config.mk | 36 -----
> board/BuR/brppt1/mux.c | 253 ----------------------------------
> configs/brppt1_mmc_defconfig | 95 -------------
> configs/brppt1_nand_defconfig | 99 -------------
> configs/brppt1_spi_defconfig | 109 ---------------
> include/configs/brppt1.h | 214 ----------------------------
> 11 files changed, 1032 deletions(-)
> delete mode 100644 board/BuR/brppt1/Kconfig
> delete mode 100644 board/BuR/brppt1/MAINTAINERS
> delete mode 100644 board/BuR/brppt1/Makefile
> delete mode 100644 board/BuR/brppt1/board.c
> delete mode 100644 board/BuR/brppt1/config.mk
> delete mode 100644 board/BuR/brppt1/mux.c
> delete mode 100644 configs/brppt1_mmc_defconfig
> delete mode 100644 configs/brppt1_nand_defconfig
> delete mode 100644 configs/brppt1_spi_defconfig
> delete mode 100644 include/configs/brppt1.h
NAK.
As the speakers before i didn't notice that deadline.
I will have a look into next few days and provide a patch for converting
if necessary.
cheers,
Hannes
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 86/93] arm: Remove brppt1_mmc board
2018-11-20 11:08 ` Hannes Schmelzer
@ 2018-11-22 20:50 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Hannes,
On Tue, 20 Nov 2018 at 04:08, Hannes Schmelzer <hannes@schmelzer.or.at> wrote:
>
>
> On 11/19/18 4:54 PM, Simon Glass wrote:
> > This board has not been converted to CONFIG_DM_BLK by the deadline.
> > Remove it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > arch/arm/mach-omap2/Kconfig | 1 -
> > board/BuR/brppt1/Kconfig | 15 --
> > board/BuR/brppt1/MAINTAINERS | 8 --
> > board/BuR/brppt1/Makefile | 12 --
> > board/BuR/brppt1/board.c | 190 -------------------------
> > board/BuR/brppt1/config.mk | 36 -----
> > board/BuR/brppt1/mux.c | 253 ----------------------------------
> > configs/brppt1_mmc_defconfig | 95 -------------
> > configs/brppt1_nand_defconfig | 99 -------------
> > configs/brppt1_spi_defconfig | 109 ---------------
> > include/configs/brppt1.h | 214 ----------------------------
> > 11 files changed, 1032 deletions(-)
> > delete mode 100644 board/BuR/brppt1/Kconfig
> > delete mode 100644 board/BuR/brppt1/MAINTAINERS
> > delete mode 100644 board/BuR/brppt1/Makefile
> > delete mode 100644 board/BuR/brppt1/board.c
> > delete mode 100644 board/BuR/brppt1/config.mk
> > delete mode 100644 board/BuR/brppt1/mux.c
> > delete mode 100644 configs/brppt1_mmc_defconfig
> > delete mode 100644 configs/brppt1_nand_defconfig
> > delete mode 100644 configs/brppt1_spi_defconfig
> > delete mode 100644 include/configs/brppt1.h
> NAK.
> As the speakers before i didn't notice that deadline.
> I will have a look into next few days and provide a patch for converting
> if necessary.
I think here I am going to change the approach, and enable
CONFIG_SPL_BLK by default, so your board should continue to work
without any changes. It will break a lot of other boards, but they can
be updated, and defaulting to on is best, I think.
Sorry for the noise.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 87/93] arm: Remove db-mv784mp-gp board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (85 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 86/93] arm: Remove brppt1_mmc board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 88/93] arm: Remove socfpga_arria5 board Simon Glass
` (10 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/Marvell/db-mv784mp-gp/MAINTAINERS | 6 -
board/Marvell/db-mv784mp-gp/Makefile | 5 -
board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 117 --------------------
configs/db-mv784mp-gp_defconfig | 64 -----------
include/configs/db-mv784mp-gp.h | 99 -----------------
5 files changed, 291 deletions(-)
delete mode 100644 board/Marvell/db-mv784mp-gp/MAINTAINERS
delete mode 100644 board/Marvell/db-mv784mp-gp/Makefile
delete mode 100644 board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
delete mode 100644 configs/db-mv784mp-gp_defconfig
delete mode 100644 include/configs/db-mv784mp-gp.h
diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS
deleted file mode 100644
index a095f898d40..00000000000
--- a/board/Marvell/db-mv784mp-gp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DB_MV784MP_GP BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/Marvell/db-mv784mp-gp/
-F: include/configs/db-mv784mp-gp.h
-F: configs/db-mv784mp-gp_defconfig
diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile
deleted file mode 100644
index 1bd2388afb3..00000000000
--- a/board/Marvell/db-mv784mp-gp/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-
-obj-y := db-mv784mp-gp.o
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
deleted file mode 100644
index 604e8c1670b..00000000000
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ETH_PHY_CTRL_REG 0
-#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
-#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
-
-/*
- * Those values and defines are taken from the Marvell U-Boot version
- * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
- * "RD-AXP-GP rev 1.0".
- *
- * GPPs
- * MPP# NAME IN/OUT
- * ----------------------------------------------
- * 21 SW_Reset_ OUT
- * 25 Phy_Int# IN
- * 28 SDI_WP IN
- * 29 SDI_Status IN
- * 54-61 On GPP Connector ?
- * 62 Switch Interrupt IN
- * 63-65 Reserved from SW Board ?
- * 66 SW_BRD connected IN
- */
-#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
-#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
-#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
-
-#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
-#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
-#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
-
-int board_early_init_f(void)
-{
- /* Configure MPP */
- writel(0x00000000, MVEBU_MPP_BASE + 0x00);
- writel(0x00000000, MVEBU_MPP_BASE + 0x04);
- writel(0x33000000, MVEBU_MPP_BASE + 0x08);
- writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
- writel(0x11111111, MVEBU_MPP_BASE + 0x10);
- writel(0x00221100, MVEBU_MPP_BASE + 0x14);
- writel(0x00000003, MVEBU_MPP_BASE + 0x18);
- writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
- writel(0x00000000, MVEBU_MPP_BASE + 0x20);
-
- /* Configure GPIO */
- writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
- writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
- writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
- writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
- writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
- writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Marvell DB-MV784MP-GP\n");
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in controller(s) come first */
- return pci_eth_init(bis);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- u16 reg;
-
- /* Enable QSGMII AN */
- /* Set page to 4 */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
- /* Enable AN */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
- /* Set page to 0 */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
-
- /* Phy C_ANEG */
- reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
- reg |= 0x1E0;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
-
- /* Soft-Reset */
- phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
- phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
-
- /* Power up the phy */
- reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
- reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
- phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
-
- printf("88E1545 Initialized\n");
- return 0;
-}
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
deleted file mode 100644
index 3f140986b69..00000000000
--- a/configs/db-mv784mp-gp_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_TEXT_BASE=0x00800000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_DB_MV784MP_GP=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SATA_MV=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_NAND_PXA3XX=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_MVNETA=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
deleted file mode 100644
index 8ad007cc491..00000000000
--- a/include/configs/db-mv784mp-gp.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
- */
-
-#ifndef _CONFIG_DB_MV7846MP_GP_H
-#define _CONFIG_DB_MV7846MP_GP_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
-
-/*
- * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
- * for DDR ECC byte filling in the SPL before loading the main
- * U-Boot into it.
- */
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-
-/* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
-#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
-
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-
-/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-/* PCIe support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-/* NAND */
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Memory layout while starting into the bin_hdr via the
- * BootROM:
- *
- * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
- * 0x4000.4030 bin_hdr start address
- * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
- * 0x4007.fffc BootROM stack top
- *
- * The address space between 0x4007.fffc and 0x400f.fff is not locked in
- * L2 cache thus cannot be used.
- */
-
-/* SPL */
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x40004030
-#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-
-/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SPD_EEPROM 0x4e
-#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
-
-#endif /* _CONFIG_DB_MV7846MP_GP_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 88/93] arm: Remove socfpga_arria5 board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (86 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 87/93] arm: Remove db-mv784mp-gp board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 89/93] arm: Remove socfpga_vining_fpga board Simon Glass
` (9 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
board/altera/arria5-socdk/MAINTAINERS | 7 -
board/altera/arria5-socdk/Makefile | 7 -
board/altera/arria5-socdk/qts/iocsr_config.h | 695 ------------------
board/altera/arria5-socdk/qts/pinmux_config.h | 218 ------
board/altera/arria5-socdk/qts/pll_config.h | 84 ---
board/altera/arria5-socdk/qts/sdram_config.h | 342 ---------
board/altera/arria5-socdk/socfpga.c | 5 -
configs/socfpga_arria5_defconfig | 77 --
include/configs/socfpga_arria5_socdk.h | 22 -
9 files changed, 1457 deletions(-)
delete mode 100644 board/altera/arria5-socdk/MAINTAINERS
delete mode 100644 board/altera/arria5-socdk/Makefile
delete mode 100644 board/altera/arria5-socdk/qts/iocsr_config.h
delete mode 100644 board/altera/arria5-socdk/qts/pinmux_config.h
delete mode 100644 board/altera/arria5-socdk/qts/pll_config.h
delete mode 100644 board/altera/arria5-socdk/qts/sdram_config.h
delete mode 100644 board/altera/arria5-socdk/socfpga.c
delete mode 100644 configs/socfpga_arria5_defconfig
delete mode 100644 include/configs/socfpga_arria5_socdk.h
diff --git a/board/altera/arria5-socdk/MAINTAINERS b/board/altera/arria5-socdk/MAINTAINERS
deleted file mode 100644
index 873ec2be2d9..00000000000
--- a/board/altera/arria5-socdk/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@kernel.org>
-M: Chin-Liang See <clsee@altera.com>
-S: Maintained
-F: board/altera/arria5-socdk/
-F: include/configs/socfpga_arria5_socdk.h
-F: configs/socfpga_arria5_defconfig
diff --git a/board/altera/arria5-socdk/Makefile b/board/altera/arria5-socdk/Makefile
deleted file mode 100644
index e1c8a6b3c7c..00000000000
--- a/board/altera/arria5-socdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y := socfpga.o
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h
deleted file mode 100644
index 69a92de6361..00000000000
--- a/board/altera/arria5-socdk/qts/iocsr_config.h
+++ /dev/null
@@ -1,695 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA IOCSR configuration
- */
-
-#ifndef __SOCFPGA_IOCSR_CONFIG_H__
-#define __SOCFPGA_IOCSR_CONFIG_H__
-
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
-
-const unsigned long iocsr_scan_chain0_table[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000060,
- 0x00018060,
- 0x06018060,
- 0x00004000,
- 0x0C0300C0,
- 0x0C030000,
- 0x00000030,
- 0x00000000,
- 0x00000000,
- 0x00002000,
- 0x00000000,
- 0x00000000,
- 0x06000000,
- 0x00006018,
- 0x01806018,
- 0x00001000,
- 0x0000C030,
- 0x04000000,
- 0x03000000,
- 0x0000300C,
- 0x00000000,
- 0x00000800,
- 0x00006018,
- 0x01806000,
- 0x01800000,
- 0x00000006,
- 0x00001806,
- 0x00000400,
- 0x0000300C,
- 0x00C03000,
- 0x00C00000,
- 0x00000003,
- 0x00000C03,
- 0x00000200,
-};
-
-const unsigned long iocsr_scan_chain1_table[] = {
- 0x00100000,
- 0x300C0000,
- 0x300000C0,
- 0x000000C0,
- 0x000300C0,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000000,
- 0x00000060,
- 0x00018060,
- 0x00004000,
- 0x000300C0,
- 0x10000000,
- 0x0C000000,
- 0x00000030,
- 0x0000C030,
- 0x00002000,
- 0x06018060,
- 0x06018000,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x00001000,
- 0x0000C030,
- 0x0300C000,
- 0x03000000,
- 0x0000300C,
- 0x0000300C,
- 0x00000800,
- 0x00006018,
- 0x01806000,
- 0x01800000,
- 0x00000006,
- 0x00002000,
- 0x00000400,
- 0x0000300C,
- 0x01000000,
- 0x00000000,
- 0x00000004,
- 0x00000C03,
- 0x00000200,
- 0x00001806,
- 0x00800000,
- 0x00000000,
- 0x00000002,
- 0x00000800,
- 0x00000100,
- 0x00001000,
- 0x00400000,
- 0xC0300000,
- 0x00000000,
- 0x00000400,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[] = {
- 0x00100000,
- 0x40000000,
- 0x00000000,
- 0x00000100,
- 0x00040000,
- 0x00008000,
- 0x18060180,
- 0x20000000,
- 0x00000000,
- 0x00000080,
- 0x00020000,
- 0x00004000,
- 0x00040000,
- 0x10000000,
- 0x00000000,
- 0x00000000,
- 0x00010000,
- 0x00002000,
- 0x10038060,
- 0x00000000,
- 0x00000000,
- 0x00000020,
- 0x01806018,
- 0x00001000,
- 0x00010000,
- 0x04000000,
- 0x03000000,
- 0x0000801C,
- 0x00004000,
- 0x00000800,
- 0x01806018,
- 0x02000000,
- 0x00000000,
- 0x00000008,
- 0x00002000,
- 0x00000400,
- 0x00C0300C,
- 0x00C03000,
- 0x00C00003,
- 0x00000C03,
- 0x00300C03,
- 0x00000200,
- 0x00601806,
- 0x80601800,
- 0x80600001,
- 0x80000601,
- 0x00180601,
- 0x00000100,
-};
-
-const unsigned long iocsr_scan_chain3_table[] = {
- 0x2C820D80,
- 0x082000FF,
- 0x0A804001,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0xE4400000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000050,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00A28,
- 0xA20D0000,
- 0x24906808,
- 0x00A28340,
- 0xD000001A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000FF0,
- 0x72200000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x6A1C0000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x1A870001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000050,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00040,
- 0xA20D0002,
- 0x24906808,
- 0x00A28340,
- 0xD005141A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x01000000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x04510680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00600391,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x8341D348,
- 0x821A0124,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00400000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F1690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0x00481800,
- 0x001A1A1A,
- 0x085506A0,
- 0x0000E1D4,
- 0x045506A0,
- 0x0000E1D4,
- 0x085506A0,
- 0x8000E1D4,
- 0x00000200,
- 0x00000004,
- 0x04000000,
- 0x00000009,
- 0x00002410,
- 0x00000040,
- 0x41000000,
- 0x00002082,
- 0x00000350,
- 0x000000DA,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x022A8350,
- 0x000070EA,
- 0x86000000,
- 0x08000004,
- 0x00000000,
- 0x00482000,
- 0x21800000,
- 0x00101061,
- 0x021541A8,
- 0x00003875,
- 0x011541A8,
- 0x00003875,
- 0x021541A8,
- 0x20003875,
- 0x00000080,
- 0x00000001,
- 0x41000000,
- 0x00000002,
- 0x00FF0904,
- 0x00000000,
- 0x90400000,
- 0x00000820,
- 0xC0000001,
- 0xFFD602AF,
- 0x86FFFFFF,
- 0x0A0A78B4,
- 0x000D020A,
- 0x00006800,
- 0x028A4320,
- 0xEC2CB23D,
- 0x8F5D1451,
- 0xA47A88A2,
- 0x0001A0E9,
- 0x00410D00,
- 0x40000068,
- 0x3D000003,
- 0x51EC2CB2,
- 0xA28F5D14,
- 0xE9A47A88,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000540,
- 0x000003A8,
- 0x08AA0D40,
- 0x8001C3A8,
- 0x0000007F,
- 0x00000000,
- 0x00004060,
- 0xE1208000,
- 0x0000001F,
- 0x00004100,
-};
-
-
-#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/pinmux_config.h b/board/altera/arria5-socdk/qts/pinmux_config.h
deleted file mode 100644
index 78a03258249..00000000000
--- a/board/altera/arria5-socdk/qts/pinmux_config.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA PinMux configuration
- */
-
-#ifndef __SOCFPGA_PINMUX_CONFIG_H__
-#define __SOCFPGA_PINMUX_CONFIG_H__
-
-const u8 sys_mgr_init_table[] = {
- 0, /* EMACIO0 */
- 2, /* EMACIO1 */
- 2, /* EMACIO2 */
- 2, /* EMACIO3 */
- 2, /* EMACIO4 */
- 2, /* EMACIO5 */
- 2, /* EMACIO6 */
- 2, /* EMACIO7 */
- 2, /* EMACIO8 */
- 0, /* EMACIO9 */
- 2, /* EMACIO10 */
- 2, /* EMACIO11 */
- 2, /* EMACIO12 */
- 2, /* EMACIO13 */
- 3, /* EMACIO14 */
- 3, /* EMACIO15 */
- 3, /* EMACIO16 */
- 3, /* EMACIO17 */
- 3, /* EMACIO18 */
- 3, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 0, /* FLASHIO4 */
- 0, /* FLASHIO5 */
- 0, /* FLASHIO6 */
- 0, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 3, /* GENERALIO0 */
- 3, /* GENERALIO1 */
- 3, /* GENERALIO2 */
- 3, /* GENERALIO3 */
- 3, /* GENERALIO4 */
- 3, /* GENERALIO5 */
- 3, /* GENERALIO6 */
- 3, /* GENERALIO7 */
- 3, /* GENERALIO8 */
- 0, /* GENERALIO9 */
- 0, /* GENERALIO10 */
- 0, /* GENERALIO11 */
- 0, /* GENERALIO12 */
- 0, /* GENERALIO13 */
- 0, /* GENERALIO14 */
- 3, /* GENERALIO15 */
- 3, /* GENERALIO16 */
- 2, /* GENERALIO17 */
- 2, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 3, /* GENERALIO23 */
- 3, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 0, /* MIXED1IO1 */
- 0, /* MIXED1IO2 */
- 0, /* MIXED1IO3 */
- 0, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 0, /* MIXED1IO8 */
- 0, /* MIXED1IO9 */
- 0, /* MIXED1IO10 */
- 0, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 3, /* MIXED1IO15 */
- 3, /* MIXED1IO16 */
- 3, /* MIXED1IO17 */
- 3, /* MIXED1IO18 */
- 3, /* MIXED1IO19 */
- 3, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 3, /* MIXED2IO0 */
- 3, /* MIXED2IO1 */
- 3, /* MIXED2IO2 */
- 3, /* MIXED2IO3 */
- 3, /* MIXED2IO4 */
- 3, /* MIXED2IO5 */
- 3, /* MIXED2IO6 */
- 3, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 1, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 1, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 1, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 1, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 1, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 1, /* GPLMUX40 */
- 1, /* GPLMUX41 */
- 1, /* GPLMUX42 */
- 1, /* GPLMUX43 */
- 1, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 1, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 1, /* GPLMUX53 */
- 1, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 1, /* GPLMUX57 */
- 1, /* GPLMUX58 */
- 1, /* GPLMUX59 */
- 1, /* GPLMUX60 */
- 1, /* GPLMUX61 */
- 1, /* GPLMUX62 */
- 1, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 1, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 0, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h
deleted file mode 100644
index 6c832543444..00000000000
--- a/board/altera/arria5-socdk/qts/pll_config.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA Clock and PLL configuration
- */
-
-#ifndef __SOCFPGA_PLL_CONFIG_H__
-#define __SOCFPGA_PLL_CONFIG_H__
-
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
-
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 350000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
-
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
-
-
-#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
deleted file mode 100644
index 927a7a4f8e0..00000000000
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA SDRAM configuration
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE 0x48
-#define RW_MGR_GUARANTEED_READ 0x4B
-#define RW_MGR_GUARANTEED_READ_CONT 0x53
-#define RW_MGR_GUARANTEED_WRITE 0x17
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_IDLE_LOOP1 0x7A
-#define RW_MGR_IDLE_LOOP2 0x79
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
-#define RW_MGR_INIT_RESET_1_CKE_0 0x73
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_READ_B2B 0x58
-#define RW_MGR_READ_B2B_WAIT1 0x60
-#define RW_MGR_READ_B2B_WAIT2 0x6A
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_SGLE_READ 0x7C
-#define RW_MGR_ZQCL 0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 8
-#define CALIB_VFIFO_OFFSET 6
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 234
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 15
-#define IO_DQS_EN_DELAY_OFFSET 16
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 6
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_MEM_DATA_WIDTH 40
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
-#define TINIT_CNTR0_VAL 132
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TRESET_CNTR0_VAL 132
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] ={
- 0x20700000,
- 0x20780000,
- 0x10080831,
- 0x10080930,
- 0x10090004,
- 0x100a0008,
- 0x100b0000,
- 0x10380400,
- 0x10080849,
- 0x100808c8,
- 0x100a0004,
- 0x10090010,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] ={
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x8000,
- 0xa000,
- 0xc000,
- 0x80000,
- 0x80,
- 0x8080,
- 0xa080,
- 0xc080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c
deleted file mode 100644
index 48bfe329517..00000000000
--- a/board/altera/arria5-socdk/socfpga.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- */
-#include <common.h>
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
deleted file mode 100644
index e7e1121c5c4..00000000000
--- a/configs/socfpga_arria5_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),- at 1536k(UBI)0"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DFU_MMC=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="altera"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
deleted file mode 100644
index 24fcdd8b5a3..00000000000
--- a/include/configs/socfpga_arria5_socdk.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
-#define __CONFIG_SOCFPGA_ARRIA5_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-
-/* Booting Linux */
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 89/93] arm: Remove socfpga_vining_fpga board
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (87 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 88/93] arm: Remove socfpga_arria5 board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 21:16 ` Marek Vasut
2018-11-19 15:54 ` [U-Boot] [PATCH 90/93] arm: Remove dra7xx_evm and dra7xx_hs_evm boards Simon Glass
` (8 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
configs/socfpga_vining_fpga_defconfig | 94 --------------
include/configs/socfpga_vining_fpga.h | 180 --------------------------
2 files changed, 274 deletions(-)
delete mode 100644 configs/socfpga_vining_fpga_defconfig
delete mode 100644 include/configs/socfpga_vining_fpga.h
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
deleted file mode 100644
index 6fcf8c66f8a..00000000000
--- a/configs/socfpga_vining_fpga_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x01000040
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_FPGA_SOCFPGA=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=48
-CONFIG_LED_STATUS1=y
-CONFIG_LED_STATUS_BIT1=53
-CONFIG_LED_STATUS2=y
-CONFIG_LED_STATUS_BIT2=54
-CONFIG_LED_STATUS3=y
-CONFIG_LED_STATUS_BIT3=65
-CONFIG_LED_STATUS_CMD=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MTD_DEVICE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_MII=y
-CONFIG_DM_RESET=y
-CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="samtec"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
deleted file mode 100644
index 5517ed722d4..00000000000
--- a/include/configs/socfpga_vining_fpga.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
-#define __CONFIG_SAMTEC_VINING_FPGA_H__
-
-#include <asm/arch/base_addr_ac5.h>
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
-
-/* Booting Linux */
-#define CONFIG_BOOTFILE "openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
-#define CONFIG_BOOTCOMMAND "run selboot"
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* I2C EEPROM */
-#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-#endif
-
-/*
- * Status LEDs:
- * 0 ... Top Green
- * 1 ... Top Red
- * 2 ... Bottom Green
- * 3 ... Bottom Red
- */
-
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_BOOTP_SEND_HOSTNAME
-/* PHY */
-#endif
-
-/* Extra Environment */
-#define CONFIG_HOSTNAME "socfpga_vining_fpga"
-
-/*
- * Active LOW GPIO buttons:
- * A: GPIO 77 ... the button between USB B and ethernet
- * B: GPIO 78 ... the button between USB A ports
- *
- * The logic:
- * if button B is not pressed, boot normal Linux system immediatelly
- * if button B is pressed, wait $bootdelay and boot recovery system
- */
-#define CONFIG_PREBOOT \
- "setenv hostname vining-${unit_serial} ; " \
- "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
- "if gpio input 78 ; then " \
- "setenv bootdelay 10 ; " \
- "setenv boottype rcvr ; " \
- "else " \
- "setenv bootdelay 5 ; " \
- "setenv boottype norm ; " \
- "fi"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "consdev=ttyS0\0" \
- "baudrate=115200\0" \
- "bootscript=boot.scr\0" \
- "ubimtdnr=5\0" \
- "ubimtd=rootfs\0" \
- "ubipart=ubi0:rootfs\0" \
- "ubisfcs=1\0" /* Default is flash at CS#1 */ \
- "netdev=eth0\0" \
- "hostname=vining_fpga\0" \
- "kernel_addr_r=0x10000000\0" \
- "mtdparts_0=ff705000.spi.0:" \
- "1m(u-boot)," \
- "64k(env1)," \
- "64k(env2)," \
- "256k(samtec1)," \
- "256k(samtec2)," \
- "-(rcvrfs)\0" /* Recovery */ \
- "mtdparts_1=ff705000.spi.1:" \
- "32m(rootfs)," \
- "-(userfs)\0" \
- "update_filename=u-boot-with-spl-dtb.sfp\0" \
- "update_qspi_offset=0x0\0" \
- "update_qspi=" /* Update the QSPI firmware */ \
- "if sf probe ; then " \
- "if tftp ${update_filename} ; then " \
- "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
- "fi ; " \
- "fi\0" \
- "fpga_filename=output_file.rbf\0" \
- "load_fpga=" /* Load FPGA bitstream */ \
- "if tftp ${fpga_filename} ; then " \
- "fpga load 0 $loadaddr $filesize ; " \
- "bridge enable ; " \
- "fi\0" \
- "addcons=" \
- "setenv bootargs ${bootargs} " \
- "console=${consdev},${baudrate}\0" \
- "addip=" \
- "setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=" \
- "setenv bootargs ${bootargs} ${miscargs}\0" \
- "addmtd=" \
- "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \
- "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
- "addargs=run addcons addmtd addmisc\0" \
- "ubiload=" \
- "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
- "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
- "netload=" \
- "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
- "miscargs=nohlt panic=1\0" \
- "ubiargs=" \
- "setenv bootargs ubi.mtd=${ubimtdnr} " \
- "root=${ubipart} rootfstype=ubifs\0" \
- "nfsargs=" \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
- "ubi_sfsel=" \
- "if test \"${boottype}\" = \"rcvr\" ; then " \
- "setenv ubisfcs 0 ; " \
- "setenv ubimtd rcvrfs ; " \
- "setenv ubimtdnr 5 ; " \
- "setenv mtdparts mtdparts=${mtdparts_0} ; " \
- "setenv mtdids nor0=ff705000.spi.0 ; " \
- "setenv ubipart ubi0:rootfs ; " \
- "else " \
- "setenv ubisfcs 1 ; " \
- "setenv ubimtd rootfs ; " \
- "setenv ubimtdnr 6 ; " \
- "setenv mtdparts mtdparts=${mtdparts_1} ; " \
- "setenv mtdids nor0=ff705000.spi.1 ; " \
- "setenv ubipart ubi0:rootfs ; " \
- "fi ; " \
- "sf probe 0:${ubisfcs}\0" \
- "ubi_ubi=" \
- "run ubi_sfsel ubiload ubiargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "ubi_nfs=" \
- "run ubiload nfsargs addip addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "net_ubi=" \
- "run netload ubiargs addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "net_nfs=" \
- "run netload nfsargs addip addargs ; " \
- "bootm ${kernel_addr_r}\0" \
- "selboot=" /* Select from where to boot. */ \
- "if test \"${bootmode}\" = \"qspi\" ; then " \
- "led all off ; " \
- "if test \"${boottype}\" = \"rcvr\" ; then " \
- "echo \"Booting recovery system\" ; " \
- "led 3 on ; " /* Bottom RED */ \
- "fi ; " \
- "led 1 on ; " /* Top RED */ \
- "run ubi_ubi ; " \
- "else echo \"Unsupported boot mode: \"${bootmode} ; " \
- "fi\0" \
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
-
-/* Support changing the prompt string */
-#define CONFIG_CMDLINE_PS_SUPPORT
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 90/93] arm: Remove dra7xx_evm and dra7xx_hs_evm boards
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (88 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 89/93] arm: Remove socfpga_vining_fpga board Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 91/93] dm: Enable CONFIG_BLK Simon Glass
` (7 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
These board have not been converted to CONFIG_DM_BLK by the deadline.
Remove them.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-omap2/omap5/Kconfig | 1 -
board/ti/dra7xx/Kconfig | 14 -
board/ti/dra7xx/MAINTAINERS | 7 -
board/ti/dra7xx/Makefile | 6 -
board/ti/dra7xx/README | 26 -
board/ti/dra7xx/evm.c | 1202 -----------------------------
board/ti/dra7xx/mux_data.h | 1121 ---------------------------
configs/dra7xx_evm_defconfig | 102 ---
configs/dra7xx_hs_evm_defconfig | 101 ---
include/configs/dra7xx_evm.h | 165 ----
10 files changed, 2745 deletions(-)
delete mode 100644 board/ti/dra7xx/Kconfig
delete mode 100644 board/ti/dra7xx/MAINTAINERS
delete mode 100644 board/ti/dra7xx/Makefile
delete mode 100644 board/ti/dra7xx/README
delete mode 100644 board/ti/dra7xx/evm.c
delete mode 100644 board/ti/dra7xx/mux_data.h
delete mode 100644 configs/dra7xx_evm_defconfig
delete mode 100644 configs/dra7xx_hs_evm_defconfig
delete mode 100644 include/configs/dra7xx_evm.h
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index f083a4a385c..fba25e8b180 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -163,7 +163,6 @@ endif
source "board/compulab/cl-som-am57x/Kconfig"
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/dra7xx/Kconfig"
source "board/ti/am57xx/Kconfig"
endif
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
deleted file mode 100644
index f6a8e07c5b2..00000000000
--- a/board/ti/dra7xx/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_DRA7XX_EVM
-
-config SYS_BOARD
- default "dra7xx"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "dra7xx_evm"
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
deleted file mode 100644
index 46b6e82b36e..00000000000
--- a/board/ti/dra7xx/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-DRA7XX BOARD
-M: Lokesh Vutla <lokeshvutla@ti.com>
-S: Maintained
-F: board/ti/dra7xx/
-F: include/configs/dra7xx_evm.h
-F: configs/dra7xx_evm_defconfig
-F: configs/dra7xx_hs_evm_defconfig
diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile
deleted file mode 100644
index 8d0ca56aded..00000000000
--- a/board/ti/dra7xx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013
-# Texas Instruments, <www.ti.com>
-
-obj-y := evm.o
diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README
deleted file mode 100644
index 533da01a347..00000000000
--- a/board/ti/dra7xx/README
+++ /dev/null
@@ -1,26 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'dra7xx_evm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2. In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} dra7xx/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
-U-Boot # mmc rst-function 1 1
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
deleted file mode 100644
index bbe54450aee..00000000000
--- a/board/ti/dra7xx/evm.c
+++ /dev/null
@@ -1,1202 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * Based on previous work by:
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- */
-#include <common.h>
-#include <palmas.h>
-#include <sata.h>
-#include <linux/string.h>
-#include <asm/gpio.h>
-#include <usb.h>
-#include <linux/usb/gadget.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/dra7xx_iodelay.h>
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sata.h>
-#include <environment.h>
-#include <dwc3-uboot.h>
-#include <dwc3-omap-uboot.h>
-#include <ti-usb-phy-uboot.h>
-#include <miiphy.h>
-
-#include "mux_data.h"
-#include "../common/board_detect.h"
-
-#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
-#define board_is_dra74x_evm() board_ti_is("5777xCPU")
-#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
-#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
-#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
- (strncmp("H", board_ti_get_rev(), 1) <= 0))
-#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
- (strncmp("C", board_ti_get_rev(), 1) <= 0))
-#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
- board_ti_get_emif2_size()
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-#include <cpsw.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO 7_11 */
-#define GPIO_DDR_VTT_EN 203
-
-#define SYSINFO_BOARD_NAME_MAX_LEN 37
-
-const struct omap_sysinfo sysinfo = {
- "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
-};
-
-static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
- .sdram_config_init = 0x61851ab2,
- .sdram_config = 0x61851ab2,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x427F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x427F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61862B32,
- .sdram_config = 0x61862B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514C,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x30717FE3,
- .sdram_tim3 = 0x409F86A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400D,
- .emif_ddr_phy_ctlr_1 = 0x0E24400D,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
- .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
- .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
- .sdram_config_init = 0x61862BB2,
- .sdram_config = 0x61862BB2,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x0000514D,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD1137824,
- .sdram_tim2 = 0x30B37FE3,
- .sdram_tim3 = 0x409F8AD8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0824400E,
- .emif_ddr_phy_ctlr_1 = 0x0E24400E,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
- .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
- .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
- .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
- .sdram_config_init = 0x61851ab2,
- .sdram_config = 0x61851ab2,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x30BF7FDA,
- .sdram_tim3 = 0x427F8BA8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x427F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
- .sdram_config_init = 0x61862B32,
- .sdram_config = 0x61862B32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x0000514C,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD113783C,
- .sdram_tim2 = 0x30B47FE3,
- .sdram_tim3 = 0x409F8AD8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0824400D,
- .emif_ddr_phy_ctlr_1 = 0x0E24400D,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
- .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
- .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
- .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
- .sdram_config_init = 0x61862B32,
- .sdram_config = 0x61862B32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x0000514C,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x30B47FE3,
- .sdram_tim3 = 0x409F8AD8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0824400D,
- .emif_ddr_phy_ctlr_1 = 0x0E24400D,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
- .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
- .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
- .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
-{
- u64 ram_size;
-
- ram_size = board_ti_get_emif_size();
-
- switch (omap_revision()) {
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA752_ES2_0:
- switch (emif_nr) {
- case 1:
- if (ram_size > CONFIG_MAX_MEM_MAPPED)
- *regs = &emif1_ddr3_532_mhz_1cs_2G;
- else
- *regs = &emif1_ddr3_532_mhz_1cs;
- break;
- case 2:
- if (ram_size > CONFIG_MAX_MEM_MAPPED)
- *regs = &emif2_ddr3_532_mhz_1cs_2G;
- else
- *regs = &emif2_ddr3_532_mhz_1cs;
- break;
- }
- break;
- case DRA762_ABZ_ES1_0:
- case DRA762_ACD_ES1_0:
- case DRA762_ES1_0:
- if (emif_nr == 1)
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
- else
- *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
- break;
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- case DRA722_ES2_1:
- if (ram_size < CONFIG_MAX_MEM_MAPPED)
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
- else
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
- break;
- default:
- *regs = &emif1_ddr3_532_mhz_1cs;
- }
-}
-
-static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x80640300,
- .dmm_lisa_map_2 = 0xC0500220,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80600100,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-/*
- * DRA722 EVM EMIF1 2GB CONFIGURATION
- * EMIF1 4 devices of 512Mb x 8 Micron
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80700100,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
-{
- u64 ram_size;
-
- ram_size = board_ti_get_emif_size();
-
- switch (omap_revision()) {
- case DRA762_ABZ_ES1_0:
- case DRA762_ACD_ES1_0:
- case DRA762_ES1_0:
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA752_ES2_0:
- if (ram_size > CONFIG_MAX_MEM_MAPPED)
- *dmm_lisa_regs = &lisa_map_dra7_2GB;
- else
- *dmm_lisa_regs = &lisa_map_dra7_1536MB;
- break;
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- case DRA722_ES2_1:
- default:
- if (ram_size < CONFIG_MAX_MEM_MAPPED)
- *dmm_lisa_regs = &lisa_map_2G_x_2;
- else
- *dmm_lisa_regs = &lisa_map_2G_x_4;
- break;
- }
-}
-
-struct vcores_data dra752_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra76x_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = LP87565_REG_ADDR_BUCK01,
- .mpu.pmic = &lp87565,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS65917_REG_ADDR_SMPS1,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = LP87565_REG_ADDR_BUCK23,
- .gpu.pmic = &lp87565,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS65917_REG_ADDR_SMPS3,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS65917_REG_ADDR_SMPS4,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS65917_REG_ADDR_SMPS1,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS65917_REG_ADDR_SMPS2,
- .core.pmic = &tps659038,
-
- /*
- * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
- * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
- */
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS65917_REG_ADDR_SMPS3,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS65917_REG_ADDR_SMPS3,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS65917_REG_ADDR_SMPS3,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra718_volts = {
- /*
- * In the case of dra71x GPU MPU and CORE
- * are all powered up by BUCK0 of LP873X PMIC
- */
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = LP873X_REG_ADDR_BUCK0,
- .mpu.pmic = &lp8733,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = LP873X_REG_ADDR_BUCK0,
- .core.pmic = &lp8733,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = LP873X_REG_ADDR_BUCK0,
- .gpu.pmic = &lp8733,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- /*
- * The DSPEVE and IVA rails are grouped on DRA71x-evm
- * and are powered by BUCK1 of LP873X PMIC
- */
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = LP873X_REG_ADDR_BUCK1,
- .eve.pmic = &lp8733,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = LP873X_REG_ADDR_BUCK1,
- .iva.pmic = &lp8733,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-int get_voltrail_opp(int rail_offset)
-{
- int opp;
-
- switch (rail_offset) {
- case VOLT_MPU:
- opp = DRA7_MPU_OPP;
- /* DRA71x supports only OPP_NOM for MPU */
- if (board_is_dra71x_evm())
- opp = OPP_NOM;
- break;
- case VOLT_CORE:
- opp = DRA7_CORE_OPP;
- /* DRA71x supports only OPP_NOM for CORE */
- if (board_is_dra71x_evm())
- opp = OPP_NOM;
- break;
- case VOLT_GPU:
- opp = DRA7_GPU_OPP;
- /* DRA71x supports only OPP_NOM for GPU */
- if (board_is_dra71x_evm())
- opp = OPP_NOM;
- break;
- case VOLT_EVE:
- opp = DRA7_DSPEVE_OPP;
- /*
- * DRA71x does not support OPP_OD for EVE.
- * If OPP_OD is selected by menuconfig, fallback
- * to OPP_NOM.
- */
- if (board_is_dra71x_evm() && opp == OPP_OD)
- opp = OPP_NOM;
- break;
- case VOLT_IVA:
- opp = DRA7_IVA_OPP;
- /*
- * DRA71x does not support OPP_OD for IVA.
- * If OPP_OD is selected by menuconfig, fallback
- * to OPP_NOM.
- */
- if (board_is_dra71x_evm() && opp == OPP_OD)
- opp = OPP_NOM;
- break;
- default:
- opp = OPP_NOM;
- }
-
- return opp;
-}
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- u64 ram_size;
-
- ram_size = board_ti_get_emif_size();
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_effective_memsize();
- if (ram_size > CONFIG_MAX_MEM_MAPPED) {
- gd->bd->bi_dram[1].start = 0x200000000;
- gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
- }
-
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- char *name = "unknown";
-
- if (is_dra72x()) {
- if (board_is_dra72x_revc_or_later())
- name = "dra72x-revc";
- else if (board_is_dra71x_evm())
- name = "dra71x";
- else
- name = "dra72x";
- } else if (is_dra76x_abz()) {
- name = "dra76x_abz";
- } else if (is_dra76x_acd()) {
- name = "dra76x_acd";
- } else {
- name = "dra7xx";
- }
-
- set_board_info_env(name);
-
- /*
- * Default FIT boot on HS devices. Non FIT images are not allowed
- * on HS devices.
- */
- if (get_device_type() == HS_DEVICE)
- env_set("boot_fit", "1");
-
- omap_die_id_serial();
- omap_set_fastboot_vars();
-
- /*
- * Hook the LDO1 regulator to EN pin. This applies only to LP8733
- * Rest all regulators are hooked to EN Pin at reset.
- */
- if (board_is_dra71x_evm())
- palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void do_board_detect(void)
-{
- int rc;
-
- rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- printf("ti_i2c_eeprom_init failed %d\n", rc);
-}
-
-#else
-
-void do_board_detect(void)
-{
- char *bname = NULL;
- int rc;
-
- rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- printf("ti_i2c_eeprom_init failed %d\n", rc);
-
- if (board_is_dra74x_evm()) {
- bname = "DRA74x EVM";
- } else if (board_is_dra72x_evm()) {
- bname = "DRA72x EVM";
- } else if (board_is_dra71x_evm()) {
- bname = "DRA71x EVM";
- } else if (board_is_dra76x_evm()) {
- bname = "DRA76x EVM";
- } else {
- /* If EEPROM is not populated */
- if (is_dra72x())
- bname = "DRA72x EVM";
- else
- bname = "DRA74x EVM";
- }
-
- if (bname)
- snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
- "Board: %s REV %s\n", bname, board_ti_get_rev());
-}
-#endif /* CONFIG_SPL_BUILD */
-
-void vcores_init(void)
-{
- if (board_is_dra74x_evm()) {
- *omap_vcores = &dra752_volts;
- } else if (board_is_dra72x_evm()) {
- *omap_vcores = &dra722_volts;
- } else if (board_is_dra71x_evm()) {
- *omap_vcores = &dra718_volts;
- } else if (board_is_dra76x_evm()) {
- *omap_vcores = &dra76x_volts;
- } else {
- /* If EEPROM is not populated */
- if (is_dra72x())
- *omap_vcores = &dra722_volts;
- else
- *omap_vcores = &dra752_volts;
- }
-}
-
-void set_muxconf_regs(void)
-{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- early_padconf, ARRAY_SIZE(early_padconf));
-}
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-void recalibrate_iodelay(void)
-{
- struct pad_conf_entry const *pads, *delta_pads = NULL;
- struct iodelay_cfg_entry const *iodelay;
- int npads, niodelays, delta_npads = 0;
- int ret;
-
- switch (omap_revision()) {
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- case DRA722_ES2_1:
- pads = dra72x_core_padconf_array_common;
- npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
- if (board_is_dra71x_evm()) {
- pads = dra71x_core_padconf_array;
- npads = ARRAY_SIZE(dra71x_core_padconf_array);
- iodelay = dra71_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
- } else if (board_is_dra72x_revc_or_later()) {
- delta_pads = dra72x_rgmii_padconf_array_revc;
- delta_npads =
- ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
- iodelay = dra72_iodelay_cfg_array_revc;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
- } else {
- delta_pads = dra72x_rgmii_padconf_array_revb;
- delta_npads =
- ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
- iodelay = dra72_iodelay_cfg_array_revb;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
- }
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- pads = dra74x_core_padconf_array;
- npads = ARRAY_SIZE(dra74x_core_padconf_array);
- iodelay = dra742_es1_1_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
- break;
- case DRA762_ACD_ES1_0:
- case DRA762_ES1_0:
- pads = dra76x_core_padconf_array;
- npads = ARRAY_SIZE(dra76x_core_padconf_array);
- iodelay = dra76x_es1_0_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
- break;
- default:
- case DRA752_ES2_0:
- case DRA762_ABZ_ES1_0:
- pads = dra74x_core_padconf_array;
- npads = ARRAY_SIZE(dra74x_core_padconf_array);
- iodelay = dra742_es2_0_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
- /* Setup port1 and port2 for rgmii with 'no-id' mode */
- clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
- RGMII1_ID_MODE_N_MASK);
- break;
- }
- /* Setup I/O isolation */
- ret = __recalibrate_iodelay_start();
- if (ret)
- goto err;
-
- /* Do the muxing here */
- do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
-
- /* Now do the weird minor deltas that should be safe */
- if (delta_npads)
- do_set_mux32((*ctrl)->control_padconf_core_base,
- delta_pads, delta_npads);
-
- if (is_dra76x())
- /* Set mux for MCAN instead of DCAN1 */
- clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
- MCAN_SEL_ALT_MASK, MCAN_SEL);
-
- /* Setup IOdelay configuration */
- ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
-err:
- /* Closeup.. remove isolation */
- __recalibrate_iodelay_end(ret);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-
-void board_mmc_poweron_ldo(uint voltage)
-{
- if (board_is_dra71x_evm()) {
- if (voltage == LDO_VOLT_3V0)
- voltage = 0x19;
- else if (voltage == LDO_VOLT_1V8)
- voltage = 0xa;
- lp873x_mmc1_poweron_ldo(voltage);
- } else if (board_is_dra76x_evm()) {
- palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
- } else {
- palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
- }
-}
-
-static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
- .hw_rev = "rev11",
- .unsupported_caps = MMC_CAP(MMC_HS_200) |
- MMC_CAP(UHS_SDR104),
- .max_freq = 96000000,
-};
-
-static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
- .hw_rev = "rev11",
- .unsupported_caps = MMC_CAP(MMC_HS_200) |
- MMC_CAP(UHS_SDR104) |
- MMC_CAP(UHS_SDR50),
- .max_freq = 48000000,
-};
-
-const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
-{
- switch (omap_revision()) {
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- if (addr == OMAP_HSMMC1_BASE)
- return &dra7x_es1_1_mmc1_fixups;
- else
- return &dra7x_es1_1_mmc23_fixups;
- default:
- return NULL;
- }
-}
-#endif
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
- .maximum_speed = USB_SPEED_SUPER,
- .base = DRA7_USB_OTG_SS1_BASE,
- .tx_fifo_resize = false,
- .index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
- .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
- .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
- .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
- .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
- .index = 0,
-};
-
-static struct dwc3_device usb_otg_ss2 = {
- .maximum_speed = USB_SPEED_SUPER,
- .base = DRA7_USB_OTG_SS2_BASE,
- .tx_fifo_resize = false,
- .index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
- .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
- .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
- .index = 1,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- enable_usb_clocks(index);
- switch (index) {
- case 0:
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- }
-
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- dwc3_uboot_init(&usb_otg_ss1);
- break;
- case 1:
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- }
-
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
- break;
- default:
- printf("Invalid Controller Index\n");
- }
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- switch (index) {
- case 0:
- case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
- break;
- default:
- printf("Invalid Controller Index\n");
- }
- disable_usb_clocks(index);
- return 0;
-}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_load();
- if (env_get_yesno("boot_os") != 1)
- return 1;
-#endif
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-extern u32 *const omap_si_rev;
-
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 2,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 3,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 2,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
- uint32_t ctrl_val;
-
- /* try reading mac address from efuse */
- mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-
- ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
- ctrl_val |= 0x22;
- writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
- if (*omap_si_rev == DRA722_ES1_0)
- cpsw_data.active_slave = 1;
-
- if (board_is_dra72x_revc_or_later()) {
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
- }
-
- ret = cpsw_register(&cpsw_data);
- if (ret < 0)
- printf("Error %d registering CPSW switch\n", ret);
-
- return ret;
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-/* VTT regulator enable */
-static inline void vtt_regulator_enable(void)
-{
- if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
- return;
-
- /* Do not enable VTT for DRA722 or DRA76x */
- if (is_dra72x() || is_dra76x())
- return;
-
- /*
- * EVM Rev G and later use gpio7_11 for DDR3 termination.
- * This is safe enough to do on older revs.
- */
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-}
-
-int board_early_init_f(void)
-{
- vtt_regulator_enable();
- return 0;
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- if (is_dra72x()) {
- if (board_is_dra71x_evm()) {
- if (!strcmp(name, "dra71-evm"))
- return 0;
- }else if(board_is_dra72x_revc_or_later()) {
- if (!strcmp(name, "dra72-evm-revc"))
- return 0;
- } else if (!strcmp(name, "dra72-evm")) {
- return 0;
- }
- } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
- return 0;
- } else if (!is_dra72x() && !is_dra76x_acd() &&
- !strcmp(name, "dra7-evm")) {
- return 0;
- }
-
- return -1;
-}
-#endif
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
-{
- secure_boot_verify_image(p_image, p_size);
-}
-
-void board_tee_image_process(ulong tee_image, size_t tee_size)
-{
- secure_tee_install((u32)tee_image);
-}
-
-#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
-int fastboot_set_reboot_flag(void)
-{
- printf("Setting reboot to fastboot flag ...\n");
- env_set("dofastboot", "1");
- env_save();
- return 0;
-}
-#endif
-
-U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
-#endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
deleted file mode 100644
index f1f6bd53167..00000000000
--- a/board/ti/dra7xx/mux_data.h
+++ /dev/null
@@ -1,1121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- * Nishant Kamat <nskamat@ti.com>
- */
-#ifndef _MUX_DATA_DRA7XX_H_
-#define _MUX_DATA_DRA7XX_H_
-
-#include <asm/arch/mux_dra7xx.h>
-
-const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
- {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
- {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
- {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
- {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
- {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
- {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
- {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
- {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
- {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
- {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
- {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
- {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
- {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
- {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
- {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
-};
-
-const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
- {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
- {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
-};
-
-const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
- {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
-};
-
-const struct pad_conf_entry dra71x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
- {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
- {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
- {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
- {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
- {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
- {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
- {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
- {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
- {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
- {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
- {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
- {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
- {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
- {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
- {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
- {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
- {MCASP1_ACLKX, (M14 | PIN_INPUT)}, /* mcasp1_aclkx.gpio7_31 */
- {MCASP1_FSX, (M14 | 0x000d0000)}, /* mcasp1_fsx.gpio7_30 */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS1, (M14 | PIN_INPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
-};
-
-const struct pad_conf_entry early_padconf[] = {
- {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
- {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
- {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
- {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
- {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
-};
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
- {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
- {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
- {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
- {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
- {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
- {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
- {0x740, 0, 220}, /* RGMMI0_TXC_OUT */
- {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
- {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
- {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
- {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
- {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
- /* These values are for using RGMII1 configuration on VIN2a_x pins. */
- {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
- {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
- {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
- {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
- {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
- {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
- {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
- {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
- {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
- {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
- {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
- {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
- {0x144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */
- {0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */
- {0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */
- {0x170, 0, 0 }, /* CFG_GPMC_A16_OUT */
- {0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */
- {0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
-};
-
-const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
- {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
- {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
-};
-
-const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
- {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
- {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
- {0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
- {0x0A50, 2031, 0}, /* CFG_VIN2A_D10_IN */
- {0x0A5C, 1702, 0}, /* CFG_VIN2A_D11_IN */
- {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
- {0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
- {0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
- {0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
- {0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
- {0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
- {0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
- {0x0B4C, 1224, 618}, /* CFG_VIN2A_D8_IN */
- {0x0B58, 1373, 509}, /* CFG_VIN2A_D9_IN */
- {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
- {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
-};
-#endif
-
-const struct pad_conf_entry dra74x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
- {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
- {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
- {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
- {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
- {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
- {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
- {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
- {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
- {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
- {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
- {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
- {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
- {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
- {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
- {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
- {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
- {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
- {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
- {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
- {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
- {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
- {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
- {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
- {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
- {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
- {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
- {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
- {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
- {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
- {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
- {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
- {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
- {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
- {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
- {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
- {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
-};
-
-const struct pad_conf_entry dra76x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs3.vout3_clk */
- {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpmc_advn_ale */
- {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */
- {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */
- {GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpmc_ben0 */
- {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */
- {VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin1a_fld0.gpio3_1 */
- {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
- {VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_de0.Driveroff */
- {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
- {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
- {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
- {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
- {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
- {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
- {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
- {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
- {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
- {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
- {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
- {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d8.vin2a_d8 */
- {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d9.vin2a_d9 */
- {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d10.vin2a_d10 */
- {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d11.vin2a_d11 */
- {VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_de.vout1_de */
- {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
- {MCASP1_ACLKX, (M14 | 0x00070000)}, /* mcasp1_aclkx.gpio7_31 */
- {MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.gpio7_30 */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | 0x000f0000)}, /* mcasp1_axr1.i2c5_scl */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)}, /* mcasp2_aclkr.Driveroff */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
- {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
- {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
- {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */
- {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
-};
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
- {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
- {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
- {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
- {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
- {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
- {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
- {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
- {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
- {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
- {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
- {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
- {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
- {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
- {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
- {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
- {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
- {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
- {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
- {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
- {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
- {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
- {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
- {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
- {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
- {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
- {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
- {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
- {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
- {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
- {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
- {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
- {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
- {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
- {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
- {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
-};
-
-const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
- {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */
- {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
- {0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */
- {0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */
- {0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */
- {0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */
- {0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */
- {0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */
- {0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */
- {0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */
- {0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */
- {0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */
- {0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */
- {0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */
- {0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */
- {0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */
- {0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */
- {0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */
- {0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */
- {0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */
- {0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */
- {0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */
- {0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */
- {0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */
- {0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */
- {0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */
- {0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */
- {0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */
- {0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */
- {0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */
- {0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
- {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
- {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
- {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
- {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
-};
-
-const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
- {0x011C, 787, 0}, /* CFG_GPMC_A0_OUT */
- {0x0128, 1181, 0}, /* CFG_GPMC_A10_OUT */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
- {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
- {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x01A0, 592, 0}, /* CFG_GPMC_A1_OUT */
- {0x020C, 641, 0}, /* CFG_GPMC_A2_OUT */
- {0x0218, 1481, 0}, /* CFG_GPMC_A3_OUT */
- {0x0224, 1775, 0}, /* CFG_GPMC_A4_OUT */
- {0x0230, 785, 0}, /* CFG_GPMC_A5_OUT */
- {0x023C, 848, 0}, /* CFG_GPMC_A6_OUT */
- {0x0248, 851, 0}, /* CFG_GPMC_A7_OUT */
- {0x0254, 1783, 0}, /* CFG_GPMC_A8_OUT */
- {0x0260, 951, 0}, /* CFG_GPMC_A9_OUT */
- {0x026C, 1091, 0}, /* CFG_GPMC_AD0_OUT */
- {0x0278, 1027, 0}, /* CFG_GPMC_AD10_OUT */
- {0x0284, 824, 0}, /* CFG_GPMC_AD11_OUT */
- {0x0290, 1196, 0}, /* CFG_GPMC_AD12_OUT */
- {0x029C, 754, 0}, /* CFG_GPMC_AD13_OUT */
- {0x02A8, 665, 0}, /* CFG_GPMC_AD14_OUT */
- {0x02B4, 1027, 0}, /* CFG_GPMC_AD15_OUT */
- {0x02C0, 937, 0}, /* CFG_GPMC_AD1_OUT */
- {0x02CC, 1168, 0}, /* CFG_GPMC_AD2_OUT */
- {0x02D8, 872, 0}, /* CFG_GPMC_AD3_OUT */
- {0x02E4, 1092, 0}, /* CFG_GPMC_AD4_OUT */
- {0x02F0, 576, 0}, /* CFG_GPMC_AD5_OUT */
- {0x02FC, 1113, 0}, /* CFG_GPMC_AD6_OUT */
- {0x0308, 943, 0}, /* CFG_GPMC_AD7_OUT */
- {0x0314, 0, 0}, /* CFG_GPMC_AD8_OUT */
- {0x0320, 0, 0}, /* CFG_GPMC_AD9_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
- {0x0380, 1801, 948}, /* CFG_GPMC_CS3_OUT */
- {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
- {0x0A44, 2180, 0}, /* CFG_VIN2A_D0_IN */
- {0x0A50, 2297, 110}, /* CFG_VIN2A_D10_IN */
- {0x0A5C, 1938, 0}, /* CFG_VIN2A_D11_IN */
- {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2326, 309}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
- {0x0B04, 2057, 0}, /* CFG_VIN2A_D2_IN */
- {0x0B10, 2440, 257}, /* CFG_VIN2A_D3_IN */
- {0x0B1C, 2142, 0}, /* CFG_VIN2A_D4_IN */
- {0x0B28, 2455, 252}, /* CFG_VIN2A_D5_IN */
- {0x0B34, 1883, 0}, /* CFG_VIN2A_D6_IN */
- {0x0B40, 2229, 0}, /* CFG_VIN2A_D7_IN */
- {0x0B4C, 2250, 151}, /* CFG_VIN2A_D8_IN */
- {0x0B58, 2279, 27}, /* CFG_VIN2A_D9_IN */
- {0x0B7C, 2233, 0}, /* CFG_VIN2A_HSYNC0_IN */
- {0x0B88, 1936, 0}, /* CFG_VIN2A_VSYNC0_IN */
- {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
- {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
- {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
- {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
- {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
- {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
- {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
- {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
- {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
- {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
- {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
- {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
- {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
- {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
- {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
- {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
- {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
- {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
- {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
- {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
- {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
- {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
- {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
- {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
- {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
- {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
- {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
- {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
-};
-#endif
-
-#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
deleted file mode 100644
index 27f6b5d981f..00000000000
--- a/configs/dra7xx_evm_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_SPL=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_DWC_AHCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_GPIO=y
-CONFIG_PCF8575_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_SPL_MMC_HS200_SUPPORT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_SPL_PHY=y
-CONFIG_PIPE3_PHY=y
-CONFIG_PMIC_PALMAS=y
-CONFIG_PMIC_LP873X=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_PALMAS=y
-CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DRA7XX_INDEX=1
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
deleted file mode 100644
index 651fc4fb427..00000000000
--- a/configs/dra7xx_hs_evm_defconfig
+++ /dev/null
@@ -1,101 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_OMAP54XX=y
-CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
-CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
-CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_IMAGE_POST_PROCESS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
-CONFIG_DWC_AHCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_GPIO=y
-CONFIG_PCF8575_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_SPL_PHY=y
-CONFIG_PIPE3_PHY=y
-CONFIG_PMIC_PALMAS=y
-CONFIG_PMIC_LP873X=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_PALMAS=y
-CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DRA7XX_INDEX=1
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
deleted file mode 100644
index 2d8758db754..00000000000
--- a/include/configs/dra7xx_evm.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * Configuration settings for the TI DRA7XX board.
- * See ti_omap5_common.h for omap5 common settings.
- */
-
-#ifndef __CONFIG_DRA7XX_EVM_H
-#define __CONFIG_DRA7XX_EVM_H
-
-#include <environment/ti/dfu.h>
-
-#define CONFIG_IODELAY_RECALIBRATION
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED 0x80000000
-
-#ifndef CONFIG_QSPI_BOOT
-/* MMC ENV related defines */
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#endif
-
-#if (CONFIG_CONS_INDEX == 1)
-#define CONSOLEDEV "ttyO0"
-#elif (CONFIG_CONS_INDEX == 3)
-#define CONSOLEDEV "ttyO2"
-#endif
-#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-#define CONFIG_SYS_OMAP_ABE_SYSCK
-
-#ifndef CONFIG_SPL_BUILD
-#define DFUARGS \
- "dfu_bufsiz=0x10000\0" \
- DFU_ALT_INFO_MMC \
- DFU_ALT_INFO_EMMC \
- DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_QSPI
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_CMD_BOOTD
-#ifdef CONFIG_SPL_DFU_SUPPORT
-#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
-#define DFUARGS \
- "dfu_bufsiz=0x10000\0" \
- DFU_ALT_INFO_RAM
-#endif
-#endif
-
-#include <configs/ti_omap5_common.h>
-
-/* Enhance our eMMC support / experience. */
-#define CONFIG_HSMMC2_8BIT
-
-/* CPSW Ethernet */
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_TI
-
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_SF_DEFAULT_SPEED 76800000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_QSPI_QUAD_SUPPORT
-
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SIZE (64 << 10)
-#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
-#define CONFIG_ENV_OFFSET 0x1C0000
-#define CONFIG_ENV_OFFSET_REDUND 0x1D0000
-#endif
-
-/* SPI SPL */
-#define CONFIG_TI_EDMA3
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
-
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-/* USB xHCI HOST */
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_OMAP_USB2PHY2_HOST
-
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-/* NAND support */
-#ifdef CONFIG_NAND
-/* NAND: device related configs */
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-/* NAND: SPL related configs */
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
-#endif
-#endif /* !CONFIG_NAND */
-
-/* Parallel NOR Support */
-#if defined(CONFIG_NOR)
-/* NOR: device related configs */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
-/* #define CONFIG_INIT_IGNORE_ERROR */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#endif
-#endif /* NOR support */
-
-#endif /* __CONFIG_DRA7XX_EVM_H */
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 91/93] dm: Enable CONFIG_BLK
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (89 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 90/93] arm: Remove dra7xx_evm and dra7xx_hs_evm boards Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 92/93] dm: Update driver-model migration schedule for CONFIG_BLK Simon Glass
` (6 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
As per the migration plan in MIGRATION.txt all boards should now be
migrated to use CONFIG_BLK.
Enable the CONFIG_BLK option for all boards that use CONFIG_DM. Allow
sandbox_noblk to continue to build until migration is complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
drivers/block/Kconfig | 2 +-
drivers/mmc/Kconfig | 2 +-
drivers/usb/Kconfig | 1 +
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 33f4aa24185..2e6b87a48a7 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,7 +1,7 @@
config BLK
bool "Support block devices"
depends on DM
- default y if DM_MMC
+ default y
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 27246ee4658..1ec23145aa3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -26,6 +26,7 @@ config MMC_BROKEN_CD
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
+ default y && !SANDBOX # Allow sandbox_noblk to work
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
@@ -36,7 +37,6 @@ config DM_MMC
config SPL_DM_MMC
bool "Enable MMC controllers using Driver Model in SPL"
depends on SPL_DM && DM_MMC
- default y
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 4fbe172e05c..38b8e2e5f5d 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -36,6 +36,7 @@ if USB
config DM_USB
bool "Enable driver model for USB"
depends on USB && DM
+ default y if !SANDBOX # Allow sandbox_noblk to work
help
Enable driver model for USB. The USB interface is then implemented
by the USB uclass. Multiple USB controllers of different types
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 92/93] dm: Update driver-model migration schedule for CONFIG_BLK
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (90 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 91/93] dm: Enable CONFIG_BLK Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 15:54 ` [U-Boot] [PATCH 93/93] RFC: dm: Force CONFIG_BLK for all boards with DM Simon Glass
` (5 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
The deadline has passed, so add a note to indicate that board removal is
in progress.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
doc/driver-model/MIGRATION.txt | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/MIGRATION.txt
index 5ebefd608b9..b0f8b410ae8 100644
--- a/doc/driver-model/MIGRATION.txt
+++ b/doc/driver-model/MIGRATION.txt
@@ -10,15 +10,15 @@ CONFIG_BLK
----------
Status: In progress
-Deadline: 2018.05
+Deadline: 2018.05 (passed)
-Maintainers should submit patches for enabling CONFIG_BLK on all boards in
-time for inclusion in the 2018.05 release. Boards not converted by this
-time may be removed in a subsequent release.
+Boards which do not build with CONFIG_BLK enabled for U-Boot proper are being
+removed at present.
Note that this implies use of driver model for all block devices (e.g.
MMC, USB, SCSI, SATA).
+
CONFIG_DM_SPI
CONFIG_DM_SPI_FLASH
-------------------
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 93/93] RFC: dm: Force CONFIG_BLK for all boards with DM
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (91 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 92/93] dm: Update driver-model migration schedule for CONFIG_BLK Simon Glass
@ 2018-11-19 15:54 ` Simon Glass
2018-11-19 16:08 ` [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Otavio Salvador
` (4 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 15:54 UTC (permalink / raw)
To: u-boot
This forces CONFIG_BLK to be used for all boards. At present it causes
significant fallout.
(This is not intended to be applied, just for testing)
Signed-off-by: Simon Glass <sjg@chromium.org>
---
drivers/core/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index e8ba20ca82d..daaafb187dc 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -2,6 +2,7 @@ menu "Generic Driver Options"
config DM
bool "Enable Driver Model"
+ select BLK
help
This config option enables Driver Model. This brings in the core
support, including scanning of platform data on start-up. If
--
2.19.1.1215.g8438c0b245-goog
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (92 preceding siblings ...)
2018-11-19 15:54 ` [U-Boot] [PATCH 93/93] RFC: dm: Force CONFIG_BLK for all boards with DM Simon Glass
@ 2018-11-19 16:08 ` Otavio Salvador
2018-11-19 18:36 ` Tom Rini
` (3 subsequent siblings)
97 siblings, 0 replies; 211+ messages in thread
From: Otavio Salvador @ 2018-11-19 16:08 UTC (permalink / raw)
To: u-boot
Hello Simon,
On Mon, Nov 19, 2018 at 1:52 PM Simon Glass <sjg@chromium.org> wrote:
> All boards should now be migrated to use CONFIG_BLK. This series removes
> those with build problems using this option.
I understand and support the goal here but it seems a little abrupt to
send it on a short notice. It'd be nice if the build were triggering a
build warning to notify about the deadline. I wasn't aware of the
deadline.
--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (93 preceding siblings ...)
2018-11-19 16:08 ` [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Otavio Salvador
@ 2018-11-19 18:36 ` Tom Rini
2018-11-19 19:45 ` Adam Ford
2018-11-20 12:42 ` Soeren Moch
` (2 subsequent siblings)
97 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-19 18:36 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>
> All boards should now be migrated to use CONFIG_BLK. This series removes
> those with build problems using this option.
>
> If maintainers want to keep these boards in they should send a patch in
> the next week or two. Otherwise the board will be removed in the next
> release, and will need to be added and re-reviewed later.
>
> The goal is to have all boards use driver model. But so far, we do allow
> CONFIG_DM to not be defined.
>
> PLEASE NOTE: This is not an easy process. It is possible that your board
> does work, or works with only minor changes. Please try to understand that
> the removal of a board is not done because people don't like your board.
> In fact the board might have been the first one I used when trying out
> U-Boot! It's just that we expect maintainers to keep up with the migration
> to driver model which has been running now for 4 years. It just isn't
> possible for a few people to migrate and test hundreds of boards.
>
> So, send a patch!
OK, so with the intention of "need to light a fire", consider the fire
lit! But, I think v2 of this series needs to:
- Address the bug that's been noted of you checking on "DM_BLK" when
it's really just "BLK".
- Do a test build with BLK just being unconditional now. For example,
you're deleting the am335x_evm family but it builds fine with BLK
being enabled now. I even gave it a run time test via test.py and
we're fine. So, I think a new run where you see what fails to build
with BLK enabled by default now is in order to come up with a new
delete list.
Thanks!
--
Tom
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 18:36 ` Tom Rini
@ 2018-11-19 19:45 ` Adam Ford
2018-11-19 21:32 ` Marek Vasut
0 siblings, 1 reply; 211+ messages in thread
From: Adam Ford @ 2018-11-19 19:45 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > All boards should now be migrated to use CONFIG_BLK. This series removes
> > those with build problems using this option.
> >
> > If maintainers want to keep these boards in they should send a patch in
> > the next week or two. Otherwise the board will be removed in the next
> > release, and will need to be added and re-reviewed later.
> >
> > The goal is to have all boards use driver model. But so far, we do allow
> > CONFIG_DM to not be defined.
> >
> > PLEASE NOTE: This is not an easy process. It is possible that your board
> > does work, or works with only minor changes. Please try to understand that
> > the removal of a board is not done because people don't like your board.
> > In fact the board might have been the first one I used when trying out
> > U-Boot! It's just that we expect maintainers to keep up with the migration
> > to driver model which has been running now for 4 years. It just isn't
> > possible for a few people to migrate and test hundreds of boards.
> >
> > So, send a patch!
>
> OK, so with the intention of "need to light a fire", consider the fire
> lit! But, I think v2 of this series needs to:
> - Address the bug that's been noted of you checking on "DM_BLK" when
> it's really just "BLK".
> - Do a test build with BLK just being unconditional now. For example,
> you're deleting the am335x_evm family but it builds fine with BLK
> being enabled now. I even gave it a run time test via test.py and
> we're fine. So, I think a new run where you see what fails to build
> with BLK enabled by default now is in order to come up with a new
> delete list.
>
When we were migrating toward GCC 6, we introduced a warning message
that was displayed at build indicating older versions of GCC would be
unsupported, and GCC 6 would become a requirement. The
CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
removed. I would like to propose that in the future, when setting
deadlines, we insert something into the build mechanism that generates
a warning to tell people that something is going to happen.
Just my 2-cents.
adam
> Thanks!
>
> --
> Tom
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 19:45 ` Adam Ford
@ 2018-11-19 21:32 ` Marek Vasut
2018-11-19 21:54 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Marek Vasut @ 2018-11-19 21:32 UTC (permalink / raw)
To: u-boot
On 11/19/2018 08:45 PM, Adam Ford wrote:
> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
>>
>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>>>
>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>> those with build problems using this option.
>>>
>>> If maintainers want to keep these boards in they should send a patch in
>>> the next week or two. Otherwise the board will be removed in the next
>>> release, and will need to be added and re-reviewed later.
>>>
>>> The goal is to have all boards use driver model. But so far, we do allow
>>> CONFIG_DM to not be defined.
>>>
>>> PLEASE NOTE: This is not an easy process. It is possible that your board
>>> does work, or works with only minor changes. Please try to understand that
>>> the removal of a board is not done because people don't like your board.
>>> In fact the board might have been the first one I used when trying out
>>> U-Boot! It's just that we expect maintainers to keep up with the migration
>>> to driver model which has been running now for 4 years. It just isn't
>>> possible for a few people to migrate and test hundreds of boards.
>>>
>>> So, send a patch!
>>
>> OK, so with the intention of "need to light a fire", consider the fire
>> lit! But, I think v2 of this series needs to:
>> - Address the bug that's been noted of you checking on "DM_BLK" when
>> it's really just "BLK".
>> - Do a test build with BLK just being unconditional now. For example,
>> you're deleting the am335x_evm family but it builds fine with BLK
>> being enabled now. I even gave it a run time test via test.py and
>> we're fine. So, I think a new run where you see what fails to build
>> with BLK enabled by default now is in order to come up with a new
>> delete list.
>>
>
> When we were migrating toward GCC 6, we introduced a warning message
> that was displayed at build indicating older versions of GCC would be
> unsupported, and GCC 6 would become a requirement. The
> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> removed. I would like to propose that in the future, when setting
> deadlines, we insert something into the build mechanism that generates
> a warning to tell people that something is going to happen.
I agree, that sounds good.
I am extremely unhappy by how Simon decided, unilaterally, some
arbitrary deadline, told pretty much no one about that deadline and then
put a knife on many peoples' throats by sending out this series which
removes boards that are actively used and maintained, demanding they be
converted right this instant.
In my opinion, most maintainers cannot just drop everything they are
working on at any given point and start doing random conversion the
minute Simon decides they should. The only result of such behavior will
be loss of functionality and more stress exerted on the maintainers,
which helps no one.
While I understand the need to move over to CONFIG_DM_BLK, U-Boot is a
cooperative project and it can only move forward as fast as the
community around it can. If anyone within that community wants to
convert others to some new feature, that's perfectly fine, but there
should be a clear way to do it and a possibility to shift a deadline for
conversion around for boards which are useful to people and simply late.
Just dropping useful functionality is not acceptable.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 21:32 ` Marek Vasut
@ 2018-11-19 21:54 ` Tom Rini
2018-11-19 21:58 ` Simon Glass
` (2 more replies)
0 siblings, 3 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-19 21:54 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> On 11/19/2018 08:45 PM, Adam Ford wrote:
> > On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> >>
> >> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> >>>
> >>> All boards should now be migrated to use CONFIG_BLK. This series removes
> >>> those with build problems using this option.
> >>>
> >>> If maintainers want to keep these boards in they should send a patch in
> >>> the next week or two. Otherwise the board will be removed in the next
> >>> release, and will need to be added and re-reviewed later.
> >>>
> >>> The goal is to have all boards use driver model. But so far, we do allow
> >>> CONFIG_DM to not be defined.
> >>>
> >>> PLEASE NOTE: This is not an easy process. It is possible that your board
> >>> does work, or works with only minor changes. Please try to understand that
> >>> the removal of a board is not done because people don't like your board.
> >>> In fact the board might have been the first one I used when trying out
> >>> U-Boot! It's just that we expect maintainers to keep up with the migration
> >>> to driver model which has been running now for 4 years. It just isn't
> >>> possible for a few people to migrate and test hundreds of boards.
> >>>
> >>> So, send a patch!
> >>
> >> OK, so with the intention of "need to light a fire", consider the fire
> >> lit! But, I think v2 of this series needs to:
> >> - Address the bug that's been noted of you checking on "DM_BLK" when
> >> it's really just "BLK".
> >> - Do a test build with BLK just being unconditional now. For example,
> >> you're deleting the am335x_evm family but it builds fine with BLK
> >> being enabled now. I even gave it a run time test via test.py and
> >> we're fine. So, I think a new run where you see what fails to build
> >> with BLK enabled by default now is in order to come up with a new
> >> delete list.
> >>
> >
> > When we were migrating toward GCC 6, we introduced a warning message
> > that was displayed at build indicating older versions of GCC would be
> > unsupported, and GCC 6 would become a requirement. The
> > CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> > removed. I would like to propose that in the future, when setting
> > deadlines, we insert something into the build mechanism that generates
> > a warning to tell people that something is going to happen.
>
> I agree, that sounds good.
>
> I am extremely unhappy by how Simon decided, unilaterally, some
> arbitrary deadline, told pretty much no one about that deadline and then
> put a knife on many peoples' throats by sending out this series which
> removes boards that are actively used and maintained, demanding they be
> converted right this instant.
OK, lets step back for a moment. Part of the problem is that yes, we
(I) never found a good way to make a big scary build warning happen.
But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
moment, which is when we set this deadline, and we had a good bit of
discussion about related issues to make it happen.
I also know that around the v2018.05 release I said, in public, but no I
can't find a link right this moment, that we were pushing off a little
bit on dropping _everything_ right then as there was basically some
fairly important / widely used USB stuff that hadn't been converted yet
(which has since been, I think, otherwise am335x_evm & co wouldn't have
been happy?). I know I did since I can see in the archives a number of
series where maintainers did a bunch of changes to various platforms /
SoCs to turn on BLK right then.
So, no, I don't want to drop a bunch of platforms _right_now_. But we
really need to see what doesn't link anymore with BLK forced on, and
plan from there.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 21:54 ` Tom Rini
@ 2018-11-19 21:58 ` Simon Glass
2018-11-20 14:29 ` Ian Campbell
2018-11-21 4:43 ` Simon Glass
2018-11-19 22:02 ` Adam Ford
2018-11-19 22:05 ` Marek Vasut
2 siblings, 2 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-19 21:58 UTC (permalink / raw)
To: u-boot
Hi,
On Mon, 19 Nov 2018 at 14:54, Tom Rini <trini@konsulko.com> wrote:
>
> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> > On 11/19/2018 08:45 PM, Adam Ford wrote:
> > > On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> > >>
> > >> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> > >>>
> > >>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > >>> those with build problems using this option.
> > >>>
> > >>> If maintainers want to keep these boards in they should send a patch in
> > >>> the next week or two. Otherwise the board will be removed in the next
> > >>> release, and will need to be added and re-reviewed later.
> > >>>
> > >>> The goal is to have all boards use driver model. But so far, we do allow
> > >>> CONFIG_DM to not be defined.
> > >>>
> > >>> PLEASE NOTE: This is not an easy process. It is possible that your board
> > >>> does work, or works with only minor changes. Please try to understand that
> > >>> the removal of a board is not done because people don't like your board.
> > >>> In fact the board might have been the first one I used when trying out
> > >>> U-Boot! It's just that we expect maintainers to keep up with the migration
> > >>> to driver model which has been running now for 4 years. It just isn't
> > >>> possible for a few people to migrate and test hundreds of boards.
> > >>>
> > >>> So, send a patch!
> > >>
> > >> OK, so with the intention of "need to light a fire", consider the fire
> > >> lit! But, I think v2 of this series needs to:
> > >> - Address the bug that's been noted of you checking on "DM_BLK" when
> > >> it's really just "BLK".
> > >> - Do a test build with BLK just being unconditional now. For example,
> > >> you're deleting the am335x_evm family but it builds fine with BLK
> > >> being enabled now. I even gave it a run time test via test.py and
> > >> we're fine. So, I think a new run where you see what fails to build
> > >> with BLK enabled by default now is in order to come up with a new
> > >> delete list.
> > >>
> > >
> > > When we were migrating toward GCC 6, we introduced a warning message
> > > that was displayed at build indicating older versions of GCC would be
> > > unsupported, and GCC 6 would become a requirement. The
> > > CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> > > removed. I would like to propose that in the future, when setting
> > > deadlines, we insert something into the build mechanism that generates
> > > a warning to tell people that something is going to happen.
> >
> > I agree, that sounds good.
> >
> > I am extremely unhappy by how Simon decided, unilaterally, some
> > arbitrary deadline, told pretty much no one about that deadline and then
> > put a knife on many peoples' throats by sending out this series which
> > removes boards that are actively used and maintained, demanding they be
> > converted right this instant.
>
> OK, lets step back for a moment. Part of the problem is that yes, we
> (I) never found a good way to make a big scary build warning happen.
> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> moment, which is when we set this deadline, and we had a good bit of
> discussion about related issues to make it happen.
>
> I also know that around the v2018.05 release I said, in public, but no I
> can't find a link right this moment, that we were pushing off a little
> bit on dropping _everything_ right then as there was basically some
> fairly important / widely used USB stuff that hadn't been converted yet
> (which has since been, I think, otherwise am335x_evm & co wouldn't have
> been happy?). I know I did since I can see in the archives a number of
> series where maintainers did a bunch of changes to various platforms /
> SoCs to turn on BLK right then.
>
> So, no, I don't want to drop a bunch of platforms _right_now_. But we
> really need to see what doesn't link anymore with BLK forced on, and
> plan from there.
Yes, I need to ignore warnings. I saw some boards trying to call
non-DM functions and assumed they all did, but they were just DTC
warnings. I'll see if I can figure out how to turn those off.
So if you didn't know about CONFIG_BLK migration from the June email,
hopefully you see this one :-) If your board is already converted,
please don't worry, I will try to get this right in the v2 series,
which hopefully will be much smaller.
Thank you very much to the many maintainers who have met the deadline
and converted their boards. Apologies to those who converted, and
still got this email.
And please read my note in the cover letter.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 21:58 ` Simon Glass
@ 2018-11-20 14:29 ` Ian Campbell
2018-11-20 14:56 ` Tom Rini
2018-11-21 4:43 ` Simon Glass
1 sibling, 1 reply; 211+ messages in thread
From: Ian Campbell @ 2018-11-20 14:29 UTC (permalink / raw)
To: u-boot
(massively trimmed cc list, leaving the current sunxi custodians and
Hans who is a fellow emeritus custodian)
On Mon, 2018-11-19 at 14:58 -0700, Simon Glass wrote:
> Thank you very much to the many maintainers who have met the deadline
> and converted their boards. Apologies to those who converted, and
> still got this email.
TBH I'm still unsure why I was copied. I stepped down as sunxi
custodian ages ago. I checked in u-boot.git and I am listed in
board/sunxi/MAINTAINERS for Cubieboard and Mele M5, but neither of
those (nor any sunxi board generally) seems to be the subject of this
series. My address doesn't appear anywhere else in the repo.
Do I (or the sunxi folks) need to be doing anything?
Or has ./scripts/get_maintainer.pl just been overzealous somewhere?
Ian.
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 14:29 ` Ian Campbell
@ 2018-11-20 14:56 ` Tom Rini
0 siblings, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-20 14:56 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 02:29:12PM +0000, Ian Campbell wrote:
> (massively trimmed cc list, leaving the current sunxi custodians and
> Hans who is a fellow emeritus custodian)
>
> On Mon, 2018-11-19 at 14:58 -0700, Simon Glass wrote:
> > Thank you very much to the many maintainers who have met the deadline
> > and converted their boards. Apologies to those who converted, and
> > still got this email.
>
> TBH I'm still unsure why I was copied. I stepped down as sunxi
> custodian ages ago. I checked in u-boot.git and I am listed in
> board/sunxi/MAINTAINERS for Cubieboard and Mele M5, but neither of
> those (nor any sunxi board generally) seems to be the subject of this
> series. My address doesn't appear anywhere else in the repo.
>
> Do I (or the sunxi folks) need to be doing anything?
>
> Or has ./scripts/get_maintainer.pl just been overzealous somewhere?
I suspect a script went a bit overzealous somewhere, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 21:58 ` Simon Glass
2018-11-20 14:29 ` Ian Campbell
@ 2018-11-21 4:43 ` Simon Glass
2018-11-21 13:26 ` Tom Rini
1 sibling, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-21 4:43 UTC (permalink / raw)
To: u-boot
Hi again,
On Mon, 19 Nov 2018 at 14:58, Simon Glass <sjg@chromium.org> wrote:
>
> Hi,
>
> On Mon, 19 Nov 2018 at 14:54, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> > > On 11/19/2018 08:45 PM, Adam Ford wrote:
> > > > On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> > > >>
> > > >> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> > > >>>
> > > >>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > >>> those with build problems using this option.
> > > >>>
> > > >>> If maintainers want to keep these boards in they should send a patch in
> > > >>> the next week or two. Otherwise the board will be removed in the next
> > > >>> release, and will need to be added and re-reviewed later.
> > > >>>
> > > >>> The goal is to have all boards use driver model. But so far, we do allow
> > > >>> CONFIG_DM to not be defined.
> > > >>>
> > > >>> PLEASE NOTE: This is not an easy process. It is possible that your board
> > > >>> does work, or works with only minor changes. Please try to understand that
> > > >>> the removal of a board is not done because people don't like your board.
> > > >>> In fact the board might have been the first one I used when trying out
> > > >>> U-Boot! It's just that we expect maintainers to keep up with the migration
> > > >>> to driver model which has been running now for 4 years. It just isn't
> > > >>> possible for a few people to migrate and test hundreds of boards.
> > > >>>
> > > >>> So, send a patch!
> > > >>
> > > >> OK, so with the intention of "need to light a fire", consider the fire
> > > >> lit! But, I think v2 of this series needs to:
> > > >> - Address the bug that's been noted of you checking on "DM_BLK" when
> > > >> it's really just "BLK".
> > > >> - Do a test build with BLK just being unconditional now. For example,
> > > >> you're deleting the am335x_evm family but it builds fine with BLK
> > > >> being enabled now. I even gave it a run time test via test.py and
> > > >> we're fine. So, I think a new run where you see what fails to build
> > > >> with BLK enabled by default now is in order to come up with a new
> > > >> delete list.
> > > >>
> > > >
> > > > When we were migrating toward GCC 6, we introduced a warning message
> > > > that was displayed at build indicating older versions of GCC would be
> > > > unsupported, and GCC 6 would become a requirement. The
> > > > CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> > > > removed. I would like to propose that in the future, when setting
> > > > deadlines, we insert something into the build mechanism that generates
> > > > a warning to tell people that something is going to happen.
> > >
> > > I agree, that sounds good.
> > >
> > > I am extremely unhappy by how Simon decided, unilaterally, some
> > > arbitrary deadline, told pretty much no one about that deadline and then
> > > put a knife on many peoples' throats by sending out this series which
> > > removes boards that are actively used and maintained, demanding they be
> > > converted right this instant.
> >
> > OK, lets step back for a moment. Part of the problem is that yes, we
> > (I) never found a good way to make a big scary build warning happen.
> > But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> > moment, which is when we set this deadline, and we had a good bit of
> > discussion about related issues to make it happen.
> >
> > I also know that around the v2018.05 release I said, in public, but no I
> > can't find a link right this moment, that we were pushing off a little
> > bit on dropping _everything_ right then as there was basically some
> > fairly important / widely used USB stuff that hadn't been converted yet
> > (which has since been, I think, otherwise am335x_evm & co wouldn't have
> > been happy?). I know I did since I can see in the archives a number of
> > series where maintainers did a bunch of changes to various platforms /
> > SoCs to turn on BLK right then.
> >
> > So, no, I don't want to drop a bunch of platforms _right_now_. But we
> > really need to see what doesn't link anymore with BLK forced on, and
> > plan from there.
>
> Yes, I need to ignore warnings. I saw some boards trying to call
> non-DM functions and assumed they all did, but they were just DTC
> warnings. I'll see if I can figure out how to turn those off.
>
> So if you didn't know about CONFIG_BLK migration from the June email,
> hopefully you see this one :-) If your board is already converted,
> please don't worry, I will try to get this right in the v2 series,
> which hopefully will be much smaller.
>
> Thank you very much to the many maintainers who have met the deadline
> and converted their boards. Apologies to those who converted, and
> still got this email.
>
> And please read my note in the cover letter.
I went back to what I did many months ago - simply checking for
CONFIG_BLK=y being enabled (using buildman -D).
Unfortunately, for ARM, this results in 517 out of 833 boards being removed!
This seems worse that the approach used in this series, checking
whether boards build with CONFIG_BLK forced on.
I do have another idea. I got a very large number of bounces from
maintainer emails from this series. I could collect all of those and
figure out which boards don't have maintainers with working emails,
and then remove them first.
The best solution IMO is for maintainers to take a little time to
convert boards over. I don't think this is a lot of work, particularly
if the board uses drivers which are already converted.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-21 4:43 ` Simon Glass
@ 2018-11-21 13:26 ` Tom Rini
0 siblings, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-21 13:26 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 09:43:04PM -0700, Simon Glass wrote:
> Hi again,
>
> On Mon, 19 Nov 2018 at 14:58, Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi,
> >
> > On Mon, 19 Nov 2018 at 14:54, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> > > > On 11/19/2018 08:45 PM, Adam Ford wrote:
> > > > > On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> > > > >>
> > > > >> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> > > > >>>
> > > > >>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > >>> those with build problems using this option.
> > > > >>>
> > > > >>> If maintainers want to keep these boards in they should send a patch in
> > > > >>> the next week or two. Otherwise the board will be removed in the next
> > > > >>> release, and will need to be added and re-reviewed later.
> > > > >>>
> > > > >>> The goal is to have all boards use driver model. But so far, we do allow
> > > > >>> CONFIG_DM to not be defined.
> > > > >>>
> > > > >>> PLEASE NOTE: This is not an easy process. It is possible that your board
> > > > >>> does work, or works with only minor changes. Please try to understand that
> > > > >>> the removal of a board is not done because people don't like your board.
> > > > >>> In fact the board might have been the first one I used when trying out
> > > > >>> U-Boot! It's just that we expect maintainers to keep up with the migration
> > > > >>> to driver model which has been running now for 4 years. It just isn't
> > > > >>> possible for a few people to migrate and test hundreds of boards.
> > > > >>>
> > > > >>> So, send a patch!
> > > > >>
> > > > >> OK, so with the intention of "need to light a fire", consider the fire
> > > > >> lit! But, I think v2 of this series needs to:
> > > > >> - Address the bug that's been noted of you checking on "DM_BLK" when
> > > > >> it's really just "BLK".
> > > > >> - Do a test build with BLK just being unconditional now. For example,
> > > > >> you're deleting the am335x_evm family but it builds fine with BLK
> > > > >> being enabled now. I even gave it a run time test via test.py and
> > > > >> we're fine. So, I think a new run where you see what fails to build
> > > > >> with BLK enabled by default now is in order to come up with a new
> > > > >> delete list.
> > > > >>
> > > > >
> > > > > When we were migrating toward GCC 6, we introduced a warning message
> > > > > that was displayed at build indicating older versions of GCC would be
> > > > > unsupported, and GCC 6 would become a requirement. The
> > > > > CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> > > > > removed. I would like to propose that in the future, when setting
> > > > > deadlines, we insert something into the build mechanism that generates
> > > > > a warning to tell people that something is going to happen.
> > > >
> > > > I agree, that sounds good.
> > > >
> > > > I am extremely unhappy by how Simon decided, unilaterally, some
> > > > arbitrary deadline, told pretty much no one about that deadline and then
> > > > put a knife on many peoples' throats by sending out this series which
> > > > removes boards that are actively used and maintained, demanding they be
> > > > converted right this instant.
> > >
> > > OK, lets step back for a moment. Part of the problem is that yes, we
> > > (I) never found a good way to make a big scary build warning happen.
> > > But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> > > moment, which is when we set this deadline, and we had a good bit of
> > > discussion about related issues to make it happen.
> > >
> > > I also know that around the v2018.05 release I said, in public, but no I
> > > can't find a link right this moment, that we were pushing off a little
> > > bit on dropping _everything_ right then as there was basically some
> > > fairly important / widely used USB stuff that hadn't been converted yet
> > > (which has since been, I think, otherwise am335x_evm & co wouldn't have
> > > been happy?). I know I did since I can see in the archives a number of
> > > series where maintainers did a bunch of changes to various platforms /
> > > SoCs to turn on BLK right then.
> > >
> > > So, no, I don't want to drop a bunch of platforms _right_now_. But we
> > > really need to see what doesn't link anymore with BLK forced on, and
> > > plan from there.
> >
> > Yes, I need to ignore warnings. I saw some boards trying to call
> > non-DM functions and assumed they all did, but they were just DTC
> > warnings. I'll see if I can figure out how to turn those off.
> >
> > So if you didn't know about CONFIG_BLK migration from the June email,
> > hopefully you see this one :-) If your board is already converted,
> > please don't worry, I will try to get this right in the v2 series,
> > which hopefully will be much smaller.
> >
> > Thank you very much to the many maintainers who have met the deadline
> > and converted their boards. Apologies to those who converted, and
> > still got this email.
> >
> > And please read my note in the cover letter.
>
> I went back to what I did many months ago - simply checking for
> CONFIG_BLK=y being enabled (using buildman -D).
>
> Unfortunately, for ARM, this results in 517 out of 833 boards being removed!
>
> This seems worse that the approach used in this series, checking
> whether boards build with CONFIG_BLK forced on.
>
> I do have another idea. I got a very large number of bounces from
> maintainer emails from this series. I could collect all of those and
> figure out which boards don't have maintainers with working emails,
> and then remove them first.
>
> The best solution IMO is for maintainers to take a little time to
> convert boards over. I don't think this is a lot of work, particularly
> if the board uses drivers which are already converted.
I think this is going the wrong way still. So I'll go and kick off a
test set of builds where we make BLK be default y for DM and see what
breaks. That will show us what subsystems / drivers haven't been
converted yet and that in turn is what we need to deal with removing or
converting. This isn't exactly a "board" issue but rather a driver
issue and while there is some overlap I think aiming at boards is the
wrong way.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 21:54 ` Tom Rini
2018-11-19 21:58 ` Simon Glass
@ 2018-11-19 22:02 ` Adam Ford
2018-11-19 22:06 ` Marek Vasut
2018-11-19 22:05 ` Marek Vasut
2 siblings, 1 reply; 211+ messages in thread
From: Adam Ford @ 2018-11-19 22:02 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> > On 11/19/2018 08:45 PM, Adam Ford wrote:
> > > On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> > >>
> > >> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> > >>>
> > >>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > >>> those with build problems using this option.
> > >>>
> > >>> If maintainers want to keep these boards in they should send a patch in
> > >>> the next week or two. Otherwise the board will be removed in the next
> > >>> release, and will need to be added and re-reviewed later.
> > >>>
> > >>> The goal is to have all boards use driver model. But so far, we do allow
> > >>> CONFIG_DM to not be defined.
> > >>>
> > >>> PLEASE NOTE: This is not an easy process. It is possible that your board
> > >>> does work, or works with only minor changes. Please try to understand that
> > >>> the removal of a board is not done because people don't like your board.
> > >>> In fact the board might have been the first one I used when trying out
> > >>> U-Boot! It's just that we expect maintainers to keep up with the migration
> > >>> to driver model which has been running now for 4 years. It just isn't
> > >>> possible for a few people to migrate and test hundreds of boards.
> > >>>
> > >>> So, send a patch!
> > >>
> > >> OK, so with the intention of "need to light a fire", consider the fire
> > >> lit! But, I think v2 of this series needs to:
> > >> - Address the bug that's been noted of you checking on "DM_BLK" when
> > >> it's really just "BLK".
> > >> - Do a test build with BLK just being unconditional now. For example,
> > >> you're deleting the am335x_evm family but it builds fine with BLK
> > >> being enabled now. I even gave it a run time test via test.py and
> > >> we're fine. So, I think a new run where you see what fails to build
> > >> with BLK enabled by default now is in order to come up with a new
> > >> delete list.
> > >>
> > >
> > > When we were migrating toward GCC 6, we introduced a warning message
> > > that was displayed at build indicating older versions of GCC would be
> > > unsupported, and GCC 6 would become a requirement. The
> > > CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> > > removed. I would like to propose that in the future, when setting
> > > deadlines, we insert something into the build mechanism that generates
> > > a warning to tell people that something is going to happen.
> >
> > I agree, that sounds good.
> >
> > I am extremely unhappy by how Simon decided, unilaterally, some
> > arbitrary deadline, told pretty much no one about that deadline and then
> > put a knife on many peoples' throats by sending out this series which
> > removes boards that are actively used and maintained, demanding they be
> > converted right this instant.
>
> OK, lets step back for a moment. Part of the problem is that yes, we
> (I) never found a good way to make a big scary build warning happen.
> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> moment, which is when we set this deadline, and we had a good bit of
> discussion about related issues to make it happen.
>
> I also know that around the v2018.05 release I said, in public, but no I
> can't find a link right this moment, that we were pushing off a little
> bit on dropping _everything_ right then as there was basically some
> fairly important / widely used USB stuff that hadn't been converted yet
> (which has since been, I think, otherwise am335x_evm & co wouldn't have
> been happy?). I know I did since I can see in the archives a number of
> series where maintainers did a bunch of changes to various platforms /
> SoCs to turn on BLK right then.
>
> So, no, I don't want to drop a bunch of platforms _right_now_. But we
> really need to see what doesn't link anymore with BLK forced on, and
> plan from there.
I remember the discussion, but it seems rather arbitrary for one
person to unilaterally start deleting boards. I think a more
appropriate approach would be to start a dialog instead of deleting
boards and then giving people a fairly short notice to respond -
especially this close to the US Thanksgiving holiday, several
religious holidays and New Years. Many people have planed time off
and/or end-of-year deadlines to hit without getting an abrupt suprise.
adam
>
> --
> Tom
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 22:02 ` Adam Ford
@ 2018-11-19 22:06 ` Marek Vasut
2018-11-20 11:00 ` Stefano Babic
0 siblings, 1 reply; 211+ messages in thread
From: Marek Vasut @ 2018-11-19 22:06 UTC (permalink / raw)
To: u-boot
On 11/19/2018 11:02 PM, Adam Ford wrote:
> On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
>>
>> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
>>> On 11/19/2018 08:45 PM, Adam Ford wrote:
>>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
>>>>>
>>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>>>>>>
>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>>>>> those with build problems using this option.
>>>>>>
>>>>>> If maintainers want to keep these boards in they should send a patch in
>>>>>> the next week or two. Otherwise the board will be removed in the next
>>>>>> release, and will need to be added and re-reviewed later.
>>>>>>
>>>>>> The goal is to have all boards use driver model. But so far, we do allow
>>>>>> CONFIG_DM to not be defined.
>>>>>>
>>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
>>>>>> does work, or works with only minor changes. Please try to understand that
>>>>>> the removal of a board is not done because people don't like your board.
>>>>>> In fact the board might have been the first one I used when trying out
>>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
>>>>>> to driver model which has been running now for 4 years. It just isn't
>>>>>> possible for a few people to migrate and test hundreds of boards.
>>>>>>
>>>>>> So, send a patch!
>>>>>
>>>>> OK, so with the intention of "need to light a fire", consider the fire
>>>>> lit! But, I think v2 of this series needs to:
>>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
>>>>> it's really just "BLK".
>>>>> - Do a test build with BLK just being unconditional now. For example,
>>>>> you're deleting the am335x_evm family but it builds fine with BLK
>>>>> being enabled now. I even gave it a run time test via test.py and
>>>>> we're fine. So, I think a new run where you see what fails to build
>>>>> with BLK enabled by default now is in order to come up with a new
>>>>> delete list.
>>>>>
>>>>
>>>> When we were migrating toward GCC 6, we introduced a warning message
>>>> that was displayed at build indicating older versions of GCC would be
>>>> unsupported, and GCC 6 would become a requirement. The
>>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
>>>> removed. I would like to propose that in the future, when setting
>>>> deadlines, we insert something into the build mechanism that generates
>>>> a warning to tell people that something is going to happen.
>>>
>>> I agree, that sounds good.
>>>
>>> I am extremely unhappy by how Simon decided, unilaterally, some
>>> arbitrary deadline, told pretty much no one about that deadline and then
>>> put a knife on many peoples' throats by sending out this series which
>>> removes boards that are actively used and maintained, demanding they be
>>> converted right this instant.
>>
>> OK, lets step back for a moment. Part of the problem is that yes, we
>> (I) never found a good way to make a big scary build warning happen.
>> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
>> moment, which is when we set this deadline, and we had a good bit of
>> discussion about related issues to make it happen.
>>
>> I also know that around the v2018.05 release I said, in public, but no I
>> can't find a link right this moment, that we were pushing off a little
>> bit on dropping _everything_ right then as there was basically some
>> fairly important / widely used USB stuff that hadn't been converted yet
>> (which has since been, I think, otherwise am335x_evm & co wouldn't have
>> been happy?). I know I did since I can see in the archives a number of
>> series where maintainers did a bunch of changes to various platforms /
>> SoCs to turn on BLK right then.
>>
>> So, no, I don't want to drop a bunch of platforms _right_now_. But we
>> really need to see what doesn't link anymore with BLK forced on, and
>> plan from there.
>
> I remember the discussion, but it seems rather arbitrary for one
> person to unilaterally start deleting boards. I think a more
> appropriate approach would be to start a dialog instead of deleting
> boards and then giving people a fairly short notice to respond -
> especially this close to the US Thanksgiving holiday, several
> religious holidays and New Years. Many people have planed time off
> and/or end-of-year deadlines to hit without getting an abrupt suprise.
ACK
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 22:06 ` Marek Vasut
@ 2018-11-20 11:00 ` Stefano Babic
2018-11-20 12:39 ` Peter Robinson
2018-11-20 14:55 ` Tom Rini
0 siblings, 2 replies; 211+ messages in thread
From: Stefano Babic @ 2018-11-20 11:00 UTC (permalink / raw)
To: u-boot
Hi,
On 19/11/18 23:06, Marek Vasut wrote:
> On 11/19/2018 11:02 PM, Adam Ford wrote:
>> On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
>>>
>>> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
>>>> On 11/19/2018 08:45 PM, Adam Ford wrote:
>>>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
>>>>>>
>>>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>>>>>>>
>>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>>>>>> those with build problems using this option.
>>>>>>>
>>>>>>> If maintainers want to keep these boards in they should send a patch in
>>>>>>> the next week or two. Otherwise the board will be removed in the next
>>>>>>> release, and will need to be added and re-reviewed later.
>>>>>>>
>>>>>>> The goal is to have all boards use driver model. But so far, we do allow
>>>>>>> CONFIG_DM to not be defined.
>>>>>>>
>>>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
>>>>>>> does work, or works with only minor changes. Please try to understand that
>>>>>>> the removal of a board is not done because people don't like your board.
>>>>>>> In fact the board might have been the first one I used when trying out
>>>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
>>>>>>> to driver model which has been running now for 4 years. It just isn't
>>>>>>> possible for a few people to migrate and test hundreds of boards.
>>>>>>>
>>>>>>> So, send a patch!
>>>>>>
>>>>>> OK, so with the intention of "need to light a fire", consider the fire
>>>>>> lit! But, I think v2 of this series needs to:
>>>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
>>>>>> it's really just "BLK".
>>>>>> - Do a test build with BLK just being unconditional now. For example,
>>>>>> you're deleting the am335x_evm family but it builds fine with BLK
>>>>>> being enabled now. I even gave it a run time test via test.py and
>>>>>> we're fine. So, I think a new run where you see what fails to build
>>>>>> with BLK enabled by default now is in order to come up with a new
>>>>>> delete list.
>>>>>>
>>>>>
>>>>> When we were migrating toward GCC 6, we introduced a warning message
>>>>> that was displayed at build indicating older versions of GCC would be
>>>>> unsupported, and GCC 6 would become a requirement. The
>>>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
>>>>> removed. I would like to propose that in the future, when setting
>>>>> deadlines, we insert something into the build mechanism that generates
>>>>> a warning to tell people that something is going to happen.
>>>>
>>>> I agree, that sounds good.
>>>>
>>>> I am extremely unhappy by how Simon decided, unilaterally, some
>>>> arbitrary deadline, told pretty much no one about that deadline and then
>>>> put a knife on many peoples' throats by sending out this series which
>>>> removes boards that are actively used and maintained, demanding they be
>>>> converted right this instant.
>>>
>>> OK, lets step back for a moment. Part of the problem is that yes, we
>>> (I) never found a good way to make a big scary build warning happen.
>>> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
>>> moment, which is when we set this deadline, and we had a good bit of
>>> discussion about related issues to make it happen.
>>>
>>> I also know that around the v2018.05 release I said, in public, but no I
>>> can't find a link right this moment, that we were pushing off a little
>>> bit on dropping _everything_ right then as there was basically some
>>> fairly important / widely used USB stuff that hadn't been converted yet
>>> (which has since been, I think, otherwise am335x_evm & co wouldn't have
>>> been happy?). I know I did since I can see in the archives a number of
>>> series where maintainers did a bunch of changes to various platforms /
>>> SoCs to turn on BLK right then.
>>>
>>> So, no, I don't want to drop a bunch of platforms _right_now_. But we
>>> really need to see what doesn't link anymore with BLK forced on, and
>>> plan from there.
>>
>> I remember the discussion, but it seems rather arbitrary for one
>> person to unilaterally start deleting boards. I think a more
>> appropriate approach would be to start a dialog instead of deleting
>> boards and then giving people a fairly short notice to respond -
>> especially this close to the US Thanksgiving holiday, several
>> religious holidays and New Years. Many people have planed time off
>> and/or end-of-year deadlines to hit without getting an abrupt suprise.
>
> ACK
I fully agree with Marek and Adam, but I have also some other technical
points related to i.MX6.
I agree to move to new and better code, but this should not drop
important features that are appreciated by customers. Up now, U-Boot as
project was pretty conservative, trying t osupport as far as it is
possible even older architectures (MPC 88x, for example).
On i.MX6, a feature is to have a single U-Boot binary (SPL + U-Boot)
running for more variants (Quad / Dual / Solo) of the SOC. This is done
with run time detection in code (SPL) - macros are provide to make the
work easy (it is, currently). There are plenty of boards doing this (all
listed by Simon for removal). This is common if the board has a SOM, and
of course the SOM is sold in different variants with different prices.
If I understand well, moving to CONFIG_BLK means enabling CONFIG_DM_MMC
and this requires to set a DTS. But a DT is compiled by DTC, that means
we have a DT for each variant of the SOC. This forbids to have a single
binary and we need different binaries, one for each variant. We lose an
important feature, at least for some boards. Agree that having DT is
nice, but this should not drop what customer are asking.
I know there are some improvement in TI code to get the root node in DT
and then load from it. Anyway, specially for i.MX6 solo, we are quite
running out of space in SRAM, mainly due to other required features. And
having multiple DTB with CONFIG_MULTI_DTB_FIT seems to work just if we
have no SPL.
So first, it looks like that the issue is not so trivial as it was, and
second a technical solution must be searched for that.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 11:00 ` Stefano Babic
@ 2018-11-20 12:39 ` Peter Robinson
2018-11-20 14:55 ` Tom Rini
1 sibling, 0 replies; 211+ messages in thread
From: Peter Robinson @ 2018-11-20 12:39 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 12:32 PM Stefano Babic <sbabic@denx.de> wrote:
>
> Hi,
>
> On 19/11/18 23:06, Marek Vasut wrote:
> > On 11/19/2018 11:02 PM, Adam Ford wrote:
> >> On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
> >>>
> >>> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> >>>> On 11/19/2018 08:45 PM, Adam Ford wrote:
> >>>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> >>>>>>
> >>>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> >>>>>>>
> >>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> >>>>>>> those with build problems using this option.
> >>>>>>>
> >>>>>>> If maintainers want to keep these boards in they should send a patch in
> >>>>>>> the next week or two. Otherwise the board will be removed in the next
> >>>>>>> release, and will need to be added and re-reviewed later.
> >>>>>>>
> >>>>>>> The goal is to have all boards use driver model. But so far, we do allow
> >>>>>>> CONFIG_DM to not be defined.
> >>>>>>>
> >>>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
> >>>>>>> does work, or works with only minor changes. Please try to understand that
> >>>>>>> the removal of a board is not done because people don't like your board.
> >>>>>>> In fact the board might have been the first one I used when trying out
> >>>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
> >>>>>>> to driver model which has been running now for 4 years. It just isn't
> >>>>>>> possible for a few people to migrate and test hundreds of boards.
> >>>>>>>
> >>>>>>> So, send a patch!
> >>>>>>
> >>>>>> OK, so with the intention of "need to light a fire", consider the fire
> >>>>>> lit! But, I think v2 of this series needs to:
> >>>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
> >>>>>> it's really just "BLK".
> >>>>>> - Do a test build with BLK just being unconditional now. For example,
> >>>>>> you're deleting the am335x_evm family but it builds fine with BLK
> >>>>>> being enabled now. I even gave it a run time test via test.py and
> >>>>>> we're fine. So, I think a new run where you see what fails to build
> >>>>>> with BLK enabled by default now is in order to come up with a new
> >>>>>> delete list.
> >>>>>>
> >>>>>
> >>>>> When we were migrating toward GCC 6, we introduced a warning message
> >>>>> that was displayed at build indicating older versions of GCC would be
> >>>>> unsupported, and GCC 6 would become a requirement. The
> >>>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> >>>>> removed. I would like to propose that in the future, when setting
> >>>>> deadlines, we insert something into the build mechanism that generates
> >>>>> a warning to tell people that something is going to happen.
> >>>>
> >>>> I agree, that sounds good.
> >>>>
> >>>> I am extremely unhappy by how Simon decided, unilaterally, some
> >>>> arbitrary deadline, told pretty much no one about that deadline and then
> >>>> put a knife on many peoples' throats by sending out this series which
> >>>> removes boards that are actively used and maintained, demanding they be
> >>>> converted right this instant.
> >>>
> >>> OK, lets step back for a moment. Part of the problem is that yes, we
> >>> (I) never found a good way to make a big scary build warning happen.
> >>> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> >>> moment, which is when we set this deadline, and we had a good bit of
> >>> discussion about related issues to make it happen.
> >>>
> >>> I also know that around the v2018.05 release I said, in public, but no I
> >>> can't find a link right this moment, that we were pushing off a little
> >>> bit on dropping _everything_ right then as there was basically some
> >>> fairly important / widely used USB stuff that hadn't been converted yet
> >>> (which has since been, I think, otherwise am335x_evm & co wouldn't have
> >>> been happy?). I know I did since I can see in the archives a number of
> >>> series where maintainers did a bunch of changes to various platforms /
> >>> SoCs to turn on BLK right then.
> >>>
> >>> So, no, I don't want to drop a bunch of platforms _right_now_. But we
> >>> really need to see what doesn't link anymore with BLK forced on, and
> >>> plan from there.
> >>
> >> I remember the discussion, but it seems rather arbitrary for one
> >> person to unilaterally start deleting boards. I think a more
> >> appropriate approach would be to start a dialog instead of deleting
> >> boards and then giving people a fairly short notice to respond -
> >> especially this close to the US Thanksgiving holiday, several
> >> religious holidays and New Years. Many people have planed time off
> >> and/or end-of-year deadlines to hit without getting an abrupt suprise.
> >
> > ACK
>
>
> I fully agree with Marek and Adam, but I have also some other technical
> points related to i.MX6.
>
> I agree to move to new and better code, but this should not drop
> important features that are appreciated by customers. Up now, U-Boot as
> project was pretty conservative, trying t osupport as far as it is
> possible even older architectures (MPC 88x, for example).
>
> On i.MX6, a feature is to have a single U-Boot binary (SPL + U-Boot)
> running for more variants (Quad / Dual / Solo) of the SOC. This is done
> with run time detection in code (SPL) - macros are provide to make the
> work easy (it is, currently). There are plenty of boards doing this (all
> listed by Simon for removal). This is common if the board has a SOM, and
> of course the SOM is sold in different variants with different prices.
>
> If I understand well, moving to CONFIG_BLK means enabling CONFIG_DM_MMC
> and this requires to set a DTS. But a DT is compiled by DTC, that means
> we have a DT for each variant of the SOC. This forbids to have a single
> binary and we need different binaries, one for each variant. We lose an
> important feature, at least for some boards. Agree that having DT is
> nice, but this should not drop what customer are asking.
>
> I know there are some improvement in TI code to get the root node in DT
> and then load from it. Anyway, specially for i.MX6 solo, we are quite
> running out of space in SRAM, mainly due to other required features. And
> having multiple DTB with CONFIG_MULTI_DTB_FIT seems to work just if we
> have no SPL.
>
> So first, it looks like that the issue is not so trivial as it was, and
> second a technical solution must be searched for that.
There's a few configs that handle multiple DT, and other things like
ATF, with a SPL+FIT combination, one example is pine64_plus_defconfig
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 11:00 ` Stefano Babic
2018-11-20 12:39 ` Peter Robinson
@ 2018-11-20 14:55 ` Tom Rini
2018-11-20 16:27 ` Stefano Babic
1 sibling, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-20 14:55 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 12:00:13PM +0100, Stefano Babic wrote:
> Hi,
>
> On 19/11/18 23:06, Marek Vasut wrote:
> > On 11/19/2018 11:02 PM, Adam Ford wrote:
> >> On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
> >>>
> >>> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> >>>> On 11/19/2018 08:45 PM, Adam Ford wrote:
> >>>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> >>>>>>
> >>>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> >>>>>>>
> >>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> >>>>>>> those with build problems using this option.
> >>>>>>>
> >>>>>>> If maintainers want to keep these boards in they should send a patch in
> >>>>>>> the next week or two. Otherwise the board will be removed in the next
> >>>>>>> release, and will need to be added and re-reviewed later.
> >>>>>>>
> >>>>>>> The goal is to have all boards use driver model. But so far, we do allow
> >>>>>>> CONFIG_DM to not be defined.
> >>>>>>>
> >>>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
> >>>>>>> does work, or works with only minor changes. Please try to understand that
> >>>>>>> the removal of a board is not done because people don't like your board.
> >>>>>>> In fact the board might have been the first one I used when trying out
> >>>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
> >>>>>>> to driver model which has been running now for 4 years. It just isn't
> >>>>>>> possible for a few people to migrate and test hundreds of boards.
> >>>>>>>
> >>>>>>> So, send a patch!
> >>>>>>
> >>>>>> OK, so with the intention of "need to light a fire", consider the fire
> >>>>>> lit! But, I think v2 of this series needs to:
> >>>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
> >>>>>> it's really just "BLK".
> >>>>>> - Do a test build with BLK just being unconditional now. For example,
> >>>>>> you're deleting the am335x_evm family but it builds fine with BLK
> >>>>>> being enabled now. I even gave it a run time test via test.py and
> >>>>>> we're fine. So, I think a new run where you see what fails to build
> >>>>>> with BLK enabled by default now is in order to come up with a new
> >>>>>> delete list.
> >>>>>>
> >>>>>
> >>>>> When we were migrating toward GCC 6, we introduced a warning message
> >>>>> that was displayed at build indicating older versions of GCC would be
> >>>>> unsupported, and GCC 6 would become a requirement. The
> >>>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> >>>>> removed. I would like to propose that in the future, when setting
> >>>>> deadlines, we insert something into the build mechanism that generates
> >>>>> a warning to tell people that something is going to happen.
> >>>>
> >>>> I agree, that sounds good.
> >>>>
> >>>> I am extremely unhappy by how Simon decided, unilaterally, some
> >>>> arbitrary deadline, told pretty much no one about that deadline and then
> >>>> put a knife on many peoples' throats by sending out this series which
> >>>> removes boards that are actively used and maintained, demanding they be
> >>>> converted right this instant.
> >>>
> >>> OK, lets step back for a moment. Part of the problem is that yes, we
> >>> (I) never found a good way to make a big scary build warning happen.
> >>> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> >>> moment, which is when we set this deadline, and we had a good bit of
> >>> discussion about related issues to make it happen.
> >>>
> >>> I also know that around the v2018.05 release I said, in public, but no I
> >>> can't find a link right this moment, that we were pushing off a little
> >>> bit on dropping _everything_ right then as there was basically some
> >>> fairly important / widely used USB stuff that hadn't been converted yet
> >>> (which has since been, I think, otherwise am335x_evm & co wouldn't have
> >>> been happy?). I know I did since I can see in the archives a number of
> >>> series where maintainers did a bunch of changes to various platforms /
> >>> SoCs to turn on BLK right then.
> >>>
> >>> So, no, I don't want to drop a bunch of platforms _right_now_. But we
> >>> really need to see what doesn't link anymore with BLK forced on, and
> >>> plan from there.
> >>
> >> I remember the discussion, but it seems rather arbitrary for one
> >> person to unilaterally start deleting boards. I think a more
> >> appropriate approach would be to start a dialog instead of deleting
> >> boards and then giving people a fairly short notice to respond -
> >> especially this close to the US Thanksgiving holiday, several
> >> religious holidays and New Years. Many people have planed time off
> >> and/or end-of-year deadlines to hit without getting an abrupt suprise.
> >
> > ACK
>
>
> I fully agree with Marek and Adam, but I have also some other technical
> points related to i.MX6.
>
> I agree to move to new and better code, but this should not drop
> important features that are appreciated by customers. Up now, U-Boot as
> project was pretty conservative, trying t osupport as far as it is
> possible even older architectures (MPC 88x, for example).
>
> On i.MX6, a feature is to have a single U-Boot binary (SPL + U-Boot)
> running for more variants (Quad / Dual / Solo) of the SOC. This is done
> with run time detection in code (SPL) - macros are provide to make the
> work easy (it is, currently). There are plenty of boards doing this (all
> listed by Simon for removal). This is common if the board has a SOM, and
> of course the SOM is sold in different variants with different prices.
>
> If I understand well, moving to CONFIG_BLK means enabling CONFIG_DM_MMC
> and this requires to set a DTS. But a DT is compiled by DTC, that means
> we have a DT for each variant of the SOC. This forbids to have a single
> binary and we need different binaries, one for each variant. We lose an
> important feature, at least for some boards. Agree that having DT is
> nice, but this should not drop what customer are asking.
>
> I know there are some improvement in TI code to get the root node in DT
> and then load from it. Anyway, specially for i.MX6 solo, we are quite
> running out of space in SRAM, mainly due to other required features. And
> having multiple DTB with CONFIG_MULTI_DTB_FIT seems to work just if we
> have no SPL.
>
> So first, it looks like that the issue is not so trivial as it was, and
> second a technical solution must be searched for that.
Yes, this is a useful feature on i.MX lines and we need to figure out
how to keep it. Perhaps we'll need some combination of
CONFIG_SPL_FIT_LOAD (and board_fit_config_name_match) along with perhaps
introducing a TPL to i.MX where we can get away with doing whatever we
need to do, to init DRAM and have enough space to put SPL and U-Boot?
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 14:55 ` Tom Rini
@ 2018-11-20 16:27 ` Stefano Babic
2018-11-20 17:18 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Stefano Babic @ 2018-11-20 16:27 UTC (permalink / raw)
To: u-boot
Hi Tom,
On 20/11/18 15:55, Tom Rini wrote:
> On Tue, Nov 20, 2018 at 12:00:13PM +0100, Stefano Babic wrote:
>> Hi,
>>
>> On 19/11/18 23:06, Marek Vasut wrote:
>>> On 11/19/2018 11:02 PM, Adam Ford wrote:
>>>> On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
>>>>>
>>>>> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
>>>>>> On 11/19/2018 08:45 PM, Adam Ford wrote:
>>>>>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
>>>>>>>>
>>>>>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>
>>>>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>>>>>>>> those with build problems using this option.
>>>>>>>>>
>>>>>>>>> If maintainers want to keep these boards in they should send a patch in
>>>>>>>>> the next week or two. Otherwise the board will be removed in the next
>>>>>>>>> release, and will need to be added and re-reviewed later.
>>>>>>>>>
>>>>>>>>> The goal is to have all boards use driver model. But so far, we do allow
>>>>>>>>> CONFIG_DM to not be defined.
>>>>>>>>>
>>>>>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
>>>>>>>>> does work, or works with only minor changes. Please try to understand that
>>>>>>>>> the removal of a board is not done because people don't like your board.
>>>>>>>>> In fact the board might have been the first one I used when trying out
>>>>>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
>>>>>>>>> to driver model which has been running now for 4 years. It just isn't
>>>>>>>>> possible for a few people to migrate and test hundreds of boards.
>>>>>>>>>
>>>>>>>>> So, send a patch!
>>>>>>>>
>>>>>>>> OK, so with the intention of "need to light a fire", consider the fire
>>>>>>>> lit! But, I think v2 of this series needs to:
>>>>>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
>>>>>>>> it's really just "BLK".
>>>>>>>> - Do a test build with BLK just being unconditional now. For example,
>>>>>>>> you're deleting the am335x_evm family but it builds fine with BLK
>>>>>>>> being enabled now. I even gave it a run time test via test.py and
>>>>>>>> we're fine. So, I think a new run where you see what fails to build
>>>>>>>> with BLK enabled by default now is in order to come up with a new
>>>>>>>> delete list.
>>>>>>>>
>>>>>>>
>>>>>>> When we were migrating toward GCC 6, we introduced a warning message
>>>>>>> that was displayed at build indicating older versions of GCC would be
>>>>>>> unsupported, and GCC 6 would become a requirement. The
>>>>>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
>>>>>>> removed. I would like to propose that in the future, when setting
>>>>>>> deadlines, we insert something into the build mechanism that generates
>>>>>>> a warning to tell people that something is going to happen.
>>>>>>
>>>>>> I agree, that sounds good.
>>>>>>
>>>>>> I am extremely unhappy by how Simon decided, unilaterally, some
>>>>>> arbitrary deadline, told pretty much no one about that deadline and then
>>>>>> put a knife on many peoples' throats by sending out this series which
>>>>>> removes boards that are actively used and maintained, demanding they be
>>>>>> converted right this instant.
>>>>>
>>>>> OK, lets step back for a moment. Part of the problem is that yes, we
>>>>> (I) never found a good way to make a big scary build warning happen.
>>>>> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
>>>>> moment, which is when we set this deadline, and we had a good bit of
>>>>> discussion about related issues to make it happen.
>>>>>
>>>>> I also know that around the v2018.05 release I said, in public, but no I
>>>>> can't find a link right this moment, that we were pushing off a little
>>>>> bit on dropping _everything_ right then as there was basically some
>>>>> fairly important / widely used USB stuff that hadn't been converted yet
>>>>> (which has since been, I think, otherwise am335x_evm & co wouldn't have
>>>>> been happy?). I know I did since I can see in the archives a number of
>>>>> series where maintainers did a bunch of changes to various platforms /
>>>>> SoCs to turn on BLK right then.
>>>>>
>>>>> So, no, I don't want to drop a bunch of platforms _right_now_. But we
>>>>> really need to see what doesn't link anymore with BLK forced on, and
>>>>> plan from there.
>>>>
>>>> I remember the discussion, but it seems rather arbitrary for one
>>>> person to unilaterally start deleting boards. I think a more
>>>> appropriate approach would be to start a dialog instead of deleting
>>>> boards and then giving people a fairly short notice to respond -
>>>> especially this close to the US Thanksgiving holiday, several
>>>> religious holidays and New Years. Many people have planed time off
>>>> and/or end-of-year deadlines to hit without getting an abrupt suprise.
>>>
>>> ACK
>>
>>
>> I fully agree with Marek and Adam, but I have also some other technical
>> points related to i.MX6.
>>
>> I agree to move to new and better code, but this should not drop
>> important features that are appreciated by customers. Up now, U-Boot as
>> project was pretty conservative, trying t osupport as far as it is
>> possible even older architectures (MPC 88x, for example).
>>
>> On i.MX6, a feature is to have a single U-Boot binary (SPL + U-Boot)
>> running for more variants (Quad / Dual / Solo) of the SOC. This is done
>> with run time detection in code (SPL) - macros are provide to make the
>> work easy (it is, currently). There are plenty of boards doing this (all
>> listed by Simon for removal). This is common if the board has a SOM, and
>> of course the SOM is sold in different variants with different prices.
>>
>> If I understand well, moving to CONFIG_BLK means enabling CONFIG_DM_MMC
>> and this requires to set a DTS. But a DT is compiled by DTC, that means
>> we have a DT for each variant of the SOC. This forbids to have a single
>> binary and we need different binaries, one for each variant. We lose an
>> important feature, at least for some boards. Agree that having DT is
>> nice, but this should not drop what customer are asking.
>>
>> I know there are some improvement in TI code to get the root node in DT
>> and then load from it. Anyway, specially for i.MX6 solo, we are quite
>> running out of space in SRAM, mainly due to other required features. And
>> having multiple DTB with CONFIG_MULTI_DTB_FIT seems to work just if we
>> have no SPL.
>>
>> So first, it looks like that the issue is not so trivial as it was, and
>> second a technical solution must be searched for that.
>
> Yes, this is a useful feature on i.MX lines and we need to figure out
> how to keep it.
Right, fully agree.
> Perhaps we'll need some combination of
> CONFIG_SPL_FIT_LOAD (and board_fit_config_name_match) along with perhaps
> introducing a TPL to i.MX where we can get away with doing whatever we
> need to do, to init DRAM and have enough space to put SPL and U-Boot?
I am just figuring out how we can do. One other aspect introducing
another stage as TPL could be the increased boot time, even if I guess
it is not much. However, there are some applications in automotive that
are very "sensible" to any increment in boot time.
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 16:27 ` Stefano Babic
@ 2018-11-20 17:18 ` Tom Rini
0 siblings, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-20 17:18 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 05:27:03PM +0100, Stefano Babic wrote:
> Hi Tom,
>
> On 20/11/18 15:55, Tom Rini wrote:
> > On Tue, Nov 20, 2018 at 12:00:13PM +0100, Stefano Babic wrote:
> >> Hi,
> >>
> >> On 19/11/18 23:06, Marek Vasut wrote:
> >>> On 11/19/2018 11:02 PM, Adam Ford wrote:
> >>>> On Mon, Nov 19, 2018 at 3:54 PM Tom Rini <trini@konsulko.com> wrote:
> >>>>>
> >>>>> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
> >>>>>> On 11/19/2018 08:45 PM, Adam Ford wrote:
> >>>>>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
> >>>>>>>>
> >>>>>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
> >>>>>>>>>
> >>>>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> >>>>>>>>> those with build problems using this option.
> >>>>>>>>>
> >>>>>>>>> If maintainers want to keep these boards in they should send a patch in
> >>>>>>>>> the next week or two. Otherwise the board will be removed in the next
> >>>>>>>>> release, and will need to be added and re-reviewed later.
> >>>>>>>>>
> >>>>>>>>> The goal is to have all boards use driver model. But so far, we do allow
> >>>>>>>>> CONFIG_DM to not be defined.
> >>>>>>>>>
> >>>>>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
> >>>>>>>>> does work, or works with only minor changes. Please try to understand that
> >>>>>>>>> the removal of a board is not done because people don't like your board.
> >>>>>>>>> In fact the board might have been the first one I used when trying out
> >>>>>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
> >>>>>>>>> to driver model which has been running now for 4 years. It just isn't
> >>>>>>>>> possible for a few people to migrate and test hundreds of boards.
> >>>>>>>>>
> >>>>>>>>> So, send a patch!
> >>>>>>>>
> >>>>>>>> OK, so with the intention of "need to light a fire", consider the fire
> >>>>>>>> lit! But, I think v2 of this series needs to:
> >>>>>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
> >>>>>>>> it's really just "BLK".
> >>>>>>>> - Do a test build with BLK just being unconditional now. For example,
> >>>>>>>> you're deleting the am335x_evm family but it builds fine with BLK
> >>>>>>>> being enabled now. I even gave it a run time test via test.py and
> >>>>>>>> we're fine. So, I think a new run where you see what fails to build
> >>>>>>>> with BLK enabled by default now is in order to come up with a new
> >>>>>>>> delete list.
> >>>>>>>>
> >>>>>>>
> >>>>>>> When we were migrating toward GCC 6, we introduced a warning message
> >>>>>>> that was displayed at build indicating older versions of GCC would be
> >>>>>>> unsupported, and GCC 6 would become a requirement. The
> >>>>>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
> >>>>>>> removed. I would like to propose that in the future, when setting
> >>>>>>> deadlines, we insert something into the build mechanism that generates
> >>>>>>> a warning to tell people that something is going to happen.
> >>>>>>
> >>>>>> I agree, that sounds good.
> >>>>>>
> >>>>>> I am extremely unhappy by how Simon decided, unilaterally, some
> >>>>>> arbitrary deadline, told pretty much no one about that deadline and then
> >>>>>> put a knife on many peoples' throats by sending out this series which
> >>>>>> removes boards that are actively used and maintained, demanding they be
> >>>>>> converted right this instant.
> >>>>>
> >>>>> OK, lets step back for a moment. Part of the problem is that yes, we
> >>>>> (I) never found a good way to make a big scary build warning happen.
> >>>>> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> >>>>> moment, which is when we set this deadline, and we had a good bit of
> >>>>> discussion about related issues to make it happen.
> >>>>>
> >>>>> I also know that around the v2018.05 release I said, in public, but no I
> >>>>> can't find a link right this moment, that we were pushing off a little
> >>>>> bit on dropping _everything_ right then as there was basically some
> >>>>> fairly important / widely used USB stuff that hadn't been converted yet
> >>>>> (which has since been, I think, otherwise am335x_evm & co wouldn't have
> >>>>> been happy?). I know I did since I can see in the archives a number of
> >>>>> series where maintainers did a bunch of changes to various platforms /
> >>>>> SoCs to turn on BLK right then.
> >>>>>
> >>>>> So, no, I don't want to drop a bunch of platforms _right_now_. But we
> >>>>> really need to see what doesn't link anymore with BLK forced on, and
> >>>>> plan from there.
> >>>>
> >>>> I remember the discussion, but it seems rather arbitrary for one
> >>>> person to unilaterally start deleting boards. I think a more
> >>>> appropriate approach would be to start a dialog instead of deleting
> >>>> boards and then giving people a fairly short notice to respond -
> >>>> especially this close to the US Thanksgiving holiday, several
> >>>> religious holidays and New Years. Many people have planed time off
> >>>> and/or end-of-year deadlines to hit without getting an abrupt suprise.
> >>>
> >>> ACK
> >>
> >>
> >> I fully agree with Marek and Adam, but I have also some other technical
> >> points related to i.MX6.
> >>
> >> I agree to move to new and better code, but this should not drop
> >> important features that are appreciated by customers. Up now, U-Boot as
> >> project was pretty conservative, trying t osupport as far as it is
> >> possible even older architectures (MPC 88x, for example).
> >>
> >> On i.MX6, a feature is to have a single U-Boot binary (SPL + U-Boot)
> >> running for more variants (Quad / Dual / Solo) of the SOC. This is done
> >> with run time detection in code (SPL) - macros are provide to make the
> >> work easy (it is, currently). There are plenty of boards doing this (all
> >> listed by Simon for removal). This is common if the board has a SOM, and
> >> of course the SOM is sold in different variants with different prices.
> >>
> >> If I understand well, moving to CONFIG_BLK means enabling CONFIG_DM_MMC
> >> and this requires to set a DTS. But a DT is compiled by DTC, that means
> >> we have a DT for each variant of the SOC. This forbids to have a single
> >> binary and we need different binaries, one for each variant. We lose an
> >> important feature, at least for some boards. Agree that having DT is
> >> nice, but this should not drop what customer are asking.
> >>
> >> I know there are some improvement in TI code to get the root node in DT
> >> and then load from it. Anyway, specially for i.MX6 solo, we are quite
> >> running out of space in SRAM, mainly due to other required features. And
> >> having multiple DTB with CONFIG_MULTI_DTB_FIT seems to work just if we
> >> have no SPL.
> >>
> >> So first, it looks like that the issue is not so trivial as it was, and
> >> second a technical solution must be searched for that.
> >
> > Yes, this is a useful feature on i.MX lines and we need to figure out
> > how to keep it.
>
> Right, fully agree.
>
> > Perhaps we'll need some combination of
> > CONFIG_SPL_FIT_LOAD (and board_fit_config_name_match) along with perhaps
> > introducing a TPL to i.MX where we can get away with doing whatever we
> > need to do, to init DRAM and have enough space to put SPL and U-Boot?
>
> I am just figuring out how we can do. One other aspect introducing
> another stage as TPL could be the increased boot time, even if I guess
> it is not much. However, there are some applications in automotive that
> are very "sensible" to any increment in boot time.
I would hope that it's no more a change in measurable boot time than
anything else that changes in the code base, but that might also be the
point when it's time to tune the build into a single config (as I would
_hope_ any run-time differences between board revs can be pushed back to
OS time or at least full U-Boot rather than initial steps but DRAM
config could complicate that).
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 21:54 ` Tom Rini
2018-11-19 21:58 ` Simon Glass
2018-11-19 22:02 ` Adam Ford
@ 2018-11-19 22:05 ` Marek Vasut
2 siblings, 0 replies; 211+ messages in thread
From: Marek Vasut @ 2018-11-19 22:05 UTC (permalink / raw)
To: u-boot
On 11/19/2018 10:54 PM, Tom Rini wrote:
> On Mon, Nov 19, 2018 at 10:32:01PM +0100, Marek Vasut wrote:
>> On 11/19/2018 08:45 PM, Adam Ford wrote:
>>> On Mon, Nov 19, 2018 at 12:36 PM Tom Rini <trini@konsulko.com> wrote:
>>>>
>>>> On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>>>>>
>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>>>> those with build problems using this option.
>>>>>
>>>>> If maintainers want to keep these boards in they should send a patch in
>>>>> the next week or two. Otherwise the board will be removed in the next
>>>>> release, and will need to be added and re-reviewed later.
>>>>>
>>>>> The goal is to have all boards use driver model. But so far, we do allow
>>>>> CONFIG_DM to not be defined.
>>>>>
>>>>> PLEASE NOTE: This is not an easy process. It is possible that your board
>>>>> does work, or works with only minor changes. Please try to understand that
>>>>> the removal of a board is not done because people don't like your board.
>>>>> In fact the board might have been the first one I used when trying out
>>>>> U-Boot! It's just that we expect maintainers to keep up with the migration
>>>>> to driver model which has been running now for 4 years. It just isn't
>>>>> possible for a few people to migrate and test hundreds of boards.
>>>>>
>>>>> So, send a patch!
>>>>
>>>> OK, so with the intention of "need to light a fire", consider the fire
>>>> lit! But, I think v2 of this series needs to:
>>>> - Address the bug that's been noted of you checking on "DM_BLK" when
>>>> it's really just "BLK".
>>>> - Do a test build with BLK just being unconditional now. For example,
>>>> you're deleting the am335x_evm family but it builds fine with BLK
>>>> being enabled now. I even gave it a run time test via test.py and
>>>> we're fine. So, I think a new run where you see what fails to build
>>>> with BLK enabled by default now is in order to come up with a new
>>>> delete list.
>>>>
>>>
>>> When we were migrating toward GCC 6, we introduced a warning message
>>> that was displayed at build indicating older versions of GCC would be
>>> unsupported, and GCC 6 would become a requirement. The
>>> CONFIG_DM_I2C_COMPAT generates a build warning and suggests that it be
>>> removed. I would like to propose that in the future, when setting
>>> deadlines, we insert something into the build mechanism that generates
>>> a warning to tell people that something is going to happen.
>>
>> I agree, that sounds good.
>>
>> I am extremely unhappy by how Simon decided, unilaterally, some
>> arbitrary deadline, told pretty much no one about that deadline and then
>> put a knife on many peoples' throats by sending out this series which
>> removes boards that are actively used and maintained, demanding they be
>> converted right this instant.
>
> OK, lets step back for a moment. Part of the problem is that yes, we
> (I) never found a good way to make a big scary build warning happen.
> But, lets look at https://patchwork.ozlabs.org/patch/798309/ for a
> moment, which is when we set this deadline, and we had a good bit of
> discussion about related issues to make it happen.
>
> I also know that around the v2018.05 release I said, in public, but no I
> can't find a link right this moment, that we were pushing off a little
> bit on dropping _everything_ right then as there was basically some
> fairly important / widely used USB stuff that hadn't been converted yet
> (which has since been, I think, otherwise am335x_evm & co wouldn't have
> been happy?). I know I did since I can see in the archives a number of
> series where maintainers did a bunch of changes to various platforms /
> SoCs to turn on BLK right then.
>
> So, no, I don't want to drop a bunch of platforms _right_now_. But we
> really need to see what doesn't link anymore with BLK forced on, and
> plan from there.
If we have a list of boards which do not build and their maintainers are
notified reasonable in advance, that is fine by me. A Makefile warning
is good IMO.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (94 preceding siblings ...)
2018-11-19 18:36 ` Tom Rini
@ 2018-11-20 12:42 ` Soeren Moch
2018-11-20 13:37 ` Tom Rini
2018-11-23 0:31 ` Fabio Estevam
2018-11-21 15:13 ` [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL Guillaume GARDET
2018-11-22 17:45 ` [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Tom Rini
97 siblings, 2 replies; 211+ messages in thread
From: Soeren Moch @ 2018-11-20 12:42 UTC (permalink / raw)
To: u-boot
On 19.11.18 16:52, Simon Glass wrote:
> All boards should now be migrated to use CONFIG_BLK. This series removes
> those with build problems using this option.
>
> If maintainers want to keep these boards in they should send a patch in
> the next week or two. Otherwise the board will be removed in the next
> release, and will need to be added and re-reviewed later.
Fabio, Stefano,
it seems (almost?) all i.mx6 boards should be removed within two weeks.
But would it not make more sense to convert the reference boards first
(mx6sabresd
in my case for tbs2910), and let hobbyist maintainers like me take this
as example for
their own modifications?
Simon, Tom,
is this really the usual u-boot working style to remove about hundred
boards within
two weeks without prior warning? As hobbyist board maintainer I try to
follow
new developments, and more than once I fixed up regressions introduced
by others
in general code.
But I cannot follow all development details without any heads-up. And
even the
NXP folks seem to be surprised about this.
All problems with this transition seem to be located around usbstorage
and sata.
This is for sure not really very board specific. Is there any migration
guide, or
examples how other SoC architectures did this conversion?
Regards,
Soeren
> The goal is to have all boards use driver model. But so far, we do allow
> CONFIG_DM to not be defined.
>
> PLEASE NOTE: This is not an easy process. It is possible that your board
> does work, or works with only minor changes. Please try to understand that
> the removal of a board is not done because people don't like your board.
> In fact the board might have been the first one I used when trying out
> U-Boot! It's just that we expect maintainers to keep up with the migration
> to driver model which has been running now for 4 years. It just isn't
> possible for a few people to migrate and test hundreds of boards.
>
> So, send a patch!
>
>
> Simon Glass (93):
> Add a simple script to remove boards
> dm: mmc: Use CONFIG_IS_ENABLED to check for BLK
> solidrun: Correct typo in MAINTAINERS
> arm: Remove s32v234evb board
> arm: Remove ls1043ardb_sdcard_SECURE_BOOT board
> arm: Remove ls1046ardb_sdcard_SECURE_BOOT board
> arm: Remove colibri_imx6_nospl board
> arm: Remove guruplug board
> arm: Remove sniper board
> arm: Remove omap3_zoom1 board
> arm: Remove sksimx6 board
> arm: Remove tbs2910 board
> arm: Remove theadorable_debug board
> arm: Remove devkit3250 board
> arm: Remove pcm051_rev3 board
> arm: Remove ds109 board
> arm: Remove pcm058 board
> arm: Remove am335x_shc_ict board
> arm: Remove vining_2000 board
> arm: Remove cm_t43 board
> arm: Remove igep00x0 board
> arm: Remove sheevaplug board
> arm: Remove omap3_overo board
> arm: Remove am335x_boneblack board
> arm: Remove warp7 board
> arm: Remove gwventana_gw5904 board
> arm: Remove cairo board
> arm: Remove pico-hobbit-imx7d board
> arm: Remove mccmon6_sd board
> arm: Remove apalis_imx6_nospl_it board
> arm: Remove wandboard board
> arm: Remove birdland_bav335a board
> arm: Remove gurnard board
> arm: Remove xpress_spl board
> arm: Remove udoo_neo board
> arm: Remove nas220 board
> arm: Remove am335x_pdu001 board
> arm: Remove snapper9260 board
> arm: Remove pfla02 board
> arm: Remove colibri_pxa270 board
> arm: Remove work_92105 board
> arm: Remove omap3_pandora board
> arm: Remove cl-som-imx7 board
> arm: Remove devkit8000 board
> arm: Remove pengwyn board
> arm: Remove dreamplug board
> arm: Remove mx6sabreauto board
> arm: Remove imx6q_logic board
> arm: Remove zc5202 board
> arm: Remove imx6dl_mamoj board
> arm: Remove omap3_logic_somlv board
> arm: Remove cm_t335 board
> arm: Remove liteboard board
> arm: Remove am43xx_evm_usbhost_boot board
> arm: Remove chiliboard board
> arm: Remove am335x_baltos board
> arm: Remove kp_imx6q_tpc board
> arm: Remove lsxhl board
> arm: Remove udoo board
> arm: Remove marsboard board
> arm: Remove mx6sabresd board
> arm: Remove dh_imx6 board
> arm: Remove vinco board
> arm: Remove ls1021atwr_sdcard_ifc_SECURE_BOOT board
> arm: Remove mx6cuboxi board
> arm: Remove ot1200 board
> arm: Remove socfpga_stratix10 board
> arm: Remove am65x_evm_a53 board
> arm: Remove ap143 board
> arm: Remove ap121 board
> arm: Remove imgtec_xilfpga board
> arm: Remove socfpga_de0_nano_soc board
> arm: Remove clearfog board
> arm: Remove socfpga_arria10 board
> arm: Remove omap3_beagle board
> arm: Remove helios4 board
> arm: Remove socfpga_socrates board
> arm: Remove socfpga_sr1500 board
> arm: Remove ls1021aiot_sdcard board
> arm: Remove socfpga_de10_nano board
> arm: Remove socfpga_dbm_soc1 board
> arm: Remove socfpga_de1_soc board
> arm: Remove socfpga_sockit board
> arm: Remove dns325 board
> arm: Remove socfpga_is1 board
> arm: Remove brppt1_mmc board
> arm: Remove db-mv784mp-gp board
> arm: Remove socfpga_arria5 board
> arm: Remove socfpga_vining_fpga board
> arm: Remove dra7xx_evm and dra7xx_hs_evm boards
> dm: Enable CONFIG_BLK
> dm: Update driver-model migration schedule for CONFIG_BLK
> RFC: dm: Force CONFIG_BLK for all boards with DM
>
> arch/arm/Kconfig | 13 -
> arch/arm/cpu/arm926ejs/lpc32xx/Kconfig | 2 -
> arch/arm/cpu/armv8/s32v234/Makefile | 6 -
> arch/arm/cpu/armv8/s32v234/cpu.c | 98 -
> arch/arm/cpu/armv8/s32v234/cpu.h | 7 -
> arch/arm/cpu/armv8/s32v234/generic.c | 349 ---
> arch/arm/dts/imx6dl-mamoj-u-boot.dtsi | 14 -
> arch/arm/dts/imx6dl-mamoj.dts | 225 --
> arch/arm/include/asm/arch-am33xx/chilisom.h | 14 -
> arch/arm/include/asm/arch-s32v234/clock.h | 33 -
> arch/arm/include/asm/arch-s32v234/ddr.h | 156 -
> arch/arm/include/asm/arch-s32v234/imx-regs.h | 328 ---
> arch/arm/include/asm/arch-s32v234/lpddr2.h | 74 -
> .../include/asm/arch-s32v234/mc_cgm_regs.h | 253 --
> .../arm/include/asm/arch-s32v234/mc_me_regs.h | 198 --
> .../include/asm/arch-s32v234/mc_rgm_regs.h | 30 -
> arch/arm/include/asm/arch-s32v234/mmdc.h | 88 -
> arch/arm/include/asm/arch-s32v234/siul.h | 149 -
> arch/arm/mach-at91/Kconfig | 3 -
> arch/arm/mach-imx/mx6/Kconfig | 24 -
> arch/arm/mach-imx/mx7/Kconfig | 3 -
> arch/arm/mach-k3/Kconfig | 1 -
> arch/arm/mach-kirkwood/Kconfig | 7 -
> arch/arm/mach-omap2/Kconfig | 5 -
> arch/arm/mach-omap2/am33xx/chilisom.c | 184 --
> arch/arm/mach-omap2/omap3/Kconfig | 9 -
> arch/arm/mach-omap2/omap5/Kconfig | 1 -
> arch/mips/Kconfig | 1 -
> arch/mips/mach-ath79/Kconfig | 2 -
> board/BuR/brppt1/Kconfig | 15 -
> board/BuR/brppt1/MAINTAINERS | 8 -
> board/BuR/brppt1/Makefile | 12 -
> board/BuR/brppt1/board.c | 190 --
> board/BuR/brppt1/config.mk | 36 -
> board/BuR/brppt1/mux.c | 253 --
> board/Marvell/db-mv784mp-gp/MAINTAINERS | 6 -
> board/Marvell/db-mv784mp-gp/Makefile | 5 -
> board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 117 -
> board/Marvell/dreamplug/Kconfig | 12 -
> board/Marvell/dreamplug/MAINTAINERS | 6 -
> board/Marvell/dreamplug/Makefile | 10 -
> board/Marvell/dreamplug/dreamplug.c | 135 -
> board/Marvell/dreamplug/dreamplug.h | 25 -
> board/Marvell/dreamplug/kwbimage.cfg | 145 -
> board/Marvell/guruplug/Kconfig | 12 -
> board/Marvell/guruplug/MAINTAINERS | 6 -
> board/Marvell/guruplug/Makefile | 7 -
> board/Marvell/guruplug/guruplug.c | 138 -
> board/Marvell/guruplug/guruplug.h | 22 -
> board/Marvell/guruplug/kwbimage.cfg | 144 -
> board/Marvell/sheevaplug/Kconfig | 12 -
> board/Marvell/sheevaplug/MAINTAINERS | 6 -
> board/Marvell/sheevaplug/Makefile | 7 -
> board/Marvell/sheevaplug/kwbimage.cfg | 144 -
> board/Marvell/sheevaplug/sheevaplug.c | 133 -
> board/Marvell/sheevaplug/sheevaplug.h | 24 -
> board/Seagate/nas220/Kconfig | 12 -
> board/Seagate/nas220/MAINTAINERS | 6 -
> board/Seagate/nas220/Makefile | 7 -
> board/Seagate/nas220/kwbimage.cfg | 151 -
> board/Seagate/nas220/nas220.c | 118 -
> board/Synology/ds109/Kconfig | 12 -
> board/Synology/ds109/MAINTAINERS | 6 -
> board/Synology/ds109/Makefile | 7 -
> board/Synology/ds109/ds109.c | 176 --
> board/Synology/ds109/ds109.h | 43 -
> board/Synology/ds109/kwbimage.cfg | 150 -
> board/Synology/ds109/openocd.cfg | 115 -
> board/altera/arria10-socdk/Kconfig | 18 -
> board/altera/arria10-socdk/MAINTAINERS | 7 -
> board/altera/arria10-socdk/Makefile | 5 -
> board/altera/arria10-socdk/socfpga.c | 6 -
> board/altera/arria5-socdk/MAINTAINERS | 7 -
> board/altera/arria5-socdk/Makefile | 7 -
> board/altera/arria5-socdk/qts/iocsr_config.h | 695 -----
> board/altera/arria5-socdk/qts/pinmux_config.h | 218 --
> board/altera/arria5-socdk/qts/pll_config.h | 84 -
> board/altera/arria5-socdk/qts/sdram_config.h | 342 ---
> board/altera/arria5-socdk/socfpga.c | 5 -
> board/altera/cyclone5-socdk/MAINTAINERS | 12 -
> board/altera/cyclone5-socdk/Makefile | 7 -
> .../altera/cyclone5-socdk/qts/iocsr_config.h | 659 -----
> .../altera/cyclone5-socdk/qts/pinmux_config.h | 218 --
> board/altera/cyclone5-socdk/qts/pll_config.h | 84 -
> .../altera/cyclone5-socdk/qts/sdram_config.h | 344 ---
> board/altera/cyclone5-socdk/socfpga.c | 5 -
> board/altera/stratix10-socdk/MAINTAINERS | 7 -
> board/altera/stratix10-socdk/Makefile | 7 -
> board/altera/stratix10-socdk/socfpga.c | 7 -
> board/bachmann/ot1200/Kconfig | 12 -
> board/bachmann/ot1200/MAINTAINERS | 6 -
> board/bachmann/ot1200/Makefile | 11 -
> board/bachmann/ot1200/README | 20 -
> board/bachmann/ot1200/mx6q_4x_mt41j128.cfg | 154 -
> board/bachmann/ot1200/ot1200.c | 356 ---
> board/bachmann/ot1200/ot1200_spl.c | 151 -
> board/birdland/bav335x/Kconfig | 23 -
> board/birdland/bav335x/Makefile | 11 -
> board/birdland/bav335x/README | 31 -
> board/birdland/bav335x/board.c | 429 ---
> board/birdland/bav335x/board.h | 58 -
> board/birdland/bav335x/mux.c | 190 --
> board/birdland/bav335x/u-boot.lds | 115 -
> board/bluewater/gurnard/Kconfig | 12 -
> board/bluewater/gurnard/MAINTAINERS | 6 -
> board/bluewater/gurnard/Makefile | 9 -
> board/bluewater/gurnard/gurnard.c | 423 ---
> board/bluewater/gurnard/splash_logo.h | 2619 -----------------
> board/bluewater/snapper9260/Kconfig | 12 -
> board/bluewater/snapper9260/MAINTAINERS | 7 -
> board/bluewater/snapper9260/Makefile | 9 -
> board/bluewater/snapper9260/snapper9260.c | 151 -
> board/bosch/shc/Kconfig | 87 -
> board/bosch/shc/MAINTAINERS | 11 -
> board/bosch/shc/Makefile | 8 -
> board/bosch/shc/README | 114 -
> board/bosch/shc/board.c | 647 ----
> board/bosch/shc/board.h | 186 --
> board/bosch/shc/mux.c | 260 --
> board/bticino/mamoj/Kconfig | 12 -
> board/bticino/mamoj/MAINTAINERS | 10 -
> board/bticino/mamoj/Makefile | 8 -
> board/bticino/mamoj/README | 124 -
> board/bticino/mamoj/mamoj.c | 26 -
> board/bticino/mamoj/spl.c | 171 --
> board/buffalo/lsxl/Kconfig | 12 -
> board/buffalo/lsxl/MAINTAINERS | 7 -
> board/buffalo/lsxl/Makefile | 6 -
> board/buffalo/lsxl/README | 139 -
> board/buffalo/lsxl/kwbimage-lschl.cfg | 211 --
> board/buffalo/lsxl/kwbimage-lsxhl.cfg | 211 --
> board/buffalo/lsxl/lsxl.c | 279 --
> board/buffalo/lsxl/lsxl.h | 58 -
> board/ccv/xpress/Kconfig | 12 -
> board/ccv/xpress/MAINTAINERS | 7 -
> board/ccv/xpress/Makefile | 6 -
> board/ccv/xpress/imximage.cfg | 175 --
> board/ccv/xpress/spl.c | 117 -
> board/ccv/xpress/xpress.c | 336 ---
> board/compulab/cl-som-imx7/Kconfig | 28 -
> board/compulab/cl-som-imx7/MAINTAINERS | 6 -
> board/compulab/cl-som-imx7/Makefile | 17 -
> board/compulab/cl-som-imx7/cl-som-imx7.c | 331 ---
> board/compulab/cl-som-imx7/common.c | 45 -
> board/compulab/cl-som-imx7/common.h | 31 -
> board/compulab/cl-som-imx7/mux.c | 141 -
> board/compulab/cl-som-imx7/spl.c | 210 --
> board/compulab/cm_t335/Kconfig | 15 -
> board/compulab/cm_t335/MAINTAINERS | 6 -
> board/compulab/cm_t335/Makefile | 8 -
> board/compulab/cm_t335/cm_t335.c | 162 -
> board/compulab/cm_t335/mux.c | 116 -
> board/compulab/cm_t335/spl.c | 113 -
> board/compulab/cm_t335/u-boot.lds | 110 -
> board/compulab/cm_t43/Kconfig | 15 -
> board/compulab/cm_t43/MAINTAINERS | 6 -
> board/compulab/cm_t43/Makefile | 11 -
> board/compulab/cm_t43/board.h | 11 -
> board/compulab/cm_t43/cm_t43.c | 164 --
> board/compulab/cm_t43/mux.c | 142 -
> board/compulab/cm_t43/spl.c | 134 -
> board/d-link/dns325/Kconfig | 12 -
> board/d-link/dns325/MAINTAINERS | 6 -
> board/d-link/dns325/Makefile | 11 -
> board/d-link/dns325/dns325.c | 131 -
> board/d-link/dns325/dns325.h | 31 -
> board/d-link/dns325/kwbimage.cfg | 190 --
> board/dhelectronics/dh_imx6/Kconfig | 12 -
> board/dhelectronics/dh_imx6/MAINTAINERS | 7 -
> board/dhelectronics/dh_imx6/Makefile | 9 -
> board/dhelectronics/dh_imx6/dh_imx6.c | 431 ---
> board/dhelectronics/dh_imx6/dh_imx6_spl.c | 591 ----
> board/ebv/socrates/MAINTAINERS | 6 -
> board/ebv/socrates/Makefile | 7 -
> board/ebv/socrates/qts/iocsr_config.h | 659 -----
> board/ebv/socrates/qts/pinmux_config.h | 218 --
> board/ebv/socrates/qts/pll_config.h | 84 -
> board/ebv/socrates/qts/sdram_config.h | 343 ---
> board/ebv/socrates/socfpga.c | 5 -
> board/eets/pdu001/Kconfig | 50 -
> board/eets/pdu001/MAINTAINERS | 6 -
> board/eets/pdu001/Makefile | 13 -
> board/eets/pdu001/README | 35 -
> board/eets/pdu001/board.c | 275 --
> board/eets/pdu001/board.h | 37 -
> board/eets/pdu001/mux.c | 119 -
> board/el/el6x/Kconfig | 25 -
> board/el/el6x/MAINTAINERS | 8 -
> board/el/el6x/Makefile | 5 -
> board/el/el6x/el6x.c | 631 ----
> board/embest/mx6boards/Kconfig | 12 -
> board/embest/mx6boards/MAINTAINERS | 7 -
> board/embest/mx6boards/Makefile | 7 -
> board/embest/mx6boards/mx6boards.c | 610 ----
> board/freescale/ls1021aiot/Kconfig | 17 -
> board/freescale/ls1021aiot/MAINTAINERS | 7 -
> board/freescale/ls1021aiot/Makefile | 7 -
> board/freescale/ls1021aiot/README | 58 -
> board/freescale/ls1021aiot/dcu.c | 46 -
> board/freescale/ls1021aiot/ls1021aiot.c | 249 --
> board/freescale/ls1021aiot/ls102xa_pbi.cfg | 14 -
> board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | 27 -
> board/freescale/ls1021aiot/psci.S | 27 -
> board/freescale/ls1021atwr/Kconfig | 17 -
> board/freescale/ls1021atwr/MAINTAINERS | 15 -
> board/freescale/ls1021atwr/Makefile | 9 -
> board/freescale/ls1021atwr/README | 115 -
> board/freescale/ls1021atwr/dcu.c | 46 -
> board/freescale/ls1021atwr/ls1021atwr.c | 764 -----
> board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 -
> .../ls1021atwr/ls102xa_rcw_sd_ifc.cfg | 8 -
> .../ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 8 -
> board/freescale/ls1021atwr/psci.S | 24 -
> board/freescale/ls1043ardb/Kconfig | 41 -
> board/freescale/ls1043ardb/MAINTAINERS | 16 -
> board/freescale/ls1043ardb/Makefile | 10 -
> board/freescale/ls1043ardb/README | 54 -
> board/freescale/ls1043ardb/cpld.c | 173 --
> board/freescale/ls1043ardb/cpld.h | 45 -
> board/freescale/ls1043ardb/ddr.c | 238 --
> board/freescale/ls1043ardb/ddr.h | 116 -
> board/freescale/ls1043ardb/eth.c | 76 -
> board/freescale/ls1043ardb/ls1043ardb.c | 221 --
> board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 -
> .../ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 -
> .../ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 -
> board/freescale/ls1046ardb/Kconfig | 31 -
> board/freescale/ls1046ardb/MAINTAINERS | 20 -
> board/freescale/ls1046ardb/Makefile | 10 -
> board/freescale/ls1046ardb/README | 76 -
> board/freescale/ls1046ardb/cpld.c | 166 --
> board/freescale/ls1046ardb/cpld.h | 49 -
> board/freescale/ls1046ardb/ddr.c | 119 -
> board/freescale/ls1046ardb/ddr.h | 62 -
> board/freescale/ls1046ardb/eth.c | 127 -
> board/freescale/ls1046ardb/ls1046ardb.c | 182 --
> board/freescale/ls1046ardb/ls1046ardb_pbi.cfg | 22 -
> .../ls1046ardb/ls1046ardb_qspi_pbi.cfg | 26 -
> .../ls1046ardb/ls1046ardb_rcw_emmc.cfg | 7 -
> .../ls1046ardb/ls1046ardb_rcw_qspi.cfg | 7 -
> .../ls1046ardb/ls1046ardb_rcw_sd.cfg | 7 -
> board/freescale/mx6sabreauto/Kconfig | 12 -
> board/freescale/mx6sabreauto/MAINTAINERS | 7 -
> board/freescale/mx6sabreauto/Makefile | 7 -
> board/freescale/mx6sabreauto/README | 82 -
> board/freescale/mx6sabreauto/mx6sabreauto.c | 1099 -------
> board/freescale/mx6sabresd/Kconfig | 12 -
> board/freescale/mx6sabresd/MAINTAINERS | 6 -
> board/freescale/mx6sabresd/Makefile | 7 -
> board/freescale/mx6sabresd/README | 114 -
> board/freescale/mx6sabresd/mx6sabresd.c | 1064 -------
> board/freescale/s32v234evb/Kconfig | 23 -
> board/freescale/s32v234evb/MAINTAINERS | 8 -
> board/freescale/s32v234evb/Makefile | 9 -
> board/freescale/s32v234evb/clock.c | 343 ---
> board/freescale/s32v234evb/lpddr2.c | 136 -
> board/freescale/s32v234evb/s32v234evb.c | 182 --
> board/freescale/s32v234evb/s32v234evb.cfg | 28 -
> board/gateworks/gw_ventana/Kconfig | 25 -
> board/gateworks/gw_ventana/MAINTAINERS | 8 -
> board/gateworks/gw_ventana/Makefile | 11 -
> board/gateworks/gw_ventana/README | 320 --
> board/gateworks/gw_ventana/common.c | 1422 ---------
> board/gateworks/gw_ventana/common.h | 98 -
> board/gateworks/gw_ventana/eeprom.c | 238 --
> board/gateworks/gw_ventana/gsc.c | 274 --
> board/gateworks/gw_ventana/gsc.h | 70 -
> board/gateworks/gw_ventana/gw_ventana.c | 1351 ---------
> board/gateworks/gw_ventana/gw_ventana_spl.c | 691 -----
> board/gateworks/gw_ventana/ventana_eeprom.h | 133 -
> board/grinn/chiliboard/Kconfig | 15 -
> board/grinn/chiliboard/MAINTAINERS | 8 -
> board/grinn/chiliboard/Makefile | 4 -
> board/grinn/chiliboard/README | 31 -
> board/grinn/chiliboard/board.c | 205 --
> board/grinn/liteboard/Kconfig | 12 -
> board/grinn/liteboard/MAINTAINERS | 6 -
> board/grinn/liteboard/Makefile | 4 -
> board/grinn/liteboard/README | 31 -
> board/grinn/liteboard/board.c | 286 --
> board/imgtec/xilfpga/Kconfig | 15 -
> board/imgtec/xilfpga/MAINTAINERS | 6 -
> board/imgtec/xilfpga/Makefile | 7 -
> board/imgtec/xilfpga/README | 55 -
> board/imgtec/xilfpga/xilfpga.c | 23 -
> board/is1/MAINTAINERS | 6 -
> board/is1/Makefile | 5 -
> board/is1/qts/iocsr_config.h | 659 -----
> board/is1/qts/pinmux_config.h | 218 --
> board/is1/qts/pll_config.h | 84 -
> board/is1/qts/sdram_config.h | 343 ---
> board/is1/socfpga.c | 4 -
> board/isee/igep00x0/Kconfig | 12 -
> board/isee/igep00x0/MAINTAINERS | 7 -
> board/isee/igep00x0/Makefile | 10 -
> board/isee/igep00x0/common.c | 67 -
> board/isee/igep00x0/igep00x0.c | 258 --
> board/isee/igep00x0/igep00x0.h | 127 -
> board/isee/igep00x0/spl.c | 63 -
> board/k+p/kp_imx6q_tpc/Kconfig | 12 -
> board/k+p/kp_imx6q_tpc/MAINTAINERS | 6 -
> board/k+p/kp_imx6q_tpc/Makefile | 9 -
> board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 301 --
> board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 337 ---
> board/kobol/helios4/MAINTAINERS | 6 -
> board/kobol/helios4/Makefile | 5 -
> board/kobol/helios4/README | 46 -
> board/kobol/helios4/helios4.c | 163 -
> board/l+g/vinco/Kconfig | 12 -
> board/l+g/vinco/MAINTAINERS | 6 -
> board/l+g/vinco/Makefile | 1 -
> board/l+g/vinco/vinco.c | 212 --
> board/lg/sniper/Kconfig | 12 -
> board/lg/sniper/MAINTAINERS | 6 -
> board/lg/sniper/Makefile | 7 -
> board/lg/sniper/sniper.c | 189 --
> board/lg/sniper/sniper.h | 364 ---
> board/liebherr/mccmon6/Kconfig | 12 -
> board/liebherr/mccmon6/MAINTAINERS | 7 -
> board/liebherr/mccmon6/Makefile | 6 -
> board/liebherr/mccmon6/mccmon6.c | 489 ---
> board/liebherr/mccmon6/mon6_imximage_nor.cfg | 8 -
> board/liebherr/mccmon6/mon6_imximage_sd.cfg | 8 -
> board/liebherr/mccmon6/spl.c | 298 --
> board/logicpd/imx6/Kconfig | 12 -
> board/logicpd/imx6/MAINTAINERS | 6 -
> board/logicpd/imx6/Makefile | 10 -
> board/logicpd/imx6/README | 37 -
> board/logicpd/imx6/imx6logic.c | 325 --
> board/logicpd/omap3som/Kconfig | 14 -
> board/logicpd/omap3som/MAINTAINERS | 9 -
> board/logicpd/omap3som/Makefile | 6 -
> board/logicpd/omap3som/README | 56 -
> board/logicpd/omap3som/omap3logic.c | 329 ---
> board/logicpd/omap3som/omap3logic.h | 236 --
> board/logicpd/zoom1/Kconfig | 12 -
> board/logicpd/zoom1/MAINTAINERS | 6 -
> board/logicpd/zoom1/Makefile | 6 -
> board/logicpd/zoom1/config.mk | 14 -
> board/logicpd/zoom1/zoom1.c | 146 -
> board/logicpd/zoom1/zoom1.h | 122 -
> board/overo/Kconfig | 9 -
> board/overo/MAINTAINERS | 6 -
> board/overo/Makefile | 10 -
> board/overo/common.c | 341 ---
> board/overo/overo.c | 420 ---
> board/overo/overo.h | 169 --
> board/overo/spl.c | 59 -
> board/pandora/Kconfig | 9 -
> board/pandora/MAINTAINERS | 6 -
> board/pandora/Makefile | 6 -
> board/pandora/pandora.c | 147 -
> board/pandora/pandora.h | 391 ---
> board/phytec/pcm051/Kconfig | 15 -
> board/phytec/pcm051/MAINTAINERS | 7 -
> board/phytec/pcm051/Makefile | 11 -
> board/phytec/pcm051/board.c | 256 --
> board/phytec/pcm051/board.h | 24 -
> board/phytec/pcm051/mux.c | 127 -
> board/phytec/pcm058/Kconfig | 12 -
> board/phytec/pcm058/MAINTAINERS | 6 -
> board/phytec/pcm058/Makefile | 7 -
> board/phytec/pcm058/README | 35 -
> board/phytec/pcm058/pcm058.c | 568 ----
> board/phytec/pfla02/Kconfig | 18 -
> board/phytec/pfla02/MAINTAINERS | 6 -
> board/phytec/pfla02/Makefile | 7 -
> board/phytec/pfla02/README | 24 -
> board/phytec/pfla02/pfla02.c | 707 -----
> board/qca/ap121/Kconfig | 27 -
> board/qca/ap121/MAINTAINERS | 6 -
> board/qca/ap121/Makefile | 3 -
> board/qca/ap121/ap121.c | 46 -
> board/qca/ap143/Kconfig | 27 -
> board/qca/ap143/MAINTAINERS | 6 -
> board/qca/ap143/Makefile | 3 -
> board/qca/ap143/ap143.c | 62 -
> board/quipos/cairo/Kconfig | 12 -
> board/quipos/cairo/MAINTAINERS | 6 -
> board/quipos/cairo/Makefile | 6 -
> board/quipos/cairo/cairo.c | 98 -
> board/quipos/cairo/cairo.h | 318 --
> board/samtec/vining_2000/Kconfig | 12 -
> board/samtec/vining_2000/MAINTAINERS | 6 -
> board/samtec/vining_2000/Makefile | 4 -
> board/samtec/vining_2000/imximage.cfg | 131 -
> board/samtec/vining_2000/vining_2000.c | 517 ----
> board/silica/pengwyn/Kconfig | 15 -
> board/silica/pengwyn/MAINTAINERS | 6 -
> board/silica/pengwyn/Makefile | 11 -
> board/silica/pengwyn/board.c | 201 --
> board/silica/pengwyn/board.h | 14 -
> board/silica/pengwyn/mux.c | 97 -
> board/sks-kinkel/sksimx6/Kconfig | 11 -
> board/sks-kinkel/sksimx6/MAINTAINERS | 6 -
> board/sks-kinkel/sksimx6/Makefile | 2 -
> board/sks-kinkel/sksimx6/sksimx6.c | 425 ---
> board/solidrun/clearfog/MAINTAINERS | 6 -
> board/solidrun/clearfog/Makefile | 5 -
> board/solidrun/clearfog/README | 51 -
> board/solidrun/clearfog/clearfog.c | 141 -
> board/solidrun/mx6cuboxi/Kconfig | 12 -
> board/solidrun/mx6cuboxi/MAINTAINERS | 6 -
> board/solidrun/mx6cuboxi/Makefile | 7 -
> board/solidrun/mx6cuboxi/README | 21 -
> board/solidrun/mx6cuboxi/mx6cuboxi.c | 857 ------
> board/sr1500/MAINTAINERS | 6 -
> board/sr1500/Makefile | 5 -
> board/sr1500/qts/iocsr_config.h | 659 -----
> board/sr1500/qts/pinmux_config.h | 218 --
> board/sr1500/qts/pll_config.h | 84 -
> board/sr1500/qts/sdram_config.h | 343 ---
> board/sr1500/socfpga.c | 26 -
> board/tbs/tbs2910/Kconfig | 18 -
> board/tbs/tbs2910/MAINTAINERS | 6 -
> board/tbs/tbs2910/Makefile | 5 -
> board/tbs/tbs2910/tbs2910.c | 454 ---
> board/tbs/tbs2910/tbs2910.cfg | 114 -
> board/technexion/pico-imx7d/Kconfig | 15 -
> board/technexion/pico-imx7d/MAINTAINERS | 16 -
> board/technexion/pico-imx7d/Makefile | 4 -
> board/technexion/pico-imx7d/README | 64 -
> board/technexion/pico-imx7d/pico-imx7d.c | 315 --
> board/technexion/pico-imx7d/spl.c | 122 -
> board/theadorable/MAINTAINERS | 6 -
> board/theadorable/Makefile | 6 -
> board/theadorable/fpga.c | 178 --
> board/theadorable/theadorable.c | 336 ---
> board/theadorable/theadorable.h | 11 -
> board/ti/am335x/Kconfig | 24 -
> board/ti/am335x/MAINTAINERS | 12 -
> board/ti/am335x/Makefile | 11 -
> board/ti/am335x/README | 205 --
> board/ti/am335x/board.c | 1073 -------
> board/ti/am335x/board.h | 97 -
> board/ti/am335x/mux.c | 413 ---
> board/ti/am335x/u-boot.lds | 164 --
> board/ti/am43xx/Kconfig | 17 -
> board/ti/am43xx/MAINTAINERS | 11 -
> board/ti/am43xx/Makefile | 11 -
> board/ti/am43xx/board.c | 957 ------
> board/ti/am43xx/board.h | 62 -
> board/ti/am43xx/mux.c | 153 -
> board/ti/am65x/Kconfig | 52 -
> board/ti/am65x/MAINTAINERS | 7 -
> board/ti/am65x/Makefile | 8 -
> board/ti/am65x/README | 211 --
> board/ti/am65x/evm.c | 68 -
> board/ti/beagle/Kconfig | 12 -
> board/ti/beagle/MAINTAINERS | 6 -
> board/ti/beagle/Makefile | 7 -
> board/ti/beagle/beagle.c | 591 ----
> board/ti/beagle/beagle.h | 545 ----
> board/ti/beagle/led.c | 71 -
> board/ti/dra7xx/Kconfig | 14 -
> board/ti/dra7xx/MAINTAINERS | 7 -
> board/ti/dra7xx/Makefile | 6 -
> board/ti/dra7xx/README | 26 -
> board/ti/dra7xx/evm.c | 1202 --------
> board/ti/dra7xx/mux_data.h | 1121 -------
> board/timll/devkit3250/Kconfig | 12 -
> board/timll/devkit3250/MAINTAINERS | 6 -
> board/timll/devkit3250/Makefile | 7 -
> board/timll/devkit3250/devkit3250.c | 80 -
> board/timll/devkit3250/devkit3250_spl.c | 67 -
> board/timll/devkit8000/Kconfig | 12 -
> board/timll/devkit8000/MAINTAINERS | 6 -
> board/timll/devkit8000/Makefile | 9 -
> board/timll/devkit8000/README | 15 -
> board/timll/devkit8000/devkit8000.c | 206 --
> board/timll/devkit8000/devkit8000.h | 359 ---
> .../toradex/apalis_imx6/1066mhz_4x128mx16.cfg | 47 -
> .../toradex/apalis_imx6/1066mhz_4x256mx16.cfg | 47 -
> board/toradex/apalis_imx6/Kconfig | 55 -
> board/toradex/apalis_imx6/MAINTAINERS | 9 -
> board/toradex/apalis_imx6/Makefile | 5 -
> board/toradex/apalis_imx6/apalis_imx6.c | 1236 --------
> board/toradex/apalis_imx6/apalis_imx6q.cfg | 33 -
> board/toradex/apalis_imx6/clocks.cfg | 41 -
> board/toradex/apalis_imx6/ddr-setup.cfg | 96 -
> board/toradex/apalis_imx6/do_fuse.c | 97 -
> board/toradex/apalis_imx6/pf0100.c | 230 --
> board/toradex/apalis_imx6/pf0100.h | 52 -
> board/toradex/apalis_imx6/pf0100_otp.inc | 190 --
> .../toradex/colibri_imx6/800mhz_2x64mx16.cfg | 58 -
> .../toradex/colibri_imx6/800mhz_4x64mx16.cfg | 58 -
> board/toradex/colibri_imx6/Kconfig | 44 -
> board/toradex/colibri_imx6/MAINTAINERS | 8 -
> board/toradex/colibri_imx6/Makefile | 5 -
> board/toradex/colibri_imx6/clocks.cfg | 41 -
> board/toradex/colibri_imx6/colibri_imx6.c | 1121 -------
> board/toradex/colibri_imx6/colibri_imx6.cfg | 37 -
> board/toradex/colibri_imx6/ddr-setup.cfg | 97 -
> board/toradex/colibri_imx6/do_fuse.c | 97 -
> board/toradex/colibri_imx6/pf0100.c | 212 --
> board/toradex/colibri_imx6/pf0100.h | 52 -
> board/toradex/colibri_imx6/pf0100_otp.inc | 188 --
> board/toradex/colibri_pxa270/Kconfig | 23 -
> board/toradex/colibri_pxa270/MAINTAINERS | 6 -
> board/toradex/colibri_pxa270/Makefile | 7 -
> board/toradex/colibri_pxa270/colibri_pxa270.c | 138 -
> board/udoo/Kconfig | 9 -
> board/udoo/MAINTAINERS | 6 -
> board/udoo/Makefile | 5 -
> board/udoo/README | 21 -
> board/udoo/neo/Kconfig | 12 -
> board/udoo/neo/MAINTAINERS | 7 -
> board/udoo/neo/Makefile | 4 -
> board/udoo/neo/neo.c | 595 ----
> board/udoo/udoo.c | 271 --
> board/udoo/udoo_spl.c | 254 --
> board/vscom/baltos/Kconfig | 15 -
> board/vscom/baltos/MAINTAINERS | 6 -
> board/vscom/baltos/Makefile | 11 -
> board/vscom/baltos/README | 1 -
> board/vscom/baltos/board.c | 493 ----
> board/vscom/baltos/board.h | 34 -
> board/vscom/baltos/mux.c | 125 -
> board/vscom/baltos/u-boot.lds | 128 -
> board/wandboard/Kconfig | 9 -
> board/wandboard/MAINTAINERS | 6 -
> board/wandboard/Makefile | 5 -
> board/wandboard/README | 39 -
> board/wandboard/spl.c | 425 ---
> board/wandboard/wandboard.c | 559 ----
> board/warp7/Kconfig | 23 -
> board/warp7/MAINTAINERS | 7 -
> board/warp7/Makefile | 4 -
> board/warp7/README | 63 -
> board/warp7/imximage.cfg | 98 -
> board/warp7/warp7.c | 237 --
> board/work-microwave/work_92105/Kconfig | 24 -
> board/work-microwave/work_92105/MAINTAINERS | 6 -
> board/work-microwave/work_92105/Makefile | 10 -
> board/work-microwave/work_92105/README | 91 -
> board/work-microwave/work_92105/work_92105.c | 76 -
> .../work_92105/work_92105_display.c | 348 ---
> .../work_92105/work_92105_display.h | 13 -
> .../work_92105/work_92105_spl.c | 84 -
> configs/am335x_baltos_defconfig | 65 -
> configs/am335x_boneblack_defconfig | 51 -
> configs/am335x_boneblack_vboot_defconfig | 56 -
> configs/am335x_evm_defconfig | 64 -
> configs/am335x_evm_nor_defconfig | 53 -
> configs/am335x_evm_norboot_defconfig | 50 -
> configs/am335x_evm_spiboot_defconfig | 48 -
> configs/am335x_evm_usbspl_defconfig | 56 -
> configs/am335x_pdu001_defconfig | 53 -
> configs/am335x_shc_defconfig | 46 -
> configs/am335x_shc_ict_defconfig | 47 -
> configs/am335x_shc_netboot_defconfig | 48 -
> configs/am335x_shc_prompt_defconfig | 45 -
> configs/am335x_shc_sdboot_defconfig | 47 -
> configs/am335x_shc_sdboot_prompt_defconfig | 47 -
> configs/am43xx_evm_defconfig | 61 -
> configs/am43xx_evm_ethboot_defconfig | 65 -
> configs/am43xx_evm_qspiboot_defconfig | 63 -
> configs/am43xx_evm_rtconly_defconfig | 62 -
> configs/am43xx_evm_usbhost_boot_defconfig | 75 -
> configs/am43xx_hs_evm_defconfig | 72 -
> configs/am65x_evm_a53_defconfig | 71 -
> configs/am65x_evm_r5_defconfig | 87 -
> configs/ap121_defconfig | 60 -
> configs/ap143_defconfig | 55 -
> configs/apalis_imx6_defconfig | 75 -
> configs/apalis_imx6_nospl_com_defconfig | 63 -
> configs/apalis_imx6_nospl_it_defconfig | 63 -
> configs/birdland_bav335a_defconfig | 67 -
> configs/birdland_bav335b_defconfig | 67 -
> configs/brppt1_mmc_defconfig | 95 -
> configs/brppt1_nand_defconfig | 99 -
> configs/brppt1_spi_defconfig | 109 -
> configs/cairo_defconfig | 39 -
> configs/chiliboard_defconfig | 47 -
> configs/cl-som-imx7_defconfig | 67 -
> configs/clearfog_defconfig | 66 -
> configs/cm_t335_defconfig | 51 -
> configs/cm_t43_defconfig | 72 -
> configs/colibri_imx6_defconfig | 73 -
> configs/colibri_imx6_nospl_defconfig | 61 -
> configs/colibri_pxa270_defconfig | 40 -
> configs/db-mv784mp-gp_defconfig | 64 -
> configs/devkit3250_defconfig | 48 -
> configs/devkit8000_defconfig | 34 -
> configs/dh_imx6_defconfig | 63 -
> configs/dns325_defconfig | 41 -
> configs/dra7xx_evm_defconfig | 102 -
> configs/dra7xx_hs_evm_defconfig | 101 -
> configs/dreamplug_defconfig | 40 -
> configs/ds109_defconfig | 38 -
> configs/gurnard_defconfig | 38 -
> configs/guruplug_defconfig | 43 -
> configs/gwventana_emmc_defconfig | 88 -
> configs/gwventana_gw5904_defconfig | 92 -
> configs/gwventana_nand_defconfig | 91 -
> configs/helios4_defconfig | 60 -
> configs/igep0032_defconfig | 52 -
> configs/igep00x0_defconfig | 53 -
> configs/imgtec_xilfpga_defconfig | 27 -
> configs/imx6dl_mamoj_defconfig | 46 -
> configs/imx6q_logic_defconfig | 77 -
> configs/kp_imx6q_tpc_defconfig | 44 -
> configs/liteboard_defconfig | 38 -
> configs/ls1021aiot_qspi_defconfig | 39 -
> configs/ls1021aiot_sdcard_defconfig | 44 -
> configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 56 -
> configs/ls1021atwr_nor_defconfig | 59 -
> configs/ls1021atwr_nor_lpuart_defconfig | 57 -
> configs/ls1021atwr_qspi_defconfig | 60 -
> ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 70 -
> configs/ls1021atwr_sdcard_ifc_defconfig | 67 -
> configs/ls1021atwr_sdcard_qspi_defconfig | 70 -
> configs/ls1043ardb_SECURE_BOOT_defconfig | 51 -
> configs/ls1043ardb_defconfig | 49 -
> configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 68 -
> configs/ls1043ardb_nand_defconfig | 66 -
> .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 66 -
> configs/ls1043ardb_sdcard_defconfig | 64 -
> configs/ls1046ardb_emmc_defconfig | 63 -
> configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 49 -
> configs/ls1046ardb_qspi_defconfig | 49 -
> configs/ls1046ardb_qspi_spl_defconfig | 66 -
> .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 64 -
> configs/ls1046ardb_sdcard_defconfig | 62 -
> configs/lschlv2_defconfig | 42 -
> configs/lsxhl_defconfig | 42 -
> configs/marsboard_defconfig | 37 -
> configs/mccmon6_nor_defconfig | 50 -
> configs/mccmon6_sd_defconfig | 51 -
> configs/mx6cuboxi_defconfig | 43 -
> configs/mx6sabreauto_defconfig | 67 -
> configs/mx6sabresd_defconfig | 75 -
> configs/nas220_defconfig | 42 -
> configs/omap35_logic_defconfig | 72 -
> configs/omap35_logic_somlv_defconfig | 78 -
> configs/omap3_beagle_defconfig | 82 -
> configs/omap3_logic_defconfig | 73 -
> configs/omap3_logic_somlv_defconfig | 78 -
> configs/omap3_overo_defconfig | 51 -
> configs/omap3_pandora_defconfig | 40 -
> configs/omap3_zoom1_defconfig | 39 -
> configs/ot1200_defconfig | 46 -
> configs/ot1200_spl_defconfig | 55 -
> configs/pcm051_rev1_defconfig | 58 -
> configs/pcm051_rev3_defconfig | 58 -
> configs/pcm058_defconfig | 57 -
> configs/pengwyn_defconfig | 62 -
> configs/pfla02_defconfig | 57 -
> configs/pico-hobbit-imx7d_defconfig | 60 -
> configs/pico-imx7d_defconfig | 60 -
> configs/pico-pi-imx7d_defconfig | 60 -
> configs/riotboard_defconfig | 37 -
> configs/s32v234evb_defconfig | 17 -
> configs/sheevaplug_defconfig | 44 -
> configs/sksimx6_defconfig | 42 -
> configs/snapper9260_defconfig | 34 -
> configs/snapper9g20_defconfig | 33 -
> configs/sniper_defconfig | 40 -
> configs/socfpga_arria10_defconfig | 44 -
> configs/socfpga_arria5_defconfig | 77 -
> configs/socfpga_cyclone5_defconfig | 78 -
> configs/socfpga_dbm_soc1_defconfig | 70 -
> configs/socfpga_de0_nano_soc_defconfig | 72 -
> configs/socfpga_de10_nano_defconfig | 68 -
> configs/socfpga_de1_soc_defconfig | 60 -
> configs/socfpga_is1_defconfig | 60 -
> configs/socfpga_sockit_defconfig | 78 -
> configs/socfpga_socrates_defconfig | 78 -
> configs/socfpga_sr1500_defconfig | 67 -
> configs/socfpga_stratix10_defconfig | 59 -
> configs/socfpga_vining_fpga_defconfig | 94 -
> configs/tbs2910_defconfig | 58 -
> configs/theadorable_debug_defconfig | 74 -
> configs/udoo_defconfig | 36 -
> configs/udoo_neo_defconfig | 33 -
> configs/vinco_defconfig | 40 -
> configs/vining_2000_defconfig | 43 -
> configs/wandboard_defconfig | 46 -
> configs/warp7_bl33_defconfig | 41 -
> configs/warp7_defconfig | 52 -
> configs/work_92105_defconfig | 41 -
> configs/xpress_defconfig | 32 -
> configs/xpress_spl_defconfig | 42 -
> configs/zc5202_defconfig | 42 -
> configs/zc5601_defconfig | 41 -
> doc/driver-model/MIGRATION.txt | 8 +-
> drivers/block/Kconfig | 2 +-
> drivers/core/Kconfig | 1 +
> drivers/mmc/Kconfig | 2 +-
> drivers/mmc/dw_mmc.c | 2 +-
> drivers/mmc/mmc-uclass.c | 2 +-
> drivers/mmc/mmc_write.c | 8 +-
> drivers/usb/Kconfig | 1 +
> include/configs/am335x_evm.h | 343 ---
> include/configs/am335x_shc.h | 263 --
> include/configs/am43xx_evm.h | 292 --
> include/configs/am65x_evm.h | 75 -
> include/configs/ap121.h | 46 -
> include/configs/ap143.h | 50 -
> include/configs/apalis_imx6.h | 277 --
> include/configs/baltos.h | 276 --
> include/configs/bav335x.h | 501 ----
> include/configs/brppt1.h | 214 --
> include/configs/chiliboard.h | 180 --
> include/configs/cl-som-imx7.h | 182 --
> include/configs/clearfog.h | 157 -
> include/configs/cm_t335.h | 152 -
> include/configs/cm_t43.h | 140 -
> include/configs/colibri_imx6.h | 251 --
> include/configs/colibri_pxa270.h | 188 --
> include/configs/db-mv784mp-gp.h | 99 -
> include/configs/devkit3250.h | 194 --
> include/configs/devkit8000.h | 190 --
> include/configs/dh_imx6.h | 178 --
> include/configs/dns325.h | 118 -
> include/configs/dra7xx_evm.h | 165 --
> include/configs/dreamplug.h | 83 -
> include/configs/ds109.h | 86 -
> include/configs/embestmx6boards.h | 150 -
> include/configs/guruplug.h | 82 -
> include/configs/gw_ventana.h | 355 ---
> include/configs/helios4.h | 172 --
> include/configs/imx6_logic.h | 172 --
> include/configs/imx6dl-mamoj.h | 99 -
> include/configs/kp_imx6q_tpc.h | 134 -
> include/configs/liteboard.h | 155 -
> include/configs/ls1021aiot.h | 251 --
> include/configs/ls1021atwr.h | 505 ----
> include/configs/ls1043ardb.h | 285 --
> include/configs/ls1046ardb.h | 220 --
> include/configs/lsxl.h | 149 -
> include/configs/mccmon6.h | 293 --
> include/configs/mx6cuboxi.h | 149 -
> include/configs/mx6sabreauto.h | 78 -
> include/configs/mx6sabresd.h | 67 -
> include/configs/nas220.h | 112 -
> include/configs/omap3_beagle.h | 233 --
> include/configs/omap3_cairo.h | 231 --
> include/configs/omap3_igep00x0.h | 135 -
> include/configs/omap3_logic.h | 210 --
> include/configs/omap3_overo.h | 192 --
> include/configs/omap3_pandora.h | 69 -
> include/configs/omap3_zoom1.h | 138 -
> include/configs/ot1200.h | 114 -
> include/configs/pcm051.h | 137 -
> include/configs/pcm058.h | 98 -
> include/configs/pdu001.h | 86 -
> include/configs/pengwyn.h | 171 --
> include/configs/pfla02.h | 157 -
> include/configs/pico-imx7d.h | 151 -
> include/configs/s32v234evb.h | 190 --
> include/configs/sheevaplug.h | 92 -
> include/configs/sksimx6.h | 96 -
> include/configs/snapper9260.h | 123 -
> include/configs/snapper9g45.h | 112 -
> include/configs/sniper.h | 154 -
> include/configs/socfpga_arria10_socdk.h | 50 -
> include/configs/socfpga_arria5_socdk.h | 22 -
> include/configs/socfpga_cyclone5_socdk.h | 22 -
> include/configs/socfpga_dbm_soc1.h | 95 -
> include/configs/socfpga_de0_nano_soc.h | 22 -
> include/configs/socfpga_de10_nano.h | 22 -
> include/configs/socfpga_de1_soc.h | 22 -
> include/configs/socfpga_is1.h | 34 -
> include/configs/socfpga_sockit.h | 22 -
> include/configs/socfpga_socrates.h | 22 -
> include/configs/socfpga_sr1500.h | 56 -
> include/configs/socfpga_stratix10_socdk.h | 221 --
> include/configs/socfpga_vining_fpga.h | 180 --
> include/configs/tbs2910.h | 158 -
> include/configs/theadorable.h | 125 -
> include/configs/udoo.h | 95 -
> include/configs/udoo_neo.h | 106 -
> include/configs/vinco.h | 118 -
> include/configs/vining_2000.h | 104 -
> include/configs/wandboard.h | 156 -
> include/configs/warp7.h | 169 --
> include/configs/work_92105.h | 161 -
> include/configs/xpress.h | 135 -
> include/configs/zc5202.h | 30 -
> include/configs/zc5601.h | 28 -
> include/dwmmc.h | 6 +-
> tools/rmboard.py | 145 +
> 783 files changed, 162 insertions(+), 87172 deletions(-)
> delete mode 100644 arch/arm/cpu/armv8/s32v234/Makefile
> delete mode 100644 arch/arm/cpu/armv8/s32v234/cpu.c
> delete mode 100644 arch/arm/cpu/armv8/s32v234/cpu.h
> delete mode 100644 arch/arm/cpu/armv8/s32v234/generic.c
> delete mode 100644 arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
> delete mode 100644 arch/arm/dts/imx6dl-mamoj.dts
> delete mode 100644 arch/arm/include/asm/arch-am33xx/chilisom.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/clock.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/ddr.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/imx-regs.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/lpddr2.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_me_regs.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/mmdc.h
> delete mode 100644 arch/arm/include/asm/arch-s32v234/siul.h
> delete mode 100644 arch/arm/mach-omap2/am33xx/chilisom.c
> delete mode 100644 board/BuR/brppt1/Kconfig
> delete mode 100644 board/BuR/brppt1/MAINTAINERS
> delete mode 100644 board/BuR/brppt1/Makefile
> delete mode 100644 board/BuR/brppt1/board.c
> delete mode 100644 board/BuR/brppt1/config.mk
> delete mode 100644 board/BuR/brppt1/mux.c
> delete mode 100644 board/Marvell/db-mv784mp-gp/MAINTAINERS
> delete mode 100644 board/Marvell/db-mv784mp-gp/Makefile
> delete mode 100644 board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
> delete mode 100644 board/Marvell/dreamplug/Kconfig
> delete mode 100644 board/Marvell/dreamplug/MAINTAINERS
> delete mode 100644 board/Marvell/dreamplug/Makefile
> delete mode 100644 board/Marvell/dreamplug/dreamplug.c
> delete mode 100644 board/Marvell/dreamplug/dreamplug.h
> delete mode 100644 board/Marvell/dreamplug/kwbimage.cfg
> delete mode 100644 board/Marvell/guruplug/Kconfig
> delete mode 100644 board/Marvell/guruplug/MAINTAINERS
> delete mode 100644 board/Marvell/guruplug/Makefile
> delete mode 100644 board/Marvell/guruplug/guruplug.c
> delete mode 100644 board/Marvell/guruplug/guruplug.h
> delete mode 100644 board/Marvell/guruplug/kwbimage.cfg
> delete mode 100644 board/Marvell/sheevaplug/Kconfig
> delete mode 100644 board/Marvell/sheevaplug/MAINTAINERS
> delete mode 100644 board/Marvell/sheevaplug/Makefile
> delete mode 100644 board/Marvell/sheevaplug/kwbimage.cfg
> delete mode 100644 board/Marvell/sheevaplug/sheevaplug.c
> delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h
> delete mode 100644 board/Seagate/nas220/Kconfig
> delete mode 100644 board/Seagate/nas220/MAINTAINERS
> delete mode 100644 board/Seagate/nas220/Makefile
> delete mode 100644 board/Seagate/nas220/kwbimage.cfg
> delete mode 100644 board/Seagate/nas220/nas220.c
> delete mode 100644 board/Synology/ds109/Kconfig
> delete mode 100644 board/Synology/ds109/MAINTAINERS
> delete mode 100644 board/Synology/ds109/Makefile
> delete mode 100644 board/Synology/ds109/ds109.c
> delete mode 100644 board/Synology/ds109/ds109.h
> delete mode 100644 board/Synology/ds109/kwbimage.cfg
> delete mode 100644 board/Synology/ds109/openocd.cfg
> delete mode 100644 board/altera/arria10-socdk/Kconfig
> delete mode 100644 board/altera/arria10-socdk/MAINTAINERS
> delete mode 100644 board/altera/arria10-socdk/Makefile
> delete mode 100644 board/altera/arria10-socdk/socfpga.c
> delete mode 100644 board/altera/arria5-socdk/MAINTAINERS
> delete mode 100644 board/altera/arria5-socdk/Makefile
> delete mode 100644 board/altera/arria5-socdk/qts/iocsr_config.h
> delete mode 100644 board/altera/arria5-socdk/qts/pinmux_config.h
> delete mode 100644 board/altera/arria5-socdk/qts/pll_config.h
> delete mode 100644 board/altera/arria5-socdk/qts/sdram_config.h
> delete mode 100644 board/altera/arria5-socdk/socfpga.c
> delete mode 100644 board/altera/cyclone5-socdk/MAINTAINERS
> delete mode 100644 board/altera/cyclone5-socdk/Makefile
> delete mode 100644 board/altera/cyclone5-socdk/qts/iocsr_config.h
> delete mode 100644 board/altera/cyclone5-socdk/qts/pinmux_config.h
> delete mode 100644 board/altera/cyclone5-socdk/qts/pll_config.h
> delete mode 100644 board/altera/cyclone5-socdk/qts/sdram_config.h
> delete mode 100644 board/altera/cyclone5-socdk/socfpga.c
> delete mode 100644 board/altera/stratix10-socdk/MAINTAINERS
> delete mode 100644 board/altera/stratix10-socdk/Makefile
> delete mode 100644 board/altera/stratix10-socdk/socfpga.c
> delete mode 100644 board/bachmann/ot1200/Kconfig
> delete mode 100644 board/bachmann/ot1200/MAINTAINERS
> delete mode 100644 board/bachmann/ot1200/Makefile
> delete mode 100644 board/bachmann/ot1200/README
> delete mode 100644 board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
> delete mode 100644 board/bachmann/ot1200/ot1200.c
> delete mode 100644 board/bachmann/ot1200/ot1200_spl.c
> delete mode 100644 board/birdland/bav335x/Kconfig
> delete mode 100644 board/birdland/bav335x/Makefile
> delete mode 100644 board/birdland/bav335x/README
> delete mode 100644 board/birdland/bav335x/board.c
> delete mode 100644 board/birdland/bav335x/board.h
> delete mode 100644 board/birdland/bav335x/mux.c
> delete mode 100644 board/birdland/bav335x/u-boot.lds
> delete mode 100644 board/bluewater/gurnard/Kconfig
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> delete mode 100644 board/bluewater/gurnard/gurnard.c
> delete mode 100644 board/bluewater/gurnard/splash_logo.h
> delete mode 100644 board/bluewater/snapper9260/Kconfig
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> delete mode 100644 board/bluewater/snapper9260/Makefile
> delete mode 100644 board/bluewater/snapper9260/snapper9260.c
> delete mode 100644 board/bosch/shc/Kconfig
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> delete mode 100644 board/bosch/shc/mux.c
> delete mode 100644 board/bticino/mamoj/Kconfig
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> delete mode 100644 board/buffalo/lsxl/Kconfig
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> delete mode 100644 board/buffalo/lsxl/kwbimage-lsxhl.cfg
> delete mode 100644 board/buffalo/lsxl/lsxl.c
> delete mode 100644 board/buffalo/lsxl/lsxl.h
> delete mode 100644 board/ccv/xpress/Kconfig
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> delete mode 100644 board/ccv/xpress/imximage.cfg
> delete mode 100644 board/ccv/xpress/spl.c
> delete mode 100644 board/ccv/xpress/xpress.c
> delete mode 100644 board/compulab/cl-som-imx7/Kconfig
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> delete mode 100644 board/compulab/cl-som-imx7/common.h
> delete mode 100644 board/compulab/cl-som-imx7/mux.c
> delete mode 100644 board/compulab/cl-som-imx7/spl.c
> delete mode 100644 board/compulab/cm_t335/Kconfig
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> delete mode 100644 board/compulab/cm_t335/Makefile
> delete mode 100644 board/compulab/cm_t335/cm_t335.c
> delete mode 100644 board/compulab/cm_t335/mux.c
> delete mode 100644 board/compulab/cm_t335/spl.c
> delete mode 100644 board/compulab/cm_t335/u-boot.lds
> delete mode 100644 board/compulab/cm_t43/Kconfig
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> delete mode 100644 board/compulab/cm_t43/mux.c
> delete mode 100644 board/compulab/cm_t43/spl.c
> delete mode 100644 board/d-link/dns325/Kconfig
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> delete mode 100644 board/d-link/dns325/kwbimage.cfg
> delete mode 100644 board/dhelectronics/dh_imx6/Kconfig
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> delete mode 100644 board/dhelectronics/dh_imx6/dh_imx6_spl.c
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> delete mode 100644 board/ebv/socrates/qts/pinmux_config.h
> delete mode 100644 board/ebv/socrates/qts/pll_config.h
> delete mode 100644 board/ebv/socrates/qts/sdram_config.h
> delete mode 100644 board/ebv/socrates/socfpga.c
> delete mode 100644 board/eets/pdu001/Kconfig
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> delete mode 100644 configs/clearfog_defconfig
> delete mode 100644 configs/cm_t335_defconfig
> delete mode 100644 configs/cm_t43_defconfig
> delete mode 100644 configs/colibri_imx6_defconfig
> delete mode 100644 configs/colibri_imx6_nospl_defconfig
> delete mode 100644 configs/colibri_pxa270_defconfig
> delete mode 100644 configs/db-mv784mp-gp_defconfig
> delete mode 100644 configs/devkit3250_defconfig
> delete mode 100644 configs/devkit8000_defconfig
> delete mode 100644 configs/dh_imx6_defconfig
> delete mode 100644 configs/dns325_defconfig
> delete mode 100644 configs/dra7xx_evm_defconfig
> delete mode 100644 configs/dra7xx_hs_evm_defconfig
> delete mode 100644 configs/dreamplug_defconfig
> delete mode 100644 configs/ds109_defconfig
> delete mode 100644 configs/gurnard_defconfig
> delete mode 100644 configs/guruplug_defconfig
> delete mode 100644 configs/gwventana_emmc_defconfig
> delete mode 100644 configs/gwventana_gw5904_defconfig
> delete mode 100644 configs/gwventana_nand_defconfig
> delete mode 100644 configs/helios4_defconfig
> delete mode 100644 configs/igep0032_defconfig
> delete mode 100644 configs/igep00x0_defconfig
> delete mode 100644 configs/imgtec_xilfpga_defconfig
> delete mode 100644 configs/imx6dl_mamoj_defconfig
> delete mode 100644 configs/imx6q_logic_defconfig
> delete mode 100644 configs/kp_imx6q_tpc_defconfig
> delete mode 100644 configs/liteboard_defconfig
> delete mode 100644 configs/ls1021aiot_qspi_defconfig
> delete mode 100644 configs/ls1021aiot_sdcard_defconfig
> delete mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1021atwr_nor_defconfig
> delete mode 100644 configs/ls1021atwr_nor_lpuart_defconfig
> delete mode 100644 configs/ls1021atwr_qspi_defconfig
> delete mode 100644 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1021atwr_sdcard_ifc_defconfig
> delete mode 100644 configs/ls1021atwr_sdcard_qspi_defconfig
> delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1043ardb_defconfig
> delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1043ardb_nand_defconfig
> delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1043ardb_sdcard_defconfig
> delete mode 100644 configs/ls1046ardb_emmc_defconfig
> delete mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1046ardb_qspi_defconfig
> delete mode 100644 configs/ls1046ardb_qspi_spl_defconfig
> delete mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
> delete mode 100644 configs/ls1046ardb_sdcard_defconfig
> delete mode 100644 configs/lschlv2_defconfig
> delete mode 100644 configs/lsxhl_defconfig
> delete mode 100644 configs/marsboard_defconfig
> delete mode 100644 configs/mccmon6_nor_defconfig
> delete mode 100644 configs/mccmon6_sd_defconfig
> delete mode 100644 configs/mx6cuboxi_defconfig
> delete mode 100644 configs/mx6sabreauto_defconfig
> delete mode 100644 configs/mx6sabresd_defconfig
> delete mode 100644 configs/nas220_defconfig
> delete mode 100644 configs/omap35_logic_defconfig
> delete mode 100644 configs/omap35_logic_somlv_defconfig
> delete mode 100644 configs/omap3_beagle_defconfig
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> delete mode 100644 configs/omap3_logic_somlv_defconfig
> delete mode 100644 configs/omap3_overo_defconfig
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> delete mode 100644 configs/omap3_zoom1_defconfig
> delete mode 100644 configs/ot1200_defconfig
> delete mode 100644 configs/ot1200_spl_defconfig
> delete mode 100644 configs/pcm051_rev1_defconfig
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> delete mode 100644 configs/pcm058_defconfig
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> delete mode 100644 configs/pfla02_defconfig
> delete mode 100644 configs/pico-hobbit-imx7d_defconfig
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> delete mode 100644 configs/pico-pi-imx7d_defconfig
> delete mode 100644 configs/riotboard_defconfig
> delete mode 100644 configs/s32v234evb_defconfig
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> delete mode 100644 configs/sksimx6_defconfig
> delete mode 100644 configs/snapper9260_defconfig
> delete mode 100644 configs/snapper9g20_defconfig
> delete mode 100644 configs/sniper_defconfig
> delete mode 100644 configs/socfpga_arria10_defconfig
> delete mode 100644 configs/socfpga_arria5_defconfig
> delete mode 100644 configs/socfpga_cyclone5_defconfig
> delete mode 100644 configs/socfpga_dbm_soc1_defconfig
> delete mode 100644 configs/socfpga_de0_nano_soc_defconfig
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> delete mode 100644 configs/socfpga_de1_soc_defconfig
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> delete mode 100644 configs/socfpga_vining_fpga_defconfig
> delete mode 100644 configs/tbs2910_defconfig
> delete mode 100644 configs/theadorable_debug_defconfig
> delete mode 100644 configs/udoo_defconfig
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> delete mode 100644 configs/warp7_bl33_defconfig
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> delete mode 100644 configs/work_92105_defconfig
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> delete mode 100644 configs/zc5202_defconfig
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> delete mode 100644 include/configs/am335x_evm.h
> delete mode 100644 include/configs/am335x_shc.h
> delete mode 100644 include/configs/am43xx_evm.h
> delete mode 100644 include/configs/am65x_evm.h
> delete mode 100644 include/configs/ap121.h
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> delete mode 100644 include/configs/apalis_imx6.h
> delete mode 100644 include/configs/baltos.h
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> delete mode 100644 include/configs/brppt1.h
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> delete mode 100644 include/configs/cl-som-imx7.h
> delete mode 100644 include/configs/clearfog.h
> delete mode 100644 include/configs/cm_t335.h
> delete mode 100644 include/configs/cm_t43.h
> delete mode 100644 include/configs/colibri_imx6.h
> delete mode 100644 include/configs/colibri_pxa270.h
> delete mode 100644 include/configs/db-mv784mp-gp.h
> delete mode 100644 include/configs/devkit3250.h
> delete mode 100644 include/configs/devkit8000.h
> delete mode 100644 include/configs/dh_imx6.h
> delete mode 100644 include/configs/dns325.h
> delete mode 100644 include/configs/dra7xx_evm.h
> delete mode 100644 include/configs/dreamplug.h
> delete mode 100644 include/configs/ds109.h
> delete mode 100644 include/configs/embestmx6boards.h
> delete mode 100644 include/configs/guruplug.h
> delete mode 100644 include/configs/gw_ventana.h
> delete mode 100644 include/configs/helios4.h
> delete mode 100644 include/configs/imx6_logic.h
> delete mode 100644 include/configs/imx6dl-mamoj.h
> delete mode 100644 include/configs/kp_imx6q_tpc.h
> delete mode 100644 include/configs/liteboard.h
> delete mode 100644 include/configs/ls1021aiot.h
> delete mode 100644 include/configs/ls1021atwr.h
> delete mode 100644 include/configs/ls1043ardb.h
> delete mode 100644 include/configs/ls1046ardb.h
> delete mode 100644 include/configs/lsxl.h
> delete mode 100644 include/configs/mccmon6.h
> delete mode 100644 include/configs/mx6cuboxi.h
> delete mode 100644 include/configs/mx6sabreauto.h
> delete mode 100644 include/configs/mx6sabresd.h
> delete mode 100644 include/configs/nas220.h
> delete mode 100644 include/configs/omap3_beagle.h
> delete mode 100644 include/configs/omap3_cairo.h
> delete mode 100644 include/configs/omap3_igep00x0.h
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> delete mode 100644 include/configs/omap3_pandora.h
> delete mode 100644 include/configs/omap3_zoom1.h
> delete mode 100644 include/configs/ot1200.h
> delete mode 100644 include/configs/pcm051.h
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> delete mode 100644 include/configs/pdu001.h
> delete mode 100644 include/configs/pengwyn.h
> delete mode 100644 include/configs/pfla02.h
> delete mode 100644 include/configs/pico-imx7d.h
> delete mode 100644 include/configs/s32v234evb.h
> delete mode 100644 include/configs/sheevaplug.h
> delete mode 100644 include/configs/sksimx6.h
> delete mode 100644 include/configs/snapper9260.h
> delete mode 100644 include/configs/snapper9g45.h
> delete mode 100644 include/configs/sniper.h
> delete mode 100644 include/configs/socfpga_arria10_socdk.h
> delete mode 100644 include/configs/socfpga_arria5_socdk.h
> delete mode 100644 include/configs/socfpga_cyclone5_socdk.h
> delete mode 100644 include/configs/socfpga_dbm_soc1.h
> delete mode 100644 include/configs/socfpga_de0_nano_soc.h
> delete mode 100644 include/configs/socfpga_de10_nano.h
> delete mode 100644 include/configs/socfpga_de1_soc.h
> delete mode 100644 include/configs/socfpga_is1.h
> delete mode 100644 include/configs/socfpga_sockit.h
> delete mode 100644 include/configs/socfpga_socrates.h
> delete mode 100644 include/configs/socfpga_sr1500.h
> delete mode 100644 include/configs/socfpga_stratix10_socdk.h
> delete mode 100644 include/configs/socfpga_vining_fpga.h
> delete mode 100644 include/configs/tbs2910.h
> delete mode 100644 include/configs/theadorable.h
> delete mode 100644 include/configs/udoo.h
> delete mode 100644 include/configs/udoo_neo.h
> delete mode 100644 include/configs/vinco.h
> delete mode 100644 include/configs/vining_2000.h
> delete mode 100644 include/configs/wandboard.h
> delete mode 100644 include/configs/warp7.h
> delete mode 100644 include/configs/work_92105.h
> delete mode 100644 include/configs/xpress.h
> delete mode 100644 include/configs/zc5202.h
> delete mode 100644 include/configs/zc5601.h
> create mode 100755 tools/rmboard.py
>
^ permalink raw reply [flat|nested] 211+ messages in thread* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 12:42 ` Soeren Moch
@ 2018-11-20 13:37 ` Tom Rini
2018-11-20 13:40 ` Marek Vasut
2018-11-23 0:31 ` Fabio Estevam
1 sibling, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-20 13:37 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
>
>
> On 19.11.18 16:52, Simon Glass wrote:
> > All boards should now be migrated to use CONFIG_BLK. This series removes
> > those with build problems using this option.
> >
> > If maintainers want to keep these boards in they should send a patch in
> > the next week or two. Otherwise the board will be removed in the next
> > release, and will need to be added and re-reviewed later.
> Fabio, Stefano,
>
> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> But would it not make more sense to convert the reference boards first
> (mx6sabresd
> in my case for tbs2910), and let hobbyist maintainers like me take this
> as example for
> their own modifications?
So, I replied to the main thread earlier but no, we're not going to drop
everything in 2 weeks, especially since there's a lot of false positives
in this series.
> Simon, Tom,
>
> is this really the usual u-boot working style to remove about hundred
> boards within
> two weeks without prior warning? As hobbyist board maintainer I try to
> follow
> new developments, and more than once I fixed up regressions introduced
> by others
> in general code.
> But I cannot follow all development details without any heads-up. And
> even the
> NXP folks seem to be surprised about this.
>
> All problems with this transition seem to be located around usbstorage
> and sata.
> This is for sure not really very board specific. Is there any migration
> guide, or
> examples how other SoC architectures did this conversion?
I'll admit this hasn't been our best notification. But, the deadline
was discussed about a year ago (and then no, I didn't get a build-time
warning in). Then around v2018.05 I said it wasn't going to be a
removal type problem yet as we had a lot of boards to fixup still, and
repeated that at v2018.07. That did lead to a lot of things getting
addressed. But yes, we still have some large areas that after a few
years still have not been converted, and that puts me in a hard spot
too.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 13:37 ` Tom Rini
@ 2018-11-20 13:40 ` Marek Vasut
2018-11-20 13:42 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Marek Vasut @ 2018-11-20 13:40 UTC (permalink / raw)
To: u-boot
On 11/20/2018 02:37 PM, Tom Rini wrote:
> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
>>
>>
>> On 19.11.18 16:52, Simon Glass wrote:
>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>> those with build problems using this option.
>>>
>>> If maintainers want to keep these boards in they should send a patch in
>>> the next week or two. Otherwise the board will be removed in the next
>>> release, and will need to be added and re-reviewed later.
>> Fabio, Stefano,
>>
>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
>> But would it not make more sense to convert the reference boards first
>> (mx6sabresd
>> in my case for tbs2910), and let hobbyist maintainers like me take this
>> as example for
>> their own modifications?
>
> So, I replied to the main thread earlier but no, we're not going to drop
> everything in 2 weeks, especially since there's a lot of false positives
> in this series.
>
>> Simon, Tom,
>>
>> is this really the usual u-boot working style to remove about hundred
>> boards within
>> two weeks without prior warning? As hobbyist board maintainer I try to
>> follow
>> new developments, and more than once I fixed up regressions introduced
>> by others
>> in general code.
>> But I cannot follow all development details without any heads-up. And
>> even the
>> NXP folks seem to be surprised about this.
>>
>> All problems with this transition seem to be located around usbstorage
>> and sata.
>> This is for sure not really very board specific. Is there any migration
>> guide, or
>> examples how other SoC architectures did this conversion?
>
> I'll admit this hasn't been our best notification. But, the deadline
> was discussed about a year ago (and then no, I didn't get a build-time
> warning in). Then around v2018.05 I said it wasn't going to be a
> removal type problem yet as we had a lot of boards to fixup still, and
> repeated that at v2018.07. That did lead to a lot of things getting
> addressed. But yes, we still have some large areas that after a few
> years still have not been converted, and that puts me in a hard spot
> too.
Build time warning for a year would be good ?
Maybe we need some generic Makefile macro to set those up.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 13:40 ` Marek Vasut
@ 2018-11-20 13:42 ` Tom Rini
2018-11-20 13:45 ` Marek Vasut
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-20 13:42 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> >>
> >>
> >> On 19.11.18 16:52, Simon Glass wrote:
> >>> All boards should now be migrated to use CONFIG_BLK. This series removes
> >>> those with build problems using this option.
> >>>
> >>> If maintainers want to keep these boards in they should send a patch in
> >>> the next week or two. Otherwise the board will be removed in the next
> >>> release, and will need to be added and re-reviewed later.
> >> Fabio, Stefano,
> >>
> >> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> >> But would it not make more sense to convert the reference boards first
> >> (mx6sabresd
> >> in my case for tbs2910), and let hobbyist maintainers like me take this
> >> as example for
> >> their own modifications?
> >
> > So, I replied to the main thread earlier but no, we're not going to drop
> > everything in 2 weeks, especially since there's a lot of false positives
> > in this series.
> >
> >> Simon, Tom,
> >>
> >> is this really the usual u-boot working style to remove about hundred
> >> boards within
> >> two weeks without prior warning? As hobbyist board maintainer I try to
> >> follow
> >> new developments, and more than once I fixed up regressions introduced
> >> by others
> >> in general code.
> >> But I cannot follow all development details without any heads-up. And
> >> even the
> >> NXP folks seem to be surprised about this.
> >>
> >> All problems with this transition seem to be located around usbstorage
> >> and sata.
> >> This is for sure not really very board specific. Is there any migration
> >> guide, or
> >> examples how other SoC architectures did this conversion?
> >
> > I'll admit this hasn't been our best notification. But, the deadline
> > was discussed about a year ago (and then no, I didn't get a build-time
> > warning in). Then around v2018.05 I said it wasn't going to be a
> > removal type problem yet as we had a lot of boards to fixup still, and
> > repeated that at v2018.07. That did lead to a lot of things getting
> > addressed. But yes, we still have some large areas that after a few
> > years still have not been converted, and that puts me in a hard spot
> > too.
>
> Build time warning for a year would be good ?
A year for this? No. New deadlines? That's not too far off from what
we've done historically, so yes.
> Maybe we need some generic Makefile macro to set those up.
It would be nice, yes. I think the problem here is (or, was) the
complex set of options that didn't work.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 13:42 ` Tom Rini
@ 2018-11-20 13:45 ` Marek Vasut
2018-11-20 13:53 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Marek Vasut @ 2018-11-20 13:45 UTC (permalink / raw)
To: u-boot
On 11/20/2018 02:42 PM, Tom Rini wrote:
> On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
>> On 11/20/2018 02:37 PM, Tom Rini wrote:
>>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
>>>>
>>>>
>>>> On 19.11.18 16:52, Simon Glass wrote:
>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>>>> those with build problems using this option.
>>>>>
>>>>> If maintainers want to keep these boards in they should send a patch in
>>>>> the next week or two. Otherwise the board will be removed in the next
>>>>> release, and will need to be added and re-reviewed later.
>>>> Fabio, Stefano,
>>>>
>>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
>>>> But would it not make more sense to convert the reference boards first
>>>> (mx6sabresd
>>>> in my case for tbs2910), and let hobbyist maintainers like me take this
>>>> as example for
>>>> their own modifications?
>>>
>>> So, I replied to the main thread earlier but no, we're not going to drop
>>> everything in 2 weeks, especially since there's a lot of false positives
>>> in this series.
>>>
>>>> Simon, Tom,
>>>>
>>>> is this really the usual u-boot working style to remove about hundred
>>>> boards within
>>>> two weeks without prior warning? As hobbyist board maintainer I try to
>>>> follow
>>>> new developments, and more than once I fixed up regressions introduced
>>>> by others
>>>> in general code.
>>>> But I cannot follow all development details without any heads-up. And
>>>> even the
>>>> NXP folks seem to be surprised about this.
>>>>
>>>> All problems with this transition seem to be located around usbstorage
>>>> and sata.
>>>> This is for sure not really very board specific. Is there any migration
>>>> guide, or
>>>> examples how other SoC architectures did this conversion?
>>>
>>> I'll admit this hasn't been our best notification. But, the deadline
>>> was discussed about a year ago (and then no, I didn't get a build-time
>>> warning in). Then around v2018.05 I said it wasn't going to be a
>>> removal type problem yet as we had a lot of boards to fixup still, and
>>> repeated that at v2018.07. That did lead to a lot of things getting
>>> addressed. But yes, we still have some large areas that after a few
>>> years still have not been converted, and that puts me in a hard spot
>>> too.
>>
>> Build time warning for a year would be good ?
>
> A year for this? No. New deadlines? That's not too far off from what
> we've done historically, so yes.
Give people some sort of breathing space to get the conversion done.
Stressing people out by arbitrary deadlines will lead nowhere.
>> Maybe we need some generic Makefile macro to set those up.
>
> It would be nice, yes. I think the problem here is (or, was) the
> complex set of options that didn't work.
The problem was many people didn't know about the conversion deadline or
simply forgot. And reminding them with a 100-patch series removing half
of the boards is like splashing icy water bucket in their sleeping faces.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 13:45 ` Marek Vasut
@ 2018-11-20 13:53 ` Tom Rini
2018-11-20 13:55 ` Marek Vasut
2018-11-21 15:10 ` Tom Rini
0 siblings, 2 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-20 13:53 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> On 11/20/2018 02:42 PM, Tom Rini wrote:
> > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> >>>>
> >>>>
> >>>> On 19.11.18 16:52, Simon Glass wrote:
> >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> >>>>> those with build problems using this option.
> >>>>>
> >>>>> If maintainers want to keep these boards in they should send a patch in
> >>>>> the next week or two. Otherwise the board will be removed in the next
> >>>>> release, and will need to be added and re-reviewed later.
> >>>> Fabio, Stefano,
> >>>>
> >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> >>>> But would it not make more sense to convert the reference boards first
> >>>> (mx6sabresd
> >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> >>>> as example for
> >>>> their own modifications?
> >>>
> >>> So, I replied to the main thread earlier but no, we're not going to drop
> >>> everything in 2 weeks, especially since there's a lot of false positives
> >>> in this series.
> >>>
> >>>> Simon, Tom,
> >>>>
> >>>> is this really the usual u-boot working style to remove about hundred
> >>>> boards within
> >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> >>>> follow
> >>>> new developments, and more than once I fixed up regressions introduced
> >>>> by others
> >>>> in general code.
> >>>> But I cannot follow all development details without any heads-up. And
> >>>> even the
> >>>> NXP folks seem to be surprised about this.
> >>>>
> >>>> All problems with this transition seem to be located around usbstorage
> >>>> and sata.
> >>>> This is for sure not really very board specific. Is there any migration
> >>>> guide, or
> >>>> examples how other SoC architectures did this conversion?
> >>>
> >>> I'll admit this hasn't been our best notification. But, the deadline
> >>> was discussed about a year ago (and then no, I didn't get a build-time
> >>> warning in). Then around v2018.05 I said it wasn't going to be a
> >>> removal type problem yet as we had a lot of boards to fixup still, and
> >>> repeated that at v2018.07. That did lead to a lot of things getting
> >>> addressed. But yes, we still have some large areas that after a few
> >>> years still have not been converted, and that puts me in a hard spot
> >>> too.
> >>
> >> Build time warning for a year would be good ?
> >
> > A year for this? No. New deadlines? That's not too far off from what
> > we've done historically, so yes.
>
> Give people some sort of breathing space to get the conversion done.
> Stressing people out by arbitrary deadlines will lead nowhere.
Sure, agreed. I didn't say we're going to drop all these boards, nor
are we going to drop SATA and USB Storage (if those are still all that's
left to convert) for this release. But given that we proposed a
deadline in August 2017, made email-but-not-build noise about it between
May and July/August of this year, no, I also don't think setting a new
deadline of November 2019 is the right call either.
So, really, lets see what the fails to build boards are with BLK being
on when we have block devices. Then assess what a good deadline is.
> >> Maybe we need some generic Makefile macro to set those up.
> >
> > It would be nice, yes. I think the problem here is (or, was) the
> > complex set of options that didn't work.
>
> The problem was many people didn't know about the conversion deadline or
> simply forgot. And reminding them with a 100-patch series removing half
> of the boards is like splashing icy water bucket in their sleeping faces.
Alright. But we've already tried less shocking approaches to
conversion, but in public (over the summer when Simon listed most of
these boards in a series but I _think_ his script failed to CC the
universe and didn't follow up with a repost that did email everyone) and
perhaps private too (I honestly don't recall if I did, or just intended
to, ask you about the USB side of this on IRC).
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 13:53 ` Tom Rini
@ 2018-11-20 13:55 ` Marek Vasut
2018-11-21 15:10 ` Tom Rini
1 sibling, 0 replies; 211+ messages in thread
From: Marek Vasut @ 2018-11-20 13:55 UTC (permalink / raw)
To: u-boot
On 11/20/2018 02:53 PM, Tom Rini wrote:
> On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
>> On 11/20/2018 02:42 PM, Tom Rini wrote:
>>> On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
>>>> On 11/20/2018 02:37 PM, Tom Rini wrote:
>>>>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
>>>>>>
>>>>>>
>>>>>> On 19.11.18 16:52, Simon Glass wrote:
>>>>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
>>>>>>> those with build problems using this option.
>>>>>>>
>>>>>>> If maintainers want to keep these boards in they should send a patch in
>>>>>>> the next week or two. Otherwise the board will be removed in the next
>>>>>>> release, and will need to be added and re-reviewed later.
>>>>>> Fabio, Stefano,
>>>>>>
>>>>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
>>>>>> But would it not make more sense to convert the reference boards first
>>>>>> (mx6sabresd
>>>>>> in my case for tbs2910), and let hobbyist maintainers like me take this
>>>>>> as example for
>>>>>> their own modifications?
>>>>>
>>>>> So, I replied to the main thread earlier but no, we're not going to drop
>>>>> everything in 2 weeks, especially since there's a lot of false positives
>>>>> in this series.
>>>>>
>>>>>> Simon, Tom,
>>>>>>
>>>>>> is this really the usual u-boot working style to remove about hundred
>>>>>> boards within
>>>>>> two weeks without prior warning? As hobbyist board maintainer I try to
>>>>>> follow
>>>>>> new developments, and more than once I fixed up regressions introduced
>>>>>> by others
>>>>>> in general code.
>>>>>> But I cannot follow all development details without any heads-up. And
>>>>>> even the
>>>>>> NXP folks seem to be surprised about this.
>>>>>>
>>>>>> All problems with this transition seem to be located around usbstorage
>>>>>> and sata.
>>>>>> This is for sure not really very board specific. Is there any migration
>>>>>> guide, or
>>>>>> examples how other SoC architectures did this conversion?
>>>>>
>>>>> I'll admit this hasn't been our best notification. But, the deadline
>>>>> was discussed about a year ago (and then no, I didn't get a build-time
>>>>> warning in). Then around v2018.05 I said it wasn't going to be a
>>>>> removal type problem yet as we had a lot of boards to fixup still, and
>>>>> repeated that at v2018.07. That did lead to a lot of things getting
>>>>> addressed. But yes, we still have some large areas that after a few
>>>>> years still have not been converted, and that puts me in a hard spot
>>>>> too.
>>>>
>>>> Build time warning for a year would be good ?
>>>
>>> A year for this? No. New deadlines? That's not too far off from what
>>> we've done historically, so yes.
>>
>> Give people some sort of breathing space to get the conversion done.
>> Stressing people out by arbitrary deadlines will lead nowhere.
>
> Sure, agreed. I didn't say we're going to drop all these boards, nor
> are we going to drop SATA and USB Storage (if those are still all that's
> left to convert) for this release. But given that we proposed a
> deadline in August 2017, made email-but-not-build noise about it between
> May and July/August of this year, no, I also don't think setting a new
> deadline of November 2019 is the right call either.
>
> So, really, lets see what the fails to build boards are with BLK being
> on when we have block devices. Then assess what a good deadline is.
Sounds good.
>>>> Maybe we need some generic Makefile macro to set those up.
>>>
>>> It would be nice, yes. I think the problem here is (or, was) the
>>> complex set of options that didn't work.
>>
>> The problem was many people didn't know about the conversion deadline or
>> simply forgot. And reminding them with a 100-patch series removing half
>> of the boards is like splashing icy water bucket in their sleeping faces.
>
> Alright. But we've already tried less shocking approaches to
> conversion, but in public (over the summer when Simon listed most of
> these boards in a series but I _think_ his script failed to CC the
> universe and didn't follow up with a repost that did email everyone) and
> perhaps private too (I honestly don't recall if I did, or just intended
> to, ask you about the USB side of this on IRC).
I think the Makefile noise would be good. It'd be annoying enough and
persistently remind people to fix their stuff.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 13:53 ` Tom Rini
2018-11-20 13:55 ` Marek Vasut
@ 2018-11-21 15:10 ` Tom Rini
2018-11-22 20:50 ` Simon Glass
1 sibling, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-21 15:10 UTC (permalink / raw)
To: u-boot
On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > >>>>
> > >>>>
> > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > >>>>> those with build problems using this option.
> > >>>>>
> > >>>>> If maintainers want to keep these boards in they should send a patch in
> > >>>>> the next week or two. Otherwise the board will be removed in the next
> > >>>>> release, and will need to be added and re-reviewed later.
> > >>>> Fabio, Stefano,
> > >>>>
> > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > >>>> But would it not make more sense to convert the reference boards first
> > >>>> (mx6sabresd
> > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > >>>> as example for
> > >>>> their own modifications?
> > >>>
> > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > >>> everything in 2 weeks, especially since there's a lot of false positives
> > >>> in this series.
> > >>>
> > >>>> Simon, Tom,
> > >>>>
> > >>>> is this really the usual u-boot working style to remove about hundred
> > >>>> boards within
> > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > >>>> follow
> > >>>> new developments, and more than once I fixed up regressions introduced
> > >>>> by others
> > >>>> in general code.
> > >>>> But I cannot follow all development details without any heads-up. And
> > >>>> even the
> > >>>> NXP folks seem to be surprised about this.
> > >>>>
> > >>>> All problems with this transition seem to be located around usbstorage
> > >>>> and sata.
> > >>>> This is for sure not really very board specific. Is there any migration
> > >>>> guide, or
> > >>>> examples how other SoC architectures did this conversion?
> > >>>
> > >>> I'll admit this hasn't been our best notification. But, the deadline
> > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > >>> addressed. But yes, we still have some large areas that after a few
> > >>> years still have not been converted, and that puts me in a hard spot
> > >>> too.
> > >>
> > >> Build time warning for a year would be good ?
> > >
> > > A year for this? No. New deadlines? That's not too far off from what
> > > we've done historically, so yes.
> >
> > Give people some sort of breathing space to get the conversion done.
> > Stressing people out by arbitrary deadlines will lead nowhere.
>
> Sure, agreed. I didn't say we're going to drop all these boards, nor
> are we going to drop SATA and USB Storage (if those are still all that's
> left to convert) for this release. But given that we proposed a
> deadline in August 2017, made email-but-not-build noise about it between
> May and July/August of this year, no, I also don't think setting a new
> deadline of November 2019 is the right call either.
>
> So, really, lets see what the fails to build boards are with BLK being
> on when we have block devices. Then assess what a good deadline is.
>
> > >> Maybe we need some generic Makefile macro to set those up.
> > >
> > > It would be nice, yes. I think the problem here is (or, was) the
> > > complex set of options that didn't work.
> >
> > The problem was many people didn't know about the conversion deadline or
> > simply forgot. And reminding them with a 100-patch series removing half
> > of the boards is like splashing icy water bucket in their sleeping faces.
>
> Alright. But we've already tried less shocking approaches to
> conversion, but in public (over the summer when Simon listed most of
> these boards in a series but I _think_ his script failed to CC the
> universe and didn't follow up with a repost that did email everyone) and
> perhaps private too (I honestly don't recall if I did, or just intended
> to, ask you about the USB side of this on IRC).
And, for the record, the USB side I had in mind here was converted, and
I just forgot, my fault. In fact, as I go through some hack-and-slash
to see what needs a real conversion (either board updated, or drivers
updated) at least some part of this is needing to adjust dependencies to
force things on with BLK. For example, if we have MMC we must have
DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-21 15:10 ` Tom Rini
@ 2018-11-22 20:50 ` Simon Glass
2018-11-22 23:31 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-22 20:50 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
>
> On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > >>>>
> > > >>>>
> > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > >>>>> those with build problems using this option.
> > > >>>>>
> > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > >>>>> release, and will need to be added and re-reviewed later.
> > > >>>> Fabio, Stefano,
> > > >>>>
> > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > >>>> But would it not make more sense to convert the reference boards first
> > > >>>> (mx6sabresd
> > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > >>>> as example for
> > > >>>> their own modifications?
> > > >>>
> > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > >>> in this series.
> > > >>>
> > > >>>> Simon, Tom,
> > > >>>>
> > > >>>> is this really the usual u-boot working style to remove about hundred
> > > >>>> boards within
> > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > >>>> follow
> > > >>>> new developments, and more than once I fixed up regressions introduced
> > > >>>> by others
> > > >>>> in general code.
> > > >>>> But I cannot follow all development details without any heads-up. And
> > > >>>> even the
> > > >>>> NXP folks seem to be surprised about this.
> > > >>>>
> > > >>>> All problems with this transition seem to be located around usbstorage
> > > >>>> and sata.
> > > >>>> This is for sure not really very board specific. Is there any migration
> > > >>>> guide, or
> > > >>>> examples how other SoC architectures did this conversion?
> > > >>>
> > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > >>> addressed. But yes, we still have some large areas that after a few
> > > >>> years still have not been converted, and that puts me in a hard spot
> > > >>> too.
> > > >>
> > > >> Build time warning for a year would be good ?
> > > >
> > > > A year for this? No. New deadlines? That's not too far off from what
> > > > we've done historically, so yes.
> > >
> > > Give people some sort of breathing space to get the conversion done.
> > > Stressing people out by arbitrary deadlines will lead nowhere.
> >
> > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > are we going to drop SATA and USB Storage (if those are still all that's
> > left to convert) for this release. But given that we proposed a
> > deadline in August 2017, made email-but-not-build noise about it between
> > May and July/August of this year, no, I also don't think setting a new
> > deadline of November 2019 is the right call either.
> >
> > So, really, lets see what the fails to build boards are with BLK being
> > on when we have block devices. Then assess what a good deadline is.
> >
> > > >> Maybe we need some generic Makefile macro to set those up.
> > > >
> > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > complex set of options that didn't work.
> > >
> > > The problem was many people didn't know about the conversion deadline or
> > > simply forgot. And reminding them with a 100-patch series removing half
> > > of the boards is like splashing icy water bucket in their sleeping faces.
> >
> > Alright. But we've already tried less shocking approaches to
> > conversion, but in public (over the summer when Simon listed most of
> > these boards in a series but I _think_ his script failed to CC the
> > universe and didn't follow up with a repost that did email everyone) and
> > perhaps private too (I honestly don't recall if I did, or just intended
> > to, ask you about the USB side of this on IRC).
>
> And, for the record, the USB side I had in mind here was converted, and
> I just forgot, my fault. In fact, as I go through some hack-and-slash
> to see what needs a real conversion (either board updated, or drivers
> updated) at least some part of this is needing to adjust dependencies to
> force things on with BLK. For example, if we have MMC we must have
> DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
Well, once we are through the migration we can remove BLK.
Yes all the block devices are related, and we should use DM for all of
them to make this work.
I am not sure if there is a better way to do this with Kconfig.
Thanks for helping with all of this. I have found it quite tricky to
plot a path forward which is why I am been putting it off for several
months.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-22 20:50 ` Simon Glass
@ 2018-11-22 23:31 ` Tom Rini
2018-11-23 12:04 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-22 23:31 UTC (permalink / raw)
To: u-boot
On Thu, Nov 22, 2018 at 01:50:34PM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > > >>>>
> > > > >>>>
> > > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > >>>>> those with build problems using this option.
> > > > >>>>>
> > > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > > >>>>> release, and will need to be added and re-reviewed later.
> > > > >>>> Fabio, Stefano,
> > > > >>>>
> > > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > > >>>> But would it not make more sense to convert the reference boards first
> > > > >>>> (mx6sabresd
> > > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > > >>>> as example for
> > > > >>>> their own modifications?
> > > > >>>
> > > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > > >>> in this series.
> > > > >>>
> > > > >>>> Simon, Tom,
> > > > >>>>
> > > > >>>> is this really the usual u-boot working style to remove about hundred
> > > > >>>> boards within
> > > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > > >>>> follow
> > > > >>>> new developments, and more than once I fixed up regressions introduced
> > > > >>>> by others
> > > > >>>> in general code.
> > > > >>>> But I cannot follow all development details without any heads-up. And
> > > > >>>> even the
> > > > >>>> NXP folks seem to be surprised about this.
> > > > >>>>
> > > > >>>> All problems with this transition seem to be located around usbstorage
> > > > >>>> and sata.
> > > > >>>> This is for sure not really very board specific. Is there any migration
> > > > >>>> guide, or
> > > > >>>> examples how other SoC architectures did this conversion?
> > > > >>>
> > > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > > >>> addressed. But yes, we still have some large areas that after a few
> > > > >>> years still have not been converted, and that puts me in a hard spot
> > > > >>> too.
> > > > >>
> > > > >> Build time warning for a year would be good ?
> > > > >
> > > > > A year for this? No. New deadlines? That's not too far off from what
> > > > > we've done historically, so yes.
> > > >
> > > > Give people some sort of breathing space to get the conversion done.
> > > > Stressing people out by arbitrary deadlines will lead nowhere.
> > >
> > > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > > are we going to drop SATA and USB Storage (if those are still all that's
> > > left to convert) for this release. But given that we proposed a
> > > deadline in August 2017, made email-but-not-build noise about it between
> > > May and July/August of this year, no, I also don't think setting a new
> > > deadline of November 2019 is the right call either.
> > >
> > > So, really, lets see what the fails to build boards are with BLK being
> > > on when we have block devices. Then assess what a good deadline is.
> > >
> > > > >> Maybe we need some generic Makefile macro to set those up.
> > > > >
> > > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > > complex set of options that didn't work.
> > > >
> > > > The problem was many people didn't know about the conversion deadline or
> > > > simply forgot. And reminding them with a 100-patch series removing half
> > > > of the boards is like splashing icy water bucket in their sleeping faces.
> > >
> > > Alright. But we've already tried less shocking approaches to
> > > conversion, but in public (over the summer when Simon listed most of
> > > these boards in a series but I _think_ his script failed to CC the
> > > universe and didn't follow up with a repost that did email everyone) and
> > > perhaps private too (I honestly don't recall if I did, or just intended
> > > to, ask you about the USB side of this on IRC).
> >
> > And, for the record, the USB side I had in mind here was converted, and
> > I just forgot, my fault. In fact, as I go through some hack-and-slash
> > to see what needs a real conversion (either board updated, or drivers
> > updated) at least some part of this is needing to adjust dependencies to
> > force things on with BLK. For example, if we have MMC we must have
> > DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
>
> Well, once we are through the migration we can remove BLK.
I don't think BLK the symbol goes away, really. We don't want more
objects built unconditionally and we will continue to have block
device-less builds.
> Yes all the block devices are related, and we should use DM for all of
> them to make this work.
>
> I am not sure if there is a better way to do this with Kconfig.
>
> Thanks for helping with all of this. I have found it quite tricky to
> plot a path forward which is why I am been putting it off for several
> months.
Thanks for starting it off. I think part of the big problem we'll have
here is that unfortunately we can't key off of the BLK migration itself
as it's short-hand for having started using OF_CONTROL. What I'm
currently working through is being able to have all block drivers using
BLK and everything is still building / linking as unconverted drivers
now depend on BROKEN. This is showing we have a few widely used but
unconverted drivers over in Freescale/NXP land.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-22 23:31 ` Tom Rini
@ 2018-11-23 12:04 ` Simon Glass
2018-11-23 19:38 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-23 12:04 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Thu, 22 Nov 2018 at 16:31, Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, Nov 22, 2018 at 01:50:34PM -0700, Simon Glass wrote:
> > Hi Tom,
> >
> > On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > > > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > > > >>>>
> > > > > >>>>
> > > > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > > >>>>> those with build problems using this option.
> > > > > >>>>>
> > > > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > > > >>>>> release, and will need to be added and re-reviewed later.
> > > > > >>>> Fabio, Stefano,
> > > > > >>>>
> > > > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > > > >>>> But would it not make more sense to convert the reference boards first
> > > > > >>>> (mx6sabresd
> > > > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > > > >>>> as example for
> > > > > >>>> their own modifications?
> > > > > >>>
> > > > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > > > >>> in this series.
> > > > > >>>
> > > > > >>>> Simon, Tom,
> > > > > >>>>
> > > > > >>>> is this really the usual u-boot working style to remove about hundred
> > > > > >>>> boards within
> > > > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > > > >>>> follow
> > > > > >>>> new developments, and more than once I fixed up regressions introduced
> > > > > >>>> by others
> > > > > >>>> in general code.
> > > > > >>>> But I cannot follow all development details without any heads-up. And
> > > > > >>>> even the
> > > > > >>>> NXP folks seem to be surprised about this.
> > > > > >>>>
> > > > > >>>> All problems with this transition seem to be located around usbstorage
> > > > > >>>> and sata.
> > > > > >>>> This is for sure not really very board specific. Is there any migration
> > > > > >>>> guide, or
> > > > > >>>> examples how other SoC architectures did this conversion?
> > > > > >>>
> > > > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > > > >>> addressed. But yes, we still have some large areas that after a few
> > > > > >>> years still have not been converted, and that puts me in a hard spot
> > > > > >>> too.
> > > > > >>
> > > > > >> Build time warning for a year would be good ?
> > > > > >
> > > > > > A year for this? No. New deadlines? That's not too far off from what
> > > > > > we've done historically, so yes.
> > > > >
> > > > > Give people some sort of breathing space to get the conversion done.
> > > > > Stressing people out by arbitrary deadlines will lead nowhere.
> > > >
> > > > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > > > are we going to drop SATA and USB Storage (if those are still all that's
> > > > left to convert) for this release. But given that we proposed a
> > > > deadline in August 2017, made email-but-not-build noise about it between
> > > > May and July/August of this year, no, I also don't think setting a new
> > > > deadline of November 2019 is the right call either.
> > > >
> > > > So, really, lets see what the fails to build boards are with BLK being
> > > > on when we have block devices. Then assess what a good deadline is.
> > > >
> > > > > >> Maybe we need some generic Makefile macro to set those up.
> > > > > >
> > > > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > > > complex set of options that didn't work.
> > > > >
> > > > > The problem was many people didn't know about the conversion deadline or
> > > > > simply forgot. And reminding them with a 100-patch series removing half
> > > > > of the boards is like splashing icy water bucket in their sleeping faces.
> > > >
> > > > Alright. But we've already tried less shocking approaches to
> > > > conversion, but in public (over the summer when Simon listed most of
> > > > these boards in a series but I _think_ his script failed to CC the
> > > > universe and didn't follow up with a repost that did email everyone) and
> > > > perhaps private too (I honestly don't recall if I did, or just intended
> > > > to, ask you about the USB side of this on IRC).
> > >
> > > And, for the record, the USB side I had in mind here was converted, and
> > > I just forgot, my fault. In fact, as I go through some hack-and-slash
> > > to see what needs a real conversion (either board updated, or drivers
> > > updated) at least some part of this is needing to adjust dependencies to
> > > force things on with BLK. For example, if we have MMC we must have
> > > DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
> >
> > Well, once we are through the migration we can remove BLK.
>
> I don't think BLK the symbol goes away, really. We don't want more
> objects built unconditionally and we will continue to have block
> device-less builds.
Yes that's right - but it becomes an optional feature rather than an
indication of completed migration.
>
> > Yes all the block devices are related, and we should use DM for all of
> > them to make this work.
> >
> > I am not sure if there is a better way to do this with Kconfig.
> >
> > Thanks for helping with all of this. I have found it quite tricky to
> > plot a path forward which is why I am been putting it off for several
> > months.
>
> Thanks for starting it off. I think part of the big problem we'll have
> here is that unfortunately we can't key off of the BLK migration itself
> as it's short-hand for having started using OF_CONTROL. What I'm
> currently working through is being able to have all block drivers using
> BLK and everything is still building / linking as unconverted drivers
> now depend on BROKEN. This is showing we have a few widely used but
> unconverted drivers over in Freescale/NXP land.
That's a good idea. Does it work OK with DM_MMC and DM_USB? Is this a
way we can keep unconverted boards around for a while without holding
up migration? They won't work properly but will build?
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-23 12:04 ` Simon Glass
@ 2018-11-23 19:38 ` Tom Rini
2018-11-24 19:41 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-23 19:38 UTC (permalink / raw)
To: u-boot
On Fri, Nov 23, 2018 at 05:04:46AM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Thu, 22 Nov 2018 at 16:31, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, Nov 22, 2018 at 01:50:34PM -0700, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > > > > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > > > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > > > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > > > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > > > > >>>>
> > > > > > >>>>
> > > > > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > > > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > > > >>>>> those with build problems using this option.
> > > > > > >>>>>
> > > > > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > > > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > > > > >>>>> release, and will need to be added and re-reviewed later.
> > > > > > >>>> Fabio, Stefano,
> > > > > > >>>>
> > > > > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > > > > >>>> But would it not make more sense to convert the reference boards first
> > > > > > >>>> (mx6sabresd
> > > > > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > > > > >>>> as example for
> > > > > > >>>> their own modifications?
> > > > > > >>>
> > > > > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > > > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > > > > >>> in this series.
> > > > > > >>>
> > > > > > >>>> Simon, Tom,
> > > > > > >>>>
> > > > > > >>>> is this really the usual u-boot working style to remove about hundred
> > > > > > >>>> boards within
> > > > > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > > > > >>>> follow
> > > > > > >>>> new developments, and more than once I fixed up regressions introduced
> > > > > > >>>> by others
> > > > > > >>>> in general code.
> > > > > > >>>> But I cannot follow all development details without any heads-up. And
> > > > > > >>>> even the
> > > > > > >>>> NXP folks seem to be surprised about this.
> > > > > > >>>>
> > > > > > >>>> All problems with this transition seem to be located around usbstorage
> > > > > > >>>> and sata.
> > > > > > >>>> This is for sure not really very board specific. Is there any migration
> > > > > > >>>> guide, or
> > > > > > >>>> examples how other SoC architectures did this conversion?
> > > > > > >>>
> > > > > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > > > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > > > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > > > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > > > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > > > > >>> addressed. But yes, we still have some large areas that after a few
> > > > > > >>> years still have not been converted, and that puts me in a hard spot
> > > > > > >>> too.
> > > > > > >>
> > > > > > >> Build time warning for a year would be good ?
> > > > > > >
> > > > > > > A year for this? No. New deadlines? That's not too far off from what
> > > > > > > we've done historically, so yes.
> > > > > >
> > > > > > Give people some sort of breathing space to get the conversion done.
> > > > > > Stressing people out by arbitrary deadlines will lead nowhere.
> > > > >
> > > > > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > > > > are we going to drop SATA and USB Storage (if those are still all that's
> > > > > left to convert) for this release. But given that we proposed a
> > > > > deadline in August 2017, made email-but-not-build noise about it between
> > > > > May and July/August of this year, no, I also don't think setting a new
> > > > > deadline of November 2019 is the right call either.
> > > > >
> > > > > So, really, lets see what the fails to build boards are with BLK being
> > > > > on when we have block devices. Then assess what a good deadline is.
> > > > >
> > > > > > >> Maybe we need some generic Makefile macro to set those up.
> > > > > > >
> > > > > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > > > > complex set of options that didn't work.
> > > > > >
> > > > > > The problem was many people didn't know about the conversion deadline or
> > > > > > simply forgot. And reminding them with a 100-patch series removing half
> > > > > > of the boards is like splashing icy water bucket in their sleeping faces.
> > > > >
> > > > > Alright. But we've already tried less shocking approaches to
> > > > > conversion, but in public (over the summer when Simon listed most of
> > > > > these boards in a series but I _think_ his script failed to CC the
> > > > > universe and didn't follow up with a repost that did email everyone) and
> > > > > perhaps private too (I honestly don't recall if I did, or just intended
> > > > > to, ask you about the USB side of this on IRC).
> > > >
> > > > And, for the record, the USB side I had in mind here was converted, and
> > > > I just forgot, my fault. In fact, as I go through some hack-and-slash
> > > > to see what needs a real conversion (either board updated, or drivers
> > > > updated) at least some part of this is needing to adjust dependencies to
> > > > force things on with BLK. For example, if we have MMC we must have
> > > > DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
> > >
> > > Well, once we are through the migration we can remove BLK.
> >
> > I don't think BLK the symbol goes away, really. We don't want more
> > objects built unconditionally and we will continue to have block
> > device-less builds.
>
> Yes that's right - but it becomes an optional feature rather than an
> indication of completed migration.
>
> >
> > > Yes all the block devices are related, and we should use DM for all of
> > > them to make this work.
> > >
> > > I am not sure if there is a better way to do this with Kconfig.
> > >
> > > Thanks for helping with all of this. I have found it quite tricky to
> > > plot a path forward which is why I am been putting it off for several
> > > months.
> >
> > Thanks for starting it off. I think part of the big problem we'll have
> > here is that unfortunately we can't key off of the BLK migration itself
> > as it's short-hand for having started using OF_CONTROL. What I'm
> > currently working through is being able to have all block drivers using
> > BLK and everything is still building / linking as unconverted drivers
> > now depend on BROKEN. This is showing we have a few widely used but
> > unconverted drivers over in Freescale/NXP land.
>
> That's a good idea. Does it work OK with DM_MMC and DM_USB? Is this a
> way we can keep unconverted boards around for a while without holding
> up migration? They won't work properly but will build?
I have some worthwhile changes in my WIP branch I haven't yet posted,
but, I think the problem is that we can't make BLK conversion the next
hard deadline. In order to make BLK (and DM) hard requirements, all of
MMC needs to be switched over (along with all of USB block related and
SATA, but MMC is the big one). That in turn shows a _lot_ of different
problems. We have:
- Drivers used by platforms which are using DM for other things but
aren't converted
- Platforms that could be switched to using DM but haven't yet, and
sometimes their storage controller is converted and sometimes it
isn't.
- What feels like almost all of PowerPC/MPC85xx at least.
So I think we should maybe try is:
- Pressing on the various folks that use MPC85xx/iMX to get some of
their drivers converted. This I think will allow us to fairly soon
mark SCSI/SATA as fully converted.
- I want to try re-working some of the Kconfig logic today so that we
have for example, DM_MMC pulling in BLK.
- Check in further with our iMX maintainers to see what they feel is
misssing before being able to fully convert.
- Check in with our Marvell maintainers to see what's missing before
they can fully convert.
- Check in with our USB maintainers to see what's missing before we can
fully convert them, aside from the PowerPC issue.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-23 19:38 ` Tom Rini
@ 2018-11-24 19:41 ` Simon Glass
2018-11-26 1:12 ` Tom Rini
0 siblings, 1 reply; 211+ messages in thread
From: Simon Glass @ 2018-11-24 19:41 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Fri, 23 Nov 2018 at 12:38, Tom Rini <trini@konsulko.com> wrote:
>
> On Fri, Nov 23, 2018 at 05:04:46AM -0700, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, 22 Nov 2018 at 16:31, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Thu, Nov 22, 2018 at 01:50:34PM -0700, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > > > > > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > > > > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > > > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > > > > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > > > > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > > > > > >>>>
> > > > > > > >>>>
> > > > > > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > > > > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > > > > >>>>> those with build problems using this option.
> > > > > > > >>>>>
> > > > > > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > > > > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > > > > > >>>>> release, and will need to be added and re-reviewed later.
> > > > > > > >>>> Fabio, Stefano,
> > > > > > > >>>>
> > > > > > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > > > > > >>>> But would it not make more sense to convert the reference boards first
> > > > > > > >>>> (mx6sabresd
> > > > > > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > > > > > >>>> as example for
> > > > > > > >>>> their own modifications?
> > > > > > > >>>
> > > > > > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > > > > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > > > > > >>> in this series.
> > > > > > > >>>
> > > > > > > >>>> Simon, Tom,
> > > > > > > >>>>
> > > > > > > >>>> is this really the usual u-boot working style to remove about hundred
> > > > > > > >>>> boards within
> > > > > > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > > > > > >>>> follow
> > > > > > > >>>> new developments, and more than once I fixed up regressions introduced
> > > > > > > >>>> by others
> > > > > > > >>>> in general code.
> > > > > > > >>>> But I cannot follow all development details without any heads-up. And
> > > > > > > >>>> even the
> > > > > > > >>>> NXP folks seem to be surprised about this.
> > > > > > > >>>>
> > > > > > > >>>> All problems with this transition seem to be located around usbstorage
> > > > > > > >>>> and sata.
> > > > > > > >>>> This is for sure not really very board specific. Is there any migration
> > > > > > > >>>> guide, or
> > > > > > > >>>> examples how other SoC architectures did this conversion?
> > > > > > > >>>
> > > > > > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > > > > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > > > > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > > > > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > > > > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > > > > > >>> addressed. But yes, we still have some large areas that after a few
> > > > > > > >>> years still have not been converted, and that puts me in a hard spot
> > > > > > > >>> too.
> > > > > > > >>
> > > > > > > >> Build time warning for a year would be good ?
> > > > > > > >
> > > > > > > > A year for this? No. New deadlines? That's not too far off from what
> > > > > > > > we've done historically, so yes.
> > > > > > >
> > > > > > > Give people some sort of breathing space to get the conversion done.
> > > > > > > Stressing people out by arbitrary deadlines will lead nowhere.
> > > > > >
> > > > > > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > > > > > are we going to drop SATA and USB Storage (if those are still all that's
> > > > > > left to convert) for this release. But given that we proposed a
> > > > > > deadline in August 2017, made email-but-not-build noise about it between
> > > > > > May and July/August of this year, no, I also don't think setting a new
> > > > > > deadline of November 2019 is the right call either.
> > > > > >
> > > > > > So, really, lets see what the fails to build boards are with BLK being
> > > > > > on when we have block devices. Then assess what a good deadline is.
> > > > > >
> > > > > > > >> Maybe we need some generic Makefile macro to set those up.
> > > > > > > >
> > > > > > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > > > > > complex set of options that didn't work.
> > > > > > >
> > > > > > > The problem was many people didn't know about the conversion deadline or
> > > > > > > simply forgot. And reminding them with a 100-patch series removing half
> > > > > > > of the boards is like splashing icy water bucket in their sleeping faces.
> > > > > >
> > > > > > Alright. But we've already tried less shocking approaches to
> > > > > > conversion, but in public (over the summer when Simon listed most of
> > > > > > these boards in a series but I _think_ his script failed to CC the
> > > > > > universe and didn't follow up with a repost that did email everyone) and
> > > > > > perhaps private too (I honestly don't recall if I did, or just intended
> > > > > > to, ask you about the USB side of this on IRC).
> > > > >
> > > > > And, for the record, the USB side I had in mind here was converted, and
> > > > > I just forgot, my fault. In fact, as I go through some hack-and-slash
> > > > > to see what needs a real conversion (either board updated, or drivers
> > > > > updated) at least some part of this is needing to adjust dependencies to
> > > > > force things on with BLK. For example, if we have MMC we must have
> > > > > DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
> > > >
> > > > Well, once we are through the migration we can remove BLK.
> > >
> > > I don't think BLK the symbol goes away, really. We don't want more
> > > objects built unconditionally and we will continue to have block
> > > device-less builds.
> >
> > Yes that's right - but it becomes an optional feature rather than an
> > indication of completed migration.
> >
> > >
> > > > Yes all the block devices are related, and we should use DM for all of
> > > > them to make this work.
> > > >
> > > > I am not sure if there is a better way to do this with Kconfig.
> > > >
> > > > Thanks for helping with all of this. I have found it quite tricky to
> > > > plot a path forward which is why I am been putting it off for several
> > > > months.
> > >
> > > Thanks for starting it off. I think part of the big problem we'll have
> > > here is that unfortunately we can't key off of the BLK migration itself
> > > as it's short-hand for having started using OF_CONTROL. What I'm
> > > currently working through is being able to have all block drivers using
> > > BLK and everything is still building / linking as unconverted drivers
> > > now depend on BROKEN. This is showing we have a few widely used but
> > > unconverted drivers over in Freescale/NXP land.
> >
> > That's a good idea. Does it work OK with DM_MMC and DM_USB? Is this a
> > way we can keep unconverted boards around for a while without holding
> > up migration? They won't work properly but will build?
>
> I have some worthwhile changes in my WIP branch I haven't yet posted,
> but, I think the problem is that we can't make BLK conversion the next
> hard deadline. In order to make BLK (and DM) hard requirements, all of
> MMC needs to be switched over (along with all of USB block related and
> SATA, but MMC is the big one). That in turn shows a _lot_ of different
> problems. We have:
> - Drivers used by platforms which are using DM for other things but
> aren't converted
> - Platforms that could be switched to using DM but haven't yet, and
> sometimes their storage controller is converted and sometimes it
> isn't.
> - What feels like almost all of PowerPC/MPC85xx at least.
>
> So I think we should maybe try is:
> - Pressing on the various folks that use MPC85xx/iMX to get some of
> their drivers converted. This I think will allow us to fairly soon
> mark SCSI/SATA as fully converted.
> - I want to try re-working some of the Kconfig logic today so that we
> have for example, DM_MMC pulling in BLK.
> - Check in further with our iMX maintainers to see what they feel is
> misssing before being able to fully convert.
> - Check in with our Marvell maintainers to see what's missing before
> they can fully convert.
> - Check in with our USB maintainers to see what's missing before we can
> fully convert them, aside from the PowerPC issue.
So you are suggesting a more 'bottom-up' approach where driver owners
do work before board owners?
Anyway this seems reasonable to me. For the case where boards could be
converted (drivers exist) but are not, perhaps a removal patch makes
sense.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-24 19:41 ` Simon Glass
@ 2018-11-26 1:12 ` Tom Rini
2018-11-26 2:59 ` Simon Glass
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-26 1:12 UTC (permalink / raw)
To: u-boot
On Sat, Nov 24, 2018 at 12:41:53PM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 23 Nov 2018 at 12:38, Tom Rini <trini@konsulko.com> wrote:
> >
> > On Fri, Nov 23, 2018 at 05:04:46AM -0700, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Thu, 22 Nov 2018 at 16:31, Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Thu, Nov 22, 2018 at 01:50:34PM -0700, Simon Glass wrote:
> > > > > Hi Tom,
> > > > >
> > > > > On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
> > > > > >
> > > > > > On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > > > > > > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > > > > > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > > > > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > > > > > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > > > > > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > > > > > > >>>>
> > > > > > > > >>>>
> > > > > > > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > > > > > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > > > > > >>>>> those with build problems using this option.
> > > > > > > > >>>>>
> > > > > > > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > > > > > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > > > > > > >>>>> release, and will need to be added and re-reviewed later.
> > > > > > > > >>>> Fabio, Stefano,
> > > > > > > > >>>>
> > > > > > > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > > > > > > >>>> But would it not make more sense to convert the reference boards first
> > > > > > > > >>>> (mx6sabresd
> > > > > > > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > > > > > > >>>> as example for
> > > > > > > > >>>> their own modifications?
> > > > > > > > >>>
> > > > > > > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > > > > > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > > > > > > >>> in this series.
> > > > > > > > >>>
> > > > > > > > >>>> Simon, Tom,
> > > > > > > > >>>>
> > > > > > > > >>>> is this really the usual u-boot working style to remove about hundred
> > > > > > > > >>>> boards within
> > > > > > > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > > > > > > >>>> follow
> > > > > > > > >>>> new developments, and more than once I fixed up regressions introduced
> > > > > > > > >>>> by others
> > > > > > > > >>>> in general code.
> > > > > > > > >>>> But I cannot follow all development details without any heads-up. And
> > > > > > > > >>>> even the
> > > > > > > > >>>> NXP folks seem to be surprised about this.
> > > > > > > > >>>>
> > > > > > > > >>>> All problems with this transition seem to be located around usbstorage
> > > > > > > > >>>> and sata.
> > > > > > > > >>>> This is for sure not really very board specific. Is there any migration
> > > > > > > > >>>> guide, or
> > > > > > > > >>>> examples how other SoC architectures did this conversion?
> > > > > > > > >>>
> > > > > > > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > > > > > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > > > > > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > > > > > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > > > > > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > > > > > > >>> addressed. But yes, we still have some large areas that after a few
> > > > > > > > >>> years still have not been converted, and that puts me in a hard spot
> > > > > > > > >>> too.
> > > > > > > > >>
> > > > > > > > >> Build time warning for a year would be good ?
> > > > > > > > >
> > > > > > > > > A year for this? No. New deadlines? That's not too far off from what
> > > > > > > > > we've done historically, so yes.
> > > > > > > >
> > > > > > > > Give people some sort of breathing space to get the conversion done.
> > > > > > > > Stressing people out by arbitrary deadlines will lead nowhere.
> > > > > > >
> > > > > > > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > > > > > > are we going to drop SATA and USB Storage (if those are still all that's
> > > > > > > left to convert) for this release. But given that we proposed a
> > > > > > > deadline in August 2017, made email-but-not-build noise about it between
> > > > > > > May and July/August of this year, no, I also don't think setting a new
> > > > > > > deadline of November 2019 is the right call either.
> > > > > > >
> > > > > > > So, really, lets see what the fails to build boards are with BLK being
> > > > > > > on when we have block devices. Then assess what a good deadline is.
> > > > > > >
> > > > > > > > >> Maybe we need some generic Makefile macro to set those up.
> > > > > > > > >
> > > > > > > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > > > > > > complex set of options that didn't work.
> > > > > > > >
> > > > > > > > The problem was many people didn't know about the conversion deadline or
> > > > > > > > simply forgot. And reminding them with a 100-patch series removing half
> > > > > > > > of the boards is like splashing icy water bucket in their sleeping faces.
> > > > > > >
> > > > > > > Alright. But we've already tried less shocking approaches to
> > > > > > > conversion, but in public (over the summer when Simon listed most of
> > > > > > > these boards in a series but I _think_ his script failed to CC the
> > > > > > > universe and didn't follow up with a repost that did email everyone) and
> > > > > > > perhaps private too (I honestly don't recall if I did, or just intended
> > > > > > > to, ask you about the USB side of this on IRC).
> > > > > >
> > > > > > And, for the record, the USB side I had in mind here was converted, and
> > > > > > I just forgot, my fault. In fact, as I go through some hack-and-slash
> > > > > > to see what needs a real conversion (either board updated, or drivers
> > > > > > updated) at least some part of this is needing to adjust dependencies to
> > > > > > force things on with BLK. For example, if we have MMC we must have
> > > > > > DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
> > > > >
> > > > > Well, once we are through the migration we can remove BLK.
> > > >
> > > > I don't think BLK the symbol goes away, really. We don't want more
> > > > objects built unconditionally and we will continue to have block
> > > > device-less builds.
> > >
> > > Yes that's right - but it becomes an optional feature rather than an
> > > indication of completed migration.
> > >
> > > >
> > > > > Yes all the block devices are related, and we should use DM for all of
> > > > > them to make this work.
> > > > >
> > > > > I am not sure if there is a better way to do this with Kconfig.
> > > > >
> > > > > Thanks for helping with all of this. I have found it quite tricky to
> > > > > plot a path forward which is why I am been putting it off for several
> > > > > months.
> > > >
> > > > Thanks for starting it off. I think part of the big problem we'll have
> > > > here is that unfortunately we can't key off of the BLK migration itself
> > > > as it's short-hand for having started using OF_CONTROL. What I'm
> > > > currently working through is being able to have all block drivers using
> > > > BLK and everything is still building / linking as unconverted drivers
> > > > now depend on BROKEN. This is showing we have a few widely used but
> > > > unconverted drivers over in Freescale/NXP land.
> > >
> > > That's a good idea. Does it work OK with DM_MMC and DM_USB? Is this a
> > > way we can keep unconverted boards around for a while without holding
> > > up migration? They won't work properly but will build?
> >
> > I have some worthwhile changes in my WIP branch I haven't yet posted,
> > but, I think the problem is that we can't make BLK conversion the next
> > hard deadline. In order to make BLK (and DM) hard requirements, all of
> > MMC needs to be switched over (along with all of USB block related and
> > SATA, but MMC is the big one). That in turn shows a _lot_ of different
> > problems. We have:
> > - Drivers used by platforms which are using DM for other things but
> > aren't converted
> > - Platforms that could be switched to using DM but haven't yet, and
> > sometimes their storage controller is converted and sometimes it
> > isn't.
> > - What feels like almost all of PowerPC/MPC85xx at least.
> >
> > So I think we should maybe try is:
> > - Pressing on the various folks that use MPC85xx/iMX to get some of
> > their drivers converted. This I think will allow us to fairly soon
> > mark SCSI/SATA as fully converted.
> > - I want to try re-working some of the Kconfig logic today so that we
> > have for example, DM_MMC pulling in BLK.
> > - Check in further with our iMX maintainers to see what they feel is
> > misssing before being able to fully convert.
> > - Check in with our Marvell maintainers to see what's missing before
> > they can fully convert.
> > - Check in with our USB maintainers to see what's missing before we can
> > fully convert them, aside from the PowerPC issue.
>
> So you are suggesting a more 'bottom-up' approach where driver owners
> do work before board owners?
In essence, yes. We _do_ have some board issues (for example,
omap3_beagle doesn't Just Work when switched to DM_MMC, and my first
reaction is that it probably needs to be updated to have all the various
DTB files for the various "beagleboard" variants and updated to load the
right one in SPL) but we have a lot more widely used drivers that need
converting. I tried to cover this in my RFC series today but as I also
listed above, unless we're going to remove huge swaths of boards, we
can't pull the trigger yet. But I do hope this will have set off enough
alarm bells to get this technical debt paid down a bit.
> Anyway this seems reasonable to me. For the case where boards could be
> converted (drivers exist) but are not, perhaps a removal patch makes
> sense.
In time, yes, after we've had the build-time warnings showing up for a
bit. And some boards can be easily converted, I'm pretty sure (ie all
of sunxi).
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-26 1:12 ` Tom Rini
@ 2018-11-26 2:59 ` Simon Glass
0 siblings, 0 replies; 211+ messages in thread
From: Simon Glass @ 2018-11-26 2:59 UTC (permalink / raw)
To: u-boot
Hi Tom.
On Sun, 25 Nov 2018 at 18:12, Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Nov 24, 2018 at 12:41:53PM -0700, Simon Glass wrote:
> > Hi Tom,
> >
> > On Fri, 23 Nov 2018 at 12:38, Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Fri, Nov 23, 2018 at 05:04:46AM -0700, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On Thu, 22 Nov 2018 at 16:31, Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Thu, Nov 22, 2018 at 01:50:34PM -0700, Simon Glass wrote:
> > > > > > Hi Tom,
> > > > > >
> > > > > > On Wed, 21 Nov 2018 at 08:10, Tom Rini <trini@konsulko.com> wrote:
> > > > > > >
> > > > > > > On Tue, Nov 20, 2018 at 08:53:12AM -0500, Tom Rini wrote:
> > > > > > > > On Tue, Nov 20, 2018 at 02:45:24PM +0100, Marek Vasut wrote:
> > > > > > > > > On 11/20/2018 02:42 PM, Tom Rini wrote:
> > > > > > > > > > On Tue, Nov 20, 2018 at 02:40:43PM +0100, Marek Vasut wrote:
> > > > > > > > > >> On 11/20/2018 02:37 PM, Tom Rini wrote:
> > > > > > > > > >>> On Tue, Nov 20, 2018 at 01:42:15PM +0100, Soeren Moch wrote:
> > > > > > > > > >>>>
> > > > > > > > > >>>>
> > > > > > > > > >>>> On 19.11.18 16:52, Simon Glass wrote:
> > > > > > > > > >>>>> All boards should now be migrated to use CONFIG_BLK. This series removes
> > > > > > > > > >>>>> those with build problems using this option.
> > > > > > > > > >>>>>
> > > > > > > > > >>>>> If maintainers want to keep these boards in they should send a patch in
> > > > > > > > > >>>>> the next week or two. Otherwise the board will be removed in the next
> > > > > > > > > >>>>> release, and will need to be added and re-reviewed later.
> > > > > > > > > >>>> Fabio, Stefano,
> > > > > > > > > >>>>
> > > > > > > > > >>>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> > > > > > > > > >>>> But would it not make more sense to convert the reference boards first
> > > > > > > > > >>>> (mx6sabresd
> > > > > > > > > >>>> in my case for tbs2910), and let hobbyist maintainers like me take this
> > > > > > > > > >>>> as example for
> > > > > > > > > >>>> their own modifications?
> > > > > > > > > >>>
> > > > > > > > > >>> So, I replied to the main thread earlier but no, we're not going to drop
> > > > > > > > > >>> everything in 2 weeks, especially since there's a lot of false positives
> > > > > > > > > >>> in this series.
> > > > > > > > > >>>
> > > > > > > > > >>>> Simon, Tom,
> > > > > > > > > >>>>
> > > > > > > > > >>>> is this really the usual u-boot working style to remove about hundred
> > > > > > > > > >>>> boards within
> > > > > > > > > >>>> two weeks without prior warning? As hobbyist board maintainer I try to
> > > > > > > > > >>>> follow
> > > > > > > > > >>>> new developments, and more than once I fixed up regressions introduced
> > > > > > > > > >>>> by others
> > > > > > > > > >>>> in general code.
> > > > > > > > > >>>> But I cannot follow all development details without any heads-up. And
> > > > > > > > > >>>> even the
> > > > > > > > > >>>> NXP folks seem to be surprised about this.
> > > > > > > > > >>>>
> > > > > > > > > >>>> All problems with this transition seem to be located around usbstorage
> > > > > > > > > >>>> and sata.
> > > > > > > > > >>>> This is for sure not really very board specific. Is there any migration
> > > > > > > > > >>>> guide, or
> > > > > > > > > >>>> examples how other SoC architectures did this conversion?
> > > > > > > > > >>>
> > > > > > > > > >>> I'll admit this hasn't been our best notification. But, the deadline
> > > > > > > > > >>> was discussed about a year ago (and then no, I didn't get a build-time
> > > > > > > > > >>> warning in). Then around v2018.05 I said it wasn't going to be a
> > > > > > > > > >>> removal type problem yet as we had a lot of boards to fixup still, and
> > > > > > > > > >>> repeated that at v2018.07. That did lead to a lot of things getting
> > > > > > > > > >>> addressed. But yes, we still have some large areas that after a few
> > > > > > > > > >>> years still have not been converted, and that puts me in a hard spot
> > > > > > > > > >>> too.
> > > > > > > > > >>
> > > > > > > > > >> Build time warning for a year would be good ?
> > > > > > > > > >
> > > > > > > > > > A year for this? No. New deadlines? That's not too far off from what
> > > > > > > > > > we've done historically, so yes.
> > > > > > > > >
> > > > > > > > > Give people some sort of breathing space to get the conversion done.
> > > > > > > > > Stressing people out by arbitrary deadlines will lead nowhere.
> > > > > > > >
> > > > > > > > Sure, agreed. I didn't say we're going to drop all these boards, nor
> > > > > > > > are we going to drop SATA and USB Storage (if those are still all that's
> > > > > > > > left to convert) for this release. But given that we proposed a
> > > > > > > > deadline in August 2017, made email-but-not-build noise about it between
> > > > > > > > May and July/August of this year, no, I also don't think setting a new
> > > > > > > > deadline of November 2019 is the right call either.
> > > > > > > >
> > > > > > > > So, really, lets see what the fails to build boards are with BLK being
> > > > > > > > on when we have block devices. Then assess what a good deadline is.
> > > > > > > >
> > > > > > > > > >> Maybe we need some generic Makefile macro to set those up.
> > > > > > > > > >
> > > > > > > > > > It would be nice, yes. I think the problem here is (or, was) the
> > > > > > > > > > complex set of options that didn't work.
> > > > > > > > >
> > > > > > > > > The problem was many people didn't know about the conversion deadline or
> > > > > > > > > simply forgot. And reminding them with a 100-patch series removing half
> > > > > > > > > of the boards is like splashing icy water bucket in their sleeping faces.
> > > > > > > >
> > > > > > > > Alright. But we've already tried less shocking approaches to
> > > > > > > > conversion, but in public (over the summer when Simon listed most of
> > > > > > > > these boards in a series but I _think_ his script failed to CC the
> > > > > > > > universe and didn't follow up with a repost that did email everyone) and
> > > > > > > > perhaps private too (I honestly don't recall if I did, or just intended
> > > > > > > > to, ask you about the USB side of this on IRC).
> > > > > > >
> > > > > > > And, for the record, the USB side I had in mind here was converted, and
> > > > > > > I just forgot, my fault. In fact, as I go through some hack-and-slash
> > > > > > > to see what needs a real conversion (either board updated, or drivers
> > > > > > > updated) at least some part of this is needing to adjust dependencies to
> > > > > > > force things on with BLK. For example, if we have MMC we must have
> > > > > > > DM_MMC and BLK, and if we have USB we must have DM_USB and BLK.
> > > > > >
> > > > > > Well, once we are through the migration we can remove BLK.
> > > > >
> > > > > I don't think BLK the symbol goes away, really. We don't want more
> > > > > objects built unconditionally and we will continue to have block
> > > > > device-less builds.
> > > >
> > > > Yes that's right - but it becomes an optional feature rather than an
> > > > indication of completed migration.
> > > >
> > > > >
> > > > > > Yes all the block devices are related, and we should use DM for all of
> > > > > > them to make this work.
> > > > > >
> > > > > > I am not sure if there is a better way to do this with Kconfig.
> > > > > >
> > > > > > Thanks for helping with all of this. I have found it quite tricky to
> > > > > > plot a path forward which is why I am been putting it off for several
> > > > > > months.
> > > > >
> > > > > Thanks for starting it off. I think part of the big problem we'll have
> > > > > here is that unfortunately we can't key off of the BLK migration itself
> > > > > as it's short-hand for having started using OF_CONTROL. What I'm
> > > > > currently working through is being able to have all block drivers using
> > > > > BLK and everything is still building / linking as unconverted drivers
> > > > > now depend on BROKEN. This is showing we have a few widely used but
> > > > > unconverted drivers over in Freescale/NXP land.
> > > >
> > > > That's a good idea. Does it work OK with DM_MMC and DM_USB? Is this a
> > > > way we can keep unconverted boards around for a while without holding
> > > > up migration? They won't work properly but will build?
> > >
> > > I have some worthwhile changes in my WIP branch I haven't yet posted,
> > > but, I think the problem is that we can't make BLK conversion the next
> > > hard deadline. In order to make BLK (and DM) hard requirements, all of
> > > MMC needs to be switched over (along with all of USB block related and
> > > SATA, but MMC is the big one). That in turn shows a _lot_ of different
> > > problems. We have:
> > > - Drivers used by platforms which are using DM for other things but
> > > aren't converted
> > > - Platforms that could be switched to using DM but haven't yet, and
> > > sometimes their storage controller is converted and sometimes it
> > > isn't.
> > > - What feels like almost all of PowerPC/MPC85xx at least.
> > >
> > > So I think we should maybe try is:
> > > - Pressing on the various folks that use MPC85xx/iMX to get some of
> > > their drivers converted. This I think will allow us to fairly soon
> > > mark SCSI/SATA as fully converted.
> > > - I want to try re-working some of the Kconfig logic today so that we
> > > have for example, DM_MMC pulling in BLK.
> > > - Check in further with our iMX maintainers to see what they feel is
> > > misssing before being able to fully convert.
> > > - Check in with our Marvell maintainers to see what's missing before
> > > they can fully convert.
> > > - Check in with our USB maintainers to see what's missing before we can
> > > fully convert them, aside from the PowerPC issue.
> >
> > So you are suggesting a more 'bottom-up' approach where driver owners
> > do work before board owners?
>
> In essence, yes. We _do_ have some board issues (for example,
> omap3_beagle doesn't Just Work when switched to DM_MMC, and my first
> reaction is that it probably needs to be updated to have all the various
> DTB files for the various "beagleboard" variants and updated to load the
> right one in SPL) but we have a lot more widely used drivers that need
> converting. I tried to cover this in my RFC series today but as I also
> listed above, unless we're going to remove huge swaths of boards, we
> can't pull the trigger yet. But I do hope this will have set off enough
> alarm bells to get this technical debt paid down a bit.
Yes I think the alarms are ringing :-) The body count is definitely
too high right now.
>
> > Anyway this seems reasonable to me. For the case where boards could be
> > converted (drivers exist) but are not, perhaps a removal patch makes
> > sense.
>
> In time, yes, after we've had the build-time warnings showing up for a
> bit. And some boards can be easily converted, I'm pretty sure (ie all
> of sunxi).
Yes that seems quite close.
I'll take a look at some other subsystems that might be close, or need
conversion. Perhaps we should add warnings for most/all of them.
Regards,
Simon
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-20 12:42 ` Soeren Moch
2018-11-20 13:37 ` Tom Rini
@ 2018-11-23 0:31 ` Fabio Estevam
2018-11-23 14:35 ` Soeren Moch
1 sibling, 1 reply; 211+ messages in thread
From: Fabio Estevam @ 2018-11-23 0:31 UTC (permalink / raw)
To: u-boot
Hi Soeren,
On Tue, Nov 20, 2018 at 10:44 AM Soeren Moch <smoch@web.de> wrote:
> Fabio, Stefano,
>
> it seems (almost?) all i.mx6 boards should be removed within two weeks.
> But would it not make more sense to convert the reference boards first
> (mx6sabresd
> in my case for tbs2910), and let hobbyist maintainers like me take this
> as example for
> their own modifications?
There are some imx boards that use DM:
git grep CONFIG_OF_CONTROL configs/ | grep mx
You can use them as a reference for converting tbs2910.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-23 0:31 ` Fabio Estevam
@ 2018-11-23 14:35 ` Soeren Moch
0 siblings, 0 replies; 211+ messages in thread
From: Soeren Moch @ 2018-11-23 14:35 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On 23.11.18 01:31, Fabio Estevam wrote:
> Hi Soeren,
>
> On Tue, Nov 20, 2018 at 10:44 AM Soeren Moch <smoch@web.de> wrote:
>
>> Fabio, Stefano,
>>
>> it seems (almost?) all i.mx6 boards should be removed within two weeks.
>> But would it not make more sense to convert the reference boards first
>> (mx6sabresd
>> in my case for tbs2910), and let hobbyist maintainers like me take this
>> as example for
>> their own modifications?
> There are some imx boards that use DM:
>
> git grep CONFIG_OF_CONTROL configs/ | grep mx
>
> You can use them as a reference for converting tbs2910.
Unfortunately, there are no imx6q (or 6d, 6dl) boards in this list. I
guess (have not investigated in detail) this is due to missing SATA
support under CONFIG_BLK for 6qdl. Maybe other additional problems.
So I'm afraid I cannot do this conversion on my own. However, I'm happy
to test anything what becomes available. At least there is only a imx6q
variant of tbs2910, so no additional worries about different dtbs or SPL.
Regards,
Soeren
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (95 preceding siblings ...)
2018-11-20 12:42 ` Soeren Moch
@ 2018-11-21 15:13 ` Guillaume GARDET
2018-11-21 17:06 ` Tom Rini
2018-11-22 17:45 ` [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Tom Rini
97 siblings, 1 reply; 211+ messages in thread
From: Guillaume GARDET @ 2018-11-21 15:13 UTC (permalink / raw)
To: u-boot
Also disable USB_STORAGE as it is not ready for the switch.
Tested on a Beagleboard xM rev. B.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
---
configs/omap3_beagle_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 4fb8aec57d..b4ea714aef 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -37,6 +37,7 @@ CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_LED_STATUS=y
@@ -52,6 +53,8 @@ CONFIG_LED_STATUS_GREEN_ENABLE=y
CONFIG_LED_STATUS_GREEN=2
CONFIG_LED_STATUS_CMD=y
CONFIG_TWL4030_LED=y
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
@@ -66,7 +69,6 @@ CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
--
2.19.1
^ permalink raw reply related [flat|nested] 211+ messages in thread* [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL
2018-11-21 15:13 ` [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL Guillaume GARDET
@ 2018-11-21 17:06 ` Tom Rini
2018-12-17 17:03 ` Guillaume Gardet
0 siblings, 1 reply; 211+ messages in thread
From: Tom Rini @ 2018-11-21 17:06 UTC (permalink / raw)
To: u-boot
On Wed, Nov 21, 2018 at 04:13:20PM +0100, Guillaume GARDET wrote:
> Also disable USB_STORAGE as it is not ready for the switch.
> Tested on a Beagleboard xM rev. B.
>
> Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Simon Glass <sjg@chromium.org>
In the case of USB_STORAGE we need to turn on DM_USB and then it works.
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL
2018-11-21 17:06 ` Tom Rini
@ 2018-12-17 17:03 ` Guillaume Gardet
2018-12-17 19:34 ` Adam Ford
0 siblings, 1 reply; 211+ messages in thread
From: Guillaume Gardet @ 2018-12-17 17:03 UTC (permalink / raw)
To: u-boot
Le 21/11/2018 à 18:06, Tom Rini a écrit :
> On Wed, Nov 21, 2018 at 04:13:20PM +0100, Guillaume GARDET wrote:
>
>> Also disable USB_STORAGE as it is not ready for the switch.
>> Tested on a Beagleboard xM rev. B.
>>
>> Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
>>
>> Cc: Tom Rini <trini@konsulko.com>
>> Cc: Simon Glass <sjg@chromium.org>
> In the case of USB_STORAGE we need to turn on DM_USB and then it works.
If DM_USB is enabled, no USB controller are detected, so we loose Ethernet. Did I miss an additional option to enable?
Guillaume
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL
2018-12-17 17:03 ` Guillaume Gardet
@ 2018-12-17 19:34 ` Adam Ford
2018-12-17 20:44 ` Adam Ford
2018-12-18 1:41 ` Tom Rini
0 siblings, 2 replies; 211+ messages in thread
From: Adam Ford @ 2018-12-17 19:34 UTC (permalink / raw)
To: u-boot
On Mon, Dec 17, 2018 at 11:04 AM Guillaume Gardet
<guillaume.gardet@free.fr> wrote:
>
>
> Le 21/11/2018 à 18:06, Tom Rini a écrit :
> > On Wed, Nov 21, 2018 at 04:13:20PM +0100, Guillaume GARDET wrote:
> >
> >> Also disable USB_STORAGE as it is not ready for the switch.
> >> Tested on a Beagleboard xM rev. B.
> >>
> >> Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
> >>
> >> Cc: Tom Rini <trini@konsulko.com>
> >> Cc: Simon Glass <sjg@chromium.org>
> > In the case of USB_STORAGE we need to turn on DM_USB and then it works.
>
>
> If DM_USB is enabled, no USB controller are detected, so we loose Ethernet. Did I miss an additional option to enable?
AFASK, the MUSB driver didn't yet support gadget mode when used with
DM_USB... at least until recently. I noticed that part of the MUSB
driver was updated, but the omap2430 glue hasn't been updated yet. I
am not 100% sure, but I think the Beagle xM is a DM3730 which uses the
omap2430 glue. I doubt TI will update the omap2430 glue, so I started
some stuff. I've got on patch that seems to show the usb gadget
controller in the DM tree, but my board hangs when I try to use a
gadget.
It's not ready for the mailing list yet, but I can push this stuff to
my github later today if someone wants to look at it and/or
test/improve it.
adam
>
> Guillaume
>
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL
2018-12-17 19:34 ` Adam Ford
@ 2018-12-17 20:44 ` Adam Ford
2018-12-18 1:41 ` Tom Rini
1 sibling, 0 replies; 211+ messages in thread
From: Adam Ford @ 2018-12-17 20:44 UTC (permalink / raw)
To: u-boot
On Mon, Dec 17, 2018 at 1:34 PM Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Dec 17, 2018 at 11:04 AM Guillaume Gardet
> <guillaume.gardet@free.fr> wrote:
> >
> >
> > Le 21/11/2018 à 18:06, Tom Rini a écrit :
> > > On Wed, Nov 21, 2018 at 04:13:20PM +0100, Guillaume GARDET wrote:
> > >
> > >> Also disable USB_STORAGE as it is not ready for the switch.
> > >> Tested on a Beagleboard xM rev. B.
> > >>
> > >> Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
> > >>
> > >> Cc: Tom Rini <trini@konsulko.com>
> > >> Cc: Simon Glass <sjg@chromium.org>
> > > In the case of USB_STORAGE we need to turn on DM_USB and then it works.
> >
> >
> > If DM_USB is enabled, no USB controller are detected, so we loose Ethernet. Did I miss an additional option to enable?
>
> AFASK, the MUSB driver didn't yet support gadget mode when used with
> DM_USB... at least until recently. I noticed that part of the MUSB
> driver was updated, but the omap2430 glue hasn't been updated yet. I
> am not 100% sure, but I think the Beagle xM is a DM3730 which uses the
> omap2430 glue. I doubt TI will update the omap2430 glue, so I started
> some stuff. I've got on patch that seems to show the usb gadget
> controller in the DM tree, but my board hangs when I try to use a
> gadget.
>
> It's not ready for the mailing list yet, but I can push this stuff to
> my github later today if someone wants to look at it and/or
> test/improve it.
Guillaume,
I 'think' I got the peripheral mode working on my DM3730. Like
before, it only supports host or gadget, and I set the patch up to
look at whether or not CONFIG_USB_MUSB_GADGET is set.
I was able to get Fastboot devices to appear and an sdp device to
appear. I wasn't setup to actually run data through those interfaces,
but my host machine recognized them.
Feel free to try the patches and please give feedback. They are
located: https://patchwork.ozlabs.org/project/uboot/list/?series=82418
adam
>
> adam
> >
> > Guillaume
> >
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL
2018-12-17 19:34 ` Adam Ford
2018-12-17 20:44 ` Adam Ford
@ 2018-12-18 1:41 ` Tom Rini
1 sibling, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-12-18 1:41 UTC (permalink / raw)
To: u-boot
On Mon, Dec 17, 2018 at 01:34:53PM -0600, Adam Ford wrote:
> On Mon, Dec 17, 2018 at 11:04 AM Guillaume Gardet
> <guillaume.gardet@free.fr> wrote:
> >
> >
> > Le 21/11/2018 à 18:06, Tom Rini a écrit :
> > > On Wed, Nov 21, 2018 at 04:13:20PM +0100, Guillaume GARDET wrote:
> > >
> > >> Also disable USB_STORAGE as it is not ready for the switch.
> > >> Tested on a Beagleboard xM rev. B.
> > >>
> > >> Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
> > >>
> > >> Cc: Tom Rini <trini@konsulko.com>
> > >> Cc: Simon Glass <sjg@chromium.org>
> > > In the case of USB_STORAGE we need to turn on DM_USB and then it works.
> >
> >
> > If DM_USB is enabled, no USB controller are detected, so we loose Ethernet. Did I miss an additional option to enable?
>
> AFASK, the MUSB driver didn't yet support gadget mode when used with
> DM_USB... at least until recently. I noticed that part of the MUSB
> driver was updated, but the omap2430 glue hasn't been updated yet. I
> am not 100% sure, but I think the Beagle xM is a DM3730 which uses the
> omap2430 glue. I doubt TI will update the omap2430 glue, so I started
> some stuff. I've got on patch that seems to show the usb gadget
> controller in the DM tree, but my board hangs when I try to use a
> gadget.
>
> It's not ready for the mailing list yet, but I can push this stuff to
> my github later today if someone wants to look at it and/or
> test/improve it.
Thanks for looking into all this. Another thing missing right now is
the logic to move to SPL FIT images and pick the right DTB for the
variant we're on as for example my bb xM doesn't work at all once we
switch to mostly DM :)
--
Tom
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^ permalink raw reply [flat|nested] 211+ messages in thread
* [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration
2018-11-19 15:52 [U-Boot] [PATCH 00/93] dm: Move towards completing CONFIG_BLK migration Simon Glass
` (96 preceding siblings ...)
2018-11-21 15:13 ` [U-Boot] [PATCH] omap3: beagle: Enable DM_MMC and BLK for u-boot only, not SPL Guillaume GARDET
@ 2018-11-22 17:45 ` Tom Rini
97 siblings, 0 replies; 211+ messages in thread
From: Tom Rini @ 2018-11-22 17:45 UTC (permalink / raw)
To: u-boot
On Mon, Nov 19, 2018 at 10:54 AM Simon Glass <sjg@chromium.org> wrote:
>
> All boards should now be migrated to use CONFIG_BLK. This series removes
> those with build problems using this option.
>
> If maintainers want to keep these boards in they should send a patch in
> the next week or two. Otherwise the board will be removed in the next
> release, and will need to be added and re-reviewed later.
>
> The goal is to have all boards use driver model. But so far, we do allow
> CONFIG_DM to not be defined.
Hey everyone. Did we scare you perhaps a bit too much? Sorry. We're
not going to be dropping boards quite just yet as we have a few
drivers yet that need converting and that in turn is what's blocking
some amount of easy mass conversion. That said, does your board set
CONFIG_OF_CONTROL and related? If not, you do indeed have some work
to go and do or the platform will be dropped. Not immediately but we
have come far enough along in our conversions that as a general rule,
you should be using DM in full U-Boot and figuring out how to use DM
in SPL (and if there's some problem, speaking up so we can figure out
a solution). Thanks all!
--
Tom
^ permalink raw reply [flat|nested] 211+ messages in thread