* [PATCH v2 0/2] Add R8A77980/Condor PCIe support
@ 2018-08-27 18:48 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:48 UTC (permalink / raw)
To: linux-arm-kernel
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180827-v4.19-rc1' tag. We're adding the R8A77980 PCIe
related device nodes and then enable PCIe on the Condor board.
[1/2] arm64: dts: renesas: r8a77980: add PCIe support
[2/2] arm64: dts: renesas: condor: add PCIe support
WBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2 0/2] Add R8A77980/Condor PCIe support
@ 2018-08-27 18:48 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:48 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180827-v4.19-rc1' tag. We're adding the R8A77980 PCIe
related device nodes and then enable PCIe on the Condor board.
[1/2] arm64: dts: renesas: r8a77980: add PCIe support
[2/2] arm64: dts: renesas: condor: add PCIe support
WBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 0/2] Add R8A77980/Condor PCIe support
2018-08-27 18:48 ` Sergei Shtylyov
(?)
@ 2018-08-27 18:52 ` Sergei Shtylyov
-1 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:52 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
v3, I meant to type... :-/
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add PCIe support
2018-08-27 18:48 ` Sergei Shtylyov
(?)
@ 2018-08-27 18:53 ` Sergei Shtylyov
-1 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:53 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 3:
- refreshed against the recent tree (moving the PCIe clock node);
- added Simon's tag.
Changes in version 2:
- merged in the PCIEC patch, renamed the patch, updated the description
accordingly;
- used R8A77980_PD_ALWAYS_ON in the "power-domains" props;
- mentioned Vladimir's original work and added his signoff.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 49 ++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,13 @@
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -437,6 +444,16 @@
status = "disabled";
};
+ pcie_phy: pcie-phy@e65d0000 {
+ compatible = "renesas,r8a77980-pcie-phy";
+ reg = <0 0xe65d0000 0 0x8000>;
+ #phy-cells = <0>;
+ clocks = <&cpg CPG_MOD 319>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
canfd: can@e66c0000 {
compatible = "renesas,r8a77980-canfd",
"renesas,rcar-gen3-canfd";
@@ -1047,6 +1064,38 @@
resets = <&cpg 408>;
};
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a77980",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <
+ 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
+ >;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
+ 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x5000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add PCIe support
@ 2018-08-27 18:53 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:53 UTC (permalink / raw)
To: linux-arm-kernel
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 3:
- refreshed against the recent tree (moving the PCIe clock node);
- added Simon's tag.
Changes in version 2:
- merged in the PCIEC patch, renamed the patch, updated the description
accordingly;
- used R8A77980_PD_ALWAYS_ON in the "power-domains" props;
- mentioned Vladimir's original work and added his signoff.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 49 ++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,13 @@
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -437,6 +444,16 @@
status = "disabled";
};
+ pcie_phy: pcie-phy at e65d0000 {
+ compatible = "renesas,r8a77980-pcie-phy";
+ reg = <0 0xe65d0000 0 0x8000>;
+ #phy-cells = <0>;
+ clocks = <&cpg CPG_MOD 319>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
canfd: can at e66c0000 {
compatible = "renesas,r8a77980-canfd",
"renesas,rcar-gen3-canfd";
@@ -1047,6 +1064,38 @@
resets = <&cpg 408>;
};
+ pciec: pcie at fe000000 {
+ compatible = "renesas,pcie-r8a77980",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <
+ 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
+ >;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
+ 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
vspd0: vsp at fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x5000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add PCIe support
@ 2018-08-27 18:53 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:53 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 3:
- refreshed against the recent tree (moving the PCIe clock node);
- added Simon's tag.
Changes in version 2:
- merged in the PCIEC patch, renamed the patch, updated the description
accordingly;
- used R8A77980_PD_ALWAYS_ON in the "power-domains" props;
- mentioned Vladimir's original work and added his signoff.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 49 ++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,13 @@
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -437,6 +444,16 @@
status = "disabled";
};
+ pcie_phy: pcie-phy@e65d0000 {
+ compatible = "renesas,r8a77980-pcie-phy";
+ reg = <0 0xe65d0000 0 0x8000>;
+ #phy-cells = <0>;
+ clocks = <&cpg CPG_MOD 319>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
canfd: can@e66c0000 {
compatible = "renesas,r8a77980-canfd",
"renesas,rcar-gen3-canfd";
@@ -1047,6 +1064,38 @@
resets = <&cpg 408>;
};
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a77980",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <
+ 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
+ >;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
+ 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x5000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add PCIe support
2018-08-27 18:53 ` Sergei Shtylyov
(?)
@ 2018-08-30 12:32 ` Simon Horman
-1 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-08-30 12:32 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, linux-renesas-soc,
Rob Herring, linux-arm-kernel
On Mon, Aug 27, 2018 at 09:53:40PM +0300, Sergei Shtylyov wrote:
> Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
> tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add PCIe support
@ 2018-08-30 12:32 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-08-30 12:32 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 27, 2018 at 09:53:40PM +0300, Sergei Shtylyov wrote:
> Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
> tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: renesas: r8a77980: add PCIe support
@ 2018-08-30 12:32 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-08-30 12:32 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, linux-arm-kernel
On Mon, Aug 27, 2018 at 09:53:40PM +0300, Sergei Shtylyov wrote:
> Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
> tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v3 2/2] arm64: dts: renesas: condor: add PCIe support
2018-08-27 18:48 ` Sergei Shtylyov
(?)
@ 2018-08-27 18:54 ` Sergei Shtylyov
-1 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:54 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Changes in version 2:
- mentioned Vladimir's original work and added his signoff;
- refreshed the patch.
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -223,6 +223,18 @@
status = "okay";
};
+&pciec {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
^ permalink raw reply [flat|nested] 86+ messages in thread* [PATCH v3 2/2] arm64: dts: renesas: condor: add PCIe support
@ 2018-08-27 18:54 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:54 UTC (permalink / raw)
To: linux-arm-kernel
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Changes in version 2:
- mentioned Vladimir's original work and added his signoff;
- refreshed the patch.
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -223,6 +223,18 @@
status = "okay";
};
+&pciec {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
^ permalink raw reply [flat|nested] 86+ messages in thread* [PATCH v3 2/2] arm64: dts: renesas: condor: add PCIe support
@ 2018-08-27 18:54 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-08-27 18:54 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Changes in version 2:
- mentioned Vladimir's original work and added his signoff;
- refreshed the patch.
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -223,6 +223,18 @@
status = "okay";
};
+&pciec {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v3 2/2] arm64: dts: renesas: condor: add PCIe support
2018-08-27 18:54 ` Sergei Shtylyov
(?)
@ 2018-08-30 12:32 ` Simon Horman
-1 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-08-30 12:32 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, linux-renesas-soc,
Rob Herring, linux-arm-kernel
On Mon, Aug 27, 2018 at 09:54:35PM +0300, Sergei Shtylyov wrote:
> Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
> board.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v3 2/2] arm64: dts: renesas: condor: add PCIe support
@ 2018-08-30 12:32 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-08-30 12:32 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 27, 2018 at 09:54:35PM +0300, Sergei Shtylyov wrote:
> Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
> board.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: renesas: condor: add PCIe support
@ 2018-08-30 12:32 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-08-30 12:32 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, linux-arm-kernel
On Mon, Aug 27, 2018 at 09:54:35PM +0300, Sergei Shtylyov wrote:
> Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
> board.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a779{7|8}0: add CMT support
2018-08-27 18:48 ` Sergei Shtylyov
` (4 preceding siblings ...)
(?)
@ 2018-09-06 17:02 ` Sergei Shtylyov
2018-09-06 18:43 ` Sergei Shtylyov
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-06 17:02 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe CMTs in the R8A779{7|8}0 device trees.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
Simon Horman's 'renesas.git' repo.
The R8A779{7|8}0 CMT DT binding updates have been posted yesterday...
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
2 files changed, 132 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -239,6 +239,72 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77980-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77980-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -209,6 +209,72 @@
reg = <0 0xe6060000 0 0x504>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77970-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77970-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77970-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77970-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add CMT support
2018-09-06 17:02 ` [PATCH] arm64: dts: renesas: r8a779{7|8}0: add CMT support Sergei Shtylyov
@ 2018-09-06 18:43 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-06 18:43 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
On 09/06/2018 08:02 PM, Sergei Shtylyov wrote:
> Describe CMTs in the R8A779{7|8}0 device trees.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
> Simon Horman's 'renesas.git' repo.
>
> The R8A779{7|8}0 CMT DT binding updates have been posted yesterday...
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
> 2 files changed, 132 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -239,6 +239,72 @@
> reg = <0 0xe6060000 0 0x50c>;
> };
>
> + cmt0: timer@e60f0000 {
> + compatible = "renesas,r8a77980-cmt0",
> + "renesas,rcar-gen3-cmt0";
> + reg = <0 0xe60f0000 0 0x1004>;
> + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 303>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + status = "disabled";
> + };
"resets"! I forgot about them again... :-(
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add CMT support
2018-08-27 18:48 ` Sergei Shtylyov
` (5 preceding siblings ...)
(?)
@ 2018-09-07 18:58 ` Sergei Shtylyov
2018-09-10 9:05 ` Simon Horman
2018-09-19 7:47 ` Geert Uytterhoeven
-1 siblings, 2 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-07 18:58 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe CMTs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
Simon Horman's 'renesas.git' repo.
The R8A779{7|8}0 CMT DT binding updates have been posted the other day...
Changes in version 2:
- added the "resets" prop to all CMT nodes;
- credited Vladimir Barinov as the formal author of the original patches.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 70 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 70 ++++++++++++++++++++++++++++++
2 files changed, 140 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -209,6 +209,76 @@
reg = <0 0xe6060000 0 0x504>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77970-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77970-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77970-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77970-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -239,6 +239,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77980-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77980-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add CMT support
2018-09-07 18:58 ` [PATCH v2] " Sergei Shtylyov
@ 2018-09-10 9:05 ` Simon Horman
2018-09-19 7:47 ` Geert Uytterhoeven
1 sibling, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-09-10 9:05 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Fri, Sep 07, 2018 at 09:58:41PM +0300, Sergei Shtylyov wrote:
> Describe CMTs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei,
This looks fine to me but I will wait to see if there are other reviews
before applying.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add CMT support
2018-09-07 18:58 ` [PATCH v2] " Sergei Shtylyov
2018-09-10 9:05 ` Simon Horman
@ 2018-09-19 7:47 ` Geert Uytterhoeven
2018-09-19 9:19 ` Simon Horman
1 sibling, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-09-19 7:47 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Fri, Sep 7, 2018 at 8:58 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe CMTs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add CMT support
2018-09-19 7:47 ` Geert Uytterhoeven
@ 2018-09-19 9:19 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-09-19 9:19 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Wed, Sep 19, 2018 at 09:47:02AM +0200, Geert Uytterhoeven wrote:
> On Fri, Sep 7, 2018 at 8:58 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe CMTs in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-08-27 18:48 ` Sergei Shtylyov
` (6 preceding siblings ...)
(?)
@ 2018-09-07 20:14 ` Sergei Shtylyov
2018-09-10 9:23 ` Simon Horman
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-07 20:14 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe TMUs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
the CMT support).
The R8A779{7|8}0 TMU DT binding update have been just posted...
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
2 files changed, 132 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -316,6 +316,72 @@
resets = <&cpg 407>;
};
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -346,6 +346,72 @@
resets = <&cpg 407>;
};
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77980",
"renesas,rcar-gen3-i2c";
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-07 20:14 ` [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support Sergei Shtylyov
@ 2018-09-10 9:23 ` Simon Horman
2018-09-10 12:04 ` Sergei Shtylyov
0 siblings, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-09-10 9:23 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Fri, Sep 07, 2018 at 11:14:40PM +0300, Sergei Shtylyov wrote:
> Describe TMUs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
> the CMT support).
>
> The R8A779{7|8}0 TMU DT binding update have been just posted...
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
> 2 files changed, 132 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -316,6 +316,72 @@
> resets = <&cpg 407>;
> };
>
> + tmu0: timer@e61e0000 {
> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> + reg = <0 0xe61e0000 0 0x30>;
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 125>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 125>;
> + status = "disabled";
> + };
> +
> + tmu1: timer@e6fc0000 {
> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> + reg = <0 0xe6fc0000 0 0x30>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 124>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 124>;
> + status = "disabled";
> + };
> +
> + tmu2: timer@e6fd0000 {
> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> + reg = <0 0xe6fd0000 0 0x30>;
> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
Should GIC_SPI 306 also be here for TMU 2 channel 3?
And likewise for the r8a77980 (V3H)
The documentation seems inconsistent as I see this listed in the
interrupt controller documentation. But I do not see that channel
documented in the TMU documentation.
> + clocks = <&cpg CPG_MOD 123>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 123>;
> + status = "disabled";
> + };
> +
> + tmu3: timer@e6fe0000 {
> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> + reg = <0 0xe6fe0000 0 0x30>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 122>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 122>;
> + status = "disabled";
> + };
> +
> + tmu4: timer@ffc00000 {
> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> + reg = <0 0xffc00000 0 0x30>;
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
As per my note above, the documentation seems inconsistent here.
> + clocks = <&cpg CPG_MOD 121>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 121>;
> + status = "disabled";
> + };
> +
> i2c0: i2c@e6500000 {
> compatible = "renesas,i2c-r8a77970",
> "renesas,rcar-gen3-i2c";
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -346,6 +346,72 @@
> resets = <&cpg 407>;
> };
>
> + tmu0: timer@e61e0000 {
> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> + reg = <0 0xe61e0000 0 0x30>;
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 125>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 125>;
> + status = "disabled";
> + };
> +
> + tmu1: timer@e6fc0000 {
> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> + reg = <0 0xe6fc0000 0 0x30>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 124>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 124>;
> + status = "disabled";
> + };
> +
> + tmu2: timer@e6fd0000 {
> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> + reg = <0 0xe6fd0000 0 0x30>;
> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 123>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 123>;
> + status = "disabled";
> + };
> +
> + tmu3: timer@e6fe0000 {
> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> + reg = <0 0xe6fe0000 0 0x30>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 122>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 122>;
> + status = "disabled";
> + };
> +
> + tmu4: timer@ffc00000 {
> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> + reg = <0 0xffc00000 0 0x30>;
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 121>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 121>;
> + status = "disabled";
> + };
> +
> i2c0: i2c@e6500000 {
> compatible = "renesas,i2c-r8a77980",
> "renesas,rcar-gen3-i2c";
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-10 9:23 ` Simon Horman
@ 2018-09-10 12:04 ` Sergei Shtylyov
2018-09-11 13:36 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-10 12:04 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
Hello!
On 09/10/2018 12:23 PM, Simon Horman wrote:
>> Describe TMUs in the R8A779{7|8}0 device trees.
>>
>> Based on the original (and large) patches by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
>> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
>> the CMT support).
>>
>> The R8A779{7|8}0 TMU DT binding update have been just posted...
>>
>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
>> 2 files changed, 132 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> @@ -316,6 +316,72 @@
>> resets = <&cpg 407>;
>> };
>>
>> + tmu0: timer@e61e0000 {
>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>> + reg = <0 0xe61e0000 0 0x30>;
>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 125>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + resets = <&cpg 125>;
>> + status = "disabled";
>> + };
>> +
>> + tmu1: timer@e6fc0000 {
>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>> + reg = <0 0xe6fc0000 0 0x30>;
>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 124>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + resets = <&cpg 124>;
>> + status = "disabled";
>> + };
>> +
>> + tmu2: timer@e6fd0000 {
>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>> + reg = <0 0xe6fd0000 0 0x30>;
>> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>
> Should GIC_SPI 306 also be here for TMU 2 channel 3?>
> And likewise for the r8a77980 (V3H)
There are only 3 channels per TMU according to the beginning of the TMU chapter.
> The documentation seems inconsistent as I see this listed in the
> interrupt controller documentation. But I do not see that channel
> documented in the TMU documentation.
Right!
>> + clocks = <&cpg CPG_MOD 123>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + resets = <&cpg 123>;
>> + status = "disabled";
>> + };
>> +
>> + tmu3: timer@e6fe0000 {
>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>> + reg = <0 0xe6fe0000 0 0x30>;
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 122>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + resets = <&cpg 122>;
>> + status = "disabled";
>> + };
>> +
>> + tmu4: timer@ffc00000 {
>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>> + reg = <0 0xffc00000 0 0x30>;
>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
>
> Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
> the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
I don't think it should be pesent in either place, and I thought I had removed
the 4th IRQ from every node before posting... :-/
> As per my note above, the documentation seems inconsistent here.
Yes.
>> + clocks = <&cpg CPG_MOD 121>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + resets = <&cpg 121>;
>> + status = "disabled";
>> + };
>> +
>> i2c0: i2c@e6500000 {
>> compatible = "renesas,i2c-r8a77970",
>> "renesas,rcar-gen3-i2c";
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> @@ -346,6 +346,72 @@
>> resets = <&cpg 407>;
>> };
>>
>> + tmu0: timer@e61e0000 {
>> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
>> + reg = <0 0xe61e0000 0 0x30>;
>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 125>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 125>;
>> + status = "disabled";
>> + };
>> +
>> + tmu1: timer@e6fc0000 {
>> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
>> + reg = <0 0xe6fc0000 0 0x30>;
>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
Hadn't removed this apparently as well...
>> + clocks = <&cpg CPG_MOD 124>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 124>;
>> + status = "disabled";
>> + };
>> +
>> + tmu2: timer@e6fd0000 {
>> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
>> + reg = <0 0xe6fd0000 0 0x30>;
>> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 123>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 123>;
>> + status = "disabled";
>> + };
>> +
>> + tmu3: timer@e6fe0000 {
>> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
>> + reg = <0 0xe6fe0000 0 0x30>;
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 122>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 122>;
>> + status = "disabled";
>> + };
>> +
>> + tmu4: timer@ffc00000 {
>> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
>> + reg = <0 0xffc00000 0 0x30>;
>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 121>;
>> + clock-names = "fck";
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 121>;
>> + status = "disabled";
>> + };
>> +
>> i2c0: i2c@e6500000 {
>> compatible = "renesas,i2c-r8a77980",
>> "renesas,rcar-gen3-i2c";
>>
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-10 12:04 ` Sergei Shtylyov
@ 2018-09-11 13:36 ` Simon Horman
2018-09-11 14:12 ` Geert Uytterhoeven
2018-09-11 18:35 ` Sergei Shtylyov
0 siblings, 2 replies; 86+ messages in thread
From: Simon Horman @ 2018-09-11 13:36 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Mon, Sep 10, 2018 at 03:04:56PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 09/10/2018 12:23 PM, Simon Horman wrote:
>
> >> Describe TMUs in the R8A779{7|8}0 device trees.
> >>
> >> Based on the original (and large) patches by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
> >> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
> >> the CMT support).
> >>
> >> The R8A779{7|8}0 TMU DT binding update have been just posted...
> >>
> >> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
> >> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
> >> 2 files changed, 132 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >> @@ -316,6 +316,72 @@
> >> resets = <&cpg 407>;
> >> };
> >>
> >> + tmu0: timer@e61e0000 {
> >> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> >> + reg = <0 0xe61e0000 0 0x30>;
> >> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 125>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >> + resets = <&cpg 125>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu1: timer@e6fc0000 {
> >> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> >> + reg = <0 0xe6fc0000 0 0x30>;
> >> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 124>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >> + resets = <&cpg 124>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu2: timer@e6fd0000 {
> >> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> >> + reg = <0 0xe6fd0000 0 0x30>;
> >> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> >
> > Should GIC_SPI 306 also be here for TMU 2 channel 3?>
> > And likewise for the r8a77980 (V3H)
>
> There are only 3 channels per TMU according to the beginning of the TMU chapter.
>
> > The documentation seems inconsistent as I see this listed in the
> > interrupt controller documentation. But I do not see that channel
> > documented in the TMU documentation.
>
> Right!
>
> >> + clocks = <&cpg CPG_MOD 123>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >> + resets = <&cpg 123>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu3: timer@e6fe0000 {
> >> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> >> + reg = <0 0xe6fe0000 0 0x30>;
> >> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 122>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >> + resets = <&cpg 122>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu4: timer@ffc00000 {
> >> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> >> + reg = <0 0xffc00000 0 0x30>;
> >> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
> >
> > Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
> > the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
>
> I don't think it should be pesent in either place, and I thought I had removed
> the 4th IRQ from every node before posting... :-/
>
> > As per my note above, the documentation seems inconsistent here.
>
> Yes.
Lets go with no 4th IRQ anywhere :)
Could you send an updated patch?
>
> >> + clocks = <&cpg CPG_MOD 121>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >> + resets = <&cpg 121>;
> >> + status = "disabled";
> >> + };
> >> +
> >> i2c0: i2c@e6500000 {
> >> compatible = "renesas,i2c-r8a77970",
> >> "renesas,rcar-gen3-i2c";
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> @@ -346,6 +346,72 @@
> >> resets = <&cpg 407>;
> >> };
> >>
> >> + tmu0: timer@e61e0000 {
> >> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> >> + reg = <0 0xe61e0000 0 0x30>;
> >> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 125>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 125>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu1: timer@e6fc0000 {
> >> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> >> + reg = <0 0xe6fc0000 0 0x30>;
> >> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
>
> Hadn't removed this apparently as well...
>
> >> + clocks = <&cpg CPG_MOD 124>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 124>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu2: timer@e6fd0000 {
> >> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> >> + reg = <0 0xe6fd0000 0 0x30>;
> >> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 123>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 123>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu3: timer@e6fe0000 {
> >> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> >> + reg = <0 0xe6fe0000 0 0x30>;
> >> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 122>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 122>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + tmu4: timer@ffc00000 {
> >> + compatible = "renesas,tmu-r8a77980", "renesas,tmu";
> >> + reg = <0 0xffc00000 0 0x30>;
> >> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 121>;
> >> + clock-names = "fck";
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 121>;
> >> + status = "disabled";
> >> + };
> >> +
> >> i2c0: i2c@e6500000 {
> >> compatible = "renesas,i2c-r8a77980",
> >> "renesas,rcar-gen3-i2c";
> >>
>
> MBR, Sergei
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-11 13:36 ` Simon Horman
@ 2018-09-11 14:12 ` Geert Uytterhoeven
2018-09-11 18:35 ` Sergei Shtylyov
1 sibling, 0 replies; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-09-11 14:12 UTC (permalink / raw)
To: Simon Horman
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Tue, Sep 11, 2018 at 3:36 PM Simon Horman <horms@verge.net.au> wrote:
> On Mon, Sep 10, 2018 at 03:04:56PM +0300, Sergei Shtylyov wrote:
> > On 09/10/2018 12:23 PM, Simon Horman wrote:
> >
> > >> Describe TMUs in the R8A779{7|8}0 device trees.
> > >>
> > >> Based on the original (and large) patches by Vladimir Barinov.
> > >>
> > >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Lets go with no 4th IRQ anywhere :)
> Could you send an updated patch?
Please consider my comments on the bindings first:
https://patchwork.kernel.org/patch/10592517/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-11 13:36 ` Simon Horman
2018-09-11 14:12 ` Geert Uytterhoeven
@ 2018-09-11 18:35 ` Sergei Shtylyov
2018-09-12 9:39 ` Simon Horman
2018-09-13 20:14 ` Sergei Shtylyov
1 sibling, 2 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-11 18:35 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
Hello!
On 09/11/2018 04:36 PM, Simon Horman wrote:
>>>> Describe TMUs in the R8A779{7|8}0 device trees.
>>>>
>>>> Based on the original (and large) patches by Vladimir Barinov.
>>>>
>>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>
>>>> ---
>>>> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
>>>> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
>>>> the CMT support).
>>>>
>>>> The R8A779{7|8}0 TMU DT binding update have been just posted...
>>>>
>>>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
>>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
>>>> 2 files changed, 132 insertions(+)
>>>>
>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>> ===================================================================
>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>> @@ -316,6 +316,72 @@
>>>> resets = <&cpg 407>;
>>>> };
>>>>
>>>> + tmu0: timer@e61e0000 {
>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>> + reg = <0 0xe61e0000 0 0x30>;
>>>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&cpg CPG_MOD 125>;
>>>> + clock-names = "fck";
>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>> + resets = <&cpg 125>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + tmu1: timer@e6fc0000 {
>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>> + reg = <0 0xe6fc0000 0 0x30>;
>>>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&cpg CPG_MOD 124>;
>>>> + clock-names = "fck";
>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>> + resets = <&cpg 124>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + tmu2: timer@e6fd0000 {
>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>> + reg = <0 0xe6fd0000 0 0x30>;
>>>> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> Should GIC_SPI 306 also be here for TMU 2 channel 3?>
>>> And likewise for the r8a77980 (V3H)
>>
>> There are only 3 channels per TMU according to the beginning of the TMU chapter.
>>
>>> The documentation seems inconsistent as I see this listed in the
>>> interrupt controller documentation. But I do not see that channel
>>> documented in the TMU documentation.
>>
>> Right!
>>
>>>> + clocks = <&cpg CPG_MOD 123>;
>>>> + clock-names = "fck";
>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>> + resets = <&cpg 123>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + tmu3: timer@e6fe0000 {
>>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>>>> + reg = <0 0xe6fe0000 0 0x30>;
>>>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&cpg CPG_MOD 122>;
>>>> + clock-names = "fck";
>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>> + resets = <&cpg 122>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + tmu4: timer@ffc00000 {
>>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>>>> + reg = <0 0xffc00000 0 0x30>;
>>>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
>>> the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
>>
>> I don't think it should be pesent in either place, and I thought I had removed
>> the 4th IRQ from every node before posting... :-/
>>
>>> As per my note above, the documentation seems inconsistent here.
>>
>> Yes.
>
> Lets go with no 4th IRQ anywhere :)
After having studied the manual, 4th IRQ might have sometging to do with the input capture channel capability which uses an extra IRQ output.
> Could you send an updated patch?
Sure. I'll verify and repost.
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-11 18:35 ` Sergei Shtylyov
@ 2018-09-12 9:39 ` Simon Horman
2018-09-13 20:29 ` Sergei Shtylyov
2018-09-13 20:14 ` Sergei Shtylyov
1 sibling, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-09-12 9:39 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Geert Uytterhoeven
On Tue, Sep 11, 2018 at 09:35:50PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 09/11/2018 04:36 PM, Simon Horman wrote:
>
> >>>> Describe TMUs in the R8A779{7|8}0 device trees.
> >>>>
> >>>> Based on the original (and large) patches by Vladimir Barinov.
> >>>>
> >>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>>>
> >>>> ---
> >>>> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
> >>>> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
> >>>> the CMT support).
> >>>>
> >>>> The R8A779{7|8}0 TMU DT binding update have been just posted...
> >>>>
> >>>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
> >>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
> >>>> 2 files changed, 132 insertions(+)
> >>>>
> >>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >>>> ===================================================================
> >>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >>>> @@ -316,6 +316,72 @@
> >>>> resets = <&cpg 407>;
> >>>> };
> >>>>
> >>>> + tmu0: timer@e61e0000 {
> >>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> >>>> + reg = <0 0xe61e0000 0 0x30>;
> >>>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> >>>> + clocks = <&cpg CPG_MOD 125>;
> >>>> + clock-names = "fck";
> >>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >>>> + resets = <&cpg 125>;
> >>>> + status = "disabled";
> >>>> + };
> >>>> +
> >>>> + tmu1: timer@e6fc0000 {
> >>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> >>>> + reg = <0 0xe6fc0000 0 0x30>;
> >>>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> >>>> + clocks = <&cpg CPG_MOD 124>;
> >>>> + clock-names = "fck";
> >>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >>>> + resets = <&cpg 124>;
> >>>> + status = "disabled";
> >>>> + };
> >>>> +
> >>>> + tmu2: timer@e6fd0000 {
> >>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> >>>> + reg = <0 0xe6fd0000 0 0x30>;
> >>>> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> >>>
> >>> Should GIC_SPI 306 also be here for TMU 2 channel 3?>
> >>> And likewise for the r8a77980 (V3H)
> >>
> >> There are only 3 channels per TMU according to the beginning of the TMU chapter.
> >>
> >>> The documentation seems inconsistent as I see this listed in the
> >>> interrupt controller documentation. But I do not see that channel
> >>> documented in the TMU documentation.
> >>
> >> Right!
> >>
> >>>> + clocks = <&cpg CPG_MOD 123>;
> >>>> + clock-names = "fck";
> >>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >>>> + resets = <&cpg 123>;
> >>>> + status = "disabled";
> >>>> + };
> >>>> +
> >>>> + tmu3: timer@e6fe0000 {
> >>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> >>>> + reg = <0 0xe6fe0000 0 0x30>;
> >>>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> >>>> + clocks = <&cpg CPG_MOD 122>;
> >>>> + clock-names = "fck";
> >>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> >>>> + resets = <&cpg 122>;
> >>>> + status = "disabled";
> >>>> + };
> >>>> +
> >>>> + tmu4: timer@ffc00000 {
> >>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> >>>> + reg = <0 0xffc00000 0 0x30>;
> >>>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
> >>>
> >>> Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
> >>> the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
> >>
> >> I don't think it should be pesent in either place, and I thought I had removed
> >> the 4th IRQ from every node before posting... :-/
> >>
> >>> As per my note above, the documentation seems inconsistent here.
> >>
> >> Yes.
> >
> > Lets go with no 4th IRQ anywhere :)
>
> After having studied the manual, 4th IRQ might have sometging to do with the input capture channel capability which uses an extra IRQ output.
>
> > Could you send an updated patch?
>
> Sure. I'll verify and repost.
Geert seems to want us to consider this further.
As DT describes hardware it seems reasonable that we should describe the
TMU device fully in DT, including all IRQs. But it seems to me that the
documentation may not be consistent enough to judge how to do that.
So perhaps a way forwards is to seek clarification of the documentation?
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-12 9:39 ` Simon Horman
@ 2018-09-13 20:29 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-13 20:29 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Geert Uytterhoeven
On 09/12/2018 12:39 PM, Simon Horman wrote:
>>>>>> Describe TMUs in the R8A779{7|8}0 device trees.
>>>>>>
>>>>>> Based on the original (and large) patches by Vladimir Barinov.
>>>>>>
>>>>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>>>
>>>>>> ---
>>>>>> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
>>>>>> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
>>>>>> the CMT support).
>>>>>>
>>>>>> The R8A779{7|8}0 TMU DT binding update have been just posted...
>>>>>>
>>>>>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
>>>>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
>>>>>> 2 files changed, 132 insertions(+)
>>>>>>
>>>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>>>> ===================================================================
>>>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>>>> @@ -316,6 +316,72 @@
>>>>>> resets = <&cpg 407>;
>>>>>> };
>>>>>>
>>>>>> + tmu0: timer@e61e0000 {
>>>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>>>> + reg = <0 0xe61e0000 0 0x30>;
>>>>>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> + clocks = <&cpg CPG_MOD 125>;
>>>>>> + clock-names = "fck";
>>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>>> + resets = <&cpg 125>;
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> +
>>>>>> + tmu1: timer@e6fc0000 {
>>>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>>>> + reg = <0 0xe6fc0000 0 0x30>;
>>>>>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> + clocks = <&cpg CPG_MOD 124>;
>>>>>> + clock-names = "fck";
>>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>>> + resets = <&cpg 124>;
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> +
>>>>>> + tmu2: timer@e6fd0000 {
>>>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>>>> + reg = <0 0xe6fd0000 0 0x30>;
>>>>>> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>>>>
>>>>> Should GIC_SPI 306 also be here for TMU 2 channel 3?>
>>>>> And likewise for the r8a77980 (V3H)
>>>>
>>>> There are only 3 channels per TMU according to the beginning of the TMU chapter.
>>>>
>>>>> The documentation seems inconsistent as I see this listed in the
>>>>> interrupt controller documentation. But I do not see that channel
>>>>> documented in the TMU documentation.
>>>>
>>>> Right!
>>>>
>>>>>> + clocks = <&cpg CPG_MOD 123>;
>>>>>> + clock-names = "fck";
>>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>>> + resets = <&cpg 123>;
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> +
>>>>>> + tmu3: timer@e6fe0000 {
>>>>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>>>>>> + reg = <0 0xe6fe0000 0 0x30>;
>>>>>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> + clocks = <&cpg CPG_MOD 122>;
>>>>>> + clock-names = "fck";
>>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>>> + resets = <&cpg 122>;
>>>>>> + status = "disabled";
>>>>>> + };
>>>>>> +
>>>>>> + tmu4: timer@ffc00000 {
>>>>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>>>>>> + reg = <0 0xffc00000 0 0x30>;
>>>>>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
>>>>>
>>>>> Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
>>>>> the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
>>>>
>>>> I don't think it should be pesent in either place, and I thought I had removed
>>>> the 4th IRQ from every node before posting... :-/
>>>>
>>>>> As per my note above, the documentation seems inconsistent here.
>>>>
>>>> Yes.
>>>
>>> Lets go with no 4th IRQ anywhere :)
>>
>> After having studied the manual, 4th IRQ might have sometging to do with the input capture channel capability which uses an extra IRQ output.
>>
>>> Could you send an updated patch?
>>
>> Sure. I'll verify and repost.
>
> Geert seems to want us to consider this further.
Geert's main concern is about the different TMU hardware on the same SoC, like
the CMT types 0/1 (each described in its separate chapter). Somehow we don't have
the same situation with TMUs...
> As DT describes hardware it seems reasonable that we should describe the
> TMU device fully in DT, including all IRQs. But it seems to me that the
> documentation may not be consistent enough to judge how to do that.
> So perhaps a way forwards is to seek clarification of the documentation?
Yes, definitely won't hurts. :-)
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-11 18:35 ` Sergei Shtylyov
2018-09-12 9:39 ` Simon Horman
@ 2018-09-13 20:14 ` Sergei Shtylyov
1 sibling, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-13 20:14 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On 09/11/2018 09:35 PM, Sergei Shtylyov wrote:
>>>>> Describe TMUs in the R8A779{7|8}0 device trees.
>>>>>
>>>>> Based on the original (and large) patches by Vladimir Barinov.
>>>>>
>>>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>>
>>>>> ---
>>>>> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
>>>>> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
>>>>> the CMT support).
>>>>>
>>>>> The R8A779{7|8}0 TMU DT binding update have been just posted...
>>>>>
>>>>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++++++++++++++++++++++++++++++
>>>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++++++++++++++++++++++++++++++
>>>>> 2 files changed, 132 insertions(+)
>>>>>
>>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>>> ===================================================================
>>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>>> @@ -316,6 +316,72 @@
>>>>> resets = <&cpg 407>;
>>>>> };
>>>>>
>>>>> + tmu0: timer@e61e0000 {
>>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>>> + reg = <0 0xe61e0000 0 0x30>;
>>>>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + clocks = <&cpg CPG_MOD 125>;
>>>>> + clock-names = "fck";
>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>> + resets = <&cpg 125>;
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + tmu1: timer@e6fc0000 {
>>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>>> + reg = <0 0xe6fc0000 0 0x30>;
>>>>> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + clocks = <&cpg CPG_MOD 124>;
>>>>> + clock-names = "fck";
>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>> + resets = <&cpg 124>;
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + tmu2: timer@e6fd0000 {
>>>>> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
>>>>> + reg = <0 0xe6fd0000 0 0x30>;
>>>>> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>>>
>>>> Should GIC_SPI 306 also be here for TMU 2 channel 3?>
>>>> And likewise for the r8a77980 (V3H)
>>>
>>> There are only 3 channels per TMU according to the beginning of the TMU chapter.
>>>
>>>> The documentation seems inconsistent as I see this listed in the
>>>> interrupt controller documentation. But I do not see that channel
>>>> documented in the TMU documentation.
>>>
>>> Right!
>>>
>>>>> + clocks = <&cpg CPG_MOD 123>;
>>>>> + clock-names = "fck";
>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>> + resets = <&cpg 123>;
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + tmu3: timer@e6fe0000 {
>>>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>>>>> + reg = <0 0xe6fe0000 0 0x30>;
>>>>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + clocks = <&cpg CPG_MOD 122>;
>>>>> + clock-names = "fck";
>>>>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>>>>> + resets = <&cpg 122>;
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + tmu4: timer@ffc00000 {
>>>>> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
>>>>> + reg = <0 0xffc00000 0 0x30>;
>>>>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>>>>> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
>>>>
>>>> Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
>>>> the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
>>>
>>> I don't think it should be pesent in either place, and I thought I had removed
>>> the 4th IRQ from every node before posting... :-/
>>>
>>>> As per my note above, the documentation seems inconsistent here.
>>>
>>> Yes.
>>
>> Lets go with no 4th IRQ anywhere :)
>
> After having studied the manual, 4th IRQ might have sometging to do with the input capture channel capability which uses an extra IRQ output.
>
>> Could you send an updated patch?
>
> Sure. I'll verify and repost.
No, the extra IRQ doesn't match the existing of the input capture hardware.
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-08-27 18:48 ` Sergei Shtylyov
` (7 preceding siblings ...)
(?)
@ 2018-09-19 20:02 ` Sergei Shtylyov
2018-09-19 20:21 ` Sergei Shtylyov
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-19 20:02 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe TPU in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
Simon Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
2 files changed, 17 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -614,6 +614,14 @@
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77970", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x100>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ #pwm-cells = <4>;
+ status = "disabled";
+ };
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77970";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -666,6 +666,15 @@
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a7798", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x100>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #pwm-cells = <4>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef0000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-19 20:02 ` [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support Sergei Shtylyov
@ 2018-09-19 20:21 ` Sergei Shtylyov
2018-09-21 7:35 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-19 20:21 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
On 09/19/2018 11:02 PM, Sergei Shtylyov wrote:
> Describe TPU in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
> Simon Horman's 'renesas.git' repo.
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
> 2 files changed, 17 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -614,6 +614,14 @@
> status = "disabled";
> };
>
> + tpu: pwm@e6e80000 {
> + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
Oops, forgot to document the SoC specific binding...
> + reg = <0 0xe6e80000 0 0x100>;
> + clocks = <&cpg CPG_MOD 304>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + #pwm-cells = <4>;
> + status = "disabled";
> + };
>
> vin0: video@e6ef0000 {
> compatible = "renesas,vin-r8a77970";
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -666,6 +666,15 @@
> status = "disabled";
> };
>
> + tpu: pwm@e6e80000 {
> + compatible = "renesas,tpu-r8a7798", "renesas,tpu";
Same here. Plus forgot a zero at the end. :-/
> + reg = <0 0xe6e80000 0 0x100>;
> + clocks = <&cpg CPG_MOD 304>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + #pwm-cells = <4>;
> + status = "disabled";
> + };
> +
> vin0: video@e6ef0000 {
> compatible = "renesas,vin-r8a77980";
> reg = <0 0xe6ef0000 0 0x1000>;
>
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-19 20:21 ` Sergei Shtylyov
@ 2018-09-21 7:35 ` Simon Horman
2018-09-21 8:27 ` Sergei Shtylyov
0 siblings, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-09-21 7:35 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Wed, Sep 19, 2018 at 11:21:49PM +0300, Sergei Shtylyov wrote:
> On 09/19/2018 11:02 PM, Sergei Shtylyov wrote:
>
> > Describe TPU in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > ---
> > This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
> > Simon Horman's 'renesas.git' repo.
> >
> > arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
> > 2 files changed, 17 insertions(+)
> >
> > Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > ===================================================================
> > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > @@ -614,6 +614,14 @@
> > status = "disabled";
> > };
> >
> > + tpu: pwm@e6e80000 {
> > + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
>
> Oops, forgot to document the SoC specific binding...
I'm still not seeing the binding in my inbox.
Could you post it or point me to a link to it?
>
> > + reg = <0 0xe6e80000 0 0x100>;
This register range seems a little small.
>From my reading of the documentation 0x148 would be a more obvious choice.
Is the driver only accessing registers in in the 0x100 range for some
reason?
> > + clocks = <&cpg CPG_MOD 304>;
> > + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> > + #pwm-cells = <4>;
> > + status = "disabled";
> > + };
> >
> > vin0: video@e6ef0000 {
> > compatible = "renesas,vin-r8a77970";
> > Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > ===================================================================
> > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > @@ -666,6 +666,15 @@
> > status = "disabled";
> > };
> >
> > + tpu: pwm@e6e80000 {
> > + compatible = "renesas,tpu-r8a7798", "renesas,tpu";
>
> Same here. Plus forgot a zero at the end. :-/
>
> > + reg = <0 0xe6e80000 0 0x100>;
> > + clocks = <&cpg CPG_MOD 304>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + #pwm-cells = <4>;
> > + status = "disabled";
> > + };
> > +
> > vin0: video@e6ef0000 {
> > compatible = "renesas,vin-r8a77980";
> > reg = <0 0xe6ef0000 0 0x1000>;
> >
>
> MBR, Sergei
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-21 7:35 ` Simon Horman
@ 2018-09-21 8:27 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-21 8:27 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On 9/21/2018 10:35 AM, Simon Horman wrote:
>>> Describe TPU in the R8A779{7|8}0 device trees.
>>>
>>> Based on the original (and large) patches by Vladimir Barinov.
>>>
>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>
>>> ---
>>> This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
>>> Simon Horman's 'renesas.git' repo.
>>>
>>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
>>> 2 files changed, 17 insertions(+)
>>>
>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>> ===================================================================
>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>> @@ -614,6 +614,14 @@
>>> status = "disabled";
>>> };
>>>
>>> + tpu: pwm@e6e80000 {
>>> + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
>>
>> Oops, forgot to document the SoC specific binding...
>
> I'm still not seeing the binding in my inbox.
> Could you post it or point me to a link to it?
Because I still haven't posted it. It turned out the bindings doc needs
some fixing 1st... :-/
>>> + reg = <0 0xe6e80000 0 0x100>;
>
> This register range seems a little small.
> From my reading of the documentation 0x148 would be a more obvious choice.
Yeah, I've noticed that too -- will be fixed in v2.
> Is the driver only accessing registers in in the 0x100 range for some
> reason?
Yes, the registers beyond 0x100 are for the step motor control...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-08-27 18:48 ` Sergei Shtylyov
` (8 preceding siblings ...)
(?)
@ 2018-09-22 20:30 ` Sergei Shtylyov
2018-09-24 9:07 ` Simon Horman
2018-09-24 11:29 ` Geert Uytterhoeven
-1 siblings, 2 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-22 20:30 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe TPU in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180921-v4.19-rc4' branch of
Simon Horman's 'renesas.git' repo.
Changes in version 2:
- fixed up the size cells in the "regs" properties;
- fixed up the "#pwm-cells" properties;
- fixed up the R8A77980's "compatible" property.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
2 files changed, 17 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -614,6 +614,14 @@
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77970", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77970";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -666,6 +666,15 @@
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77980", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef0000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-22 20:30 ` [PATCH v2] " Sergei Shtylyov
@ 2018-09-24 9:07 ` Simon Horman
2018-09-24 14:44 ` Sergei Shtylyov
2018-09-24 11:29 ` Geert Uytterhoeven
1 sibling, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-09-24 9:07 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Sat, Sep 22, 2018 at 11:30:09PM +0300, Sergei Shtylyov wrote:
> Describe TPU in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks, this looks good but I'd like to see the binding update
before accepting this.
>
> ---
> This patch is against the 'renesas-devel-20180921-v4.19-rc4' branch of
> Simon Horman's 'renesas.git' repo.
>
> Changes in version 2:
> - fixed up the size cells in the "regs" properties;
> - fixed up the "#pwm-cells" properties;
> - fixed up the R8A77980's "compatible" property.
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 ++++++++
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
> 2 files changed, 17 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -614,6 +614,14 @@
> status = "disabled";
> };
>
> + tpu: pwm@e6e80000 {
> + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
> + reg = <0 0xe6e80000 0 0x148>;
> + clocks = <&cpg CPG_MOD 304>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
>
> vin0: video@e6ef0000 {
> compatible = "renesas,vin-r8a77970";
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -666,6 +666,15 @@
> status = "disabled";
> };
>
> + tpu: pwm@e6e80000 {
> + compatible = "renesas,tpu-r8a77980", "renesas,tpu";
> + reg = <0 0xe6e80000 0 0x148>;
> + clocks = <&cpg CPG_MOD 304>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> vin0: video@e6ef0000 {
> compatible = "renesas,vin-r8a77980";
> reg = <0 0xe6ef0000 0 0x1000>;
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-24 9:07 ` Simon Horman
@ 2018-09-24 14:44 ` Sergei Shtylyov
2018-09-24 15:32 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-24 14:44 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On 09/24/2018 12:07 PM, Simon Horman wrote:
>> Describe TPU in the R8A779{7|8}0 device trees.
>>
>> Based on the original (and large) patches by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Thanks, this looks good but I'd like to see the binding update
> before accepting this.
See it merged, you mean? Because the binding updates have been posted before v2,
and I'm seeing them in patchwork...
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-24 14:44 ` Sergei Shtylyov
@ 2018-09-24 15:32 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-09-24 15:32 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Mon, Sep 24, 2018 at 05:44:22PM +0300, Sergei Shtylyov wrote:
> On 09/24/2018 12:07 PM, Simon Horman wrote:
>
> >> Describe TPU in the R8A779{7|8}0 device trees.
> >>
> >> Based on the original (and large) patches by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > Thanks, this looks good but I'd like to see the binding update
> > before accepting this.
>
> See it merged, you mean? Because the binding updates have been posted
> before v2, and I'm seeing them in patchwork...
See them Acked.
Somehow I couldn't find them this morning but I see them now.
Could you respond to Geert's comment on this patch regarding interrupts?
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-22 20:30 ` [PATCH v2] " Sergei Shtylyov
2018-09-24 9:07 ` Simon Horman
@ 2018-09-24 11:29 ` Geert Uytterhoeven
2018-09-24 17:55 ` Sergei Shtylyov
1 sibling, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-09-24 11:29 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Sat, Sep 22, 2018 at 10:30 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe TPU in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -614,6 +614,14 @@
> status = "disabled";
> };
>
> + tpu: pwm@e6e80000 {
> + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
> + reg = <0 0xe6e80000 0 0x148>;
> + clocks = <&cpg CPG_MOD 304>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
While not used by the driver, I think it would be good to describe its interrupt
(SPI 135). Same for r8a77980.dtsi.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-24 11:29 ` Geert Uytterhoeven
@ 2018-09-24 17:55 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-24 17:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On 09/24/2018 02:29 PM, Geert Uytterhoeven wrote:
>> Describe TPU in the R8A779{7|8}0 device trees.
>>
>> Based on the original (and large) patches by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> @@ -614,6 +614,14 @@
>> status = "disabled";
>> };
>>
>> + tpu: pwm@e6e80000 {
>> + compatible = "renesas,tpu-r8a77970", "renesas,tpu";
>> + reg = <0 0xe6e80000 0 0x148>;
>> + clocks = <&cpg CPG_MOD 304>;
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + #pwm-cells = <3>;
>> + status = "disabled";
>> + };
>
> While not used by the driver, I think it would be good to describe its interrupt
> (SPI 135). Same for r8a77980.dtsi.
Gosh, you're right! Will re-spin. :-)
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v3] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-08-27 18:48 ` Sergei Shtylyov
` (9 preceding siblings ...)
(?)
@ 2018-09-24 18:33 ` Sergei Shtylyov
2018-09-24 19:36 ` Geert Uytterhoeven
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-24 18:33 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe TPU in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180924-v4.19-rc5' branch of
Simon Horman's 'renesas.git' repo.
Changes in version 3:
- added the "interrupts" and "resets" properties.
Changes in version 2:
- fixed up the size cells in the "regs" properties;
- fixed up the "#pwm-cells" properties;
- fixed up the R8A77980's "compatible" property.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 ++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 11 +++++++++++
2 files changed, 21 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -614,6 +614,16 @@
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77970", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77970";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -666,6 +666,17 @@
status = "disabled";
};
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77980", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef0000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v3] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-24 18:33 ` [PATCH v3] " Sergei Shtylyov
@ 2018-09-24 19:36 ` Geert Uytterhoeven
2018-09-25 7:42 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-09-24 19:36 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Mon, Sep 24, 2018 at 9:31 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe TPU in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v3] arm64: dts: renesas: r8a779{7|8}0: add TPU support
2018-09-24 19:36 ` Geert Uytterhoeven
@ 2018-09-25 7:42 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-09-25 7:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Mon, Sep 24, 2018 at 09:36:11PM +0200, Geert Uytterhoeven wrote:
> On Mon, Sep 24, 2018 at 9:31 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe TPU in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-08-27 18:48 ` Sergei Shtylyov
` (10 preceding siblings ...)
(?)
@ 2018-09-24 20:13 ` Sergei Shtylyov
2018-10-18 18:32 ` Sergei Shtylyov
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-09-24 20:13 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe TMUs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180924-v4.19-rc5' branch of
Simon Horman's 'renesas.git' repo.
Changes in version 2:
- fixed up the "compatible" prop in the R8A77970 TMU3/4 node;
- removed the 4th interrupt from the R8A77970 TMU4 node and the R8A77980 TMU1
node.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 65 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 65 ++++++++++++++++++++++++++++++
2 files changed, 130 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -316,6 +316,71 @@
resets = <&cpg 407>;
};
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -346,6 +346,71 @@
resets = <&cpg 407>;
};
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77980",
"renesas,rcar-gen3-i2c";
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-09-24 20:13 ` [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TMU support Sergei Shtylyov
@ 2018-10-18 18:32 ` Sergei Shtylyov
2018-10-19 13:43 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-18 18:32 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Hello!
On 09/24/2018 11:13 PM, Sergei Shtylyov wrote:
> Describe TMUs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180924-v4.19-rc5' branch of
> Simon Horman's 'renesas.git' repo.
>
> Changes in version 2:
> - fixed up the "compatible" prop in the R8A77970 TMU3/4 node;
> - removed the 4th interrupt from the R8A77970 TMU4 node and the R8A77980 TMU1
> node.
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 65 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 65 ++++++++++++++++++++++++++++++
> 2 files changed, 130 insertions(+)
I thought we had a consensus about TMU? Why this patch is marked as superseded
in the patchwork?
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add TMU support
2018-10-18 18:32 ` Sergei Shtylyov
@ 2018-10-19 13:43 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-19 13:43 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Thu, Oct 18, 2018 at 09:32:27PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 09/24/2018 11:13 PM, Sergei Shtylyov wrote:
>
> > Describe TMUs in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > ---
> > This patch is against the 'renesas-devel-20180924-v4.19-rc5' branch of
> > Simon Horman's 'renesas.git' repo.
> >
> > Changes in version 2:
> > - fixed up the "compatible" prop in the R8A77970 TMU3/4 node;
> > - removed the 4th interrupt from the R8A77970 TMU4 node and the R8A77980 TMU1
> > node.
> >
> > arch/arm64/boot/dts/renesas/r8a77970.dtsi | 65 ++++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 65 ++++++++++++++++++++++++++++++
> > 2 files changed, 130 insertions(+)
>
> I thought we had a consensus about TMU? Why this patch is marked as superseded
> in the patchwork?
Thanks, that looks like an error in my part.
I have applied this for v4.21.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a779{7|8}0: add PWM support
2018-08-27 18:48 ` Sergei Shtylyov
` (11 preceding siblings ...)
(?)
@ 2018-10-01 20:25 ` Sergei Shtylyov
2018-10-02 7:16 ` Geert Uytterhoeven
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-01 20:25 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe PWMs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181001-v4.19-rc6' branch of
Simon Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 50 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 50 ++++++++++++++++++++++++++++++
2 files changed, 100 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -543,6 +543,56 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif",
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -594,6 +594,56 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77980",
"renesas,rcar-gen3-scif",
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add PWM support
2018-10-01 20:25 ` [PATCH] arm64: dts: renesas: r8a779{7|8}0: add PWM support Sergei Shtylyov
@ 2018-10-02 7:16 ` Geert Uytterhoeven
2018-10-04 9:33 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-02 7:16 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Mon, Oct 1, 2018 at 10:26 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe PWMs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add PWM support
2018-10-02 7:16 ` Geert Uytterhoeven
@ 2018-10-04 9:33 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-04 9:33 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Tue, Oct 02, 2018 at 09:16:30AM +0200, Geert Uytterhoeven wrote:
> On Mon, Oct 1, 2018 at 10:26 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe PWMs in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.21.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-08-27 18:48 ` Sergei Shtylyov
` (12 preceding siblings ...)
(?)
@ 2018-10-05 19:25 ` Sergei Shtylyov
2018-10-05 19:33 ` Sergei Shtylyov
` (2 more replies)
-1 siblings, 3 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-05 19:25 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe THS/CIVM in the R8A77970 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
Horman's 'renesas.git' repo.
The thermal driver/bindings patches have been posted yesterday...
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -300,6 +300,19 @@
#power-domain-cells = <1>;
};
+ thermal: thermal@e6190000 {
+ compatible = "renesas,thermal-r8a77970";
+ reg = <0 0xe6190000 0 0x14
+ 0 0xe6190100 0 0x38>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>;
@@ -1033,6 +1046,25 @@
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-05 19:25 ` [PATCH] arm64: dts: renesas: r8a77970: add thermal support Sergei Shtylyov
@ 2018-10-05 19:33 ` Sergei Shtylyov
2018-10-08 7:55 ` Simon Horman
2018-10-08 8:12 ` Geert Uytterhoeven
2 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-05 19:33 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
On 10/05/2018 10:25 PM, Sergei Shtylyov wrote:
> Describe THS/CIVM in the R8A77970 device trees.
Damn, should be singular "tree"! :-/
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-05 19:25 ` [PATCH] arm64: dts: renesas: r8a77970: add thermal support Sergei Shtylyov
2018-10-05 19:33 ` Sergei Shtylyov
@ 2018-10-08 7:55 ` Simon Horman
2018-10-08 8:12 ` Geert Uytterhoeven
2 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-08 7:55 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Yoshihiro Kaneko
On Fri, Oct 05, 2018 at 10:25:47PM +0300, Sergei Shtylyov wrote:
> Describe THS/CIVM in the R8A77970 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
> Horman's 'renesas.git' repo.
>
> The thermal driver/bindings patches have been posted yesterday...
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -300,6 +300,19 @@
> #power-domain-cells = <1>;
> };
>
> + thermal: thermal@e6190000 {
> + compatible = "renesas,thermal-r8a77970";
> + reg = <0 0xe6190000 0 0x14
What is the motivation for 0x14, to me 0x10 seems like a more natural size
for the register window.
Otherwise the patch looks good to me.
> + 0 0xe6190100 0 0x38>;
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 522>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 522>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> intc_ex: interrupt-controller@e61c0000 {
> compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
> #interrupt-cells = <2>;
> @@ -1033,6 +1046,25 @@
> };
> };
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&thermal>;
> +
> + trips {
> + cpu-crit {
> + temperature = <120000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + };
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-05 19:25 ` [PATCH] arm64: dts: renesas: r8a77970: add thermal support Sergei Shtylyov
2018-10-05 19:33 ` Sergei Shtylyov
2018-10-08 7:55 ` Simon Horman
@ 2018-10-08 8:12 ` Geert Uytterhoeven
2018-10-08 16:35 ` Sergei Shtylyov
2 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-08 8:12 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hi Sergei,
On Fri, Oct 5, 2018 at 9:26 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe THS/CIVM in the R8A77970 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
> Horman's 'renesas.git' repo.
>
> The thermal driver/bindings patches have been posted yesterday...
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -300,6 +300,19 @@
> #power-domain-cells = <1>;
> };
>
> + thermal: thermal@e6190000 {
> + compatible = "renesas,thermal-r8a77970";
> + reg = <0 0xe6190000 0 0x14
0x14 was appropriate for R-Mobile APE6...
> + 0 0xe6190100 0 0x38>;
What about the CIVM status register? DT describes hardware, not driver
limitations.
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 522>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 522>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> intc_ex: interrupt-controller@e61c0000 {
> compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
> #interrupt-cells = <2>;
The rest looks good to me, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-08 8:12 ` Geert Uytterhoeven
@ 2018-10-08 16:35 ` Sergei Shtylyov
2018-10-08 16:40 ` Geert Uytterhoeven
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-08 16:35 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On 10/08/2018 11:12 AM, Geert Uytterhoeven wrote:
>> Describe THS/CIVM in the R8A77970 device trees.
>>
>> Based on the original (and large) patches by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
>> Horman's 'renesas.git' repo.
>>
>> The thermal driver/bindings patches have been posted yesterday...
>>
>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> @@ -300,6 +300,19 @@
>> #power-domain-cells = <1>;
>> };
>>
>> + thermal: thermal@e6190000 {
>> + compatible = "renesas,thermal-r8a77970";
>> + reg = <0 0xe6190000 0 0x14
>
> 0x14 was appropriate for R-Mobile APE6...
Copy&paste is to blame here, I guess... I'll fix to 0x10.
>
>> + 0 0xe6190100 0 0x38>;
>
> What about the CIVM status register? DT describes hardware, not driver
> limitations.
I wasn't sure whether to put it into a separate "reg" tuple (which would confuse
the driver) or not. After looking into the manual again, I'm going to extend the
2nd "reg" tuple...
>> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 522>;
>> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
>> + resets = <&cpg 522>;
>> + #thermal-sensor-cells = <0>;
>> + };
>> +
>> intc_ex: interrupt-controller@e61c0000 {
>> compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
>> #interrupt-cells = <2>;
>
> The rest looks good to me, so with the above fixed:
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks :-)
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-08 16:35 ` Sergei Shtylyov
@ 2018-10-08 16:40 ` Geert Uytterhoeven
2018-10-08 18:04 ` Sergei Shtylyov
0 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-08 16:40 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hi Sergei,
On Mon, Oct 8, 2018 at 6:35 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 10/08/2018 11:12 AM, Geert Uytterhoeven wrote:
> >> Describe THS/CIVM in the R8A77970 device trees.
> >> Based on the original (and large) patches by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
> >> Horman's 'renesas.git' repo.
> >>
> >> The thermal driver/bindings patches have been posted yesterday...
> >>
> >> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
> >> 1 file changed, 32 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> >> @@ -300,6 +300,19 @@
> >> #power-domain-cells = <1>;
> >> };
> >>
> >> + thermal: thermal@e6190000 {
> >> + compatible = "renesas,thermal-r8a77970";
> >> + reg = <0 0xe6190000 0 0x14
> >
> > 0x14 was appropriate for R-Mobile APE6...
>
> Copy&paste is to blame here, I guess... I'll fix to 0x10.
OK.
> >> + 0 0xe6190100 0 0x38>;
> >
> > What about the CIVM status register? DT describes hardware, not driver
> > limitations.
>
> I wasn't sure whether to put it into a separate "reg" tuple (which would confuse
> the driver) or not. After looking into the manual again, I'm going to extend the
> 2nd "reg" tuple...
The CIVM Status Register indicates the chip internal voltage.
As such it's not a per-channel property, and IMHO doesn't belong in the second
tuple (e.g. R-Mobile APE6 has 3 channels).
Perhaps extending the bindings to handle more reg tuples, possibly using
reg-names?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-08 16:40 ` Geert Uytterhoeven
@ 2018-10-08 18:04 ` Sergei Shtylyov
2018-10-10 7:10 ` Geert Uytterhoeven
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-08 18:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hello!
On 10/08/2018 07:40 PM, Geert Uytterhoeven wrote:
>>>> Describe THS/CIVM in the R8A77970 device trees.
>>>> Based on the original (and large) patches by Vladimir Barinov.
>>>>
>>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>
>>>> ---
>>>> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
>>>> Horman's 'renesas.git' repo.
>>>>
>>>> The thermal driver/bindings patches have been posted yesterday...
>>>>
>>>> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
>>>> 1 file changed, 32 insertions(+)
>>>>
>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>> ===================================================================
>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>>>> @@ -300,6 +300,19 @@
>>>> #power-domain-cells = <1>;
>>>> };
>>>>
>>>> + thermal: thermal@e6190000 {
>>>> + compatible = "renesas,thermal-r8a77970";
>>>> + reg = <0 0xe6190000 0 0x14
>>>
>>> 0x14 was appropriate for R-Mobile APE6...
>>
>> Copy&paste is to blame here, I guess... I'll fix to 0x10.
>
> OK.
>
>>>> + 0 0xe6190100 0 0x38>;
>>>
>>> What about the CIVM status register? DT describes hardware, not driver
>>> limitations.
>>
>> I wasn't sure whether to put it into a separate "reg" tuple (which would confuse
>> the driver) or not. After looking into the manual again, I'm going to extend the
>> 2nd "reg" tuple...
>
> The CIVM Status Register indicates the chip internal voltage.
> As such it's not a per-channel property, and IMHO doesn't belong in the second
> tuple
I was looking a the block diagrams (both in the chapters 10A and 10B) and I got a totally different impression...
> (e.g. R-Mobile APE6 has 3 channels).
The driver handles that alright. It's the adding the CIVM as a separate tuple
that would break it.
> Perhaps extending the bindings to handle more reg tuples, possibly using
> reg-names?
You mean teaching the driver about one more kind of "reg" tuples? I would like
to avoid that of course -- due to the need to still handle the old DTs as well...
> Gr{oetje,eeting}s,
>
> Geert
>
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77970: add thermal support
2018-10-08 18:04 ` Sergei Shtylyov
@ 2018-10-10 7:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-10 7:10 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hi Sergei,
On Mon, Oct 8, 2018 at 8:04 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 10/08/2018 07:40 PM, Geert Uytterhoeven wrote:
> >>>> Describe THS/CIVM in the R8A77970 device trees.
> >>>> Based on the original (and large) patches by Vladimir Barinov.
> >>>> + 0 0xe6190100 0 0x38>;
> >>>
> >>> What about the CIVM status register? DT describes hardware, not driver
> >>> limitations.
> >>
> >> I wasn't sure whether to put it into a separate "reg" tuple (which would confuse
> >> the driver) or not. After looking into the manual again, I'm going to extend the
> >> 2nd "reg" tuple...
> >
> > The CIVM Status Register indicates the chip internal voltage.
> > As such it's not a per-channel property, and IMHO doesn't belong in the second
> > tuple
>
> I was looking a the block diagrams (both in the chapters 10A and 10B) and I got a totally different impression...
I stand corrected. So extending the second reg block is fine.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add thermal support
2018-08-27 18:48 ` Sergei Shtylyov
` (13 preceding siblings ...)
(?)
@ 2018-10-09 19:37 ` Sergei Shtylyov
2018-10-10 8:36 ` Simon Horman
2018-10-10 10:57 ` Niklas Söderlund
-1 siblings, 2 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-09 19:37 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe THS/CIVM in the R8A77980 device trees.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
Horman's 'renesas.git' repo.
The thermal driver/bindings patches have been just posted...
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -330,6 +330,19 @@
#power-domain-cells = <1>;
};
+ thermal: thermal@e6198000 {
+ compatible = "renesas,r8a77980-thermal";
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <1>;
+ };
+
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
#interrupt-cells = <2>;
@@ -1404,6 +1417,31 @@
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ cpu-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+
+ sensor2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&thermal 1>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add thermal support
2018-10-09 19:37 ` [PATCH] arm64: dts: renesas: r8a77980: " Sergei Shtylyov
@ 2018-10-10 8:36 ` Simon Horman
2018-10-10 10:47 ` Sergei Shtylyov
2018-10-10 10:57 ` Niklas Söderlund
1 sibling, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-10-10 8:36 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Niklas Söderlund
[+ Niklas]
On Tue, Oct 09, 2018 at 10:37:47PM +0300, Sergei Shtylyov wrote:
> Describe THS/CIVM in the R8A77980 device trees.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
> Horman's 'renesas.git' repo.
>
> The thermal driver/bindings patches have been just posted...
>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 38 ++++++++++++++++++++++++++++++
Thanks Sergei, one minor nit from me below.
Niklas, I'd value your review of this patch.
> 1 file changed, 38 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -330,6 +330,19 @@
> #power-domain-cells = <1>;
> };
>
> + thermal: thermal@e6198000 {
"tsc:" would be consistent with other R-Car Gen 3 dtsi that
describe this device.
> + compatible = "renesas,r8a77980-thermal";
> + reg = <0 0xe6198000 0 0x100>,
> + <0 0xe61a0000 0 0x100>;
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 522>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 522>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> intc_ex: interrupt-controller@e61c0000 {
> compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
> #interrupt-cells = <2>;
> @@ -1404,6 +1417,31 @@
> };
> };
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&thermal 0>;
> +
> + trips {
> + cpu-crit {
> + temperature = <120000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + };
> + };
> +
> + sensor2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&thermal 1>;
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add thermal support
2018-10-10 8:36 ` Simon Horman
@ 2018-10-10 10:47 ` Sergei Shtylyov
2018-10-10 10:52 ` Niklas Söderlund
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-10 10:47 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Niklas Söderlund
On 10/10/2018 11:36 AM, Simon Horman wrote:
>> Describe THS/CIVM in the R8A77980 device trees.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
>> Horman's 'renesas.git' repo.
>>
>> The thermal driver/bindings patches have been just posted...
>>
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 38 ++++++++++++++++++++++++++++++
>
> Thanks Sergei, one minor nit from me below.
>
> Niklas, I'd value your review of this patch.
>
>> 1 file changed, 38 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> @@ -330,6 +330,19 @@
>> #power-domain-cells = <1>;
>> };
>>
>> + thermal: thermal@e6198000 {
>
> "tsc:" would be consistent with other R-Car Gen 3 dtsi that
> describe this device.
There's no consistency even among those: R8A779{5|6}0 use "tsc:",
R8A77995 uses "thermal:"... :-)
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add thermal support
2018-10-10 10:47 ` Sergei Shtylyov
@ 2018-10-10 10:52 ` Niklas Söderlund
0 siblings, 0 replies; 86+ messages in thread
From: Niklas Söderlund @ 2018-10-10 10:52 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, linux-renesas-soc, devicetree,
Magnus Damm, Mark Rutland
Hi Sergei,
On 2018-10-10 13:47:36 +0300, Sergei Shtylyov wrote:
> On 10/10/2018 11:36 AM, Simon Horman wrote:
>
> >> Describe THS/CIVM in the R8A77980 device trees.
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
> >> Horman's 'renesas.git' repo.
> >>
> >> The thermal driver/bindings patches have been just posted...
> >>
> >> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 38 ++++++++++++++++++++++++++++++
> >
> > Thanks Sergei, one minor nit from me below.
> >
> > Niklas, I'd value your review of this patch.
> >
> >> 1 file changed, 38 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> @@ -330,6 +330,19 @@
> >> #power-domain-cells = <1>;
> >> };
> >>
> >> + thermal: thermal@e6198000 {
> >
> > "tsc:" would be consistent with other R-Car Gen 3 dtsi that
> > describe this device.
>
> There's no consistency even among those: R8A779{5|6}0 use "tsc:",
> R8A77995 uses "thermal:"... :-)
D3 (R8A77995) uses the Gen2 thermal driver while V3H uses Gen3 thermal
driver, so there is some consistency and I think we should aim to make
it as consistent as possible :-)
>
> [...]
>
> MBR, Sergei
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add thermal support
2018-10-09 19:37 ` [PATCH] arm64: dts: renesas: r8a77980: " Sergei Shtylyov
2018-10-10 8:36 ` Simon Horman
@ 2018-10-10 10:57 ` Niklas Söderlund
2018-10-10 11:20 ` Sergei Shtylyov
1 sibling, 1 reply; 86+ messages in thread
From: Niklas Söderlund @ 2018-10-10 10:57 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, linux-renesas-soc, devicetree,
Magnus Damm, Mark Rutland
Hi Sergei,
Thanks for your work.
On 2018-10-09 22:37:47 +0300, Sergei Shtylyov wrote:
> Describe THS/CIVM in the R8A77980 device trees.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
> Horman's 'renesas.git' repo.
>
> The thermal driver/bindings patches have been just posted...
>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 38 ++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -330,6 +330,19 @@
> #power-domain-cells = <1>;
> };
>
> + thermal: thermal@e6198000 {
As Simon points out other Gen3 thermal nodes use "tsc:" not "thermal:".
> + compatible = "renesas,r8a77980-thermal";
> + reg = <0 0xe6198000 0 0x100>,
> + <0 0xe61a0000 0 0x100>;
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 522>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 522>;
> + #thermal-sensor-cells = <1>;
Missing status = "okay" or am I missing something?
> + };
> +
> intc_ex: interrupt-controller@e61c0000 {
> compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
> #interrupt-cells = <2>;
> @@ -1404,6 +1417,31 @@
> };
> };
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&thermal 0>;
> +
> + trips {
> + cpu-crit {
> + temperature = <120000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + };
> + };
> +
> + sensor2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&thermal 1>;
> + };
> + };
The thermal-zones node uses the Gen2 labels and I think this should be
updated to be as consistent as possible with other Gen3 users. For extra
points expand this could be expanded to also include the cooling-maps
but could also happen in a separate patch if cooling-devices are not yet
defined :-)
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add thermal support
2018-10-10 10:57 ` Niklas Söderlund
@ 2018-10-10 11:20 ` Sergei Shtylyov
0 siblings, 0 replies; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-10 11:20 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Simon Horman, Rob Herring, linux-renesas-soc, devicetree,
Magnus Damm, Mark Rutland
On 10/10/2018 01:57 PM, Niklas Söderlund wrote:
>> Describe THS/CIVM in the R8A77980 device trees.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
>> Horman's 'renesas.git' repo.
>>
>> The thermal driver/bindings patches have been just posted...
>>
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 38 ++++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> @@ -330,6 +330,19 @@
>> #power-domain-cells = <1>;
>> };
>>
>> + thermal: thermal@e6198000 {
>
> As Simon points out other Gen3 thermal nodes use "tsc:" not "thermal:".
Ah, indeed. However the manual calls this device THS/CIVM regardless of
the version.
>> + compatible = "renesas,r8a77980-thermal";
>> + reg = <0 0xe6198000 0 0x100>,
>> + <0 0xe61a0000 0 0x100>;
>> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 522>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 522>;
>> + #thermal-sensor-cells = <1>;
>
> Missing status = "okay" or am I missing something?
Yes, 'status = "okay"' can be omitted with the same effect.
>> + };
>> +
>> intc_ex: interrupt-controller@e61c0000 {
>> compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
>> #interrupt-cells = <2>;
>> @@ -1404,6 +1417,31 @@
>> };
>> };
>>
>> + thermal-zones {
>> + cpu-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> + thermal-sensors = <&thermal 0>;
>> +
>> + trips {
>> + cpu-crit {
>> + temperature = <120000>;
>> + hysteresis = <2000>;
>> + type = "critical";
>> + };
>> + };
>> +
>> + cooling-maps {
>> + };
>> + };
>> +
>> + sensor2-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <1000>;
>> + thermal-sensors = <&thermal 1>;
>> + };
>> + };
>
> The thermal-zones node uses the Gen2 labels
I don't see it using any labels at all...
> and I think this should be
> updated to be as consistent as possible with other Gen3 users. For extra
OK, I forgot to look at the thermal zones on R8A779{5|6}0...
> points expand this could be expanded to also include the cooling-maps
> but could also happen in a separate patch if cooling-devices are not yet
> defined :-)
I'll look into that...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
2018-08-27 18:48 ` Sergei Shtylyov
` (14 preceding siblings ...)
(?)
@ 2018-10-09 19:47 ` Sergei Shtylyov
2018-10-10 7:12 ` Geert Uytterhoeven
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-09 19:47 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe THS/CIVM in the R8A77970 device tree.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
Horman's 'renesas.git' repo.
Changed in version 2:
- fix the "reg" prop in the thermal device node;
- fixed wrong plural in the patch description.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 ++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -300,6 +300,19 @@
#power-domain-cells = <1>;
};
+ thermal: thermal@e6190000 {
+ compatible = "renesas,thermal-r8a77970";
+ reg = <0 0xe6190000 0 0x10
+ 0 0xe6190100 0 0x120>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>;
@@ -1033,6 +1046,25 @@
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
2018-10-09 19:47 ` [PATCH v2] arm64: dts: renesas: r8a77970: " Sergei Shtylyov
@ 2018-10-10 7:12 ` Geert Uytterhoeven
2018-10-12 11:21 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-10 7:12 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Tue, Oct 9, 2018 at 9:50 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe THS/CIVM in the R8A77970 device tree.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
> Horman's 'renesas.git' repo.
>
> Changed in version 2:
> - fix the "reg" prop in the thermal device node;
> - fixed wrong plural in the patch description.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
2018-10-10 7:12 ` Geert Uytterhoeven
@ 2018-10-12 11:21 ` Simon Horman
2018-10-12 14:36 ` Sergei Shtylyov
0 siblings, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-10-12 11:21 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Wed, Oct 10, 2018 at 09:12:54AM +0200, Geert Uytterhoeven wrote:
> On Tue, Oct 9, 2018 at 9:50 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe THS/CIVM in the R8A77970 device tree.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > ---
> > This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
> > Horman's 'renesas.git' repo.
> >
> > Changed in version 2:
> > - fix the "reg" prop in the thermal device node;
> > - fixed wrong plural in the patch description.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.21.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
2018-10-12 11:21 ` Simon Horman
@ 2018-10-12 14:36 ` Sergei Shtylyov
2018-10-15 15:43 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-12 14:36 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven
Cc: Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On 10/12/2018 02:21 PM, Simon Horman wrote:
>>> Describe THS/CIVM in the R8A77970 device tree.
>>>
>>> Based on the original (and large) patches by Vladimir Barinov.
>>>
>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>
>>> ---
>>> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
>>> Horman's 'renesas.git' repo.
>>>
>>> Changed in version 2:
>>> - fix the "reg" prop in the thermal device node;
>>> - fixed wrong plural in the patch description.
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks, applied for v4.21.
Not seeing any updates -- forgot to push?
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2] arm64: dts: renesas: r8a77970: add thermal support
2018-10-12 14:36 ` Sergei Shtylyov
@ 2018-10-15 15:43 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-15 15:43 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Geert Uytterhoeven, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Fri, Oct 12, 2018 at 05:36:55PM +0300, Sergei Shtylyov wrote:
> On 10/12/2018 02:21 PM, Simon Horman wrote:
>
> >>> Describe THS/CIVM in the R8A77970 device tree.
> >>>
> >>> Based on the original (and large) patches by Vladimir Barinov.
> >>>
> >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>>
> >>> ---
> >>> This patch is against the 'renesas-devel-20181004-v4.19-rc6' tag of Simon
> >>> Horman's 'renesas.git' repo.
> >>>
> >>> Changed in version 2:
> >>> - fix the "reg" prop in the thermal device node;
> >>> - fixed wrong plural in the patch description.
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Thanks, applied for v4.21.
>
> Not seeing any updates -- forgot to push?
Yes, sorry. I noticed that this morning and pushed
renesas-devel-20181012-v4.19-rc7.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2] arm64: dts: renesas: r8a77980: add thermal support
2018-08-27 18:48 ` Sergei Shtylyov
` (15 preceding siblings ...)
(?)
@ 2018-10-10 19:18 ` Sergei Shtylyov
2018-10-10 22:11 ` Niklas Söderlund
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-10 19:18 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe THS/CIVM in the R8A77980 device trees.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
Horman's 'renesas.git' repo.
Changes in version 2:
- renamed the thermal device node label;
- renamed the thermal zone nodes;
- added the passive trip point in the 1st thermal zone and the passive and
critical trip points in the 2nd thermal zone;
- changed the "hysteresis" prop in the critical trip point;
- removed the empty "cooling-maps" node from the 1st thermal zone.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 53 ++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -330,6 +330,19 @@
#power-domain-cells = <1>;
};
+ tsc: thermal@e6198000 {
+ compatible = "renesas,r8a77980-thermal";
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <1>;
+ };
+
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
#interrupt-cells = <2>;
@@ -1404,6 +1417,46 @@
};
};
+ thermal-zones {
+ thermal-sensor-1 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 0>;
+
+ trips {
+ sensor1-passive {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ sensor1-critical {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ thermal-sensor-2 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 1>;
+
+ trips {
+ sensor2-passive {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ sensor2-critical {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a77980: add thermal support
2018-10-10 19:18 ` [PATCH v2] arm64: dts: renesas: r8a77980: " Sergei Shtylyov
@ 2018-10-10 22:11 ` Niklas Söderlund
2018-10-11 7:02 ` Geert Uytterhoeven
0 siblings, 1 reply; 86+ messages in thread
From: Niklas Söderlund @ 2018-10-10 22:11 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, linux-renesas-soc, devicetree,
Magnus Damm, Mark Rutland
Hi Sergei,
Thanks for keep working on this patch.
On 2018-10-10 22:18:11 +0300, Sergei Shtylyov wrote:
> Describe THS/CIVM in the R8A77980 device trees.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181008-v4.19-rc7' tag of Simon
> Horman's 'renesas.git' repo.
>
> Changes in version 2:
> - renamed the thermal device node label;
> - renamed the thermal zone nodes;
> - added the passive trip point in the 1st thermal zone and the passive and
> critical trip points in the 2nd thermal zone;
> - changed the "hysteresis" prop in the critical trip point;
> - removed the empty "cooling-maps" node from the 1st thermal zone.
>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 53 ++++++++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -330,6 +330,19 @@
> #power-domain-cells = <1>;
> };
>
> + tsc: thermal@e6198000 {
> + compatible = "renesas,r8a77980-thermal";
> + reg = <0 0xe6198000 0 0x100>,
> + <0 0xe61a0000 0 0x100>;
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 522>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 522>;
> + #thermal-sensor-cells = <1>;
The status property is missing but as you told me in v1 it should not
matter. I will leave it for Simon to decide if he wants it to keep it
consistent with other SoC or if we should remove it from the other dtsi
files. In any case with or without the status property.
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> + };
> +
> intc_ex: interrupt-controller@e61c0000 {
> compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
> #interrupt-cells = <2>;
> @@ -1404,6 +1417,46 @@
> };
> };
>
> + thermal-zones {
> + thermal-sensor-1 {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&tsc 0>;
> +
> + trips {
> + sensor1-passive {
> + temperature = <95000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
> + sensor1-critical {
> + temperature = <120000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + thermal-sensor-2 {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&tsc 1>;
> +
> + trips {
> + sensor2-passive {
> + temperature = <95000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
> + sensor2-critical {
> + temperature = <120000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a77980: add thermal support
2018-10-10 22:11 ` Niklas Söderlund
@ 2018-10-11 7:02 ` Geert Uytterhoeven
2018-10-11 7:30 ` Niklas Söderlund
0 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-11 7:02 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Sergei Shtylyov, Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hi Niklas,
On Thu, Oct 11, 2018 at 12:11 AM Niklas Söderlund
<niklas.soderlund@ragnatech.se> wrote:
> On 2018-10-10 22:18:11 +0300, Sergei Shtylyov wrote:
> > Describe THS/CIVM in the R8A77980 device trees.
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > @@ -330,6 +330,19 @@
> > #power-domain-cells = <1>;
> > };
> >
> > + tsc: thermal@e6198000 {
> > + compatible = "renesas,r8a77980-thermal";
> > + reg = <0 0xe6198000 0 0x100>,
> > + <0 0xe61a0000 0 0x100>;
> > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 522>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 522>;
> > + #thermal-sensor-cells = <1>;
>
> The status property is missing but as you told me in v1 it should not
> matter. I will leave it for Simon to decide if he wants it to keep it
> consistent with other SoC or if we should remove it from the other dtsi
> files. In any case with or without the status property.
Forgot to review commit c79661eb5060e2bf ("arm64: dts: renesas: Remove
unneeded status from thermal nodes")? ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a77980: add thermal support
2018-10-11 7:02 ` Geert Uytterhoeven
@ 2018-10-11 7:30 ` Niklas Söderlund
2018-10-12 11:23 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Niklas Söderlund @ 2018-10-11 7:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Simon Horman, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hi Geert,
On 2018-10-11 09:02:22 +0200, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Thu, Oct 11, 2018 at 12:11 AM Niklas S�derlund
> <niklas.soderlund@ragnatech.se> wrote:
> > On 2018-10-10 22:18:11 +0300, Sergei Shtylyov wrote:
> > > Describe THS/CIVM in the R8A77980 device trees.
> > >
> > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> > > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > > @@ -330,6 +330,19 @@
> > > #power-domain-cells = <1>;
> > > };
> > >
> > > + tsc: thermal@e6198000 {
> > > + compatible = "renesas,r8a77980-thermal";
> > > + reg = <0 0xe6198000 0 0x100>,
> > > + <0 0xe61a0000 0 0x100>;
> > > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 522>;
> > > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > > + resets = <&cpg 522>;
> > > + #thermal-sensor-cells = <1>;
> >
> > The status property is missing but as you told me in v1 it should not
> > matter. I will leave it for Simon to decide if he wants it to keep it
> > consistent with other SoC or if we should remove it from the other dtsi
> > files. In any case with or without the status property.
>
> Forgot to review commit c79661eb5060e2bf ("arm64: dts: renesas: Remove
> unneeded status from thermal nodes")? ;-)
Not only that also reviewing using the context from v4.19-rc1 which of
course is not correct for dtsi patches, thanks for enlightening me :-)
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a77980: add thermal support
2018-10-11 7:30 ` Niklas Söderlund
@ 2018-10-12 11:23 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-12 11:23 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Thu, Oct 11, 2018 at 09:30:02AM +0200, Niklas Söderlund wrote:
> Hi Geert,
>
> On 2018-10-11 09:02:22 +0200, Geert Uytterhoeven wrote:
> > Hi Niklas,
> >
> > On Thu, Oct 11, 2018 at 12:11 AM Niklas Söderlund
> > <niklas.soderlund@ragnatech.se> wrote:
> > > On 2018-10-10 22:18:11 +0300, Sergei Shtylyov wrote:
> > > > Describe THS/CIVM in the R8A77980 device trees.
> > > >
> > > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > > > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > > > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > > > @@ -330,6 +330,19 @@
> > > > #power-domain-cells = <1>;
> > > > };
> > > >
> > > > + tsc: thermal@e6198000 {
> > > > + compatible = "renesas,r8a77980-thermal";
> > > > + reg = <0 0xe6198000 0 0x100>,
> > > > + <0 0xe61a0000 0 0x100>;
> > > > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&cpg CPG_MOD 522>;
> > > > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > > > + resets = <&cpg 522>;
> > > > + #thermal-sensor-cells = <1>;
> > >
> > > The status property is missing but as you told me in v1 it should not
> > > matter. I will leave it for Simon to decide if he wants it to keep it
> > > consistent with other SoC or if we should remove it from the other dtsi
> > > files. In any case with or without the status property.
> >
> > Forgot to review commit c79661eb5060e2bf ("arm64: dts: renesas: Remove
> > unneeded status from thermal nodes")? ;-)
>
> Not only that also reviewing using the context from v4.19-rc1 which of
> course is not correct for dtsi patches, thanks for enlightening me :-)
Thanks everyone, applied or v4.21.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
2018-08-27 18:48 ` Sergei Shtylyov
` (16 preceding siblings ...)
(?)
@ 2018-10-16 19:36 ` Sergei Shtylyov
2018-10-17 8:12 ` Simon Horman
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-16 19:36 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe MSIOF in the R8A779{7|8}0 device trees.
The DMA props are deliberately omitted as the MSIOF DMA doesn't work on
R8A77970 (due to IPMMU issue) and the RT-DMAC isn't supported on R8A77980.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
Simon Horman's 'renesas.git' repo.
The MSIOF bindings patch has just been posted...
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 56 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 56 ++++++++++++++++++++++++++++++
2 files changed, 112 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -22,6 +22,10 @@
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ spi3 = &msiof2;
+ spi4 = &msiof3;
};
/* External CAN clock - to be overridden by boards that provide it */
@@ -688,6 +692,58 @@
status = "disabled";
};
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x64>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77970";
reg = <0 0xe6ef0000 0 0x1000>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -23,6 +23,10 @@
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
+ spi1 = &msiof0;
+ spi2 = &msiof1;
+ spi3 = &msiof2;
+ spi4 = &msiof3;
};
/* External CAN clock - to be overridden by boards that provide it */
@@ -740,6 +744,58 @@
status = "disabled";
};
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x64>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef0000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
2018-10-16 19:36 ` [PATCH] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support Sergei Shtylyov
@ 2018-10-17 8:12 ` Simon Horman
2018-10-17 8:52 ` Geert Uytterhoeven
0 siblings, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-10-17 8:12 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Tue, Oct 16, 2018 at 10:36:33PM +0300, Sergei Shtylyov wrote:
> Describe MSIOF in the R8A779{7|8}0 device trees.
>
> The DMA props are deliberately omitted as the MSIOF DMA doesn't work on
> R8A77970 (due to IPMMU issue) and the RT-DMAC isn't supported on R8A77980.
For the record: In the short term I'm fine with not enabling DMA if there
are known problems. But in the long term we should describe DMA in DT as
the purpose of DT is to describe hardware rather than software.
So please, as follow-up work, lets work towards a solution that allows us
to describe the hardware in DT.
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
> Simon Horman's 'renesas.git' repo.
>
> The MSIOF bindings patch has just been posted...
>
> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 56 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 56 ++++++++++++++++++++++++++++++
> 2 files changed, 112 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -22,6 +22,10 @@
> i2c2 = &i2c2;
> i2c3 = &i2c3;
> i2c4 = &i2c4;
> + spi1 = &msiof0;
> + spi2 = &msiof1;
> + spi3 = &msiof2;
> + spi4 = &msiof3;
Geert, could you comment on these aliases and the similar ones below?
I'm not seeing them for any other ARM64-based Renesas SoCs.
Otherwise I am happy with this patch.
> };
>
> /* External CAN clock - to be overridden by boards that provide it */
> @@ -688,6 +692,58 @@
> status = "disabled";
> };
>
> + msiof0: spi@e6e90000 {
> + compatible = "renesas,msiof-r8a77970",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6e90000 0 0x64>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 211>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 211>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + msiof1: spi@e6ea0000 {
> + compatible = "renesas,msiof-r8a77970",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6ea0000 0 0x0064>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 210>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 210>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + msiof2: spi@e6c00000 {
> + compatible = "renesas,msiof-r8a77970",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6c00000 0 0x0064>;
> + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 209>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 209>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + msiof3: spi@e6c10000 {
> + compatible = "renesas,msiof-r8a77970",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6c10000 0 0x0064>;
> + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 208>;
> + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
> + resets = <&cpg 208>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> vin0: video@e6ef0000 {
> compatible = "renesas,vin-r8a77970";
> reg = <0 0xe6ef0000 0 0x1000>;
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -23,6 +23,10 @@
> i2c3 = &i2c3;
> i2c4 = &i2c4;
> i2c5 = &i2c5;
> + spi1 = &msiof0;
> + spi2 = &msiof1;
> + spi3 = &msiof2;
> + spi4 = &msiof3;
> };
>
> /* External CAN clock - to be overridden by boards that provide it */
> @@ -740,6 +744,58 @@
> status = "disabled";
> };
>
> + msiof0: spi@e6e90000 {
> + compatible = "renesas,msiof-r8a77980",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6e90000 0 0x64>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 211>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 211>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + msiof1: spi@e6ea0000 {
> + compatible = "renesas,msiof-r8a77980",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6ea0000 0 0x0064>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 210>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 210>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + msiof2: spi@e6c00000 {
> + compatible = "renesas,msiof-r8a77980",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6c00000 0 0x0064>;
> + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 209>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 209>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + msiof3: spi@e6c10000 {
> + compatible = "renesas,msiof-r8a77980",
> + "renesas,rcar-gen3-msiof";
> + reg = <0 0xe6c10000 0 0x0064>;
> + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 208>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 208>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> vin0: video@e6ef0000 {
> compatible = "renesas,vin-r8a77980";
> reg = <0 0xe6ef0000 0 0x1000>;
>
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
2018-10-17 8:12 ` Simon Horman
@ 2018-10-17 8:52 ` Geert Uytterhoeven
2018-10-18 12:45 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Geert Uytterhoeven @ 2018-10-17 8:52 UTC (permalink / raw)
To: Simon Horman
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
Hi Simon,
On Wed, Oct 17, 2018 at 10:13 AM Simon Horman <horms@verge.net.au> wrote:
> On Tue, Oct 16, 2018 at 10:36:33PM +0300, Sergei Shtylyov wrote:
> > Describe MSIOF in the R8A779{7|8}0 device trees.
> >
> > The DMA props are deliberately omitted as the MSIOF DMA doesn't work on
> > R8A77970 (due to IPMMU issue) and the RT-DMAC isn't supported on R8A77980.
>
> For the record: In the short term I'm fine with not enabling DMA if there
> are known problems. But in the long term we should describe DMA in DT as
> the purpose of DT is to describe hardware rather than software.
>
> So please, as follow-up work, lets work towards a solution that allows us
> to describe the hardware in DT.
>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > ---
> > This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
> > Simon Horman's 'renesas.git' repo.
> >
> > The MSIOF bindings patch has just been posted...
> >
> > arch/arm64/boot/dts/renesas/r8a77970.dtsi | 56 ++++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 56 ++++++++++++++++++++++++++++++
> > 2 files changed, 112 insertions(+)
> >
> > Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > ===================================================================
> > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > @@ -22,6 +22,10 @@
> > i2c2 = &i2c2;
> > i2c3 = &i2c3;
> > i2c4 = &i2c4;
> > + spi1 = &msiof0;
> > + spi2 = &msiof1;
> > + spi3 = &msiof2;
> > + spi4 = &msiof3;
>
> Geert, could you comment on these aliases and the similar ones below?
> I'm not seeing them for any other ARM64-based Renesas SoCs.
I2c and spi aliases are "used, but not recommended", cfr.
https://lore.kernel.org/lkml/20181015180046.GA18294@bogus/
Personally (but I'm biased, referring to an email thread I participated in ;-),
I'd only leave serial0 (+ perhaps a 2nd/3th serial port) and ethernet0.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
2018-10-17 8:52 ` Geert Uytterhoeven
@ 2018-10-18 12:45 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-18 12:45 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland
On Wed, Oct 17, 2018 at 10:52:14AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Oct 17, 2018 at 10:13 AM Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Oct 16, 2018 at 10:36:33PM +0300, Sergei Shtylyov wrote:
> > > Describe MSIOF in the R8A779{7|8}0 device trees.
> > >
> > > The DMA props are deliberately omitted as the MSIOF DMA doesn't work on
> > > R8A77970 (due to IPMMU issue) and the RT-DMAC isn't supported on R8A77980.
> >
> > For the record: In the short term I'm fine with not enabling DMA if there
> > are known problems. But in the long term we should describe DMA in DT as
> > the purpose of DT is to describe hardware rather than software.
> >
> > So please, as follow-up work, lets work towards a solution that allows us
> > to describe the hardware in DT.
> >
> > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > >
> > > ---
> > > This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
> > > Simon Horman's 'renesas.git' repo.
> > >
> > > The MSIOF bindings patch has just been posted...
> > >
> > > arch/arm64/boot/dts/renesas/r8a77970.dtsi | 56 ++++++++++++++++++++++++++++++
> > > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 56 ++++++++++++++++++++++++++++++
> > > 2 files changed, 112 insertions(+)
> > >
> > > Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > > ===================================================================
> > > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > > +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> > > @@ -22,6 +22,10 @@
> > > i2c2 = &i2c2;
> > > i2c3 = &i2c3;
> > > i2c4 = &i2c4;
> > > + spi1 = &msiof0;
> > > + spi2 = &msiof1;
> > > + spi3 = &msiof2;
> > > + spi4 = &msiof3;
> >
> > Geert, could you comment on these aliases and the similar ones below?
> > I'm not seeing them for any other ARM64-based Renesas SoCs.
>
> I2c and spi aliases are "used, but not recommended", cfr.
> https://lore.kernel.org/lkml/20181015180046.GA18294@bogus/
>
> Personally (but I'm biased, referring to an email thread I participated in ;-),
> I'd only leave serial0 (+ perhaps a 2nd/3th serial port) and ethernet0.
Thanks, it seems to me that would be a good direction to move towards.
Sergei, could you consider dropping the alias portions of this patch?
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH] arm64: dts: renesas: condor: switch from EtherAVB to GEther
2018-08-27 18:48 ` Sergei Shtylyov
` (17 preceding siblings ...)
(?)
@ 2018-10-18 16:48 ` Sergei Shtylyov
2018-10-31 14:30 ` Simon Horman
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-18 16:48 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, Valentine Barshak
The "official" Condor boards have always been wired to mount NFS via
GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
to Cogent Embedded, so we've been having an unpleasant situation where
a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
extension board is plugged in). Switch from EtherAVB to GEther at last!
Fixes: 8091788f3d38 ("arm64: dts: renesas: condor: add EtherAVB support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against Linus' 'linux.git' repo -- coulan't find a fitting
brancxh in Simon Horman's 'renesas.git' repo...
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 47 ++++++++++++------------
1 file changed, 24 insertions(+), 23 deletions(-)
Index: linux/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- linux.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ linux/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -15,7 +15,7 @@
aliases {
serial0 = &scif0;
- ethernet0 = &avb;
+ ethernet0 = &gether;
};
chosen {
@@ -47,23 +47,6 @@
};
};
-&avb {
- pinctrl-0 = <&avb_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii-id";
- phy-handle = <&phy0>;
- renesas,no-ether-link;
- status = "okay";
-
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
@@ -82,6 +65,23 @@
clock-frequency = <32768>;
};
+&gether {
+ pinctrl-0 = <&gether_pins>;
+ pinctrl-names = "default";
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
@@ -118,16 +118,17 @@
};
&pfc {
- avb_pins: avb {
- groups = "avb_mdio", "avb_rgmii";
- function = "avb";
- };
-
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
+ gether_pins: gether {
+ groups = "gether_mdio_a", "gether_rgmii",
+ "gether_txcrefclk", "gether_txcrefclk_mega";
+ function = "gether";
+ };
+
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: condor: switch from EtherAVB to GEther
2018-10-18 16:48 ` [PATCH] arm64: dts: renesas: condor: switch from EtherAVB to GEther Sergei Shtylyov
@ 2018-10-31 14:30 ` Simon Horman
2018-10-31 17:29 ` Sergei Shtylyov
0 siblings, 1 reply; 86+ messages in thread
From: Simon Horman @ 2018-10-31 14:30 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Valentine Barshak
On Thu, Oct 18, 2018 at 07:48:53PM +0300, Sergei Shtylyov wrote:
> The "official" Condor boards have always been wired to mount NFS via
> GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
> to Cogent Embedded, so we've been having an unpleasant situation where
> a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
> extension board is plugged in). Switch from EtherAVB to GEther at last!
>
> Fixes: 8091788f3d38 ("arm64: dts: renesas: condor: add EtherAVB support")
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks, applied for v4.21.
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: condor: switch from EtherAVB to GEther
2018-10-31 14:30 ` Simon Horman
@ 2018-10-31 17:29 ` Sergei Shtylyov
2018-11-02 11:25 ` Simon Horman
0 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-31 17:29 UTC (permalink / raw)
To: Simon Horman
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Valentine Barshak
On 10/31/2018 5:30 PM, Simon Horman wrote:
>> The "official" Condor boards have always been wired to mount NFS via
>> GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
>> to Cogent Embedded, so we've been having an unpleasant situation where
>> a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
>> extension board is plugged in). Switch from EtherAVB to GEther at last!
>>
>> Fixes: 8091788f3d38 ("arm64: dts: renesas: condor: add EtherAVB support")
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Thanks, applied for v4.21.
Wait, this was intended as a fix for 4.20...
MBR, Sergei
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH] arm64: dts: renesas: condor: switch from EtherAVB to GEther
2018-10-31 17:29 ` Sergei Shtylyov
@ 2018-11-02 11:25 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-11-02 11:25 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm,
Mark Rutland, Valentine Barshak
On Wed, Oct 31, 2018 at 08:29:50PM +0300, Sergei Shtylyov wrote:
> On 10/31/2018 5:30 PM, Simon Horman wrote:
>
> > > The "official" Condor boards have always been wired to mount NFS via
> > > GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
> > > to Cogent Embedded, so we've been having an unpleasant situation where
> > > a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
> > > extension board is plugged in). Switch from EtherAVB to GEther at last!
> > >
> > > Fixes: 8091788f3d38 ("arm64: dts: renesas: condor: add EtherAVB support")
> > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > Thanks, applied for v4.21.
>
> Wait, this was intended as a fix for 4.20...
Thanks, I have re-queued this as a fix for v4.20.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
2018-08-27 18:48 ` Sergei Shtylyov
` (18 preceding siblings ...)
(?)
@ 2018-10-19 19:10 ` Sergei Shtylyov
2018-10-29 10:24 ` Simon Horman
-1 siblings, 1 reply; 86+ messages in thread
From: Sergei Shtylyov @ 2018-10-19 19:10 UTC (permalink / raw)
To: Simon Horman, Rob Herring, linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland
Describe MSIOF in the R8A779{7|8}0 device trees.
The DMA props are omitted for R8A77980 as the RT-DMAC isn't supported
(yet?)...
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
Simon Horman's 'renesas.git' repo.
Changes in version 2:
- removed the aliases;
- restored the DMA props on R8A77970, updated the description accordingly;
- mentioned Vladimir in the description and added his signoff;
- refreshed the patch.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 64 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 52 ++++++++++++++++++++++++
2 files changed, 116 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -753,6 +753,70 @@
status = "disabled";
};
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x64>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+ <&dmac2 0x41>, <&dmac2 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+ <&dmac2 0x43>, <&dmac2 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ dmas = <&dmac1 0x45>, <&dmac1 0x44>,
+ <&dmac2 0x45>, <&dmac2 0x44>;
+ dma-names = "tx", "rx", "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a77970",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ dmas = <&dmac1 0x47>, <&dmac1 0x46>,
+ <&dmac2 0x47>, <&dmac2 0x46>;
+ dma-names = "tx", "rx", "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77970";
reg = <0 0xe6ef0000 0 0x1000>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -805,6 +805,58 @@
status = "disabled";
};
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x64>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77980";
reg = <0 0xe6ef0000 0 0x1000>;
^ permalink raw reply [flat|nested] 86+ messages in thread* Re: [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
2018-10-19 19:10 ` [PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support Sergei Shtylyov
@ 2018-10-29 10:24 ` Simon Horman
0 siblings, 0 replies; 86+ messages in thread
From: Simon Horman @ 2018-10-29 10:24 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, linux-renesas-soc, devicetree, Magnus Damm, Mark Rutland
On Fri, Oct 19, 2018 at 10:10:44PM +0300, Sergei Shtylyov wrote:
> Describe MSIOF in the R8A779{7|8}0 device trees.
>
> The DMA props are omitted for R8A77980 as the RT-DMAC isn't supported
> (yet?)...
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
> Simon Horman's 'renesas.git' repo.
>
> Changes in version 2:
> - removed the aliases;
> - restored the DMA props on R8A77970, updated the description accordingly;
> - mentioned Vladimir in the description and added his signoff;
> - refreshed the patch.
Thanks, applied for v4.21.
^ permalink raw reply [flat|nested] 86+ messages in thread