* [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
@ 2023-01-25 22:27 Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 01/16] rockchip: mkimage: Add rk3588 support Jagan Teki
` (16 more replies)
0 siblings, 17 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
This series support Rockchip RK3588. All the device tree files are
synced from linux-next with the proper SHA1 mentioned in the commit
messages.
Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
it is failing to load ATF entry from SPL and hang.
Verified below BL31 versions,
bl31-v1.15
bl31-v1.21
bl31-v1.22
bl31-v1.23
bl31-v1.24
bl31-v1.25
bl31-v1.26
Rever-engineered with respect to rockchip u-boot by using the same
FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
mainline showing the same issue.
Log:
LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
Trying to boot from MMC1
bl31_entry: atf_entry start
<< hang >>
Any information on BL31 for RK3588 please share.
Any inputs?
Jagan.
Jagan Teki (16):
rockchip: mkimage: Add rk3588 support
arm: rockchip: Add cru header for rk3588
arm: rockchip: Add grf header for rk3588
dt-bindings: clk: Add dt-binding header for RK3588
clk: rockchip: Add rk3588 clk support
clk: rockchip: pll: Add pll_rk3588 type for rk3588
ram: rockchip: Add rk3588 ddr driver support
dt-bindings: power: Add power-domain header for rk3588
dt-bindings: reset: add rk3588 reset definitions
arm: rockchip: Add ioc header for rk3588
arm64: dts: rockchip: Add base DT for rk3588 SoC
arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
arm: rockchip: Add RK3588 arch core support
ARM: dts: rockchip: Add rk3588-u-boot.dtsi
board: rockchip: Add Edgeble Neural Compute Module 6
arch/arm/dts/Makefile | 3 +
.../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 23 +
arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 27 +
arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 32 +
arch/arm/dts/rk3588-pinctrl.dtsi | 516 +++
arch/arm/dts/rk3588-u-boot.dtsi | 101 +
arch/arm/dts/rk3588.dtsi | 58 +
arch/arm/dts/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++
arch/arm/dts/rk3588s.dtsi | 1703 +++++++++
arch/arm/include/asm/arch-rk3588/boot0.h | 11 +
arch/arm/include/asm/arch-rk3588/gpio.h | 11 +
arch/arm/include/asm/arch-rockchip/clock.h | 24 +
.../include/asm/arch-rockchip/cru_rk3588.h | 451 +++
.../include/asm/arch-rockchip/grf_rk3588.h | 35 +
.../include/asm/arch-rockchip/ioc_rk3588.h | 102 +
arch/arm/mach-rockchip/Kconfig | 20 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3588/Kconfig | 30 +
arch/arm/mach-rockchip/rk3588/Makefile | 9 +
arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 33 +
arch/arm/mach-rockchip/rk3588/rk3588.c | 162 +
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 32 +
board/edgeble/neural-compute-module-6/Kconfig | 15 +
.../neural-compute-module-6/MAINTAINERS | 6 +
.../edgeble/neural-compute-module-6/Makefile | 7 +
board/edgeble/neural-compute-module-6/neu6.c | 4 +
configs/neu6a-io-rk3588_defconfig | 68 +
doc/board/rockchip/rockchip.rst | 2 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_pll.c | 267 +-
drivers/clk/rockchip/clk_rk3588.c | 2019 ++++++++++
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3588.c | 56 +
include/configs/neural-compute-module-6.h | 15 +
include/configs/rk3588_common.h | 32 +
.../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++
include/dt-bindings/power/rk3588-power.h | 69 +
.../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++
tools/rkcommon.c | 1 +
39 files changed, 10867 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io.dts
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a.dtsi
create mode 100644 arch/arm/dts/rk3588-pinctrl.dtsi
create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588.dtsi
create mode 100644 arch/arm/dts/rk3588s-pinctrl.dtsi
create mode 100644 arch/arm/dts/rk3588s.dtsi
create mode 100644 arch/arm/include/asm/arch-rk3588/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3588/gpio.h
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3588.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3588.h
create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
create mode 100644 arch/arm/mach-rockchip/rk3588/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3588/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3588/clk_rk3588.c
create mode 100644 arch/arm/mach-rockchip/rk3588/rk3588.c
create mode 100644 arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
create mode 100644 board/edgeble/neural-compute-module-6/Kconfig
create mode 100644 board/edgeble/neural-compute-module-6/MAINTAINERS
create mode 100644 board/edgeble/neural-compute-module-6/Makefile
create mode 100644 board/edgeble/neural-compute-module-6/neu6.c
create mode 100644 configs/neu6a-io-rk3588_defconfig
create mode 100644 drivers/clk/rockchip/clk_rk3588.c
create mode 100644 drivers/ram/rockchip/sdram_rk3588.c
create mode 100644 include/configs/neural-compute-module-6.h
create mode 100644 include/configs/rk3588_common.h
create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h
create mode 100644 include/dt-bindings/power/rk3588-power.h
create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h
--
2.25.1
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH 01/16] rockchip: mkimage: Add rk3588 support
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 02/16] arm: rockchip: Add cru header for rk3588 Jagan Teki
` (15 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Add support for rk3588 package header in mkimage tool.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 1f1eaa1675..2e22a1bf8a 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -135,6 +135,7 @@ static struct spl_info spl_infos[] = {
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
{ "rk3568", "RK35", 0x14000 - 0x1000, false, RK_HEADER_V2 },
+ { "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
/**
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 02/16] arm: rockchip: Add cru header for rk3588
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 01/16] rockchip: mkimage: Add rk3588 support Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 03/16] arm: rockchip: Add grf " Jagan Teki
` (14 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Elaine Zhang
Add clock and reset unit header include for rk3588.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../include/asm/arch-rockchip/cru_rk3588.h | 451 ++++++++++++++++++
1 file changed, 451 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3588.h
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
new file mode 100644
index 0000000000..3ea59e9008
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -0,0 +1,451 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3588_H
+#define _ASM_ARCH_CRU_RK3588_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1008 * MHz)
+#define LPLL_HZ (816 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (1500 * MHz)
+#define NPLL_HZ (850 * MHz)
+#define PPLL_HZ (1100 * MHz)
+
+/* RK3588 pll id */
+enum rk3588_pll_id {
+ B0PLL,
+ B1PLL,
+ LPLL,
+ CPLL,
+ GPLL,
+ NPLL,
+ V0PLL,
+ AUPLL,
+ PPLL,
+ PLL_COUNT,
+};
+
+struct rk3588_clk_info {
+ unsigned long id;
+ char *name;
+ bool is_cru;
+};
+
+struct rk3588_clk_priv {
+ struct rk3588_cru *cru;
+ struct rk3588_grf *grf;
+ ulong ppll_hz;
+ ulong gpll_hz;
+ ulong cpll_hz;
+ ulong npll_hz;
+ ulong v0pll_hz;
+ ulong aupll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3588_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rk3588_cru {
+ struct rk3588_pll pll[18];
+ unsigned int reserved0[16];/* Address Offset: 0x0240 */
+ unsigned int mode_con00;/* Address Offset: 0x0280 */
+ unsigned int reserved1[31];/* Address Offset: 0x0284 */
+ unsigned int clksel_con[178]; /* Address Offset: 0x0300 */
+ unsigned int reserved2[142];/* Address Offset: 0x05c8 */
+ unsigned int clkgate_con[78];/* Address Offset: 0x0800 */
+ unsigned int reserved3[50];/* Address Offset: 0x0938 */
+ unsigned int softrst_con[78];/* Address Offset: 0x0400 */
+ unsigned int reserved4[50];/* Address Offset: 0x0b38 */
+ unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
+ unsigned int glb_rst_st;/* Address Offset: 0x0c04 */
+ unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */
+ unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */
+ unsigned int glb_rst_con;/* Address Offset: 0x0c10 */
+ unsigned int reserved5[4];/* Address Offset: 0x0c14 */
+ unsigned int sdio_con[2];/* Address Offset: 0x0c24 */
+ unsigned int reserved7;/* Address Offset: 0x0c2c */
+ unsigned int sdmmc_con[2];/* Address Offset: 0x0c30 */
+ unsigned int reserved8[48562];/* Address Offset: 0x0c38 */
+ unsigned int pmuclksel_con[21]; /* Address Offset: 0x0100 */
+ unsigned int reserved9[299];/* Address Offset: 0x0c38 */
+ unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */
+};
+
+check_member(rk3588_cru, mode_con00, 0x280);
+check_member(rk3588_cru, pmuclksel_con[1], 0x30304);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int m;
+ unsigned int p;
+ unsigned int s;
+ unsigned int k;
+};
+
+#define RK3588_PLL_CON(x) ((x) * 0x4)
+#define RK3588_MODE_CON 0x280
+
+#define RK3588_PHP_CRU_BASE 0x8000
+#define RK3588_PMU_CRU_BASE 0x30000
+#define RK3588_BIGCORE0_CRU_BASE 0x50000
+#define RK3588_BIGCORE1_CRU_BASE 0x52000
+#define RK3588_DSU_CRU_BASE 0x58000
+
+#define RK3588_PLL_CON(x) ((x) * 0x4)
+#define RK3588_MODE_CON0 0x280
+#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3588_GLB_CNT_TH 0xc00
+#define RK3588_GLB_SRST_FST 0xc08
+#define RK3588_GLB_SRST_SND 0xc0c
+#define RK3588_GLB_RST_CON 0xc10
+#define RK3588_GLB_RST_ST 0xc04
+#define RK3588_SDIO_CON0 0xC24
+#define RK3588_SDIO_CON1 0xC28
+#define RK3588_SDMMC_CON0 0xC30
+#define RK3588_SDMMC_CON1 0xC34
+
+#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
+#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
+
+#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
+#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
+#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
+#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
+
+#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
+#define RK3588_B0_PLL_MODE_CON (RK3588_BIGCORE0_CRU_BASE + 0x280)
+#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
+#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
+#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
+#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
+#define RK3588_B1_PLL_MODE_CON (RK3588_BIGCORE1_CRU_BASE + 0x280)
+#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
+#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
+#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
+#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
+#define RK3588_LPLL_MODE_CON (RK3588_DSU_CRU_BASE + 0x280)
+#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
+#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
+#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
+
+enum {
+ /* CRU_CLK_SEL8_CON */
+ ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,
+ ACLK_LOW_TOP_ROOT_SRC_SEL_MASK = 1 << ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT,
+ ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL = 0,
+ ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL,
+ ACLK_LOW_TOP_ROOT_DIV_SHIFT = 9,
+ ACLK_LOW_TOP_ROOT_DIV_MASK = 0x1f << ACLK_LOW_TOP_ROOT_DIV_SHIFT,
+ PCLK_TOP_ROOT_SEL_SHIFT = 7,
+ PCLK_TOP_ROOT_SEL_MASK = 3 << PCLK_TOP_ROOT_SEL_SHIFT,
+ PCLK_TOP_ROOT_SEL_100M = 0,
+ PCLK_TOP_ROOT_SEL_50M,
+ PCLK_TOP_ROOT_SEL_24M,
+ ACLK_TOP_ROOT_SRC_SEL_SHIFT = 5,
+ ACLK_TOP_ROOT_SRC_SEL_MASK = 3 << ACLK_TOP_ROOT_SRC_SEL_SHIFT,
+ ACLK_TOP_ROOT_SRC_SEL_GPLL = 0,
+ ACLK_TOP_ROOT_SRC_SEL_CPLL,
+ ACLK_TOP_ROOT_SRC_SEL_AUPLL,
+ ACLK_TOP_ROOT_DIV_SHIFT = 0,
+ ACLK_TOP_ROOT_DIV_MASK = 0x1f << ACLK_TOP_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL9_CON */
+ ACLK_TOP_S400_SEL_SHIFT = 8,
+ ACLK_TOP_S400_SEL_MASK = 3 << ACLK_TOP_S400_SEL_SHIFT,
+ ACLK_TOP_S400_SEL_400M = 0,
+ ACLK_TOP_S400_SEL_200M,
+ ACLK_TOP_S200_SEL_SHIFT = 6,
+ ACLK_TOP_S200_SEL_MASK = 3 << ACLK_TOP_S200_SEL_SHIFT,
+ ACLK_TOP_S200_SEL_200M = 0,
+ ACLK_TOP_S200_SEL_100M,
+
+ /* CRU_CLK_SEL38_CON */
+ CLK_I2C8_SEL_SHIFT = 13,
+ CLK_I2C8_SEL_MASK = 1 << CLK_I2C8_SEL_SHIFT,
+ CLK_I2C7_SEL_SHIFT = 12,
+ CLK_I2C7_SEL_MASK = 1 << CLK_I2C7_SEL_SHIFT,
+ CLK_I2C6_SEL_SHIFT = 11,
+ CLK_I2C6_SEL_MASK = 1 << CLK_I2C6_SEL_SHIFT,
+ CLK_I2C5_SEL_SHIFT = 10,
+ CLK_I2C5_SEL_MASK = 1 << CLK_I2C5_SEL_SHIFT,
+ CLK_I2C4_SEL_SHIFT = 9,
+ CLK_I2C4_SEL_MASK = 1 << CLK_I2C4_SEL_SHIFT,
+ CLK_I2C3_SEL_SHIFT = 8,
+ CLK_I2C3_SEL_MASK = 1 << CLK_I2C3_SEL_SHIFT,
+ CLK_I2C2_SEL_SHIFT = 7,
+ CLK_I2C2_SEL_MASK = 1 << CLK_I2C2_SEL_SHIFT,
+ CLK_I2C1_SEL_SHIFT = 6,
+ CLK_I2C1_SEL_MASK = 1 << CLK_I2C1_SEL_SHIFT,
+ ACLK_BUS_ROOT_SEL_SHIFT = 5,
+ ACLK_BUS_ROOT_SEL_MASK = 3 << ACLK_BUS_ROOT_SEL_SHIFT,
+ ACLK_BUS_ROOT_SEL_GPLL = 0,
+ ACLK_BUS_ROOT_SEL_CPLL,
+ ACLK_BUS_ROOT_DIV_SHIFT = 0,
+ ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL40_CON */
+ CLK_SARADC_SEL_SHIFT = 14,
+ CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT,
+ CLK_SARADC_SEL_GPLL = 0,
+ CLK_SARADC_SEL_24M,
+ CLK_SARADC_DIV_SHIFT = 6,
+ CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL41_CON */
+ CLK_UART_SRC_SEL_SHIFT = 14,
+ CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT,
+ CLK_UART_SRC_SEL_GPLL = 0,
+ CLK_UART_SRC_SEL_CPLL,
+ CLK_UART_SRC_DIV_SHIFT = 9,
+ CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT,
+ CLK_TSADC_SEL_SHIFT = 8,
+ CLK_TSADC_SEL_MASK = 0x1 << CLK_TSADC_SEL_SHIFT,
+ CLK_TSADC_SEL_GPLL = 0,
+ CLK_TSADC_SEL_24M,
+ CLK_TSADC_DIV_SHIFT = 0,
+ CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL42_CON */
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
+
+ /* CRU_CLK_SEL43_CON */
+ CLK_UART_SEL_SHIFT = 0,
+ CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
+ CLK_UART_SEL_SRC = 0,
+ CLK_UART_SEL_FRAC,
+ CLK_UART_SEL_XIN24M,
+
+ /* CRU_CLK_SEL59_CON */
+ CLK_PWM2_SEL_SHIFT = 14,
+ CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
+ CLK_PWM1_SEL_SHIFT = 12,
+ CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
+ CLK_SPI4_SEL_SHIFT = 10,
+ CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT,
+ CLK_SPI3_SEL_SHIFT = 8,
+ CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
+ CLK_SPI2_SEL_SHIFT = 6,
+ CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
+ CLK_SPI1_SEL_SHIFT = 4,
+ CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
+ CLK_SPI0_SEL_SHIFT = 2,
+ CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
+ CLK_SPI_SEL_200M = 0,
+ CLK_SPI_SEL_150M,
+ CLK_SPI_SEL_24M,
+
+ /* CRU_CLK_SEL60_CON */
+ CLK_PWM3_SEL_SHIFT = 0,
+ CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT,
+ CLK_PWM_SEL_100M = 0,
+ CLK_PWM_SEL_50M,
+ CLK_PWM_SEL_24M,
+
+ /* CRU_CLK_SEL62_CON */
+ DCLK_DECOM_SEL_SHIFT = 5,
+ DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
+ DCLK_DECOM_SEL_GPLL = 0,
+ DCLK_DECOM_SEL_SPLL,
+ DCLK_DECOM_DIV_SHIFT = 0,
+ DCLK_DECOM_DIV_MASK = 0x1F << DCLK_DECOM_DIV_SHIFT,
+
+ /* CRU_CLK_SEL77_CON */
+ CCLK_EMMC_SEL_SHIFT = 14,
+ CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT,
+ CCLK_EMMC_SEL_GPLL = 0,
+ CCLK_EMMC_SEL_CPLL,
+ CCLK_EMMC_SEL_24M,
+ CCLK_EMMC_DIV_SHIFT = 8,
+ CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL78_CON */
+ SCLK_SFC_SEL_SHIFT = 12,
+ SCLK_SFC_SEL_MASK = 3 << SCLK_SFC_SEL_SHIFT,
+ SCLK_SFC_SEL_GPLL = 0,
+ SCLK_SFC_SEL_CPLL,
+ SCLK_SFC_SEL_24M,
+ SCLK_SFC_DIV_SHIFT = 6,
+ SCLK_SFC_DIV_MASK = 0x3f << SCLK_SFC_DIV_SHIFT,
+ BCLK_EMMC_SEL_SHIFT = 5,
+ BCLK_EMMC_SEL_MASK = 1 << BCLK_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_GPLL = 0,
+ BCLK_EMMC_SEL_CPLL,
+ BCLK_EMMC_DIV_SHIFT = 0,
+ BCLK_EMMC_DIV_MASK = 0x1f << BCLK_EMMC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL81_CON */
+ CLK_GMAC1_PTP_SEL_SHIFT = 13,
+ CLK_GMAC1_PTP_SEL_MASK = 1 << CLK_GMAC1_PTP_SEL_SHIFT,
+ CLK_GMAC1_PTP_SEL_CPLL = 0,
+ CLK_GMAC1_PTP_DIV_SHIFT = 7,
+ CLK_GMAC1_PTP_DIV_MASK = 0x3f << CLK_GMAC1_PTP_DIV_SHIFT,
+ CLK_GMAC0_PTP_SEL_SHIFT = 6,
+ CLK_GMAC0_PTP_SEL_MASK = 1 << CLK_GMAC0_PTP_SEL_SHIFT,
+ CLK_GMAC0_PTP_SEL_CPLL = 0,
+ CLK_GMAC0_PTP_DIV_SHIFT = 0,
+ CLK_GMAC0_PTP_DIV_MASK = 0x3f << CLK_GMAC0_PTP_DIV_SHIFT,
+
+ /* CRU_CLK_SEL83_CON */
+ CLK_GMAC_125M_SEL_SHIFT = 15,
+ CLK_GMAC_125M_SEL_MASK = 1 << CLK_GMAC_125M_SEL_SHIFT,
+ CLK_GMAC_125M_SEL_GPLL = 0,
+ CLK_GMAC_125M_SEL_CPLL,
+ CLK_GMAC_125M_DIV_SHIFT = 8,
+ CLK_GMAC_125M_DIV_MASK = 0x7f << CLK_GMAC_125M_DIV_SHIFT,
+
+ /* CRU_CLK_SEL84_CON */
+ CLK_GMAC_50M_SEL_SHIFT = 7,
+ CLK_GMAC_50M_SEL_MASK = 1 << CLK_GMAC_50M_SEL_SHIFT,
+ CLK_GMAC_50M_SEL_GPLL = 0,
+ CLK_GMAC_50M_SEL_CPLL,
+ CLK_GMAC_50M_DIV_SHIFT = 0,
+ CLK_GMAC_50M_DIV_MASK = 0x7f << CLK_GMAC_50M_DIV_SHIFT,
+
+ /* CRU_CLK_SEL110_CON */
+ HCLK_VOP_ROOT_SEL_SHIFT = 10,
+ HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT,
+ HCLK_VOP_ROOT_SEL_200M = 0,
+ HCLK_VOP_ROOT_SEL_100M,
+ HCLK_VOP_ROOT_SEL_50M,
+ HCLK_VOP_ROOT_SEL_24M,
+ ACLK_VOP_LOW_ROOT_SEL_SHIFT = 8,
+ ACLK_VOP_LOW_ROOT_SEL_MASK = 3 << ACLK_VOP_LOW_ROOT_SEL_SHIFT,
+ ACLK_VOP_LOW_ROOT_SEL_400M = 0,
+ ACLK_VOP_LOW_ROOT_SEL_200M,
+ ACLK_VOP_LOW_ROOT_SEL_100M,
+ ACLK_VOP_LOW_ROOT_SEL_24M,
+ ACLK_VOP_ROOT_SEL_SHIFT = 5,
+ ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT,
+ ACLK_VOP_ROOT_SEL_GPLL = 0,
+ ACLK_VOP_ROOT_SEL_CPLL,
+ ACLK_VOP_ROOT_SEL_AUPLL,
+ ACLK_VOP_ROOT_SEL_NPLL,
+ ACLK_VOP_ROOT_SEL_SPLL,
+ ACLK_VOP_ROOT_DIV_SHIFT = 0,
+ ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL111_CON */
+ DCLK1_VOP_SRC_SEL_SHIFT = 14,
+ DCLK1_VOP_SRC_SEL_MASK = 3 << DCLK1_VOP_SRC_SEL_SHIFT,
+ DCLK1_VOP_SRC_DIV_SHIFT = 9,
+ DCLK1_VOP_SRC_DIV_MASK = 0x1f << DCLK1_VOP_SRC_DIV_SHIFT,
+ DCLK0_VOP_SRC_SEL_SHIFT = 7,
+ DCLK0_VOP_SRC_SEL_MASK = 3 << DCLK0_VOP_SRC_SEL_SHIFT,
+ DCLK_VOP_SRC_SEL_GPLL = 0,
+ DCLK_VOP_SRC_SEL_CPLL,
+ DCLK_VOP_SRC_SEL_V0PLL,
+ DCLK_VOP_SRC_SEL_AUPLL,
+ DCLK0_VOP_SRC_DIV_SHIFT = 0,
+ DCLK0_VOP_SRC_DIV_MASK = 0x7f << DCLK0_VOP_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL112_CON */
+ DCLK2_VOP_SEL_SHIFT = 11,
+ DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT,
+ DCLK1_VOP_SEL_SHIFT = 9,
+ DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT,
+ DCLK0_VOP_SEL_SHIFT = 7,
+ DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT,
+ DCLK2_VOP_SRC_SEL_SHIFT = 5,
+ DCLK2_VOP_SRC_SEL_MASK = 3 << DCLK2_VOP_SRC_SEL_SHIFT,
+ DCLK2_VOP_SRC_DIV_SHIFT = 0,
+ DCLK2_VOP_SRC_DIV_MASK = 0x1f << DCLK2_VOP_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL113_CON */
+ DCLK3_VOP_SRC_SEL_SHIFT = 7,
+ DCLK3_VOP_SRC_SEL_MASK = 3 << DCLK3_VOP_SRC_SEL_SHIFT,
+ DCLK3_VOP_SRC_DIV_SHIFT = 0,
+ DCLK3_VOP_SRC_DIV_MASK = 0x7f << DCLK3_VOP_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL117_CON */
+ CLK_AUX16MHZ_1_DIV_SHIFT = 8,
+ CLK_AUX16MHZ_1_DIV_MASK = 0xff << CLK_AUX16MHZ_1_DIV_SHIFT,
+ CLK_AUX16MHZ_0_DIV_SHIFT = 0,
+ CLK_AUX16MHZ_0_DIV_MASK = 0xff << CLK_AUX16MHZ_0_DIV_SHIFT,
+
+ /* CRU_CLK_SEL165_CON */
+ PCLK_CENTER_ROOT_SEL_SHIFT = 6,
+ PCLK_CENTER_ROOT_SEL_MASK = 3 << PCLK_CENTER_ROOT_SEL_SHIFT,
+ PCLK_CENTER_ROOT_SEL_200M = 0,
+ PCLK_CENTER_ROOT_SEL_100M,
+ PCLK_CENTER_ROOT_SEL_50M,
+ PCLK_CENTER_ROOT_SEL_24M,
+ HCLK_CENTER_ROOT_SEL_SHIFT = 4,
+ HCLK_CENTER_ROOT_SEL_MASK = 3 << HCLK_CENTER_ROOT_SEL_SHIFT,
+ HCLK_CENTER_ROOT_SEL_400M = 0,
+ HCLK_CENTER_ROOT_SEL_200M,
+ HCLK_CENTER_ROOT_SEL_100M,
+ HCLK_CENTER_ROOT_SEL_24M,
+ ACLK_CENTER_LOW_ROOT_SEL_SHIFT = 2,
+ ACLK_CENTER_LOW_ROOT_SEL_MASK = 3 << ACLK_CENTER_LOW_ROOT_SEL_SHIFT,
+ ACLK_CENTER_LOW_ROOT_SEL_500M = 0,
+ ACLK_CENTER_LOW_ROOT_SEL_250M,
+ ACLK_CENTER_LOW_ROOT_SEL_100M,
+ ACLK_CENTER_LOW_ROOT_SEL_24M,
+ ACLK_CENTER_ROOT_SEL_SHIFT = 0,
+ ACLK_CENTER_ROOT_SEL_MASK = 3 << ACLK_CENTER_ROOT_SEL_SHIFT,
+ ACLK_CENTER_ROOT_SEL_700M = 0,
+ ACLK_CENTER_ROOT_SEL_400M,
+ ACLK_CENTER_ROOT_SEL_200M,
+ ACLK_CENTER_ROOT_SEL_24M,
+
+ /* CRU_CLK_SEL172_CON */
+ CCLK_SDIO_SRC_SEL_SHIFT = 8,
+ CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT,
+ CCLK_SDIO_SRC_SEL_GPLL = 0,
+ CCLK_SDIO_SRC_SEL_CPLL,
+ CCLK_SDIO_SRC_SEL_24M,
+ CCLK_SDIO_SRC_DIV_SHIFT = 2,
+ CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL176_CON */
+ CLK_PCIE_PHY1_PLL_DIV_SHIFT = 6,
+ CLK_PCIE_PHY1_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY1_PLL_DIV_SHIFT,
+ CLK_PCIE_PHY0_PLL_DIV_SHIFT = 0,
+ CLK_PCIE_PHY0_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY0_PLL_DIV_SHIFT,
+
+ /* CRU_CLK_SEL177_CON */
+ CLK_PCIE_PHY2_REF_SEL_SHIFT = 8,
+ CLK_PCIE_PHY2_REF_SEL_MASK = 1 << CLK_PCIE_PHY2_REF_SEL_SHIFT,
+ CLK_PCIE_PHY1_REF_SEL_SHIFT = 7,
+ CLK_PCIE_PHY1_REF_SEL_MASK = 1 << CLK_PCIE_PHY1_REF_SEL_SHIFT,
+ CLK_PCIE_PHY0_REF_SEL_SHIFT = 6,
+ CLK_PCIE_PHY0_REF_SEL_MASK = 1 << CLK_PCIE_PHY0_REF_SEL_SHIFT,
+ CLK_PCIE_PHY_REF_SEL_24M = 0,
+ CLK_PCIE_PHY_REF_SEL_PPLL,
+ CLK_PCIE_PHY2_PLL_DIV_SHIFT = 0,
+ CLK_PCIE_PHY2_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY2_PLL_DIV_SHIFT,
+
+ /* PMUCRU_CLK_SEL2_CON */
+ CLK_PMU1PWM_SEL_SHIFT = 9,
+ CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT,
+
+ /* PMUCRU_CLK_SEL3_CON */
+ CLK_I2C0_SEL_SHIFT = 6,
+ CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT,
+ CLK_I2C_SEL_200M = 0,
+ CLK_I2C_SEL_100M,
+};
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 03/16] arm: rockchip: Add grf header for rk3588
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 01/16] rockchip: mkimage: Add rk3588 support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 02/16] arm: rockchip: Add cru header for rk3588 Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 04/16] dt-bindings: clk: Add dt-binding header for RK3588 Jagan Teki
` (13 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Add GRF header for Rockchip RK3588.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../include/asm/arch-rockchip/grf_rk3588.h | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3588.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
new file mode 100644
index 0000000000..e0694068bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3588_GRF_H__
+#define __SOC_ROCKCHIP_RK3588_GRF_H__
+
+struct rk3588_pmu1grf {
+ unsigned int soc_con[12];
+ unsigned int reserved0[(0x0050 - 0x002c) / 4 - 1];
+ unsigned int biu_con;
+ unsigned int biu_sts;
+ unsigned int reserved1[(0x0060 - 0x0054) / 4 - 1];
+ unsigned int soc_sts;
+ unsigned int reserved2[(0x0080 - 0x0060) / 4 - 1];
+ unsigned int mem_con[4];
+ unsigned int reserved3[(0x0200 - 0x008c) / 4 - 1];
+ unsigned int os_reg[8];
+ unsigned int reserved4[(0x0230 - 0x021c) / 4 - 1];
+ unsigned int rst_sts;
+ unsigned int rst_clr;
+ unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
+ unsigned int sd_detect_con;
+ unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
+ unsigned int sd_detect_sts;
+ unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
+ unsigned int sd_detect_clr;
+ unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
+ unsigned int sd_detect_cnt;
+};
+
+check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0);
+
+#endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 04/16] dt-bindings: clk: Add dt-binding header for RK3588
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (2 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 03/16] arm: rockchip: Add grf " Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 05/16] clk: rockchip: Add rk3588 clk support Jagan Teki
` (12 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Add the dt-bindings header for the Rockchip RK3588, that gets
shared between the clock controller and the clock references
in the dts.
commit <f204a60e545c> ("dt-bindings: clock: add rk3588 clock
definitions")
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++++++++++++++++
1 file changed, 766 insertions(+)
create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h
diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h
new file mode 100644
index 0000000000..b5616bca7b
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
@@ -0,0 +1,766 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2022 Collabora Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
+
+/* cru-clocks indices */
+
+#define PLL_B0PLL 0
+#define PLL_B1PLL 1
+#define PLL_LPLL 2
+#define PLL_V0PLL 3
+#define PLL_AUPLL 4
+#define PLL_CPLL 5
+#define PLL_GPLL 6
+#define PLL_NPLL 7
+#define PLL_PPLL 8
+#define ARMCLK_L 9
+#define ARMCLK_B01 10
+#define ARMCLK_B23 11
+#define PCLK_BIGCORE0_ROOT 12
+#define PCLK_BIGCORE0_PVTM 13
+#define PCLK_BIGCORE1_ROOT 14
+#define PCLK_BIGCORE1_PVTM 15
+#define PCLK_DSU_S_ROOT 16
+#define PCLK_DSU_ROOT 17
+#define PCLK_DSU_NS_ROOT 18
+#define PCLK_LITCORE_PVTM 19
+#define PCLK_DBG 20
+#define PCLK_DSU 21
+#define PCLK_S_DAPLITE 22
+#define PCLK_M_DAPLITE 23
+#define MBIST_MCLK_PDM1 24
+#define MBIST_CLK_ACDCDIG 25
+#define HCLK_I2S2_2CH 26
+#define HCLK_I2S3_2CH 27
+#define CLK_I2S2_2CH_SRC 28
+#define CLK_I2S2_2CH_FRAC 29
+#define CLK_I2S2_2CH 30
+#define MCLK_I2S2_2CH 31
+#define I2S2_2CH_MCLKOUT 32
+#define CLK_DAC_ACDCDIG 33
+#define CLK_I2S3_2CH_SRC 34
+#define CLK_I2S3_2CH_FRAC 35
+#define CLK_I2S3_2CH 36
+#define MCLK_I2S3_2CH 37
+#define I2S3_2CH_MCLKOUT 38
+#define PCLK_ACDCDIG 39
+#define HCLK_I2S0_8CH 40
+#define CLK_I2S0_8CH_TX_SRC 41
+#define CLK_I2S0_8CH_TX_FRAC 42
+#define MCLK_I2S0_8CH_TX 43
+#define CLK_I2S0_8CH_TX 44
+#define CLK_I2S0_8CH_RX_SRC 45
+#define CLK_I2S0_8CH_RX_FRAC 46
+#define MCLK_I2S0_8CH_RX 47
+#define CLK_I2S0_8CH_RX 48
+#define I2S0_8CH_MCLKOUT 49
+#define HCLK_PDM1 50
+#define MCLK_PDM1 51
+#define HCLK_AUDIO_ROOT 52
+#define PCLK_AUDIO_ROOT 53
+#define HCLK_SPDIF0 54
+#define CLK_SPDIF0_SRC 55
+#define CLK_SPDIF0_FRAC 56
+#define MCLK_SPDIF0 57
+#define CLK_SPDIF0 58
+#define CLK_SPDIF1 59
+#define HCLK_SPDIF1 60
+#define CLK_SPDIF1_SRC 61
+#define CLK_SPDIF1_FRAC 62
+#define MCLK_SPDIF1 63
+#define ACLK_AV1_ROOT 64
+#define ACLK_AV1 65
+#define PCLK_AV1_ROOT 66
+#define PCLK_AV1 67
+#define PCLK_MAILBOX0 68
+#define PCLK_MAILBOX1 69
+#define PCLK_MAILBOX2 70
+#define PCLK_PMU2 71
+#define PCLK_PMUCM0_INTMUX 72
+#define PCLK_DDRCM0_INTMUX 73
+#define PCLK_TOP 74
+#define PCLK_PWM1 75
+#define CLK_PWM1 76
+#define CLK_PWM1_CAPTURE 77
+#define PCLK_PWM2 78
+#define CLK_PWM2 79
+#define CLK_PWM2_CAPTURE 80
+#define PCLK_PWM3 81
+#define CLK_PWM3 82
+#define CLK_PWM3_CAPTURE 83
+#define PCLK_BUSTIMER0 84
+#define PCLK_BUSTIMER1 85
+#define CLK_BUS_TIMER_ROOT 86
+#define CLK_BUSTIMER0 87
+#define CLK_BUSTIMER1 88
+#define CLK_BUSTIMER2 89
+#define CLK_BUSTIMER3 90
+#define CLK_BUSTIMER4 91
+#define CLK_BUSTIMER5 92
+#define CLK_BUSTIMER6 93
+#define CLK_BUSTIMER7 94
+#define CLK_BUSTIMER8 95
+#define CLK_BUSTIMER9 96
+#define CLK_BUSTIMER10 97
+#define CLK_BUSTIMER11 98
+#define PCLK_WDT0 99
+#define TCLK_WDT0 100
+#define PCLK_CAN0 101
+#define CLK_CAN0 102
+#define PCLK_CAN1 103
+#define CLK_CAN1 104
+#define PCLK_CAN2 105
+#define CLK_CAN2 106
+#define ACLK_DECOM 107
+#define PCLK_DECOM 108
+#define DCLK_DECOM 109
+#define ACLK_DMAC0 110
+#define ACLK_DMAC1 111
+#define ACLK_DMAC2 112
+#define ACLK_BUS_ROOT 113
+#define ACLK_GIC 114
+#define PCLK_GPIO1 115
+#define DBCLK_GPIO1 116
+#define PCLK_GPIO2 117
+#define DBCLK_GPIO2 118
+#define PCLK_GPIO3 119
+#define DBCLK_GPIO3 120
+#define PCLK_GPIO4 121
+#define DBCLK_GPIO4 122
+#define PCLK_I2C1 123
+#define PCLK_I2C2 124
+#define PCLK_I2C3 125
+#define PCLK_I2C4 126
+#define PCLK_I2C5 127
+#define PCLK_I2C6 128
+#define PCLK_I2C7 129
+#define PCLK_I2C8 130
+#define CLK_I2C1 131
+#define CLK_I2C2 132
+#define CLK_I2C3 133
+#define CLK_I2C4 134
+#define CLK_I2C5 135
+#define CLK_I2C6 136
+#define CLK_I2C7 137
+#define CLK_I2C8 138
+#define PCLK_OTPC_NS 139
+#define CLK_OTPC_NS 140
+#define CLK_OTPC_ARB 141
+#define CLK_OTPC_AUTO_RD_G 142
+#define CLK_OTP_PHY_G 143
+#define PCLK_SARADC 144
+#define CLK_SARADC 145
+#define PCLK_SPI0 146
+#define PCLK_SPI1 147
+#define PCLK_SPI2 148
+#define PCLK_SPI3 149
+#define PCLK_SPI4 150
+#define CLK_SPI0 151
+#define CLK_SPI1 152
+#define CLK_SPI2 153
+#define CLK_SPI3 154
+#define CLK_SPI4 155
+#define ACLK_SPINLOCK 156
+#define PCLK_TSADC 157
+#define CLK_TSADC 158
+#define PCLK_UART1 159
+#define PCLK_UART2 160
+#define PCLK_UART3 161
+#define PCLK_UART4 162
+#define PCLK_UART5 163
+#define PCLK_UART6 164
+#define PCLK_UART7 165
+#define PCLK_UART8 166
+#define PCLK_UART9 167
+#define CLK_UART1_SRC 168
+#define CLK_UART1_FRAC 169
+#define CLK_UART1 170
+#define SCLK_UART1 171
+#define CLK_UART2_SRC 172
+#define CLK_UART2_FRAC 173
+#define CLK_UART2 174
+#define SCLK_UART2 175
+#define CLK_UART3_SRC 176
+#define CLK_UART3_FRAC 177
+#define CLK_UART3 178
+#define SCLK_UART3 179
+#define CLK_UART4_SRC 180
+#define CLK_UART4_FRAC 181
+#define CLK_UART4 182
+#define SCLK_UART4 183
+#define CLK_UART5_SRC 184
+#define CLK_UART5_FRAC 185
+#define CLK_UART5 186
+#define SCLK_UART5 187
+#define CLK_UART6_SRC 188
+#define CLK_UART6_FRAC 189
+#define CLK_UART6 190
+#define SCLK_UART6 191
+#define CLK_UART7_SRC 192
+#define CLK_UART7_FRAC 193
+#define CLK_UART7 194
+#define SCLK_UART7 195
+#define CLK_UART8_SRC 196
+#define CLK_UART8_FRAC 197
+#define CLK_UART8 198
+#define SCLK_UART8 199
+#define CLK_UART9_SRC 200
+#define CLK_UART9_FRAC 201
+#define CLK_UART9 202
+#define SCLK_UART9 203
+#define ACLK_CENTER_ROOT 204
+#define ACLK_CENTER_LOW_ROOT 205
+#define HCLK_CENTER_ROOT 206
+#define PCLK_CENTER_ROOT 207
+#define ACLK_DMA2DDR 208
+#define ACLK_DDR_SHAREMEM 209
+#define ACLK_CENTER_S200_ROOT 210
+#define ACLK_CENTER_S400_ROOT 211
+#define FCLK_DDR_CM0_CORE 212
+#define CLK_DDR_TIMER_ROOT 213
+#define CLK_DDR_TIMER0 214
+#define CLK_DDR_TIMER1 215
+#define TCLK_WDT_DDR 216
+#define CLK_DDR_CM0_RTC 217
+#define PCLK_WDT 218
+#define PCLK_TIMER 219
+#define PCLK_DMA2DDR 220
+#define PCLK_SHAREMEM 221
+#define CLK_50M_SRC 222
+#define CLK_100M_SRC 223
+#define CLK_150M_SRC 224
+#define CLK_200M_SRC 225
+#define CLK_250M_SRC 226
+#define CLK_300M_SRC 227
+#define CLK_350M_SRC 228
+#define CLK_400M_SRC 229
+#define CLK_450M_SRC 230
+#define CLK_500M_SRC 231
+#define CLK_600M_SRC 232
+#define CLK_650M_SRC 233
+#define CLK_700M_SRC 234
+#define CLK_800M_SRC 235
+#define CLK_1000M_SRC 236
+#define CLK_1200M_SRC 237
+#define ACLK_TOP_M300_ROOT 238
+#define ACLK_TOP_M500_ROOT 239
+#define ACLK_TOP_M400_ROOT 240
+#define ACLK_TOP_S200_ROOT 241
+#define ACLK_TOP_S400_ROOT 242
+#define CLK_MIPI_CAMARAOUT_M0 243
+#define CLK_MIPI_CAMARAOUT_M1 244
+#define CLK_MIPI_CAMARAOUT_M2 245
+#define CLK_MIPI_CAMARAOUT_M3 246
+#define CLK_MIPI_CAMARAOUT_M4 247
+#define MCLK_GMAC0_OUT 248
+#define REFCLKO25M_ETH0_OUT 249
+#define REFCLKO25M_ETH1_OUT 250
+#define CLK_CIFOUT_OUT 251
+#define PCLK_MIPI_DCPHY0 252
+#define PCLK_MIPI_DCPHY1 253
+#define PCLK_CSIPHY0 254
+#define PCLK_CSIPHY1 255
+#define ACLK_TOP_ROOT 256
+#define PCLK_TOP_ROOT 257
+#define ACLK_LOW_TOP_ROOT 258
+#define PCLK_CRU 259
+#define PCLK_GPU_ROOT 260
+#define CLK_GPU_SRC 261
+#define CLK_GPU 262
+#define CLK_GPU_COREGROUP 263
+#define CLK_GPU_STACKS 264
+#define PCLK_GPU_PVTM 265
+#define CLK_GPU_PVTM 266
+#define CLK_CORE_GPU_PVTM 267
+#define PCLK_GPU_GRF 268
+#define ACLK_ISP1_ROOT 269
+#define HCLK_ISP1_ROOT 270
+#define CLK_ISP1_CORE 271
+#define CLK_ISP1_CORE_MARVIN 272
+#define CLK_ISP1_CORE_VICAP 273
+#define ACLK_ISP1 274
+#define HCLK_ISP1 275
+#define ACLK_NPU1 276
+#define HCLK_NPU1 277
+#define ACLK_NPU2 278
+#define HCLK_NPU2 279
+#define HCLK_NPU_CM0_ROOT 280
+#define FCLK_NPU_CM0_CORE 281
+#define CLK_NPU_CM0_RTC 282
+#define PCLK_NPU_PVTM 283
+#define PCLK_NPU_GRF 284
+#define CLK_NPU_PVTM 285
+#define CLK_CORE_NPU_PVTM 286
+#define ACLK_NPU0 287
+#define HCLK_NPU0 288
+#define HCLK_NPU_ROOT 289
+#define CLK_NPU_DSU0 290
+#define PCLK_NPU_ROOT 291
+#define PCLK_NPU_TIMER 292
+#define CLK_NPUTIMER_ROOT 293
+#define CLK_NPUTIMER0 294
+#define CLK_NPUTIMER1 295
+#define PCLK_NPU_WDT 296
+#define TCLK_NPU_WDT 297
+#define HCLK_EMMC 298
+#define ACLK_EMMC 299
+#define CCLK_EMMC 300
+#define BCLK_EMMC 301
+#define TMCLK_EMMC 302
+#define SCLK_SFC 303
+#define HCLK_SFC 304
+#define HCLK_SFC_XIP 305
+#define HCLK_NVM_ROOT 306
+#define ACLK_NVM_ROOT 307
+#define CLK_GMAC0_PTP_REF 308
+#define CLK_GMAC1_PTP_REF 309
+#define CLK_GMAC_125M 310
+#define CLK_GMAC_50M 311
+#define ACLK_PHP_GIC_ITS 312
+#define ACLK_MMU_PCIE 313
+#define ACLK_MMU_PHP 314
+#define ACLK_PCIE_4L_DBI 315
+#define ACLK_PCIE_2L_DBI 316
+#define ACLK_PCIE_1L0_DBI 317
+#define ACLK_PCIE_1L1_DBI 318
+#define ACLK_PCIE_1L2_DBI 319
+#define ACLK_PCIE_4L_MSTR 320
+#define ACLK_PCIE_2L_MSTR 321
+#define ACLK_PCIE_1L0_MSTR 322
+#define ACLK_PCIE_1L1_MSTR 323
+#define ACLK_PCIE_1L2_MSTR 324
+#define ACLK_PCIE_4L_SLV 325
+#define ACLK_PCIE_2L_SLV 326
+#define ACLK_PCIE_1L0_SLV 327
+#define ACLK_PCIE_1L1_SLV 328
+#define ACLK_PCIE_1L2_SLV 329
+#define PCLK_PCIE_4L 330
+#define PCLK_PCIE_2L 331
+#define PCLK_PCIE_1L0 332
+#define PCLK_PCIE_1L1 333
+#define PCLK_PCIE_1L2 334
+#define CLK_PCIE_AUX0 335
+#define CLK_PCIE_AUX1 336
+#define CLK_PCIE_AUX2 337
+#define CLK_PCIE_AUX3 338
+#define CLK_PCIE_AUX4 339
+#define CLK_PIPEPHY0_REF 340
+#define CLK_PIPEPHY1_REF 341
+#define CLK_PIPEPHY2_REF 342
+#define PCLK_PHP_ROOT 343
+#define PCLK_GMAC0 344
+#define PCLK_GMAC1 345
+#define ACLK_PCIE_ROOT 346
+#define ACLK_PHP_ROOT 347
+#define ACLK_PCIE_BRIDGE 348
+#define ACLK_GMAC0 349
+#define ACLK_GMAC1 350
+#define CLK_PMALIVE0 351
+#define CLK_PMALIVE1 352
+#define CLK_PMALIVE2 353
+#define ACLK_SATA0 354
+#define ACLK_SATA1 355
+#define ACLK_SATA2 356
+#define CLK_RXOOB0 357
+#define CLK_RXOOB1 358
+#define CLK_RXOOB2 359
+#define ACLK_USB3OTG2 360
+#define SUSPEND_CLK_USB3OTG2 361
+#define REF_CLK_USB3OTG2 362
+#define CLK_UTMI_OTG2 363
+#define CLK_PIPEPHY0_PIPE_G 364
+#define CLK_PIPEPHY1_PIPE_G 365
+#define CLK_PIPEPHY2_PIPE_G 366
+#define CLK_PIPEPHY0_PIPE_ASIC_G 367
+#define CLK_PIPEPHY1_PIPE_ASIC_G 368
+#define CLK_PIPEPHY2_PIPE_ASIC_G 369
+#define CLK_PIPEPHY2_PIPE_U3_G 370
+#define CLK_PCIE1L2_PIPE 371
+#define CLK_PCIE4L_PIPE 372
+#define CLK_PCIE2L_PIPE 373
+#define PCLK_PCIE_COMBO_PIPE_PHY0 374
+#define PCLK_PCIE_COMBO_PIPE_PHY1 375
+#define PCLK_PCIE_COMBO_PIPE_PHY2 376
+#define PCLK_PCIE_COMBO_PIPE_PHY 377
+#define HCLK_RGA3_1 378
+#define ACLK_RGA3_1 379
+#define CLK_RGA3_1_CORE 380
+#define ACLK_RGA3_ROOT 381
+#define HCLK_RGA3_ROOT 382
+#define ACLK_RKVDEC_CCU 383
+#define HCLK_RKVDEC0 384
+#define ACLK_RKVDEC0 385
+#define CLK_RKVDEC0_CA 386
+#define CLK_RKVDEC0_HEVC_CA 387
+#define CLK_RKVDEC0_CORE 388
+#define HCLK_RKVDEC1 389
+#define ACLK_RKVDEC1 390
+#define CLK_RKVDEC1_CA 391
+#define CLK_RKVDEC1_HEVC_CA 392
+#define CLK_RKVDEC1_CORE 393
+#define HCLK_SDIO 394
+#define CCLK_SRC_SDIO 395
+#define ACLK_USB_ROOT 396
+#define HCLK_USB_ROOT 397
+#define HCLK_HOST0 398
+#define HCLK_HOST_ARB0 399
+#define HCLK_HOST1 400
+#define HCLK_HOST_ARB1 401
+#define ACLK_USB3OTG0 402
+#define SUSPEND_CLK_USB3OTG0 403
+#define REF_CLK_USB3OTG0 404
+#define ACLK_USB3OTG1 405
+#define SUSPEND_CLK_USB3OTG1 406
+#define REF_CLK_USB3OTG1 407
+#define UTMI_OHCI_CLK48_HOST0 408
+#define UTMI_OHCI_CLK48_HOST1 409
+#define HCLK_IEP2P0 410
+#define ACLK_IEP2P0 411
+#define CLK_IEP2P0_CORE 412
+#define ACLK_JPEG_ENCODER0 413
+#define HCLK_JPEG_ENCODER0 414
+#define ACLK_JPEG_ENCODER1 415
+#define HCLK_JPEG_ENCODER1 416
+#define ACLK_JPEG_ENCODER2 417
+#define HCLK_JPEG_ENCODER2 418
+#define ACLK_JPEG_ENCODER3 419
+#define HCLK_JPEG_ENCODER3 420
+#define ACLK_JPEG_DECODER 421
+#define HCLK_JPEG_DECODER 422
+#define HCLK_RGA2 423
+#define ACLK_RGA2 424
+#define CLK_RGA2_CORE 425
+#define HCLK_RGA3_0 426
+#define ACLK_RGA3_0 427
+#define CLK_RGA3_0_CORE 428
+#define ACLK_VDPU_ROOT 429
+#define ACLK_VDPU_LOW_ROOT 430
+#define HCLK_VDPU_ROOT 431
+#define ACLK_JPEG_DECODER_ROOT 432
+#define ACLK_VPU 433
+#define HCLK_VPU 434
+#define HCLK_RKVENC0_ROOT 435
+#define ACLK_RKVENC0_ROOT 436
+#define HCLK_RKVENC0 437
+#define ACLK_RKVENC0 438
+#define CLK_RKVENC0_CORE 439
+#define HCLK_RKVENC1_ROOT 440
+#define ACLK_RKVENC1_ROOT 441
+#define HCLK_RKVENC1 442
+#define ACLK_RKVENC1 443
+#define CLK_RKVENC1_CORE 444
+#define ICLK_CSIHOST01 445
+#define ICLK_CSIHOST0 446
+#define ICLK_CSIHOST1 447
+#define PCLK_CSI_HOST_0 448
+#define PCLK_CSI_HOST_1 449
+#define PCLK_CSI_HOST_2 450
+#define PCLK_CSI_HOST_3 451
+#define PCLK_CSI_HOST_4 452
+#define PCLK_CSI_HOST_5 453
+#define ACLK_FISHEYE0 454
+#define HCLK_FISHEYE0 455
+#define CLK_FISHEYE0_CORE 456
+#define ACLK_FISHEYE1 457
+#define HCLK_FISHEYE1 458
+#define CLK_FISHEYE1_CORE 459
+#define CLK_ISP0_CORE 460
+#define CLK_ISP0_CORE_MARVIN 461
+#define CLK_ISP0_CORE_VICAP 462
+#define ACLK_ISP0 463
+#define HCLK_ISP0 464
+#define ACLK_VI_ROOT 465
+#define HCLK_VI_ROOT 466
+#define PCLK_VI_ROOT 467
+#define DCLK_VICAP 468
+#define ACLK_VICAP 469
+#define HCLK_VICAP 470
+#define PCLK_DP0 471
+#define PCLK_DP1 472
+#define PCLK_S_DP0 473
+#define PCLK_S_DP1 474
+#define CLK_DP0 475
+#define CLK_DP1 476
+#define HCLK_HDCP_KEY0 477
+#define ACLK_HDCP0 478
+#define HCLK_HDCP0 479
+#define PCLK_HDCP0 480
+#define HCLK_I2S4_8CH 481
+#define ACLK_TRNG0 482
+#define PCLK_TRNG0 483
+#define ACLK_VO0_ROOT 484
+#define HCLK_VO0_ROOT 485
+#define HCLK_VO0_S_ROOT 486
+#define PCLK_VO0_ROOT 487
+#define PCLK_VO0_S_ROOT 488
+#define PCLK_VO0GRF 489
+#define CLK_I2S4_8CH_TX_SRC 490
+#define CLK_I2S4_8CH_TX_FRAC 491
+#define MCLK_I2S4_8CH_TX 492
+#define CLK_I2S4_8CH_TX 493
+#define HCLK_I2S8_8CH 494
+#define CLK_I2S8_8CH_TX_SRC 495
+#define CLK_I2S8_8CH_TX_FRAC 496
+#define MCLK_I2S8_8CH_TX 497
+#define CLK_I2S8_8CH_TX 498
+#define HCLK_SPDIF2_DP0 499
+#define CLK_SPDIF2_DP0_SRC 500
+#define CLK_SPDIF2_DP0_FRAC 501
+#define MCLK_SPDIF2_DP0 502
+#define CLK_SPDIF2_DP0 503
+#define MCLK_SPDIF2 504
+#define HCLK_SPDIF5_DP1 505
+#define CLK_SPDIF5_DP1_SRC 506
+#define CLK_SPDIF5_DP1_FRAC 507
+#define MCLK_SPDIF5_DP1 508
+#define CLK_SPDIF5_DP1 509
+#define MCLK_SPDIF5 510
+#define PCLK_EDP0 511
+#define CLK_EDP0_24M 512
+#define CLK_EDP0_200M 513
+#define PCLK_EDP1 514
+#define CLK_EDP1_24M 515
+#define CLK_EDP1_200M 516
+#define HCLK_HDCP_KEY1 517
+#define ACLK_HDCP1 518
+#define HCLK_HDCP1 519
+#define PCLK_HDCP1 520
+#define ACLK_HDMIRX 521
+#define PCLK_HDMIRX 522
+#define CLK_HDMIRX_REF 523
+#define CLK_HDMIRX_AUD_SRC 524
+#define CLK_HDMIRX_AUD_FRAC 525
+#define CLK_HDMIRX_AUD 526
+#define CLK_HDMIRX_AUD_P_MUX 527
+#define PCLK_HDMITX0 528
+#define CLK_HDMITX0_EARC 529
+#define CLK_HDMITX0_REF 530
+#define PCLK_HDMITX1 531
+#define CLK_HDMITX1_EARC 532
+#define CLK_HDMITX1_REF 533
+#define CLK_HDMITRX_REFSRC 534
+#define ACLK_TRNG1 535
+#define PCLK_TRNG1 536
+#define ACLK_HDCP1_ROOT 537
+#define ACLK_HDMIRX_ROOT 538
+#define HCLK_VO1_ROOT 539
+#define HCLK_VO1_S_ROOT 540
+#define PCLK_VO1_ROOT 541
+#define PCLK_VO1_S_ROOT 542
+#define PCLK_S_EDP0 543
+#define PCLK_S_EDP1 544
+#define PCLK_S_HDMIRX 545
+#define HCLK_I2S10_8CH 546
+#define CLK_I2S10_8CH_RX_SRC 547
+#define CLK_I2S10_8CH_RX_FRAC 548
+#define CLK_I2S10_8CH_RX 549
+#define MCLK_I2S10_8CH_RX 550
+#define HCLK_I2S7_8CH 551
+#define CLK_I2S7_8CH_RX_SRC 552
+#define CLK_I2S7_8CH_RX_FRAC 553
+#define CLK_I2S7_8CH_RX 554
+#define MCLK_I2S7_8CH_RX 555
+#define HCLK_I2S9_8CH 556
+#define CLK_I2S9_8CH_RX_SRC 557
+#define CLK_I2S9_8CH_RX_FRAC 558
+#define CLK_I2S9_8CH_RX 559
+#define MCLK_I2S9_8CH_RX 560
+#define CLK_I2S5_8CH_TX_SRC 561
+#define CLK_I2S5_8CH_TX_FRAC 562
+#define CLK_I2S5_8CH_TX 563
+#define MCLK_I2S5_8CH_TX 564
+#define HCLK_I2S5_8CH 565
+#define CLK_I2S6_8CH_TX_SRC 566
+#define CLK_I2S6_8CH_TX_FRAC 567
+#define CLK_I2S6_8CH_TX 568
+#define MCLK_I2S6_8CH_TX 569
+#define CLK_I2S6_8CH_RX_SRC 570
+#define CLK_I2S6_8CH_RX_FRAC 571
+#define CLK_I2S6_8CH_RX 572
+#define MCLK_I2S6_8CH_RX 573
+#define I2S6_8CH_MCLKOUT 574
+#define HCLK_I2S6_8CH 575
+#define HCLK_SPDIF3 576
+#define CLK_SPDIF3_SRC 577
+#define CLK_SPDIF3_FRAC 578
+#define CLK_SPDIF3 579
+#define MCLK_SPDIF3 580
+#define HCLK_SPDIF4 581
+#define CLK_SPDIF4_SRC 582
+#define CLK_SPDIF4_FRAC 583
+#define CLK_SPDIF4 584
+#define MCLK_SPDIF4 585
+#define HCLK_SPDIFRX0 586
+#define MCLK_SPDIFRX0 587
+#define HCLK_SPDIFRX1 588
+#define MCLK_SPDIFRX1 589
+#define HCLK_SPDIFRX2 590
+#define MCLK_SPDIFRX2 591
+#define ACLK_VO1USB_TOP_ROOT 592
+#define HCLK_VO1USB_TOP_ROOT 593
+#define CLK_HDMIHDP0 594
+#define CLK_HDMIHDP1 595
+#define PCLK_HDPTX0 596
+#define PCLK_HDPTX1 597
+#define PCLK_USBDPPHY0 598
+#define PCLK_USBDPPHY1 599
+#define ACLK_VOP_ROOT 600
+#define ACLK_VOP_LOW_ROOT 601
+#define HCLK_VOP_ROOT 602
+#define PCLK_VOP_ROOT 603
+#define HCLK_VOP 604
+#define ACLK_VOP 605
+#define DCLK_VOP0_SRC 606
+#define DCLK_VOP1_SRC 607
+#define DCLK_VOP2_SRC 608
+#define DCLK_VOP0 609
+#define DCLK_VOP1 610
+#define DCLK_VOP2 611
+#define DCLK_VOP3 612
+#define PCLK_DSIHOST0 613
+#define PCLK_DSIHOST1 614
+#define CLK_DSIHOST0 615
+#define CLK_DSIHOST1 616
+#define CLK_VOP_PMU 617
+#define ACLK_VOP_DOBY 618
+#define ACLK_VOP_SUB_SRC 619
+#define CLK_USBDP_PHY0_IMMORTAL 620
+#define CLK_USBDP_PHY1_IMMORTAL 621
+#define CLK_PMU0 622
+#define PCLK_PMU0 623
+#define PCLK_PMU0IOC 624
+#define PCLK_GPIO0 625
+#define DBCLK_GPIO0 626
+#define PCLK_I2C0 627
+#define CLK_I2C0 628
+#define HCLK_I2S1_8CH 629
+#define CLK_I2S1_8CH_TX_SRC 630
+#define CLK_I2S1_8CH_TX_FRAC 631
+#define CLK_I2S1_8CH_TX 632
+#define MCLK_I2S1_8CH_TX 633
+#define CLK_I2S1_8CH_RX_SRC 634
+#define CLK_I2S1_8CH_RX_FRAC 635
+#define CLK_I2S1_8CH_RX 636
+#define MCLK_I2S1_8CH_RX 637
+#define I2S1_8CH_MCLKOUT 638
+#define CLK_PMU1_50M_SRC 639
+#define CLK_PMU1_100M_SRC 640
+#define CLK_PMU1_200M_SRC 641
+#define CLK_PMU1_300M_SRC 642
+#define CLK_PMU1_400M_SRC 643
+#define HCLK_PMU1_ROOT 644
+#define PCLK_PMU1_ROOT 645
+#define PCLK_PMU0_ROOT 646
+#define HCLK_PMU_CM0_ROOT 647
+#define PCLK_PMU1 648
+#define CLK_DDR_FAIL_SAFE 649
+#define CLK_PMU1 650
+#define HCLK_PDM0 651
+#define MCLK_PDM0 652
+#define HCLK_VAD 653
+#define FCLK_PMU_CM0_CORE 654
+#define CLK_PMU_CM0_RTC 655
+#define PCLK_PMU1_IOC 656
+#define PCLK_PMU1PWM 657
+#define CLK_PMU1PWM 658
+#define CLK_PMU1PWM_CAPTURE 659
+#define PCLK_PMU1TIMER 660
+#define CLK_PMU1TIMER_ROOT 661
+#define CLK_PMU1TIMER0 662
+#define CLK_PMU1TIMER1 663
+#define CLK_UART0_SRC 664
+#define CLK_UART0_FRAC 665
+#define CLK_UART0 666
+#define SCLK_UART0 667
+#define PCLK_UART0 668
+#define PCLK_PMU1WDT 669
+#define TCLK_PMU1WDT 670
+#define CLK_CR_PARA 671
+#define CLK_USB2PHY_HDPTXRXPHY_REF 672
+#define CLK_USBDPPHY_MIPIDCPPHY_REF 673
+#define CLK_REF_PIPE_PHY0_OSC_SRC 674
+#define CLK_REF_PIPE_PHY1_OSC_SRC 675
+#define CLK_REF_PIPE_PHY2_OSC_SRC 676
+#define CLK_REF_PIPE_PHY0_PLL_SRC 677
+#define CLK_REF_PIPE_PHY1_PLL_SRC 678
+#define CLK_REF_PIPE_PHY2_PLL_SRC 679
+#define CLK_REF_PIPE_PHY0 680
+#define CLK_REF_PIPE_PHY1 681
+#define CLK_REF_PIPE_PHY2 682
+#define SCLK_SDIO_DRV 683
+#define SCLK_SDIO_SAMPLE 684
+#define SCLK_SDMMC_DRV 685
+#define SCLK_SDMMC_SAMPLE 686
+#define CLK_PCIE1L0_PIPE 687
+#define CLK_PCIE1L1_PIPE 688
+#define CLK_BIGCORE0_PVTM 689
+#define CLK_CORE_BIGCORE0_PVTM 690
+#define CLK_BIGCORE1_PVTM 691
+#define CLK_CORE_BIGCORE1_PVTM 692
+#define CLK_LITCORE_PVTM 693
+#define CLK_CORE_LITCORE_PVTM 694
+#define CLK_AUX16M_0 695
+#define CLK_AUX16M_1 696
+#define CLK_PHY0_REF_ALT_P 697
+#define CLK_PHY0_REF_ALT_M 698
+#define CLK_PHY1_REF_ALT_P 699
+#define CLK_PHY1_REF_ALT_M 700
+#define ACLK_ISP1_PRE 701
+#define HCLK_ISP1_PRE 702
+#define HCLK_NVM 703
+#define ACLK_USB 704
+#define HCLK_USB 705
+#define ACLK_JPEG_DECODER_PRE 706
+#define ACLK_VDPU_LOW_PRE 707
+#define ACLK_RKVENC1_PRE 708
+#define HCLK_RKVENC1_PRE 709
+#define HCLK_RKVDEC0_PRE 710
+#define ACLK_RKVDEC0_PRE 711
+#define HCLK_RKVDEC1_PRE 712
+#define ACLK_RKVDEC1_PRE 713
+#define ACLK_HDCP0_PRE 714
+#define HCLK_VO0 715
+#define ACLK_HDCP1_PRE 716
+#define HCLK_VO1 717
+#define ACLK_AV1_PRE 718
+#define PCLK_AV1_PRE 719
+#define HCLK_SDIO_PRE 720
+
+#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
+
+/* scmi-clocks indices */
+
+#define SCMI_CLK_CPUL 0
+#define SCMI_CLK_DSU 1
+#define SCMI_CLK_CPUB01 2
+#define SCMI_CLK_CPUB23 3
+#define SCMI_CLK_DDR 4
+#define SCMI_CLK_GPU 5
+#define SCMI_CLK_NPU 6
+#define SCMI_CLK_SBUS 7
+#define SCMI_PCLK_SBUS 8
+#define SCMI_CCLK_SD 9
+#define SCMI_DCLK_SD 10
+#define SCMI_ACLK_SECURE_NS 11
+#define SCMI_HCLK_SECURE_NS 12
+#define SCMI_TCLK_WDT 13
+#define SCMI_KEYLADDER_CORE 14
+#define SCMI_KEYLADDER_RNG 15
+#define SCMI_ACLK_SECURE_S 16
+#define SCMI_HCLK_SECURE_S 17
+#define SCMI_PCLK_SECURE_S 18
+#define SCMI_CRYPTO_RNG 19
+#define SCMI_CRYPTO_CORE 20
+#define SCMI_CRYPTO_PKA 21
+#define SCMI_SPLL 22
+#define SCMI_HCLK_SD 23
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 05/16] clk: rockchip: Add rk3588 clk support
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (3 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 04/16] dt-bindings: clk: Add dt-binding header for RK3588 Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-02-02 14:09 ` Eugen Hristev
2023-01-25 22:27 ` [RFC PATCH 06/16] clk: rockchip: pll: Add pll_rk3588 type for rk3588 Jagan Teki
` (11 subsequent siblings)
16 siblings, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Elaine Zhang
Add clock driver support for Rockchip RK3588 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3588.c | 2019 +++++++++++++++++++++++++++++
2 files changed, 2020 insertions(+)
create mode 100644 drivers/clk/rockchip/clk_rk3588.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index f719f4e379..9e379cc2e3 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -16,5 +16,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
new file mode 100644
index 0000000000..55532b5c2a
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -0,0 +1,2019 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <common.h>
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/cru_rk3588.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rockchip,rk3588-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
+ /* _mhz, _p, _m, _s, _k */
+ RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
+ RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
+ RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
+ RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
+ RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
+ RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
+ RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
+ RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
+ RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
+ RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
+ RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+ RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
+ RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
+ RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
+ RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3588_pll_clks[] = {
+ [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0),
+ RK3588_B0_PLL_MODE_CON, 0, 15, 0,
+ rk3588_pll_rates),
+ [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8),
+ RK3588_B1_PLL_MODE_CON, 0, 15, 0,
+ rk3588_pll_rates),
+ [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16),
+ RK3588_LPLL_MODE_CON, 0, 15, 0, rk3588_pll_rates),
+ [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
+ RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
+ [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),
+ RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
+ [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
+ RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
+ [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
+ RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
+ [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
+ RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
+ [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
+ RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+};
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+#endif
+
+static ulong rk3588_center_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 con, sel, rate;
+
+ switch (clk_id) {
+ case ACLK_CENTER_ROOT:
+ con = readl(&cru->clksel_con[165]);
+ sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >>
+ ACLK_CENTER_ROOT_SEL_SHIFT;
+ if (sel == ACLK_CENTER_ROOT_SEL_700M)
+ rate = 702 * MHz;
+ else if (sel == ACLK_CENTER_ROOT_SEL_400M)
+ rate = 396 * MHz;
+ else if (sel == ACLK_CENTER_ROOT_SEL_200M)
+ rate = 200 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case ACLK_CENTER_LOW_ROOT:
+ con = readl(&cru->clksel_con[165]);
+ sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >>
+ ACLK_CENTER_LOW_ROOT_SEL_SHIFT;
+ if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M)
+ rate = 500 * MHz;
+ else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M)
+ rate = 250 * MHz;
+ else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case HCLK_CENTER_ROOT:
+ con = readl(&cru->clksel_con[165]);
+ sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >>
+ HCLK_CENTER_ROOT_SEL_SHIFT;
+ if (sel == HCLK_CENTER_ROOT_SEL_400M)
+ rate = 396 * MHz;
+ else if (sel == HCLK_CENTER_ROOT_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == HCLK_CENTER_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case PCLK_CENTER_ROOT:
+ con = readl(&cru->clksel_con[165]);
+ sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >>
+ PCLK_CENTER_ROOT_SEL_SHIFT;
+ if (sel == PCLK_CENTER_ROOT_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == PCLK_CENTER_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == PCLK_CENTER_ROOT_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3588_center_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk;
+
+ switch (clk_id) {
+ case ACLK_CENTER_ROOT:
+ if (rate >= 700 * MHz)
+ src_clk = ACLK_CENTER_ROOT_SEL_700M;
+ else if (rate >= 396 * MHz)
+ src_clk = ACLK_CENTER_ROOT_SEL_400M;
+ else if (rate >= 200 * MHz)
+ src_clk = ACLK_CENTER_ROOT_SEL_200M;
+ else
+ src_clk = ACLK_CENTER_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[165],
+ ACLK_CENTER_ROOT_SEL_MASK,
+ src_clk << ACLK_CENTER_ROOT_SEL_SHIFT);
+ break;
+ case ACLK_CENTER_LOW_ROOT:
+ if (rate >= 500 * MHz)
+ src_clk = ACLK_CENTER_LOW_ROOT_SEL_500M;
+ else if (rate >= 250 * MHz)
+ src_clk = ACLK_CENTER_LOW_ROOT_SEL_250M;
+ else if (rate >= 99 * MHz)
+ src_clk = ACLK_CENTER_LOW_ROOT_SEL_100M;
+ else
+ src_clk = ACLK_CENTER_LOW_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[165],
+ ACLK_CENTER_LOW_ROOT_SEL_MASK,
+ src_clk << ACLK_CENTER_LOW_ROOT_SEL_SHIFT);
+ break;
+ case HCLK_CENTER_ROOT:
+ if (rate >= 396 * MHz)
+ src_clk = HCLK_CENTER_ROOT_SEL_400M;
+ else if (rate >= 198 * MHz)
+ src_clk = HCLK_CENTER_ROOT_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = HCLK_CENTER_ROOT_SEL_100M;
+ else
+ src_clk = HCLK_CENTER_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[165],
+ HCLK_CENTER_ROOT_SEL_MASK,
+ src_clk << HCLK_CENTER_ROOT_SEL_SHIFT);
+ break;
+ case PCLK_CENTER_ROOT:
+ if (rate >= 198 * MHz)
+ src_clk = PCLK_CENTER_ROOT_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = PCLK_CENTER_ROOT_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = PCLK_CENTER_ROOT_SEL_50M;
+ else
+ src_clk = PCLK_CENTER_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[165],
+ PCLK_CENTER_ROOT_SEL_MASK,
+ src_clk << PCLK_CENTER_ROOT_SEL_SHIFT);
+ break;
+ default:
+ printf("do not support this center freq\n");
+ return -EINVAL;
+ }
+
+ return rk3588_center_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_top_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 con, sel, div, rate, prate;
+
+ switch (clk_id) {
+ case ACLK_TOP_ROOT:
+ con = readl(&cru->clksel_con[8]);
+ div = (con & ACLK_TOP_ROOT_DIV_MASK) >>
+ ACLK_TOP_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >>
+ ACLK_TOP_ROOT_SRC_SEL_SHIFT;
+ if (sel == ACLK_TOP_ROOT_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = priv->cpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case ACLK_LOW_TOP_ROOT:
+ con = readl(&cru->clksel_con[8]);
+ div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >>
+ ACLK_LOW_TOP_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >>
+ ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT;
+ if (sel == ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case PCLK_TOP_ROOT:
+ con = readl(&cru->clksel_con[8]);
+ sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT;
+ if (sel == PCLK_TOP_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == PCLK_TOP_ROOT_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk, src_clk_div;
+
+ switch (clk_id) {
+ case ACLK_TOP_ROOT:
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ assert(src_clk_div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[8],
+ ACLK_TOP_ROOT_DIV_MASK |
+ ACLK_TOP_ROOT_SRC_SEL_MASK,
+ (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
+ ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
+ break;
+ case ACLK_LOW_TOP_ROOT:
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ assert(src_clk_div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[8],
+ ACLK_LOW_TOP_ROOT_DIV_MASK |
+ ACLK_LOW_TOP_ROOT_SRC_SEL_MASK,
+ (ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL <<
+ ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_LOW_TOP_ROOT_DIV_SHIFT);
+ break;
+ case PCLK_TOP_ROOT:
+ if (rate == 100 * MHz)
+ src_clk = PCLK_TOP_ROOT_SEL_100M;
+ else if (rate == 50 * MHz)
+ src_clk = PCLK_TOP_ROOT_SEL_50M;
+ else
+ src_clk = PCLK_TOP_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[8],
+ PCLK_TOP_ROOT_SEL_MASK,
+ src_clk << PCLK_TOP_ROOT_SEL_SHIFT);
+ break;
+ default:
+ printf("do not support this top freq\n");
+ return -EINVAL;
+ }
+
+ return rk3588_top_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_i2c_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 sel, con;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ con = readl(&cru->pmuclksel_con[3]);
+ sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;
+ break;
+ case CLK_I2C1:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;
+ break;
+ case CLK_I2C2:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;
+ break;
+ case CLK_I2C3:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;
+ break;
+ case CLK_I2C4:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;
+ break;
+ case CLK_I2C5:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;
+ break;
+ case CLK_I2C6:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;
+ break;
+ case CLK_I2C7:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;
+ break;
+ case CLK_I2C8:
+ con = readl(&cru->clksel_con[38]);
+ sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+ if (sel == CLK_I2C_SEL_200M)
+ rate = 200 * MHz;
+ else
+ rate = 100 * MHz;
+
+ return rate;
+}
+
+static ulong rk3588_i2c_set_clk(struct rk3588_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_I2C_SEL_200M;
+ else
+ src_clk = CLK_I2C_SEL_100M;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ rk_clrsetreg(&cru->pmuclksel_con[3], CLK_I2C0_SEL_MASK,
+ src_clk << CLK_I2C0_SEL_SHIFT);
+ break;
+ case CLK_I2C1:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C1_SEL_MASK,
+ src_clk << CLK_I2C1_SEL_SHIFT);
+ break;
+ case CLK_I2C2:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C2_SEL_MASK,
+ src_clk << CLK_I2C2_SEL_SHIFT);
+ break;
+ case CLK_I2C3:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C3_SEL_MASK,
+ src_clk << CLK_I2C3_SEL_SHIFT);
+ break;
+ case CLK_I2C4:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C4_SEL_MASK,
+ src_clk << CLK_I2C4_SEL_SHIFT);
+ break;
+ case CLK_I2C5:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C5_SEL_MASK,
+ src_clk << CLK_I2C5_SEL_SHIFT);
+ break;
+ case CLK_I2C6:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C6_SEL_MASK,
+ src_clk << CLK_I2C6_SEL_SHIFT);
+ break;
+ case CLK_I2C7:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C7_SEL_MASK,
+ src_clk << CLK_I2C7_SEL_SHIFT);
+ break;
+ case CLK_I2C8:
+ rk_clrsetreg(&cru->clksel_con[38], CLK_I2C8_SEL_MASK,
+ src_clk << CLK_I2C8_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_spi_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 sel, con;
+
+ con = readl(&cru->clksel_con[59]);
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
+ break;
+ case CLK_SPI1:
+ sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
+ break;
+ case CLK_SPI2:
+ sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
+ break;
+ case CLK_SPI3:
+ sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
+ break;
+ case CLK_SPI4:
+ sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_SPI_SEL_200M:
+ return 200 * MHz;
+ case CLK_SPI_SEL_150M:
+ return 150 * MHz;
+ case CLK_SPI_SEL_24M:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_spi_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_SPI_SEL_200M;
+ else if (rate >= 140 * MHz)
+ src_clk = CLK_SPI_SEL_150M;
+ else
+ src_clk = CLK_SPI_SEL_24M;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SPI0_SEL_MASK,
+ src_clk << CLK_SPI0_SEL_SHIFT);
+ break;
+ case CLK_SPI1:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SPI1_SEL_MASK,
+ src_clk << CLK_SPI1_SEL_SHIFT);
+ break;
+ case CLK_SPI2:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SPI2_SEL_MASK,
+ src_clk << CLK_SPI2_SEL_SHIFT);
+ break;
+ case CLK_SPI3:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SPI3_SEL_MASK,
+ src_clk << CLK_SPI3_SEL_SHIFT);
+ break;
+ case CLK_SPI4:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SPI4_SEL_MASK,
+ src_clk << CLK_SPI4_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_pwm_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 sel, con;
+
+ switch (clk_id) {
+ case CLK_PWM1:
+ con = readl(&cru->clksel_con[59]);
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
+ break;
+ case CLK_PWM2:
+ con = readl(&cru->clksel_con[59]);
+ sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
+ break;
+ case CLK_PWM3:
+ con = readl(&cru->clksel_con[60]);
+ sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+ break;
+ case CLK_PMU1PWM:
+ con = readl(&cru->pmuclksel_con[2]);
+ sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_PWM_SEL_100M:
+ return 100 * MHz;
+ case CLK_PWM_SEL_50M:
+ return 50 * MHz;
+ case CLK_PWM_SEL_24M:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_pwm_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 99 * MHz)
+ src_clk = CLK_PWM_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = CLK_PWM_SEL_50M;
+ else
+ src_clk = CLK_PWM_SEL_24M;
+
+ switch (clk_id) {
+ case CLK_PWM1:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_PWM1_SEL_MASK,
+ src_clk << CLK_PWM1_SEL_SHIFT);
+ break;
+ case CLK_PWM2:
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_PWM2_SEL_MASK,
+ src_clk << CLK_PWM2_SEL_SHIFT);
+ break;
+ case CLK_PWM3:
+ rk_clrsetreg(&cru->clksel_con[60],
+ CLK_PWM3_SEL_MASK,
+ src_clk << CLK_PWM3_SEL_SHIFT);
+ break;
+ case CLK_PMU1PWM:
+ rk_clrsetreg(&cru->pmuclksel_con[2],
+ CLK_PMU1PWM_SEL_MASK,
+ src_clk << CLK_PMU1PWM_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_adc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 div, sel, con, prate;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ con = readl(&cru->clksel_con[40]);
+ div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
+ sel = (con & CLK_SARADC_SEL_MASK) >>
+ CLK_SARADC_SEL_SHIFT;
+ if (sel == CLK_SARADC_SEL_24M)
+ prate = OSC_HZ;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case CLK_TSADC:
+ con = readl(&cru->clksel_con[41]);
+ div = (con & CLK_TSADC_DIV_MASK) >>
+ CLK_TSADC_DIV_SHIFT;
+ sel = (con & CLK_TSADC_SEL_MASK) >>
+ CLK_TSADC_SEL_SHIFT;
+ if (sel == CLK_TSADC_SEL_24M)
+ prate = OSC_HZ;
+ else
+ prate = 100 * MHz;
+ return DIV_TO_RATE(prate, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_adc_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk_div;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ if (!(OSC_HZ % rate)) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[40],
+ CLK_SARADC_SEL_MASK |
+ CLK_SARADC_DIV_MASK,
+ (CLK_SARADC_SEL_24M <<
+ CLK_SARADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ } else {
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[40],
+ CLK_SARADC_SEL_MASK |
+ CLK_SARADC_DIV_MASK,
+ (CLK_SARADC_SEL_GPLL <<
+ CLK_SARADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ }
+ break;
+ case CLK_TSADC:
+ if (!(OSC_HZ % rate)) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[41],
+ CLK_TSADC_SEL_MASK |
+ CLK_TSADC_DIV_MASK,
+ (CLK_TSADC_SEL_24M <<
+ CLK_TSADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_TSADC_DIV_SHIFT);
+ } else {
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ assert(src_clk_div - 1 <= 7);
+ rk_clrsetreg(&cru->clksel_con[41],
+ CLK_TSADC_SEL_MASK |
+ CLK_TSADC_DIV_MASK,
+ (CLK_TSADC_SEL_GPLL <<
+ CLK_TSADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_TSADC_DIV_SHIFT);
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rk3588_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_mmc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 sel, con, div, prate;
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ con = readl(&cru->clksel_con[172]);
+ div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;
+ sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>
+ CCLK_SDIO_SRC_SEL_SHIFT;
+ if (sel == CCLK_SDIO_SRC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SDIO_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_EMMC:
+ con = readl(&cru->clksel_con[77]);
+ div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_EMMC_SEL_MASK) >>
+ CCLK_EMMC_SEL_SHIFT;
+ if (sel == CCLK_EMMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_EMMC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case BCLK_EMMC:
+ con = readl(&cru->clksel_con[78]);
+ div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;
+ sel = (con & BCLK_EMMC_SEL_MASK) >>
+ BCLK_EMMC_SEL_SHIFT;
+ if (sel == CCLK_EMMC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case SCLK_SFC:
+ con = readl(&cru->clksel_con[78]);
+ div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;
+ sel = (con & SCLK_SFC_SEL_MASK) >>
+ SCLK_SFC_SEL_SHIFT;
+ if (sel == SCLK_SFC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == SCLK_SFC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case DCLK_DECOM:
+ con = readl(&cru->clksel_con[62]);
+ div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;
+ sel = (con & DCLK_DECOM_SEL_MASK) >>
+ DCLK_DECOM_SEL_SHIFT;
+ if (sel == DCLK_DECOM_SEL_SPLL)
+ prate = 702 * MHz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk, div;
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case CCLK_EMMC:
+ case SCLK_SFC:
+ if (!(OSC_HZ % rate)) {
+ src_clk = SCLK_SFC_SEL_24M;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else if (!(priv->cpll_hz % rate)) {
+ src_clk = SCLK_SFC_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = SCLK_SFC_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ case BCLK_EMMC:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = CCLK_EMMC_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = CCLK_EMMC_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ case DCLK_DECOM:
+ if (!(702 * MHz % rate)) {
+ src_clk = DCLK_DECOM_SEL_SPLL;
+ div = DIV_ROUND_UP(702 * MHz, rate);
+ } else {
+ src_clk = DCLK_DECOM_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ rk_clrsetreg(&cru->clksel_con[172],
+ CCLK_SDIO_SRC_SEL_MASK |
+ CCLK_SDIO_SRC_DIV_MASK,
+ (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) |
+ (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);
+ break;
+ case CCLK_EMMC:
+ rk_clrsetreg(&cru->clksel_con[77],
+ CCLK_EMMC_SEL_MASK |
+ CCLK_EMMC_DIV_MASK,
+ (src_clk << CCLK_EMMC_SEL_SHIFT) |
+ (div - 1) << CCLK_EMMC_DIV_SHIFT);
+ break;
+ case BCLK_EMMC:
+ rk_clrsetreg(&cru->clksel_con[78],
+ BCLK_EMMC_DIV_MASK |
+ BCLK_EMMC_SEL_MASK,
+ (src_clk << BCLK_EMMC_SEL_SHIFT) |
+ (div - 1) << BCLK_EMMC_DIV_SHIFT);
+ break;
+ case SCLK_SFC:
+ rk_clrsetreg(&cru->clksel_con[78],
+ SCLK_SFC_DIV_MASK |
+ SCLK_SFC_SEL_MASK,
+ (src_clk << SCLK_SFC_SEL_SHIFT) |
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
+ break;
+ case DCLK_DECOM:
+ rk_clrsetreg(&cru->clksel_con[62],
+ DCLK_DECOM_DIV_MASK |
+ DCLK_DECOM_SEL_MASK,
+ (src_clk << DCLK_DECOM_SEL_SHIFT) |
+ (div - 1) << DCLK_DECOM_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_mmc_get_clk(priv, clk_id);
+}
+
+#ifndef CONFIG_SPL_BUILD
+static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 div, con, parent;
+
+ parent = priv->gpll_hz;
+ con = readl(&cru->clksel_con[117]);
+
+ switch (clk_id) {
+ case CLK_AUX16M_0:
+ div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT;
+ return DIV_TO_RATE(parent, div);
+ case CLK_AUX16M_1:
+ div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT;
+ return DIV_TO_RATE(parent, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_aux16m_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 div;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+
+ switch (clk_id) {
+ case CLK_AUX16M_0:
+ rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_0_DIV_MASK,
+ (div - 1) << CLK_AUX16MHZ_0_DIV_SHIFT);
+ break;
+ case CLK_AUX16M_1:
+ rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_1_DIV_MASK,
+ (div - 1) << CLK_AUX16MHZ_1_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_aux16m_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_aclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ con = readl(&cru->clksel_con[110]);
+ div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VOP_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_NPLL)
+ parent = priv->npll_hz;
+ else
+ parent = 702 * MHz;
+ return DIV_TO_RATE(parent, div);
+ case ACLK_VOP_LOW_ROOT:
+ con = readl(&cru->clksel_con[110]);
+ sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >>
+ ACLK_VOP_LOW_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VOP_LOW_ROOT_SEL_400M)
+ return 396 * MHz;
+ else if (sel == ACLK_VOP_LOW_ROOT_SEL_200M)
+ return 200 * MHz;
+ else if (sel == ACLK_VOP_LOW_ROOT_SEL_100M)
+ return 100 * MHz;
+ else
+ return OSC_HZ;
+ case HCLK_VOP_ROOT:
+ con = readl(&cru->clksel_con[110]);
+ sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == HCLK_VOP_ROOT_SEL_200M)
+ return 200 * MHz;
+ else if (sel == HCLK_VOP_ROOT_SEL_100M)
+ return 100 * MHz;
+ else if (sel == HCLK_VOP_ROOT_SEL_50M)
+ return 50 * MHz;
+ else
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_aclk_vop_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int src_clk, div;
+
+ switch (clk_id) {
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ if (rate >= 850 * MHz) {
+ src_clk = ACLK_VOP_ROOT_SEL_NPLL;
+ div = 1;
+ } else if (rate >= 750 * MHz) {
+ src_clk = ACLK_VOP_ROOT_SEL_CPLL;
+ div = 2;
+ } else if (rate >= 700 * MHz) {
+ src_clk = ACLK_VOP_ROOT_SEL_SPLL;
+ div = 1;
+ } else if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VOP_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VOP_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[110],
+ ACLK_VOP_ROOT_DIV_MASK |
+ ACLK_VOP_ROOT_SEL_MASK,
+ (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);
+ break;
+ case ACLK_VOP_LOW_ROOT:
+ if (rate == 400 * MHz || rate == 396 * MHz)
+ src_clk = ACLK_VOP_LOW_ROOT_SEL_400M;
+ else if (rate == 200 * MHz)
+ src_clk = ACLK_VOP_LOW_ROOT_SEL_200M;
+ else if (rate == 100 * MHz)
+ src_clk = ACLK_VOP_LOW_ROOT_SEL_100M;
+ else
+ src_clk = ACLK_VOP_LOW_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[110],
+ ACLK_VOP_LOW_ROOT_SEL_MASK,
+ src_clk << ACLK_VOP_LOW_ROOT_SEL_SHIFT);
+ break;
+ case HCLK_VOP_ROOT:
+ if (rate == 200 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_200M;
+ else if (rate == 100 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_100M;
+ else if (rate == 50 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_50M;
+ else
+ src_clk = HCLK_VOP_ROOT_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[110],
+ HCLK_VOP_ROOT_SEL_MASK,
+ src_clk << HCLK_VOP_ROOT_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_aclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_dclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ case DCLK_VOP0_SRC:
+ con = readl(&cru->clksel_con[111]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VOP1:
+ case DCLK_VOP1_SRC:
+ con = readl(&cru->clksel_con[111]);
+ div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VOP2:
+ case DCLK_VOP2_SRC:
+ con = readl(&cru->clksel_con[112]);
+ div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VOP3:
+ con = readl(&cru->clksel_con[113]);
+ div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SRC_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else if (sel == DCLK_VOP_SRC_SEL_V0PLL)
+ parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL);
+ else if (sel == DCLK_VOP_SRC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == DCLK_VOP_SRC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else
+ return -ENOENT;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+#define RK3588_VOP_PLL_LIMIT_FREQ 600000000
+
+static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
+ u32 mask, div_shift, sel_shift;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ case DCLK_VOP0_SRC:
+ conid = 111;
+ con = readl(&cru->clksel_con[111]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VOP1:
+ case DCLK_VOP1_SRC:
+ conid = 111;
+ con = readl(&cru->clksel_con[111]);
+ sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;
+ mask = DCLK1_VOP_SRC_SEL_MASK | DCLK1_VOP_SRC_DIV_MASK;
+ div_shift = DCLK1_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK1_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VOP2:
+ case DCLK_VOP2_SRC:
+ conid = 112;
+ con = readl(&cru->clksel_con[112]);
+ sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;
+ mask = DCLK2_VOP_SRC_SEL_MASK | DCLK2_VOP_SRC_DIV_MASK;
+ div_shift = DCLK2_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK2_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VOP3:
+ conid = 113;
+ con = readl(&cru->clksel_con[113]);
+ sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
+ mask = DCLK3_VOP_SRC_SEL_MASK | DCLK3_VOP_SRC_DIV_MASK;
+ div_shift = DCLK3_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK3_VOP_SRC_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SRC_SEL_V0PLL) {
+ div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
+ ((div - 1) << div_shift));
+ rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL, div * rate);
+ } else {
+ for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
+ switch (i) {
+ case DCLK_VOP_SRC_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_AUPLL:
+ pll_rate = priv->aupll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_V0PLL:
+ pll_rate = 0;
+ break;
+ default:
+ printf("do not support this vop pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+ pll_rate, best_rate, best_div, best_sel);
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ best_sel << sel_shift |
+ (best_div - 1) << div_shift);
+ } else {
+ printf("do not support this vop freq %lu\n", rate);
+ return -EINVAL;
+ }
+ }
+ return rk3588_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_gmac_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 con, div;
+
+ switch (clk_id) {
+ case CLK_GMAC0_PTP_REF:
+ con = readl(&cru->clksel_con[81]);
+ div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ case CLK_GMAC1_PTP_REF:
+ con = readl(&cru->clksel_con[81]);
+ div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ case CLK_GMAC_125M:
+ con = readl(&cru->clksel_con[83]);
+ div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ case CLK_GMAC_50M:
+ con = readl(&cru->clksel_con[84]);
+ div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3588_gmac_set_clk(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ int div;
+
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+
+ switch (clk_id) {
+ case CLK_GMAC0_PTP_REF:
+ rk_clrsetreg(&cru->clksel_con[81],
+ CLK_GMAC0_PTP_DIV_MASK | CLK_GMAC0_PTP_SEL_MASK,
+ CLK_GMAC0_PTP_SEL_CPLL << CLK_GMAC0_PTP_SEL_SHIFT |
+ (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);
+ break;
+ case CLK_GMAC1_PTP_REF:
+ rk_clrsetreg(&cru->clksel_con[81],
+ CLK_GMAC1_PTP_DIV_MASK | CLK_GMAC1_PTP_SEL_MASK,
+ CLK_GMAC1_PTP_SEL_CPLL << CLK_GMAC1_PTP_SEL_SHIFT |
+ (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);
+ break;
+
+ case CLK_GMAC_125M:
+ rk_clrsetreg(&cru->clksel_con[83],
+ CLK_GMAC_125M_DIV_MASK | CLK_GMAC_125M_SEL_MASK,
+ CLK_GMAC_125M_SEL_CPLL << CLK_GMAC_125M_SEL_SHIFT |
+ (div - 1) << CLK_GMAC_125M_DIV_SHIFT);
+ break;
+ case CLK_GMAC_50M:
+ rk_clrsetreg(&cru->clksel_con[84],
+ CLK_GMAC_50M_DIV_MASK | CLK_GMAC_50M_SEL_MASK,
+ CLK_GMAC_50M_SEL_CPLL << CLK_GMAC_50M_SEL_SHIFT |
+ (div - 1) << CLK_GMAC_50M_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_gmac_get_clk(priv, clk_id);
+}
+
+static ulong rk3588_uart_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 reg, con, fracdiv, div, src, p_src, p_rate;
+ unsigned long m, n;
+
+ switch (clk_id) {
+ case SCLK_UART1:
+ reg = 41;
+ break;
+ case SCLK_UART2:
+ reg = 43;
+ break;
+ case SCLK_UART3:
+ reg = 45;
+ break;
+ case SCLK_UART4:
+ reg = 47;
+ break;
+ case SCLK_UART5:
+ reg = 49;
+ break;
+ case SCLK_UART6:
+ reg = 51;
+ break;
+ case SCLK_UART7:
+ reg = 53;
+ break;
+ case SCLK_UART8:
+ reg = 55;
+ break;
+ case SCLK_UART9:
+ reg = 57;
+ break;
+ default:
+ return -ENOENT;
+ }
+ con = readl(&cru->clksel_con[reg + 2]);
+ src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
+ con = readl(&cru->clksel_con[reg]);
+ div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
+ p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
+ if (p_src == CLK_UART_SRC_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else
+ p_rate = priv->cpll_hz;
+
+ if (src == CLK_UART_SEL_SRC) {
+ return DIV_TO_RATE(p_rate, div);
+ } else if (src == CLK_UART_SEL_FRAC) {
+ fracdiv = readl(&cru->clksel_con[reg + 1]);
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return DIV_TO_RATE(p_rate, div) * n / m;
+ } else {
+ return OSC_HZ;
+ }
+}
+
+static ulong rk3588_uart_set_rate(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 reg, clk_src, uart_src, div;
+ unsigned long m = 0, n = 0, val;
+
+ if (priv->gpll_hz % rate == 0) {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ uart_src = CLK_UART_SEL_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (priv->cpll_hz % rate == 0) {
+ clk_src = CLK_UART_SRC_SEL_CPLL;
+ uart_src = CLK_UART_SEL_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (rate == OSC_HZ) {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ uart_src = CLK_UART_SEL_XIN24M;
+ div = 2;
+ } else {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ uart_src = CLK_UART_SEL_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->gpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &m, &n);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART1:
+ reg = 41;
+ break;
+ case SCLK_UART2:
+ reg = 43;
+ break;
+ case SCLK_UART3:
+ reg = 45;
+ break;
+ case SCLK_UART4:
+ reg = 47;
+ break;
+ case SCLK_UART5:
+ reg = 49;
+ break;
+ case SCLK_UART6:
+ reg = 51;
+ break;
+ case SCLK_UART7:
+ reg = 53;
+ break;
+ case SCLK_UART8:
+ reg = 55;
+ break;
+ case SCLK_UART9:
+ reg = 57;
+ break;
+ default:
+ return -ENOENT;
+ }
+ rk_clrsetreg(&cru->clksel_con[reg],
+ CLK_UART_SRC_SEL_MASK |
+ CLK_UART_SRC_DIV_MASK,
+ (clk_src << CLK_UART_SRC_SEL_SHIFT) |
+ ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
+ rk_clrsetreg(&cru->clksel_con[reg + 2],
+ CLK_UART_SEL_MASK,
+ (uart_src << CLK_UART_SEL_SHIFT));
+ if (m && n) {
+ val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[reg + 1]);
+ }
+
+ return rk3588_uart_get_rate(priv, clk_id);
+}
+
+static ulong rk3588_pciephy_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 con, div, src;
+
+ switch (clk_id) {
+ case CLK_REF_PIPE_PHY0:
+ con = readl(&cru->clksel_con[177]);
+ src = (con & CLK_PCIE_PHY0_REF_SEL_MASK) >> CLK_PCIE_PHY0_REF_SEL_SHIFT;
+ con = readl(&cru->clksel_con[176]);
+ div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT;
+ break;
+ case CLK_REF_PIPE_PHY1:
+ con = readl(&cru->clksel_con[177]);
+ src = (con & CLK_PCIE_PHY1_REF_SEL_MASK) >> CLK_PCIE_PHY1_REF_SEL_SHIFT;
+ con = readl(&cru->clksel_con[176]);
+ div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT;
+ break;
+ case CLK_REF_PIPE_PHY2:
+ con = readl(&cru->clksel_con[177]);
+ src = (con & CLK_PCIE_PHY2_REF_SEL_MASK) >> CLK_PCIE_PHY2_REF_SEL_SHIFT;
+ div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (src == CLK_PCIE_PHY_REF_SEL_PPLL)
+ return DIV_TO_RATE(priv->ppll_hz, div);
+ else
+ return OSC_HZ;
+}
+
+static ulong rk3588_pciephy_set_rate(struct rk3588_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3588_cru *cru = priv->cru;
+ u32 clk_src, div;
+
+ if (rate == OSC_HZ) {
+ clk_src = CLK_PCIE_PHY_REF_SEL_24M;
+ div = 1;
+ } else {
+ clk_src = CLK_PCIE_PHY_REF_SEL_PPLL;
+ div = DIV_ROUND_UP(priv->ppll_hz, rate);
+ }
+
+ switch (clk_id) {
+ case CLK_REF_PIPE_PHY0:
+ rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY0_REF_SEL_MASK,
+ (clk_src << CLK_PCIE_PHY0_REF_SEL_SHIFT));
+ rk_clrsetreg(&cru->clksel_con[176], CLK_PCIE_PHY0_PLL_DIV_MASK,
+ ((div - 1) << CLK_PCIE_PHY0_PLL_DIV_SHIFT));
+ break;
+ case CLK_REF_PIPE_PHY1:
+ rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY1_REF_SEL_MASK,
+ (clk_src << CLK_PCIE_PHY1_REF_SEL_SHIFT));
+ rk_clrsetreg(&cru->clksel_con[176], CLK_PCIE_PHY1_PLL_DIV_MASK,
+ ((div - 1) << CLK_PCIE_PHY1_PLL_DIV_SHIFT));
+ break;
+ case CLK_REF_PIPE_PHY2:
+ rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY2_REF_SEL_MASK |
+ CLK_PCIE_PHY2_PLL_DIV_MASK,
+ (clk_src << CLK_PCIE_PHY2_REF_SEL_SHIFT) |
+ ((div - 1) << CLK_PCIE_PHY2_PLL_DIV_SHIFT));
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3588_pciephy_get_rate(priv, clk_id);
+}
+#endif
+
+static ulong rk3588_clk_get_rate(struct clk *clk)
+{
+ struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ if (!priv->ppll_hz) {
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+
+ switch (clk->id) {
+ case PLL_LPLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru,
+ LPLL);
+ break;
+ case PLL_B0PLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru,
+ B0PLL);
+ break;
+ case PLL_B1PLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru,
+ B1PLL);
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_NPLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru,
+ NPLL);
+ break;
+ case PLL_V0PLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru,
+ V0PLL);
+ break;
+ case PLL_AUPLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru,
+ AUPLL);
+ break;
+ case PLL_PPLL:
+ rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru,
+ PPLL);
+ break;
+ case ACLK_CENTER_ROOT:
+ case PCLK_CENTER_ROOT:
+ case HCLK_CENTER_ROOT:
+ case ACLK_CENTER_LOW_ROOT:
+ rate = rk3588_center_get_clk(priv, clk->id);
+ break;
+ case ACLK_TOP_ROOT:
+ case PCLK_TOP_ROOT:
+ case ACLK_LOW_TOP_ROOT:
+ rate = rk3588_top_get_clk(priv, clk->id);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ case CLK_I2C8:
+ rate = rk3588_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ case CLK_SPI3:
+ case CLK_SPI4:
+ rate = rk3588_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM1:
+ case CLK_PWM2:
+ case CLK_PWM3:
+ case CLK_PMU1PWM:
+ rate = rk3588_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ rate = rk3588_adc_get_clk(priv, clk->id);
+ break;
+ case CCLK_SRC_SDIO:
+ case CCLK_EMMC:
+ case BCLK_EMMC:
+ case SCLK_SFC:
+ case DCLK_DECOM:
+ rate = rk3588_mmc_get_clk(priv, clk->id);
+ break;
+ case TCLK_WDT0:
+ rate = OSC_HZ;
+ break;
+#ifndef CONFIG_SPL_BUILD
+ case CLK_AUX16M_0:
+ case CLK_AUX16M_1:
+ rk3588_aux16m_get_clk(priv, clk->id);
+ break;
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ case ACLK_VOP_LOW_ROOT:
+ case HCLK_VOP_ROOT:
+ rate = rk3588_aclk_vop_get_clk(priv, clk->id);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP0_SRC:
+ case DCLK_VOP1:
+ case DCLK_VOP1_SRC:
+ case DCLK_VOP2:
+ case DCLK_VOP2_SRC:
+ case DCLK_VOP3:
+ rate = rk3588_dclk_vop_get_clk(priv, clk->id);
+ break;
+ case CLK_GMAC0_PTP_REF:
+ case CLK_GMAC1_PTP_REF:
+ case CLK_GMAC_125M:
+ case CLK_GMAC_50M:
+ rate = rk3588_gmac_get_clk(priv, clk->id);
+ break;
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ rate = rk3588_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_REF_PIPE_PHY0:
+ case CLK_REF_PIPE_PHY1:
+ case CLK_REF_PIPE_PHY2:
+ rate = rk3588_pciephy_get_rate(priv, clk->id);
+ break;
+#endif
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ if (!priv->ppll_hz) {
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+
+ switch (clk->id) {
+ case PLL_CPLL:
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
+ CPLL, rate);
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL],
+ priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_NPLL:
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru,
+ NPLL, rate);
+ break;
+ case PLL_V0PLL:
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru,
+ V0PLL, rate);
+ priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL);
+ break;
+ case PLL_AUPLL:
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[AUPLL], priv->cru,
+ AUPLL, rate);
+ priv->aupll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL],
+ priv->cru, AUPLL);
+ break;
+ case PLL_PPLL:
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
+ PPLL, rate);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
+ priv->cru, PPLL);
+ break;
+ case ACLK_CENTER_ROOT:
+ case PCLK_CENTER_ROOT:
+ case HCLK_CENTER_ROOT:
+ case ACLK_CENTER_LOW_ROOT:
+ ret = rk3588_center_set_clk(priv, clk->id, rate);
+ break;
+ case ACLK_TOP_ROOT:
+ case PCLK_TOP_ROOT:
+ case ACLK_LOW_TOP_ROOT:
+ ret = rk3588_top_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ case CLK_I2C8:
+ ret = rk3588_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ case CLK_SPI3:
+ case CLK_SPI4:
+ ret = rk3588_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM1:
+ case CLK_PWM2:
+ case CLK_PWM3:
+ case CLK_PMU1PWM:
+ ret = rk3588_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ ret = rk3588_adc_set_clk(priv, clk->id, rate);
+ break;
+ case CCLK_SRC_SDIO:
+ case CCLK_EMMC:
+ case BCLK_EMMC:
+ case SCLK_SFC:
+ case DCLK_DECOM:
+ ret = rk3588_mmc_set_clk(priv, clk->id, rate);
+ break;
+ case TCLK_WDT0:
+ ret = OSC_HZ;
+ break;
+#ifndef CONFIG_SPL_BUILD
+ case CLK_AUX16M_0:
+ case CLK_AUX16M_1:
+ rk3588_aux16m_set_clk(priv, clk->id, rate);
+ break;
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ case ACLK_VOP_LOW_ROOT:
+ case HCLK_VOP_ROOT:
+ ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP0_SRC:
+ case DCLK_VOP1:
+ case DCLK_VOP1_SRC:
+ case DCLK_VOP2:
+ case DCLK_VOP2_SRC:
+ case DCLK_VOP3:
+ ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_GMAC0_PTP_REF:
+ case CLK_GMAC1_PTP_REF:
+ case CLK_GMAC_125M:
+ case CLK_GMAC_50M:
+ ret = rk3588_gmac_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ ret = rk3588_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_REF_PIPE_PHY0:
+ case CLK_REF_PIPE_PHY1:
+ case CLK_REF_PIPE_PHY2:
+ ret = rk3588_pciephy_set_rate(priv, clk->id, rate);
+ break;
+#endif
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
+
+#define PSECS_PER_SEC 1000000000000LL
+/*
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+static int __maybe_unused rk3588_dclk_vop_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3588_cru *cru = priv->cru;
+ u32 sel;
+ const char *clock_dev_name = parent->dev->name;
+
+ if (parent->id == PLL_V0PLL)
+ sel = 2;
+ else if (parent->id == PLL_GPLL)
+ sel = 0;
+ else if (parent->id == PLL_CPLL)
+ sel = 1;
+ else
+ sel = 3;
+
+ switch (clk->id) {
+ case DCLK_VOP0_SRC:
+ rk_clrsetreg(&cru->clksel_con[111], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VOP1_SRC:
+ rk_clrsetreg(&cru->clksel_con[111], DCLK1_VOP_SRC_SEL_MASK,
+ sel << DCLK1_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VOP2_SRC:
+ rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SRC_SEL_MASK,
+ sel << DCLK2_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VOP3:
+ rk_clrsetreg(&cru->clksel_con[113], DCLK3_VOP_SRC_SEL_MASK,
+ sel << DCLK3_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VOP0:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
+ sel = 2;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[112], DCLK0_VOP_SEL_MASK,
+ sel << DCLK0_VOP_SEL_SHIFT);
+ break;
+ case DCLK_VOP1:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
+ sel = 2;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[112], DCLK1_VOP_SEL_MASK,
+ sel << DCLK1_VOP_SEL_SHIFT);
+ break;
+ case DCLK_VOP2:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
+ sel = 2;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SEL_MASK,
+ sel << DCLK2_VOP_SEL_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int rk3588_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case DCLK_VOP0_SRC:
+ case DCLK_VOP1_SRC:
+ case DCLK_VOP2_SRC:
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ case DCLK_VOP2:
+ case DCLK_VOP3:
+ return rk3588_dclk_vop_set_parent(clk, parent);
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+}
+#endif
+
+static struct clk_ops rk3588_clk_ops = {
+ .get_rate = rk3588_clk_get_rate,
+ .set_rate = rk3588_clk_set_rate,
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+ .set_parent = rk3588_clk_set_parent,
+#endif
+};
+
+static void rk3588_clk_init(struct rk3588_clk_priv *priv)
+{
+ int ret, div;
+
+ div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz);
+ rk_clrsetreg(&priv->cru->clksel_con[38],
+ ACLK_BUS_ROOT_SEL_MASK |
+ ACLK_BUS_ROOT_DIV_MASK,
+ div << ACLK_BUS_ROOT_DIV_SHIFT);
+
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+
+#ifdef CONFIG_PCI
+ if (priv->ppll_hz != PPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
+ PPLL, PPLL_HZ);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+#endif
+ rk_clrsetreg(&priv->cru->clksel_con[9],
+ ACLK_TOP_S400_SEL_MASK |
+ ACLK_TOP_S200_SEL_MASK,
+ (ACLK_TOP_S400_SEL_400M << ACLK_TOP_S400_SEL_SHIFT) |
+ (ACLK_TOP_S200_SEL_200M << ACLK_TOP_S200_SEL_SHIFT));
+}
+
+static int rk3588_clk_probe(struct udevice *dev)
+{
+ struct rk3588_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->sync_kernel = false;
+
+#ifdef CONFIG_SPL_BUILD
+ rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru,
+ B0PLL, LPLL_HZ);
+ rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru,
+ B1PLL, LPLL_HZ);
+ if (!priv->armclk_enter_hz) {
+ ret = rockchip_pll_set_rate(&rk3588_pll_clks[LPLL], priv->cru,
+ LPLL, LPLL_HZ);
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3588_pll_clks[LPLL],
+ priv->cru, LPLL);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ }
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+ struct clk clk;
+
+ if (!priv->armclk_enter_hz) {
+ clk.id = SCMI_CLK_CPUL;
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
+ if (ret < 0) {
+ printf("Failed to set cpubl\n");
+ } else {
+ priv->armclk_enter_hz = CPU_PVTPLL_HZ;
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
+ }
+ }
+ clk.id = SCMI_CLK_CPUB01;
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
+ if (ret < 0)
+ printf("Failed to set cpub01\n");
+ clk.id = SCMI_CLK_CPUB23;
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
+ if (ret < 0)
+ printf("Failed to set cpub23\n");
+#endif
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ return PTR_ERR(priv->grf);
+
+ rk3588_clk_init(priv);
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev, 1);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3588_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3588_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3588_clk_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3588_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3588_cru,
+ glb_srsr_snd);
+ dev_set_priv(sys_child, priv);
+ }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+ ret = offsetof(struct rk3588_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 49158);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id rk3588_clk_ids[] = {
+ { .compatible = "rockchip,rk3588-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3588_cru) = {
+ .name = "rockchip_rk3588_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3588_clk_ids,
+ .priv_auto = sizeof(struct rk3588_clk_priv),
+ .of_to_plat = rk3588_clk_ofdata_to_platdata,
+ .ops = &rk3588_clk_ops,
+ .bind = rk3588_clk_bind,
+ .probe = rk3588_clk_probe,
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 06/16] clk: rockchip: pll: Add pll_rk3588 type for rk3588
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (4 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 05/16] clk: rockchip: Add rk3588 clk support Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 07/16] ram: rockchip: Add rk3588 ddr driver support Jagan Teki
` (10 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Elaine Zhang
Add RK3588 pll set and get rate clock support.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/include/asm/arch-rockchip/clock.h | 24 ++
drivers/clk/rockchip/clk_pll.c | 267 ++++++++++++++++++++-
2 files changed, 288 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 566bdcc4fa..90e66c7da0 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -22,6 +22,14 @@ enum {
ROCKCHIP_SYSCON_PMUSGRF,
ROCKCHIP_SYSCON_CIC,
ROCKCHIP_SYSCON_MSCH,
+ ROCKCHIP_SYSCON_USBGRF,
+ ROCKCHIP_SYSCON_PCIE30_PHY_GRF,
+ ROCKCHIP_SYSCON_PHP_GRF,
+ ROCKCHIP_SYSCON_PIPE_PHY0_GRF,
+ ROCKCHIP_SYSCON_PIPE_PHY1_GRF,
+ ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
+ ROCKCHIP_SYSCON_VOP_GRF,
+ ROCKCHIP_SYSCON_VO_GRF,
};
/* Standard Rockchip clock numbers */
@@ -61,6 +69,15 @@ enum rk_clk_id {
.frac = _frac, \
}
+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
+{ \
+ .rate = _rate##U, \
+ .p = _p, \
+ .m = _m, \
+ .s = _s, \
+ .k = _k, \
+}
+
struct rockchip_pll_rate_table {
unsigned long rate;
unsigned int nr;
@@ -74,6 +91,11 @@ struct rockchip_pll_rate_table {
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
+ /* for RK3588 */
+ unsigned int m;
+ unsigned int p;
+ unsigned int s;
+ unsigned int k;
};
enum rockchip_pll_type {
@@ -82,6 +104,7 @@ enum rockchip_pll_type {
pll_rk3328,
pll_rk3366,
pll_rk3399,
+ pll_rk3588,
};
struct rockchip_pll_clock {
@@ -171,5 +194,6 @@ int rockchip_get_clk(struct udevice **devp);
* Return: 0 success, or error value
*/
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+int rockchip_get_scmi_clk(struct udevice **devp);
#endif
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 09b97cf57a..d657ef38f3 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -45,6 +45,10 @@ enum {
#define MIN_FOUTVCO_FREQ (800 * MHZ)
#define MAX_FOUTVCO_FREQ (2000 * MHZ)
+#define RK3588_VCO_MIN_HZ (2250UL * MHZ)
+#define RK3588_VCO_MAX_HZ (4500UL * MHZ)
+#define RK3588_FOUT_MIN_HZ (37UL * MHZ)
+#define RK3588_FOUT_MAX_HZ (4500UL * MHZ)
int gcd(int m, int n)
{
@@ -164,6 +168,65 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
return rate_table;
}
+static struct rockchip_pll_rate_table *
+rk3588_pll_clk_set_by_auto(unsigned long fin_hz,
+ unsigned long fout_hz)
+{
+ struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
+ u32 p, m, s;
+ ulong fvco, fref, fout, ffrac;
+
+ if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
+ return NULL;
+
+ if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ)
+ return NULL;
+
+ if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
+ for (s = 0; s <= 6; s++) {
+ fvco = fout_hz << s;
+ if (fvco < RK3588_VCO_MIN_HZ ||
+ fvco > RK3588_VCO_MAX_HZ)
+ continue;
+ for (p = 2; p <= 4; p++) {
+ for (m = 64; m <= 1023; m++) {
+ if (fvco == m * fin_hz / p) {
+ rate_table->p = p;
+ rate_table->m = m;
+ rate_table->s = s;
+ rate_table->k = 0;
+ return rate_table;
+ }
+ }
+ }
+ }
+ pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
+ } else {
+ for (s = 0; s <= 6; s++) {
+ fvco = fout_hz << s;
+ if (fvco < RK3588_VCO_MIN_HZ ||
+ fvco > RK3588_VCO_MAX_HZ)
+ continue;
+ for (p = 1; p <= 4; p++) {
+ for (m = 64; m <= 1023; m++) {
+ if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
+ rate_table->p = p;
+ rate_table->m = m;
+ rate_table->s = s;
+ fref = fin_hz / p;
+ ffrac = fvco - (m * fref);
+ fout = ffrac * 65536;
+ rate_table->k = fout / fref;
+ return rate_table;
+ }
+ }
+ }
+ }
+ pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
+ }
+ return NULL;
+}
+
static const struct rockchip_pll_rate_table *
rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
{
@@ -174,10 +237,14 @@ rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
break;
rate_table++;
}
- if (rate_table->rate != rate)
- return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
- else
+ if (rate_table->rate != rate) {
+ if (pll->type == pll_rk3588)
+ return rk3588_pll_clk_set_by_auto(24 * MHZ, rate);
+ else
+ return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
+ } else {
return rate_table;
+ }
}
static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
@@ -296,6 +363,192 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
}
}
+#define RK3588_PLLCON(i) ((i) * 0x4)
+#define RK3588_PLLCON0_M_MASK 0x3ff << 0
+#define RK3588_PLLCON0_M_SHIFT 0
+#define RK3588_PLLCON1_P_MASK 0x3f << 0
+#define RK3588_PLLCON1_P_SHIFT 0
+#define RK3588_PLLCON1_S_MASK 0x7 << 6
+#define RK3588_PLLCON1_S_SHIFT 6
+#define RK3588_PLLCON2_K_MASK 0xffff
+#define RK3588_PLLCON2_K_SHIFT 0
+#define RK3588_PLLCON1_PWRDOWN BIT(13)
+#define RK3588_PLLCON6_LOCK_STATUS BIT(15)
+#define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300)
+#define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300)
+#define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300)
+#define RK3588_CORE_DIV_MASK 0x1f
+#define RK3588_CORE_L02_DIV_SHIFT 0
+#define RK3588_CORE_L13_DIV_SHIFT 7
+#define RK3588_CORE_B02_DIV_SHIFT 8
+#define RK3588_CORE_B13_DIV_SHIFT 0
+
+static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll,
+ void __iomem *base, ulong pll_id,
+ ulong drate)
+{
+ const struct rockchip_pll_rate_table *rate;
+
+ rate = rockchip_get_pll_settings(pll, drate);
+ if (!rate) {
+ printf("%s unsupported rate\n", __func__);
+ return -EINVAL;
+ }
+
+ debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
+ __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
+
+ /*
+ * When power on or changing PLL setting,
+ * we must force PLL into slow mode to ensure output stable clock.
+ */
+ if (pll_id == 3)
+ rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1);
+
+ rk_clrsetreg(base + pll->mode_offset,
+ pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ if (pll_id == 0)
+ rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
+ pll->mode_mask << 6,
+ RKCLK_PLL_MODE_SLOW << 6);
+ else if (pll_id == 1)
+ rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
+ pll->mode_mask << 6,
+ RKCLK_PLL_MODE_SLOW << 6);
+ else if (pll_id == 2)
+ rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
+ pll->mode_mask << 14,
+ RKCLK_PLL_MODE_SLOW << 14);
+
+ /* Power down */
+ rk_setreg(base + pll->con_offset + RK3588_PLLCON(1),
+ RK3588_PLLCON1_PWRDOWN);
+
+ rk_clrsetreg(base + pll->con_offset,
+ RK3588_PLLCON0_M_MASK,
+ (rate->m << RK3588_PLLCON0_M_SHIFT));
+ rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1),
+ (RK3588_PLLCON1_P_MASK |
+ RK3588_PLLCON1_S_MASK),
+ (rate->p << RK3588_PLLCON1_P_SHIFT |
+ rate->s << RK3588_PLLCON1_S_SHIFT));
+ if (rate->k) {
+ rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
+ RK3588_PLLCON2_K_MASK,
+ rate->k << RK3588_PLLCON2_K_SHIFT);
+ }
+ /* Power up */
+ rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),
+ RK3588_PLLCON1_PWRDOWN);
+
+ /* waiting for pll lock */
+ while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) &
+ RK3588_PLLCON6_LOCK_STATUS)) {
+ udelay(1);
+ debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id);
+ }
+
+ rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ if (pll_id == 0) {
+ rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
+ pll->mode_mask << 6,
+ 2 << 6);
+ rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
+ 0 << RK3588_CORE_B02_DIV_SHIFT);
+ rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
+ 0 << RK3588_CORE_B13_DIV_SHIFT);
+ } else if (pll_id == 1) {
+ rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
+ pll->mode_mask << 6,
+ 2 << 6);
+ rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
+ 0 << RK3588_CORE_B02_DIV_SHIFT);
+ rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
+ 0 << RK3588_CORE_B13_DIV_SHIFT);
+ } else if (pll_id == 2) {
+ rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
+ pll->mode_mask << 14,
+ 2 << 14);
+ rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
+ 0 << RK3588_CORE_L13_DIV_SHIFT);
+ rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
+ 0 << RK3588_CORE_L02_DIV_SHIFT);
+ rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
+ 0 << RK3588_CORE_L13_DIV_SHIFT);
+ rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
+ RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
+ 0 << RK3588_CORE_L02_DIV_SHIFT);
+ }
+
+ if (pll_id == 3)
+ rk_clrsetreg(base + 0x84c, 0x1 << 1, 0);
+
+ debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
+ pll, readl(base + pll->con_offset),
+ readl(base + pll->con_offset + 0x4),
+ readl(base + pll->con_offset + 0x8),
+ readl(base + pll->mode_offset));
+
+ return 0;
+}
+
+static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll,
+ void __iomem *base, ulong pll_id)
+{
+ u32 m, p, s, k;
+ u32 con = 0, shift, mode;
+ u64 rate, postdiv;
+
+ con = readl(base + pll->mode_offset);
+ shift = pll->mode_shift;
+ if (pll_id == 8)
+ mode = RKCLK_PLL_MODE_NORMAL;
+ else
+ mode = (con & (pll->mode_mask << shift)) >> shift;
+ switch (mode) {
+ case RKCLK_PLL_MODE_SLOW:
+ return OSC_HZ;
+ case RKCLK_PLL_MODE_NORMAL:
+ /* normal mode */
+ con = readl(base + pll->con_offset);
+ m = (con & RK3588_PLLCON0_M_MASK) >>
+ RK3588_PLLCON0_M_SHIFT;
+ con = readl(base + pll->con_offset + RK3588_PLLCON(1));
+ p = (con & RK3588_PLLCON1_P_MASK) >>
+ RK3036_PLLCON0_FBDIV_SHIFT;
+ s = (con & RK3588_PLLCON1_S_MASK) >>
+ RK3588_PLLCON1_S_SHIFT;
+ con = readl(base + pll->con_offset + RK3588_PLLCON(2));
+ k = (con & RK3588_PLLCON2_K_MASK) >>
+ RK3588_PLLCON2_K_SHIFT;
+
+ rate = OSC_HZ / p;
+ rate *= m;
+ if (k) {
+ /* fractional mode */
+ u64 frac_rate64 = OSC_HZ * k;
+
+ postdiv = p * 65536;
+ do_div(frac_rate64, postdiv);
+ rate += frac_rate64;
+ }
+ rate = rate >> s;
+ return rate;
+ case RKCLK_PLL_MODE_DEEP:
+ default:
+ return 32768;
+ }
+}
+
ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
void __iomem *base,
ulong pll_id)
@@ -311,6 +564,10 @@ ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
pll->mode_mask = PLL_RK3328_MODE_MASK;
rate = rk3036_pll_get_rate(pll, base, pll_id);
break;
+ case pll_rk3588:
+ pll->mode_mask = PLL_MODE_MASK;
+ rate = rk3588_pll_get_rate(pll, base, pll_id);
+ break;
default:
printf("%s: Unknown pll type for pll clk %ld\n",
__func__, pll_id);
@@ -336,6 +593,10 @@ int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
pll->mode_mask = PLL_RK3328_MODE_MASK;
ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
break;
+ case pll_rk3588:
+ pll->mode_mask = PLL_MODE_MASK;
+ ret = rk3588_pll_set_rate(pll, base, pll_id, drate);
+ break;
default:
printf("%s: Unknown pll type for pll clk %ld\n",
__func__, pll_id);
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 07/16] ram: rockchip: Add rk3588 ddr driver support
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (5 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 06/16] clk: rockchip: pll: Add pll_rk3588 type for rk3588 Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 08/16] dt-bindings: power: Add power-domain header for rk3588 Jagan Teki
` (9 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Add ddr driver for rk3588 to get the ram capacity.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3588.c | 56 +++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_rk3588.c
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 98839ad6a6..36dc0500da 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
diff --git a/drivers/ram/rockchip/sdram_rk3588.c b/drivers/ram/rockchip/sdram_rk3588.c
new file mode 100644
index 0000000000..16fcea595a
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3588.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3588.h>
+#include <asm/arch-rockchip/sdram.h>
+
+struct dram_info {
+ struct ram_info info;
+ struct rk3588_pmu1grf *pmugrf;
+};
+
+static int rk3588_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ priv->info.base = CFG_SYS_SDRAM_BASE;
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
+
+ return 0;
+}
+
+static int rk3588_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops rk3588_dmc_ops = {
+ .get_info = rk3588_dmc_get_info,
+};
+
+static const struct udevice_id rk3588_dmc_ids[] = {
+ { .compatible = "rockchip,rk3588-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3588) = {
+ .name = "rockchip_rk3588_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3588_dmc_ids,
+ .ops = &rk3588_dmc_ops,
+ .probe = rk3588_dmc_probe,
+ .priv_auto = sizeof(struct dram_info),
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 08/16] dt-bindings: power: Add power-domain header for rk3588
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (6 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 07/16] ram: rockchip: Add rk3588 ddr driver support Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 09/16] dt-bindings: reset: add rk3588 reset definitions Jagan Teki
` (8 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Finley Xiao
Add power-domain header for RK3588 SoC from description in TRM.
commit <67944950c2d0> ("dt-bindings: power: add power-domain header for
rk3588")
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
include/dt-bindings/power/rk3588-power.h | 69 ++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/dt-bindings/power/rk3588-power.h
diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h
new file mode 100644
index 0000000000..1b92fec013
--- /dev/null
+++ b/include/dt-bindings/power/rk3588-power.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__
+#define __DT_BINDINGS_POWER_RK3588_POWER_H__
+
+/* VD_LITDSU */
+#define RK3588_PD_CPU_0 0
+#define RK3588_PD_CPU_1 1
+#define RK3588_PD_CPU_2 2
+#define RK3588_PD_CPU_3 3
+
+/* VD_BIGCORE0 */
+#define RK3588_PD_CPU_4 4
+#define RK3588_PD_CPU_5 5
+
+/* VD_BIGCORE1 */
+#define RK3588_PD_CPU_6 6
+#define RK3588_PD_CPU_7 7
+
+/* VD_NPU */
+#define RK3588_PD_NPU 8
+#define RK3588_PD_NPUTOP 9
+#define RK3588_PD_NPU1 10
+#define RK3588_PD_NPU2 11
+
+/* VD_GPU */
+#define RK3588_PD_GPU 12
+
+/* VD_VCODEC */
+#define RK3588_PD_VCODEC 13
+#define RK3588_PD_RKVDEC0 14
+#define RK3588_PD_RKVDEC1 15
+#define RK3588_PD_VENC0 16
+#define RK3588_PD_VENC1 17
+
+/* VD_DD01 */
+#define RK3588_PD_DDR01 18
+
+/* VD_DD23 */
+#define RK3588_PD_DDR23 19
+
+/* VD_LOGIC */
+#define RK3588_PD_CENTER 20
+#define RK3588_PD_VDPU 21
+#define RK3588_PD_RGA30 22
+#define RK3588_PD_AV1 23
+#define RK3588_PD_VOP 24
+#define RK3588_PD_VO0 25
+#define RK3588_PD_VO1 26
+#define RK3588_PD_VI 27
+#define RK3588_PD_ISP1 28
+#define RK3588_PD_FEC 29
+#define RK3588_PD_RGA31 30
+#define RK3588_PD_USB 31
+#define RK3588_PD_PHP 32
+#define RK3588_PD_GMAC 33
+#define RK3588_PD_PCIE 34
+#define RK3588_PD_NVM 35
+#define RK3588_PD_NVM0 36
+#define RK3588_PD_SDIO 37
+#define RK3588_PD_AUDIO 38
+#define RK3588_PD_SECURE 39
+#define RK3588_PD_SDMMC 40
+#define RK3588_PD_CRYPTO 41
+#define RK3588_PD_BUS 42
+
+/* VD_PMU */
+#define RK3588_PD_PMU1 43
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 09/16] dt-bindings: reset: add rk3588 reset definitions
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (7 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 08/16] dt-bindings: power: Add power-domain header for rk3588 Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 10/16] arm: rockchip: Add ioc header for rk3588 Jagan Teki
` (7 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Sebastian Reichel
Add reset ID defines for rk3588.
commit <0a8eb7dae617> ("dt-bindings: reset: add rk3588 reset
definitions")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++++++++++++++++
1 file changed, 754 insertions(+)
create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h
diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h
new file mode 100644
index 0000000000..738e56aead
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
@@ -0,0 +1,754 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2022 Collabora Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
+
+#define SRST_A_TOP_BIU 0
+#define SRST_P_TOP_BIU 1
+#define SRST_P_CSIPHY0 2
+#define SRST_CSIPHY0 3
+#define SRST_P_CSIPHY1 4
+#define SRST_CSIPHY1 5
+#define SRST_A_TOP_M500_BIU 6
+
+#define SRST_A_TOP_M400_BIU 7
+#define SRST_A_TOP_S200_BIU 8
+#define SRST_A_TOP_S400_BIU 9
+#define SRST_A_TOP_M300_BIU 10
+#define SRST_USBDP_COMBO_PHY0_INIT 11
+#define SRST_USBDP_COMBO_PHY0_CMN 12
+#define SRST_USBDP_COMBO_PHY0_LANE 13
+#define SRST_USBDP_COMBO_PHY0_PCS 14
+#define SRST_USBDP_COMBO_PHY1_INIT 15
+
+#define SRST_USBDP_COMBO_PHY1_CMN 16
+#define SRST_USBDP_COMBO_PHY1_LANE 17
+#define SRST_USBDP_COMBO_PHY1_PCS 18
+#define SRST_DCPHY0 19
+#define SRST_P_MIPI_DCPHY0 20
+#define SRST_P_MIPI_DCPHY0_GRF 21
+
+#define SRST_DCPHY1 22
+#define SRST_P_MIPI_DCPHY1 23
+#define SRST_P_MIPI_DCPHY1_GRF 24
+#define SRST_P_APB2ASB_SLV_CDPHY 25
+#define SRST_P_APB2ASB_SLV_CSIPHY 26
+#define SRST_P_APB2ASB_SLV_VCCIO3_5 27
+#define SRST_P_APB2ASB_SLV_VCCIO6 28
+#define SRST_P_APB2ASB_SLV_EMMCIO 29
+#define SRST_P_APB2ASB_SLV_IOC_TOP 30
+#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31
+
+#define SRST_P_CRU 32
+#define SRST_A_CHANNEL_SECURE2VO1USB 33
+#define SRST_A_CHANNEL_SECURE2CENTER 34
+#define SRST_H_CHANNEL_SECURE2VO1USB 35
+#define SRST_H_CHANNEL_SECURE2CENTER 36
+
+#define SRST_P_CHANNEL_SECURE2VO1USB 37
+#define SRST_P_CHANNEL_SECURE2CENTER 38
+
+#define SRST_H_AUDIO_BIU 39
+#define SRST_P_AUDIO_BIU 40
+#define SRST_H_I2S0_8CH 41
+#define SRST_M_I2S0_8CH_TX 42
+#define SRST_M_I2S0_8CH_RX 43
+#define SRST_P_ACDCDIG 44
+#define SRST_H_I2S2_2CH 45
+#define SRST_H_I2S3_2CH 46
+
+#define SRST_M_I2S2_2CH 47
+#define SRST_M_I2S3_2CH 48
+#define SRST_DAC_ACDCDIG 49
+#define SRST_H_SPDIF0 50
+
+#define SRST_M_SPDIF0 51
+#define SRST_H_SPDIF1 52
+#define SRST_M_SPDIF1 53
+#define SRST_H_PDM1 54
+#define SRST_PDM1 55
+
+#define SRST_A_BUS_BIU 56
+#define SRST_P_BUS_BIU 57
+#define SRST_A_GIC 58
+#define SRST_A_GIC_DBG 59
+#define SRST_A_DMAC0 60
+#define SRST_A_DMAC1 61
+#define SRST_A_DMAC2 62
+#define SRST_P_I2C1 63
+#define SRST_P_I2C2 64
+#define SRST_P_I2C3 65
+#define SRST_P_I2C4 66
+#define SRST_P_I2C5 67
+#define SRST_P_I2C6 68
+#define SRST_P_I2C7 69
+#define SRST_P_I2C8 70
+
+#define SRST_I2C1 71
+#define SRST_I2C2 72
+#define SRST_I2C3 73
+#define SRST_I2C4 74
+#define SRST_I2C5 75
+#define SRST_I2C6 76
+#define SRST_I2C7 77
+#define SRST_I2C8 78
+#define SRST_P_CAN0 79
+#define SRST_CAN0 80
+#define SRST_P_CAN1 81
+#define SRST_CAN1 82
+#define SRST_P_CAN2 83
+#define SRST_CAN2 84
+#define SRST_P_SARADC 85
+
+#define SRST_P_TSADC 86
+#define SRST_TSADC 87
+#define SRST_P_UART1 88
+#define SRST_P_UART2 89
+#define SRST_P_UART3 90
+#define SRST_P_UART4 91
+#define SRST_P_UART5 92
+#define SRST_P_UART6 93
+#define SRST_P_UART7 94
+#define SRST_P_UART8 95
+#define SRST_P_UART9 96
+#define SRST_S_UART1 97
+
+#define SRST_S_UART2 98
+#define SRST_S_UART3 99
+#define SRST_S_UART4 100
+#define SRST_S_UART5 101
+#define SRST_S_UART6 102
+#define SRST_S_UART7 103
+
+#define SRST_S_UART8 104
+#define SRST_S_UART9 105
+#define SRST_P_SPI0 106
+#define SRST_P_SPI1 107
+#define SRST_P_SPI2 108
+#define SRST_P_SPI3 109
+#define SRST_P_SPI4 110
+#define SRST_SPI0 111
+#define SRST_SPI1 112
+#define SRST_SPI2 113
+#define SRST_SPI3 114
+#define SRST_SPI4 115
+
+#define SRST_P_WDT0 116
+#define SRST_T_WDT0 117
+#define SRST_P_SYS_GRF 118
+#define SRST_P_PWM1 119
+#define SRST_PWM1 120
+#define SRST_P_PWM2 121
+#define SRST_PWM2 122
+#define SRST_P_PWM3 123
+#define SRST_PWM3 124
+#define SRST_P_BUSTIMER0 125
+#define SRST_P_BUSTIMER1 126
+#define SRST_BUSTIMER0 127
+
+#define SRST_BUSTIMER1 128
+#define SRST_BUSTIMER2 129
+#define SRST_BUSTIMER3 130
+#define SRST_BUSTIMER4 131
+#define SRST_BUSTIMER5 132
+#define SRST_BUSTIMER6 133
+#define SRST_BUSTIMER7 134
+#define SRST_BUSTIMER8 135
+#define SRST_BUSTIMER9 136
+#define SRST_BUSTIMER10 137
+#define SRST_BUSTIMER11 138
+#define SRST_P_MAILBOX0 139
+#define SRST_P_MAILBOX1 140
+#define SRST_P_MAILBOX2 141
+#define SRST_P_GPIO1 142
+#define SRST_GPIO1 143
+
+#define SRST_P_GPIO2 144
+#define SRST_GPIO2 145
+#define SRST_P_GPIO3 146
+#define SRST_GPIO3 147
+#define SRST_P_GPIO4 148
+#define SRST_GPIO4 149
+#define SRST_A_DECOM 150
+#define SRST_P_DECOM 151
+#define SRST_D_DECOM 152
+#define SRST_P_TOP 153
+#define SRST_A_GICADB_GIC2CORE_BUS 154
+#define SRST_P_DFT2APB 155
+#define SRST_P_APB2ASB_MST_TOP 156
+#define SRST_P_APB2ASB_MST_CDPHY 157
+#define SRST_P_APB2ASB_MST_BOT_RIGHT 158
+
+#define SRST_P_APB2ASB_MST_IOC_TOP 159
+#define SRST_P_APB2ASB_MST_IOC_RIGHT 160
+#define SRST_P_APB2ASB_MST_CSIPHY 161
+#define SRST_P_APB2ASB_MST_VCCIO3_5 162
+#define SRST_P_APB2ASB_MST_VCCIO6 163
+#define SRST_P_APB2ASB_MST_EMMCIO 164
+#define SRST_A_SPINLOCK 165
+#define SRST_P_OTPC_NS 166
+#define SRST_OTPC_NS 167
+#define SRST_OTPC_ARB 168
+
+#define SRST_P_BUSIOC 169
+#define SRST_P_PMUCM0_INTMUX 170
+#define SRST_P_DDRCM0_INTMUX 171
+
+#define SRST_P_DDR_DFICTL_CH0 172
+#define SRST_P_DDR_MON_CH0 173
+#define SRST_P_DDR_STANDBY_CH0 174
+#define SRST_P_DDR_UPCTL_CH0 175
+#define SRST_TM_DDR_MON_CH0 176
+#define SRST_P_DDR_GRF_CH01 177
+#define SRST_DFI_CH0 178
+#define SRST_SBR_CH0 179
+#define SRST_DDR_UPCTL_CH0 180
+#define SRST_DDR_DFICTL_CH0 181
+#define SRST_DDR_MON_CH0 182
+#define SRST_DDR_STANDBY_CH0 183
+#define SRST_A_DDR_UPCTL_CH0 184
+#define SRST_P_DDR_DFICTL_CH1 185
+#define SRST_P_DDR_MON_CH1 186
+#define SRST_P_DDR_STANDBY_CH1 187
+
+#define SRST_P_DDR_UPCTL_CH1 188
+#define SRST_TM_DDR_MON_CH1 189
+#define SRST_DFI_CH1 190
+#define SRST_SBR_CH1 191
+#define SRST_DDR_UPCTL_CH1 192
+#define SRST_DDR_DFICTL_CH1 193
+#define SRST_DDR_MON_CH1 194
+#define SRST_DDR_STANDBY_CH1 195
+#define SRST_A_DDR_UPCTL_CH1 196
+#define SRST_A_DDR01_MSCH0 197
+#define SRST_A_DDR01_RS_MSCH0 198
+#define SRST_A_DDR01_FRS_MSCH0 199
+
+#define SRST_A_DDR01_SCRAMBLE0 200
+#define SRST_A_DDR01_FRS_SCRAMBLE0 201
+#define SRST_A_DDR01_MSCH1 202
+#define SRST_A_DDR01_RS_MSCH1 203
+#define SRST_A_DDR01_FRS_MSCH1 204
+#define SRST_A_DDR01_SCRAMBLE1 205
+#define SRST_A_DDR01_FRS_SCRAMBLE1 206
+#define SRST_P_DDR01_MSCH0 207
+#define SRST_P_DDR01_MSCH1 208
+
+#define SRST_P_DDR_DFICTL_CH2 209
+#define SRST_P_DDR_MON_CH2 210
+#define SRST_P_DDR_STANDBY_CH2 211
+#define SRST_P_DDR_UPCTL_CH2 212
+#define SRST_TM_DDR_MON_CH2 213
+#define SRST_P_DDR_GRF_CH23 214
+#define SRST_DFI_CH2 215
+#define SRST_SBR_CH2 216
+#define SRST_DDR_UPCTL_CH2 217
+#define SRST_DDR_DFICTL_CH2 218
+#define SRST_DDR_MON_CH2 219
+#define SRST_DDR_STANDBY_CH2 220
+#define SRST_A_DDR_UPCTL_CH2 221
+#define SRST_P_DDR_DFICTL_CH3 222
+#define SRST_P_DDR_MON_CH3 223
+#define SRST_P_DDR_STANDBY_CH3 224
+
+#define SRST_P_DDR_UPCTL_CH3 225
+#define SRST_TM_DDR_MON_CH3 226
+#define SRST_DFI_CH3 227
+#define SRST_SBR_CH3 228
+#define SRST_DDR_UPCTL_CH3 229
+#define SRST_DDR_DFICTL_CH3 230
+#define SRST_DDR_MON_CH3 231
+#define SRST_DDR_STANDBY_CH3 232
+#define SRST_A_DDR_UPCTL_CH3 233
+#define SRST_A_DDR23_MSCH2 234
+#define SRST_A_DDR23_RS_MSCH2 235
+#define SRST_A_DDR23_FRS_MSCH2 236
+
+#define SRST_A_DDR23_SCRAMBLE2 237
+#define SRST_A_DDR23_FRS_SCRAMBLE2 238
+#define SRST_A_DDR23_MSCH3 239
+#define SRST_A_DDR23_RS_MSCH3 240
+#define SRST_A_DDR23_FRS_MSCH3 241
+#define SRST_A_DDR23_SCRAMBLE3 242
+#define SRST_A_DDR23_FRS_SCRAMBLE3 243
+#define SRST_P_DDR23_MSCH2 244
+#define SRST_P_DDR23_MSCH3 245
+
+#define SRST_ISP1 246
+#define SRST_ISP1_VICAP 247
+#define SRST_A_ISP1_BIU 248
+#define SRST_H_ISP1_BIU 249
+
+#define SRST_A_RKNN1 250
+#define SRST_A_RKNN1_BIU 251
+#define SRST_H_RKNN1 252
+#define SRST_H_RKNN1_BIU 253
+
+#define SRST_A_RKNN2 254
+#define SRST_A_RKNN2_BIU 255
+#define SRST_H_RKNN2 256
+#define SRST_H_RKNN2_BIU 257
+
+#define SRST_A_RKNN_DSU0 258
+#define SRST_P_NPUTOP_BIU 259
+#define SRST_P_NPU_TIMER 260
+#define SRST_NPUTIMER0 261
+#define SRST_NPUTIMER1 262
+#define SRST_P_NPU_WDT 263
+#define SRST_T_NPU_WDT 264
+#define SRST_P_NPU_PVTM 265
+#define SRST_P_NPU_GRF 266
+#define SRST_NPU_PVTM 267
+
+#define SRST_NPU_PVTPLL 268
+#define SRST_H_NPU_CM0_BIU 269
+#define SRST_F_NPU_CM0_CORE 270
+#define SRST_T_NPU_CM0_JTAG 271
+#define SRST_A_RKNN0 272
+#define SRST_A_RKNN0_BIU 273
+#define SRST_H_RKNN0 274
+#define SRST_H_RKNN0_BIU 275
+
+#define SRST_H_NVM_BIU 276
+#define SRST_A_NVM_BIU 277
+#define SRST_H_EMMC 278
+#define SRST_A_EMMC 279
+#define SRST_C_EMMC 280
+#define SRST_B_EMMC 281
+#define SRST_T_EMMC 282
+#define SRST_S_SFC 283
+#define SRST_H_SFC 284
+#define SRST_H_SFC_XIP 285
+
+#define SRST_P_GRF 286
+#define SRST_P_DEC_BIU 287
+#define SRST_P_PHP_BIU 288
+#define SRST_A_PCIE_GRIDGE 289
+#define SRST_A_PHP_BIU 290
+#define SRST_A_GMAC0 291
+#define SRST_A_GMAC1 292
+#define SRST_A_PCIE_BIU 293
+#define SRST_PCIE0_POWER_UP 294
+#define SRST_PCIE1_POWER_UP 295
+#define SRST_PCIE2_POWER_UP 296
+
+#define SRST_PCIE3_POWER_UP 297
+#define SRST_PCIE4_POWER_UP 298
+#define SRST_P_PCIE0 299
+#define SRST_P_PCIE1 300
+#define SRST_P_PCIE2 301
+#define SRST_P_PCIE3 302
+
+#define SRST_P_PCIE4 303
+#define SRST_A_PHP_GIC_ITS 304
+#define SRST_A_MMU_PCIE 305
+#define SRST_A_MMU_PHP 306
+#define SRST_A_MMU_BIU 307
+
+#define SRST_A_USB3OTG2 308
+
+#define SRST_PMALIVE0 309
+#define SRST_PMALIVE1 310
+#define SRST_PMALIVE2 311
+#define SRST_A_SATA0 312
+#define SRST_A_SATA1 313
+#define SRST_A_SATA2 314
+#define SRST_RXOOB0 315
+#define SRST_RXOOB1 316
+#define SRST_RXOOB2 317
+#define SRST_ASIC0 318
+#define SRST_ASIC1 319
+#define SRST_ASIC2 320
+
+#define SRST_A_RKVDEC_CCU 321
+#define SRST_H_RKVDEC0 322
+#define SRST_A_RKVDEC0 323
+#define SRST_H_RKVDEC0_BIU 324
+#define SRST_A_RKVDEC0_BIU 325
+#define SRST_RKVDEC0_CA 326
+#define SRST_RKVDEC0_HEVC_CA 327
+#define SRST_RKVDEC0_CORE 328
+
+#define SRST_H_RKVDEC1 329
+#define SRST_A_RKVDEC1 330
+#define SRST_H_RKVDEC1_BIU 331
+#define SRST_A_RKVDEC1_BIU 332
+#define SRST_RKVDEC1_CA 333
+#define SRST_RKVDEC1_HEVC_CA 334
+#define SRST_RKVDEC1_CORE 335
+
+#define SRST_A_USB_BIU 336
+#define SRST_H_USB_BIU 337
+#define SRST_A_USB3OTG0 338
+#define SRST_A_USB3OTG1 339
+#define SRST_H_HOST0 340
+#define SRST_H_HOST_ARB0 341
+#define SRST_H_HOST1 342
+#define SRST_H_HOST_ARB1 343
+#define SRST_A_USB_GRF 344
+#define SRST_C_USB2P0_HOST0 345
+
+#define SRST_C_USB2P0_HOST1 346
+#define SRST_HOST_UTMI0 347
+#define SRST_HOST_UTMI1 348
+
+#define SRST_A_VDPU_BIU 349
+#define SRST_A_VDPU_LOW_BIU 350
+#define SRST_H_VDPU_BIU 351
+#define SRST_A_JPEG_DECODER_BIU 352
+#define SRST_A_VPU 353
+#define SRST_H_VPU 354
+#define SRST_A_JPEG_ENCODER0 355
+#define SRST_H_JPEG_ENCODER0 356
+#define SRST_A_JPEG_ENCODER1 357
+#define SRST_H_JPEG_ENCODER1 358
+#define SRST_A_JPEG_ENCODER2 359
+#define SRST_H_JPEG_ENCODER2 360
+
+#define SRST_A_JPEG_ENCODER3 361
+#define SRST_H_JPEG_ENCODER3 362
+#define SRST_A_JPEG_DECODER 363
+#define SRST_H_JPEG_DECODER 364
+#define SRST_H_IEP2P0 365
+#define SRST_A_IEP2P0 366
+#define SRST_IEP2P0_CORE 367
+#define SRST_H_RGA2 368
+#define SRST_A_RGA2 369
+#define SRST_RGA2_CORE 370
+#define SRST_H_RGA3_0 371
+#define SRST_A_RGA3_0 372
+#define SRST_RGA3_0_CORE 373
+
+#define SRST_H_RKVENC0_BIU 374
+#define SRST_A_RKVENC0_BIU 375
+#define SRST_H_RKVENC0 376
+#define SRST_A_RKVENC0 377
+#define SRST_RKVENC0_CORE 378
+
+#define SRST_H_RKVENC1_BIU 379
+#define SRST_A_RKVENC1_BIU 380
+#define SRST_H_RKVENC1 381
+#define SRST_A_RKVENC1 382
+#define SRST_RKVENC1_CORE 383
+
+#define SRST_A_VI_BIU 384
+#define SRST_H_VI_BIU 385
+#define SRST_P_VI_BIU 386
+#define SRST_D_VICAP 387
+#define SRST_A_VICAP 388
+#define SRST_H_VICAP 389
+#define SRST_ISP0 390
+#define SRST_ISP0_VICAP 391
+
+#define SRST_FISHEYE0 392
+#define SRST_FISHEYE1 393
+#define SRST_P_CSI_HOST_0 394
+#define SRST_P_CSI_HOST_1 395
+#define SRST_P_CSI_HOST_2 396
+#define SRST_P_CSI_HOST_3 397
+#define SRST_P_CSI_HOST_4 398
+#define SRST_P_CSI_HOST_5 399
+
+#define SRST_CSIHOST0_VICAP 400
+#define SRST_CSIHOST1_VICAP 401
+#define SRST_CSIHOST2_VICAP 402
+#define SRST_CSIHOST3_VICAP 403
+#define SRST_CSIHOST4_VICAP 404
+#define SRST_CSIHOST5_VICAP 405
+#define SRST_CIFIN 406
+
+#define SRST_A_VOP_BIU 407
+#define SRST_A_VOP_LOW_BIU 408
+#define SRST_H_VOP_BIU 409
+#define SRST_P_VOP_BIU 410
+#define SRST_H_VOP 411
+#define SRST_A_VOP 412
+#define SRST_D_VOP0 413
+#define SRST_D_VOP2HDMI_BRIDGE0 414
+#define SRST_D_VOP2HDMI_BRIDGE1 415
+
+#define SRST_D_VOP1 416
+#define SRST_D_VOP2 417
+#define SRST_D_VOP3 418
+#define SRST_P_VOPGRF 419
+#define SRST_P_DSIHOST0 420
+#define SRST_P_DSIHOST1 421
+#define SRST_DSIHOST0 422
+#define SRST_DSIHOST1 423
+#define SRST_VOP_PMU 424
+#define SRST_P_VOP_CHANNEL_BIU 425
+
+#define SRST_H_VO0_BIU 426
+#define SRST_H_VO0_S_BIU 427
+#define SRST_P_VO0_BIU 428
+#define SRST_P_VO0_S_BIU 429
+#define SRST_A_HDCP0_BIU 430
+#define SRST_P_VO0GRF 431
+#define SRST_H_HDCP_KEY0 432
+#define SRST_A_HDCP0 433
+#define SRST_H_HDCP0 434
+#define SRST_HDCP0 435
+
+#define SRST_P_TRNG0 436
+#define SRST_DP0 437
+#define SRST_DP1 438
+#define SRST_H_I2S4_8CH 439
+#define SRST_M_I2S4_8CH_TX 440
+#define SRST_H_I2S8_8CH 441
+
+#define SRST_M_I2S8_8CH_TX 442
+#define SRST_H_SPDIF2_DP0 443
+#define SRST_M_SPDIF2_DP0 444
+#define SRST_H_SPDIF5_DP1 445
+#define SRST_M_SPDIF5_DP1 446
+
+#define SRST_A_HDCP1_BIU 447
+#define SRST_A_VO1_BIU 448
+#define SRST_H_VOP1_BIU 449
+#define SRST_H_VOP1_S_BIU 450
+#define SRST_P_VOP1_BIU 451
+#define SRST_P_VO1GRF 452
+#define SRST_P_VO1_S_BIU 453
+
+#define SRST_H_I2S7_8CH 454
+#define SRST_M_I2S7_8CH_RX 455
+#define SRST_H_HDCP_KEY1 456
+#define SRST_A_HDCP1 457
+#define SRST_H_HDCP1 458
+#define SRST_HDCP1 459
+#define SRST_P_TRNG1 460
+#define SRST_P_HDMITX0 461
+
+#define SRST_HDMITX0_REF 462
+#define SRST_P_HDMITX1 463
+#define SRST_HDMITX1_REF 464
+#define SRST_A_HDMIRX 465
+#define SRST_P_HDMIRX 466
+#define SRST_HDMIRX_REF 467
+
+#define SRST_P_EDP0 468
+#define SRST_EDP0_24M 469
+#define SRST_P_EDP1 470
+#define SRST_EDP1_24M 471
+#define SRST_M_I2S5_8CH_TX 472
+#define SRST_H_I2S5_8CH 473
+#define SRST_M_I2S6_8CH_TX 474
+
+#define SRST_M_I2S6_8CH_RX 475
+#define SRST_H_I2S6_8CH 476
+#define SRST_H_SPDIF3 477
+#define SRST_M_SPDIF3 478
+#define SRST_H_SPDIF4 479
+#define SRST_M_SPDIF4 480
+#define SRST_H_SPDIFRX0 481
+#define SRST_M_SPDIFRX0 482
+#define SRST_H_SPDIFRX1 483
+#define SRST_M_SPDIFRX1 484
+
+#define SRST_H_SPDIFRX2 485
+#define SRST_M_SPDIFRX2 486
+#define SRST_LINKSYM_HDMITXPHY0 487
+#define SRST_LINKSYM_HDMITXPHY1 488
+#define SRST_VO1_BRIDGE0 489
+#define SRST_VO1_BRIDGE1 490
+
+#define SRST_H_I2S9_8CH 491
+#define SRST_M_I2S9_8CH_RX 492
+#define SRST_H_I2S10_8CH 493
+#define SRST_M_I2S10_8CH_RX 494
+#define SRST_P_S_HDMIRX 495
+
+#define SRST_GPU 496
+#define SRST_SYS_GPU 497
+#define SRST_A_S_GPU_BIU 498
+#define SRST_A_M0_GPU_BIU 499
+#define SRST_A_M1_GPU_BIU 500
+#define SRST_A_M2_GPU_BIU 501
+#define SRST_A_M3_GPU_BIU 502
+#define SRST_P_GPU_BIU 503
+#define SRST_P_GPU_PVTM 504
+
+#define SRST_GPU_PVTM 505
+#define SRST_P_GPU_GRF 506
+#define SRST_GPU_PVTPLL 507
+#define SRST_GPU_JTAG 508
+
+#define SRST_A_AV1_BIU 509
+#define SRST_A_AV1 510
+#define SRST_P_AV1_BIU 511
+#define SRST_P_AV1 512
+
+#define SRST_A_DDR_BIU 513
+#define SRST_A_DMA2DDR 514
+#define SRST_A_DDR_SHAREMEM 515
+#define SRST_A_DDR_SHAREMEM_BIU 516
+#define SRST_A_CENTER_S200_BIU 517
+#define SRST_A_CENTER_S400_BIU 518
+#define SRST_H_AHB2APB 519
+#define SRST_H_CENTER_BIU 520
+#define SRST_F_DDR_CM0_CORE 521
+
+#define SRST_DDR_TIMER0 522
+#define SRST_DDR_TIMER1 523
+#define SRST_T_WDT_DDR 524
+#define SRST_T_DDR_CM0_JTAG 525
+#define SRST_P_CENTER_GRF 526
+#define SRST_P_AHB2APB 527
+#define SRST_P_WDT 528
+#define SRST_P_TIMER 529
+#define SRST_P_DMA2DDR 530
+#define SRST_P_SHAREMEM 531
+#define SRST_P_CENTER_BIU 532
+#define SRST_P_CENTER_CHANNEL_BIU 533
+
+#define SRST_P_USBDPGRF0 534
+#define SRST_P_USBDPPHY0 535
+#define SRST_P_USBDPGRF1 536
+#define SRST_P_USBDPPHY1 537
+#define SRST_P_HDPTX0 538
+#define SRST_P_HDPTX1 539
+#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540
+#define SRST_P_USB2PHY_U3_0_GRF0 541
+#define SRST_P_USB2PHY_U3_1_GRF0 542
+#define SRST_P_USB2PHY_U2_0_GRF0 543
+#define SRST_P_USB2PHY_U2_1_GRF0 544
+#define SRST_HDPTX0_ROPLL 545
+#define SRST_HDPTX0_LCPLL 546
+#define SRST_HDPTX0 547
+#define SRST_HDPTX1_ROPLL 548
+
+#define SRST_HDPTX1_LCPLL 549
+#define SRST_HDPTX1 550
+#define SRST_HDPTX0_HDMIRXPHY_SET 551
+#define SRST_USBDP_COMBO_PHY0 552
+#define SRST_USBDP_COMBO_PHY0_LCPLL 553
+#define SRST_USBDP_COMBO_PHY0_ROPLL 554
+#define SRST_USBDP_COMBO_PHY0_PCS_HS 555
+#define SRST_USBDP_COMBO_PHY1 556
+#define SRST_USBDP_COMBO_PHY1_LCPLL 557
+#define SRST_USBDP_COMBO_PHY1_ROPLL 558
+#define SRST_USBDP_COMBO_PHY1_PCS_HS 559
+#define SRST_HDMIHDP0 560
+#define SRST_HDMIHDP1 561
+
+#define SRST_A_VO1USB_TOP_BIU 562
+#define SRST_H_VO1USB_TOP_BIU 563
+
+#define SRST_H_SDIO_BIU 564
+#define SRST_H_SDIO 565
+#define SRST_SDIO 566
+
+#define SRST_H_RGA3_BIU 567
+#define SRST_A_RGA3_BIU 568
+#define SRST_H_RGA3_1 569
+#define SRST_A_RGA3_1 570
+#define SRST_RGA3_1_CORE 571
+
+#define SRST_REF_PIPE_PHY0 572
+#define SRST_REF_PIPE_PHY1 573
+#define SRST_REF_PIPE_PHY2 574
+
+#define SRST_P_PHPTOP_CRU 575
+#define SRST_P_PCIE2_GRF0 576
+#define SRST_P_PCIE2_GRF1 577
+#define SRST_P_PCIE2_GRF2 578
+#define SRST_P_PCIE2_PHY0 579
+#define SRST_P_PCIE2_PHY1 580
+#define SRST_P_PCIE2_PHY2 581
+#define SRST_P_PCIE3_PHY 582
+#define SRST_P_APB2ASB_SLV_CHIP_TOP 583
+#define SRST_PCIE30_PHY 584
+
+#define SRST_H_PMU1_BIU 585
+#define SRST_P_PMU1_BIU 586
+#define SRST_H_PMU_CM0_BIU 587
+#define SRST_F_PMU_CM0_CORE 588
+#define SRST_T_PMU1_CM0_JTAG 589
+
+#define SRST_DDR_FAIL_SAFE 590
+#define SRST_P_CRU_PMU1 591
+#define SRST_P_PMU1_GRF 592
+#define SRST_P_PMU1_IOC 593
+#define SRST_P_PMU1WDT 594
+#define SRST_T_PMU1WDT 595
+#define SRST_P_PMU1TIMER 596
+#define SRST_PMU1TIMER0 597
+#define SRST_PMU1TIMER1 598
+#define SRST_P_PMU1PWM 599
+#define SRST_PMU1PWM 600
+
+#define SRST_P_I2C0 601
+#define SRST_I2C0 602
+#define SRST_S_UART0 603
+#define SRST_P_UART0 604
+#define SRST_H_I2S1_8CH 605
+#define SRST_M_I2S1_8CH_TX 606
+#define SRST_M_I2S1_8CH_RX 607
+#define SRST_H_PDM0 608
+#define SRST_PDM0 609
+
+#define SRST_H_VAD 610
+#define SRST_HDPTX0_INIT 611
+#define SRST_HDPTX0_CMN 612
+#define SRST_HDPTX0_LANE 613
+#define SRST_HDPTX1_INIT 614
+
+#define SRST_HDPTX1_CMN 615
+#define SRST_HDPTX1_LANE 616
+#define SRST_M_MIPI_DCPHY0 617
+#define SRST_S_MIPI_DCPHY0 618
+#define SRST_M_MIPI_DCPHY1 619
+#define SRST_S_MIPI_DCPHY1 620
+#define SRST_OTGPHY_U3_0 621
+#define SRST_OTGPHY_U3_1 622
+#define SRST_OTGPHY_U2_0 623
+#define SRST_OTGPHY_U2_1 624
+
+#define SRST_P_PMU0GRF 625
+#define SRST_P_PMU0IOC 626
+#define SRST_P_GPIO0 627
+#define SRST_GPIO0 628
+
+#define SRST_A_SECURE_NS_BIU 629
+#define SRST_H_SECURE_NS_BIU 630
+#define SRST_A_SECURE_S_BIU 631
+#define SRST_H_SECURE_S_BIU 632
+#define SRST_P_SECURE_S_BIU 633
+#define SRST_CRYPTO_CORE 634
+
+#define SRST_CRYPTO_PKA 635
+#define SRST_CRYPTO_RNG 636
+#define SRST_A_CRYPTO 637
+#define SRST_H_CRYPTO 638
+#define SRST_KEYLADDER_CORE 639
+#define SRST_KEYLADDER_RNG 640
+#define SRST_A_KEYLADDER 641
+#define SRST_H_KEYLADDER 642
+#define SRST_P_OTPC_S 643
+#define SRST_OTPC_S 644
+#define SRST_WDT_S 645
+
+#define SRST_T_WDT_S 646
+#define SRST_H_BOOTROM 647
+#define SRST_A_DCF 648
+#define SRST_P_DCF 649
+#define SRST_H_BOOTROM_NS 650
+#define SRST_P_KEYLADDER 651
+#define SRST_H_TRNG_S 652
+
+#define SRST_H_TRNG_NS 653
+#define SRST_D_SDMMC_BUFFER 654
+#define SRST_H_SDMMC 655
+#define SRST_H_SDMMC_BUFFER 656
+#define SRST_SDMMC 657
+#define SRST_P_TRNG_CHK 658
+#define SRST_TRNG_S 659
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 10/16] arm: rockchip: Add ioc header for rk3588
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (8 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 09/16] dt-bindings: reset: add rk3588 reset definitions Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC Jagan Teki
` (6 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Steven Liu, Joseph Chen
Add IOC unit header include for rk3588.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../include/asm/arch-rockchip/ioc_rk3588.h | 102 ++++++++++++++++++
1 file changed, 102 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
new file mode 100644
index 0000000000..2fd47b5d1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_IOC_RK3588_H
+#define _ASM_ARCH_IOC_RK3588_H
+
+#include <common.h>
+
+struct rk3588_bus_ioc {
+ uint32_t reserved0000[3]; /* Address Offset: 0x0000 */
+ uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
+ uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
+ uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
+ uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
+ uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
+ uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
+ uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
+ uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
+ uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
+ uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
+ uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
+ uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
+ uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
+ uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
+ uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
+ uint32_t gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */
+ uint32_t gpio2b_iomux_sel_h; /* Address Offset: 0x004C */
+ uint32_t gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */
+ uint32_t gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */
+ uint32_t gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */
+ uint32_t gpio2d_iomux_sel_h; /* Address Offset: 0x005C */
+ uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
+ uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
+ uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
+ uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
+ uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
+ uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */
+ uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */
+ uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x007C */
+ uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
+ uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
+ uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
+ uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
+ uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
+ uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
+ uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
+ uint32_t gpio4d_iomux_sel_h; /* Address Offset: 0x009C */
+};
+check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
+
+
+struct rk3588_pmu1_ioc {
+ uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
+ uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
+ uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */
+ uint32_t reserved0012; /* Address Offset: 0x000C */
+ uint32_t gpio0a_ds_l; /* Address Offset: 0x0010 */
+ uint32_t gpio0a_ds_h; /* Address Offset: 0x0014 */
+ uint32_t gpio0b_ds_l; /* Address Offset: 0x0018 */
+ uint32_t reserved0028; /* Address Offset: 0x001C */
+ uint32_t gpio0a_p; /* Address Offset: 0x0020 */
+ uint32_t gpio0b_p; /* Address Offset: 0x0024 */
+ uint32_t gpio0a_ie; /* Address Offset: 0x0028 */
+ uint32_t gpio0b_ie; /* Address Offset: 0x002C */
+ uint32_t gpio0a_smt; /* Address Offset: 0x0030 */
+ uint32_t gpio0b_smt; /* Address Offset: 0x0034 */
+ uint32_t gpio0a_pdis; /* Address Offset: 0x0038 */
+ uint32_t gpio0b_pdis; /* Address Offset: 0x003C */
+ uint32_t xin_con; /* Address Offset: 0x0040 */
+};
+check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
+
+struct rk3588_pmu2_ioc {
+ uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
+ uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
+ uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */
+ uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x000C */
+ uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */
+ uint32_t gpio0b_ds_h; /* Address Offset: 0x0014 */
+ uint32_t gpio0c_ds_l; /* Address Offset: 0x0018 */
+ uint32_t gpio0c_ds_h; /* Address Offset: 0x001C */
+ uint32_t gpio0d_ds_l; /* Address Offset: 0x0020 */
+ uint32_t gpio0d_ds_h; /* Address Offset: 0x0024 */
+ uint32_t gpio0b_p; /* Address Offset: 0x0028 */
+ uint32_t gpio0c_p; /* Address Offset: 0x002C */
+ uint32_t gpio0d_p; /* Address Offset: 0x0030 */
+ uint32_t gpio0b_ie; /* Address Offset: 0x0034 */
+ uint32_t gpio0c_ie; /* Address Offset: 0x0038 */
+ uint32_t gpio0d_ie; /* Address Offset: 0x003C */
+ uint32_t gpio0b_smt; /* Address Offset: 0x0040 */
+ uint32_t gpio0c_smt; /* Address Offset: 0x0044 */
+ uint32_t gpio0d_smt; /* Address Offset: 0x0048 */
+ uint32_t gpio0b_pdis; /* Address Offset: 0x004C */
+ uint32_t gpio0c_pdis; /* Address Offset: 0x0050 */
+ uint32_t gpio0d_pdis; /* Address Offset: 0x0054 */
+};
+check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054);
+
+#endif
+
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (9 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 10/16] arm: rockchip: Add ioc header for rk3588 Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-02-02 14:06 ` Eugen Hristev
2023-01-25 22:27 ` [RFC PATCH 12/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM Jagan Teki
` (5 subsequent siblings)
16 siblings, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jagan Teki, Jianqun Xu
This initial version supports CPU, dma, interrupts, timers, UART and
SDHCI (everything necessary to boot Linux on this system on chip) as
well as Ethernet, I2C, PWM and SPI.
The DT is split into rk3588 and rk3588s, which is a reduced version
(i.e. with less peripherals) of the former.
commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588
SoC")
commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/dts/rk3588-pinctrl.dtsi | 516 +++++
arch/arm/dts/rk3588.dtsi | 58 +
arch/arm/dts/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++++++++++++++
arch/arm/dts/rk3588s.dtsi | 1703 +++++++++++++++
4 files changed, 5680 insertions(+)
create mode 100644 arch/arm/dts/rk3588-pinctrl.dtsi
create mode 100644 arch/arm/dts/rk3588.dtsi
create mode 100644 arch/arm/dts/rk3588s-pinctrl.dtsi
create mode 100644 arch/arm/dts/rk3588s.dtsi
diff --git a/arch/arm/dts/rk3588-pinctrl.dtsi b/arch/arm/dts/rk3588-pinctrl.dtsi
new file mode 100644
index 0000000000..244c66faa1
--- /dev/null
+++ b/arch/arm/dts/rk3588-pinctrl.dtsi
@@ -0,0 +1,516 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ clk32k {
+ /omit-if-no-ref/
+ clk32k_out1: clk32k-out1 {
+ rockchip,pins =
+ /* clk32k_out1 */
+ <2 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ };
+
+ eth0 {
+ /omit-if-no-ref/
+ eth0_pins: eth0-pins {
+ rockchip,pins =
+ /* eth0_refclko_25m */
+ <2 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspim1_pins: fspim1-pins {
+ rockchip,pins =
+ /* fspi_clk_m1 */
+ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_cs0n_m1 */
+ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d0_m1 */
+ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d1_m1 */
+ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d2_m1 */
+ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d3_m1 */
+ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim1_cs1: fspim1-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n_m1 */
+ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+
+ gmac0 {
+ /omit-if-no-ref/
+ gmac0_miim: gmac0-miim {
+ rockchip,pins =
+ /* gmac0_mdc */
+ <4 RK_PC4 1 &pcfg_pull_none>,
+ /* gmac0_mdio */
+ <4 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_clkinout: gmac0-clkinout {
+ rockchip,pins =
+ /* gmac0_mclkinout */
+ <4 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rx_bus2: gmac0-rx-bus2 {
+ rockchip,pins =
+ /* gmac0_rxd0 */
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ /* gmac0_rxd1 */
+ <2 RK_PC2 1 &pcfg_pull_none>,
+ /* gmac0_rxdv_crs */
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_tx_bus2: gmac0-tx-bus2 {
+ rockchip,pins =
+ /* gmac0_txd0 */
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ /* gmac0_txd1 */
+ <2 RK_PB7 1 &pcfg_pull_none>,
+ /* gmac0_txen */
+ <2 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_clk: gmac0-rgmii-clk {
+ rockchip,pins =
+ /* gmac0_rxclk */
+ <2 RK_PB0 1 &pcfg_pull_none>,
+ /* gmac0_txclk */
+ <2 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_bus: gmac0-rgmii-bus {
+ rockchip,pins =
+ /* gmac0_rxd2 */
+ <2 RK_PA6 1 &pcfg_pull_none>,
+ /* gmac0_rxd3 */
+ <2 RK_PA7 1 &pcfg_pull_none>,
+ /* gmac0_txd2 */
+ <2 RK_PB1 1 &pcfg_pull_none>,
+ /* gmac0_txd3 */
+ <2 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_ppsclk: gmac0-ppsclk {
+ rockchip,pins =
+ /* gmac0_ppsclk */
+ <2 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_ppstring: gmac0-ppstring {
+ rockchip,pins =
+ /* gmac0_ppstring */
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_ptp_refclk: gmac0-ptp-refclk {
+ rockchip,pins =
+ /* gmac0_ptp_refclk */
+ <2 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_txer: gmac0-txer {
+ rockchip,pins =
+ /* gmac0_txer */
+ <4 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ };
+
+ hdmi {
+ /omit-if-no-ref/
+ hdmim0_tx1_cec: hdmim0-tx1-cec {
+ rockchip,pins =
+ /* hdmim0_tx1_cec */
+ <2 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx1_scl: hdmim0-tx1-scl {
+ rockchip,pins =
+ /* hdmim0_tx1_scl */
+ <2 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx1_sda: hdmim0-tx1-sda {
+ rockchip,pins =
+ /* hdmim0_tx1_sda */
+ <2 RK_PB4 4 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <4 RK_PC5 9 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <4 RK_PC6 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <2 RK_PC1 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <2 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m3_xfer: i2c3m3-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m3 */
+ <2 RK_PB2 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m3 */
+ <2 RK_PB3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <2 RK_PB5 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m1 */
+ <2 RK_PB4 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m4_xfer: i2c5m4-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m4 */
+ <2 RK_PB6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m4 */
+ <2 RK_PB7 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m2_xfer: i2c6m2-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m2 */
+ <2 RK_PC3 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m2 */
+ <2 RK_PC2 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7m1_xfer: i2c7m1-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m1 */
+ <4 RK_PC3 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m1 */
+ <4 RK_PC4 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c8 {
+ /omit-if-no-ref/
+ i2c8m1_xfer: i2c8m1-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m1 */
+ <2 RK_PB0 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m1 */
+ <2 RK_PB1 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m0_lrck: i2s2m0-lrck {
+ rockchip,pins =
+ /* i2s2m0_lrck */
+ <2 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2m0_mclk */
+ <2 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins =
+ /* i2s2m0_sclk */
+ <2 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2m0_sdi */
+ <2 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2m0_sdo */
+ <4 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m2_pins: pwm2m2-pins {
+ rockchip,pins =
+ /* pwm2_m2 */
+ <4 RK_PC2 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <4 RK_PC3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m2_pins: pwm5m2-pins {
+ rockchip,pins =
+ /* pwm5_m2 */
+ <4 RK_PC4 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m2_pins: pwm6m2-pins {
+ rockchip,pins =
+ /* pwm6_m2 */
+ <4 RK_PC5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m3_pins: pwm7m3-pins {
+ rockchip,pins =
+ /* pwm7_ir_m3 */
+ <4 RK_PC6 11 &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ /omit-if-no-ref/
+ sdiom0_pins: sdiom0-pins {
+ rockchip,pins =
+ /* sdio_clk_m0 */
+ <2 RK_PB3 2 &pcfg_pull_none>,
+ /* sdio_cmd_m0 */
+ <2 RK_PB2 2 &pcfg_pull_none>,
+ /* sdio_d0_m0 */
+ <2 RK_PA6 2 &pcfg_pull_none>,
+ /* sdio_d1_m0 */
+ <2 RK_PA7 2 &pcfg_pull_none>,
+ /* sdio_d2_m0 */
+ <2 RK_PB0 2 &pcfg_pull_none>,
+ /* sdio_d3_m0 */
+ <2 RK_PB1 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clk_m0 */
+ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_miso_m0 */
+ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosi_m0 */
+ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs0: spi1m0-cs0 {
+ rockchip,pins =
+ /* spi1_cs0_m0 */
+ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs1: spi1m0-cs1 {
+ rockchip,pins =
+ /* spi1_cs1_m0 */
+ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m0_pins: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clk_m0 */
+ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_miso_m0 */
+ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosi_m0 */
+ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs0: spi3m0-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m0 */
+ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs1: spi3m0-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m0 */
+ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <2 RK_PB6 10 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <2 RK_PB7 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <2 RK_PC1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <2 RK_PC0 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <2 RK_PA6 10 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <2 RK_PA7 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <2 RK_PB1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <2 RK_PB0 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <2 RK_PB4 10 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <2 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <4 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <4 RK_PC2 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rx_m0 */
+ <2 RK_PC4 10 &pcfg_pull_up>,
+ /* uart9_tx_m0 */
+ <2 RK_PC2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <4 RK_PC5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <4 RK_PC4 10 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi
new file mode 100644
index 0000000000..d085e57fbc
--- /dev/null
+++ b/arch/arm/dts/rk3588.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk3588s.dtsi"
+#include "rk3588-pinctrl.dtsi"
+
+/ {
+ gmac0: ethernet@fe1b0000 {
+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe1b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
+ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
+ <&cru CLK_GMAC0_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ power-domains = <&power RK3588_PD_GMAC>;
+ resets = <&cru SRST_A_GMAC0>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&sys_grf>;
+ rockchip,php-grf = <&php_grf>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi
new file mode 100644
index 0000000000..48181671ea
--- /dev/null
+++ b/arch/arm/dts/rk3588s-pinctrl.dtsi
@@ -0,0 +1,3403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ auddsm {
+ /omit-if-no-ref/
+ auddsm_pins: auddsm-pins {
+ rockchip,pins =
+ /* auddsm_ln */
+ <3 RK_PA1 4 &pcfg_pull_none>,
+ /* auddsm_lp */
+ <3 RK_PA2 4 &pcfg_pull_none>,
+ /* auddsm_rn */
+ <3 RK_PA3 4 &pcfg_pull_none>,
+ /* auddsm_rp */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ bt1120 {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ /* bt1120_clkout */
+ <4 RK_PB0 2 &pcfg_pull_none>,
+ /* bt1120_d0 */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* bt1120_d1 */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* bt1120_d2 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* bt1120_d3 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* bt1120_d4 */
+ <4 RK_PA4 2 &pcfg_pull_none>,
+ /* bt1120_d5 */
+ <4 RK_PA5 2 &pcfg_pull_none>,
+ /* bt1120_d6 */
+ <4 RK_PA6 2 &pcfg_pull_none>,
+ /* bt1120_d7 */
+ <4 RK_PA7 2 &pcfg_pull_none>,
+ /* bt1120_d8 */
+ <4 RK_PB2 2 &pcfg_pull_none>,
+ /* bt1120_d9 */
+ <4 RK_PB3 2 &pcfg_pull_none>,
+ /* bt1120_d10 */
+ <4 RK_PB4 2 &pcfg_pull_none>,
+ /* bt1120_d11 */
+ <4 RK_PB5 2 &pcfg_pull_none>,
+ /* bt1120_d12 */
+ <4 RK_PB6 2 &pcfg_pull_none>,
+ /* bt1120_d13 */
+ <4 RK_PB7 2 &pcfg_pull_none>,
+ /* bt1120_d14 */
+ <4 RK_PC0 2 &pcfg_pull_none>,
+ /* bt1120_d15 */
+ <4 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rx_m0 */
+ <0 RK_PC0 11 &pcfg_pull_none>,
+ /* can0_tx_m0 */
+ <0 RK_PB7 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rx_m1 */
+ <4 RK_PD5 9 &pcfg_pull_none>,
+ /* can0_tx_m1 */
+ <4 RK_PD4 9 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rx_m0 */
+ <3 RK_PB5 9 &pcfg_pull_none>,
+ /* can1_tx_m0 */
+ <3 RK_PB6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rx_m1 */
+ <4 RK_PB2 12 &pcfg_pull_none>,
+ /* can1_tx_m1 */
+ <4 RK_PB3 12 &pcfg_pull_none>;
+ };
+ };
+
+ can2 {
+ /omit-if-no-ref/
+ can2m0_pins: can2m0-pins {
+ rockchip,pins =
+ /* can2_rx_m0 */
+ <3 RK_PC4 9 &pcfg_pull_none>,
+ /* can2_tx_m0 */
+ <3 RK_PC5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can2m1_pins: can2m1-pins {
+ rockchip,pins =
+ /* can2_rx_m1 */
+ <0 RK_PD4 10 &pcfg_pull_none>,
+ /* can2_tx_m1 */
+ <0 RK_PD5 10 &pcfg_pull_none>;
+ };
+ };
+
+ cif {
+ /omit-if-no-ref/
+ cif_clk: cif-clk {
+ rockchip,pins =
+ /* cif_clkout */
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_clk: cif-dvp-clk {
+ rockchip,pins =
+ /* cif_clkin */
+ <4 RK_PB0 1 &pcfg_pull_none>,
+ /* cif_href */
+ <4 RK_PB2 1 &pcfg_pull_none>,
+ /* cif_vsync */
+ <4 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus16: cif-dvp-bus16 {
+ rockchip,pins =
+ /* cif_d8 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* cif_d9 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* cif_d10 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* cif_d11 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* cif_d12 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* cif_d13 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* cif_d14 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* cif_d15 */
+ <3 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus8: cif-dvp-bus8 {
+ rockchip,pins =
+ /* cif_d0 */
+ <4 RK_PA0 1 &pcfg_pull_none>,
+ /* cif_d1 */
+ <4 RK_PA1 1 &pcfg_pull_none>,
+ /* cif_d2 */
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ /* cif_d3 */
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ /* cif_d4 */
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ /* cif_d5 */
+ <4 RK_PA5 1 &pcfg_pull_none>,
+ /* cif_d6 */
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ /* cif_d7 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ clk32k {
+ /omit-if-no-ref/
+ clk32k_in: clk32k-in {
+ rockchip,pins =
+ /* clk32k_in */
+ <0 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clk32k_out0: clk32k-out0 {
+ rockchip,pins =
+ /* clk32k_out0 */
+ <0 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ /omit-if-no-ref/
+ cpu_pins: cpu-pins {
+ rockchip,pins =
+ /* cpu_big0_avs */
+ <0 RK_PD1 2 &pcfg_pull_none>,
+ /* cpu_big1_avs */
+ <0 RK_PD5 2 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych0 {
+ /omit-if-no-ref/
+ ddrphych0_pins: ddrphych0-pins {
+ rockchip,pins =
+ /* ddrphych0_dtb0 */
+ <4 RK_PA0 7 &pcfg_pull_none>,
+ /* ddrphych0_dtb1 */
+ <4 RK_PA1 7 &pcfg_pull_none>,
+ /* ddrphych0_dtb2 */
+ <4 RK_PA2 7 &pcfg_pull_none>,
+ /* ddrphych0_dtb3 */
+ <4 RK_PA3 7 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych1 {
+ /omit-if-no-ref/
+ ddrphych1_pins: ddrphych1-pins {
+ rockchip,pins =
+ /* ddrphych1_dtb0 */
+ <4 RK_PA4 7 &pcfg_pull_none>,
+ /* ddrphych1_dtb1 */
+ <4 RK_PA5 7 &pcfg_pull_none>,
+ /* ddrphych1_dtb2 */
+ <4 RK_PA6 7 &pcfg_pull_none>,
+ /* ddrphych1_dtb3 */
+ <4 RK_PA7 7 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych2 {
+ /omit-if-no-ref/
+ ddrphych2_pins: ddrphych2-pins {
+ rockchip,pins =
+ /* ddrphych2_dtb0 */
+ <4 RK_PB0 7 &pcfg_pull_none>,
+ /* ddrphych2_dtb1 */
+ <4 RK_PB1 7 &pcfg_pull_none>,
+ /* ddrphych2_dtb2 */
+ <4 RK_PB2 7 &pcfg_pull_none>,
+ /* ddrphych2_dtb3 */
+ <4 RK_PB3 7 &pcfg_pull_none>;
+ };
+ };
+
+ ddrphych3 {
+ /omit-if-no-ref/
+ ddrphych3_pins: ddrphych3-pins {
+ rockchip,pins =
+ /* ddrphych3_dtb0 */
+ <4 RK_PB4 7 &pcfg_pull_none>,
+ /* ddrphych3_dtb1 */
+ <4 RK_PB5 7 &pcfg_pull_none>,
+ /* ddrphych3_dtb2 */
+ <4 RK_PB6 7 &pcfg_pull_none>,
+ /* ddrphych3_dtb3 */
+ <4 RK_PB7 7 &pcfg_pull_none>;
+ };
+ };
+
+ dp0 {
+ /omit-if-no-ref/
+ dp0m0_pins: dp0m0-pins {
+ rockchip,pins =
+ /* dp0_hpdin_m0 */
+ <4 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp0m1_pins: dp0m1-pins {
+ rockchip,pins =
+ /* dp0_hpdin_m1 */
+ <0 RK_PC4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp0m2_pins: dp0m2-pins {
+ rockchip,pins =
+ /* dp0_hpdin_m2 */
+ <1 RK_PA0 5 &pcfg_pull_none>;
+ };
+ };
+
+ dp1 {
+ /omit-if-no-ref/
+ dp1m0_pins: dp1m0-pins {
+ rockchip,pins =
+ /* dp1_hpdin_m0 */
+ <3 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp1m1_pins: dp1m1-pins {
+ rockchip,pins =
+ /* dp1_hpdin_m1 */
+ <0 RK_PC5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dp1m2_pins: dp1m2-pins {
+ rockchip,pins =
+ /* dp1_hpdin_m2 */
+ <1 RK_PA1 5 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <2 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clkout */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_data_strobe: emmc-data-strobe {
+ rockchip,pins =
+ /* emmc_data_strobe */
+ <2 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth1 {
+ /omit-if-no-ref/
+ eth1_pins: eth1-pins {
+ rockchip,pins =
+ /* eth1_refclko_25m */
+ <3 RK_PA6 1 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspim0_pins: fspim0-pins {
+ rockchip,pins =
+ /* fspi_clk_m0 */
+ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_cs0n_m0 */
+ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d0_m0 */
+ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d1_m0 */
+ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d2_m0 */
+ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d3_m0 */
+ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim0_cs1: fspim0-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n_m0 */
+ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim2_pins: fspim2-pins {
+ rockchip,pins =
+ /* fspi_clk_m2 */
+ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_cs0n_m2 */
+ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d0_m2 */
+ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d1_m2 */
+ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d2_m2 */
+ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
+ /* fspi_d3_m2 */
+ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ fspim2_cs1: fspim2-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n_m2 */
+ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+
+ gmac1 {
+ /omit-if-no-ref/
+ gmac1_miim: gmac1-miim {
+ rockchip,pins =
+ /* gmac1_mdc */
+ <3 RK_PC2 1 &pcfg_pull_none>,
+ /* gmac1_mdio */
+ <3 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_clkinout: gmac1-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinout */
+ <3 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_rx_bus2: gmac1-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* gmac1_rxd1 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* gmac1_rxdv_crs */
+ <3 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_tx_bus2: gmac1-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0 */
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ /* gmac1_txd1 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* gmac1_txen */
+ <3 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_rgmii_clk: gmac1-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclk */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* gmac1_txclk */
+ <3 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_rgmii_bus: gmac1-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2 */
+ <3 RK_PA2 1 &pcfg_pull_none>,
+ /* gmac1_rxd3 */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* gmac1_txd2 */
+ <3 RK_PA0 1 &pcfg_pull_none>,
+ /* gmac1_txd3 */
+ <3 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_ppsclk: gmac1-ppsclk {
+ rockchip,pins =
+ /* gmac1_ppsclk */
+ <3 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_ppstrig: gmac1-ppstrig {
+ rockchip,pins =
+ /* gmac1_ppstrig */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
+ rockchip,pins =
+ /* gmac1_ptp_ref_clk */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1_txer: gmac1-txer {
+ rockchip,pins =
+ /* gmac1_txer */
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PC5 2 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ /omit-if-no-ref/
+ hdmim0_rx_cec: hdmim0-rx-cec {
+ rockchip,pins =
+ /* hdmim0_rx_cec */
+ <4 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_rx_hpdin: hdmim0-rx-hpdin {
+ rockchip,pins =
+ /* hdmim0_rx_hpdin */
+ <4 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_rx_scl: hdmim0-rx-scl {
+ rockchip,pins =
+ /* hdmim0_rx_scl */
+ <0 RK_PD2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_rx_sda: hdmim0-rx-sda {
+ rockchip,pins =
+ /* hdmim0_rx_sda */
+ <0 RK_PD1 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_cec: hdmim0-tx0-cec {
+ rockchip,pins =
+ /* hdmim0_tx0_cec */
+ <4 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_hpd: hdmim0-tx0-hpd {
+ rockchip,pins =
+ /* hdmim0_tx0_hpd */
+ <1 RK_PA5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_scl: hdmim0-tx0-scl {
+ rockchip,pins =
+ /* hdmim0_tx0_scl */
+ <4 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx0_sda: hdmim0-tx0-sda {
+ rockchip,pins =
+ /* hdmim0_tx0_sda */
+ <4 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim0_tx1_hpd: hdmim0-tx1-hpd {
+ rockchip,pins =
+ /* hdmim0_tx1_hpd */
+ <1 RK_PA6 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ hdmim1_rx_cec: hdmim1-rx-cec {
+ rockchip,pins =
+ /* hdmim1_rx_cec */
+ <3 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_hpdin: hdmim1-rx-hpdin {
+ rockchip,pins =
+ /* hdmim1_rx_hpdin */
+ <3 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_scl: hdmim1-rx-scl {
+ rockchip,pins =
+ /* hdmim1_rx_scl */
+ <3 RK_PD2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_rx_sda: hdmim1-rx-sda {
+ rockchip,pins =
+ /* hdmim1_rx_sda */
+ <3 RK_PD3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_cec: hdmim1-tx0-cec {
+ rockchip,pins =
+ /* hdmim1_tx0_cec */
+ <0 RK_PD1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_hpd: hdmim1-tx0-hpd {
+ rockchip,pins =
+ /* hdmim1_tx0_hpd */
+ <3 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_scl: hdmim1-tx0-scl {
+ rockchip,pins =
+ /* hdmim1_tx0_scl */
+ <0 RK_PD5 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx0_sda: hdmim1-tx0-sda {
+ rockchip,pins =
+ /* hdmim1_tx0_sda */
+ <0 RK_PD4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_cec: hdmim1-tx1-cec {
+ rockchip,pins =
+ /* hdmim1_tx1_cec */
+ <0 RK_PD2 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_hpd: hdmim1-tx1-hpd {
+ rockchip,pins =
+ /* hdmim1_tx1_hpd */
+ <3 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_scl: hdmim1-tx1-scl {
+ rockchip,pins =
+ /* hdmim1_tx1_scl */
+ <3 RK_PC6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim1_tx1_sda: hdmim1-tx1-sda {
+ rockchip,pins =
+ /* hdmim1_tx1_sda */
+ <3 RK_PC5 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ hdmim2_rx_cec: hdmim2-rx-cec {
+ rockchip,pins =
+ /* hdmim2_rx_cec */
+ <1 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_rx_hpdin: hdmim2-rx-hpdin {
+ rockchip,pins =
+ /* hdmim2_rx_hpdin */
+ <1 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_rx_scl: hdmim2-rx-scl {
+ rockchip,pins =
+ /* hdmim2_rx_scl */
+ <1 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_rx_sda: hdmim2-rx-sda {
+ rockchip,pins =
+ /* hdmim2_rx_sda */
+ <1 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx0_scl: hdmim2-tx0-scl {
+ rockchip,pins =
+ /* hdmim2_tx0_scl */
+ <3 RK_PC7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx0_sda: hdmim2-tx0-sda {
+ rockchip,pins =
+ /* hdmim2_tx0_sda */
+ <3 RK_PD0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx1_cec: hdmim2-tx1-cec {
+ rockchip,pins =
+ /* hdmim2_tx1_cec */
+ <3 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx1_scl: hdmim2-tx1-scl {
+ rockchip,pins =
+ /* hdmim2_tx1_scl */
+ <1 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmim2_tx1_sda: hdmim2-tx1-sda {
+ rockchip,pins =
+ /* hdmim2_tx1_sda */
+ <1 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug0: hdmi-debug0 {
+ rockchip,pins =
+ /* hdmi_debug0 */
+ <1 RK_PA7 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug1: hdmi-debug1 {
+ rockchip,pins =
+ /* hdmi_debug1 */
+ <1 RK_PB0 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug2: hdmi-debug2 {
+ rockchip,pins =
+ /* hdmi_debug2 */
+ <1 RK_PB1 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug3: hdmi-debug3 {
+ rockchip,pins =
+ /* hdmi_debug3 */
+ <1 RK_PB2 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug4: hdmi-debug4 {
+ rockchip,pins =
+ /* hdmi_debug4 */
+ <1 RK_PB3 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug5: hdmi-debug5 {
+ rockchip,pins =
+ /* hdmi_debug5 */
+ <1 RK_PB4 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_debug6: hdmi-debug6 {
+ rockchip,pins =
+ /* hdmi_debug6 */
+ <1 RK_PA0 7 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <0 RK_PB3 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <0 RK_PA6 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m2_xfer: i2c0m2-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m2 */
+ <0 RK_PD1 3 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m2 */
+ <0 RK_PD2 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB5 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB6 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <0 RK_PB0 2 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <0 RK_PB1 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m2_xfer: i2c1m2-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m2 */
+ <0 RK_PD4 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m2 */
+ <0 RK_PD5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m3_xfer: i2c1m3-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m3 */
+ <2 RK_PD4 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m3 */
+ <2 RK_PD5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m4_xfer: i2c1m4-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m4 */
+ <1 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m4 */
+ <1 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PB7 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m2_xfer: i2c2m2-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m2 */
+ <2 RK_PA3 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m2 */
+ <2 RK_PA2 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m3_xfer: i2c2m3-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m3 */
+ <1 RK_PC5 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m3 */
+ <1 RK_PC4 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m4_xfer: i2c2m4-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m4 */
+ <1 RK_PA1 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m4 */
+ <1 RK_PA0 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <1 RK_PC1 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <1 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <3 RK_PB7 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <3 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <4 RK_PA4 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m2 */
+ <4 RK_PA5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m4_xfer: i2c3m4-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m4 */
+ <4 RK_PD0 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m4 */
+ <4 RK_PD1 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PA6 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PA5 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m2_xfer: i2c4m2-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m2 */
+ <0 RK_PC5 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m2 */
+ <0 RK_PC4 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m3_xfer: i2c4m3-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m3 */
+ <1 RK_PA3 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m3 */
+ <1 RK_PA2 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m4_xfer: i2c4m4-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m4 */
+ <1 RK_PC7 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m4 */
+ <1 RK_PC6 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <3 RK_PC7 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <3 RK_PD0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <4 RK_PB6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <4 RK_PB7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <4 RK_PA6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m2 */
+ <4 RK_PA7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m3_xfer: i2c5m3-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m3 */
+ <1 RK_PB6 9 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m3 */
+ <1 RK_PB7 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m0_xfer: i2c6m0-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <0 RK_PD0 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m0 */
+ <0 RK_PC7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m1_xfer: i2c6m1-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m1 */
+ <1 RK_PC3 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m1 */
+ <1 RK_PC2 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m3_xfer: i2c6m3-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m3 */
+ <4 RK_PB1 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m3 */
+ <4 RK_PB0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m4_xfer: i2c6m4-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m4 */
+ <3 RK_PA1 9 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m4 */
+ <3 RK_PA0 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7m0_xfer: i2c7m0-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m0 */
+ <1 RK_PD0 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m0 */
+ <1 RK_PD1 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m2_xfer: i2c7m2-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m2 */
+ <3 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m2 */
+ <3 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m3_xfer: i2c7m3-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m3 */
+ <4 RK_PB2 9 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m3 */
+ <4 RK_PB3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c8 {
+ /omit-if-no-ref/
+ i2c8m0_xfer: i2c8m0-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m0 */
+ <4 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m0 */
+ <4 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m2_xfer: i2c8m2-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m2 */
+ <1 RK_PD6 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m2 */
+ <1 RK_PD7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m3_xfer: i2c8m3-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m3 */
+ <4 RK_PC0 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m3 */
+ <4 RK_PC1 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m4_xfer: i2c8m4-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m4 */
+ <3 RK_PC2 9 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m4 */
+ <3 RK_PC3 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ /omit-if-no-ref/
+ i2s0_lrck: i2s0-lrck {
+ rockchip,pins =
+ /* i2s0_lrck */
+ <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_mclk: i2s0-mclk {
+ rockchip,pins =
+ /* i2s0_mclk */
+ <1 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sclk: i2s0-sclk {
+ rockchip,pins =
+ /* i2s0_sclk */
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi0: i2s0-sdi0 {
+ rockchip,pins =
+ /* i2s0_sdi0 */
+ <1 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi1: i2s0-sdi1 {
+ rockchip,pins =
+ /* i2s0_sdi1 */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi2: i2s0-sdi2 {
+ rockchip,pins =
+ /* i2s0_sdi2 */
+ <1 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdi3: i2s0-sdi3 {
+ rockchip,pins =
+ /* i2s0_sdi3 */
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo0: i2s0-sdo0 {
+ rockchip,pins =
+ /* i2s0_sdo0 */
+ <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo1: i2s0-sdo1 {
+ rockchip,pins =
+ /* i2s0_sdo1 */
+ <1 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo2: i2s0-sdo2 {
+ rockchip,pins =
+ /* i2s0_sdo2 */
+ <1 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0_sdo3: i2s0-sdo3 {
+ rockchip,pins =
+ /* i2s0_sdo3 */
+ <1 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1m0_lrck: i2s1m0-lrck {
+ rockchip,pins =
+ /* i2s1m0_lrck */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_mclk: i2s1m0-mclk {
+ rockchip,pins =
+ /* i2s1m0_mclk */
+ <4 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclk: i2s1m0-sclk {
+ rockchip,pins =
+ /* i2s1m0_sclk */
+ <4 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi0: i2s1m0-sdi0 {
+ rockchip,pins =
+ /* i2s1m0_sdi0 */
+ <4 RK_PA5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi1: i2s1m0-sdi1 {
+ rockchip,pins =
+ /* i2s1m0_sdi1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi2: i2s1m0-sdi2 {
+ rockchip,pins =
+ /* i2s1m0_sdi2 */
+ <4 RK_PA7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi3: i2s1m0-sdi3 {
+ rockchip,pins =
+ /* i2s1m0_sdi3 */
+ <4 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo0: i2s1m0-sdo0 {
+ rockchip,pins =
+ /* i2s1m0_sdo0 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo1: i2s1m0-sdo1 {
+ rockchip,pins =
+ /* i2s1m0_sdo1 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo2: i2s1m0-sdo2 {
+ rockchip,pins =
+ /* i2s1m0_sdo2 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo3: i2s1m0-sdo3 {
+ rockchip,pins =
+ /* i2s1m0_sdo3 */
+ <4 RK_PB4 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ i2s1m1_lrck: i2s1m1-lrck {
+ rockchip,pins =
+ /* i2s1m1_lrck */
+ <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_mclk: i2s1m1-mclk {
+ rockchip,pins =
+ /* i2s1m1_mclk */
+ <0 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclk: i2s1m1-sclk {
+ rockchip,pins =
+ /* i2s1m1_sclk */
+ <0 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi0: i2s1m1-sdi0 {
+ rockchip,pins =
+ /* i2s1m1_sdi0 */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi1: i2s1m1-sdi1 {
+ rockchip,pins =
+ /* i2s1m1_sdi1 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi2: i2s1m1-sdi2 {
+ rockchip,pins =
+ /* i2s1m1_sdi2 */
+ <0 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi3: i2s1m1-sdi3 {
+ rockchip,pins =
+ /* i2s1m1_sdi3 */
+ <0 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo0: i2s1m1-sdo0 {
+ rockchip,pins =
+ /* i2s1m1_sdo0 */
+ <0 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo1: i2s1m1-sdo1 {
+ rockchip,pins =
+ /* i2s1m1_sdo1 */
+ <0 RK_PD2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo2: i2s1m1-sdo2 {
+ rockchip,pins =
+ /* i2s1m1_sdo2 */
+ <0 RK_PD4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo3: i2s1m1-sdo3 {
+ rockchip,pins =
+ /* i2s1m1_sdo3 */
+ <0 RK_PD5 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m1_lrck: i2s2m1-lrck {
+ rockchip,pins =
+ /* i2s2m1_lrck */
+ <3 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ /* i2s2m1_mclk */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclk: i2s2m1-sclk {
+ rockchip,pins =
+ /* i2s2m1_sclk */
+ <3 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ /* i2s2m1_sdi */
+ <3 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ /* i2s2m1_sdo */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2s3 {
+ /omit-if-no-ref/
+ i2s3_lrck: i2s3-lrck {
+ rockchip,pins =
+ /* i2s3_lrck */
+ <3 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_mclk: i2s3-mclk {
+ rockchip,pins =
+ /* i2s3_mclk */
+ <3 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_sclk: i2s3-sclk {
+ rockchip,pins =
+ /* i2s3_sclk */
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_sdi: i2s3-sdi {
+ rockchip,pins =
+ /* i2s3_sdi */
+ <3 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3_sdo: i2s3-sdo {
+ rockchip,pins =
+ /* i2s3_sdo */
+ <3 RK_PA3 3 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_tck_m0 */
+ <4 RK_PD2 5 &pcfg_pull_none>,
+ /* jtag_tms_m0 */
+ <4 RK_PD3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_tck_m1 */
+ <4 RK_PD0 5 &pcfg_pull_none>,
+ /* jtag_tms_m1 */
+ <4 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm2_pins: jtagm2-pins {
+ rockchip,pins =
+ /* jtag_tck_m2 */
+ <0 RK_PB5 2 &pcfg_pull_none>,
+ /* jtag_tms_m2 */
+ <0 RK_PB6 2 &pcfg_pull_none>;
+ };
+ };
+
+ litcpu {
+ /omit-if-no-ref/
+ litcpu_pins: litcpu-pins {
+ rockchip,pins =
+ /* litcpu_avs */
+ <0 RK_PD3 1 &pcfg_pull_none>;
+ };
+ };
+
+ mcu {
+ /omit-if-no-ref/
+ mcum0_pins: mcum0-pins {
+ rockchip,pins =
+ /* mcu_jtag_tck_m0 */
+ <4 RK_PD4 5 &pcfg_pull_none>,
+ /* mcu_jtag_tms_m0 */
+ <4 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mcum1_pins: mcum1-pins {
+ rockchip,pins =
+ /* mcu_jtag_tck_m1 */
+ <3 RK_PD4 6 &pcfg_pull_none>,
+ /* mcu_jtag_tms_m1 */
+ <3 RK_PD5 6 &pcfg_pull_none>;
+ };
+ };
+
+ mipi {
+ /omit-if-no-ref/
+ mipim0_camera0_clk: mipim0-camera0-clk {
+ rockchip,pins =
+ /* mipim0_camera0_clk */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera1_clk: mipim0-camera1-clk {
+ rockchip,pins =
+ /* mipim0_camera1_clk */
+ <1 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera2_clk: mipim0-camera2-clk {
+ rockchip,pins =
+ /* mipim0_camera2_clk */
+ <1 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera3_clk: mipim0-camera3-clk {
+ rockchip,pins =
+ /* mipim0_camera3_clk */
+ <1 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim0_camera4_clk: mipim0-camera4-clk {
+ rockchip,pins =
+ /* mipim0_camera4_clk */
+ <1 RK_PD7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera0_clk: mipim1-camera0-clk {
+ rockchip,pins =
+ /* mipim1_camera0_clk */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera1_clk: mipim1-camera1-clk {
+ rockchip,pins =
+ /* mipim1_camera1_clk */
+ <3 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera2_clk: mipim1-camera2-clk {
+ rockchip,pins =
+ /* mipim1_camera2_clk */
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera3_clk: mipim1-camera3-clk {
+ rockchip,pins =
+ /* mipim1_camera3_clk */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_camera4_clk: mipim1-camera4-clk {
+ rockchip,pins =
+ /* mipim1_camera4_clk */
+ <3 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipi_te0: mipi-te0 {
+ rockchip,pins =
+ /* mipi_te0 */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipi_te1: mipi-te1 {
+ rockchip,pins =
+ /* mipi_te1 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PC6 2 &pcfg_pull_none>;
+ };
+ };
+
+ pcie20x1 {
+ /omit-if-no-ref/
+ pcie20x1m0_pins: pcie20x1m0-pins {
+ rockchip,pins =
+ /* pcie20x1_2_clkreqn_m0 */
+ <3 RK_PC7 4 &pcfg_pull_none>,
+ /* pcie20x1_2_perstn_m0 */
+ <3 RK_PD1 4 &pcfg_pull_none>,
+ /* pcie20x1_2_waken_m0 */
+ <3 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1m1_pins: pcie20x1m1-pins {
+ rockchip,pins =
+ /* pcie20x1_2_clkreqn_m1 */
+ <4 RK_PB7 4 &pcfg_pull_none>,
+ /* pcie20x1_2_perstn_m1 */
+ <4 RK_PC1 4 &pcfg_pull_none>,
+ /* pcie20x1_2_waken_m1 */
+ <4 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
+ rockchip,pins =
+ /* pcie20x1_2_button_rstn */
+ <4 RK_PB3 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30phy {
+ /omit-if-no-ref/
+ pcie30phy_pins: pcie30phy-pins {
+ rockchip,pins =
+ /* pcie30phy_dtb0 */
+ <1 RK_PC4 4 &pcfg_pull_none>,
+ /* pcie30phy_dtb1 */
+ <1 RK_PD1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x1 {
+ /omit-if-no-ref/
+ pcie30x1m0_pins: pcie30x1m0-pins {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m0 */
+ <0 RK_PC0 12 &pcfg_pull_none>,
+ /* pcie30x1_0_perstn_m0 */
+ <0 RK_PC5 12 &pcfg_pull_none>,
+ /* pcie30x1_0_waken_m0 */
+ <0 RK_PC4 12 &pcfg_pull_none>,
+ /* pcie30x1_1_clkreqn_m0 */
+ <0 RK_PB5 12 &pcfg_pull_none>,
+ /* pcie30x1_1_perstn_m0 */
+ <0 RK_PB7 12 &pcfg_pull_none>,
+ /* pcie30x1_1_waken_m0 */
+ <0 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_pins: pcie30x1m1-pins {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m1 */
+ <4 RK_PA3 4 &pcfg_pull_none>,
+ /* pcie30x1_0_perstn_m1 */
+ <4 RK_PA5 4 &pcfg_pull_none>,
+ /* pcie30x1_0_waken_m1 */
+ <4 RK_PA4 4 &pcfg_pull_none>,
+ /* pcie30x1_1_clkreqn_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie30x1_1_perstn_m1 */
+ <4 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie30x1_1_waken_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_pins: pcie30x1m2-pins {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m2 */
+ <1 RK_PB5 4 &pcfg_pull_none>,
+ /* pcie30x1_0_perstn_m2 */
+ <1 RK_PB4 4 &pcfg_pull_none>,
+ /* pcie30x1_0_waken_m2 */
+ <1 RK_PB3 4 &pcfg_pull_none>,
+ /* pcie30x1_1_clkreqn_m2 */
+ <1 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie30x1_1_perstn_m2 */
+ <1 RK_PA7 4 &pcfg_pull_none>,
+ /* pcie30x1_1_waken_m2 */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
+ rockchip,pins =
+ /* pcie30x1_0_button_rstn */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
+ rockchip,pins =
+ /* pcie30x1_1_button_rstn */
+ <4 RK_PB2 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x2 {
+ /omit-if-no-ref/
+ pcie30x2m0_pins: pcie30x2m0-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m0 */
+ <0 RK_PD1 12 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m0 */
+ <0 RK_PD4 12 &pcfg_pull_none>,
+ /* pcie30x2_waken_m0 */
+ <0 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_pins: pcie30x2m1-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m1 */
+ <4 RK_PA6 4 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m1 */
+ <4 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie30x2_waken_m1 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_pins: pcie30x2m2-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m2 */
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m2 */
+ <3 RK_PD4 4 &pcfg_pull_none>,
+ /* pcie30x2_waken_m2 */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m3_pins: pcie30x2m3-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m3 */
+ <1 RK_PD7 4 &pcfg_pull_none>,
+ /* pcie30x2_perstn_m3 */
+ <1 RK_PB7 4 &pcfg_pull_none>,
+ /* pcie30x2_waken_m3 */
+ <1 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2_button_rstn: pcie30x2-button-rstn {
+ rockchip,pins =
+ /* pcie30x2_button_rstn */
+ <3 RK_PC1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x4 {
+ /omit-if-no-ref/
+ pcie30x4m0_pins: pcie30x4m0-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m0 */
+ <0 RK_PC6 12 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m0 */
+ <0 RK_PD0 12 &pcfg_pull_none>,
+ /* pcie30x4_waken_m0 */
+ <0 RK_PC7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m1_pins: pcie30x4m1-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m1 */
+ <4 RK_PB4 4 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m1 */
+ <4 RK_PB6 4 &pcfg_pull_none>,
+ /* pcie30x4_waken_m1 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m2_pins: pcie30x4m2-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m2 */
+ <3 RK_PC4 4 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m2 */
+ <3 RK_PC6 4 &pcfg_pull_none>,
+ /* pcie30x4_waken_m2 */
+ <3 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4m3_pins: pcie30x4m3-pins {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m3 */
+ <1 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie30x4_perstn_m3 */
+ <1 RK_PB2 4 &pcfg_pull_none>,
+ /* pcie30x4_waken_m3 */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x4_button_rstn: pcie30x4-button-rstn {
+ rockchip,pins =
+ /* pcie30x4_button_rstn */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pdm0 {
+ /omit-if-no-ref/
+ pdm0m0_clk: pdm0m0-clk {
+ rockchip,pins =
+ /* pdm0_clk0_m0 */
+ <1 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_clk1: pdm0m0-clk1 {
+ rockchip,pins =
+ /* pdm0m0_clk1 */
+ <1 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi0: pdm0m0-sdi0 {
+ rockchip,pins =
+ /* pdm0m0_sdi0 */
+ <1 RK_PD5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi1: pdm0m0-sdi1 {
+ rockchip,pins =
+ /* pdm0m0_sdi1 */
+ <1 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi2: pdm0m0-sdi2 {
+ rockchip,pins =
+ /* pdm0m0_sdi2 */
+ <1 RK_PD2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi3: pdm0m0-sdi3 {
+ rockchip,pins =
+ /* pdm0m0_sdi3 */
+ <1 RK_PD3 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ pdm0m1_clk: pdm0m1-clk {
+ rockchip,pins =
+ /* pdm0_clk0_m1 */
+ <0 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_clk1: pdm0m1-clk1 {
+ rockchip,pins =
+ /* pdm0m1_clk1 */
+ <0 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi0: pdm0m1-sdi0 {
+ rockchip,pins =
+ /* pdm0m1_sdi0 */
+ <0 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi1: pdm0m1-sdi1 {
+ rockchip,pins =
+ /* pdm0m1_sdi1 */
+ <0 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi2: pdm0m1-sdi2 {
+ rockchip,pins =
+ /* pdm0m1_sdi2 */
+ <0 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi3: pdm0m1-sdi3 {
+ rockchip,pins =
+ /* pdm0m1_sdi3 */
+ <0 RK_PD6 2 &pcfg_pull_none>;
+ };
+ };
+
+ pdm1 {
+ /omit-if-no-ref/
+ pdm1m0_clk: pdm1m0-clk {
+ rockchip,pins =
+ /* pdm1_clk0_m0 */
+ <4 RK_PD5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_clk1: pdm1m0-clk1 {
+ rockchip,pins =
+ /* pdm1m0_clk1 */
+ <4 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi0: pdm1m0-sdi0 {
+ rockchip,pins =
+ /* pdm1m0_sdi0 */
+ <4 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi1: pdm1m0-sdi1 {
+ rockchip,pins =
+ /* pdm1m0_sdi1 */
+ <4 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi2: pdm1m0-sdi2 {
+ rockchip,pins =
+ /* pdm1m0_sdi2 */
+ <4 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi3: pdm1m0-sdi3 {
+ rockchip,pins =
+ /* pdm1m0_sdi3 */
+ <4 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ pdm1m1_clk: pdm1m1-clk {
+ rockchip,pins =
+ /* pdm1_clk0_m1 */
+ <1 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_clk1: pdm1m1-clk1 {
+ rockchip,pins =
+ /* pdm1m1_clk1 */
+ <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi0: pdm1m1-sdi0 {
+ rockchip,pins =
+ /* pdm1m1_sdi0 */
+ <1 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi1: pdm1m1-sdi1 {
+ rockchip,pins =
+ /* pdm1m1_sdi1 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi2: pdm1m1-sdi2 {
+ rockchip,pins =
+ /* pdm1m1_sdi2 */
+ <1 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi3: pdm1m1-sdi3 {
+ rockchip,pins =
+ /* pdm1m1_sdi3 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ /omit-if-no-ref/
+ pmic_pins: pmic-pins {
+ rockchip,pins =
+ /* pmic_int_l */
+ <0 RK_PA7 0 &pcfg_pull_up>,
+ /* pmic_sleep1 */
+ <0 RK_PA2 1 &pcfg_pull_none>,
+ /* pmic_sleep2 */
+ <0 RK_PA3 1 &pcfg_pull_none>,
+ /* pmic_sleep3 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* pmic_sleep4 */
+ <0 RK_PC2 1 &pcfg_pull_none>,
+ /* pmic_sleep5 */
+ <0 RK_PC3 1 &pcfg_pull_none>,
+ /* pmic_sleep6 */
+ <0 RK_PD6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <0 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <0 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PD2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_pins: pwm0m2-pins {
+ rockchip,pins =
+ /* pwm0_m2 */
+ <1 RK_PA2 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <0 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PD3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_pins: pwm1m2-pins {
+ rockchip,pins =
+ /* pwm1_m2 */
+ <1 RK_PA3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <0 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <3 RK_PB1 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_ir_m0 */
+ <0 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_ir_m1 */
+ <3 RK_PB2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m2_pins: pwm3m2-pins {
+ rockchip,pins =
+ /* pwm3_ir_m2 */
+ <1 RK_PC2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m3_pins: pwm3m3-pins {
+ rockchip,pins =
+ /* pwm3_ir_m3 */
+ <1 RK_PA7 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <0 RK_PC5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <0 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <0 RK_PC6 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <0 RK_PC7 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <4 RK_PC1 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_ir_m0 */
+ <0 RK_PD0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_ir_m1 */
+ <4 RK_PD4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m2_pins: pwm7m2-pins {
+ rockchip,pins =
+ /* pwm7_ir_m2 */
+ <1 RK_PC3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm8 {
+ /omit-if-no-ref/
+ pwm8m0_pins: pwm8m0-pins {
+ rockchip,pins =
+ /* pwm8_m0 */
+ <3 RK_PA7 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m1_pins: pwm8m1-pins {
+ rockchip,pins =
+ /* pwm8_m1 */
+ <4 RK_PD0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m2_pins: pwm8m2-pins {
+ rockchip,pins =
+ /* pwm8_m2 */
+ <3 RK_PD0 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm9 {
+ /omit-if-no-ref/
+ pwm9m0_pins: pwm9m0-pins {
+ rockchip,pins =
+ /* pwm9_m0 */
+ <3 RK_PB0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m1_pins: pwm9m1-pins {
+ rockchip,pins =
+ /* pwm9_m1 */
+ <4 RK_PD1 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m2_pins: pwm9m2-pins {
+ rockchip,pins =
+ /* pwm9_m2 */
+ <3 RK_PD1 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm10 {
+ /omit-if-no-ref/
+ pwm10m0_pins: pwm10m0-pins {
+ rockchip,pins =
+ /* pwm10_m0 */
+ <3 RK_PA0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m1_pins: pwm10m1-pins {
+ rockchip,pins =
+ /* pwm10_m1 */
+ <4 RK_PD3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m2_pins: pwm10m2-pins {
+ rockchip,pins =
+ /* pwm10_m2 */
+ <3 RK_PD3 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm11 {
+ /omit-if-no-ref/
+ pwm11m0_pins: pwm11m0-pins {
+ rockchip,pins =
+ /* pwm11_ir_m0 */
+ <3 RK_PA1 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m1_pins: pwm11m1-pins {
+ rockchip,pins =
+ /* pwm11_ir_m1 */
+ <4 RK_PB4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m2_pins: pwm11m2-pins {
+ rockchip,pins =
+ /* pwm11_ir_m2 */
+ <1 RK_PC4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m3_pins: pwm11m3-pins {
+ rockchip,pins =
+ /* pwm11_ir_m3 */
+ <3 RK_PD5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm12 {
+ /omit-if-no-ref/
+ pwm12m0_pins: pwm12m0-pins {
+ rockchip,pins =
+ /* pwm12_m0 */
+ <3 RK_PB5 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm12m1_pins: pwm12m1-pins {
+ rockchip,pins =
+ /* pwm12_m1 */
+ <4 RK_PB5 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm13 {
+ /omit-if-no-ref/
+ pwm13m0_pins: pwm13m0-pins {
+ rockchip,pins =
+ /* pwm13_m0 */
+ <3 RK_PB6 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m1_pins: pwm13m1-pins {
+ rockchip,pins =
+ /* pwm13_m1 */
+ <4 RK_PB6 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m2_pins: pwm13m2-pins {
+ rockchip,pins =
+ /* pwm13_m2 */
+ <1 RK_PB7 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm14 {
+ /omit-if-no-ref/
+ pwm14m0_pins: pwm14m0-pins {
+ rockchip,pins =
+ /* pwm14_m0 */
+ <3 RK_PC2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m1_pins: pwm14m1-pins {
+ rockchip,pins =
+ /* pwm14_m1 */
+ <4 RK_PB2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m2_pins: pwm14m2-pins {
+ rockchip,pins =
+ /* pwm14_m2 */
+ <1 RK_PD6 11 &pcfg_pull_none>;
+ };
+ };
+
+ pwm15 {
+ /omit-if-no-ref/
+ pwm15m0_pins: pwm15m0-pins {
+ rockchip,pins =
+ /* pwm15_ir_m0 */
+ <3 RK_PC3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m1_pins: pwm15m1-pins {
+ rockchip,pins =
+ /* pwm15_ir_m1 */
+ <4 RK_PB3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m2_pins: pwm15m2-pins {
+ rockchip,pins =
+ /* pwm15_ir_m2 */
+ <1 RK_PC6 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m3_pins: pwm15m3-pins {
+ rockchip,pins =
+ /* pwm15_ir_m3 */
+ <1 RK_PD7 11 &pcfg_pull_none>;
+ };
+ };
+
+ refclk {
+ /omit-if-no-ref/
+ refclk_pins: refclk-pins {
+ rockchip,pins =
+ /* refclk_out */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ sata {
+ /omit-if-no-ref/
+ sata_pins: sata-pins {
+ rockchip,pins =
+ /* sata_cp_pod */
+ <0 RK_PC6 13 &pcfg_pull_none>,
+ /* sata_cpdet */
+ <0 RK_PD4 13 &pcfg_pull_none>,
+ /* sata_mp_switch */
+ <0 RK_PD5 13 &pcfg_pull_none>;
+ };
+ };
+
+ sata0 {
+ /omit-if-no-ref/
+ sata0m0_pins: sata0m0-pins {
+ rockchip,pins =
+ /* sata0_act_led_m0 */
+ <4 RK_PB6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata0m1_pins: sata0m1-pins {
+ rockchip,pins =
+ /* sata0_act_led_m1 */
+ <1 RK_PB3 6 &pcfg_pull_none>;
+ };
+ };
+
+ sata1 {
+ /omit-if-no-ref/
+ sata1m0_pins: sata1m0-pins {
+ rockchip,pins =
+ /* sata1_act_led_m0 */
+ <4 RK_PB5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata1m1_pins: sata1m1-pins {
+ rockchip,pins =
+ /* sata1_act_led_m1 */
+ <1 RK_PA1 6 &pcfg_pull_none>;
+ };
+ };
+
+ sata2 {
+ /omit-if-no-ref/
+ sata2m0_pins: sata2m0-pins {
+ rockchip,pins =
+ /* sata2_act_led_m0 */
+ <4 RK_PB1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata2m1_pins: sata2m1-pins {
+ rockchip,pins =
+ /* sata2_act_led_m1 */
+ <1 RK_PB7 6 &pcfg_pull_none>;
+ };
+ };
+
+ sdio {
+ /omit-if-no-ref/
+ sdiom1_pins: sdiom1-pins {
+ rockchip,pins =
+ /* sdio_clk_m1 */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* sdio_cmd_m1 */
+ <3 RK_PA4 2 &pcfg_pull_none>,
+ /* sdio_d0_m1 */
+ <3 RK_PA0 2 &pcfg_pull_none>,
+ /* sdio_d1_m1 */
+ <3 RK_PA1 2 &pcfg_pull_none>,
+ /* sdio_d2_m1 */
+ <3 RK_PA2 2 &pcfg_pull_none>,
+ /* sdio_d3_m1 */
+ <3 RK_PA3 2 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ /omit-if-no-ref/
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ /* sdmmc_d0 */
+ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d1 */
+ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d2 */
+ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d3 */
+ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ /* sdmmc_clk */
+ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ /* sdmmc_cmd */
+ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_det: sdmmc-det {
+ rockchip,pins =
+ /* sdmmc_det */
+ <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ /* sdmmc_pwren */
+ <0 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif0 {
+ /omit-if-no-ref/
+ spdif0m0_tx: spdif0m0-tx {
+ rockchip,pins =
+ /* spdif0m0_tx */
+ <1 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdif0m1_tx: spdif0m1-tx {
+ rockchip,pins =
+ /* spdif0m1_tx */
+ <4 RK_PB4 6 &pcfg_pull_none>;
+ };
+ };
+
+ spdif1 {
+ /omit-if-no-ref/
+ spdif1m0_tx: spdif1m0-tx {
+ rockchip,pins =
+ /* spdif1m0_tx */
+ <1 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdif1m1_tx: spdif1m1-tx {
+ rockchip,pins =
+ /* spdif1m1_tx */
+ <4 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdif1m2_tx: spdif1m2-tx {
+ rockchip,pins =
+ /* spdif1m2_tx */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_miso_m0 */
+ <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosi_m0 */
+ <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m0 */
+ <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m0 */
+ <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
+ };
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clk_m1 */
+ <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_miso_m1 */
+ <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosi_m1 */
+ <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m1 */
+ <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs1: spi0m1-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m1 */
+ <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
+ };
+ /omit-if-no-ref/
+ spi0m2_pins: spi0m2-pins {
+ rockchip,pins =
+ /* spi0_clk_m2 */
+ <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_miso_m2 */
+ <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosi_m2 */
+ <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_cs0: spi0m2-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m2 */
+ <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_cs1: spi0m2-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m2 */
+ <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
+ };
+ /omit-if-no-ref/
+ spi0m3_pins: spi0m3-pins {
+ rockchip,pins =
+ /* spi0_clk_m3 */
+ <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_miso_m3 */
+ <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosi_m3 */
+ <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m3_cs0: spi0m3-cs0 {
+ rockchip,pins =
+ /* spi0_cs0_m3 */
+ <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m3_cs1: spi0m3-cs1 {
+ rockchip,pins =
+ /* spi0_cs1_m3 */
+ <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clk_m1 */
+ <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_miso_m1 */
+ <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosi_m1 */
+ <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs0: spi1m1-cs0 {
+ rockchip,pins =
+ /* spi1_cs0_m1 */
+ <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs1: spi1m1-cs1 {
+ rockchip,pins =
+ /* spi1_cs1_m1 */
+ <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_pins: spi1m2-pins {
+ rockchip,pins =
+ /* spi1_clk_m2 */
+ <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_miso_m2 */
+ <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosi_m2 */
+ <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_cs0: spi1m2-cs0 {
+ rockchip,pins =
+ /* spi1_cs0_m2 */
+ <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_cs1: spi1m2-cs1 {
+ rockchip,pins =
+ /* spi1_cs1_m2 */
+ <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clk_m0 */
+ <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
+ /* spi2_miso_m0 */
+ <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosi_m0 */
+ <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs0: spi2m0-cs0 {
+ rockchip,pins =
+ /* spi2_cs0_m0 */
+ <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs1: spi2m0-cs1 {
+ rockchip,pins =
+ /* spi2_cs1_m0 */
+ <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clk_m1 */
+ <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
+ /* spi2_miso_m1 */
+ <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosi_m1 */
+ <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs0: spi2m1-cs0 {
+ rockchip,pins =
+ /* spi2_cs0_m1 */
+ <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs1: spi2m1-cs1 {
+ rockchip,pins =
+ /* spi2_cs1_m1 */
+ <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_pins: spi2m2-pins {
+ rockchip,pins =
+ /* spi2_clk_m2 */
+ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
+ /* spi2_miso_m2 */
+ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosi_m2 */
+ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_cs0: spi2m2-cs0 {
+ rockchip,pins =
+ /* spi2_cs0_m2 */
+ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_cs1: spi2m2-cs1 {
+ rockchip,pins =
+ /* spi2_cs1_m2 */
+ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m1_pins: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clk_m1 */
+ <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_miso_m1 */
+ <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosi_m1 */
+ <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs0: spi3m1-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m1 */
+ <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs1: spi3m1-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m1 */
+ <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_pins: spi3m2-pins {
+ rockchip,pins =
+ /* spi3_clk_m2 */
+ <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_miso_m2 */
+ <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosi_m2 */
+ <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_cs0: spi3m2-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m2 */
+ <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_cs1: spi3m2-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m2 */
+ <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m3_pins: spi3m3-pins {
+ rockchip,pins =
+ /* spi3_clk_m3 */
+ <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_miso_m3 */
+ <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosi_m3 */
+ <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m3_cs0: spi3m3-cs0 {
+ rockchip,pins =
+ /* spi3_cs0_m3 */
+ <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m3_cs1: spi3m3-cs1 {
+ rockchip,pins =
+ /* spi3_cs1_m3 */
+ <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi4 {
+ /omit-if-no-ref/
+ spi4m0_pins: spi4m0-pins {
+ rockchip,pins =
+ /* spi4_clk_m0 */
+ <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
+ /* spi4_miso_m0 */
+ <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi4_mosi_m0 */
+ <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_cs0: spi4m0-cs0 {
+ rockchip,pins =
+ /* spi4_cs0_m0 */
+ <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_cs1: spi4m0-cs1 {
+ rockchip,pins =
+ /* spi4_cs1_m0 */
+ <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_pins: spi4m1-pins {
+ rockchip,pins =
+ /* spi4_clk_m1 */
+ <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
+ /* spi4_miso_m1 */
+ <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi4_mosi_m1 */
+ <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_cs0: spi4m1-cs0 {
+ rockchip,pins =
+ /* spi4_cs0_m1 */
+ <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_cs1: spi4m1-cs1 {
+ rockchip,pins =
+ /* spi4_cs1_m1 */
+ <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_pins: spi4m2-pins {
+ rockchip,pins =
+ /* spi4_clk_m2 */
+ <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
+ /* spi4_miso_m2 */
+ <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
+ /* spi4_mosi_m2 */
+ <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_cs0: spi4m2-cs0 {
+ rockchip,pins =
+ /* spi4_cs0_m2 */
+ <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm1_shut: tsadcm1-shut {
+ rockchip,pins =
+ /* tsadcm1_shut */
+ <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shut: tsadc-shut {
+ rockchip,pins =
+ /* tsadc_shut */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shut_org: tsadc-shut-org {
+ rockchip,pins =
+ /* tsadc_shut_org */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PC4 4 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PC5 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <0 RK_PB0 4 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <0 RK_PB1 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m2_xfer: uart0m2-xfer {
+ rockchip,pins =
+ /* uart0_rx_m2 */
+ <4 RK_PA4 10 &pcfg_pull_up>,
+ /* uart0_tx_m2 */
+ <4 RK_PA3 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ /* uart0_ctsn */
+ <0 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ /* uart0_rtsn */
+ <0 RK_PC6 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <1 RK_PB7 10 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <1 RK_PB6 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <1 RK_PD7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <1 RK_PD6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_xfer: uart1m2-xfer {
+ rockchip,pins =
+ /* uart1_rx_m2 */
+ <0 RK_PD2 10 &pcfg_pull_up>,
+ /* uart1_tx_m2 */
+ <0 RK_PD1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_ctsn: uart1m2-ctsn {
+ rockchip,pins =
+ /* uart1m2_ctsn */
+ <0 RK_PD0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_rtsn: uart1m2-rtsn {
+ rockchip,pins =
+ /* uart1m2_rtsn */
+ <0 RK_PC7 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PB6 10 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <4 RK_PD1 10 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <4 RK_PD0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_xfer: uart2m2-xfer {
+ rockchip,pins =
+ /* uart2_rx_m2 */
+ <3 RK_PB2 10 &pcfg_pull_up>,
+ /* uart2_tx_m2 */
+ <3 RK_PB1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2_ctsn: uart2-ctsn {
+ rockchip,pins =
+ /* uart2_ctsn */
+ <3 RK_PB4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2_rtsn: uart2-rtsn {
+ rockchip,pins =
+ /* uart2_rtsn */
+ <3 RK_PB3 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <1 RK_PC0 10 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <1 RK_PC1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <3 RK_PB6 10 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <3 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_xfer: uart3m2-xfer {
+ rockchip,pins =
+ /* uart3_rx_m2 */
+ <4 RK_PA6 10 &pcfg_pull_up>,
+ /* uart3_tx_m2 */
+ <4 RK_PA5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3_ctsn: uart3-ctsn {
+ rockchip,pins =
+ /* uart3_ctsn */
+ <1 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3_rtsn: uart3-rtsn {
+ rockchip,pins =
+ /* uart3_rtsn */
+ <1 RK_PC2 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <1 RK_PD3 10 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <1 RK_PD2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rx_m1 */
+ <3 RK_PD0 10 &pcfg_pull_up>,
+ /* uart4_tx_m1 */
+ <3 RK_PD1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m2_xfer: uart4m2-xfer {
+ rockchip,pins =
+ /* uart4_rx_m2 */
+ <1 RK_PB2 10 &pcfg_pull_up>,
+ /* uart4_tx_m2 */
+ <1 RK_PB3 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4_ctsn: uart4-ctsn {
+ rockchip,pins =
+ /* uart4_ctsn */
+ <1 RK_PC7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4_rtsn: uart4-rtsn {
+ rockchip,pins =
+ /* uart4_rtsn */
+ <1 RK_PC5 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <4 RK_PD4 10 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <4 RK_PD5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <4 RK_PD2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <4 RK_PD3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <3 RK_PC5 10 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <3 RK_PC4 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <2 RK_PA2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <2 RK_PA3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_xfer: uart5m2-xfer {
+ rockchip,pins =
+ /* uart5_rx_m2 */
+ <2 RK_PD4 10 &pcfg_pull_up>,
+ /* uart5_tx_m2 */
+ <2 RK_PD5 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <1 RK_PA0 10 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <1 RK_PA1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_ctsn: uart6m1-ctsn {
+ rockchip,pins =
+ /* uart6m1_ctsn */
+ <1 RK_PA3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_rtsn: uart6m1-rtsn {
+ rockchip,pins =
+ /* uart6m1_rtsn */
+ <1 RK_PA2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_xfer: uart6m2-xfer {
+ rockchip,pins =
+ /* uart6_rx_m2 */
+ <1 RK_PD1 10 &pcfg_pull_up>,
+ /* uart6_tx_m2 */
+ <1 RK_PD0 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <3 RK_PC1 10 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <3 RK_PC0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_ctsn: uart7m1-ctsn {
+ rockchip,pins =
+ /* uart7m1_ctsn */
+ <3 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_rtsn: uart7m1-rtsn {
+ rockchip,pins =
+ /* uart7m1_rtsn */
+ <3 RK_PC2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m2_xfer: uart7m2-xfer {
+ rockchip,pins =
+ /* uart7_rx_m2 */
+ <1 RK_PB4 10 &pcfg_pull_up>,
+ /* uart7_tx_m2 */
+ <1 RK_PB5 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rx_m0 */
+ <4 RK_PB1 10 &pcfg_pull_up>,
+ /* uart8_tx_m0 */
+ <4 RK_PB0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <4 RK_PB3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <4 RK_PB2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rx_m1 */
+ <3 RK_PA3 10 &pcfg_pull_up>,
+ /* uart8_tx_m1 */
+ <3 RK_PA2 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_ctsn: uart8m1-ctsn {
+ rockchip,pins =
+ /* uart8m1_ctsn */
+ <3 RK_PA5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_rtsn: uart8m1-rtsn {
+ rockchip,pins =
+ /* uart8m1_rtsn */
+ <3 RK_PA4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8_xfer: uart8-xfer {
+ rockchip,pins =
+ /* uart8_rx_ */
+ <4 RK_PB1 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rx_m1 */
+ <4 RK_PB5 10 &pcfg_pull_up>,
+ /* uart9_tx_m1 */
+ <4 RK_PB4 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_ctsn: uart9m1-ctsn {
+ rockchip,pins =
+ /* uart9m1_ctsn */
+ <4 RK_PA1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_rtsn: uart9m1-rtsn {
+ rockchip,pins =
+ /* uart9m1_rtsn */
+ <4 RK_PA0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_xfer: uart9m2-xfer {
+ rockchip,pins =
+ /* uart9_rx_m2 */
+ <3 RK_PD4 10 &pcfg_pull_up>,
+ /* uart9_tx_m2 */
+ <3 RK_PD5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_ctsn: uart9m2-ctsn {
+ rockchip,pins =
+ /* uart9m2_ctsn */
+ <3 RK_PD3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_rtsn: uart9m2-rtsn {
+ rockchip,pins =
+ /* uart9m2_rtsn */
+ <3 RK_PD2 10 &pcfg_pull_none>;
+ };
+ };
+
+ vop {
+ /omit-if-no-ref/
+ vop_pins: vop-pins {
+ rockchip,pins =
+ /* vop_post_empty */
+ <1 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+ bt656 {
+ /omit-if-no-ref/
+ bt656_pins: bt656-pins {
+ rockchip,pins =
+ /* bt1120_clkout */
+ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d0 */
+ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d1 */
+ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d2 */
+ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d3 */
+ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d4 */
+ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d5 */
+ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d6 */
+ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
+ /* bt1120_d7 */
+ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ gpio-func {
+ /omit-if-no-ref/
+ tsadc_gpio_func: tsadc-gpio-func {
+ rockchip,pins =
+ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
new file mode 100644
index 0000000000..005cde61b4
--- /dev/null
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -0,0 +1,1703 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rk3588-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/rk3588-power.h>
+#include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+/ {
+ compatible = "rockchip,rk3588";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_l0>;
+ };
+ core1 {
+ cpu = <&cpu_l1>;
+ };
+ core2 {
+ cpu = <&cpu_l2>;
+ };
+ core3 {
+ cpu = <&cpu_l3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu_b0>;
+ };
+ core1 {
+ cpu = <&cpu_b1>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&cpu_b2>;
+ };
+ core1 {
+ cpu = <&cpu_b3>;
+ };
+ };
+ };
+
+ cpu_l0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l0>;
+ dynamic-power-coefficient = <228>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_l1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l1>;
+ dynamic-power-coefficient = <228>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_l2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l2>;
+ dynamic-power-coefficient = <228>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_l3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <530>;
+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l3>;
+ dynamic-power-coefficient = <228>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_b0: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b0>;
+ dynamic-power-coefficient = <416>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_b1: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b1>;
+ dynamic-power-coefficient = <416>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_b2: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b2>;
+ dynamic-power-coefficient = <416>;
+ #cooling-cells = <2>;
+ };
+
+ cpu_b3: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_b3>;
+ dynamic-power-coefficient = <416>;
+ #cooling-cells = <2>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <100>;
+ exit-latency-us = <120>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_cache_l0: l2-cache-l0 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l1: l2-cache-l1 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l2: l2-cache-l2 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l3: l2-cache-l3 {
+ compatible = "cache";
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b0: l2-cache-b0 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b1: l2-cache-b1 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b2: l2-cache-b2 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_b3: l2-cache-b3 {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <3145728>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
+ };
+ };
+
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
+ <&scmi_clk SCMI_CLK_CPUB23>;
+ assigned-clock-rates = <1200000000>,
+ <1200000000>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
+ };
+
+ pmu-a76 {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ spll: clock-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <702000000>;
+ clock-output-names = "spll";
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+ };
+
+ xin24m: clock-1 {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ xin32k: clock-2 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ pmu_sram: sram@10f000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ ranges = <0 0x0 0x0010f000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ sys_grf: syscon@fd58c000 {
+ compatible = "rockchip,rk3588-sys-grf", "syscon";
+ reg = <0x0 0xfd58c000 0x0 0x1000>;
+ };
+
+ php_grf: syscon@fd5b0000 {
+ compatible = "rockchip,rk3588-php-grf", "syscon";
+ reg = <0x0 0xfd5b0000 0x0 0x1000>;
+ };
+
+ ioc: syscon@fd5f0000 {
+ compatible = "rockchip,rk3588-ioc", "syscon";
+ reg = <0x0 0xfd5f0000 0x0 0x10000>;
+ };
+
+ system_sram1: sram@fd600000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xfd600000 0x0 0x100000>;
+ ranges = <0x0 0x0 0xfd600000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ cru: clock-controller@fd7c0000 {
+ compatible = "rockchip,rk3588-cru";
+ reg = <0x0 0xfd7c0000 0x0 0x5c000>;
+ assigned-clocks =
+ <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
+ <&cru PLL_NPLL>, <&cru PLL_GPLL>,
+ <&cru ACLK_CENTER_ROOT>,
+ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
+ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
+ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
+ <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
+ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
+ <&cru CLK_GPU>;
+ assigned-clock-rates =
+ <100000000>, <786432000>,
+ <850000000>, <1188000000>,
+ <702000000>,
+ <400000000>, <500000000>,
+ <800000000>, <100000000>,
+ <400000000>, <100000000>,
+ <200000000>, <500000000>,
+ <375000000>, <150000000>,
+ <200000000>;
+ rockchip,grf = <&php_grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ i2c0: i2c@fd880000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfd880000 0x0 0x1000>;
+ interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c0m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@fd890000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfd890000 0x0 0x100>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 6>, <&dmac0 7>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart0m1_xfer>;
+ pinctrl-names = "default";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@fd8b0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0000 0x0 0x10>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm0m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@fd8b0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0010 0x0 0x10>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm1m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@fd8b0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0020 0x0 0x10>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm2m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@fd8b0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfd8b0030 0x0 0x10>;
+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm3m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pmu: power-management@fd8d8000 {
+ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xfd8d8000 0x0 0x400>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3588-power-controller";
+ #address-cells = <1>;
+ #power-domain-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* These power domains are grouped by VD_NPU */
+ power-domain@RK3588_PD_NPU {
+ reg = <RK3588_PD_NPU>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3588_PD_NPUTOP {
+ reg = <RK3588_PD_NPUTOP>;
+ clocks = <&cru HCLK_NPU_ROOT>,
+ <&cru PCLK_NPU_ROOT>,
+ <&cru CLK_NPU_DSU0>,
+ <&cru HCLK_NPU_CM0_ROOT>;
+ pm_qos = <&qos_npu0_mwr>,
+ <&qos_npu0_mro>,
+ <&qos_mcu_npu>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3588_PD_NPU1 {
+ reg = <RK3588_PD_NPU1>;
+ clocks = <&cru HCLK_NPU_ROOT>,
+ <&cru PCLK_NPU_ROOT>,
+ <&cru CLK_NPU_DSU0>;
+ pm_qos = <&qos_npu1>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_NPU2 {
+ reg = <RK3588_PD_NPU2>;
+ clocks = <&cru HCLK_NPU_ROOT>,
+ <&cru PCLK_NPU_ROOT>,
+ <&cru CLK_NPU_DSU0>;
+ pm_qos = <&qos_npu2>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ /* These power domains are grouped by VD_GPU */
+ power-domain@RK3588_PD_GPU {
+ reg = <RK3588_PD_GPU>;
+ clocks = <&cru CLK_GPU>,
+ <&cru CLK_GPU_COREGROUP>,
+ <&cru CLK_GPU_STACKS>;
+ pm_qos = <&qos_gpu_m0>,
+ <&qos_gpu_m1>,
+ <&qos_gpu_m2>,
+ <&qos_gpu_m3>;
+ #power-domain-cells = <0>;
+ };
+ /* These power domains are grouped by VD_VCODEC */
+ power-domain@RK3588_PD_VCODEC {
+ reg = <RK3588_PD_VCODEC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ power-domain@RK3588_PD_RKVDEC0 {
+ reg = <RK3588_PD_RKVDEC0>;
+ clocks = <&cru HCLK_RKVDEC0>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_RKVDEC0>,
+ <&cru ACLK_RKVDEC_CCU>;
+ pm_qos = <&qos_rkvdec0>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_RKVDEC1 {
+ reg = <RK3588_PD_RKVDEC1>;
+ clocks = <&cru HCLK_RKVDEC1>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_RKVDEC1>;
+ pm_qos = <&qos_rkvdec1>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_VENC0 {
+ reg = <RK3588_PD_VENC0>;
+ clocks = <&cru HCLK_RKVENC0>,
+ <&cru ACLK_RKVENC0>;
+ pm_qos = <&qos_rkvenc0_m0ro>,
+ <&qos_rkvenc0_m1ro>,
+ <&qos_rkvenc0_m2wo>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ power-domain@RK3588_PD_VENC1 {
+ reg = <RK3588_PD_VENC1>;
+ clocks = <&cru HCLK_RKVENC1>,
+ <&cru HCLK_RKVENC0>,
+ <&cru ACLK_RKVENC0>,
+ <&cru ACLK_RKVENC1>;
+ pm_qos = <&qos_rkvenc1_m0ro>,
+ <&qos_rkvenc1_m1ro>,
+ <&qos_rkvenc1_m2wo>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@RK3588_PD_VDPU {
+ reg = <RK3588_PD_VDPU>;
+ clocks = <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_LOW_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_JPEG_DECODER_ROOT>,
+ <&cru ACLK_IEP2P0>,
+ <&cru HCLK_IEP2P0>,
+ <&cru ACLK_JPEG_ENCODER0>,
+ <&cru HCLK_JPEG_ENCODER0>,
+ <&cru ACLK_JPEG_ENCODER1>,
+ <&cru HCLK_JPEG_ENCODER1>,
+ <&cru ACLK_JPEG_ENCODER2>,
+ <&cru HCLK_JPEG_ENCODER2>,
+ <&cru ACLK_JPEG_ENCODER3>,
+ <&cru HCLK_JPEG_ENCODER3>,
+ <&cru ACLK_JPEG_DECODER>,
+ <&cru HCLK_JPEG_DECODER>,
+ <&cru ACLK_RGA2>,
+ <&cru HCLK_RGA2>;
+ pm_qos = <&qos_iep>,
+ <&qos_jpeg_dec>,
+ <&qos_jpeg_enc0>,
+ <&qos_jpeg_enc1>,
+ <&qos_jpeg_enc2>,
+ <&qos_jpeg_enc3>,
+ <&qos_rga2_mro>,
+ <&qos_rga2_mwo>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+
+ power-domain@RK3588_PD_AV1 {
+ reg = <RK3588_PD_AV1>;
+ clocks = <&cru PCLK_AV1>,
+ <&cru ACLK_AV1>,
+ <&cru HCLK_VDPU_ROOT>;
+ pm_qos = <&qos_av1>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_RKVDEC0 {
+ reg = <RK3588_PD_RKVDEC0>;
+ clocks = <&cru HCLK_RKVDEC0>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>,
+ <&cru ACLK_RKVDEC0>;
+ pm_qos = <&qos_rkvdec0>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_RKVDEC1 {
+ reg = <RK3588_PD_RKVDEC1>;
+ clocks = <&cru HCLK_RKVDEC1>,
+ <&cru HCLK_VDPU_ROOT>,
+ <&cru ACLK_VDPU_ROOT>;
+ pm_qos = <&qos_rkvdec1>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_RGA30 {
+ reg = <RK3588_PD_RGA30>;
+ clocks = <&cru ACLK_RGA3_0>,
+ <&cru HCLK_RGA3_0>;
+ pm_qos = <&qos_rga3_0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ power-domain@RK3588_PD_VOP {
+ reg = <RK3588_PD_VOP>;
+ clocks = <&cru PCLK_VOP_ROOT>,
+ <&cru HCLK_VOP_ROOT>,
+ <&cru ACLK_VOP>;
+ pm_qos = <&qos_vop_m0>,
+ <&qos_vop_m1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ power-domain@RK3588_PD_VO0 {
+ reg = <RK3588_PD_VO0>;
+ clocks = <&cru PCLK_VO0_ROOT>,
+ <&cru PCLK_VO0_S_ROOT>,
+ <&cru HCLK_VO0_S_ROOT>,
+ <&cru ACLK_VO0_ROOT>,
+ <&cru HCLK_HDCP0>,
+ <&cru ACLK_HDCP0>,
+ <&cru HCLK_VOP_ROOT>;
+ pm_qos = <&qos_hdcp0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ power-domain@RK3588_PD_VO1 {
+ reg = <RK3588_PD_VO1>;
+ clocks = <&cru PCLK_VO1_ROOT>,
+ <&cru PCLK_VO1_S_ROOT>,
+ <&cru HCLK_VO1_S_ROOT>,
+ <&cru HCLK_HDCP1>,
+ <&cru ACLK_HDCP1>,
+ <&cru ACLK_HDMIRX_ROOT>,
+ <&cru HCLK_VO1USB_TOP_ROOT>;
+ pm_qos = <&qos_hdcp1>,
+ <&qos_hdmirx>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_VI {
+ reg = <RK3588_PD_VI>;
+ clocks = <&cru HCLK_VI_ROOT>,
+ <&cru PCLK_VI_ROOT>,
+ <&cru HCLK_ISP0>,
+ <&cru ACLK_ISP0>,
+ <&cru HCLK_VICAP>,
+ <&cru ACLK_VICAP>;
+ pm_qos = <&qos_isp0_mro>,
+ <&qos_isp0_mwo>,
+ <&qos_vicap_m0>,
+ <&qos_vicap_m1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ power-domain@RK3588_PD_ISP1 {
+ reg = <RK3588_PD_ISP1>;
+ clocks = <&cru HCLK_ISP1>,
+ <&cru ACLK_ISP1>,
+ <&cru HCLK_VI_ROOT>,
+ <&cru PCLK_VI_ROOT>;
+ pm_qos = <&qos_isp1_mwo>,
+ <&qos_isp1_mro>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_FEC {
+ reg = <RK3588_PD_FEC>;
+ clocks = <&cru HCLK_FISHEYE0>,
+ <&cru ACLK_FISHEYE0>,
+ <&cru HCLK_FISHEYE1>,
+ <&cru ACLK_FISHEYE1>,
+ <&cru PCLK_VI_ROOT>;
+ pm_qos = <&qos_fisheye0>,
+ <&qos_fisheye1>;
+ #power-domain-cells = <0>;
+ };
+ };
+ power-domain@RK3588_PD_RGA31 {
+ reg = <RK3588_PD_RGA31>;
+ clocks = <&cru HCLK_RGA3_1>,
+ <&cru ACLK_RGA3_1>;
+ pm_qos = <&qos_rga3_1>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_USB {
+ reg = <RK3588_PD_USB>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_USB_ROOT>,
+ <&cru HCLK_USB_ROOT>,
+ <&cru HCLK_HOST0>,
+ <&cru HCLK_HOST_ARB0>,
+ <&cru HCLK_HOST1>,
+ <&cru HCLK_HOST_ARB1>;
+ pm_qos = <&qos_usb3_0>,
+ <&qos_usb3_1>,
+ <&qos_usb2host_0>,
+ <&qos_usb2host_1>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_GMAC {
+ reg = <RK3588_PD_GMAC>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_PCIE_ROOT>,
+ <&cru ACLK_PHP_ROOT>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_PCIE {
+ reg = <RK3588_PD_PCIE>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_PCIE_ROOT>,
+ <&cru ACLK_PHP_ROOT>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_SDIO {
+ reg = <RK3588_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru HCLK_NVM_ROOT>;
+ pm_qos = <&qos_sdio>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_AUDIO {
+ reg = <RK3588_PD_AUDIO>;
+ clocks = <&cru HCLK_AUDIO_ROOT>,
+ <&cru PCLK_AUDIO_ROOT>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3588_PD_SDMMC {
+ reg = <RK3588_PD_SDMMC>;
+ pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ qos_gpu_m0: qos@fdf35000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf35000 0x0 0x20>;
+ };
+
+ qos_gpu_m1: qos@fdf35200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf35200 0x0 0x20>;
+ };
+
+ qos_gpu_m2: qos@fdf35400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf35400 0x0 0x20>;
+ };
+
+ qos_gpu_m3: qos@fdf35600 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf35600 0x0 0x20>;
+ };
+
+ qos_rga3_1: qos@fdf36000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf36000 0x0 0x20>;
+ };
+
+ qos_sdio: qos@fdf39000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf39000 0x0 0x20>;
+ };
+
+ qos_sdmmc: qos@fdf3d800 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf3d800 0x0 0x20>;
+ };
+
+ qos_usb3_1: qos@fdf3e000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf3e000 0x0 0x20>;
+ };
+
+ qos_usb3_0: qos@fdf3e200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf3e200 0x0 0x20>;
+ };
+
+ qos_usb2host_0: qos@fdf3e400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf3e400 0x0 0x20>;
+ };
+
+ qos_usb2host_1: qos@fdf3e600 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf3e600 0x0 0x20>;
+ };
+
+ qos_fisheye0: qos@fdf40000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf40000 0x0 0x20>;
+ };
+
+ qos_fisheye1: qos@fdf40200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf40200 0x0 0x20>;
+ };
+
+ qos_isp0_mro: qos@fdf40400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf40400 0x0 0x20>;
+ };
+
+ qos_isp0_mwo: qos@fdf40500 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf40500 0x0 0x20>;
+ };
+
+ qos_vicap_m0: qos@fdf40600 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf40600 0x0 0x20>;
+ };
+
+ qos_vicap_m1: qos@fdf40800 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf40800 0x0 0x20>;
+ };
+
+ qos_isp1_mwo: qos@fdf41000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf41000 0x0 0x20>;
+ };
+
+ qos_isp1_mro: qos@fdf41100 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf41100 0x0 0x20>;
+ };
+
+ qos_rkvenc0_m0ro: qos@fdf60000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf60000 0x0 0x20>;
+ };
+
+ qos_rkvenc0_m1ro: qos@fdf60200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf60200 0x0 0x20>;
+ };
+
+ qos_rkvenc0_m2wo: qos@fdf60400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf60400 0x0 0x20>;
+ };
+
+ qos_rkvenc1_m0ro: qos@fdf61000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf61000 0x0 0x20>;
+ };
+
+ qos_rkvenc1_m1ro: qos@fdf61200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf61200 0x0 0x20>;
+ };
+
+ qos_rkvenc1_m2wo: qos@fdf61400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf61400 0x0 0x20>;
+ };
+
+ qos_rkvdec0: qos@fdf62000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf62000 0x0 0x20>;
+ };
+
+ qos_rkvdec1: qos@fdf63000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf63000 0x0 0x20>;
+ };
+
+ qos_av1: qos@fdf64000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf64000 0x0 0x20>;
+ };
+
+ qos_iep: qos@fdf66000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66000 0x0 0x20>;
+ };
+
+ qos_jpeg_dec: qos@fdf66200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66200 0x0 0x20>;
+ };
+
+ qos_jpeg_enc0: qos@fdf66400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66400 0x0 0x20>;
+ };
+
+ qos_jpeg_enc1: qos@fdf66600 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66600 0x0 0x20>;
+ };
+
+ qos_jpeg_enc2: qos@fdf66800 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66800 0x0 0x20>;
+ };
+
+ qos_jpeg_enc3: qos@fdf66a00 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66a00 0x0 0x20>;
+ };
+
+ qos_rga2_mro: qos@fdf66c00 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66c00 0x0 0x20>;
+ };
+
+ qos_rga2_mwo: qos@fdf66e00 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf66e00 0x0 0x20>;
+ };
+
+ qos_rga3_0: qos@fdf67000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf67000 0x0 0x20>;
+ };
+
+ qos_vdpu: qos@fdf67200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf67200 0x0 0x20>;
+ };
+
+ qos_npu1: qos@fdf70000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf70000 0x0 0x20>;
+ };
+
+ qos_npu2: qos@fdf71000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf71000 0x0 0x20>;
+ };
+
+ qos_npu0_mwr: qos@fdf72000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf72000 0x0 0x20>;
+ };
+
+ qos_npu0_mro: qos@fdf72200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf72200 0x0 0x20>;
+ };
+
+ qos_mcu_npu: qos@fdf72400 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf72400 0x0 0x20>;
+ };
+
+ qos_hdcp0: qos@fdf80000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf80000 0x0 0x20>;
+ };
+
+ qos_hdcp1: qos@fdf81000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf81000 0x0 0x20>;
+ };
+
+ qos_hdmirx: qos@fdf81200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf81200 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@fdf82000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf82000 0x0 0x20>;
+ };
+
+ qos_vop_m1: qos@fdf82200 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf82200 0x0 0x20>;
+ };
+
+ gmac1: ethernet@fe1c0000 {
+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe1c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
+ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
+ <&cru CLK_GMAC1_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ power-domains = <&power RK3588_PD_GMAC>;
+ resets = <&cru SRST_A_GMAC1>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&sys_grf>;
+ rockchip,php-grf = <&php_grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+ };
+
+ sdhci: mmc@fe2e0000 {
+ compatible = "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0xfe2e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TMCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ max-frequency = <200000000>;
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@fe600000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
+ <0x0 0xfe680000 0 0x100000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
+ mbi-alias = <0x0 0xfe610000>;
+ mbi-ranges = <424 56>;
+ msi-controller;
+ #interrupt-cells = <4>;
+
+ ppi-partitions {
+ ppi_partition0: interrupt-partition-0 {
+ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
+ };
+
+ ppi_partition1: interrupt-partition-1 {
+ affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
+ };
+ };
+ };
+
+ dmac0: dma-controller@fea10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfea10000 0x0 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ dmac1: dma-controller@fea30000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfea30000 0x0 0x4000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ i2c1: i2c@fea90000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfea90000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c1m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@feaa0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeaa0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c2m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@feab0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeab0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c3m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@feac0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeac0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c4m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@fead0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfead0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c5m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@feb00000 {
+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 14>, <&dmac0 15>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@feb10000 {
+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 16>, <&dmac0 17>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@feb20000 {
+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb20000 0x0 0x1000>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 15>, <&dmac1 16>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@feb30000 {
+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfeb30000 0x0 0x1000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 17>, <&dmac1 18>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart1: serial@feb40000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb40000 0x0 0x100>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 8>, <&dmac0 9>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart1m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@feb50000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb50000 0x0 0x100>;
+ interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 10>, <&dmac0 11>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart2m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@feb60000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb60000 0x0 0x100>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 12>, <&dmac0 13>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart3m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@feb70000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb70000 0x0 0x100>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac1 9>, <&dmac1 10>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart4m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@feb80000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb80000 0x0 0x100>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac1 11>, <&dmac1 12>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart5m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart6: serial@feb90000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeb90000 0x0 0x100>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac1 13>, <&dmac1 14>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart6m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart7: serial@feba0000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfeba0000 0x0 0x100>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 7>, <&dmac2 8>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart7m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart8: serial@febb0000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfebb0000 0x0 0x100>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 9>, <&dmac2 10>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart8m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart9: serial@febc0000 {
+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfebc0000 0x0 0x100>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 11>, <&dmac2 12>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&uart9m1_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@febd0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm4m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@febd0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm5m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@febd0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm6m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@febd0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebd0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm7m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm8: pwm@febe0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm8m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm9: pwm@febe0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm9m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm10: pwm@febe0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm10m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm11: pwm@febe0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebe0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm11m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm12: pwm@febf0000 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0000 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm12m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm13: pwm@febf0010 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0010 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm13m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm14: pwm@febf0020 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0020 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm14m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm15: pwm@febf0030 {
+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xfebf0030 0x0 0x10>;
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+ clock-names = "pwm", "pclk";
+ pinctrl-0 = <&pwm15m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@fec80000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfec80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c6m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@fec90000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfec90000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c7m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@feca0000 {
+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfeca0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-0 = <&i2c8m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@fecb0000 {
+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfecb0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac2 13>, <&dmac2 14>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dmac2: dma-controller@fed10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfed10000 0x0 0x4000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ system_sram2: sram@ff001000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xff001000 0x0 0xef000>;
+ ranges = <0x0 0x0 0xff001000 0xef000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3588-pinctrl";
+ ranges;
+ rockchip,grf = <&ioc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gpio0: gpio@fd8a0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfd8a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@fec20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec20000 0x0 0x100>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@fec30000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec30000 0x0 0x100>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@fec40000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec40000 0x0 0x100>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@fec50000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfec50000 0x0 0x100>;
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3588s-pinctrl.dtsi"
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 12/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (10 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 13/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO Jagan Teki
` (4 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
On module WiFi6/BT5 is available in the following Neu6 variants.
Neu6 needs to mount on top of associated Edgeble IO boards for
creating complete platform solutions.
Enable eMMC for now to boot Linux successfully.
commit <3d9a2f7e7c5e> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A SoM")
Add support for Edgeble Neu6 Model A SoM.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 32 ++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a.dtsi
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
new file mode 100644
index 0000000000..38e1a1e25f
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 13/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (11 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 12/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 14/16] arm: rockchip: Add RK3588 arch core support Jagan Teki
` (3 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.
Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.
commit <a5079a534554> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A IO")
Add support for Edgeble Neu6 Model A IO Board.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/dts/Makefile | 3 +++
arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 27 ++++++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 103af9b99c..760b1abf3f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -168,6 +168,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb
+dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+ rk3588-edgeble-neu6a-io.dtb
+
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts
new file mode 100644
index 0000000000..b515438920
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rk3588.dtsi"
+#include "rk3588-edgeble-neu6a.dtsi"
+
+/ {
+ model = "Edgeble Neu6A IO Board";
+ compatible = "edgeble,neural-compute-module-6a-io",
+ "edgeble,neural-compute-module-6a", "rockchip,rk3588";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 14/16] arm: rockchip: Add RK3588 arch core support
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (12 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 13/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi Jagan Teki
` (2 subsequent siblings)
16 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.
Add arch core support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/include/asm/arch-rk3588/boot0.h | 11 ++
arch/arm/include/asm/arch-rk3588/gpio.h | 11 ++
arch/arm/mach-rockchip/Kconfig | 20 +++
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3588/Kconfig | 15 ++
arch/arm/mach-rockchip/rk3588/Makefile | 9 +
arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 33 ++++
arch/arm/mach-rockchip/rk3588/rk3588.c | 162 ++++++++++++++++++
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 32 ++++
include/configs/rk3588_common.h | 32 ++++
10 files changed, 326 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rk3588/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3588/gpio.h
create mode 100644 arch/arm/mach-rockchip/rk3588/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3588/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3588/clk_rk3588.c
create mode 100644 arch/arm/mach-rockchip/rk3588/rk3588.c
create mode 100644 arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
create mode 100644 include/configs/rk3588_common.h
diff --git a/arch/arm/include/asm/arch-rk3588/boot0.h b/arch/arm/include/asm/arch-rk3588/boot0.h
new file mode 100644
index 0000000000..dea2b20252
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3588/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3588/gpio.h b/arch/arm/include/asm/arch-rk3588/gpio.h
new file mode 100644
index 0000000000..b48c0a5cf8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3588/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index b678ec4131..71774a5f2e 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -294,6 +294,25 @@ config ROCKCHIP_RK3568
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3588
+ bool "Support Rockchip RK3588"
+ select ARM64
+ select SUPPORT_SPL
+ select SPL
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ imply ROCKCHIP_COMMON_BOARD
+ help
+ The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
+ quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
+ HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
+ SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
+ SDIO3.0 I2C, UART, SPI, GPIO and PWM.
+
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@@ -491,6 +510,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
+source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 32138fa723..bee4fa4b5a 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
+obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
new file mode 100644
index 0000000000..e8c14e4187
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -0,0 +1,15 @@
+if ROCKCHIP_RK3588
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xfd588080
+
+config ROCKCHIP_STIMER_BASE
+ default 0xfd8c8000
+
+config SYS_SOC
+ default "rk3588"
+
+config SYS_MALLOC_F_LEN
+ default 0x80000
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3588/Makefile b/arch/arm/mach-rockchip/rk3588/Makefile
new file mode 100644
index 0000000000..4003eea87a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3588.o
+obj-y += clk_rk3588.o
+obj-y += syscon_rk3588.o
diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c
new file mode 100644
index 0000000000..89e0ab99dd
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3588.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3588_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3588_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
new file mode 100644
index 0000000000..8e4f5e55f4
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/ioc_rk3588.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FIREWALL_DDR_BASE 0xfe030000
+#define FW_DDR_MST5_REG 0x54
+#define FW_DDR_MST13_REG 0x74
+#define FW_DDR_MST21_REG 0x94
+#define FW_DDR_MST26_REG 0xa8
+#define FW_DDR_MST27_REG 0xac
+#define FIREWALL_SYSMEM_BASE 0xfe038000
+#define FW_SYSM_MST5_REG 0x54
+#define FW_SYSM_MST13_REG 0x74
+#define FW_SYSM_MST21_REG 0x94
+#define FW_SYSM_MST26_REG 0xa8
+#define FW_SYSM_MST27_REG 0xac
+
+#define PMU1_IOC_BASE 0xfd5f0000
+#define PMU2_IOC_BASE 0xfd5f4000
+
+#define BUS_IOC_BASE 0xfd5f8000
+#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
+#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
+#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
+#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
+#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
+
+static struct mm_region rk3588_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xf0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x900000000,
+ .phys = 0x900000000,
+ .size = 0x150000000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3588_mem_map;
+
+/* GPIO0B_IOMUX_SEL_H */
+enum {
+ GPIO0B5_SHIFT = 4,
+ GPIO0B5_MASK = GENMASK(7, 4),
+ GPIO0B5_REFER = 8,
+ GPIO0B5_UART2_TX_M0 = 10,
+
+ GPIO0B6_SHIFT = 8,
+ GPIO0B6_MASK = GENMASK(11, 8),
+ GPIO0B6_REFER = 8,
+ GPIO0B6_UART2_RX_M0 = 10,
+};
+
+void board_debug_uart_init(void)
+{
+ __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+ static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
+
+ /* Refer to BUS_IOC */
+ rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
+ GPIO0B6_MASK | GPIO0B5_MASK,
+ GPIO0B6_REFER << GPIO0B6_SHIFT |
+ GPIO0B5_REFER << GPIO0B5_SHIFT);
+
+ /* UART2_M0 Switch iomux */
+ rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
+ GPIO0B6_MASK | GPIO0B5_MASK,
+ GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
+ GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void rockchip_stimer_init(void)
+{
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+
+ if (reg & 0x1)
+ return;
+
+ asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
+ writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+}
+#endif
+
+#ifndef CONFIG_TPL_BUILD
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ int secure_reg;
+
+ /* Set the SDMMC eMMC crypto_ns FSPI access secure area */
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
+ secure_reg &= 0xffff0000;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
+
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
+ secure_reg &= 0xffff0000;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
+
+ /* Set emmc iomux for good extension if the emmc is not the boot device */
+ writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
+ writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
+ writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
new file mode 100644
index 0000000000..e8772d3a38
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3588_syscon_ids[] = {
+ { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
+ { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF },
+ { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
+ { .compatible = "rockchip,rk3588-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
+ { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY0_GRF },
+ { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY1_GRF },
+ { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY2_GRF },
+ { .compatible = "rockchip,rk3588-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3588) = {
+ .name = "rk3588_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3588_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
new file mode 100644
index 0000000000..abd20139aa
--- /dev/null
+++ b/include/configs/rk3588_common.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#ifndef __CONFIG_RK3588_COMMON_H
+#define __CONFIG_RK3588_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0xff000000
+
+#define CFG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xf0000000
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "fdt_addr_r=0x0a100000\0" \
+ "kernel_addr_r=0x02080000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+
+#endif /* __CONFIG_RK3588_COMMON_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (13 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 14/16] arm: rockchip: Add RK3588 arch core support Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-01-27 13:33 ` Eugen Hristev
2023-01-27 15:19 ` Eugen Hristev
2023-01-25 22:27 ` [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6 Jagan Teki
2023-01-25 22:47 ` [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jonas Karlman
16 siblings, 2 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RK3588 SoC.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
new file mode 100644
index 0000000000..b5cc4dcc60
--- /dev/null
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rockchip-u-boot.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ dmc {
+ compatible = "rockchip,rk3588-dmc";
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ };
+
+ pmu1_grf: syscon@fd58a000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3588-pmu1-grf", "syscon";
+ reg = <0x0 0xfd58a000 0x0 0x2000>;
+ };
+
+ sdmmc: mmc@fe2c0000 {
+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SDMMC_SAMPLE>, <&cru SCLK_SDMMC_DRV>,
+ <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
+ clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+ status = "disabled";
+ };
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio4 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&scmi {
+ u-boot,dm-spl;
+};
+
+&scmi_clk {
+ u-boot,dm-spl;
+};
+
+&xin24m {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&cru {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&sys_grf {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ u-boot,dm-spl;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&ioc {
+ u-boot,dm-spl;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (14 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi Jagan Teki
@ 2023-01-25 22:27 ` Jagan Teki
2023-02-02 8:23 ` Eugen Hristev
2023-01-25 22:47 ` [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jonas Karlman
16 siblings, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-25 22:27 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot, Jagan Teki
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
On module WiFi6/BT5 is available in the following Neu6 variants.
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.
Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.
Add support for Edgeble Neu6 Model A IO Board.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 23 +++++++
arch/arm/mach-rockchip/rk3588/Kconfig | 15 ++++
board/edgeble/neural-compute-module-6/Kconfig | 15 ++++
.../neural-compute-module-6/MAINTAINERS | 6 ++
.../edgeble/neural-compute-module-6/Makefile | 7 ++
board/edgeble/neural-compute-module-6/neu6.c | 4 ++
configs/neu6a-io-rk3588_defconfig | 68 +++++++++++++++++++
doc/board/rockchip/rockchip.rst | 2 +
include/configs/neural-compute-module-6.h | 15 ++++
9 files changed, 155 insertions(+)
create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
create mode 100644 board/edgeble/neural-compute-module-6/Kconfig
create mode 100644 board/edgeble/neural-compute-module-6/MAINTAINERS
create mode 100644 board/edgeble/neural-compute-module-6/Makefile
create mode 100644 board/edgeble/neural-compute-module-6/neu6.c
create mode 100644 configs/neu6a-io-rk3588_defconfig
create mode 100644 include/configs/neural-compute-module-6.h
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
new file mode 100644
index 0000000000..dc94ff9ef0
--- /dev/null
+++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = &sdmmc;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index e8c14e4187..def4094e2e 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -1,5 +1,18 @@
if ROCKCHIP_RK3588
+config TARGET_RK3588_NEU6
+ bool "Edgeble Neural Compute Module 6(Neu6) SoM"
+ select BOARD_LATE_INIT
+ help
+ Neu6:
+ Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module
+ based on Rockchip RK3588 from Edgeble AI.
+
+ Neu6-IO:
+ Neural Compute Module 6(Neu6) IO board is an industrial form factor
+ IO board and Neu6a needs to mount on top of this IO board in order to
+ create complete Edgeble Neural Compute Module 6(Neu6) IO platform.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
@@ -12,4 +25,6 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
default 0x80000
+source board/edgeble/neural-compute-module-6/Kconfig
+
endif
diff --git a/board/edgeble/neural-compute-module-6/Kconfig b/board/edgeble/neural-compute-module-6/Kconfig
new file mode 100644
index 0000000000..c445454dde
--- /dev/null
+++ b/board/edgeble/neural-compute-module-6/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_RK3588_NEU6
+
+config SYS_BOARD
+ default "neural-compute-module-6"
+
+config SYS_VENDOR
+ default "edgeble"
+
+config SYS_CONFIG_NAME
+ default "neural-compute-module-6"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS
new file mode 100644
index 0000000000..249df957f1
--- /dev/null
+++ b/board/edgeble/neural-compute-module-6/MAINTAINERS
@@ -0,0 +1,6 @@
+RK3588-NEU6
+M: Jagan Teki <jagan@edgeble.ai>
+S: Maintained
+F: board/edgeble/neural-compute-module-6
+F: include/configs/neural-compute-module-6.h
+F: configs/neu6a-io-rk3588_defconfig
diff --git a/board/edgeble/neural-compute-module-6/Makefile b/board/edgeble/neural-compute-module-6/Makefile
new file mode 100644
index 0000000000..28310b1b34
--- /dev/null
+++ b/board/edgeble/neural-compute-module-6/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += neu6.o
diff --git a/board/edgeble/neural-compute-module-6/neu6.c b/board/edgeble/neural-compute-module-6/neu6.c
new file mode 100644
index 0000000000..3d2262ce97
--- /dev/null
+++ b/board/edgeble/neural-compute-module-6/neu6.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
new file mode 100644
index 0000000000..c089f415d7
--- /dev/null
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_RK3588_NEU6=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x400000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 28c837a382..a140c1a8a4 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -86,6 +86,8 @@ List of mainline supported Rockchip boards:
- Radxa ROCK Pi 4 (rock-pi-4-rk3399)
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
+* rk3588
+ - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-r1126)
* rv1108
- Rockchip Evb-rv1108 (evb-rv1108)
- Elgin-R1 (elgin-rv1108)
diff --git a/include/configs/neural-compute-module-6.h b/include/configs/neural-compute-module-6.h
new file mode 100644
index 0000000000..52501b7ab8
--- /dev/null
+++ b/include/configs/neural-compute-module-6.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#ifndef __NEURAL_COMPUTE_MODULE_6_H
+#define __NEURAL_COMPUTE_MODULE_6_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __NEURAL_COMPUTE_MODULE_6_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
` (15 preceding siblings ...)
2023-01-25 22:27 ` [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6 Jagan Teki
@ 2023-01-25 22:47 ` Jonas Karlman
2023-01-26 16:51 ` Jagan Teki
2023-01-29 9:47 ` Kever Yang
16 siblings, 2 replies; 56+ messages in thread
From: Jonas Karlman @ 2023-01-25 22:47 UTC (permalink / raw)
To: Jagan Teki, Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot
Hi Jagan,
On 2023-01-25 23:27, Jagan Teki wrote:
> This series support Rockchip RK3588. All the device tree files are
> synced from linux-next with the proper SHA1 mentioned in the commit
> messages.
>
> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> it is failing to load ATF entry from SPL and hang.
>
> Verified below BL31 versions,
> bl31-v1.15
> bl31-v1.21
> bl31-v1.22
> bl31-v1.23
> bl31-v1.24
> bl31-v1.25
> bl31-v1.26
>
> Rever-engineered with respect to rockchip u-boot by using the same
> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> mainline showing the same issue.
>
> Log:
>
> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> change to F1: 528MHz
> change to F2: 1068MHz
> change to F3: 1560MHz
> change to F0: 2112MHz
> out
>
> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> Trying to boot from MMC1
> bl31_entry: atf_entry start
> << hang >>
>
> Any information on BL31 for RK3588 please share.
I had a similar strange booing issue with RK3568 and mainline U-Boot,
turned out to be related to all parts of ATF not being properly loaded
into PMU SRAM.
Using my series at [1] I managed to get ATF to be fully loaded into
PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
the segment being loaded ended up corrupted.
The use of 512 bytes alignment of the FIT helped mitigate that issue.
Vendor U-Boot use a bounce buffer for all parts that is written into
SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
You can also find newer bl31 at [2], up to version v1.32.
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891
[2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35
Regards,
Jonas
>
> Any inputs?
> Jagan.
>
> Jagan Teki (16):
> rockchip: mkimage: Add rk3588 support
> arm: rockchip: Add cru header for rk3588
> arm: rockchip: Add grf header for rk3588
> dt-bindings: clk: Add dt-binding header for RK3588
> clk: rockchip: Add rk3588 clk support
> clk: rockchip: pll: Add pll_rk3588 type for rk3588
> ram: rockchip: Add rk3588 ddr driver support
> dt-bindings: power: Add power-domain header for rk3588
> dt-bindings: reset: add rk3588 reset definitions
> arm: rockchip: Add ioc header for rk3588
> arm64: dts: rockchip: Add base DT for rk3588 SoC
> arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
> arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
> arm: rockchip: Add RK3588 arch core support
> ARM: dts: rockchip: Add rk3588-u-boot.dtsi
> board: rockchip: Add Edgeble Neural Compute Module 6
>
> arch/arm/dts/Makefile | 3 +
> .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 23 +
> arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 27 +
> arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 32 +
> arch/arm/dts/rk3588-pinctrl.dtsi | 516 +++
> arch/arm/dts/rk3588-u-boot.dtsi | 101 +
> arch/arm/dts/rk3588.dtsi | 58 +
> arch/arm/dts/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++
> arch/arm/dts/rk3588s.dtsi | 1703 +++++++++
> arch/arm/include/asm/arch-rk3588/boot0.h | 11 +
> arch/arm/include/asm/arch-rk3588/gpio.h | 11 +
> arch/arm/include/asm/arch-rockchip/clock.h | 24 +
> .../include/asm/arch-rockchip/cru_rk3588.h | 451 +++
> .../include/asm/arch-rockchip/grf_rk3588.h | 35 +
> .../include/asm/arch-rockchip/ioc_rk3588.h | 102 +
> arch/arm/mach-rockchip/Kconfig | 20 +
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3588/Kconfig | 30 +
> arch/arm/mach-rockchip/rk3588/Makefile | 9 +
> arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 33 +
> arch/arm/mach-rockchip/rk3588/rk3588.c | 162 +
> arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 32 +
> board/edgeble/neural-compute-module-6/Kconfig | 15 +
> .../neural-compute-module-6/MAINTAINERS | 6 +
> .../edgeble/neural-compute-module-6/Makefile | 7 +
> board/edgeble/neural-compute-module-6/neu6.c | 4 +
> configs/neu6a-io-rk3588_defconfig | 68 +
> doc/board/rockchip/rockchip.rst | 2 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_pll.c | 267 +-
> drivers/clk/rockchip/clk_rk3588.c | 2019 ++++++++++
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3588.c | 56 +
> include/configs/neural-compute-module-6.h | 15 +
> include/configs/rk3588_common.h | 32 +
> .../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++
> include/dt-bindings/power/rk3588-power.h | 69 +
> .../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++
> tools/rkcommon.c | 1 +
> 39 files changed, 10867 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io.dts
> create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a.dtsi
> create mode 100644 arch/arm/dts/rk3588-pinctrl.dtsi
> create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3588.dtsi
> create mode 100644 arch/arm/dts/rk3588s-pinctrl.dtsi
> create mode 100644 arch/arm/dts/rk3588s.dtsi
> create mode 100644 arch/arm/include/asm/arch-rk3588/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3588/gpio.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3588.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3588.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
> create mode 100644 arch/arm/mach-rockchip/rk3588/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3588/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3588/clk_rk3588.c
> create mode 100644 arch/arm/mach-rockchip/rk3588/rk3588.c
> create mode 100644 arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
> create mode 100644 board/edgeble/neural-compute-module-6/Kconfig
> create mode 100644 board/edgeble/neural-compute-module-6/MAINTAINERS
> create mode 100644 board/edgeble/neural-compute-module-6/Makefile
> create mode 100644 board/edgeble/neural-compute-module-6/neu6.c
> create mode 100644 configs/neu6a-io-rk3588_defconfig
> create mode 100644 drivers/clk/rockchip/clk_rk3588.c
> create mode 100644 drivers/ram/rockchip/sdram_rk3588.c
> create mode 100644 include/configs/neural-compute-module-6.h
> create mode 100644 include/configs/rk3588_common.h
> create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h
> create mode 100644 include/dt-bindings/power/rk3588-power.h
> create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-25 22:47 ` [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jonas Karlman
@ 2023-01-26 16:51 ` Jagan Teki
2023-01-26 16:58 ` Jonas Karlman
2023-01-29 9:47 ` Kever Yang
1 sibling, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-26 16:51 UTC (permalink / raw)
To: Jonas Karlman
Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
Hi Jonas,
On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Jagan,
>
> On 2023-01-25 23:27, Jagan Teki wrote:
> > This series support Rockchip RK3588. All the device tree files are
> > synced from linux-next with the proper SHA1 mentioned in the commit
> > messages.
> >
> > Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> > it is failing to load ATF entry from SPL and hang.
> >
> > Verified below BL31 versions,
> > bl31-v1.15
> > bl31-v1.21
> > bl31-v1.22
> > bl31-v1.23
> > bl31-v1.24
> > bl31-v1.25
> > bl31-v1.26
> >
> > Rever-engineered with respect to rockchip u-boot by using the same
> > FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> > mainline showing the same issue.
> >
> > Log:
> >
> > LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> > channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > change to F1: 528MHz
> > change to F2: 1068MHz
> > change to F3: 1560MHz
> > change to F0: 2112MHz
> > out
> >
> > U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> > Trying to boot from MMC1
> > bl31_entry: atf_entry start
> > << hang >>
> >
> > Any information on BL31 for RK3588 please share.
>
> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> turned out to be related to all parts of ATF not being properly loaded
> into PMU SRAM.
>
> Using my series at [1] I managed to get ATF to be fully loaded into
> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> the segment being loaded ended up corrupted.
>
> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> Vendor U-Boot use a bounce buffer for all parts that is written into
> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
>
> You can also find newer bl31 at [2], up to version v1.32.
>
> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891
> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35
Thanks for the details. I did apply this set on the master. No change
in the behavior, used BL31 and ddr from [2] as well as in
rkbin/master.
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 16:51 ` Jagan Teki
@ 2023-01-26 16:58 ` Jonas Karlman
2023-01-26 17:42 ` Jagan Teki
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-01-26 16:58 UTC (permalink / raw)
To: Jagan Teki; +Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
Hi Jagan,
On 2023-01-26 17:51, Jagan Teki wrote:
> Hi Jonas,
>
> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> Hi Jagan,
>>
>> On 2023-01-25 23:27, Jagan Teki wrote:
>>> This series support Rockchip RK3588. All the device tree files are
>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>> messages.
>>>
>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>> it is failing to load ATF entry from SPL and hang.
>>>
>>> Verified below BL31 versions,
>>> bl31-v1.15
>>> bl31-v1.21
>>> bl31-v1.22
>>> bl31-v1.23
>>> bl31-v1.24
>>> bl31-v1.25
>>> bl31-v1.26
>>>
>>> Rever-engineered with respect to rockchip u-boot by using the same
>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>>> mainline showing the same issue.
>>>
>>> Log:
>>>
>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> change to F1: 528MHz
>>> change to F2: 1068MHz
>>> change to F3: 1560MHz
>>> change to F0: 2112MHz
>>> out
>>>
>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>>> Trying to boot from MMC1
>>> bl31_entry: atf_entry start
>>> << hang >>
>>>
>>> Any information on BL31 for RK3588 please share.
>>
>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
>> turned out to be related to all parts of ATF not being properly loaded
>> into PMU SRAM.
>>
>> Using my series at [1] I managed to get ATF to be fully loaded into
>> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
>> the segment being loaded ended up corrupted.
>>
>> The use of 512 bytes alignment of the FIT helped mitigate that issue.
>> Vendor U-Boot use a bounce buffer for all parts that is written into
>> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
>>
>> You can also find newer bl31 at [2], up to version v1.32.
>>
>> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> Thanks for the details. I did apply this set on the master. No change
> in the behavior, used BL31 and ddr from [2] as well as in
> rkbin/master.
I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
and it looked like it failed to read data into memory, see below.
It also looks like the sdhci compatible is not supported by the driver.
Something that may need to be added to driver to properly read data?
DDR V1.09 a930779e06 typ 22/11/21-17:50:56
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
Trying to boot from MMC1
## Checking hash(es) for config config_1 ... OK
## Checking hash(es) for Image atf_1 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf_1' image node
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
## Checking hash(es) for config config_1 ... OK
## Checking hash(es) for Image atf_1 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf_1' image node
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Regards,
Jonas
>
> Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 16:58 ` Jonas Karlman
@ 2023-01-26 17:42 ` Jagan Teki
2023-01-26 18:01 ` Jagan Teki
2023-01-26 18:04 ` Simon Glass
0 siblings, 2 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-26 17:42 UTC (permalink / raw)
To: Jonas Karlman
Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Jagan,
> On 2023-01-26 17:51, Jagan Teki wrote:
> > Hi Jonas,
> >
> > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On 2023-01-25 23:27, Jagan Teki wrote:
> >>> This series support Rockchip RK3588. All the device tree files are
> >>> synced from linux-next with the proper SHA1 mentioned in the commit
> >>> messages.
> >>>
> >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> >>> it is failing to load ATF entry from SPL and hang.
> >>>
> >>> Verified below BL31 versions,
> >>> bl31-v1.15
> >>> bl31-v1.21
> >>> bl31-v1.22
> >>> bl31-v1.23
> >>> bl31-v1.24
> >>> bl31-v1.25
> >>> bl31-v1.26
> >>>
> >>> Rever-engineered with respect to rockchip u-boot by using the same
> >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> >>> mainline showing the same issue.
> >>>
> >>> Log:
> >>>
> >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>> change to F1: 528MHz
> >>> change to F2: 1068MHz
> >>> change to F3: 1560MHz
> >>> change to F0: 2112MHz
> >>> out
> >>>
> >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> >>> Trying to boot from MMC1
> >>> bl31_entry: atf_entry start
> >>> << hang >>
> >>>
> >>> Any information on BL31 for RK3588 please share.
> >>
> >> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> >> turned out to be related to all parts of ATF not being properly loaded
> >> into PMU SRAM.
> >>
> >> Using my series at [1] I managed to get ATF to be fully loaded into
> >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> >> the segment being loaded ended up corrupted.
> >>
> >> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> >> Vendor U-Boot use a bounce buffer for all parts that is written into
> >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> >>
> >> You can also find newer bl31 at [2], up to version v1.32.
> >>
> >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> > Thanks for the details. I did apply this set on the master. No change
> > in the behavior, used BL31 and ddr from [2] as well as in
> > rkbin/master.
>
> I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> and it looked like it failed to read data into memory, see below.
>
> It also looks like the sdhci compatible is not supported by the driver.
> Something that may need to be added to driver to properly read data?
>
>
> DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> LPDDR4X, 2112MHz
> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> Manufacturer ID:0x6
> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> change to F1: 528MHz
> change to F2: 1068MHz
> change to F3: 1560MHz
> change to F0: 2112MHz
> out
>
> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> Trying to boot from MMC1
> ## Checking hash(es) for config config_1 ... OK
> ## Checking hash(es) for Image atf_1 ... sha256 error!
> Bad hash value for 'hash' hash node in 'atf_1' image node
> mmc_load_image_raw_sector: mmc block read error
> Trying to boot from MMC1
> ## Checking hash(es) for config config_1 ... OK
> ## Checking hash(es) for Image atf_1 ... sha256 error!
> Bad hash value for 'hash' hash node in 'atf_1' image node
Look like this is something wrong with your patch series or master
changes on binman, not with the driver. I have observed the same if I
enable CONFIG_SPL_FIT_SIGNATURE.
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 17:42 ` Jagan Teki
@ 2023-01-26 18:01 ` Jagan Teki
2023-01-26 18:04 ` Simon Glass
1 sibling, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-26 18:01 UTC (permalink / raw)
To: Jonas Karlman
Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
On Thu, 26 Jan 2023 at 23:12, Jagan Teki <jagan@edgeble.ai> wrote:
>
> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> >
> > Hi Jagan,
> > On 2023-01-26 17:51, Jagan Teki wrote:
> > > Hi Jonas,
> > >
> > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> > >>
> > >> Hi Jagan,
> > >>
> > >> On 2023-01-25 23:27, Jagan Teki wrote:
> > >>> This series support Rockchip RK3588. All the device tree files are
> > >>> synced from linux-next with the proper SHA1 mentioned in the commit
> > >>> messages.
> > >>>
> > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> > >>> it is failing to load ATF entry from SPL and hang.
> > >>>
> > >>> Verified below BL31 versions,
> > >>> bl31-v1.15
> > >>> bl31-v1.21
> > >>> bl31-v1.22
> > >>> bl31-v1.23
> > >>> bl31-v1.24
> > >>> bl31-v1.25
> > >>> bl31-v1.26
> > >>>
> > >>> Rever-engineered with respect to rockchip u-boot by using the same
> > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> > >>> mainline showing the same issue.
> > >>>
> > >>> Log:
> > >>>
> > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> change to F1: 528MHz
> > >>> change to F2: 1068MHz
> > >>> change to F3: 1560MHz
> > >>> change to F0: 2112MHz
> > >>> out
> > >>>
> > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> > >>> Trying to boot from MMC1
> > >>> bl31_entry: atf_entry start
> > >>> << hang >>
> > >>>
> > >>> Any information on BL31 for RK3588 please share.
> > >>
> > >> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> > >> turned out to be related to all parts of ATF not being properly loaded
> > >> into PMU SRAM.
> > >>
> > >> Using my series at [1] I managed to get ATF to be fully loaded into
> > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> > >> the segment being loaded ended up corrupted.
> > >>
> > >> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> > >> Vendor U-Boot use a bounce buffer for all parts that is written into
> > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> > >>
> > >> You can also find newer bl31 at [2], up to version v1.32.
> > >>
> > >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> > > Thanks for the details. I did apply this set on the master. No change
> > > in the behavior, used BL31 and ddr from [2] as well as in
> > > rkbin/master.
> >
> > I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> > and it looked like it failed to read data into memory, see below.
> >
> > It also looks like the sdhci compatible is not supported by the driver.
> > Something that may need to be added to driver to properly read data?
> >
> >
> > DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> > LPDDR4X, 2112MHz
> > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > Manufacturer ID:0x6
> > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> > change to F1: 528MHz
> > change to F2: 1068MHz
> > change to F3: 1560MHz
> > change to F0: 2112MHz
> > out
> >
> > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config_1 ... OK
> > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > Bad hash value for 'hash' hash node in 'atf_1' image node
> > mmc_load_image_raw_sector: mmc block read error
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config_1 ... OK
> > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > Bad hash value for 'hash' hash node in 'atf_1' image node
>
> Look like this is something wrong with your patch series or master
> changes on binman, not with the driver. I have observed the same if I
> enable CONFIG_SPL_FIT_SIGNATURE.
Do you have a repo where it worked before with CONFIG_SPL_FIT_SIGNATURE?
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 17:42 ` Jagan Teki
2023-01-26 18:01 ` Jagan Teki
@ 2023-01-26 18:04 ` Simon Glass
2023-01-26 18:26 ` Jagan Teki
1 sibling, 1 reply; 56+ messages in thread
From: Simon Glass @ 2023-01-26 18:04 UTC (permalink / raw)
To: Jagan Teki
Cc: Jonas Karlman, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
Hi Jagan,
On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>
> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> >
> > Hi Jagan,
> > On 2023-01-26 17:51, Jagan Teki wrote:
> > > Hi Jonas,
> > >
> > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> > >>
> > >> Hi Jagan,
> > >>
> > >> On 2023-01-25 23:27, Jagan Teki wrote:
> > >>> This series support Rockchip RK3588. All the device tree files are
> > >>> synced from linux-next with the proper SHA1 mentioned in the commit
> > >>> messages.
> > >>>
> > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> > >>> it is failing to load ATF entry from SPL and hang.
> > >>>
> > >>> Verified below BL31 versions,
> > >>> bl31-v1.15
> > >>> bl31-v1.21
> > >>> bl31-v1.22
> > >>> bl31-v1.23
> > >>> bl31-v1.24
> > >>> bl31-v1.25
> > >>> bl31-v1.26
> > >>>
> > >>> Rever-engineered with respect to rockchip u-boot by using the same
> > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> > >>> mainline showing the same issue.
> > >>>
> > >>> Log:
> > >>>
> > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > >>> change to F1: 528MHz
> > >>> change to F2: 1068MHz
> > >>> change to F3: 1560MHz
> > >>> change to F0: 2112MHz
> > >>> out
> > >>>
> > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> > >>> Trying to boot from MMC1
> > >>> bl31_entry: atf_entry start
> > >>> << hang >>
> > >>>
> > >>> Any information on BL31 for RK3588 please share.
> > >>
> > >> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> > >> turned out to be related to all parts of ATF not being properly loaded
> > >> into PMU SRAM.
> > >>
> > >> Using my series at [1] I managed to get ATF to be fully loaded into
> > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> > >> the segment being loaded ended up corrupted.
> > >>
> > >> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> > >> Vendor U-Boot use a bounce buffer for all parts that is written into
> > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> > >>
> > >> You can also find newer bl31 at [2], up to version v1.32.
> > >>
> > >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> > > Thanks for the details. I did apply this set on the master. No change
> > > in the behavior, used BL31 and ddr from [2] as well as in
> > > rkbin/master.
> >
> > I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> > and it looked like it failed to read data into memory, see below.
> >
> > It also looks like the sdhci compatible is not supported by the driver.
> > Something that may need to be added to driver to properly read data?
> >
> >
> > DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> > LPDDR4X, 2112MHz
> > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > Manufacturer ID:0x6
> > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> > change to F1: 528MHz
> > change to F2: 1068MHz
> > change to F3: 1560MHz
> > change to F0: 2112MHz
> > out
> >
> > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config_1 ... OK
> > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > Bad hash value for 'hash' hash node in 'atf_1' image node
> > mmc_load_image_raw_sector: mmc block read error
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config_1 ... OK
> > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > Bad hash value for 'hash' hash node in 'atf_1' image node
>
> Look like this is something wrong with your patch series or master
> changes on binman, not with the driver. I have observed the same if I
> enable CONFIG_SPL_FIT_SIGNATURE.
There are some more changes in dm/master that I'm about to pull in.
One of them from Jonas Karlman adds hash nodes so may be involved.
Regards,
Simon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 18:04 ` Simon Glass
@ 2023-01-26 18:26 ` Jagan Teki
2023-01-26 19:03 ` Jonas Karlman
2023-01-26 19:14 ` Simon Glass
0 siblings, 2 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-26 18:26 UTC (permalink / raw)
To: Simon Glass, Jonas Karlman
Cc: Kever Yang, Philipp Tomsich, fatorangecat, u-boot
Hi Simon,
On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Jagan,
>
> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> >
> > On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> > >
> > > Hi Jagan,
> > > On 2023-01-26 17:51, Jagan Teki wrote:
> > > > Hi Jonas,
> > > >
> > > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> > > >>
> > > >> Hi Jagan,
> > > >>
> > > >> On 2023-01-25 23:27, Jagan Teki wrote:
> > > >>> This series support Rockchip RK3588. All the device tree files are
> > > >>> synced from linux-next with the proper SHA1 mentioned in the commit
> > > >>> messages.
> > > >>>
> > > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> > > >>> it is failing to load ATF entry from SPL and hang.
> > > >>>
> > > >>> Verified below BL31 versions,
> > > >>> bl31-v1.15
> > > >>> bl31-v1.21
> > > >>> bl31-v1.22
> > > >>> bl31-v1.23
> > > >>> bl31-v1.24
> > > >>> bl31-v1.25
> > > >>> bl31-v1.26
> > > >>>
> > > >>> Rever-engineered with respect to rockchip u-boot by using the same
> > > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> > > >>> mainline showing the same issue.
> > > >>>
> > > >>> Log:
> > > >>>
> > > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> > > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > >>> change to F1: 528MHz
> > > >>> change to F2: 1068MHz
> > > >>> change to F3: 1560MHz
> > > >>> change to F0: 2112MHz
> > > >>> out
> > > >>>
> > > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> > > >>> Trying to boot from MMC1
> > > >>> bl31_entry: atf_entry start
> > > >>> << hang >>
> > > >>>
> > > >>> Any information on BL31 for RK3588 please share.
> > > >>
> > > >> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> > > >> turned out to be related to all parts of ATF not being properly loaded
> > > >> into PMU SRAM.
> > > >>
> > > >> Using my series at [1] I managed to get ATF to be fully loaded into
> > > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> > > >> the segment being loaded ended up corrupted.
> > > >>
> > > >> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> > > >> Vendor U-Boot use a bounce buffer for all parts that is written into
> > > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> > > >>
> > > >> You can also find newer bl31 at [2], up to version v1.32.
> > > >>
> > > >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> > > > Thanks for the details. I did apply this set on the master. No change
> > > > in the behavior, used BL31 and ddr from [2] as well as in
> > > > rkbin/master.
> > >
> > > I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> > > and it looked like it failed to read data into memory, see below.
> > >
> > > It also looks like the sdhci compatible is not supported by the driver.
> > > Something that may need to be added to driver to properly read data?
> > >
> > >
> > > DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> > > LPDDR4X, 2112MHz
> > > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > Manufacturer ID:0x6
> > > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> > > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> > > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> > > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> > > change to F1: 528MHz
> > > change to F2: 1068MHz
> > > change to F3: 1560MHz
> > > change to F0: 2112MHz
> > > out
> > >
> > > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> > > Trying to boot from MMC1
> > > ## Checking hash(es) for config config_1 ... OK
> > > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > > Bad hash value for 'hash' hash node in 'atf_1' image node
> > > mmc_load_image_raw_sector: mmc block read error
> > > Trying to boot from MMC1
> > > ## Checking hash(es) for config config_1 ... OK
> > > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > > Bad hash value for 'hash' hash node in 'atf_1' image node
> >
> > Look like this is something wrong with your patch series or master
> > changes on binman, not with the driver. I have observed the same if I
> > enable CONFIG_SPL_FIT_SIGNATURE.
>
> There are some more changes in dm/master that I'm about to pull in.
> One of them from Jonas Karlman adds hash nodes so may be involved.
I found the same issue on the dm/master
U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-1' image node
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 18:26 ` Jagan Teki
@ 2023-01-26 19:03 ` Jonas Karlman
2023-01-26 19:17 ` Jagan Teki
2023-01-26 19:14 ` Simon Glass
1 sibling, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-01-26 19:03 UTC (permalink / raw)
To: Jagan Teki, Simon Glass; +Cc: Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 2023-01-26 19:26, Jagan Teki wrote:
> Hi Simon,
>
> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>
>> Hi Jagan,
>>
>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>
>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>
>>>> Hi Jagan,
>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>> Hi Jonas,
>>>>>
>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>
>>>>>> Hi Jagan,
>>>>>>
>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>> messages.
>>>>>>>
>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>
>>>>>>> Verified below BL31 versions,
>>>>>>> bl31-v1.15
>>>>>>> bl31-v1.21
>>>>>>> bl31-v1.22
>>>>>>> bl31-v1.23
>>>>>>> bl31-v1.24
>>>>>>> bl31-v1.25
>>>>>>> bl31-v1.26
>>>>>>>
>>>>>>> Rever-engineered with respect to rockchip u-boot by using the same
>>>>>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>>>>>>> mainline showing the same issue.
>>>>>>>
>>>>>>> Log:
>>>>>>>
>>>>>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>>>>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>> change to F1: 528MHz
>>>>>>> change to F2: 1068MHz
>>>>>>> change to F3: 1560MHz
>>>>>>> change to F0: 2112MHz
>>>>>>> out
>>>>>>>
>>>>>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>>>>>>> Trying to boot from MMC1
>>>>>>> bl31_entry: atf_entry start
>>>>>>> << hang >>
>>>>>>>
>>>>>>> Any information on BL31 for RK3588 please share.
>>>>>>
>>>>>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
>>>>>> turned out to be related to all parts of ATF not being properly loaded
>>>>>> into PMU SRAM.
>>>>>>
>>>>>> Using my series at [1] I managed to get ATF to be fully loaded into
>>>>>> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
>>>>>> the segment being loaded ended up corrupted.
>>>>>>
>>>>>> The use of 512 bytes alignment of the FIT helped mitigate that issue.
>>>>>> Vendor U-Boot use a bounce buffer for all parts that is written into
>>>>>> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
>>>>>>
>>>>>> You can also find newer bl31 at [2], up to version v1.32.
>>>>>>
>>>>>> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>>>>> Thanks for the details. I did apply this set on the master. No change
>>>>> in the behavior, used BL31 and ddr from [2] as well as in
>>>>> rkbin/master.
>>>>
>>>> I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
>>>> and it looked like it failed to read data into memory, see below.
>>>>
>>>> It also looks like the sdhci compatible is not supported by the driver.
>>>> Something that may need to be added to driver to properly read data?
>>>>
>>>>
>>>> DDR V1.09 a930779e06 typ 22/11/21-17:50:56
>>>> LPDDR4X, 2112MHz
>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>> Manufacturer ID:0x6
>>>> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
>>>> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
>>>> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
>>>> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
>>>> change to F1: 528MHz
>>>> change to F2: 1068MHz
>>>> change to F3: 1560MHz
>>>> change to F0: 2112MHz
>>>> out
>>>>
>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
>>>> Trying to boot from MMC1
>>>> ## Checking hash(es) for config config_1 ... OK
>>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
>>>> Bad hash value for 'hash' hash node in 'atf_1' image node
>>>> mmc_load_image_raw_sector: mmc block read error
>>>> Trying to boot from MMC1
>>>> ## Checking hash(es) for config config_1 ... OK
>>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
>>>> Bad hash value for 'hash' hash node in 'atf_1' image node
>>>
>>> Look like this is something wrong with your patch series or master
>>> changes on binman, not with the driver. I have observed the same if I
>>> enable CONFIG_SPL_FIT_SIGNATURE.
>>
>> There are some more changes in dm/master that I'm about to pull in.
>> One of them from Jonas Karlman adds hash nodes so may be involved.
>
> I found the same issue on the dm/master
>
> U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
> Trying to boot from MMC1
> ## Checking hash(es) for config config-1 ... OK
> ## Checking hash(es) for Image atf-1 ... sha256 error!
> Bad hash value for 'hash' hash node in 'atf-1' image node
> mmc_load_image_raw_sector: mmc block read error
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
On my RK3568 ROCK 3A board this is working correctly, see below.
This was using u-boot master 17e8e58fe62c019b2cc26af221b6defc3368229f
with a few patches on top, see [1].
-------------
U-Boot SPL 2023.01 (Jan 26 2023 - 18:29:56 +0000)
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
## Checking hash(es) for Image atf-4 ... sha256+ OK
## Checking hash(es) for Image atf-5 ... sha256+ OK
## Checking hash(es) for Image atf-6 ... sha256+ OK
INFO: Preloader serial: 2
NOTICE: BL31: v2.3():v2.3-460-g2c8be93f9:huan.he
NOTICE: BL31: Built : 19:45:17, Nov 8 2022
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: pmu v1 is valid 220114
INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz
INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0xa00000
INFO: SPSR = 0x3c9
U-Boot 2023.01 (Jan 26 2023 - 18:29:56 +0000)
Model: Rockchip RK3568 EVB1 DDR4 V10 Board
DRAM: 8 GiB (effective 7.7 GiB)
Core: 58 devices, 17 uclasses, devicetree: separate
MMC: mmc@fe2b0000: 1, mmc@fe310000: 0
...
-------------
However, on my RK3588 ROCK 5B device I get a similar error you get.
Seems to be the mmc reading that times out all of sudden.
It can read the FIP and config, and then some mmc command/transfer times out.
See below for details with LOG_DEBUG defined at top of include/log.h
This was trying to boot from a SD-card, trying to use eMMC fails earlier.
Because there is no driver for emmc compatible, SPL only tries to boot from SD-card.
I believe this is related to your << hang >>, reading atf
from mmc fails in the background and there is no error message.
That is why I suggested trying with CONFIG_SPL_FIT_SIGNATURE=y,
to see if there is any hidden issue trying to load ATF.
-------------
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
-------------
Trying to boot from MMC1
0
- 0 'mmc@fe2c0000'
- found
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD2
Sending CMD3
Sending CMD9
Sending CMD7
Sending CMD55
Sending CMD51
Sending CMD6
Sending CMD55
Sending CMD6
Buswidth = 4, clock: 400000
Sending CMD6
clock is enabled (50000000Hz)
Buswidth = 4, clock: 50000000
clk_set_rate(clk=500000, rate=50000000)
rockchip_dwmmc_get_mmc_clk: err=-2
spl: mmc boot mode: raw
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
Sending CMD17
hdr read sector 4000, count=1
Found FIT
size=a00, ptr=ac0, limit=100000: aligned to 5000c0
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
Sending CMD18
Sending CMD12
fit read sector 4000, sectors=5, dst=5000c0, count=5, size=0xa00
Selecting default config 'rk3588-evb.dtb'
## Checking hash(es) for config config-1 ... fit_config_verify_required_keys: No signature node found: FDT_ERR_NOTFOUND
OK
firmware: 'atf-1'
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
Sending CMD18
dwmci_data_transfer: Timeout waiting for data!
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
Trying to boot from MMC1
0
- 0 'mmc@fe2c0000'
- found
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
spl: mmc boot mode: raw
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
dwmci_send_cmd: Response Timeout.
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
-------------
[1] https://github.com/Kwiboo/u-boot-rockchip/compare/17e8e58fe62c019b2cc26af221b6defc3368229f...123bee8cb2229ebae35810371827d2b73b71248b
Regards,
Jonas
>
> Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 18:26 ` Jagan Teki
2023-01-26 19:03 ` Jonas Karlman
@ 2023-01-26 19:14 ` Simon Glass
2023-01-26 19:35 ` Jagan Teki
1 sibling, 1 reply; 56+ messages in thread
From: Simon Glass @ 2023-01-26 19:14 UTC (permalink / raw)
To: Jagan Teki
Cc: Jonas Karlman, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
Hi Jagan,
On Thu, 26 Jan 2023 at 11:27, Jagan Teki <jagan@edgeble.ai> wrote:
>
> Hi Simon,
>
> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Jagan,
> >
> > On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> > >
> > > On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> > > >
> > > > Hi Jagan,
> > > > On 2023-01-26 17:51, Jagan Teki wrote:
> > > > > Hi Jonas,
> > > > >
> > > > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> > > > >>
> > > > >> Hi Jagan,
> > > > >>
> > > > >> On 2023-01-25 23:27, Jagan Teki wrote:
> > > > >>> This series support Rockchip RK3588. All the device tree files are
> > > > >>> synced from linux-next with the proper SHA1 mentioned in the commit
> > > > >>> messages.
> > > > >>>
> > > > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> > > > >>> it is failing to load ATF entry from SPL and hang.
> > > > >>>
> > > > >>> Verified below BL31 versions,
> > > > >>> bl31-v1.15
> > > > >>> bl31-v1.21
> > > > >>> bl31-v1.22
> > > > >>> bl31-v1.23
> > > > >>> bl31-v1.24
> > > > >>> bl31-v1.25
> > > > >>> bl31-v1.26
> > > > >>>
> > > > >>> Rever-engineered with respect to rockchip u-boot by using the same
> > > > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> > > > >>> mainline showing the same issue.
> > > > >>>
> > > > >>> Log:
> > > > >>>
> > > > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> > > > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > >>> change to F1: 528MHz
> > > > >>> change to F2: 1068MHz
> > > > >>> change to F3: 1560MHz
> > > > >>> change to F0: 2112MHz
> > > > >>> out
> > > > >>>
> > > > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> > > > >>> Trying to boot from MMC1
> > > > >>> bl31_entry: atf_entry start
> > > > >>> << hang >>
> > > > >>>
> > > > >>> Any information on BL31 for RK3588 please share.
> > > > >>
> > > > >> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> > > > >> turned out to be related to all parts of ATF not being properly loaded
> > > > >> into PMU SRAM.
> > > > >>
> > > > >> Using my series at [1] I managed to get ATF to be fully loaded into
> > > > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> > > > >> the segment being loaded ended up corrupted.
> > > > >>
> > > > >> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> > > > >> Vendor U-Boot use a bounce buffer for all parts that is written into
> > > > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> > > > >>
> > > > >> You can also find newer bl31 at [2], up to version v1.32.
> > > > >>
> > > > >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> > > > > Thanks for the details. I did apply this set on the master. No change
> > > > > in the behavior, used BL31 and ddr from [2] as well as in
> > > > > rkbin/master.
> > > >
> > > > I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> > > > and it looked like it failed to read data into memory, see below.
> > > >
> > > > It also looks like the sdhci compatible is not supported by the driver.
> > > > Something that may need to be added to driver to properly read data?
> > > >
> > > >
> > > > DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> > > > LPDDR4X, 2112MHz
> > > > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > Manufacturer ID:0x6
> > > > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> > > > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> > > > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> > > > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> > > > change to F1: 528MHz
> > > > change to F2: 1068MHz
> > > > change to F3: 1560MHz
> > > > change to F0: 2112MHz
> > > > out
> > > >
> > > > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> > > > Trying to boot from MMC1
> > > > ## Checking hash(es) for config config_1 ... OK
> > > > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > > > Bad hash value for 'hash' hash node in 'atf_1' image node
> > > > mmc_load_image_raw_sector: mmc block read error
> > > > Trying to boot from MMC1
> > > > ## Checking hash(es) for config config_1 ... OK
> > > > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > > > Bad hash value for 'hash' hash node in 'atf_1' image node
> > >
> > > Look like this is something wrong with your patch series or master
> > > changes on binman, not with the driver. I have observed the same if I
> > > enable CONFIG_SPL_FIT_SIGNATURE.
> >
> > There are some more changes in dm/master that I'm about to pull in.
> > One of them from Jonas Karlman adds hash nodes so may be involved.
>
> I found the same issue on the dm/master
>
> U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
> Trying to boot from MMC1
> ## Checking hash(es) for config config-1 ... OK
> ## Checking hash(es) for Image atf-1 ... sha256 error!
> Bad hash value for 'hash' hash node in 'atf-1' image node
> mmc_load_image_raw_sector: mmc block read error
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
Is the FIT image broken? You can use check_sign or dump_image to see.
Regards,
Simon
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 19:03 ` Jonas Karlman
@ 2023-01-26 19:17 ` Jagan Teki
2023-01-26 22:16 ` Jonas Karlman
0 siblings, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-26 19:17 UTC (permalink / raw)
To: Jonas Karlman
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> On 2023-01-26 19:26, Jagan Teki wrote:
> > Hi Simon,
> >
> > On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> >>>
> >>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>
> >>>> Hi Jagan,
> >>>> On 2023-01-26 17:51, Jagan Teki wrote:
> >>>>> Hi Jonas,
> >>>>>
> >>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>
> >>>>>> Hi Jagan,
> >>>>>>
> >>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
> >>>>>>> This series support Rockchip RK3588. All the device tree files are
> >>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
> >>>>>>> messages.
> >>>>>>>
> >>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> >>>>>>> it is failing to load ATF entry from SPL and hang.
> >>>>>>>
> >>>>>>> Verified below BL31 versions,
> >>>>>>> bl31-v1.15
> >>>>>>> bl31-v1.21
> >>>>>>> bl31-v1.22
> >>>>>>> bl31-v1.23
> >>>>>>> bl31-v1.24
> >>>>>>> bl31-v1.25
> >>>>>>> bl31-v1.26
> >>>>>>>
> >>>>>>> Rever-engineered with respect to rockchip u-boot by using the same
> >>>>>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> >>>>>>> mainline showing the same issue.
> >>>>>>>
> >>>>>>> Log:
> >>>>>>>
> >>>>>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> >>>>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>>>>> change to F1: 528MHz
> >>>>>>> change to F2: 1068MHz
> >>>>>>> change to F3: 1560MHz
> >>>>>>> change to F0: 2112MHz
> >>>>>>> out
> >>>>>>>
> >>>>>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> >>>>>>> Trying to boot from MMC1
> >>>>>>> bl31_entry: atf_entry start
> >>>>>>> << hang >>
> >>>>>>>
> >>>>>>> Any information on BL31 for RK3588 please share.
> >>>>>>
> >>>>>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> >>>>>> turned out to be related to all parts of ATF not being properly loaded
> >>>>>> into PMU SRAM.
> >>>>>>
> >>>>>> Using my series at [1] I managed to get ATF to be fully loaded into
> >>>>>> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> >>>>>> the segment being loaded ended up corrupted.
> >>>>>>
> >>>>>> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> >>>>>> Vendor U-Boot use a bounce buffer for all parts that is written into
> >>>>>> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> >>>>>>
> >>>>>> You can also find newer bl31 at [2], up to version v1.32.
> >>>>>>
> >>>>>> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>>>>> Thanks for the details. I did apply this set on the master. No change
> >>>>> in the behavior, used BL31 and ddr from [2] as well as in
> >>>>> rkbin/master.
> >>>>
> >>>> I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> >>>> and it looked like it failed to read data into memory, see below.
> >>>>
> >>>> It also looks like the sdhci compatible is not supported by the driver.
> >>>> Something that may need to be added to driver to properly read data?
> >>>>
> >>>>
> >>>> DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> >>>> LPDDR4X, 2112MHz
> >>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> >>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> >>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> >>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> >>>> Manufacturer ID:0x6
> >>>> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> >>>> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> >>>> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> >>>> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> >>>> change to F1: 528MHz
> >>>> change to F2: 1068MHz
> >>>> change to F3: 1560MHz
> >>>> change to F0: 2112MHz
> >>>> out
> >>>>
> >>>> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> >>>> Trying to boot from MMC1
> >>>> ## Checking hash(es) for config config_1 ... OK
> >>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
> >>>> Bad hash value for 'hash' hash node in 'atf_1' image node
> >>>> mmc_load_image_raw_sector: mmc block read error
> >>>> Trying to boot from MMC1
> >>>> ## Checking hash(es) for config config_1 ... OK
> >>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
> >>>> Bad hash value for 'hash' hash node in 'atf_1' image node
> >>>
> >>> Look like this is something wrong with your patch series or master
> >>> changes on binman, not with the driver. I have observed the same if I
> >>> enable CONFIG_SPL_FIT_SIGNATURE.
> >>
> >> There are some more changes in dm/master that I'm about to pull in.
> >> One of them from Jonas Karlman adds hash nodes so may be involved.
> >
> > I found the same issue on the dm/master
> >
> > U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config-1 ... OK
> > ## Checking hash(es) for Image atf-1 ... sha256 error!
> > Bad hash value for 'hash' hash node in 'atf-1' image node
> > mmc_load_image_raw_sector: mmc block read error
> > SPL: failed to boot from all boot devices
> > ### ERROR ### Please RESET the board ###
>
> On my RK3568 ROCK 3A board this is working correctly, see below.
>
> This was using u-boot master 17e8e58fe62c019b2cc26af221b6defc3368229f
> with a few patches on top, see [1].
>
> -------------
> U-Boot SPL 2023.01 (Jan 26 2023 - 18:29:56 +0000)
> Trying to boot from MMC1
> ## Checking hash(es) for config config-1 ... OK
> ## Checking hash(es) for Image atf-1 ... sha256+ OK
> ## Checking hash(es) for Image u-boot ... sha256+ OK
> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
> ## Checking hash(es) for Image atf-2 ... sha256+ OK
> ## Checking hash(es) for Image atf-3 ... sha256+ OK
> ## Checking hash(es) for Image atf-4 ... sha256+ OK
> ## Checking hash(es) for Image atf-5 ... sha256+ OK
> ## Checking hash(es) for Image atf-6 ... sha256+ OK
> INFO: Preloader serial: 2
> NOTICE: BL31: v2.3():v2.3-460-g2c8be93f9:huan.he
> NOTICE: BL31: Built : 19:45:17, Nov 8 2022
> INFO: GICv3 without legacy support detected.
> INFO: ARM GICv3 driver initialized in EL3
> INFO: pmu v1 is valid 220114
> INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz
> INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz
> INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz
> INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz
> INFO: Using opteed sec cpu_context!
> INFO: boot cpu mask: 0
> INFO: BL31: Initializing runtime services
> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
> ERROR: Error initializing runtime service opteed_fast
> INFO: BL31: Preparing for EL3 exit to normal world
> INFO: Entry point address = 0xa00000
> INFO: SPSR = 0x3c9
>
>
> U-Boot 2023.01 (Jan 26 2023 - 18:29:56 +0000)
>
> Model: Rockchip RK3568 EVB1 DDR4 V10 Board
> DRAM: 8 GiB (effective 7.7 GiB)
> Core: 58 devices, 17 uclasses, devicetree: separate
> MMC: mmc@fe2b0000: 1, mmc@fe310000: 0
> ...
> -------------
>
> However, on my RK3588 ROCK 5B device I get a similar error you get.
> Seems to be the mmc reading that times out all of sudden.
>
> It can read the FIP and config, and then some mmc command/transfer times out.
> See below for details with LOG_DEBUG defined at top of include/log.h
>
> This was trying to boot from a SD-card, trying to use eMMC fails earlier.
> Because there is no driver for emmc compatible, SPL only tries to boot from SD-card.
>
> I believe this is related to your << hang >>, reading atf
> from mmc fails in the background and there is no error message.
>
> That is why I suggested trying with CONFIG_SPL_FIT_SIGNATURE=y,
> to see if there is any hidden issue trying to load ATF.
>
> -------------
> Trying to boot from MMC1
> ## Checking hash(es) for config config-1 ... OK
> mmc_load_image_raw_sector: mmc block read error
> Trying to boot from MMC1
> mmc_load_image_raw_sector: mmc block read error
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
> -------------
> Trying to boot from MMC1
> 0
> - 0 'mmc@fe2c0000'
> - found
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> clock is disabled (0Hz)
> Buswidth = 0, clock: 0
> Buswidth = 1, clock: 0
> clock is enabled (400000Hz)
> Buswidth = 1, clock: 400000
> Sending CMD0
> Sending CMD8
> Sending CMD55
> Sending CMD41
> Sending CMD55
> Sending CMD41
> Sending CMD2
> Sending CMD3
> Sending CMD9
> Sending CMD7
> Sending CMD55
> Sending CMD51
> Sending CMD6
> Sending CMD55
> Sending CMD6
> Buswidth = 4, clock: 400000
> Sending CMD6
> clock is enabled (50000000Hz)
> Buswidth = 4, clock: 50000000
> clk_set_rate(clk=500000, rate=50000000)
> rockchip_dwmmc_get_mmc_clk: err=-2
> spl: mmc boot mode: raw
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> Sending CMD17
> hdr read sector 4000, count=1
> Found FIT
> size=a00, ptr=ac0, limit=100000: aligned to 5000c0
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> Sending CMD18
> Sending CMD12
> fit read sector 4000, sectors=5, dst=5000c0, count=5, size=0xa00
> Selecting default config 'rk3588-evb.dtb'
> ## Checking hash(es) for config config-1 ... fit_config_verify_required_keys: No signature node found: FDT_ERR_NOTFOUND
> OK
> firmware: 'atf-1'
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> Sending CMD18
> dwmci_data_transfer: Timeout waiting for data!
> mmc_load_image_raw_sector: mmc block read error
> spl: mmc boot mode: fs
> Trying to boot from MMC1
> 0
> - 0 'mmc@fe2c0000'
> - found
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> spl: mmc boot mode: raw
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> dwmci_send_cmd: Response Timeout.
> hdr read sector 4000, count=0
> mmc_load_image_raw_sector: mmc block read error
> spl: mmc boot mode: fs
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
I'm thinking this is fit/binman issue rather than mmc.
U-Boot SPL 2023.01-00176-gb21fb7a9c0-dirty (Jan 27 2023 - 00:43:52 +0530)
SPL malloc() before relocation used 0xbe0 bytes (2 KB)
>>SPL: board_init_r()
spl_init
size=a0, ptr=a0, limit=100000: 500000
size=8, ptr=a8, limit=100000: 5000a0
fdtdec_get_addr_size_auto_parent: na=2, ns=2,
fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32_index: bus-width: x (4)
ofnode_read_bool: non-removable: false
ofnode_read_u32_index: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: false
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array:
clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32_index: max-frequency: x (200000000)
clk_set_defaults(mmc@fe2c0000)
clk_set_default_parents: could not read assigned-clock-parents for 3f60700
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
fdtdec_get_int: #clock-cells: x (1)
Looking for clock-controller@fd7c0000
Looking for clock-controller@fd7c0000
- checking clock-1
- checking clock-controller@fd7c0000
- result for clock-controller@fd7c0000: clock-controller@fd7c0000 (ret=0)
- result for clock-controller@fd7c0000: clock-controller@fd7c0000 (ret=0)
clk_of_xlate_default(clk=500000)
clk_request(dev=3f60320, clk=500000)
clk_set_rate(clk=500000, rate=400000)
rockchip_dwmmc_get_mmc_clk: err=-2
Trying to boot from MMC1
0
- 0 'mmc@fe2c0000'
- found
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD2
Sending CMD3
Sending CMD9
Sending CMD7
Sending CMD55
Unaligned buffer length u
size=40, ptr=100, limit=100000: aligned to 5000c0
Sending CMD51
Sending CMD6
Sending CMD55
Sending CMD6
Buswidth = 4, clock: 400000
Sending CMD6
clock is enabled (50000000Hz)
Buswidth = 4, clock: 50000000
clk_set_rate(clk=500000, rate=50000000)
rockchip_dwmmc_get_mmc_clk: err=-2
spl: mmc boot mode: raw
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
Sending CMD17
hdr read sector 4000, count=1
Found FIT
size=a00, ptr=b00, limit=100000: aligned to 500100
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
Sending CMD18
Sending CMD12
fit read sector 4000, sectors=5, dst=500100, count=5, size=0xa00
Selecting default config 'rk3588-edgeble-neu6a-io.dtb'
## Checking hash(es) for config config-1 ...
fit_config_verify_required_keys: No signature node found:
FDT_ERR_NOTFOUND
OK
firmware: 'atf-1'
blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
Sending CMD16
Sending CMD18
dwmci_data_transfer: Timeout waiting for data!
Sending CMD12
External data: dst=40000, offset=ad200, size=2e940
## Checking hash(es) for Image atf-1 ...
fit_image_verify_required_sigs: No signature node found:
FDT_ERR_NOTFOUND
sha256 error!
Bad hash value for 'hash' hash node in 'atf-1' image node
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Please check this repo, it is on top of the dm/master
https://github.com/edgeble/u-boot/tree/neu6-v1
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 19:14 ` Simon Glass
@ 2023-01-26 19:35 ` Jagan Teki
0 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-26 19:35 UTC (permalink / raw)
To: Simon Glass
Cc: Jonas Karlman, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
Hi Simon,
On Fri, 27 Jan 2023 at 00:45, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Jagan,
>
> On Thu, 26 Jan 2023 at 11:27, Jagan Teki <jagan@edgeble.ai> wrote:
> >
> > Hi Simon,
> >
> > On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Jagan,
> > >
> > > On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> > > >
> > > > On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> > > > >
> > > > > Hi Jagan,
> > > > > On 2023-01-26 17:51, Jagan Teki wrote:
> > > > > > Hi Jonas,
> > > > > >
> > > > > > On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> > > > > >>
> > > > > >> Hi Jagan,
> > > > > >>
> > > > > >> On 2023-01-25 23:27, Jagan Teki wrote:
> > > > > >>> This series support Rockchip RK3588. All the device tree files are
> > > > > >>> synced from linux-next with the proper SHA1 mentioned in the commit
> > > > > >>> messages.
> > > > > >>>
> > > > > >>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> > > > > >>> it is failing to load ATF entry from SPL and hang.
> > > > > >>>
> > > > > >>> Verified below BL31 versions,
> > > > > >>> bl31-v1.15
> > > > > >>> bl31-v1.21
> > > > > >>> bl31-v1.22
> > > > > >>> bl31-v1.23
> > > > > >>> bl31-v1.24
> > > > > >>> bl31-v1.25
> > > > > >>> bl31-v1.26
> > > > > >>>
> > > > > >>> Rever-engineered with respect to rockchip u-boot by using the same
> > > > > >>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> > > > > >>> mainline showing the same issue.
> > > > > >>>
> > > > > >>> Log:
> > > > > >>>
> > > > > >>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> > > > > >>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > > >>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > > >>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > > >>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> > > > > >>> change to F1: 528MHz
> > > > > >>> change to F2: 1068MHz
> > > > > >>> change to F3: 1560MHz
> > > > > >>> change to F0: 2112MHz
> > > > > >>> out
> > > > > >>>
> > > > > >>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> > > > > >>> Trying to boot from MMC1
> > > > > >>> bl31_entry: atf_entry start
> > > > > >>> << hang >>
> > > > > >>>
> > > > > >>> Any information on BL31 for RK3588 please share.
> > > > > >>
> > > > > >> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> > > > > >> turned out to be related to all parts of ATF not being properly loaded
> > > > > >> into PMU SRAM.
> > > > > >>
> > > > > >> Using my series at [1] I managed to get ATF to be fully loaded into
> > > > > >> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
> > > > > >> the segment being loaded ended up corrupted.
> > > > > >>
> > > > > >> The use of 512 bytes alignment of the FIT helped mitigate that issue.
> > > > > >> Vendor U-Boot use a bounce buffer for all parts that is written into
> > > > > >> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
> > > > > >>
> > > > > >> You can also find newer bl31 at [2], up to version v1.32.
> > > > > >>
> > > > > >> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891>>> [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35>>
> > > > > > Thanks for the details. I did apply this set on the master. No change
> > > > > > in the behavior, used BL31 and ddr from [2] as well as in
> > > > > > rkbin/master.
> > > > >
> > > > > I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
> > > > > and it looked like it failed to read data into memory, see below.
> > > > >
> > > > > It also looks like the sdhci compatible is not supported by the driver.
> > > > > Something that may need to be added to driver to properly read data?
> > > > >
> > > > >
> > > > > DDR V1.09 a930779e06 typ 22/11/21-17:50:56
> > > > > LPDDR4X, 2112MHz
> > > > > channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > > channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > > channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > > channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
> > > > > Manufacturer ID:0x6
> > > > > CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
> > > > > CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
> > > > > CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
> > > > > CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
> > > > > change to F1: 528MHz
> > > > > change to F2: 1068MHz
> > > > > change to F3: 1560MHz
> > > > > change to F0: 2112MHz
> > > > > out
> > > > >
> > > > > U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
> > > > > Trying to boot from MMC1
> > > > > ## Checking hash(es) for config config_1 ... OK
> > > > > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > > > > Bad hash value for 'hash' hash node in 'atf_1' image node
> > > > > mmc_load_image_raw_sector: mmc block read error
> > > > > Trying to boot from MMC1
> > > > > ## Checking hash(es) for config config_1 ... OK
> > > > > ## Checking hash(es) for Image atf_1 ... sha256 error!
> > > > > Bad hash value for 'hash' hash node in 'atf_1' image node
> > > >
> > > > Look like this is something wrong with your patch series or master
> > > > changes on binman, not with the driver. I have observed the same if I
> > > > enable CONFIG_SPL_FIT_SIGNATURE.
> > >
> > > There are some more changes in dm/master that I'm about to pull in.
> > > One of them from Jonas Karlman adds hash nodes so may be involved.
> >
> > I found the same issue on the dm/master
> >
> > U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config-1 ... OK
> > ## Checking hash(es) for Image atf-1 ... sha256 error!
> > Bad hash value for 'hash' hash node in 'atf-1' image node
> > mmc_load_image_raw_sector: mmc block read error
> > SPL: failed to boot from all boot devices
> > ### ERROR ### Please RESET the board ###
>
> Is the FIT image broken? You can use check_sign or dump_image to see.
This seems okay, let me know if you see any issue.
> ./tools/fit_check_sign -f u-boot.itb -k arch/arm/dts/rk3588-edgeble-neu6a-io.dtb
Verifying Hash Integrity for node 'config-1'... Verified OK, loading images
## Loading kernel from FIT Image at 7f98532c7000 ...
Using 'config-1' configuration
Verifying Hash Integrity ...
OK
Could not find subimage node type 'kernel'
## Loading fdt from FIT Image at 7f98532c7000 ...
Using 'config-1' configuration
Verifying Hash Integrity ...
OK
Trying 'fdt-1' fdt subimage
Description: fdt-rk3588-edgeble-neu6a-io
Created: Fri Jan 27 01:01:31 2023
Type: Flat Device Tree
Compression: uncompressed
Data Size: 41408 Bytes = 40.44 KiB = 0.04 MiB
Architecture: Unknown Architecture
Hash algo: sha256
Hash value:
a5de5505624412d216c6e985fb3669e84785b3675765bc85f08d8b0dbeffdbd7
Verifying Hash Integrity ...
sha256+
OK
Decrypting Data ...
OK
Loading Flat Device Tree
## Loading ramdisk from FIT Image at 7f98532c7000 ...
Using 'config-1' configuration
Verifying Hash Integrity ...
OK
Could not find subimage node type 'ramdisk'
Signature check OK
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 19:17 ` Jagan Teki
@ 2023-01-26 22:16 ` Jonas Karlman
2023-01-26 23:43 ` Jonas Karlman
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-01-26 22:16 UTC (permalink / raw)
To: Jagan Teki; +Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
Hi Jagan,
On 2023-01-26 20:17, Jagan Teki wrote:
> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> On 2023-01-26 19:26, Jagan Teki wrote:
>>> Hi Simon,
>>>
>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>
>>>> Hi Jagan,
>>>>
>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>
>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>
>>>>>> Hi Jagan,
>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>> Hi Jonas,
>>>>>>>
>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>
>>>>>>>> Hi Jagan,
>>>>>>>>
>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>> messages.
>>>>>>>>>
>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>
>>>>>>>>> Verified below BL31 versions,
>>>>>>>>> bl31-v1.15
>>>>>>>>> bl31-v1.21
>>>>>>>>> bl31-v1.22
>>>>>>>>> bl31-v1.23
>>>>>>>>> bl31-v1.24
>>>>>>>>> bl31-v1.25
>>>>>>>>> bl31-v1.26
>>>>>>>>>
>>>>>>>>> Rever-engineered with respect to rockchip u-boot by using the same
>>>>>>>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>>>>>>>>> mainline showing the same issue.
>>>>>>>>>
>>>>>>>>> Log:
>>>>>>>>>
>>>>>>>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>>>>>>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>> change to F1: 528MHz
>>>>>>>>> change to F2: 1068MHz
>>>>>>>>> change to F3: 1560MHz
>>>>>>>>> change to F0: 2112MHz
>>>>>>>>> out
>>>>>>>>>
>>>>>>>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>>>>>>>>> Trying to boot from MMC1
>>>>>>>>> bl31_entry: atf_entry start
>>>>>>>>> << hang >>
>>>>>>>>>
>>>>>>>>> Any information on BL31 for RK3588 please share.
>>>>>>>>
>>>>>>>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
>>>>>>>> turned out to be related to all parts of ATF not being properly loaded
>>>>>>>> into PMU SRAM.
>>>>>>>>
>>>>>>>> Using my series at [1] I managed to get ATF to be fully loaded into
>>>>>>>> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
>>>>>>>> the segment being loaded ended up corrupted.
>>>>>>>>
>>>>>>>> The use of 512 bytes alignment of the FIT helped mitigate that issue.
>>>>>>>> Vendor U-Boot use a bounce buffer for all parts that is written into
>>>>>>>> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
>>>>>>>>
>>>>>>>> You can also find newer bl31 at [2], up to version v1.32.
>>>>>>>>
>>>>>>>> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35 Thanks for the details. I did apply this set on the master. No change
>>>>>>> in the behavior, used BL31 and ddr from [2] as well as in
>>>>>>> rkbin/master.
>>>>>>
>>>>>> I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
>>>>>> and it looked like it failed to read data into memory, see below.
>>>>>>
>>>>>> It also looks like the sdhci compatible is not supported by the driver.
>>>>>> Something that may need to be added to driver to properly read data?
>>>>>>
>>>>>>
>>>>>> DDR V1.09 a930779e06 typ 22/11/21-17:50:56
>>>>>> LPDDR4X, 2112MHz
>>>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>> Manufacturer ID:0x6
>>>>>> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
>>>>>> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
>>>>>> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
>>>>>> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
>>>>>> change to F1: 528MHz
>>>>>> change to F2: 1068MHz
>>>>>> change to F3: 1560MHz
>>>>>> change to F0: 2112MHz
>>>>>> out
>>>>>>
>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
>>>>>> Trying to boot from MMC1
>>>>>> ## Checking hash(es) for config config_1 ... OK
>>>>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
>>>>>> Bad hash value for 'hash' hash node in 'atf_1' image node
>>>>>> mmc_load_image_raw_sector: mmc block read error
>>>>>> Trying to boot from MMC1
>>>>>> ## Checking hash(es) for config config_1 ... OK
>>>>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
>>>>>> Bad hash value for 'hash' hash node in 'atf_1' image node
>>>>>
>>>>> Look like this is something wrong with your patch series or master
>>>>> changes on binman, not with the driver. I have observed the same if I
>>>>> enable CONFIG_SPL_FIT_SIGNATURE.
>>>>
>>>> There are some more changes in dm/master that I'm about to pull in.
>>>> One of them from Jonas Karlman adds hash nodes so may be involved.
>>>
>>> I found the same issue on the dm/master
>>>
>>> U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
>>> Trying to boot from MMC1
>>> ## Checking hash(es) for config config-1 ... OK
>>> ## Checking hash(es) for Image atf-1 ... sha256 error!
>>> Bad hash value for 'hash' hash node in 'atf-1' image node
>>> mmc_load_image_raw_sector: mmc block read error
>>> SPL: failed to boot from all boot devices
>>> ### ERROR ### Please RESET the board ###
>>
>> On my RK3568 ROCK 3A board this is working correctly, see below.
>>
>> This was using u-boot master 17e8e58fe62c019b2cc26af221b6defc3368229f
>> with a few patches on top, see [1].
>>
>> -------------
>> U-Boot SPL 2023.01 (Jan 26 2023 - 18:29:56 +0000)
>> Trying to boot from MMC1
>> ## Checking hash(es) for config config-1 ... OK
>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>> ## Checking hash(es) for Image atf-4 ... sha256+ OK
>> ## Checking hash(es) for Image atf-5 ... sha256+ OK
>> ## Checking hash(es) for Image atf-6 ... sha256+ OK
>> INFO: Preloader serial: 2
>> NOTICE: BL31: v2.3():v2.3-460-g2c8be93f9:huan.he
>> NOTICE: BL31: Built : 19:45:17, Nov 8 2022
>> INFO: GICv3 without legacy support detected.
>> INFO: ARM GICv3 driver initialized in EL3
>> INFO: pmu v1 is valid 220114
>> INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz
>> INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz
>> INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz
>> INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz
>> INFO: Using opteed sec cpu_context!
>> INFO: boot cpu mask: 0
>> INFO: BL31: Initializing runtime services
>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>> ERROR: Error initializing runtime service opteed_fast
>> INFO: BL31: Preparing for EL3 exit to normal world
>> INFO: Entry point address = 0xa00000
>> INFO: SPSR = 0x3c9
>>
>>
>> U-Boot 2023.01 (Jan 26 2023 - 18:29:56 +0000)
>>
>> Model: Rockchip RK3568 EVB1 DDR4 V10 Board
>> DRAM: 8 GiB (effective 7.7 GiB)
>> Core: 58 devices, 17 uclasses, devicetree: separate
>> MMC: mmc@fe2b0000: 1, mmc@fe310000: 0
>> ...
>> -------------
>>
>> However, on my RK3588 ROCK 5B device I get a similar error you get.
>> Seems to be the mmc reading that times out all of sudden.
>>
>> It can read the FIP and config, and then some mmc command/transfer times out.
>> See below for details with LOG_DEBUG defined at top of include/log.h
>>
>> This was trying to boot from a SD-card, trying to use eMMC fails earlier.
>> Because there is no driver for emmc compatible, SPL only tries to boot from SD-card.
>>
>> I believe this is related to your << hang >>, reading atf
>> from mmc fails in the background and there is no error message.
>>
>> That is why I suggested trying with CONFIG_SPL_FIT_SIGNATURE=y,
>> to see if there is any hidden issue trying to load ATF.
>>
>> -------------
>> Trying to boot from MMC1
>> ## Checking hash(es) for config config-1 ... OK
>> mmc_load_image_raw_sector: mmc block read error
>> Trying to boot from MMC1
>> mmc_load_image_raw_sector: mmc block read error
>> SPL: failed to boot from all boot devices
>> ### ERROR ### Please RESET the board ###
>> -------------
>> Trying to boot from MMC1
>> 0
>> - 0 'mmc@fe2c0000'
>> - found
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> clock is disabled (0Hz)
>> Buswidth = 0, clock: 0
>> Buswidth = 1, clock: 0
>> clock is enabled (400000Hz)
>> Buswidth = 1, clock: 400000
>> Sending CMD0
>> Sending CMD8
>> Sending CMD55
>> Sending CMD41
>> Sending CMD55
>> Sending CMD41
>> Sending CMD2
>> Sending CMD3
>> Sending CMD9
>> Sending CMD7
>> Sending CMD55
>> Sending CMD51
>> Sending CMD6
>> Sending CMD55
>> Sending CMD6
>> Buswidth = 4, clock: 400000
>> Sending CMD6
>> clock is enabled (50000000Hz)
>> Buswidth = 4, clock: 50000000
>> clk_set_rate(clk=500000, rate=50000000)
>> rockchip_dwmmc_get_mmc_clk: err=-2
>> spl: mmc boot mode: raw
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> Sending CMD17
>> hdr read sector 4000, count=1
>> Found FIT
>> size=a00, ptr=ac0, limit=100000: aligned to 5000c0
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> Sending CMD18
>> Sending CMD12
>> fit read sector 4000, sectors=5, dst=5000c0, count=5, size=0xa00
>> Selecting default config 'rk3588-evb.dtb'
>> ## Checking hash(es) for config config-1 ... fit_config_verify_required_keys: No signature node found: FDT_ERR_NOTFOUND
>> OK
>> firmware: 'atf-1'
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> Sending CMD18
>> dwmci_data_transfer: Timeout waiting for data!
>> mmc_load_image_raw_sector: mmc block read error
>> spl: mmc boot mode: fs
>> Trying to boot from MMC1
>> 0
>> - 0 'mmc@fe2c0000'
>> - found
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> spl: mmc boot mode: raw
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> dwmci_send_cmd: Response Timeout.
>> hdr read sector 4000, count=0
>> mmc_load_image_raw_sector: mmc block read error
>> spl: mmc boot mode: fs
>> SPL: failed to boot from all boot devices
>> ### ERROR ### Please RESET the board ###
>
> I'm thinking this is fit/binman issue rather than mmc.
>
> U-Boot SPL 2023.01-00176-gb21fb7a9c0-dirty (Jan 27 2023 - 00:43:52 +0530)
> SPL malloc() before relocation used 0xbe0 bytes (2 KB)
>>> SPL: board_init_r()
> spl_init
> size=a0, ptr=a0, limit=100000: 500000
> size=8, ptr=a8, limit=100000: 5000a0
> fdtdec_get_addr_size_auto_parent: na=2, ns=2,
> fdtdec_get_addr_size_fixed: reg: addr=00000000x
> ofnode_read_u32_index: bus-width: x (4)
> ofnode_read_bool: non-removable: false
> ofnode_read_u32_index: fifo-depth: x (256)
> ofnode_read_bool: fifo-mode: false
> ofnode_read_bool: u-boot,spl-fifo-mode: false
> ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array:
> clock-freq-min-max
> get_prop_check_min_len: clock-freq-min-max
> ofnode_read_u32_index: max-frequency: x (200000000)
> clk_set_defaults(mmc@fe2c0000)
> clk_set_default_parents: could not read assigned-clock-parents for 3f60700
> ofnode_read_prop: assigned-clock-rates: <not found>
> fdtdec_get_int: #clock-cells: x (1)
> fdtdec_get_int: #clock-cells: x (1)
> Looking for clock-controller@fd7c0000
> Looking for clock-controller@fd7c0000
> - checking clock-1
> - checking clock-controller@fd7c0000
> - result for clock-controller@fd7c0000: clock-controller@fd7c0000 (ret=0)
> - result for clock-controller@fd7c0000: clock-controller@fd7c0000 (ret=0)
> clk_of_xlate_default(clk=500000)
> clk_request(dev=3f60320, clk=500000)
> clk_set_rate(clk=500000, rate=400000)
> rockchip_dwmmc_get_mmc_clk: err=-2
> Trying to boot from MMC1
> 0
> - 0 'mmc@fe2c0000'
> - found
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> clock is disabled (0Hz)
> Buswidth = 0, clock: 0
> Buswidth = 1, clock: 0
> clock is enabled (400000Hz)
> Buswidth = 1, clock: 400000
> Sending CMD0
> Sending CMD8
> Sending CMD55
> Sending CMD41
> Sending CMD55
> Sending CMD41
> Sending CMD55
> Sending CMD41
> Sending CMD2
> Sending CMD3
> Sending CMD9
> Sending CMD7
> Sending CMD55
> Unaligned buffer length u
> size=40, ptr=100, limit=100000: aligned to 5000c0
> Sending CMD51
> Sending CMD6
> Sending CMD55
> Sending CMD6
> Buswidth = 4, clock: 400000
> Sending CMD6
> clock is enabled (50000000Hz)
> Buswidth = 4, clock: 50000000
> clk_set_rate(clk=500000, rate=50000000)
> rockchip_dwmmc_get_mmc_clk: err=-2
> spl: mmc boot mode: raw
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> Sending CMD17
> hdr read sector 4000, count=1
> Found FIT
> size=a00, ptr=b00, limit=100000: aligned to 500100
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> Sending CMD18
> Sending CMD12
> fit read sector 4000, sectors=5, dst=500100, count=5, size=0xa00
> Selecting default config 'rk3588-edgeble-neu6a-io.dtb'
> ## Checking hash(es) for config config-1 ...
> fit_config_verify_required_keys: No signature node found:
> FDT_ERR_NOTFOUND
> OK
> firmware: 'atf-1'
> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
> Sending CMD16
> Sending CMD18
> dwmci_data_transfer: Timeout waiting for data!
> Sending CMD12
> External data: dst=40000, offset=ad200, size=2e940
> ## Checking hash(es) for Image atf-1 ...
> fit_image_verify_required_sigs: No signature node found:
> FDT_ERR_NOTFOUND
> sha256 error!
> Bad hash value for 'hash' hash node in 'atf-1' image node
> mmc_load_image_raw_sector: mmc block read error
> spl: mmc boot mode: fs
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
As you can see in the logs above there is timeout waiting for data.
I managed to find the issue and have a workaround that gets me longer
in the boot process, there still seem to be other issue with the rk3588
startup.
--------
U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
Trying to boot from MMC1
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
INFO: Preloader serial: 2
NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
NOTICE: BL31: Built : 09:59:49, Nov 21 2022
INFO: spec: 0x1
INFO: ext 32k is not valid
INFO: ddr: stride-en 4CH
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
INFO: system boots from cpu-hwid-0
INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO: BL31: Initialising Exception Handling Framework
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0xa00000
INFO: SPSR = 0x3c9
"Synchronous Abort" handler, esr 0x96000000
elr: 0000000000a23650 lr : 0000000000a24d9c
x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
x2 : 0000000000000000 x3 : 0000000000b80ff0
x4 : 0000000000b80ff0 x5 : 0000000000b80e88
x6 : 0000000000000054 x7 : 0000000000000044
x8 : 000000000000000a x9 : 0000000000000000
x10: 0000000000000034 x11: 0000000000000002
x12: 0000000000001988 x13: 0000000000b7fadc
x14: 0000000000a7e808 x15: 0000000000a7e808
x16: 0000000000000000 x17: 0000000000000000
x18: 0000000000b7fe50 x19: 0000000000b7fbe8
x20: 000000003c14dc00 x21: 000000003c14dc00
x22: 0000000000a7e808 x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 0000000000b7fb80
Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
Resetting CPU ...
--------
This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
with some rk3568 patches and this series, see [1].
The last 3 commits contains workaround to issue with sdmmc clock.
dwmmc driver set sclk to (uint)-2, my workaround just adds a
fallback to default 400khz clock.
Next issue is the sync abort, looks it happens when u-boot
tries to set clock rates based on devicetree. this is the
last debug line before the crash.
clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
[1] https://github.com/Kwiboo/u-boot-rockchip/compare/060a65e899859dcbf42049a18be20ce7118e7c0e...be21c34067d6e3a2036ce70d571700170c59d270
Regards,
Jonas
>
> Please check this repo, it is on top of the dm/master
> https://github.com/edgeble/u-boot/tree/neu6-v1
>
> Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 22:16 ` Jonas Karlman
@ 2023-01-26 23:43 ` Jonas Karlman
2023-01-27 13:21 ` Jagan Teki
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-01-26 23:43 UTC (permalink / raw)
To: Jagan Teki; +Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 2023-01-26 23:16, Jonas Karlman wrote:
> Hi Jagan,
> On 2023-01-26 20:17, Jagan Teki wrote:
>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>
>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>> Hi Simon,
>>>>
>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>
>>>>> Hi Jagan,
>>>>>
>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>
>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>
>>>>>>> Hi Jagan,
>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>> Hi Jonas,
>>>>>>>>
>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>
>>>>>>>>> Hi Jagan,
>>>>>>>>>
>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>> messages.
>>>>>>>>>>
>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>
>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>> bl31-v1.15
>>>>>>>>>> bl31-v1.21
>>>>>>>>>> bl31-v1.22
>>>>>>>>>> bl31-v1.23
>>>>>>>>>> bl31-v1.24
>>>>>>>>>> bl31-v1.25
>>>>>>>>>> bl31-v1.26
>>>>>>>>>>
>>>>>>>>>> Rever-engineered with respect to rockchip u-boot by using the same
>>>>>>>>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>>>>>>>>>> mainline showing the same issue.
>>>>>>>>>>
>>>>>>>>>> Log:
>>>>>>>>>>
>>>>>>>>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>>>>>>>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>>>>>>>> change to F1: 528MHz
>>>>>>>>>> change to F2: 1068MHz
>>>>>>>>>> change to F3: 1560MHz
>>>>>>>>>> change to F0: 2112MHz
>>>>>>>>>> out
>>>>>>>>>>
>>>>>>>>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>>>>>>>>>> Trying to boot from MMC1
>>>>>>>>>> bl31_entry: atf_entry start
>>>>>>>>>> << hang >>
>>>>>>>>>>
>>>>>>>>>> Any information on BL31 for RK3588 please share.
>>>>>>>>>
>>>>>>>>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
>>>>>>>>> turned out to be related to all parts of ATF not being properly loaded
>>>>>>>>> into PMU SRAM.
>>>>>>>>>
>>>>>>>>> Using my series at [1] I managed to get ATF to be fully loaded into
>>>>>>>>> PMU SRAM. Using CONFIG_SPL_FIT_SIGNATURE=y helped me finding out that
>>>>>>>>> the segment being loaded ended up corrupted.
>>>>>>>>>
>>>>>>>>> The use of 512 bytes alignment of the FIT helped mitigate that issue.
>>>>>>>>> Vendor U-Boot use a bounce buffer for all parts that is written into
>>>>>>>>> SRAM (anything loaded outside the gd->ram_base to gd->ram_top range).
>>>>>>>>>
>>>>>>>>> You can also find newer bl31 at [2], up to version v1.32.
>>>>>>>>>
>>>>>>>>> [1] https://patchwork.ozlabs.org/project/uboot/list/?series=337891 [2] https://gitlab.com/rk3588_linux/rk/rkbin/-/tree/linux-5.10-gen-rkr3.5/bin/rk35 Thanks for the details. I did apply this set on the master. No change
>>>>>>>> in the behavior, used BL31 and ddr from [2] as well as in
>>>>>>>> rkbin/master.
>>>>>>>
>>>>>>> I did some tests on my Radxa ROCK 3 Model B with CONFIG_SPL_FIT_SIGNATURE=y
>>>>>>> and it looked like it failed to read data into memory, see below.
>>>>>>>
>>>>>>> It also looks like the sdhci compatible is not supported by the driver.
>>>>>>> Something that may need to be added to driver to properly read data?
>>>>>>>
>>>>>>>
>>>>>>> DDR V1.09 a930779e06 typ 22/11/21-17:50:56
>>>>>>> LPDDR4X, 2112MHz
>>>>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
>>>>>>> Manufacturer ID:0x6
>>>>>>> CH0 RX Vref:31.7%, TX Vref:21.8%,20.8%
>>>>>>> CH1 RX Vref:31.7%, TX Vref:21.8%,21.8%
>>>>>>> CH2 RX Vref:32.7%, TX Vref:22.8%,21.8%
>>>>>>> CH3 RX Vref:32.7%, TX Vref:21.8%,20.8%
>>>>>>> change to F1: 528MHz
>>>>>>> change to F2: 1068MHz
>>>>>>> change to F3: 1560MHz
>>>>>>> change to F0: 2112MHz
>>>>>>> out
>>>>>>>
>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 00:24:53 +0000)
>>>>>>> Trying to boot from MMC1
>>>>>>> ## Checking hash(es) for config config_1 ... OK
>>>>>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
>>>>>>> Bad hash value for 'hash' hash node in 'atf_1' image node
>>>>>>> mmc_load_image_raw_sector: mmc block read error
>>>>>>> Trying to boot from MMC1
>>>>>>> ## Checking hash(es) for config config_1 ... OK
>>>>>>> ## Checking hash(es) for Image atf_1 ... sha256 error!
>>>>>>> Bad hash value for 'hash' hash node in 'atf_1' image node
>>>>>>
>>>>>> Look like this is something wrong with your patch series or master
>>>>>> changes on binman, not with the driver. I have observed the same if I
>>>>>> enable CONFIG_SPL_FIT_SIGNATURE.
>>>>>
>>>>> There are some more changes in dm/master that I'm about to pull in.
>>>>> One of them from Jonas Karlman adds hash nodes so may be involved.
>>>>
>>>> I found the same issue on the dm/master
>>>>
>>>> U-Boot SPL 2023.01-00176-gb21fb7a9c0 (Jan 26 2023 - 23:55:11 +0530)
>>>> Trying to boot from MMC1
>>>> ## Checking hash(es) for config config-1 ... OK
>>>> ## Checking hash(es) for Image atf-1 ... sha256 error!
>>>> Bad hash value for 'hash' hash node in 'atf-1' image node
>>>> mmc_load_image_raw_sector: mmc block read error
>>>> SPL: failed to boot from all boot devices
>>>> ### ERROR ### Please RESET the board ###
>>>
>>> On my RK3568 ROCK 3A board this is working correctly, see below.
>>>
>>> This was using u-boot master 17e8e58fe62c019b2cc26af221b6defc3368229f
>>> with a few patches on top, see [1].
>>>
>>> -------------
>>> U-Boot SPL 2023.01 (Jan 26 2023 - 18:29:56 +0000)
>>> Trying to boot from MMC1
>>> ## Checking hash(es) for config config-1 ... OK
>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-4 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-5 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-6 ... sha256+ OK
>>> INFO: Preloader serial: 2
>>> NOTICE: BL31: v2.3():v2.3-460-g2c8be93f9:huan.he
>>> NOTICE: BL31: Built : 19:45:17, Nov 8 2022
>>> INFO: GICv3 without legacy support detected.
>>> INFO: ARM GICv3 driver initialized in EL3
>>> INFO: pmu v1 is valid 220114
>>> INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz
>>> INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz
>>> INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz
>>> INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz
>>> INFO: Using opteed sec cpu_context!
>>> INFO: boot cpu mask: 0
>>> INFO: BL31: Initializing runtime services
>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>> ERROR: Error initializing runtime service opteed_fast
>>> INFO: BL31: Preparing for EL3 exit to normal world
>>> INFO: Entry point address = 0xa00000
>>> INFO: SPSR = 0x3c9
>>>
>>>
>>> U-Boot 2023.01 (Jan 26 2023 - 18:29:56 +0000)
>>>
>>> Model: Rockchip RK3568 EVB1 DDR4 V10 Board
>>> DRAM: 8 GiB (effective 7.7 GiB)
>>> Core: 58 devices, 17 uclasses, devicetree: separate
>>> MMC: mmc@fe2b0000: 1, mmc@fe310000: 0
>>> ...
>>> -------------
>>>
>>> However, on my RK3588 ROCK 5B device I get a similar error you get.
>>> Seems to be the mmc reading that times out all of sudden.
>>>
>>> It can read the FIP and config, and then some mmc command/transfer times out.
>>> See below for details with LOG_DEBUG defined at top of include/log.h
>>>
>>> This was trying to boot from a SD-card, trying to use eMMC fails earlier.
>>> Because there is no driver for emmc compatible, SPL only tries to boot from SD-card.
>>>
>>> I believe this is related to your << hang >>, reading atf
>>> from mmc fails in the background and there is no error message.
>>>
>>> That is why I suggested trying with CONFIG_SPL_FIT_SIGNATURE=y,
>>> to see if there is any hidden issue trying to load ATF.
>>>
>>> -------------
>>> Trying to boot from MMC1
>>> ## Checking hash(es) for config config-1 ... OK
>>> mmc_load_image_raw_sector: mmc block read error
>>> Trying to boot from MMC1
>>> mmc_load_image_raw_sector: mmc block read error
>>> SPL: failed to boot from all boot devices
>>> ### ERROR ### Please RESET the board ###
>>> -------------
>>> Trying to boot from MMC1
>>> 0
>>> - 0 'mmc@fe2c0000'
>>> - found
>>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>>> clock is disabled (0Hz)
>>> Buswidth = 0, clock: 0
>>> Buswidth = 1, clock: 0
>>> clock is enabled (400000Hz)
>>> Buswidth = 1, clock: 400000
>>> Sending CMD0
>>> Sending CMD8
>>> Sending CMD55
>>> Sending CMD41
>>> Sending CMD55
>>> Sending CMD41
>>> Sending CMD2
>>> Sending CMD3
>>> Sending CMD9
>>> Sending CMD7
>>> Sending CMD55
>>> Sending CMD51
>>> Sending CMD6
>>> Sending CMD55
>>> Sending CMD6
>>> Buswidth = 4, clock: 400000
>>> Sending CMD6
>>> clock is enabled (50000000Hz)
>>> Buswidth = 4, clock: 50000000
>>> clk_set_rate(clk=500000, rate=50000000)
>>> rockchip_dwmmc_get_mmc_clk: err=-2
>>> spl: mmc boot mode: raw
>>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>>> Sending CMD16
>>> Sending CMD17
>>> hdr read sector 4000, count=1
>>> Found FIT
>>> size=a00, ptr=ac0, limit=100000: aligned to 5000c0
>>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>>> Sending CMD16
>>> Sending CMD18
>>> Sending CMD12
>>> fit read sector 4000, sectors=5, dst=5000c0, count=5, size=0xa00
>>> Selecting default config 'rk3588-evb.dtb'
>>> ## Checking hash(es) for config config-1 ... fit_config_verify_required_keys: No signature node found: FDT_ERR_NOTFOUND
>>> OK
>>> firmware: 'atf-1'
>>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>>> Sending CMD16
>>> Sending CMD18
>>> dwmci_data_transfer: Timeout waiting for data!
>>> mmc_load_image_raw_sector: mmc block read error
>>> spl: mmc boot mode: fs
>>> Trying to boot from MMC1
>>> 0
>>> - 0 'mmc@fe2c0000'
>>> - found
>>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>>> spl: mmc boot mode: raw
>>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>>> Sending CMD16
>>> dwmci_send_cmd: Response Timeout.
>>> hdr read sector 4000, count=0
>>> mmc_load_image_raw_sector: mmc block read error
>>> spl: mmc boot mode: fs
>>> SPL: failed to boot from all boot devices
>>> ### ERROR ### Please RESET the board ###
>>
>> I'm thinking this is fit/binman issue rather than mmc.
>>
>> U-Boot SPL 2023.01-00176-gb21fb7a9c0-dirty (Jan 27 2023 - 00:43:52 +0530)
>> SPL malloc() before relocation used 0xbe0 bytes (2 KB)
>>>> SPL: board_init_r()
>> spl_init
>> size=a0, ptr=a0, limit=100000: 500000
>> size=8, ptr=a8, limit=100000: 5000a0
>> fdtdec_get_addr_size_auto_parent: na=2, ns=2,
>> fdtdec_get_addr_size_fixed: reg: addr=00000000x
>> ofnode_read_u32_index: bus-width: x (4)
>> ofnode_read_bool: non-removable: false
>> ofnode_read_u32_index: fifo-depth: x (256)
>> ofnode_read_bool: fifo-mode: false
>> ofnode_read_bool: u-boot,spl-fifo-mode: false
>> ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array:
>> clock-freq-min-max
>> get_prop_check_min_len: clock-freq-min-max
>> ofnode_read_u32_index: max-frequency: x (200000000)
>> clk_set_defaults(mmc@fe2c0000)
>> clk_set_default_parents: could not read assigned-clock-parents for 3f60700
>> ofnode_read_prop: assigned-clock-rates: <not found>
>> fdtdec_get_int: #clock-cells: x (1)
>> fdtdec_get_int: #clock-cells: x (1)
>> Looking for clock-controller@fd7c0000
>> Looking for clock-controller@fd7c0000
>> - checking clock-1
>> - checking clock-controller@fd7c0000
>> - result for clock-controller@fd7c0000: clock-controller@fd7c0000 (ret=0)
>> - result for clock-controller@fd7c0000: clock-controller@fd7c0000 (ret=0)
>> clk_of_xlate_default(clk=500000)
>> clk_request(dev=3f60320, clk=500000)
>> clk_set_rate(clk=500000, rate=400000)
>> rockchip_dwmmc_get_mmc_clk: err=-2
>> Trying to boot from MMC1
>> 0
>> - 0 'mmc@fe2c0000'
>> - found
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> clock is disabled (0Hz)
>> Buswidth = 0, clock: 0
>> Buswidth = 1, clock: 0
>> clock is enabled (400000Hz)
>> Buswidth = 1, clock: 400000
>> Sending CMD0
>> Sending CMD8
>> Sending CMD55
>> Sending CMD41
>> Sending CMD55
>> Sending CMD41
>> Sending CMD55
>> Sending CMD41
>> Sending CMD2
>> Sending CMD3
>> Sending CMD9
>> Sending CMD7
>> Sending CMD55
>> Unaligned buffer length u
>> size=40, ptr=100, limit=100000: aligned to 5000c0
>> Sending CMD51
>> Sending CMD6
>> Sending CMD55
>> Sending CMD6
>> Buswidth = 4, clock: 400000
>> Sending CMD6
>> clock is enabled (50000000Hz)
>> Buswidth = 4, clock: 50000000
>> clk_set_rate(clk=500000, rate=50000000)
>> rockchip_dwmmc_get_mmc_clk: err=-2
>> spl: mmc boot mode: raw
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> Sending CMD17
>> hdr read sector 4000, count=1
>> Found FIT
>> size=a00, ptr=b00, limit=100000: aligned to 500100
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> Sending CMD18
>> Sending CMD12
>> fit read sector 4000, sectors=5, dst=500100, count=5, size=0xa00
>> Selecting default config 'rk3588-edgeble-neu6a-io.dtb'
>> ## Checking hash(es) for config config-1 ...
>> fit_config_verify_required_keys: No signature node found:
>> FDT_ERR_NOTFOUND
>> OK
>> firmware: 'atf-1'
>> blk_find_device: uclass_id=67, devnum=0: mmc@fe2c0000.blk, 67, 0
>> Sending CMD16
>> Sending CMD18
>> dwmci_data_transfer: Timeout waiting for data!
>> Sending CMD12
>> External data: dst=40000, offset=ad200, size=2e940
>> ## Checking hash(es) for Image atf-1 ...
>> fit_image_verify_required_sigs: No signature node found:
>> FDT_ERR_NOTFOUND
>> sha256 error!
>> Bad hash value for 'hash' hash node in 'atf-1' image node
>> mmc_load_image_raw_sector: mmc block read error
>> spl: mmc boot mode: fs
>> SPL: failed to boot from all boot devices
>> ### ERROR ### Please RESET the board ###
>
> As you can see in the logs above there is timeout waiting for data.
>
> I managed to find the issue and have a workaround that gets me longer
> in the boot process, there still seem to be other issue with the rk3588
> startup.
>
> --------
> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
> Trying to boot from MMC1
> ## Checking hash(es) for config config-1 ... OK
> ## Checking hash(es) for Image atf-1 ... sha256+ OK
> ## Checking hash(es) for Image u-boot ... sha256+ OK
> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
> ## Checking hash(es) for Image atf-2 ... sha256+ OK
> ## Checking hash(es) for Image atf-3 ... sha256+ OK
> INFO: Preloader serial: 2
> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
> INFO: spec: 0x1
> INFO: ext 32k is not valid
> INFO: ddr: stride-en 4CH
> INFO: GICv3 without legacy support detected.
> INFO: ARM GICv3 driver initialized in EL3
> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
> INFO: system boots from cpu-hwid-0
> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
> INFO: BL31: Initialising Exception Handling Framework
> INFO: BL31: Initializing runtime services
> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
> ERROR: Error initializing runtime service opteed_fast
> INFO: BL31: Preparing for EL3 exit to normal world
> INFO: Entry point address = 0xa00000
> INFO: SPSR = 0x3c9
> "Synchronous Abort" handler, esr 0x96000000
> elr: 0000000000a23650 lr : 0000000000a24d9c
> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
> x2 : 0000000000000000 x3 : 0000000000b80ff0
> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
> x6 : 0000000000000054 x7 : 0000000000000044
> x8 : 000000000000000a x9 : 0000000000000000
> x10: 0000000000000034 x11: 0000000000000002
> x12: 0000000000001988 x13: 0000000000b7fadc
> x14: 0000000000a7e808 x15: 0000000000a7e808
> x16: 0000000000000000 x17: 0000000000000000
> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
> x20: 000000003c14dc00 x21: 000000003c14dc00
> x22: 0000000000a7e808 x23: 0000000000000000
> x24: 0000000000000000 x25: 0000000000000000
> x26: 0000000000000000 x27: 0000000000000000
> x28: 0000000000000000 x29: 0000000000b7fb80
>
> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
> Resetting CPU ...
> --------
>
> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
> with some rk3568 patches and this series, see [1].
>
> The last 3 commits contains workaround to issue with sdmmc clock.
> dwmmc driver set sclk to (uint)-2, my workaround just adds a
> fallback to default 400khz clock.
>
> Next issue is the sync abort, looks it happens when u-boot
> tries to set clock rates based on devicetree. this is the
> last debug line before the crash.
>
> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
With the commit at [2] I can now successfully run U-Boot proper.
Source of the two main issues to get this series to run have been the scmi clocks.
Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
We can just remove it and leave setting a faster cpu rate to linux.
I also noticed that my sdram size series only detect the first two channels of memory,
will respin a v2 of that series to add detection of all 4 channels of memory.
[2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
Regards,
Jonas
>
> [1] https://github.com/Kwiboo/u-boot-rockchip/compare/060a65e899859dcbf42049a18be20ce7118e7c0e...be21c34067d6e3a2036ce70d571700170c59d270
>
> Regards,
> Jonas
>
>>
>> Please check this repo, it is on top of the dm/master
>> https://github.com/edgeble/u-boot/tree/neu6-v1
>>
>> Jagan.
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-26 23:43 ` Jonas Karlman
@ 2023-01-27 13:21 ` Jagan Teki
2023-01-29 9:04 ` Jonas Karlman
0 siblings, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-27 13:21 UTC (permalink / raw)
To: Jonas Karlman
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> On 2023-01-26 23:16, Jonas Karlman wrote:
> > Hi Jagan,
> > On 2023-01-26 20:17, Jagan Teki wrote:
> >> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>
> >>> On 2023-01-26 19:26, Jagan Teki wrote:
> >>>> Hi Simon,
> >>>>
> >>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
> >>>>>
> >>>>> Hi Jagan,
> >>>>>
> >>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> >>>>>>
> >>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>
> >>>>>>> Hi Jagan,
> >>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
> >>>>>>>> Hi Jonas,
> >>>>>>>>
> >>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>
> >>>>>>>>> Hi Jagan,
> >>>>>>>>>
> >>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
> >>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
> >>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
> >>>>>>>>>> messages.
> >>>>>>>>>>
> >>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> >>>>>>>>>> it is failing to load ATF entry from SPL and hang.
> >>>>>>>>>>
> >>>>>>>>>> Verified below BL31 versions,
> >>>>>>>>>> bl31-v1.15
> >>>>>>>>>> bl31-v1.21
> >>>>>>>>>> bl31-v1.22
> >>>>>>>>>> bl31-v1.23
> >>>>>>>>>> bl31-v1.24
> >>>>>>>>>> bl31-v1.25
> >>>>>>>>>> bl31-v1.26
> >>>>>>>>>>
< snip >
> >
> > As you can see in the logs above there is timeout waiting for data.
> >
> > I managed to find the issue and have a workaround that gets me longer
> > in the boot process, there still seem to be other issue with the rk3588
> > startup.
> >
> > --------
> > U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
> > Trying to boot from MMC1
> > ## Checking hash(es) for config config-1 ... OK
> > ## Checking hash(es) for Image atf-1 ... sha256+ OK
> > ## Checking hash(es) for Image u-boot ... sha256+ OK
> > ## Checking hash(es) for Image fdt-1 ... sha256+ OK
> > ## Checking hash(es) for Image atf-2 ... sha256+ OK
> > ## Checking hash(es) for Image atf-3 ... sha256+ OK
> > INFO: Preloader serial: 2
> > NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
> > NOTICE: BL31: Built : 09:59:49, Nov 21 2022
> > INFO: spec: 0x1
> > INFO: ext 32k is not valid
> > INFO: ddr: stride-en 4CH
> > INFO: GICv3 without legacy support detected.
> > INFO: ARM GICv3 driver initialized in EL3
> > INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
> > INFO: system boots from cpu-hwid-0
> > INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
> > INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
> > INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
> > INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
> > INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
> > INFO: BL31: Initialising Exception Handling Framework
> > INFO: BL31: Initializing runtime services
> > WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
> > ERROR: Error initializing runtime service opteed_fast
> > INFO: BL31: Preparing for EL3 exit to normal world
> > INFO: Entry point address = 0xa00000
> > INFO: SPSR = 0x3c9
> > "Synchronous Abort" handler, esr 0x96000000
> > elr: 0000000000a23650 lr : 0000000000a24d9c
> > x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
> > x2 : 0000000000000000 x3 : 0000000000b80ff0
> > x4 : 0000000000b80ff0 x5 : 0000000000b80e88
> > x6 : 0000000000000054 x7 : 0000000000000044
> > x8 : 000000000000000a x9 : 0000000000000000
> > x10: 0000000000000034 x11: 0000000000000002
> > x12: 0000000000001988 x13: 0000000000b7fadc
> > x14: 0000000000a7e808 x15: 0000000000a7e808
> > x16: 0000000000000000 x17: 0000000000000000
> > x18: 0000000000b7fe50 x19: 0000000000b7fbe8
> > x20: 000000003c14dc00 x21: 000000003c14dc00
> > x22: 0000000000a7e808 x23: 0000000000000000
> > x24: 0000000000000000 x25: 0000000000000000
> > x26: 0000000000000000 x27: 0000000000000000
> > x28: 0000000000000000 x29: 0000000000b7fb80
> >
> > Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
> > Resetting CPU ...
> > --------
> >
> > This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
> > with some rk3568 patches and this series, see [1].
> >
> > The last 3 commits contains workaround to issue with sdmmc clock.
> > dwmmc driver set sclk to (uint)-2, my workaround just adds a
> > fallback to default 400khz clock.
> >
> > Next issue is the sync abort, looks it happens when u-boot
> > tries to set clock rates based on devicetree. this is the
> > last debug line before the crash.
> >
> > clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>
> With the commit at [2] I can now successfully run U-Boot proper.
>
> Source of the two main issues to get this series to run have been the scmi clocks.
> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
> We can just remove it and leave setting a faster cpu rate to linux.
>
> I also noticed that my sdram size series only detect the first two channels of memory,
> will respin a v2 of that series to add detection of all 4 channels of memory.
>
> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
Okay. We need to find a way to handle the clock value 400Khz
generically via the CLK framework or eMMC can be worth checking as it
doesn't involve SCMI and have a working patch set before MW. I did
that and was able to detect eMMC in U-Boot proper but got some issues
while booting from eMMC [3]
[3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi
2023-01-25 22:27 ` [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi Jagan Teki
@ 2023-01-27 13:33 ` Eugen Hristev
2023-01-27 13:37 ` Jagan Teki
2023-01-27 15:19 ` Eugen Hristev
1 sibling, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-01-27 13:33 UTC (permalink / raw)
To: Jagan Teki, Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot
Hello Jagan,
On 1/26/23 00:27, Jagan Teki wrote:
> Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
> for Rockchip RK3588 SoC.
It appears this file/commit does more than just adding u-boot,* properties
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
> create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
> new file mode 100644
> index 0000000000..b5cc4dcc60
> --- /dev/null
> +++ b/arch/arm/dts/rk3588-u-boot.dtsi
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +#include "rockchip-u-boot.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + dmc {
> + compatible = "rockchip,rk3588-dmc";
> + u-boot,dm-pre-reloc;
> + status = "okay";
> + };
> +
> + pmu1_grf: syscon@fd58a000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3588-pmu1-grf", "syscon";
> + reg = <0x0 0xfd58a000 0x0 0x2000>;
> + };
> +
> + sdmmc: mmc@fe2c0000 {
Just for my understanding, why are you adding here a new node sdmmc, and
have it disabled, while you have another node called 'sdhci' which you
enable further down in the file ?
What is the purpose of this sdmmc node? and defining it here.
Eugen
> + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xfe2c0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_SDMMC_SAMPLE>, <&cru SCLK_SDMMC_DRV>,
> + <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
> + clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <200000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
> + status = "disabled";
> + };
> +};
> +
> +&gpio0 {
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&gpio1 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&gpio2 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&gpio3 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&gpio4 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&scmi {
> + u-boot,dm-spl;
> +};
> +
> +&scmi_clk {
> + u-boot,dm-spl;
> +};
> +
> +&xin24m {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&cru {
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&sys_grf {
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&uart2 {
> + clock-frequency = <24000000>;
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&sdhci {
> + bus-width = <8>;
> + u-boot,dm-spl;
> + mmc-hs200-1_8v;
> + non-removable;
> + status = "okay";
> +};
> +
> +&ioc {
> + u-boot,dm-spl;
> +};
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi
2023-01-27 13:33 ` Eugen Hristev
@ 2023-01-27 13:37 ` Jagan Teki
2023-01-27 13:50 ` Eugen Hristev
0 siblings, 1 reply; 56+ messages in thread
From: Jagan Teki @ 2023-01-27 13:37 UTC (permalink / raw)
To: Eugen Hristev
Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
On Fri, 27 Jan 2023 at 19:03, Eugen Hristev <eugen.hristev@collabora.com> wrote:
>
> Hello Jagan,
>
>
> On 1/26/23 00:27, Jagan Teki wrote:
> > Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
> > for Rockchip RK3588 SoC.
>
> It appears this file/commit does more than just adding u-boot,* properties
>
> >
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> > ---
> > arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++
> > 1 file changed, 101 insertions(+)
> > create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
> >
> > diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..b5cc4dcc60
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3588-u-boot.dtsi
> > @@ -0,0 +1,101 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> > + */
> > +
> > +#include "rockchip-u-boot.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + dmc {
> > + compatible = "rockchip,rk3588-dmc";
> > + u-boot,dm-pre-reloc;
> > + status = "okay";
> > + };
> > +
> > + pmu1_grf: syscon@fd58a000 {
> > + u-boot,dm-pre-reloc;
> > + compatible = "rockchip,rk3588-pmu1-grf", "syscon";
> > + reg = <0x0 0xfd58a000 0x0 0x2000>;
> > + };
> > +
> > + sdmmc: mmc@fe2c0000 {
>
> Just for my understanding, why are you adding here a new node sdmmc, and
> have it disabled, while you have another node called 'sdhci' which you
> enable further down in the file ?
> What is the purpose of this sdmmc node? and defining it here.
In order to boot SDCard, linux doesn't support this node yet so once
Linux has it we can sync and drop this from here. Idea is to have
devicetree files be the same as in Linux in order to maintain them
properly. As long as the specific node is not supported in Linux that
would be considered as -u-boot.dtsi specific.
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi
2023-01-27 13:37 ` Jagan Teki
@ 2023-01-27 13:50 ` Eugen Hristev
2023-01-27 14:23 ` Jagan Teki
0 siblings, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-01-27 13:50 UTC (permalink / raw)
To: Jagan Teki; +Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
On 1/27/23 15:37, Jagan Teki wrote:
> On Fri, 27 Jan 2023 at 19:03, Eugen Hristev <eugen.hristev@collabora.com> wrote:
>>
>> Hello Jagan,
>>
>>
>> On 1/26/23 00:27, Jagan Teki wrote:
>>> Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
>>> for Rockchip RK3588 SoC.
>>
>> It appears this file/commit does more than just adding u-boot,* properties
>>
>>>
>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>> ---
>>> arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++
>>> 1 file changed, 101 insertions(+)
>>> create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
>>>
>>> diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
>>> new file mode 100644
>>> index 0000000000..b5cc4dcc60
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3588-u-boot.dtsi
>>> @@ -0,0 +1,101 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
>>> + */
>>> +
>>> +#include "rockchip-u-boot.dtsi"
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +
>>> +/ {
>>> + dmc {
>>> + compatible = "rockchip,rk3588-dmc";
>>> + u-boot,dm-pre-reloc;
>>> + status = "okay";
>>> + };
>>> +
>>> + pmu1_grf: syscon@fd58a000 {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "rockchip,rk3588-pmu1-grf", "syscon";
>>> + reg = <0x0 0xfd58a000 0x0 0x2000>;
>>> + };
>>> +
>>> + sdmmc: mmc@fe2c0000 {
>>
>> Just for my understanding, why are you adding here a new node sdmmc, and
>> have it disabled, while you have another node called 'sdhci' which you
>> enable further down in the file ?
>> What is the purpose of this sdmmc node? and defining it here.
>
> In order to boot SDCard, linux doesn't support this node yet so once
> Linux has it we can sync and drop this from here. Idea is to have
> devicetree files be the same as in Linux in order to maintain them
> properly. As long as the specific node is not supported in Linux that
> would be considered as -u-boot.dtsi specific.
Okay, but the node is disabled.. while you enable the 'sdhci' node below
in the file.
>
> Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi
2023-01-27 13:50 ` Eugen Hristev
@ 2023-01-27 14:23 ` Jagan Teki
0 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-27 14:23 UTC (permalink / raw)
To: Eugen Hristev
Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
On Fri, 27 Jan 2023 at 19:21, Eugen Hristev <eugen.hristev@collabora.com> wrote:
>
> On 1/27/23 15:37, Jagan Teki wrote:
> > On Fri, 27 Jan 2023 at 19:03, Eugen Hristev <eugen.hristev@collabora.com> wrote:
> >>
> >> Hello Jagan,
> >>
> >>
> >> On 1/26/23 00:27, Jagan Teki wrote:
> >>> Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
> >>> for Rockchip RK3588 SoC.
> >>
> >> It appears this file/commit does more than just adding u-boot,* properties
> >>
> >>>
> >>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>> ---
> >>> arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++
> >>> 1 file changed, 101 insertions(+)
> >>> create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
> >>>
> >>> diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
> >>> new file mode 100644
> >>> index 0000000000..b5cc4dcc60
> >>> --- /dev/null
> >>> +++ b/arch/arm/dts/rk3588-u-boot.dtsi
> >>> @@ -0,0 +1,101 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >>> +/*
> >>> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> >>> + */
> >>> +
> >>> +#include "rockchip-u-boot.dtsi"
> >>> +#include <dt-bindings/gpio/gpio.h>
> >>> +
> >>> +/ {
> >>> + dmc {
> >>> + compatible = "rockchip,rk3588-dmc";
> >>> + u-boot,dm-pre-reloc;
> >>> + status = "okay";
> >>> + };
> >>> +
> >>> + pmu1_grf: syscon@fd58a000 {
> >>> + u-boot,dm-pre-reloc;
> >>> + compatible = "rockchip,rk3588-pmu1-grf", "syscon";
> >>> + reg = <0x0 0xfd58a000 0x0 0x2000>;
> >>> + };
> >>> +
> >>> + sdmmc: mmc@fe2c0000 {
> >>
> >> Just for my understanding, why are you adding here a new node sdmmc, and
> >> have it disabled, while you have another node called 'sdhci' which you
> >> enable further down in the file ?
> >> What is the purpose of this sdmmc node? and defining it here.
> >
> > In order to boot SDCard, linux doesn't support this node yet so once
> > Linux has it we can sync and drop this from here. Idea is to have
> > devicetree files be the same as in Linux in order to maintain them
> > properly. As long as the specific node is not supported in Linux that
> > would be considered as -u-boot.dtsi specific.
>
> Okay, but the node is disabled.. while you enable the 'sdhci' node below
> in the file.
Yes, few nits to fix. I'm working on the final working version. Will
fix these in the next version patchset.
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi
2023-01-25 22:27 ` [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi Jagan Teki
2023-01-27 13:33 ` Eugen Hristev
@ 2023-01-27 15:19 ` Eugen Hristev
1 sibling, 0 replies; 56+ messages in thread
From: Eugen Hristev @ 2023-01-27 15:19 UTC (permalink / raw)
To: Jagan Teki, Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot
On 1/26/23 00:27, Jagan Teki wrote:
> Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
> for Rockchip RK3588 SoC.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> arch/arm/dts/rk3588-u-boot.dtsi | 101 ++++++++++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
> create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
> new file mode 100644
> index 0000000000..b5cc4dcc60
> --- /dev/null
> +++ b/arch/arm/dts/rk3588-u-boot.dtsi
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +#include "rockchip-u-boot.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + dmc {
> + compatible = "rockchip,rk3588-dmc";
> + u-boot,dm-pre-reloc;
> + status = "okay";
> + };
> +
> + pmu1_grf: syscon@fd58a000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3588-pmu1-grf", "syscon";
> + reg = <0x0 0xfd58a000 0x0 0x2000>;
> + };
> +
> + sdmmc: mmc@fe2c0000 {
> + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xfe2c0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
One extra thing, it appears the interrupt needs 4 fields , not just 3 as
you wrote for this node. Other nodes referencing GIC_SPI have an extra
4th field in the other DT files.
Eugen
> + clocks = <&cru SCLK_SDMMC_SAMPLE>, <&cru SCLK_SDMMC_DRV>,
> + <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>;
> + clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <200000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
> + status = "disabled";
> + };
> +};
> +
> +&gpio0 {
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&gpio1 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&gpio2 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&gpio3 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&gpio4 {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&scmi {
> + u-boot,dm-spl;
> +};
> +
> +&scmi_clk {
> + u-boot,dm-spl;
> +};
> +
> +&xin24m {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&cru {
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&sys_grf {
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&uart2 {
> + clock-frequency = <24000000>;
> + u-boot,dm-spl;
> + status = "okay";
> +};
> +
> +&sdhci {
> + bus-width = <8>;
> + u-boot,dm-spl;
> + mmc-hs200-1_8v;
> + non-removable;
> + status = "okay";
> +};
> +
> +&ioc {
> + u-boot,dm-spl;
> +};
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-27 13:21 ` Jagan Teki
@ 2023-01-29 9:04 ` Jonas Karlman
2023-03-08 8:57 ` Eugen Hristev
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-01-29 9:04 UTC (permalink / raw)
To: Jagan Teki; +Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 2023-01-27 14:21, Jagan Teki wrote:
> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>> Hi Jagan,
>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>
>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>> Hi Simon,
>>>>>>
>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>
>>>>>>> Hi Jagan,
>>>>>>>
>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>
>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>
>>>>>>>>> Hi Jagan,
>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>> Hi Jonas,
>>>>>>>>>>
>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>
>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>
>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>> messages.
>>>>>>>>>>>>
>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>
>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>
>
> < snip >
>
>>>
>>> As you can see in the logs above there is timeout waiting for data.
>>>
>>> I managed to find the issue and have a workaround that gets me longer
>>> in the boot process, there still seem to be other issue with the rk3588
>>> startup.
>>>
>>> --------
>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>> Trying to boot from MMC1
>>> ## Checking hash(es) for config config-1 ... OK
>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>> INFO: Preloader serial: 2
>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>> INFO: spec: 0x1
>>> INFO: ext 32k is not valid
>>> INFO: ddr: stride-en 4CH
>>> INFO: GICv3 without legacy support detected.
>>> INFO: ARM GICv3 driver initialized in EL3
>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>> INFO: system boots from cpu-hwid-0
>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>> INFO: BL31: Initialising Exception Handling Framework
>>> INFO: BL31: Initializing runtime services
>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>> ERROR: Error initializing runtime service opteed_fast
>>> INFO: BL31: Preparing for EL3 exit to normal world
>>> INFO: Entry point address = 0xa00000
>>> INFO: SPSR = 0x3c9
>>> "Synchronous Abort" handler, esr 0x96000000
>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>> x6 : 0000000000000054 x7 : 0000000000000044
>>> x8 : 000000000000000a x9 : 0000000000000000
>>> x10: 0000000000000034 x11: 0000000000000002
>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>> x16: 0000000000000000 x17: 0000000000000000
>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>> x22: 0000000000a7e808 x23: 0000000000000000
>>> x24: 0000000000000000 x25: 0000000000000000
>>> x26: 0000000000000000 x27: 0000000000000000
>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>
>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>> Resetting CPU ...
>>> --------
>>>
>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>> with some rk3568 patches and this series, see [1].
>>>
>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>> fallback to default 400khz clock.
>>>
>>> Next issue is the sync abort, looks it happens when u-boot
>>> tries to set clock rates based on devicetree. this is the
>>> last debug line before the crash.
>>>
>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>
>> With the commit at [2] I can now successfully run U-Boot proper.
>>
>> Source of the two main issues to get this series to run have been the scmi clocks.
>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>> We can just remove it and leave setting a faster cpu rate to linux.
>>
>> I also noticed that my sdram size series only detect the first two channels of memory,
>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>
>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>
> Okay. We need to find a way to handle the clock value 400Khz
> generically via the CLK framework or eMMC can be worth checking as it
> doesn't involve SCMI and have a working patch set before MW. I did
> that and was able to detect eMMC in U-Boot proper but got some issues
> while booting from eMMC [3]
I have an updated branch at [4] that should support booting from sdmmc and sdhci.
Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
and I have included some rk3568 patches and your rk3588 rfc series.
I added a few fixup on top of that and a few additional patches, please see commit message
for a very brief note on why the change was needed.
Feel free to squash fixups and pick commits up to and possible including
"board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
for a v2 of this series.
The remaining sdhci patches needs a little bit more work,
I can send a separate series with emmc patches once they are fully ready.
The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
I think this is a more appropriate way to work around this issue, instead of patching
u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
[4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
Regards,
Jonas
>
> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>
> Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-25 22:47 ` [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jonas Karlman
2023-01-26 16:51 ` Jagan Teki
@ 2023-01-29 9:47 ` Kever Yang
2023-01-29 9:58 ` Jonas Karlman
1 sibling, 1 reply; 56+ messages in thread
From: Kever Yang @ 2023-01-29 9:47 UTC (permalink / raw)
To: Jonas Karlman, Jagan Teki, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot
Hi Jonas, Jagan,
On 2023/1/26 06:47, Jonas Karlman wrote:
> Hi Jagan,
>
> On 2023-01-25 23:27, Jagan Teki wrote:
>> This series support Rockchip RK3588. All the device tree files are
>> synced from linux-next with the proper SHA1 mentioned in the commit
>> messages.
>>
>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>> it is failing to load ATF entry from SPL and hang.
>>
>> Verified below BL31 versions,
>> bl31-v1.15
>> bl31-v1.21
>> bl31-v1.22
>> bl31-v1.23
>> bl31-v1.24
>> bl31-v1.25
>> bl31-v1.26
>>
>> Rever-engineered with respect to rockchip u-boot by using the same
>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>> mainline showing the same issue.
>>
>> Log:
>>
>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>> change to F1: 528MHz
>> change to F2: 1068MHz
>> change to F3: 1560MHz
>> change to F0: 2112MHz
>> out
>>
>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>> Trying to boot from MMC1
>> bl31_entry: atf_entry start
>> << hang >>
>>
>> Any information on BL31 for RK3588 please share.
> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> turned out to be related to all parts of ATF not being properly loaded
> into PMU SRAM.
For this issue, could you try to add below property for mmc dts node?
"u-boot,spl-fifo-mode"
The emmc/sdmmc controller do not have a direct path to the SRAM, so we
can't use
its internal DMA to do the data transfer. The "fifo-mode" will use CPU
to do the data
copy instead of the internal DMA.
Thanks,
- Kever
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-29 9:47 ` Kever Yang
@ 2023-01-29 9:58 ` Jonas Karlman
2023-01-30 0:55 ` Kever Yang
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-01-29 9:58 UTC (permalink / raw)
To: Kever Yang, Jagan Teki, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot
Hi Kever,
On 2023-01-29 10:47, Kever Yang wrote:
> Hi Jonas, Jagan,
>
> On 2023/1/26 06:47, Jonas Karlman wrote:
>> Hi Jagan,
>>
>> On 2023-01-25 23:27, Jagan Teki wrote:
>>> This series support Rockchip RK3588. All the device tree files are
>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>> messages.
>>>
>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>> it is failing to load ATF entry from SPL and hang.
>>>
>>> Verified below BL31 versions,
>>> bl31-v1.15
>>> bl31-v1.21
>>> bl31-v1.22
>>> bl31-v1.23
>>> bl31-v1.24
>>> bl31-v1.25
>>> bl31-v1.26
>>>
>>> Rever-engineered with respect to rockchip u-boot by using the same
>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>>> mainline showing the same issue.
>>>
>>> Log:
>>>
>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>> change to F1: 528MHz
>>> change to F2: 1068MHz
>>> change to F3: 1560MHz
>>> change to F0: 2112MHz
>>> out
>>>
>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>>> Trying to boot from MMC1
>>> bl31_entry: atf_entry start
>>> << hang >>
>>>
>>> Any information on BL31 for RK3588 please share.
>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
>> turned out to be related to all parts of ATF not being properly loaded
>> into PMU SRAM.
>
> For this issue, could you try to add below property for mmc dts node?
>
> "u-boot,spl-fifo-mode"
>
> The emmc/sdmmc controller do not have a direct path to the SRAM, so we
> can't use
>
> its internal DMA to do the data transfer. The "fifo-mode" will use CPU
> to do the data
>
> copy instead of the internal DMA.
For sdmmc this worked, but for emmc it did not, trying to use the emmc without
SDMA seemed to cause issues reading data in general, did not fully investigate why.
I am thinking we could use some sort of mechanism to signal mkimage that we want to
keep the parts that should be loaded into SRAM as embedded data instead of external data.
That way the FIT can be loaded using DMA into DRAM, and the embedded data will then
be memcpy into SRAM using CPU.
I quickly tested [0] and this seem to work and we do not need to use the fifo-mode
to work around this DMA to SRAM issue. Will work on a proper RFC for such solution.
[0] https://github.com/Kwiboo/u-boot-rockchip/commit/551b02a5cd7d28244f44b2e7d7a29196305c26f6
Regards,
Jonas
>
>
> Thanks,
>
> - Kever
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-29 9:58 ` Jonas Karlman
@ 2023-01-30 0:55 ` Kever Yang
2023-01-30 5:19 ` Jagan Teki
0 siblings, 1 reply; 56+ messages in thread
From: Kever Yang @ 2023-01-30 0:55 UTC (permalink / raw)
To: Jonas Karlman, Jagan Teki, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot
Hi Jonas,
On 2023/1/29 17:58, Jonas Karlman wrote:
> Hi Kever,
> On 2023-01-29 10:47, Kever Yang wrote:
>> Hi Jonas, Jagan,
>>
>> On 2023/1/26 06:47, Jonas Karlman wrote:
>>> Hi Jagan,
>>>
>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>> This series support Rockchip RK3588. All the device tree files are
>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>> messages.
>>>>
>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>> it is failing to load ATF entry from SPL and hang.
>>>>
>>>> Verified below BL31 versions,
>>>> bl31-v1.15
>>>> bl31-v1.21
>>>> bl31-v1.22
>>>> bl31-v1.23
>>>> bl31-v1.24
>>>> bl31-v1.25
>>>> bl31-v1.26
>>>>
>>>> Rever-engineered with respect to rockchip u-boot by using the same
>>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
>>>> mainline showing the same issue.
>>>>
>>>> Log:
>>>>
>>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
>>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
>>>> change to F1: 528MHz
>>>> change to F2: 1068MHz
>>>> change to F3: 1560MHz
>>>> change to F0: 2112MHz
>>>> out
>>>>
>>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
>>>> Trying to boot from MMC1
>>>> bl31_entry: atf_entry start
>>>> << hang >>
>>>>
>>>> Any information on BL31 for RK3588 please share.
>>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
>>> turned out to be related to all parts of ATF not being properly loaded
>>> into PMU SRAM.
>> For this issue, could you try to add below property for mmc dts node?
>>
>> "u-boot,spl-fifo-mode"
>>
>> The emmc/sdmmc controller do not have a direct path to the SRAM, so we
>> can't use
>>
>> its internal DMA to do the data transfer. The "fifo-mode" will use CPU
>> to do the data
>>
>> copy instead of the internal DMA.
> For sdmmc this worked, but for emmc it did not, trying to use the emmc without
> SDMA seemed to cause issues reading data in general, did not fully investigate why.
The sdmmc is using driver rockchip_dw_mmc.c while the emmc is using the
driver rockchip_sdhci.c,
I think this is the root cause for the "spl-fifo-mode" only only works
on sdmmc.
Thanks,
- Kever
> I am thinking we could use some sort of mechanism to signal mkimage that we want to
> keep the parts that should be loaded into SRAM as embedded data instead of external data.
> That way the FIT can be loaded using DMA into DRAM, and the embedded data will then
> be memcpy into SRAM using CPU.
>
> I quickly tested [0] and this seem to work and we do not need to use the fifo-mode
> to work around this DMA to SRAM issue. Will work on a proper RFC for such solution.
>
> [0] https://github.com/Kwiboo/u-boot-rockchip/commit/551b02a5cd7d28244f44b2e7d7a29196305c26f6
>
> Regards,
> Jonas
>
>>
>> Thanks,
>>
>> - Kever
>>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-30 0:55 ` Kever Yang
@ 2023-01-30 5:19 ` Jagan Teki
0 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-01-30 5:19 UTC (permalink / raw)
To: Kever Yang
Cc: Jonas Karlman, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
Hi Kever,
On Mon, 30 Jan 2023 at 06:25, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Jonas,
>
>
> On 2023/1/29 17:58, Jonas Karlman wrote:
> > Hi Kever,
> > On 2023-01-29 10:47, Kever Yang wrote:
> >> Hi Jonas, Jagan,
> >>
> >> On 2023/1/26 06:47, Jonas Karlman wrote:
> >>> Hi Jagan,
> >>>
> >>> On 2023-01-25 23:27, Jagan Teki wrote:
> >>>> This series support Rockchip RK3588. All the device tree files are
> >>>> synced from linux-next with the proper SHA1 mentioned in the commit
> >>>> messages.
> >>>>
> >>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> >>>> it is failing to load ATF entry from SPL and hang.
> >>>>
> >>>> Verified below BL31 versions,
> >>>> bl31-v1.15
> >>>> bl31-v1.21
> >>>> bl31-v1.22
> >>>> bl31-v1.23
> >>>> bl31-v1.24
> >>>> bl31-v1.25
> >>>> bl31-v1.26
> >>>>
> >>>> Rever-engineered with respect to rockchip u-boot by using the same
> >>>> FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but
> >>>> mainline showing the same issue.
> >>>>
> >>>> Log:
> >>>>
> >>>> LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ���3:44:34 +0530)
> >>>> channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>> channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>> channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>> channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB
> >>>> change to F1: 528MHz
> >>>> change to F2: 1068MHz
> >>>> change to F3: 1560MHz
> >>>> change to F0: 2112MHz
> >>>> out
> >>>>
> >>>> U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530)
> >>>> Trying to boot from MMC1
> >>>> bl31_entry: atf_entry start
> >>>> << hang >>
> >>>>
> >>>> Any information on BL31 for RK3588 please share.
> >>> I had a similar strange booing issue with RK3568 and mainline U-Boot,
> >>> turned out to be related to all parts of ATF not being properly loaded
> >>> into PMU SRAM.
> >> For this issue, could you try to add below property for mmc dts node?
> >>
> >> "u-boot,spl-fifo-mode"
> >>
> >> The emmc/sdmmc controller do not have a direct path to the SRAM, so we
> >> can't use
> >>
> >> its internal DMA to do the data transfer. The "fifo-mode" will use CPU
> >> to do the data
> >>
> >> copy instead of the internal DMA.
> > For sdmmc this worked, but for emmc it did not, trying to use the emmc without
> > SDMA seemed to cause issues reading data in general, did not fully investigate why.
>
>
> The sdmmc is using driver rockchip_dw_mmc.c while the emmc is using the
> driver rockchip_sdhci.c,
>
> I think this is the root cause for the "spl-fifo-mode" only only works
> on sdmmc.
Apart from this, the 400KHZ clock workaround is required to boot the
SDMMC. I feel this hack of 400KHZ cannot be proper, we need to handle
that via CLK drivers to get the rate.
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6
2023-01-25 22:27 ` [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6 Jagan Teki
@ 2023-02-02 8:23 ` Eugen Hristev
2023-02-16 9:03 ` Jagan Teki
0 siblings, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-02-02 8:23 UTC (permalink / raw)
To: Jagan Teki, Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat; +Cc: u-boot
On 1/26/23 00:27, Jagan Teki wrote:
> Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
> based on Rockchip RK3588 from Edgeble AI.
>
> General features:
> - Rockchip RK3588
> - up to 32GB LPDDR4x
> - up to 128GB eMMC
> - 2x MIPI CSI2 FPC
>
> On module WiFi6/BT5 is available in the following Neu6 variants.
>
> Neural Compute Module 6(Neu6) IO board is an industrial form factor
> ready-to-use IO board from Edgeble AI.
>
> IO board offers plenty of peripherals and connectivity options and
> this patch enables basic eMMC and UART which is enough to successfully
> boot Linux.
>
> Neu6 needs to mount on top of this IO board in order to create a
> complete Edgeble Neural Compute Module 6(Neu6) IO platform.
>
> Add support for Edgeble Neu6 Model A IO Board.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
[snip]
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 28c837a382..a140c1a8a4 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -86,6 +86,8 @@ List of mainline supported Rockchip boards:
> - Radxa ROCK Pi 4 (rock-pi-4-rk3399)
> - Rockchip Evb-RK3399 (evb_rk3399)
> - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
> +* rk3588
> + - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-r1126)
Hi Jagan,
I suppose here it should be neu6a-io-rk3588 , in the line above
Eugen
> * rv1108
> - Rockchip Evb-rv1108 (evb-rv1108)
> - Elgin-R1 (elgin-rv1108)
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC
2023-01-25 22:27 ` [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC Jagan Teki
@ 2023-02-02 14:06 ` Eugen Hristev
0 siblings, 0 replies; 56+ messages in thread
From: Eugen Hristev @ 2023-02-02 14:06 UTC (permalink / raw)
To: Jagan Teki, Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Jianqun Xu
On 1/26/23 00:27, Jagan Teki wrote:
> This initial version supports CPU, dma, interrupts, timers, UART and
> SDHCI (everything necessary to boot Linux on this system on chip) as
> well as Ethernet, I2C, PWM and SPI.
>
> The DT is split into rk3588 and rk3588s, which is a reduced version
> (i.e. with less peripherals) of the former.
>
> commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588
> SoC")
> commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data")
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
[snip]
> +
> + cru: clock-controller@fd7c0000 {
> + compatible = "rockchip,rk3588-cru";
> + reg = <0x0 0xfd7c0000 0x0 0x5c000>;
> + assigned-clocks =
> + <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
> + <&cru PLL_NPLL>, <&cru PLL_GPLL>,
> + <&cru ACLK_CENTER_ROOT>,
> + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
> + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
> + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
Hi Jagan,
This clock PCLK_PMU0_ROOT is assigned here a clock rate (100 Mhz), but
your patch clk: rockchip: Add rk3588 clk support , in function
rk3588_clk_set_rate , does not take into account the PCLK_PMU0_ROOT ,
hence there is an error printed :
rk3588_clk_set_rate(clk=37fc28, rate=100000000): unknown clock id=646
(switch statement exits on default branch )
Could you have a look please?
Thanks,
Eugen
> + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
> + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
> + <&cru CLK_GPU>;
> + assigned-clock-rates =
> + <100000000>, <786432000>,
> + <850000000>, <1188000000>,
> + <702000000>,
> + <400000000>, <500000000>,
> + <800000000>, <100000000>,
> + <400000000>, <100000000>,
> + <200000000>, <500000000>,
> + <375000000>, <150000000>,
> + <200000000>;
> + rockchip,grf = <&php_grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 05/16] clk: rockchip: Add rk3588 clk support
2023-01-25 22:27 ` [RFC PATCH 05/16] clk: rockchip: Add rk3588 clk support Jagan Teki
@ 2023-02-02 14:09 ` Eugen Hristev
0 siblings, 0 replies; 56+ messages in thread
From: Eugen Hristev @ 2023-02-02 14:09 UTC (permalink / raw)
To: Jagan Teki, Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat
Cc: u-boot, Elaine Zhang
On 1/26/23 00:27, Jagan Teki wrote:
> Add clock driver support for Rockchip RK3588 SoC.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3588.c | 2019 +++++++++++++++++++++++++++++
> 2 files changed, 2020 insertions(+)
> create mode 100644 drivers/clk/rockchip/clk_rk3588.c
>
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index f719f4e379..9e379cc2e3 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -16,5 +16,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
> +obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
> new file mode 100644
> index 0000000000..55532b5c2a
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3588.c
> @@ -0,0 +1,2019 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
> +
> +#include <common.h>
> +#include <bitfield.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/cru_rk3588.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <asm/io.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rockchip,rk3588-cru.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
> + /* _mhz, _p, _m, _s, _k */
> + RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
> + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
> + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
> + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
> + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
> + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
> + RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
> + RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
> + RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
> + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
> + RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
> + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
> + RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
> + RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
> + RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
> + RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
> + { /* sentinel */ },
> +};
> +
> +static struct rockchip_pll_clock rk3588_pll_clks[] = {
> + [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0),
> + RK3588_B0_PLL_MODE_CON, 0, 15, 0,
> + rk3588_pll_rates),
> + [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8),
> + RK3588_B1_PLL_MODE_CON, 0, 15, 0,
> + rk3588_pll_rates),
> + [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16),
> + RK3588_LPLL_MODE_CON, 0, 15, 0, rk3588_pll_rates),
> + [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
> + RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
> + [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),
> + RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
> + [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
> + RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
> + [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
> + RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
> + [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
> + RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
> + [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
> + RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
> +};
> +
> +#ifndef CONFIG_SPL_BUILD
> +/*
> + *
> + * rational_best_approximation(31415, 10000,
> + * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
> + *
> + * you may look at given_numerator as a fixed point number,
> + * with the fractional part size described in given_denominator.
> + *
> + * for theoretical background, see:
> + * http://en.wikipedia.org/wiki/Continued_fraction
> + */
> +static void rational_best_approximation(unsigned long given_numerator,
> + unsigned long given_denominator,
> + unsigned long max_numerator,
> + unsigned long max_denominator,
> + unsigned long *best_numerator,
> + unsigned long *best_denominator)
> +{
> + unsigned long n, d, n0, d0, n1, d1;
> +
> + n = given_numerator;
> + d = given_denominator;
> + n0 = 0;
> + d1 = 0;
> + n1 = 1;
> + d0 = 1;
> + for (;;) {
> + unsigned long t, a;
> +
> + if (n1 > max_numerator || d1 > max_denominator) {
> + n1 = n0;
> + d1 = d0;
> + break;
> + }
> + if (d == 0)
> + break;
> + t = d;
> + a = n / d;
> + d = n % d;
> + n = t;
> + t = n0 + a * n1;
> + n0 = n1;
> + n1 = t;
> + t = d0 + a * d1;
> + d0 = d1;
> + d1 = t;
> + }
> + *best_numerator = n1;
> + *best_denominator = d1;
> +}
> +#endif
> +
> +static ulong rk3588_center_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 con, sel, rate;
> +
> + switch (clk_id) {
> + case ACLK_CENTER_ROOT:
> + con = readl(&cru->clksel_con[165]);
> + sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >>
> + ACLK_CENTER_ROOT_SEL_SHIFT;
> + if (sel == ACLK_CENTER_ROOT_SEL_700M)
> + rate = 702 * MHz;
> + else if (sel == ACLK_CENTER_ROOT_SEL_400M)
> + rate = 396 * MHz;
> + else if (sel == ACLK_CENTER_ROOT_SEL_200M)
> + rate = 200 * MHz;
> + else
> + rate = OSC_HZ;
> + break;
> + case ACLK_CENTER_LOW_ROOT:
> + con = readl(&cru->clksel_con[165]);
> + sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >>
> + ACLK_CENTER_LOW_ROOT_SEL_SHIFT;
> + if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M)
> + rate = 500 * MHz;
> + else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M)
> + rate = 250 * MHz;
> + else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M)
> + rate = 100 * MHz;
> + else
> + rate = OSC_HZ;
> + break;
> + case HCLK_CENTER_ROOT:
> + con = readl(&cru->clksel_con[165]);
> + sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >>
> + HCLK_CENTER_ROOT_SEL_SHIFT;
> + if (sel == HCLK_CENTER_ROOT_SEL_400M)
> + rate = 396 * MHz;
> + else if (sel == HCLK_CENTER_ROOT_SEL_200M)
> + rate = 200 * MHz;
> + else if (sel == HCLK_CENTER_ROOT_SEL_100M)
> + rate = 100 * MHz;
> + else
> + rate = OSC_HZ;
> + break;
> + case PCLK_CENTER_ROOT:
> + con = readl(&cru->clksel_con[165]);
> + sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >>
> + PCLK_CENTER_ROOT_SEL_SHIFT;
> + if (sel == PCLK_CENTER_ROOT_SEL_200M)
> + rate = 200 * MHz;
> + else if (sel == PCLK_CENTER_ROOT_SEL_100M)
> + rate = 100 * MHz;
> + else if (sel == PCLK_CENTER_ROOT_SEL_50M)
> + rate = 50 * MHz;
> + else
> + rate = OSC_HZ;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk3588_center_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk;
> +
> + switch (clk_id) {
> + case ACLK_CENTER_ROOT:
> + if (rate >= 700 * MHz)
> + src_clk = ACLK_CENTER_ROOT_SEL_700M;
> + else if (rate >= 396 * MHz)
> + src_clk = ACLK_CENTER_ROOT_SEL_400M;
> + else if (rate >= 200 * MHz)
> + src_clk = ACLK_CENTER_ROOT_SEL_200M;
> + else
> + src_clk = ACLK_CENTER_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[165],
> + ACLK_CENTER_ROOT_SEL_MASK,
> + src_clk << ACLK_CENTER_ROOT_SEL_SHIFT);
> + break;
> + case ACLK_CENTER_LOW_ROOT:
> + if (rate >= 500 * MHz)
> + src_clk = ACLK_CENTER_LOW_ROOT_SEL_500M;
> + else if (rate >= 250 * MHz)
> + src_clk = ACLK_CENTER_LOW_ROOT_SEL_250M;
> + else if (rate >= 99 * MHz)
> + src_clk = ACLK_CENTER_LOW_ROOT_SEL_100M;
> + else
> + src_clk = ACLK_CENTER_LOW_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[165],
> + ACLK_CENTER_LOW_ROOT_SEL_MASK,
> + src_clk << ACLK_CENTER_LOW_ROOT_SEL_SHIFT);
> + break;
> + case HCLK_CENTER_ROOT:
> + if (rate >= 396 * MHz)
> + src_clk = HCLK_CENTER_ROOT_SEL_400M;
> + else if (rate >= 198 * MHz)
> + src_clk = HCLK_CENTER_ROOT_SEL_200M;
> + else if (rate >= 99 * MHz)
> + src_clk = HCLK_CENTER_ROOT_SEL_100M;
> + else
> + src_clk = HCLK_CENTER_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[165],
> + HCLK_CENTER_ROOT_SEL_MASK,
> + src_clk << HCLK_CENTER_ROOT_SEL_SHIFT);
> + break;
> + case PCLK_CENTER_ROOT:
> + if (rate >= 198 * MHz)
> + src_clk = PCLK_CENTER_ROOT_SEL_200M;
> + else if (rate >= 99 * MHz)
> + src_clk = PCLK_CENTER_ROOT_SEL_100M;
> + else if (rate >= 50 * MHz)
> + src_clk = PCLK_CENTER_ROOT_SEL_50M;
> + else
> + src_clk = PCLK_CENTER_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[165],
> + PCLK_CENTER_ROOT_SEL_MASK,
> + src_clk << PCLK_CENTER_ROOT_SEL_SHIFT);
> + break;
> + default:
> + printf("do not support this center freq\n");
> + return -EINVAL;
> + }
> +
> + return rk3588_center_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_top_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 con, sel, div, rate, prate;
> +
> + switch (clk_id) {
> + case ACLK_TOP_ROOT:
> + con = readl(&cru->clksel_con[8]);
> + div = (con & ACLK_TOP_ROOT_DIV_MASK) >>
> + ACLK_TOP_ROOT_DIV_SHIFT;
> + sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >>
> + ACLK_TOP_ROOT_SRC_SEL_SHIFT;
> + if (sel == ACLK_TOP_ROOT_SRC_SEL_CPLL)
> + prate = priv->cpll_hz;
> + else
> + prate = priv->cpll_hz;
> + return DIV_TO_RATE(prate, div);
> + case ACLK_LOW_TOP_ROOT:
> + con = readl(&cru->clksel_con[8]);
> + div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >>
> + ACLK_LOW_TOP_ROOT_DIV_SHIFT;
> + sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >>
> + ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT;
> + if (sel == ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL)
> + prate = priv->cpll_hz;
> + else
> + prate = priv->gpll_hz;
> + return DIV_TO_RATE(prate, div);
> + case PCLK_TOP_ROOT:
> + con = readl(&cru->clksel_con[8]);
> + sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT;
> + if (sel == PCLK_TOP_ROOT_SEL_100M)
> + rate = 100 * MHz;
> + else if (sel == PCLK_TOP_ROOT_SEL_50M)
> + rate = 50 * MHz;
> + else
> + rate = OSC_HZ;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk, src_clk_div;
> +
> + switch (clk_id) {
> + case ACLK_TOP_ROOT:
> + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + assert(src_clk_div - 1 <= 31);
> + rk_clrsetreg(&cru->clksel_con[8],
> + ACLK_TOP_ROOT_DIV_MASK |
> + ACLK_TOP_ROOT_SRC_SEL_MASK,
> + (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
> + ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
> + (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
> + break;
> + case ACLK_LOW_TOP_ROOT:
> + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + assert(src_clk_div - 1 <= 31);
> + rk_clrsetreg(&cru->clksel_con[8],
> + ACLK_LOW_TOP_ROOT_DIV_MASK |
> + ACLK_LOW_TOP_ROOT_SRC_SEL_MASK,
> + (ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL <<
> + ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT) |
> + (src_clk_div - 1) << ACLK_LOW_TOP_ROOT_DIV_SHIFT);
> + break;
> + case PCLK_TOP_ROOT:
> + if (rate == 100 * MHz)
> + src_clk = PCLK_TOP_ROOT_SEL_100M;
> + else if (rate == 50 * MHz)
> + src_clk = PCLK_TOP_ROOT_SEL_50M;
> + else
> + src_clk = PCLK_TOP_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[8],
> + PCLK_TOP_ROOT_SEL_MASK,
> + src_clk << PCLK_TOP_ROOT_SEL_SHIFT);
> + break;
> + default:
> + printf("do not support this top freq\n");
> + return -EINVAL;
> + }
> +
> + return rk3588_top_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_i2c_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 sel, con;
> + ulong rate;
> +
> + switch (clk_id) {
> + case CLK_I2C0:
> + con = readl(&cru->pmuclksel_con[3]);
> + sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;
> + break;
> + case CLK_I2C1:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;
> + break;
> + case CLK_I2C2:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;
> + break;
> + case CLK_I2C3:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;
> + break;
> + case CLK_I2C4:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;
> + break;
> + case CLK_I2C5:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;
> + break;
> + case CLK_I2C6:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;
> + break;
> + case CLK_I2C7:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;
> + break;
> + case CLK_I2C8:
> + con = readl(&cru->clksel_con[38]);
> + sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> + if (sel == CLK_I2C_SEL_200M)
> + rate = 200 * MHz;
> + else
> + rate = 100 * MHz;
> +
> + return rate;
> +}
> +
> +static ulong rk3588_i2c_set_clk(struct rk3588_clk_priv *priv, ulong clk_id,
> + ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk;
> +
> + if (rate >= 198 * MHz)
> + src_clk = CLK_I2C_SEL_200M;
> + else
> + src_clk = CLK_I2C_SEL_100M;
> +
> + switch (clk_id) {
> + case CLK_I2C0:
> + rk_clrsetreg(&cru->pmuclksel_con[3], CLK_I2C0_SEL_MASK,
> + src_clk << CLK_I2C0_SEL_SHIFT);
> + break;
> + case CLK_I2C1:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C1_SEL_MASK,
> + src_clk << CLK_I2C1_SEL_SHIFT);
> + break;
> + case CLK_I2C2:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C2_SEL_MASK,
> + src_clk << CLK_I2C2_SEL_SHIFT);
> + break;
> + case CLK_I2C3:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C3_SEL_MASK,
> + src_clk << CLK_I2C3_SEL_SHIFT);
> + break;
> + case CLK_I2C4:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C4_SEL_MASK,
> + src_clk << CLK_I2C4_SEL_SHIFT);
> + break;
> + case CLK_I2C5:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C5_SEL_MASK,
> + src_clk << CLK_I2C5_SEL_SHIFT);
> + break;
> + case CLK_I2C6:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C6_SEL_MASK,
> + src_clk << CLK_I2C6_SEL_SHIFT);
> + break;
> + case CLK_I2C7:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C7_SEL_MASK,
> + src_clk << CLK_I2C7_SEL_SHIFT);
> + break;
> + case CLK_I2C8:
> + rk_clrsetreg(&cru->clksel_con[38], CLK_I2C8_SEL_MASK,
> + src_clk << CLK_I2C8_SEL_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_i2c_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_spi_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 sel, con;
> +
> + con = readl(&cru->clksel_con[59]);
> +
> + switch (clk_id) {
> + case CLK_SPI0:
> + sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
> + break;
> + case CLK_SPI1:
> + sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
> + break;
> + case CLK_SPI2:
> + sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
> + break;
> + case CLK_SPI3:
> + sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
> + break;
> + case CLK_SPI4:
> + sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + switch (sel) {
> + case CLK_SPI_SEL_200M:
> + return 200 * MHz;
> + case CLK_SPI_SEL_150M:
> + return 150 * MHz;
> + case CLK_SPI_SEL_24M:
> + return OSC_HZ;
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_spi_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk;
> +
> + if (rate >= 198 * MHz)
> + src_clk = CLK_SPI_SEL_200M;
> + else if (rate >= 140 * MHz)
> + src_clk = CLK_SPI_SEL_150M;
> + else
> + src_clk = CLK_SPI_SEL_24M;
> +
> + switch (clk_id) {
> + case CLK_SPI0:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_SPI0_SEL_MASK,
> + src_clk << CLK_SPI0_SEL_SHIFT);
> + break;
> + case CLK_SPI1:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_SPI1_SEL_MASK,
> + src_clk << CLK_SPI1_SEL_SHIFT);
> + break;
> + case CLK_SPI2:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_SPI2_SEL_MASK,
> + src_clk << CLK_SPI2_SEL_SHIFT);
> + break;
> + case CLK_SPI3:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_SPI3_SEL_MASK,
> + src_clk << CLK_SPI3_SEL_SHIFT);
> + break;
> + case CLK_SPI4:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_SPI4_SEL_MASK,
> + src_clk << CLK_SPI4_SEL_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_spi_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_pwm_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 sel, con;
> +
> + switch (clk_id) {
> + case CLK_PWM1:
> + con = readl(&cru->clksel_con[59]);
> + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
> + break;
> + case CLK_PWM2:
> + con = readl(&cru->clksel_con[59]);
> + sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
> + break;
> + case CLK_PWM3:
> + con = readl(&cru->clksel_con[60]);
> + sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
> + break;
> + case CLK_PMU1PWM:
> + con = readl(&cru->pmuclksel_con[2]);
> + sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + switch (sel) {
> + case CLK_PWM_SEL_100M:
> + return 100 * MHz;
> + case CLK_PWM_SEL_50M:
> + return 50 * MHz;
> + case CLK_PWM_SEL_24M:
> + return OSC_HZ;
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_pwm_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk;
> +
> + if (rate >= 99 * MHz)
> + src_clk = CLK_PWM_SEL_100M;
> + else if (rate >= 50 * MHz)
> + src_clk = CLK_PWM_SEL_50M;
> + else
> + src_clk = CLK_PWM_SEL_24M;
> +
> + switch (clk_id) {
> + case CLK_PWM1:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_PWM1_SEL_MASK,
> + src_clk << CLK_PWM1_SEL_SHIFT);
> + break;
> + case CLK_PWM2:
> + rk_clrsetreg(&cru->clksel_con[59],
> + CLK_PWM2_SEL_MASK,
> + src_clk << CLK_PWM2_SEL_SHIFT);
> + break;
> + case CLK_PWM3:
> + rk_clrsetreg(&cru->clksel_con[60],
> + CLK_PWM3_SEL_MASK,
> + src_clk << CLK_PWM3_SEL_SHIFT);
> + break;
> + case CLK_PMU1PWM:
> + rk_clrsetreg(&cru->pmuclksel_con[2],
> + CLK_PMU1PWM_SEL_MASK,
> + src_clk << CLK_PMU1PWM_SEL_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_pwm_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_adc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 div, sel, con, prate;
> +
> + switch (clk_id) {
> + case CLK_SARADC:
> + con = readl(&cru->clksel_con[40]);
> + div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
> + sel = (con & CLK_SARADC_SEL_MASK) >>
> + CLK_SARADC_SEL_SHIFT;
> + if (sel == CLK_SARADC_SEL_24M)
> + prate = OSC_HZ;
> + else
> + prate = priv->gpll_hz;
> + return DIV_TO_RATE(prate, div);
> + case CLK_TSADC:
> + con = readl(&cru->clksel_con[41]);
> + div = (con & CLK_TSADC_DIV_MASK) >>
> + CLK_TSADC_DIV_SHIFT;
> + sel = (con & CLK_TSADC_SEL_MASK) >>
> + CLK_TSADC_SEL_SHIFT;
> + if (sel == CLK_TSADC_SEL_24M)
> + prate = OSC_HZ;
> + else
> + prate = 100 * MHz;
> + return DIV_TO_RATE(prate, div);
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_adc_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk_div;
> +
> + switch (clk_id) {
> + case CLK_SARADC:
> + if (!(OSC_HZ % rate)) {
> + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
> + assert(src_clk_div - 1 <= 255);
> + rk_clrsetreg(&cru->clksel_con[40],
> + CLK_SARADC_SEL_MASK |
> + CLK_SARADC_DIV_MASK,
> + (CLK_SARADC_SEL_24M <<
> + CLK_SARADC_SEL_SHIFT) |
> + (src_clk_div - 1) <<
> + CLK_SARADC_DIV_SHIFT);
> + } else {
> + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + assert(src_clk_div - 1 <= 255);
> + rk_clrsetreg(&cru->clksel_con[40],
> + CLK_SARADC_SEL_MASK |
> + CLK_SARADC_DIV_MASK,
> + (CLK_SARADC_SEL_GPLL <<
> + CLK_SARADC_SEL_SHIFT) |
> + (src_clk_div - 1) <<
> + CLK_SARADC_DIV_SHIFT);
> + }
> + break;
> + case CLK_TSADC:
> + if (!(OSC_HZ % rate)) {
> + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
> + assert(src_clk_div - 1 <= 255);
> + rk_clrsetreg(&cru->clksel_con[41],
> + CLK_TSADC_SEL_MASK |
> + CLK_TSADC_DIV_MASK,
> + (CLK_TSADC_SEL_24M <<
> + CLK_TSADC_SEL_SHIFT) |
> + (src_clk_div - 1) <<
> + CLK_TSADC_DIV_SHIFT);
> + } else {
> + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + assert(src_clk_div - 1 <= 7);
> + rk_clrsetreg(&cru->clksel_con[41],
> + CLK_TSADC_SEL_MASK |
> + CLK_TSADC_DIV_MASK,
> + (CLK_TSADC_SEL_GPLL <<
> + CLK_TSADC_SEL_SHIFT) |
> + (src_clk_div - 1) <<
> + CLK_TSADC_DIV_SHIFT);
> + }
> + break;
> + default:
> + return -ENOENT;
> + }
> + return rk3588_adc_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_mmc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 sel, con, div, prate;
> +
> + switch (clk_id) {
> + case CCLK_SRC_SDIO:
> + con = readl(&cru->clksel_con[172]);
> + div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;
> + sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>
> + CCLK_SDIO_SRC_SEL_SHIFT;
> + if (sel == CCLK_SDIO_SRC_SEL_GPLL)
> + prate = priv->gpll_hz;
> + else if (sel == CCLK_SDIO_SRC_SEL_CPLL)
> + prate = priv->cpll_hz;
> + else
> + prate = OSC_HZ;
> + return DIV_TO_RATE(prate, div);
> + case CCLK_EMMC:
> + con = readl(&cru->clksel_con[77]);
> + div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
> + sel = (con & CCLK_EMMC_SEL_MASK) >>
> + CCLK_EMMC_SEL_SHIFT;
> + if (sel == CCLK_EMMC_SEL_GPLL)
> + prate = priv->gpll_hz;
> + else if (sel == CCLK_EMMC_SEL_CPLL)
> + prate = priv->cpll_hz;
> + else
> + prate = OSC_HZ;
> + return DIV_TO_RATE(prate, div);
> + case BCLK_EMMC:
> + con = readl(&cru->clksel_con[78]);
> + div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;
> + sel = (con & BCLK_EMMC_SEL_MASK) >>
> + BCLK_EMMC_SEL_SHIFT;
> + if (sel == CCLK_EMMC_SEL_CPLL)
> + prate = priv->cpll_hz;
> + else
> + prate = priv->gpll_hz;
> + return DIV_TO_RATE(prate, div);
> + case SCLK_SFC:
> + con = readl(&cru->clksel_con[78]);
> + div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;
> + sel = (con & SCLK_SFC_SEL_MASK) >>
> + SCLK_SFC_SEL_SHIFT;
> + if (sel == SCLK_SFC_SEL_GPLL)
> + prate = priv->gpll_hz;
> + else if (sel == SCLK_SFC_SEL_CPLL)
> + prate = priv->cpll_hz;
> + else
> + prate = OSC_HZ;
> + return DIV_TO_RATE(prate, div);
> + case DCLK_DECOM:
> + con = readl(&cru->clksel_con[62]);
> + div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;
> + sel = (con & DCLK_DECOM_SEL_MASK) >>
> + DCLK_DECOM_SEL_SHIFT;
> + if (sel == DCLK_DECOM_SEL_SPLL)
> + prate = 702 * MHz;
> + else
> + prate = priv->gpll_hz;
> + return DIV_TO_RATE(prate, div);
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk, div;
> +
> + switch (clk_id) {
> + case CCLK_SRC_SDIO:
> + case CCLK_EMMC:
> + case SCLK_SFC:
> + if (!(OSC_HZ % rate)) {
> + src_clk = SCLK_SFC_SEL_24M;
> + div = DIV_ROUND_UP(OSC_HZ, rate);
> + } else if (!(priv->cpll_hz % rate)) {
> + src_clk = SCLK_SFC_SEL_CPLL;
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> + } else {
> + src_clk = SCLK_SFC_SEL_GPLL;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + }
> + break;
> + case BCLK_EMMC:
> + if (!(priv->cpll_hz % rate)) {
> + src_clk = CCLK_EMMC_SEL_CPLL;
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> + } else {
> + src_clk = CCLK_EMMC_SEL_GPLL;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + }
> + break;
> + case DCLK_DECOM:
> + if (!(702 * MHz % rate)) {
> + src_clk = DCLK_DECOM_SEL_SPLL;
> + div = DIV_ROUND_UP(702 * MHz, rate);
> + } else {
> + src_clk = DCLK_DECOM_SEL_GPLL;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + }
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + switch (clk_id) {
> + case CCLK_SRC_SDIO:
> + rk_clrsetreg(&cru->clksel_con[172],
> + CCLK_SDIO_SRC_SEL_MASK |
> + CCLK_SDIO_SRC_DIV_MASK,
> + (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) |
> + (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);
> + break;
> + case CCLK_EMMC:
> + rk_clrsetreg(&cru->clksel_con[77],
> + CCLK_EMMC_SEL_MASK |
> + CCLK_EMMC_DIV_MASK,
> + (src_clk << CCLK_EMMC_SEL_SHIFT) |
> + (div - 1) << CCLK_EMMC_DIV_SHIFT);
> + break;
> + case BCLK_EMMC:
> + rk_clrsetreg(&cru->clksel_con[78],
> + BCLK_EMMC_DIV_MASK |
> + BCLK_EMMC_SEL_MASK,
> + (src_clk << BCLK_EMMC_SEL_SHIFT) |
> + (div - 1) << BCLK_EMMC_DIV_SHIFT);
> + break;
> + case SCLK_SFC:
> + rk_clrsetreg(&cru->clksel_con[78],
> + SCLK_SFC_DIV_MASK |
> + SCLK_SFC_SEL_MASK,
> + (src_clk << SCLK_SFC_SEL_SHIFT) |
> + (div - 1) << SCLK_SFC_DIV_SHIFT);
> + break;
> + case DCLK_DECOM:
> + rk_clrsetreg(&cru->clksel_con[62],
> + DCLK_DECOM_DIV_MASK |
> + DCLK_DECOM_SEL_MASK,
> + (src_clk << DCLK_DECOM_SEL_SHIFT) |
> + (div - 1) << DCLK_DECOM_DIV_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_mmc_get_clk(priv, clk_id);
> +}
> +
> +#ifndef CONFIG_SPL_BUILD
> +static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 div, con, parent;
> +
> + parent = priv->gpll_hz;
> + con = readl(&cru->clksel_con[117]);
> +
> + switch (clk_id) {
> + case CLK_AUX16M_0:
> + div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT;
> + return DIV_TO_RATE(parent, div);
> + case CLK_AUX16M_1:
> + div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT;
> + return DIV_TO_RATE(parent, div);
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_aux16m_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 div;
> +
> + if (!priv->gpll_hz) {
> + printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
> + return -ENOENT;
> + }
> +
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> +
> + switch (clk_id) {
> + case CLK_AUX16M_0:
> + rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_0_DIV_MASK,
> + (div - 1) << CLK_AUX16MHZ_0_DIV_SHIFT);
> + break;
> + case CLK_AUX16M_1:
> + rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_1_DIV_MASK,
> + (div - 1) << CLK_AUX16MHZ_1_DIV_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_aux16m_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_aclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 div, sel, con, parent;
> +
> + switch (clk_id) {
> + case ACLK_VOP_ROOT:
> + case ACLK_VOP:
> + con = readl(&cru->clksel_con[110]);
> + div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;
> + sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;
> + if (sel == ACLK_VOP_ROOT_SEL_GPLL)
> + parent = priv->gpll_hz;
> + else if (sel == ACLK_VOP_ROOT_SEL_CPLL)
> + parent = priv->cpll_hz;
> + else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)
> + parent = priv->aupll_hz;
> + else if (sel == ACLK_VOP_ROOT_SEL_NPLL)
> + parent = priv->npll_hz;
> + else
> + parent = 702 * MHz;
> + return DIV_TO_RATE(parent, div);
> + case ACLK_VOP_LOW_ROOT:
> + con = readl(&cru->clksel_con[110]);
> + sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >>
> + ACLK_VOP_LOW_ROOT_SEL_SHIFT;
> + if (sel == ACLK_VOP_LOW_ROOT_SEL_400M)
> + return 396 * MHz;
> + else if (sel == ACLK_VOP_LOW_ROOT_SEL_200M)
> + return 200 * MHz;
> + else if (sel == ACLK_VOP_LOW_ROOT_SEL_100M)
> + return 100 * MHz;
> + else
> + return OSC_HZ;
> + case HCLK_VOP_ROOT:
> + con = readl(&cru->clksel_con[110]);
> + sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;
> + if (sel == HCLK_VOP_ROOT_SEL_200M)
> + return 200 * MHz;
> + else if (sel == HCLK_VOP_ROOT_SEL_100M)
> + return 100 * MHz;
> + else if (sel == HCLK_VOP_ROOT_SEL_50M)
> + return 50 * MHz;
> + else
> + return OSC_HZ;
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_aclk_vop_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int src_clk, div;
> +
> + switch (clk_id) {
> + case ACLK_VOP_ROOT:
> + case ACLK_VOP:
> + if (rate >= 850 * MHz) {
> + src_clk = ACLK_VOP_ROOT_SEL_NPLL;
> + div = 1;
> + } else if (rate >= 750 * MHz) {
> + src_clk = ACLK_VOP_ROOT_SEL_CPLL;
> + div = 2;
> + } else if (rate >= 700 * MHz) {
> + src_clk = ACLK_VOP_ROOT_SEL_SPLL;
> + div = 1;
> + } else if (!(priv->cpll_hz % rate)) {
> + src_clk = ACLK_VOP_ROOT_SEL_CPLL;
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> + } else {
> + src_clk = ACLK_VOP_ROOT_SEL_GPLL;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + }
> + rk_clrsetreg(&cru->clksel_con[110],
> + ACLK_VOP_ROOT_DIV_MASK |
> + ACLK_VOP_ROOT_SEL_MASK,
> + (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) |
> + (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);
> + break;
> + case ACLK_VOP_LOW_ROOT:
> + if (rate == 400 * MHz || rate == 396 * MHz)
> + src_clk = ACLK_VOP_LOW_ROOT_SEL_400M;
> + else if (rate == 200 * MHz)
> + src_clk = ACLK_VOP_LOW_ROOT_SEL_200M;
> + else if (rate == 100 * MHz)
> + src_clk = ACLK_VOP_LOW_ROOT_SEL_100M;
> + else
> + src_clk = ACLK_VOP_LOW_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[110],
> + ACLK_VOP_LOW_ROOT_SEL_MASK,
> + src_clk << ACLK_VOP_LOW_ROOT_SEL_SHIFT);
> + break;
> + case HCLK_VOP_ROOT:
> + if (rate == 200 * MHz)
> + src_clk = HCLK_VOP_ROOT_SEL_200M;
> + else if (rate == 100 * MHz)
> + src_clk = HCLK_VOP_ROOT_SEL_100M;
> + else if (rate == 50 * MHz)
> + src_clk = HCLK_VOP_ROOT_SEL_50M;
> + else
> + src_clk = HCLK_VOP_ROOT_SEL_24M;
> + rk_clrsetreg(&cru->clksel_con[110],
> + HCLK_VOP_ROOT_SEL_MASK,
> + src_clk << HCLK_VOP_ROOT_SEL_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_aclk_vop_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_dclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 div, sel, con, parent;
> +
> + switch (clk_id) {
> + case DCLK_VOP0:
> + case DCLK_VOP0_SRC:
> + con = readl(&cru->clksel_con[111]);
> + div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
> + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
> + break;
> + case DCLK_VOP1:
> + case DCLK_VOP1_SRC:
> + con = readl(&cru->clksel_con[111]);
> + div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT;
> + sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;
> + break;
> + case DCLK_VOP2:
> + case DCLK_VOP2_SRC:
> + con = readl(&cru->clksel_con[112]);
> + div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT;
> + sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;
> + break;
> + case DCLK_VOP3:
> + con = readl(&cru->clksel_con[113]);
> + div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT;
> + sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + if (sel == DCLK_VOP_SRC_SEL_AUPLL)
> + parent = priv->aupll_hz;
> + else if (sel == DCLK_VOP_SRC_SEL_V0PLL)
> + parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
> + priv->cru, V0PLL);
> + else if (sel == DCLK_VOP_SRC_SEL_GPLL)
> + parent = priv->gpll_hz;
> + else if (sel == DCLK_VOP_SRC_SEL_CPLL)
> + parent = priv->cpll_hz;
> + else
> + return -ENOENT;
> +
> + return DIV_TO_RATE(parent, div);
> +}
> +
> +#define RK3588_VOP_PLL_LIMIT_FREQ 600000000
> +
> +static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + ulong pll_rate, now, best_rate = 0;
> + u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
> + u32 mask, div_shift, sel_shift;
> +
> + switch (clk_id) {
> + case DCLK_VOP0:
> + case DCLK_VOP0_SRC:
> + conid = 111;
> + con = readl(&cru->clksel_con[111]);
> + sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
> + mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
> + div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
> + sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
> + break;
> + case DCLK_VOP1:
> + case DCLK_VOP1_SRC:
> + conid = 111;
> + con = readl(&cru->clksel_con[111]);
> + sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;
> + mask = DCLK1_VOP_SRC_SEL_MASK | DCLK1_VOP_SRC_DIV_MASK;
> + div_shift = DCLK1_VOP_SRC_DIV_SHIFT;
> + sel_shift = DCLK1_VOP_SRC_SEL_SHIFT;
> + break;
> + case DCLK_VOP2:
> + case DCLK_VOP2_SRC:
> + conid = 112;
> + con = readl(&cru->clksel_con[112]);
> + sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;
> + mask = DCLK2_VOP_SRC_SEL_MASK | DCLK2_VOP_SRC_DIV_MASK;
> + div_shift = DCLK2_VOP_SRC_DIV_SHIFT;
> + sel_shift = DCLK2_VOP_SRC_SEL_SHIFT;
> + break;
> + case DCLK_VOP3:
> + conid = 113;
> + con = readl(&cru->clksel_con[113]);
> + sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
> + mask = DCLK3_VOP_SRC_SEL_MASK | DCLK3_VOP_SRC_DIV_MASK;
> + div_shift = DCLK3_VOP_SRC_DIV_SHIFT;
> + sel_shift = DCLK3_VOP_SRC_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + if (sel == DCLK_VOP_SRC_SEL_V0PLL) {
> + div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
> + rk_clrsetreg(&cru->clksel_con[conid],
> + mask,
> + DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
> + ((div - 1) << div_shift));
> + rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
> + priv->cru, V0PLL, div * rate);
> + } else {
> + for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
> + switch (i) {
> + case DCLK_VOP_SRC_SEL_GPLL:
> + pll_rate = priv->gpll_hz;
> + break;
> + case DCLK_VOP_SRC_SEL_CPLL:
> + pll_rate = priv->cpll_hz;
> + break;
> + case DCLK_VOP_SRC_SEL_AUPLL:
> + pll_rate = priv->aupll_hz;
> + break;
> + case DCLK_VOP_SRC_SEL_V0PLL:
> + pll_rate = 0;
> + break;
> + default:
> + printf("do not support this vop pll sel\n");
> + return -EINVAL;
> + }
> +
> + div = DIV_ROUND_UP(pll_rate, rate);
> + if (div > 255)
> + continue;
> + now = pll_rate / div;
> + if (abs(rate - now) < abs(rate - best_rate)) {
> + best_rate = now;
> + best_div = div;
> + best_sel = i;
> + }
> + debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
> + pll_rate, best_rate, best_div, best_sel);
> + }
> +
> + if (best_rate) {
> + rk_clrsetreg(&cru->clksel_con[conid],
> + mask,
> + best_sel << sel_shift |
> + (best_div - 1) << div_shift);
> + } else {
> + printf("do not support this vop freq %lu\n", rate);
> + return -EINVAL;
> + }
> + }
> + return rk3588_dclk_vop_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_gmac_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 con, div;
> +
> + switch (clk_id) {
> + case CLK_GMAC0_PTP_REF:
> + con = readl(&cru->clksel_con[81]);
> + div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
> + return DIV_TO_RATE(priv->cpll_hz, div);
> + case CLK_GMAC1_PTP_REF:
> + con = readl(&cru->clksel_con[81]);
> + div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT;
> + return DIV_TO_RATE(priv->cpll_hz, div);
> + case CLK_GMAC_125M:
> + con = readl(&cru->clksel_con[83]);
> + div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT;
> + return DIV_TO_RATE(priv->cpll_hz, div);
> + case CLK_GMAC_50M:
> + con = readl(&cru->clksel_con[84]);
> + div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT;
> + return DIV_TO_RATE(priv->cpll_hz, div);
> + default:
> + return -ENOENT;
> + }
> +}
> +
> +static ulong rk3588_gmac_set_clk(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + int div;
> +
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> +
> + switch (clk_id) {
> + case CLK_GMAC0_PTP_REF:
> + rk_clrsetreg(&cru->clksel_con[81],
> + CLK_GMAC0_PTP_DIV_MASK | CLK_GMAC0_PTP_SEL_MASK,
> + CLK_GMAC0_PTP_SEL_CPLL << CLK_GMAC0_PTP_SEL_SHIFT |
> + (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);
> + break;
> + case CLK_GMAC1_PTP_REF:
> + rk_clrsetreg(&cru->clksel_con[81],
> + CLK_GMAC1_PTP_DIV_MASK | CLK_GMAC1_PTP_SEL_MASK,
> + CLK_GMAC1_PTP_SEL_CPLL << CLK_GMAC1_PTP_SEL_SHIFT |
> + (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);
> + break;
> +
> + case CLK_GMAC_125M:
> + rk_clrsetreg(&cru->clksel_con[83],
> + CLK_GMAC_125M_DIV_MASK | CLK_GMAC_125M_SEL_MASK,
> + CLK_GMAC_125M_SEL_CPLL << CLK_GMAC_125M_SEL_SHIFT |
> + (div - 1) << CLK_GMAC_125M_DIV_SHIFT);
> + break;
> + case CLK_GMAC_50M:
> + rk_clrsetreg(&cru->clksel_con[84],
> + CLK_GMAC_50M_DIV_MASK | CLK_GMAC_50M_SEL_MASK,
> + CLK_GMAC_50M_SEL_CPLL << CLK_GMAC_50M_SEL_SHIFT |
> + (div - 1) << CLK_GMAC_50M_DIV_SHIFT);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_gmac_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3588_uart_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 reg, con, fracdiv, div, src, p_src, p_rate;
> + unsigned long m, n;
> +
> + switch (clk_id) {
> + case SCLK_UART1:
> + reg = 41;
> + break;
> + case SCLK_UART2:
> + reg = 43;
> + break;
> + case SCLK_UART3:
> + reg = 45;
> + break;
> + case SCLK_UART4:
> + reg = 47;
> + break;
> + case SCLK_UART5:
> + reg = 49;
> + break;
> + case SCLK_UART6:
> + reg = 51;
> + break;
> + case SCLK_UART7:
> + reg = 53;
> + break;
> + case SCLK_UART8:
> + reg = 55;
> + break;
> + case SCLK_UART9:
> + reg = 57;
> + break;
> + default:
> + return -ENOENT;
> + }
> + con = readl(&cru->clksel_con[reg + 2]);
> + src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
> + con = readl(&cru->clksel_con[reg]);
> + div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
> + p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
> + if (p_src == CLK_UART_SRC_SEL_GPLL)
> + p_rate = priv->gpll_hz;
> + else
> + p_rate = priv->cpll_hz;
> +
> + if (src == CLK_UART_SEL_SRC) {
> + return DIV_TO_RATE(p_rate, div);
> + } else if (src == CLK_UART_SEL_FRAC) {
> + fracdiv = readl(&cru->clksel_con[reg + 1]);
> + n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
> + n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
> + m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
> + m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
> + return DIV_TO_RATE(p_rate, div) * n / m;
> + } else {
> + return OSC_HZ;
> + }
> +}
> +
> +static ulong rk3588_uart_set_rate(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 reg, clk_src, uart_src, div;
> + unsigned long m = 0, n = 0, val;
> +
> + if (priv->gpll_hz % rate == 0) {
> + clk_src = CLK_UART_SRC_SEL_GPLL;
> + uart_src = CLK_UART_SEL_SRC;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + } else if (priv->cpll_hz % rate == 0) {
> + clk_src = CLK_UART_SRC_SEL_CPLL;
> + uart_src = CLK_UART_SEL_SRC;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + } else if (rate == OSC_HZ) {
> + clk_src = CLK_UART_SRC_SEL_GPLL;
> + uart_src = CLK_UART_SEL_XIN24M;
> + div = 2;
> + } else {
> + clk_src = CLK_UART_SRC_SEL_GPLL;
> + uart_src = CLK_UART_SEL_FRAC;
> + div = 2;
> + rational_best_approximation(rate, priv->gpll_hz / div,
> + GENMASK(16 - 1, 0),
> + GENMASK(16 - 1, 0),
> + &m, &n);
> + }
> +
> + switch (clk_id) {
> + case SCLK_UART1:
> + reg = 41;
> + break;
> + case SCLK_UART2:
> + reg = 43;
> + break;
> + case SCLK_UART3:
> + reg = 45;
> + break;
> + case SCLK_UART4:
> + reg = 47;
> + break;
> + case SCLK_UART5:
> + reg = 49;
> + break;
> + case SCLK_UART6:
> + reg = 51;
> + break;
> + case SCLK_UART7:
> + reg = 53;
> + break;
> + case SCLK_UART8:
> + reg = 55;
> + break;
> + case SCLK_UART9:
> + reg = 57;
> + break;
> + default:
> + return -ENOENT;
> + }
> + rk_clrsetreg(&cru->clksel_con[reg],
> + CLK_UART_SRC_SEL_MASK |
> + CLK_UART_SRC_DIV_MASK,
> + (clk_src << CLK_UART_SRC_SEL_SHIFT) |
> + ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
> + rk_clrsetreg(&cru->clksel_con[reg + 2],
> + CLK_UART_SEL_MASK,
> + (uart_src << CLK_UART_SEL_SHIFT));
> + if (m && n) {
> + val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
> + writel(val, &cru->clksel_con[reg + 1]);
> + }
> +
> + return rk3588_uart_get_rate(priv, clk_id);
> +}
> +
> +static ulong rk3588_pciephy_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 con, div, src;
> +
> + switch (clk_id) {
> + case CLK_REF_PIPE_PHY0:
> + con = readl(&cru->clksel_con[177]);
> + src = (con & CLK_PCIE_PHY0_REF_SEL_MASK) >> CLK_PCIE_PHY0_REF_SEL_SHIFT;
> + con = readl(&cru->clksel_con[176]);
> + div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT;
> + break;
> + case CLK_REF_PIPE_PHY1:
> + con = readl(&cru->clksel_con[177]);
> + src = (con & CLK_PCIE_PHY1_REF_SEL_MASK) >> CLK_PCIE_PHY1_REF_SEL_SHIFT;
> + con = readl(&cru->clksel_con[176]);
> + div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT;
> + break;
> + case CLK_REF_PIPE_PHY2:
> + con = readl(&cru->clksel_con[177]);
> + src = (con & CLK_PCIE_PHY2_REF_SEL_MASK) >> CLK_PCIE_PHY2_REF_SEL_SHIFT;
> + div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + if (src == CLK_PCIE_PHY_REF_SEL_PPLL)
> + return DIV_TO_RATE(priv->ppll_hz, div);
> + else
> + return OSC_HZ;
> +}
> +
> +static ulong rk3588_pciephy_set_rate(struct rk3588_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3588_cru *cru = priv->cru;
> + u32 clk_src, div;
> +
> + if (rate == OSC_HZ) {
> + clk_src = CLK_PCIE_PHY_REF_SEL_24M;
> + div = 1;
> + } else {
> + clk_src = CLK_PCIE_PHY_REF_SEL_PPLL;
> + div = DIV_ROUND_UP(priv->ppll_hz, rate);
> + }
> +
> + switch (clk_id) {
> + case CLK_REF_PIPE_PHY0:
> + rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY0_REF_SEL_MASK,
> + (clk_src << CLK_PCIE_PHY0_REF_SEL_SHIFT));
> + rk_clrsetreg(&cru->clksel_con[176], CLK_PCIE_PHY0_PLL_DIV_MASK,
> + ((div - 1) << CLK_PCIE_PHY0_PLL_DIV_SHIFT));
> + break;
> + case CLK_REF_PIPE_PHY1:
> + rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY1_REF_SEL_MASK,
> + (clk_src << CLK_PCIE_PHY1_REF_SEL_SHIFT));
> + rk_clrsetreg(&cru->clksel_con[176], CLK_PCIE_PHY1_PLL_DIV_MASK,
> + ((div - 1) << CLK_PCIE_PHY1_PLL_DIV_SHIFT));
> + break;
> + case CLK_REF_PIPE_PHY2:
> + rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY2_REF_SEL_MASK |
> + CLK_PCIE_PHY2_PLL_DIV_MASK,
> + (clk_src << CLK_PCIE_PHY2_REF_SEL_SHIFT) |
> + ((div - 1) << CLK_PCIE_PHY2_PLL_DIV_SHIFT));
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rk3588_pciephy_get_rate(priv, clk_id);
> +}
> +#endif
> +
> +static ulong rk3588_clk_get_rate(struct clk *clk)
> +{
> + struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong rate = 0;
> +
> + if (!priv->gpll_hz) {
> + printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
> + return -ENOENT;
> + }
> +
> + if (!priv->ppll_hz) {
> + priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
> + priv->cru, PPLL);
> + }
> +
> + switch (clk->id) {
> + case PLL_LPLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru,
> + LPLL);
> + break;
> + case PLL_B0PLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru,
> + B0PLL);
> + break;
> + case PLL_B1PLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru,
> + B1PLL);
> + break;
> + case PLL_GPLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru,
> + GPLL);
> + break;
> + case PLL_CPLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru,
> + CPLL);
> + break;
> + case PLL_NPLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru,
> + NPLL);
> + break;
> + case PLL_V0PLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru,
> + V0PLL);
> + break;
> + case PLL_AUPLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru,
> + AUPLL);
> + break;
> + case PLL_PPLL:
> + rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru,
> + PPLL);
> + break;
> + case ACLK_CENTER_ROOT:
> + case PCLK_CENTER_ROOT:
> + case HCLK_CENTER_ROOT:
> + case ACLK_CENTER_LOW_ROOT:
> + rate = rk3588_center_get_clk(priv, clk->id);
> + break;
> + case ACLK_TOP_ROOT:
> + case PCLK_TOP_ROOT:
> + case ACLK_LOW_TOP_ROOT:
> + rate = rk3588_top_get_clk(priv, clk->id);
> + break;
> + case CLK_I2C0:
> + case CLK_I2C1:
> + case CLK_I2C2:
> + case CLK_I2C3:
> + case CLK_I2C4:
> + case CLK_I2C5:
> + case CLK_I2C6:
> + case CLK_I2C7:
> + case CLK_I2C8:
> + rate = rk3588_i2c_get_clk(priv, clk->id);
> + break;
> + case CLK_SPI0:
> + case CLK_SPI1:
> + case CLK_SPI2:
> + case CLK_SPI3:
> + case CLK_SPI4:
> + rate = rk3588_spi_get_clk(priv, clk->id);
> + break;
> + case CLK_PWM1:
> + case CLK_PWM2:
> + case CLK_PWM3:
> + case CLK_PMU1PWM:
> + rate = rk3588_pwm_get_clk(priv, clk->id);
> + break;
> + case CLK_SARADC:
> + case CLK_TSADC:
> + rate = rk3588_adc_get_clk(priv, clk->id);
> + break;
> + case CCLK_SRC_SDIO:
> + case CCLK_EMMC:
> + case BCLK_EMMC:
> + case SCLK_SFC:
> + case DCLK_DECOM:
> + rate = rk3588_mmc_get_clk(priv, clk->id);
> + break;
> + case TCLK_WDT0:
> + rate = OSC_HZ;
> + break;
> +#ifndef CONFIG_SPL_BUILD
> + case CLK_AUX16M_0:
> + case CLK_AUX16M_1:
> + rk3588_aux16m_get_clk(priv, clk->id);
> + break;
> + case ACLK_VOP_ROOT:
> + case ACLK_VOP:
> + case ACLK_VOP_LOW_ROOT:
> + case HCLK_VOP_ROOT:
> + rate = rk3588_aclk_vop_get_clk(priv, clk->id);
> + break;
> + case DCLK_VOP0:
> + case DCLK_VOP0_SRC:
> + case DCLK_VOP1:
> + case DCLK_VOP1_SRC:
> + case DCLK_VOP2:
> + case DCLK_VOP2_SRC:
> + case DCLK_VOP3:
> + rate = rk3588_dclk_vop_get_clk(priv, clk->id);
> + break;
> + case CLK_GMAC0_PTP_REF:
> + case CLK_GMAC1_PTP_REF:
> + case CLK_GMAC_125M:
> + case CLK_GMAC_50M:
> + rate = rk3588_gmac_get_clk(priv, clk->id);
> + break; > + case SCLK_UART1:
> + case SCLK_UART2:
> + case SCLK_UART3:
> + case SCLK_UART4:
> + case SCLK_UART5:
> + case SCLK_UART6:
> + case SCLK_UART7:
> + case SCLK_UART8:
> + case SCLK_UART9:
> + rate = rk3588_uart_get_rate(priv, clk->id);
> + break;
Hi Jagan,
Any reason why the UART clocks are not available in SPL ?
Maybe the clock should be tied to some fixed clock in SPL if the reason
is that it should not be touched.
Otherwise SPL will report this error:
rk3588_clk_get_rate(clk=37fd98): unknown clock id=175
Eugen
> + case CLK_REF_PIPE_PHY0:
> + case CLK_REF_PIPE_PHY1:
> + case CLK_REF_PIPE_PHY2:
> + rate = rk3588_pciephy_get_rate(priv, clk->id);
> + break;
> +#endif
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +};
> +
> +static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong ret = 0;
> +
> + if (!priv->gpll_hz) {
> + printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
> + return -ENOENT;
> + }
> +
> + if (!priv->ppll_hz) {
> + priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
> + priv->cru, PPLL);
> + }
> +
> + switch (clk->id) {
> + case PLL_CPLL:
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
> + CPLL, rate);
> + priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL],
> + priv->cru, CPLL);
> + break;
> + case PLL_GPLL:
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
> + GPLL, rate);
> + priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL],
> + priv->cru, GPLL);
> + break;
> + case PLL_NPLL:
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru,
> + NPLL, rate);
> + break;
> + case PLL_V0PLL:
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru,
> + V0PLL, rate);
> + priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
> + priv->cru, V0PLL);
> + break;
> + case PLL_AUPLL:
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[AUPLL], priv->cru,
> + AUPLL, rate);
> + priv->aupll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL],
> + priv->cru, AUPLL);
> + break;
> + case PLL_PPLL:
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
> + PPLL, rate);
> + priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
> + priv->cru, PPLL);
> + break;
> + case ACLK_CENTER_ROOT:
> + case PCLK_CENTER_ROOT:
> + case HCLK_CENTER_ROOT:
> + case ACLK_CENTER_LOW_ROOT:
> + ret = rk3588_center_set_clk(priv, clk->id, rate);
> + break;
> + case ACLK_TOP_ROOT:
> + case PCLK_TOP_ROOT:
> + case ACLK_LOW_TOP_ROOT:
> + ret = rk3588_top_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_I2C0:
> + case CLK_I2C1:
> + case CLK_I2C2:
> + case CLK_I2C3:
> + case CLK_I2C4:
> + case CLK_I2C5:
> + case CLK_I2C6:
> + case CLK_I2C7:
> + case CLK_I2C8:
> + ret = rk3588_i2c_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_SPI0:
> + case CLK_SPI1:
> + case CLK_SPI2:
> + case CLK_SPI3:
> + case CLK_SPI4:
> + ret = rk3588_spi_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_PWM1:
> + case CLK_PWM2:
> + case CLK_PWM3:
> + case CLK_PMU1PWM:
> + ret = rk3588_pwm_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_SARADC:
> + case CLK_TSADC:
> + ret = rk3588_adc_set_clk(priv, clk->id, rate);
> + break;
> + case CCLK_SRC_SDIO:
> + case CCLK_EMMC:
> + case BCLK_EMMC:
> + case SCLK_SFC:
> + case DCLK_DECOM:
> + ret = rk3588_mmc_set_clk(priv, clk->id, rate);
> + break;
> + case TCLK_WDT0:
> + ret = OSC_HZ;
> + break;
> +#ifndef CONFIG_SPL_BUILD
> + case CLK_AUX16M_0:
> + case CLK_AUX16M_1:
> + rk3588_aux16m_set_clk(priv, clk->id, rate);
> + break;
> + case ACLK_VOP_ROOT:
> + case ACLK_VOP:
> + case ACLK_VOP_LOW_ROOT:
> + case HCLK_VOP_ROOT:
> + ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate);
> + break;
> + case DCLK_VOP0:
> + case DCLK_VOP0_SRC:
> + case DCLK_VOP1:
> + case DCLK_VOP1_SRC:
> + case DCLK_VOP2:
> + case DCLK_VOP2_SRC:
> + case DCLK_VOP3:
> + ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_GMAC0_PTP_REF:
> + case CLK_GMAC1_PTP_REF:
> + case CLK_GMAC_125M:
> + case CLK_GMAC_50M:
> + ret = rk3588_gmac_set_clk(priv, clk->id, rate);
> + break;
> + case SCLK_UART1:
> + case SCLK_UART2:
> + case SCLK_UART3:
> + case SCLK_UART4:
> + case SCLK_UART5:
> + case SCLK_UART6:
> + case SCLK_UART7:
> + case SCLK_UART8:
> + case SCLK_UART9:
> + ret = rk3588_uart_set_rate(priv, clk->id, rate);
> + break;
> + case CLK_REF_PIPE_PHY0:
> + case CLK_REF_PIPE_PHY1:
> + case CLK_REF_PIPE_PHY2:
> + ret = rk3588_pciephy_set_rate(priv, clk->id, rate);
> + break;
> +#endif
> + default:
> + return -ENOENT;
> + }
> +
> + return ret;
> +};
> +
> +#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
> +#define ROCKCHIP_MMC_DEGREE_MASK 0x3
> +#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
> +#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
> +
> +#define PSECS_PER_SEC 1000000000000LL
> +/*
> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
> + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
> + */
> +#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
> +
> +#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
> +static int __maybe_unused rk3588_dclk_vop_set_parent(struct clk *clk,
> + struct clk *parent)
> +{
> + struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
> + struct rk3588_cru *cru = priv->cru;
> + u32 sel;
> + const char *clock_dev_name = parent->dev->name;
> +
> + if (parent->id == PLL_V0PLL)
> + sel = 2;
> + else if (parent->id == PLL_GPLL)
> + sel = 0;
> + else if (parent->id == PLL_CPLL)
> + sel = 1;
> + else
> + sel = 3;
> +
> + switch (clk->id) {
> + case DCLK_VOP0_SRC:
> + rk_clrsetreg(&cru->clksel_con[111], DCLK0_VOP_SRC_SEL_MASK,
> + sel << DCLK0_VOP_SRC_SEL_SHIFT);
> + break;
> + case DCLK_VOP1_SRC:
> + rk_clrsetreg(&cru->clksel_con[111], DCLK1_VOP_SRC_SEL_MASK,
> + sel << DCLK1_VOP_SRC_SEL_SHIFT);
> + break;
> + case DCLK_VOP2_SRC:
> + rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SRC_SEL_MASK,
> + sel << DCLK2_VOP_SRC_SEL_SHIFT);
> + break;
> + case DCLK_VOP3:
> + rk_clrsetreg(&cru->clksel_con[113], DCLK3_VOP_SRC_SEL_MASK,
> + sel << DCLK3_VOP_SRC_SEL_SHIFT);
> + break;
> + case DCLK_VOP0:
> + if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
> + sel = 1;
> + else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
> + sel = 2;
> + else
> + sel = 0;
> + rk_clrsetreg(&cru->clksel_con[112], DCLK0_VOP_SEL_MASK,
> + sel << DCLK0_VOP_SEL_SHIFT);
> + break;
> + case DCLK_VOP1:
> + if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
> + sel = 1;
> + else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
> + sel = 2;
> + else
> + sel = 0;
> + rk_clrsetreg(&cru->clksel_con[112], DCLK1_VOP_SEL_MASK,
> + sel << DCLK1_VOP_SEL_SHIFT);
> + break;
> + case DCLK_VOP2:
> + if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
> + sel = 1;
> + else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
> + sel = 2;
> + else
> + sel = 0;
> + rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SEL_MASK,
> + sel << DCLK2_VOP_SEL_SHIFT);
> + break;
> + default:
> + return -EINVAL;
> + }
> + return 0;
> +}
> +
> +static int rk3588_clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> + switch (clk->id) {
> + case DCLK_VOP0_SRC:
> + case DCLK_VOP1_SRC:
> + case DCLK_VOP2_SRC:
> + case DCLK_VOP0:
> + case DCLK_VOP1:
> + case DCLK_VOP2:
> + case DCLK_VOP3:
> + return rk3588_dclk_vop_set_parent(clk, parent);
> + default:
> + return -ENOENT;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static struct clk_ops rk3588_clk_ops = {
> + .get_rate = rk3588_clk_get_rate,
> + .set_rate = rk3588_clk_set_rate,
> +#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
> + .set_parent = rk3588_clk_set_parent,
> +#endif
> +};
> +
> +static void rk3588_clk_init(struct rk3588_clk_priv *priv)
> +{
> + int ret, div;
> +
> + div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz);
> + rk_clrsetreg(&priv->cru->clksel_con[38],
> + ACLK_BUS_ROOT_SEL_MASK |
> + ACLK_BUS_ROOT_DIV_MASK,
> + div << ACLK_BUS_ROOT_DIV_SHIFT);
> +
> + if (priv->cpll_hz != CPLL_HZ) {
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
> + CPLL, CPLL_HZ);
> + if (!ret)
> + priv->cpll_hz = CPLL_HZ;
> + }
> + if (priv->gpll_hz != GPLL_HZ) {
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
> + GPLL, GPLL_HZ);
> + if (!ret)
> + priv->gpll_hz = GPLL_HZ;
> + }
> +
> +#ifdef CONFIG_PCI
> + if (priv->ppll_hz != PPLL_HZ) {
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
> + PPLL, PPLL_HZ);
> + priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
> + priv->cru, PPLL);
> + }
> +#endif
> + rk_clrsetreg(&priv->cru->clksel_con[9],
> + ACLK_TOP_S400_SEL_MASK |
> + ACLK_TOP_S200_SEL_MASK,
> + (ACLK_TOP_S400_SEL_400M << ACLK_TOP_S400_SEL_SHIFT) |
> + (ACLK_TOP_S200_SEL_200M << ACLK_TOP_S200_SEL_SHIFT));
> +}
> +
> +static int rk3588_clk_probe(struct udevice *dev)
> +{
> + struct rk3588_clk_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + priv->sync_kernel = false;
> +
> +#ifdef CONFIG_SPL_BUILD
> + rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru,
> + B0PLL, LPLL_HZ);
> + rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru,
> + B1PLL, LPLL_HZ);
> + if (!priv->armclk_enter_hz) {
> + ret = rockchip_pll_set_rate(&rk3588_pll_clks[LPLL], priv->cru,
> + LPLL, LPLL_HZ);
> + priv->armclk_enter_hz =
> + rockchip_pll_get_rate(&rk3588_pll_clks[LPLL],
> + priv->cru, LPLL);
> + priv->armclk_init_hz = priv->armclk_enter_hz;
> + }
> +#endif
> +
> +#ifndef CONFIG_SPL_BUILD
> + struct clk clk;
> +
> + if (!priv->armclk_enter_hz) {
> + clk.id = SCMI_CLK_CPUL;
> + ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
> + if (ret < 0) {
> + printf("Failed to set cpubl\n");
> + } else {
> + priv->armclk_enter_hz = CPU_PVTPLL_HZ;
> + priv->armclk_init_hz = CPU_PVTPLL_HZ;
> + }
> + }
> + clk.id = SCMI_CLK_CPUB01;
> + ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
> + if (ret < 0)
> + printf("Failed to set cpub01\n");
> + clk.id = SCMI_CLK_CPUB23;
> + ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
> + if (ret < 0)
> + printf("Failed to set cpub23\n");
> +#endif
> +
> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (IS_ERR(priv->grf))
> + return PTR_ERR(priv->grf);
> +
> + rk3588_clk_init(priv);
> +
> + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
> + ret = clk_set_defaults(dev, 1);
> + if (ret)
> + debug("%s clk_set_defaults failed %d\n", __func__, ret);
> + else
> + priv->sync_kernel = true;
> +
> + return 0;
> +}
> +
> +static int rk3588_clk_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk3588_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = dev_read_addr_ptr(dev);
> +
> + return 0;
> +}
> +
> +static int rk3588_clk_bind(struct udevice *dev)
> +{
> + int ret;
> + struct udevice *sys_child;
> + struct sysreset_reg *priv;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
> + &sys_child);
> + if (ret) {
> + debug("Warning: No sysreset driver: ret=%d\n", ret);
> + } else {
> + priv = malloc(sizeof(struct sysreset_reg));
> + priv->glb_srst_fst_value = offsetof(struct rk3588_cru,
> + glb_srst_fst);
> + priv->glb_srst_snd_value = offsetof(struct rk3588_cru,
> + glb_srsr_snd);
> + dev_set_priv(sys_child, priv);
> + }
> +
> +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> + ret = offsetof(struct rk3588_cru, softrst_con[0]);
> + ret = rockchip_reset_bind(dev, ret, 49158);
> + if (ret)
> + debug("Warning: software reset driver bind faile\n");
> +#endif
> +
> + return 0;
> +}
> +
> +static const struct udevice_id rk3588_clk_ids[] = {
> + { .compatible = "rockchip,rk3588-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3588_cru) = {
> + .name = "rockchip_rk3588_cru",
> + .id = UCLASS_CLK,
> + .of_match = rk3588_clk_ids,
> + .priv_auto = sizeof(struct rk3588_clk_priv),
> + .of_to_plat = rk3588_clk_ofdata_to_platdata,
> + .ops = &rk3588_clk_ops,
> + .bind = rk3588_clk_bind,
> + .probe = rk3588_clk_probe,
> +};
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6
2023-02-02 8:23 ` Eugen Hristev
@ 2023-02-16 9:03 ` Jagan Teki
0 siblings, 0 replies; 56+ messages in thread
From: Jagan Teki @ 2023-02-16 9:03 UTC (permalink / raw)
To: Eugen Hristev
Cc: Kever Yang, Simon Glass, Philipp Tomsich, fatorangecat, u-boot
On Thu, 2 Feb 2023 at 13:53, Eugen Hristev <eugen.hristev@collabora.com> wrote:
>
> On 1/26/23 00:27, Jagan Teki wrote:
> > Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
> > based on Rockchip RK3588 from Edgeble AI.
> >
> > General features:
> > - Rockchip RK3588
> > - up to 32GB LPDDR4x
> > - up to 128GB eMMC
> > - 2x MIPI CSI2 FPC
> >
> > On module WiFi6/BT5 is available in the following Neu6 variants.
> >
> > Neural Compute Module 6(Neu6) IO board is an industrial form factor
> > ready-to-use IO board from Edgeble AI.
> >
> > IO board offers plenty of peripherals and connectivity options and
> > this patch enables basic eMMC and UART which is enough to successfully
> > boot Linux.
> >
> > Neu6 needs to mount on top of this IO board in order to create a
> > complete Edgeble Neural Compute Module 6(Neu6) IO platform.
> >
> > Add support for Edgeble Neu6 Model A IO Board.
> >
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> > ---
>
> [snip]
>
> > diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> > index 28c837a382..a140c1a8a4 100644
> > --- a/doc/board/rockchip/rockchip.rst
> > +++ b/doc/board/rockchip/rockchip.rst
> > @@ -86,6 +86,8 @@ List of mainline supported Rockchip boards:
> > - Radxa ROCK Pi 4 (rock-pi-4-rk3399)
> > - Rockchip Evb-RK3399 (evb_rk3399)
> > - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
> > +* rk3588
> > + - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-r1126)
>
> Hi Jagan,
>
> I suppose here it should be neu6a-io-rk3588 , in the line above
Correct will fix it.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-01-29 9:04 ` Jonas Karlman
@ 2023-03-08 8:57 ` Eugen Hristev
2023-03-12 22:34 ` Jonas Karlman
0 siblings, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-03-08 8:57 UTC (permalink / raw)
To: Jonas Karlman, Jagan Teki
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 1/29/23 11:04, Jonas Karlman wrote:
> On 2023-01-27 14:21, Jagan Teki wrote:
>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>
>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>> Hi Jagan,
>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>
>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>> Hi Simon,
>>>>>>>
>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>
>>>>>>>> Hi Jagan,
>>>>>>>>
>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>
>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>
>>>>>>>>>> Hi Jagan,
>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>
>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>
>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>
>>
>> < snip >
>>
>>>>
>>>> As you can see in the logs above there is timeout waiting for data.
>>>>
>>>> I managed to find the issue and have a workaround that gets me longer
>>>> in the boot process, there still seem to be other issue with the rk3588
>>>> startup.
>>>>
>>>> --------
>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>> Trying to boot from MMC1
>>>> ## Checking hash(es) for config config-1 ... OK
>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>> INFO: Preloader serial: 2
>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>> INFO: spec: 0x1
>>>> INFO: ext 32k is not valid
>>>> INFO: ddr: stride-en 4CH
>>>> INFO: GICv3 without legacy support detected.
>>>> INFO: ARM GICv3 driver initialized in EL3
>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>> INFO: system boots from cpu-hwid-0
>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>> INFO: BL31: Initialising Exception Handling Framework
>>>> INFO: BL31: Initializing runtime services
>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>> ERROR: Error initializing runtime service opteed_fast
>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>> INFO: Entry point address = 0xa00000
>>>> INFO: SPSR = 0x3c9
>>>> "Synchronous Abort" handler, esr 0x96000000
>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>> x10: 0000000000000034 x11: 0000000000000002
>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>> x16: 0000000000000000 x17: 0000000000000000
>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>> x24: 0000000000000000 x25: 0000000000000000
>>>> x26: 0000000000000000 x27: 0000000000000000
>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>
>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>> Resetting CPU ...
>>>> --------
>>>>
>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>> with some rk3568 patches and this series, see [1].
>>>>
>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>> fallback to default 400khz clock.
>>>>
>>>> Next issue is the sync abort, looks it happens when u-boot
>>>> tries to set clock rates based on devicetree. this is the
>>>> last debug line before the crash.
>>>>
>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>
>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>
>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>
>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>
>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>
>> Okay. We need to find a way to handle the clock value 400Khz
>> generically via the CLK framework or eMMC can be worth checking as it
>> doesn't involve SCMI and have a working patch set before MW. I did
>> that and was able to detect eMMC in U-Boot proper but got some issues
>> while booting from eMMC [3]
>
> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>
> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
> and I have included some rk3568 patches and your rk3588 rfc series.
> I added a few fixup on top of that and a few additional patches, please see commit message
> for a very brief note on why the change was needed.
> Feel free to squash fixups and pick commits up to and possible including
> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
> for a v2 of this series.
>
> The remaining sdhci patches needs a little bit more work,
> I can send a separate series with emmc patches once they are fully ready.
>
> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
> I think this is a more appropriate way to work around this issue, instead of patching
> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>
> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
Hello Jagan, Jonas,
I wanted to chip into this discussion, to ask whether you did anything
more on the SD clock matter ?
I am currently using your workaround that creates dummy clocks in the DT
and then the SD node just uses those, and it works, in the SPL, if and
only if the bootrom also loads the SPL from SD.
I tried to have the SPL inside the SPI flash, or load it to DDR using
the rockusb protocol, and then, initializing the SD-Card from SPL fails
utterly, namely, it cannot communicate with the card.
I did some changes to have the pinctrl working at SPL level, which
appears to be fine, but I would like to see what can be done about the
clocks.
Having the cru and all the required drivers at SPL level is the way to
go ? The SPL should run before SCMI is required so it should be able to
change all the clocks at the clock controller level ?
Thanks,
Eugen
>
> Regards,
> Jonas
>
>>
>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>
>> Jagan.
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-08 8:57 ` Eugen Hristev
@ 2023-03-12 22:34 ` Jonas Karlman
2023-03-13 8:42 ` Eugen Hristev
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-03-12 22:34 UTC (permalink / raw)
To: Eugen Hristev, Jagan Teki
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
Hi Eugen,
On 2023-03-08 09:57, Eugen Hristev wrote:
> On 1/29/23 11:04, Jonas Karlman wrote:
>> On 2023-01-27 14:21, Jagan Teki wrote:
>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>
>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>> Hi Jagan,
>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>
>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>> Hi Simon,
>>>>>>>>
>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>
>>>>>>>>> Hi Jagan,
>>>>>>>>>
>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>
>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>
>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>
>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>
>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>
>>>
>>> < snip >
>>>
>>>>>
>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>
>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>> startup.
>>>>>
>>>>> --------
>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>> Trying to boot from MMC1
>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>> INFO: Preloader serial: 2
>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>> INFO: spec: 0x1
>>>>> INFO: ext 32k is not valid
>>>>> INFO: ddr: stride-en 4CH
>>>>> INFO: GICv3 without legacy support detected.
>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>> INFO: system boots from cpu-hwid-0
>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>> INFO: BL31: Initializing runtime services
>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>> INFO: Entry point address = 0xa00000
>>>>> INFO: SPSR = 0x3c9
>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>
>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>> Resetting CPU ...
>>>>> --------
>>>>>
>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>> with some rk3568 patches and this series, see [1].
>>>>>
>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>> fallback to default 400khz clock.
>>>>>
>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>> tries to set clock rates based on devicetree. this is the
>>>>> last debug line before the crash.
>>>>>
>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>
>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>
>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>
>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>
>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>
>>> Okay. We need to find a way to handle the clock value 400Khz
>>> generically via the CLK framework or eMMC can be worth checking as it
>>> doesn't involve SCMI and have a working patch set before MW. I did
>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>> while booting from eMMC [3]
>>
>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>
>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>> and I have included some rk3568 patches and your rk3588 rfc series.
>> I added a few fixup on top of that and a few additional patches, please see commit message
>> for a very brief note on why the change was needed.
>> Feel free to squash fixups and pick commits up to and possible including
>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>> for a v2 of this series.
>>
>> The remaining sdhci patches needs a little bit more work,
>> I can send a separate series with emmc patches once they are fully ready.
>>
>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>> I think this is a more appropriate way to work around this issue, instead of patching
>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>
>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>
> Hello Jagan, Jonas,
>
> I wanted to chip into this discussion, to ask whether you did anything
> more on the SD clock matter ?
I have been busy this past week but have now had time to take a new look
at the sdmmc issue, along with completing some other fixes.
>
> I am currently using your workaround that creates dummy clocks in the DT
> and then the SD node just uses those, and it works, in the SPL, if and
> only if the bootrom also loads the SPL from SD.
> I tried to have the SPL inside the SPI flash, or load it to DDR using
> the rockusb protocol, and then, initializing the SD-Card from SPL fails
> utterly, namely, it cannot communicate with the card.
> I did some changes to have the pinctrl working at SPL level, which
> appears to be fine, but I would like to see what can be done about the
> clocks.
> Having the cru and all the required drivers at SPL level is the way to
> go ? The SPL should run before SCMI is required so it should be able to
> change all the clocks at the clock controller level ?
I fully agree that we should have some sort of scmi clk driver so that
we can control the sdmmc clk in both SPL and U-Boot proper.
As you have noticed the current workaround only works because bootrom
leave the clocks in a working state after it has loaded TPL/SPL from
the sdmmc device. When TPL/SPL is loaded from any other source it is
not be possible to read from the sdmmc device in u-boot.
After having played around with the scmi agent driver and being inspired
by the dummy scmi clk driver in vendor u-boot I have managed to create
something that could work. See top three commits from [5] for a working
proof-of-concept.
What I did was to enable the scmi agent driver for use in u-boot proper
and keeping it disabled in SPL build. Then added a new scmi clk driver
that is enabled in SPL build, the rk3588 clk driver hooks the new clk
driver to the scmi_clk ofnode. I only implemented the get/set rate ops
for the two sdmmc clocks. With this both SPL and U-Boot proper should
be able to configure the sdmmc clocks.
The initial fixes commits in that branch should hit the list soon.
Will send the sdmmc related commits once I have had some time to do
more testing.
[5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
Regards,
Jonas
>
> Thanks,
> Eugen
>
>>
>> Regards,
>> Jonas
>>
>>>
>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>
>>> Jagan.
>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-12 22:34 ` Jonas Karlman
@ 2023-03-13 8:42 ` Eugen Hristev
2023-03-13 10:00 ` Jonas Karlman
0 siblings, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-03-13 8:42 UTC (permalink / raw)
To: Jonas Karlman, Jagan Teki
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 3/13/23 00:34, Jonas Karlman wrote:
> Hi Eugen,
>
> On 2023-03-08 09:57, Eugen Hristev wrote:
>> On 1/29/23 11:04, Jonas Karlman wrote:
>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>
>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>> Hi Jagan,
>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>
>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>> Hi Simon,
>>>>>>>>>
>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>
>>>>>>>>>> Hi Jagan,
>>>>>>>>>>
>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>
>>>>
>>>> < snip >
>>>>
>>>>>>
>>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>>
>>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>>> startup.
>>>>>>
>>>>>> --------
>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>> Trying to boot from MMC1
>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>> INFO: Preloader serial: 2
>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>> INFO: spec: 0x1
>>>>>> INFO: ext 32k is not valid
>>>>>> INFO: ddr: stride-en 4CH
>>>>>> INFO: GICv3 without legacy support detected.
>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>> INFO: system boots from cpu-hwid-0
>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>> INFO: BL31: Initializing runtime services
>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>> INFO: Entry point address = 0xa00000
>>>>>> INFO: SPSR = 0x3c9
>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>
>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>> Resetting CPU ...
>>>>>> --------
>>>>>>
>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>
>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>> fallback to default 400khz clock.
>>>>>>
>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>> last debug line before the crash.
>>>>>>
>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>
>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>
>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>
>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>>
>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>
>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>> generically via the CLK framework or eMMC can be worth checking as it
>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>>> while booting from eMMC [3]
>>>
>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>
>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>> I added a few fixup on top of that and a few additional patches, please see commit message
>>> for a very brief note on why the change was needed.
>>> Feel free to squash fixups and pick commits up to and possible including
>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>>> for a v2 of this series.
>>>
>>> The remaining sdhci patches needs a little bit more work,
>>> I can send a separate series with emmc patches once they are fully ready.
>>>
>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>>> I think this is a more appropriate way to work around this issue, instead of patching
>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>>
>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>
>> Hello Jagan, Jonas,
>>
>> I wanted to chip into this discussion, to ask whether you did anything
>> more on the SD clock matter ?
>
> I have been busy this past week but have now had time to take a new look
> at the sdmmc issue, along with completing some other fixes.
>
>>
>> I am currently using your workaround that creates dummy clocks in the DT
>> and then the SD node just uses those, and it works, in the SPL, if and
>> only if the bootrom also loads the SPL from SD.
>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
>> utterly, namely, it cannot communicate with the card.
>> I did some changes to have the pinctrl working at SPL level, which
>> appears to be fine, but I would like to see what can be done about the
>> clocks.
>> Having the cru and all the required drivers at SPL level is the way to
>> go ? The SPL should run before SCMI is required so it should be able to
>> change all the clocks at the clock controller level ?
>
> I fully agree that we should have some sort of scmi clk driver so that
> we can control the sdmmc clk in both SPL and U-Boot proper.
>
> As you have noticed the current workaround only works because bootrom
> leave the clocks in a working state after it has loaded TPL/SPL from
> the sdmmc device. When TPL/SPL is loaded from any other source it is
> not be possible to read from the sdmmc device in u-boot.
>
> After having played around with the scmi agent driver and being inspired
> by the dummy scmi clk driver in vendor u-boot I have managed to create
> something that could work. See top three commits from [5] for a working
> proof-of-concept.
>
> What I did was to enable the scmi agent driver for use in u-boot proper
> and keeping it disabled in SPL build. Then added a new scmi clk driver
> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
> for the two sdmmc clocks. With this both SPL and U-Boot proper should
> be able to configure the sdmmc clocks.
>
> The initial fixes commits in that branch should hit the list soon.
> Will send the sdmmc related commits once I have had some time to do
> more testing.
>
> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
Hi Jonas,
I managed to get it working in SPL as well, with a similar code inspired
from the vendor tree.
About the solution, I am not sure whether it should be called a scmi
clock, and whether it should be part of clk_rk3588
Honestly by looking at the DT node, I find the description of the clock
tree wrong to begin with.
The SD should not have the 2 clocks tied to the scmi agent, because this
is true only if it's running in normal world with a secure world agent
that will act as a middle man. So if we are running at a higher EL, as
in the SPL case, the clocks should be tied directly to the CRU.
So the node itself is described bad IMO.
Anyway, if the node is set in stone from Linux, there isn;t much we can do.
I am also thinking whether we should have the SCMI enabled in SPL as
well, but the agent/clock should just access the CRU directly, meaning
to do something at the agent level :
#ifdef CONFIG_SPL_BUILD
-> access CRU
#else
-> send SCMI message
#endif
Does this make more sense ?
Or have some kind of wrapper driver that would act as a dispatcher
depending on the SPL/proper build ?
Meanwhile, I will test your patches to see how they work on my setup, I
also have some things in progress including pinctrl in SPL for the rock5b.
Thanks for your detailed description,
Eugen
>
> Regards,
> Jonas
>
>>
>> Thanks,
>> Eugen
>>
>>>
>>> Regards,
>>> Jonas
>>>
>>>>
>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>
>>>> Jagan.
>>>
>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 8:42 ` Eugen Hristev
@ 2023-03-13 10:00 ` Jonas Karlman
2023-03-13 14:21 ` Eugen Hristev
0 siblings, 1 reply; 56+ messages in thread
From: Jonas Karlman @ 2023-03-13 10:00 UTC (permalink / raw)
To: Eugen Hristev, Jagan Teki
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 2023-03-13 09:42, Eugen Hristev wrote:
> On 3/13/23 00:34, Jonas Karlman wrote:
>> Hi Eugen,
>>
>> On 2023-03-08 09:57, Eugen Hristev wrote:
>>> On 1/29/23 11:04, Jonas Karlman wrote:
>>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>
>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>>> Hi Jagan,
>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>
>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>>> Hi Simon,
>>>>>>>>>>
>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>>
>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>
>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>>
>>>>>
>>>>> < snip >
>>>>>
>>>>>>>
>>>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>>>
>>>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>>>> startup.
>>>>>>>
>>>>>>> --------
>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>>> Trying to boot from MMC1
>>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>>> INFO: Preloader serial: 2
>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>>> INFO: spec: 0x1
>>>>>>> INFO: ext 32k is not valid
>>>>>>> INFO: ddr: stride-en 4CH
>>>>>>> INFO: GICv3 without legacy support detected.
>>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>>> INFO: system boots from cpu-hwid-0
>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>>> INFO: BL31: Initializing runtime services
>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>>> INFO: Entry point address = 0xa00000
>>>>>>> INFO: SPSR = 0x3c9
>>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>>
>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>>> Resetting CPU ...
>>>>>>> --------
>>>>>>>
>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>>
>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>>> fallback to default 400khz clock.
>>>>>>>
>>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>>> last debug line before the crash.
>>>>>>>
>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>>
>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>>
>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>>
>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>>>
>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>>
>>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>>> generically via the CLK framework or eMMC can be worth checking as it
>>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>>>> while booting from eMMC [3]
>>>>
>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>>
>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>>> I added a few fixup on top of that and a few additional patches, please see commit message
>>>> for a very brief note on why the change was needed.
>>>> Feel free to squash fixups and pick commits up to and possible including
>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>>>> for a v2 of this series.
>>>>
>>>> The remaining sdhci patches needs a little bit more work,
>>>> I can send a separate series with emmc patches once they are fully ready.
>>>>
>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>>>> I think this is a more appropriate way to work around this issue, instead of patching
>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>>>
>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>>
>>> Hello Jagan, Jonas,
>>>
>>> I wanted to chip into this discussion, to ask whether you did anything
>>> more on the SD clock matter ?
>>
>> I have been busy this past week but have now had time to take a new look
>> at the sdmmc issue, along with completing some other fixes.
>>
>>>
>>> I am currently using your workaround that creates dummy clocks in the DT
>>> and then the SD node just uses those, and it works, in the SPL, if and
>>> only if the bootrom also loads the SPL from SD.
>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
>>> utterly, namely, it cannot communicate with the card.
>>> I did some changes to have the pinctrl working at SPL level, which
>>> appears to be fine, but I would like to see what can be done about the
>>> clocks.
>>> Having the cru and all the required drivers at SPL level is the way to
>>> go ? The SPL should run before SCMI is required so it should be able to
>>> change all the clocks at the clock controller level ?
>>
>> I fully agree that we should have some sort of scmi clk driver so that
>> we can control the sdmmc clk in both SPL and U-Boot proper.
>>
>> As you have noticed the current workaround only works because bootrom
>> leave the clocks in a working state after it has loaded TPL/SPL from
>> the sdmmc device. When TPL/SPL is loaded from any other source it is
>> not be possible to read from the sdmmc device in u-boot.
>>
>> After having played around with the scmi agent driver and being inspired
>> by the dummy scmi clk driver in vendor u-boot I have managed to create
>> something that could work. See top three commits from [5] for a working
>> proof-of-concept.
>>
>> What I did was to enable the scmi agent driver for use in u-boot proper
>> and keeping it disabled in SPL build. Then added a new scmi clk driver
>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
>> be able to configure the sdmmc clocks.
>>
>> The initial fixes commits in that branch should hit the list soon.
>> Will send the sdmmc related commits once I have had some time to do
>> more testing.
>>
>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
>>
> Hi Jonas,
>
> I managed to get it working in SPL as well, with a similar code inspired
> from the vendor tree.
> About the solution, I am not sure whether it should be called a scmi
> clock, and whether it should be part of clk_rk3588
> Honestly by looking at the DT node, I find the description of the clock
> tree wrong to begin with.
> The SD should not have the 2 clocks tied to the scmi agent, because this
> is true only if it's running in normal world with a secure world agent
> that will act as a middle man. So if we are running at a higher EL, as
> in the SPL case, the clocks should be tied directly to the CRU.
> So the node itself is described bad IMO.
>
> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
> I am also thinking whether we should have the SCMI enabled in SPL as
> well, but the agent/clock should just access the CRU directly, meaning
> to do something at the agent level :
> #ifdef CONFIG_SPL_BUILD
> -> access CRU
> #else
> -> send SCMI message
> #endif
> Does this make more sense ?
>
> Or have some kind of wrapper driver that would act as a dispatcher
> depending on the SPL/proper build ?
Looks like the sdmmc clock is controlled by the securecru registers and I
expect that this can only be configured in secure world, not sure how this
could have been modeled differently.
With the approach that I took I think the normal clk framework will behave
as such dispatcher and clock gets tied to cru in SPL.
#ifdef CONFIG_SPL_BUILD
-> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
#else
-> bind protocol@14 to scmi clk driver -> send SCMI message
#endif
Naming and placement of the SPL securecru driver could be improved.
Not sure if any other soc beside rk3588 will need this at this moment.
>
>
> Meanwhile, I will test your patches to see how they work on my setup, I
> also have some things in progress including pinctrl in SPL for the rock5b.
> Thanks for your detailed description,
Thanks for the hint at pinctrl, I made some updates to [5] and could verify
that sdmmc works when booting from emmc thanks to your pinctrl commit.
Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
and build a spi firmware image.
There is an issue with non-DMA access in sdhci that requires the HACK commit
for proper loading of atf, was hoping to disable SDMA in SPL like what is done
using fifo-mode for sdmmc. But only first sector is read successfully then it
fails, see below. Will take a closer look before I post eMMC series.
Trying to boot from MMC2
1
- 0 'mmc@fe2c0000'
- 1 'mmc@fe2e0000'
- found
blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
clock is disabled (0Hz)
clock is enabled (400000Hz)
clk_set_rate(clk=5000d8, rate=400000)
size=200, ptr=3b8, limit=100000: 5001b8
clock is enabled (25000000Hz)
clk_set_rate(clk=5000d8, rate=25000000)
clk_set_rate(clk=5000d8, rate=25000000)
clock is enabled (52000000Hz)
clk_set_rate(clk=5000d8, rate=52000000)
spl: mmc boot mode: raw
blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
hdr read sector 4000, count=1
Found FIT
size=a00, ptr=dc0, limit=100000: aligned to 5003c0
blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
Trying to boot from MMC1
[6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
Regards,
Jonas
> Eugen
>
>>
>> Regards,
>> Jonas
>>
>>>
>>> Thanks,
>>> Eugen
>>>
>>>>
>>>> Regards,
>>>> Jonas
>>>>
>>>>>
>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>
>>>>> Jagan.
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 10:00 ` Jonas Karlman
@ 2023-03-13 14:21 ` Eugen Hristev
2023-03-13 14:51 ` Eugen Hristev
2023-03-13 15:07 ` Mark Kettenis
0 siblings, 2 replies; 56+ messages in thread
From: Eugen Hristev @ 2023-03-13 14:21 UTC (permalink / raw)
To: Jonas Karlman, Jagan Teki
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 3/13/23 12:00, Jonas Karlman wrote:
> On 2023-03-13 09:42, Eugen Hristev wrote:
>> On 3/13/23 00:34, Jonas Karlman wrote:
>>> Hi Eugen,
>>>
>>> On 2023-03-08 09:57, Eugen Hristev wrote:
>>>> On 1/29/23 11:04, Jonas Karlman wrote:
>>>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>
>>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>>>> Hi Jagan,
>>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>
>>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>
>>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>
>>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>>>
>>>>>>
>>>>>> < snip >
>>>>>>
>>>>>>>>
>>>>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>>>>
>>>>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>>>>> startup.
>>>>>>>>
>>>>>>>> --------
>>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>>>> Trying to boot from MMC1
>>>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>>>> INFO: Preloader serial: 2
>>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>>>> INFO: spec: 0x1
>>>>>>>> INFO: ext 32k is not valid
>>>>>>>> INFO: ddr: stride-en 4CH
>>>>>>>> INFO: GICv3 without legacy support detected.
>>>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>>>> INFO: system boots from cpu-hwid-0
>>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>>>> INFO: BL31: Initializing runtime services
>>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>>>> INFO: Entry point address = 0xa00000
>>>>>>>> INFO: SPSR = 0x3c9
>>>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>>>
>>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>>>> Resetting CPU ...
>>>>>>>> --------
>>>>>>>>
>>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>>>
>>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>>>> fallback to default 400khz clock.
>>>>>>>>
>>>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>>>> last debug line before the crash.
>>>>>>>>
>>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>>>
>>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>>>
>>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>>>
>>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>>>>
>>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>>>
>>>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>>>> generically via the CLK framework or eMMC can be worth checking as it
>>>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>>>>> while booting from eMMC [3]
>>>>>
>>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>>>
>>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>>>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>>>> I added a few fixup on top of that and a few additional patches, please see commit message
>>>>> for a very brief note on why the change was needed.
>>>>> Feel free to squash fixups and pick commits up to and possible including
>>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>>>>> for a v2 of this series.
>>>>>
>>>>> The remaining sdhci patches needs a little bit more work,
>>>>> I can send a separate series with emmc patches once they are fully ready.
>>>>>
>>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>>>>> I think this is a more appropriate way to work around this issue, instead of patching
>>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>>>>
>>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>>>
>>>> Hello Jagan, Jonas,
>>>>
>>>> I wanted to chip into this discussion, to ask whether you did anything
>>>> more on the SD clock matter ?
>>>
>>> I have been busy this past week but have now had time to take a new look
>>> at the sdmmc issue, along with completing some other fixes.
>>>
>>>>
>>>> I am currently using your workaround that creates dummy clocks in the DT
>>>> and then the SD node just uses those, and it works, in the SPL, if and
>>>> only if the bootrom also loads the SPL from SD.
>>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
>>>> utterly, namely, it cannot communicate with the card.
>>>> I did some changes to have the pinctrl working at SPL level, which
>>>> appears to be fine, but I would like to see what can be done about the
>>>> clocks.
>>>> Having the cru and all the required drivers at SPL level is the way to
>>>> go ? The SPL should run before SCMI is required so it should be able to
>>>> change all the clocks at the clock controller level ?
>>>
>>> I fully agree that we should have some sort of scmi clk driver so that
>>> we can control the sdmmc clk in both SPL and U-Boot proper.
>>>
>>> As you have noticed the current workaround only works because bootrom
>>> leave the clocks in a working state after it has loaded TPL/SPL from
>>> the sdmmc device. When TPL/SPL is loaded from any other source it is
>>> not be possible to read from the sdmmc device in u-boot.
>>>
>>> After having played around with the scmi agent driver and being inspired
>>> by the dummy scmi clk driver in vendor u-boot I have managed to create
>>> something that could work. See top three commits from [5] for a working
>>> proof-of-concept.
>>>
>>> What I did was to enable the scmi agent driver for use in u-boot proper
>>> and keeping it disabled in SPL build. Then added a new scmi clk driver
>>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
>>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
>>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
>>> be able to configure the sdmmc clocks.
>>>
>>> The initial fixes commits in that branch should hit the list soon.
>>> Will send the sdmmc related commits once I have had some time to do
>>> more testing.
>>>
>>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
>>>
>> Hi Jonas,
>>
>> I managed to get it working in SPL as well, with a similar code inspired
>> from the vendor tree.
>> About the solution, I am not sure whether it should be called a scmi
>> clock, and whether it should be part of clk_rk3588
>> Honestly by looking at the DT node, I find the description of the clock
>> tree wrong to begin with.
>> The SD should not have the 2 clocks tied to the scmi agent, because this
>> is true only if it's running in normal world with a secure world agent
>> that will act as a middle man. So if we are running at a higher EL, as
>> in the SPL case, the clocks should be tied directly to the CRU.
>> So the node itself is described bad IMO.
>>
>> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
>> I am also thinking whether we should have the SCMI enabled in SPL as
>> well, but the agent/clock should just access the CRU directly, meaning
>> to do something at the agent level :
>> #ifdef CONFIG_SPL_BUILD
>> -> access CRU
>> #else
>> -> send SCMI message
>> #endif
>> Does this make more sense ?
>>
>> Or have some kind of wrapper driver that would act as a dispatcher
>> depending on the SPL/proper build ?
>
> Looks like the sdmmc clock is controlled by the securecru registers and I
> expect that this can only be configured in secure world, not sure how this
> could have been modeled differently.
Since it can work with a clock given by either scmi or securecru, I
would expect all clocks to be in the list, and the driver could start
the needed clock as per the EL level it's running into :)
e.g.
clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
HCLK_SD> , <&cru basic other clocks..>
Just my vision of how it could be modeled
>
> With the approach that I took I think the normal clk framework will behave
> as such dispatcher and clock gets tied to cru in SPL.
>
> #ifdef CONFIG_SPL_BUILD
> -> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
> #else
> -> bind protocol@14 to scmi clk driver -> send SCMI message
> #endif
This looks right, just that we would have to bring a lot of bloat to SPL
, firmware subsystem and things we may not want.
>
> Naming and placement of the SPL securecru driver could be improved.
> Not sure if any other soc beside rk3588 will need this at this moment.
securecru sounds better for me, I don't think we can have a scmi clock
fake driver like in vendor uboot, it has nothing 'scmi' about it.
>
>>
>>
>> Meanwhile, I will test your patches to see how they work on my setup, I
>> also have some things in progress including pinctrl in SPL for the rock5b.
>> Thanks for your detailed description,
>
> Thanks for the hint at pinctrl, I made some updates to [5] and could verify
> that sdmmc works when booting from emmc thanks to your pinctrl commit.
> Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
> and build a spi firmware image.
>
> There is an issue with non-DMA access in sdhci that requires the HACK commit
> for proper loading of atf, was hoping to disable SDMA in SPL like what is done
> using fifo-mode for sdmmc. But only first sector is read successfully then it
> fails, see below. Will take a closer look before I post eMMC series.
In your patches, I see this :
https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
but the sdmmc can ?
one possible workaround is to have DMA to DRAM and then relocate it to
SRAM using the CPU. Having DMA disabled for the whole IP may have
downsides, but this is U-boot, we don't expect to have anything else to
do with the CPU while the DMA master works its magic, and the CPU should
be faster.
I tested your patches together with the series I sent now
( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
boot correctly from SD-Card
Once you send them to the ML I can retest them.
Thanks !
>
> Trying to boot from MMC2
> 1
> - 0 'mmc@fe2c0000'
> - 1 'mmc@fe2e0000'
> - found
> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> clock is disabled (0Hz)
> clock is enabled (400000Hz)
> clk_set_rate(clk=5000d8, rate=400000)
> size=200, ptr=3b8, limit=100000: 5001b8
> clock is enabled (25000000Hz)
> clk_set_rate(clk=5000d8, rate=25000000)
> clk_set_rate(clk=5000d8, rate=25000000)
> clock is enabled (52000000Hz)
> clk_set_rate(clk=5000d8, rate=52000000)
> spl: mmc boot mode: raw
> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> hdr read sector 4000, count=1
> Found FIT
> size=a00, ptr=dc0, limit=100000: aligned to 5003c0
> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
> mmc_load_image_raw_sector: mmc block read error
> spl: mmc boot mode: fs
> Trying to boot from MMC1
>
> [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
>
> Regards,
> Jonas
>
>
>> Eugen
>>
>>>
>>> Regards,
>>> Jonas
>>>
>>>>
>>>> Thanks,
>>>> Eugen
>>>>
>>>>>
>>>>> Regards,
>>>>> Jonas
>>>>>
>>>>>>
>>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>>
>>>>>> Jagan.
>>>>>
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 14:21 ` Eugen Hristev
@ 2023-03-13 14:51 ` Eugen Hristev
2023-03-13 15:07 ` Mark Kettenis
1 sibling, 0 replies; 56+ messages in thread
From: Eugen Hristev @ 2023-03-13 14:51 UTC (permalink / raw)
To: Jonas Karlman, Jagan Teki
Cc: Simon Glass, Kever Yang, Philipp Tomsich, fatorangecat, u-boot
On 3/13/23 16:21, Eugen Hristev wrote:
> On 3/13/23 12:00, Jonas Karlman wrote:
>> On 2023-03-13 09:42, Eugen Hristev wrote:
>>> On 3/13/23 00:34, Jonas Karlman wrote:
>>>> Hi Eugen,
>>>>
>>>> On 2023-03-08 09:57, Eugen Hristev wrote:
>>>>> On 1/29/23 11:04, Jonas Karlman wrote:
>>>>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>
>>>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>>>>> Hi Jagan,
>>>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se>
>>>>>>>>>> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>>
>>>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org>
>>>>>>>>>>>> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai>
>>>>>>>>>>>>> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman
>>>>>>>>>>>>>> <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman
>>>>>>>>>>>>>>>> <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device
>>>>>>>>>>>>>>>>>> tree files are
>>>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned
>>>>>>>>>>>>>>>>>> in the commit
>>>>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible
>>>>>>>>>>>>>>>>>> with U-Boot so
>>>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>>>>
>>>>>>>
>>>>>>> < snip >
>>>>>>>
>>>>>>>>>
>>>>>>>>> As you can see in the logs above there is timeout waiting for
>>>>>>>>> data.
>>>>>>>>>
>>>>>>>>> I managed to find the issue and have a workaround that gets me
>>>>>>>>> longer
>>>>>>>>> in the boot process, there still seem to be other issue with
>>>>>>>>> the rk3588
>>>>>>>>> startup.
>>>>>>>>>
>>>>>>>>> --------
>>>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>>>>> Trying to boot from MMC1
>>>>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>>>>> INFO: Preloader serial: 2
>>>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>>>>> INFO: spec: 0x1
>>>>>>>>> INFO: ext 32k is not valid
>>>>>>>>> INFO: ddr: stride-en 4CH
>>>>>>>>> INFO: GICv3 without legacy support detected.
>>>>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>>>>> INFO: system boots from cpu-hwid-0
>>>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>>>>> INFO: BL31: Initializing runtime services
>>>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device
>>>>>>>>> without OPTEE initialization. SMC`s destined for OPTEE will
>>>>>>>>> return SMC_UNK
>>>>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>>>>> INFO: Entry point address = 0xa00000
>>>>>>>>> INFO: SPSR = 0x3c9
>>>>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>>>>
>>>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>>>>> Resetting CPU ...
>>>>>>>>> --------
>>>>>>>>>
>>>>>>>>> This was running on top of u-boot-dm/master
>>>>>>>>> 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>>>>
>>>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>>>>> fallback to default 400khz clock.
>>>>>>>>>
>>>>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>>>>> last debug line before the crash.
>>>>>>>>>
>>>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>>>>
>>>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>>>>
>>>>>>>> Source of the two main issues to get this series to run have
>>>>>>>> been the scmi clocks.
>>>>>>>> Vendor u-boot first load its scmi driver before trying to set
>>>>>>>> the cpu clocks.
>>>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>>>>
>>>>>>>> I also noticed that my sdram size series only detect the first
>>>>>>>> two channels of memory,
>>>>>>>> will respin a v2 of that series to add detection of all 4
>>>>>>>> channels of memory.
>>>>>>>>
>>>>>>>> [2]
>>>>>>>> https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>>>>
>>>>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>>>>> generically via the CLK framework or eMMC can be worth checking
>>>>>>> as it
>>>>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>>>>> that and was able to detect eMMC in U-Boot proper but got some
>>>>>>> issues
>>>>>>> while booting from eMMC [3]
>>>>>>
>>>>>> I have an updated branch at [4] that should support booting from
>>>>>> sdmmc and sdhci.
>>>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>>>>
>>>>>> This branch is based on u-boot/master
>>>>>> f147aa80f52989c7455022ca1ab959e8545feccc
>>>>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>>>>> I added a few fixup on top of that and a few additional patches,
>>>>>> please see commit message
>>>>>> for a very brief note on why the change was needed.
>>>>>> Feel free to squash fixups and pick commits up to and possible
>>>>>> including
>>>>>> "board: rockchip: Sync evb-rk3568_defconfig with
>>>>>> evb-rk3588_defconfig"
>>>>>> for a v2 of this series.
>>>>>>
>>>>>> The remaining sdhci patches needs a little bit more work,
>>>>>> I can send a separate series with emmc patches once they are fully
>>>>>> ready.
>>>>>>
>>>>>> The last commit adds a hack to mkimage to keep the data for atf-3
>>>>>> embedded in the FIT.
>>>>>> This ensures we do not run into problems trying to use dma from
>>>>>> emmc into secure pmu sram.
>>>>>> I think this is a more appropriate way to work around this issue,
>>>>>> instead of patching
>>>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very
>>>>>> special case.
>>>>>>
>>>>>> [4]
>>>>>> https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>>>>
>>>>> Hello Jagan, Jonas,
>>>>>
>>>>> I wanted to chip into this discussion, to ask whether you did anything
>>>>> more on the SD clock matter ?
>>>>
>>>> I have been busy this past week but have now had time to take a new
>>>> look
>>>> at the sdmmc issue, along with completing some other fixes.
>>>>
>>>>>
>>>>> I am currently using your workaround that creates dummy clocks in
>>>>> the DT
>>>>> and then the SD node just uses those, and it works, in the SPL, if and
>>>>> only if the bootrom also loads the SPL from SD.
>>>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>>>>> the rockusb protocol, and then, initializing the SD-Card from SPL
>>>>> fails
>>>>> utterly, namely, it cannot communicate with the card.
>>>>> I did some changes to have the pinctrl working at SPL level, which
>>>>> appears to be fine, but I would like to see what can be done about the
>>>>> clocks.
>>>>> Having the cru and all the required drivers at SPL level is the way to
>>>>> go ? The SPL should run before SCMI is required so it should be
>>>>> able to
>>>>> change all the clocks at the clock controller level ?
>>>>
>>>> I fully agree that we should have some sort of scmi clk driver so that
>>>> we can control the sdmmc clk in both SPL and U-Boot proper.
>>>>
>>>> As you have noticed the current workaround only works because bootrom
>>>> leave the clocks in a working state after it has loaded TPL/SPL from
>>>> the sdmmc device. When TPL/SPL is loaded from any other source it is
>>>> not be possible to read from the sdmmc device in u-boot.
>>>>
>>>> After having played around with the scmi agent driver and being
>>>> inspired
>>>> by the dummy scmi clk driver in vendor u-boot I have managed to create
>>>> something that could work. See top three commits from [5] for a working
>>>> proof-of-concept.
>>>>
>>>> What I did was to enable the scmi agent driver for use in u-boot proper
>>>> and keeping it disabled in SPL build. Then added a new scmi clk driver
>>>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
>>>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
>>>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
>>>> be able to configure the sdmmc clocks.
>>>>
>>>> The initial fixes commits in that branch should hit the list soon.
>>>> Will send the sdmmc related commits once I have had some time to do
>>>> more testing.
>>>>
>>>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
>>>>
>>> Hi Jonas,
>>>
>>> I managed to get it working in SPL as well, with a similar code inspired
>>> from the vendor tree.
>>> About the solution, I am not sure whether it should be called a scmi
>>> clock, and whether it should be part of clk_rk3588
>>> Honestly by looking at the DT node, I find the description of the clock
>>> tree wrong to begin with.
>>> The SD should not have the 2 clocks tied to the scmi agent, because this
>>> is true only if it's running in normal world with a secure world agent
>>> that will act as a middle man. So if we are running at a higher EL, as
>>> in the SPL case, the clocks should be tied directly to the CRU.
>>> So the node itself is described bad IMO.
>>>
>>> Anyway, if the node is set in stone from Linux, there isn;t much we
>>> can do.
>>> I am also thinking whether we should have the SCMI enabled in SPL as
>>> well, but the agent/clock should just access the CRU directly, meaning
>>> to do something at the agent level :
>>> #ifdef CONFIG_SPL_BUILD
>>> -> access CRU
>>> #else
>>> -> send SCMI message
>>> #endif
>>> Does this make more sense ?
>>>
>>> Or have some kind of wrapper driver that would act as a dispatcher
>>> depending on the SPL/proper build ?
>>
>> Looks like the sdmmc clock is controlled by the securecru registers and I
>> expect that this can only be configured in secure world, not sure how
>> this
>> could have been modeled differently.
>
> Since it can work with a clock given by either scmi or securecru, I
> would expect all clocks to be in the list, and the driver could start
> the needed clock as per the EL level it's running into :)
>
> e.g.
> clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
> HCLK_SD> , <&cru basic other clocks..>
>
> Just my vision of how it could be modeled
>
>>
>> With the approach that I took I think the normal clk framework will
>> behave
>> as such dispatcher and clock gets tied to cru in SPL.
>>
>> #ifdef CONFIG_SPL_BUILD
>> -> bind protocol@14 to rk3588 securecru driver -> read/write securecru
>> regs
>> #else
>> -> bind protocol@14 to scmi clk driver -> send SCMI message
>> #endif
>
> This looks right, just that we would have to bring a lot of bloat to SPL
> , firmware subsystem and things we may not want.
>>
>> Naming and placement of the SPL securecru driver could be improved.
>> Not sure if any other soc beside rk3588 will need this at this moment.
>
> securecru sounds better for me, I don't think we can have a scmi clock
> fake driver like in vendor uboot, it has nothing 'scmi' about it.
>
>>
>>>
>>>
>>> Meanwhile, I will test your patches to see how they work on my setup, I
>>> also have some things in progress including pinctrl in SPL for the
>>> rock5b.
>>> Thanks for your detailed description,
>>
>> Thanks for the hint at pinctrl, I made some updates to [5] and could
>> verify
>> that sdmmc works when booting from emmc thanks to your pinctrl commit.
>> Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
>> and build a spi firmware image.
>>
>> There is an issue with non-DMA access in sdhci that requires the HACK
>> commit
>> for proper loading of atf, was hoping to disable SDMA in SPL like what
>> is done
>> using fifo-mode for sdmmc. But only first sector is read successfully
>> then it
>> fails, see below. Will take a closer look before I post eMMC series.
>
> In your patches, I see this :
> https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
> Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
> sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
> but the sdmmc can ?
> one possible workaround is to have DMA to DRAM and then relocate it to
> SRAM using the CPU. Having DMA disabled for the whole IP may have
> downsides, but this is U-boot, we don't expect to have anything else to
> do with the CPU while the DMA master works its magic, and the CPU should
> be faster.
>
> I tested your patches together with the series I sent now
> ( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
> boot correctly from SD-Card
> Once you send them to the ML I can retest them.
> Thanks !
Sorry I just realized I had something extra in my tree. It does not work
without the dw_mmc reset after data error implementation.
I can say that it was the same for me when I had it done on my own.
I still have not figured it out why the first attempted SD mode does not
work, and after reset, going to legacy mode, SD transfers work.
I will send a patch with the dw reset code
Eugen
>
>>
>> Trying to boot from MMC2
>> 1
>> - 0 'mmc@fe2c0000'
>> - 1 'mmc@fe2e0000'
>> - found
>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>> clock is disabled (0Hz)
>> clock is enabled (400000Hz)
>> clk_set_rate(clk=5000d8, rate=400000)
>> size=200, ptr=3b8, limit=100000: 5001b8
>> clock is enabled (25000000Hz)
>> clk_set_rate(clk=5000d8, rate=25000000)
>> clk_set_rate(clk=5000d8, rate=25000000)
>> clock is enabled (52000000Hz)
>> clk_set_rate(clk=5000d8, rate=52000000)
>> spl: mmc boot mode: raw
>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>> hdr read sector 4000, count=1
>> Found FIT
>> size=a00, ptr=dc0, limit=100000: aligned to 5003c0
>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>> fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
>> mmc_load_image_raw_sector: mmc block read error
>> spl: mmc boot mode: fs
>> Trying to boot from MMC1
>>
>> [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
>>
>> Regards,
>> Jonas
>>
>>
>>> Eugen
>>>
>>>>
>>>> Regards,
>>>> Jonas
>>>>
>>>>>
>>>>> Thanks,
>>>>> Eugen
>>>>>
>>>>>>
>>>>>> Regards,
>>>>>> Jonas
>>>>>>
>>>>>>>
>>>>>>> [3]
>>>>>>> https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>>>
>>>>>>> Jagan.
>>>>>>
>>>>>
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 14:21 ` Eugen Hristev
2023-03-13 14:51 ` Eugen Hristev
@ 2023-03-13 15:07 ` Mark Kettenis
2023-03-13 15:21 ` Eugen Hristev
1 sibling, 1 reply; 56+ messages in thread
From: Mark Kettenis @ 2023-03-13 15:07 UTC (permalink / raw)
To: Eugen Hristev
Cc: jonas, jagan, sjg, kever.yang, philipp.tomsich, fatorangecat, u-boot
> Date: Mon, 13 Mar 2023 16:21:36 +0200
> From: Eugen Hristev <eugen.hristev@collabora.com>
>
> On 3/13/23 12:00, Jonas Karlman wrote:
> > On 2023-03-13 09:42, Eugen Hristev wrote:
> >> On 3/13/23 00:34, Jonas Karlman wrote:
> >>> Hi Eugen,
> >>>
> >>> On 2023-03-08 09:57, Eugen Hristev wrote:
> >>>> On 1/29/23 11:04, Jonas Karlman wrote:
> >>>>> On 2023-01-27 14:21, Jagan Teki wrote:
> >>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>
> >>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
> >>>>>>>> Hi Jagan,
> >>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
> >>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>>
> >>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
> >>>>>>>>>>> Hi Simon,
> >>>>>>>>>>>
> >>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
> >>>>>>>>>>>>
> >>>>>>>>>>>> Hi Jagan,
> >>>>>>>>>>>>
> >>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>> Hi Jagan,
> >>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
> >>>>>>>>>>>>>>> Hi Jonas,
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> Hi Jagan,
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
> >>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
> >>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
> >>>>>>>>>>>>>>>>> messages.
> >>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> >>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
> >>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>> Verified below BL31 versions,
> >>>>>>>>>>>>>>>>> bl31-v1.15
> >>>>>>>>>>>>>>>>> bl31-v1.21
> >>>>>>>>>>>>>>>>> bl31-v1.22
> >>>>>>>>>>>>>>>>> bl31-v1.23
> >>>>>>>>>>>>>>>>> bl31-v1.24
> >>>>>>>>>>>>>>>>> bl31-v1.25
> >>>>>>>>>>>>>>>>> bl31-v1.26
> >>>>>>>>>>>>>>>>>
> >>>>>>
> >>>>>> < snip >
> >>>>>>
> >>>>>>>>
> >>>>>>>> As you can see in the logs above there is timeout waiting for data.
> >>>>>>>>
> >>>>>>>> I managed to find the issue and have a workaround that gets me longer
> >>>>>>>> in the boot process, there still seem to be other issue with the rk3588
> >>>>>>>> startup.
> >>>>>>>>
> >>>>>>>> --------
> >>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
> >>>>>>>> Trying to boot from MMC1
> >>>>>>>> ## Checking hash(es) for config config-1 ... OK
> >>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
> >>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
> >>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
> >>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
> >>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
> >>>>>>>> INFO: Preloader serial: 2
> >>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
> >>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
> >>>>>>>> INFO: spec: 0x1
> >>>>>>>> INFO: ext 32k is not valid
> >>>>>>>> INFO: ddr: stride-en 4CH
> >>>>>>>> INFO: GICv3 without legacy support detected.
> >>>>>>>> INFO: ARM GICv3 driver initialized in EL3
> >>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
> >>>>>>>> INFO: system boots from cpu-hwid-0
> >>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
> >>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
> >>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
> >>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
> >>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
> >>>>>>>> INFO: BL31: Initialising Exception Handling Framework
> >>>>>>>> INFO: BL31: Initializing runtime services
> >>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
> >>>>>>>> ERROR: Error initializing runtime service opteed_fast
> >>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
> >>>>>>>> INFO: Entry point address = 0xa00000
> >>>>>>>> INFO: SPSR = 0x3c9
> >>>>>>>> "Synchronous Abort" handler, esr 0x96000000
> >>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
> >>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
> >>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
> >>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
> >>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
> >>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
> >>>>>>>> x10: 0000000000000034 x11: 0000000000000002
> >>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
> >>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
> >>>>>>>> x16: 0000000000000000 x17: 0000000000000000
> >>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
> >>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
> >>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
> >>>>>>>> x24: 0000000000000000 x25: 0000000000000000
> >>>>>>>> x26: 0000000000000000 x27: 0000000000000000
> >>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
> >>>>>>>>
> >>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
> >>>>>>>> Resetting CPU ...
> >>>>>>>> --------
> >>>>>>>>
> >>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
> >>>>>>>> with some rk3568 patches and this series, see [1].
> >>>>>>>>
> >>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
> >>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
> >>>>>>>> fallback to default 400khz clock.
> >>>>>>>>
> >>>>>>>> Next issue is the sync abort, looks it happens when u-boot
> >>>>>>>> tries to set clock rates based on devicetree. this is the
> >>>>>>>> last debug line before the crash.
> >>>>>>>>
> >>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
> >>>>>>>
> >>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
> >>>>>>>
> >>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
> >>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
> >>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
> >>>>>>>
> >>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
> >>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
> >>>>>>>
> >>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
> >>>>>>>
> >>>>>> Okay. We need to find a way to handle the clock value 400Khz
> >>>>>> generically via the CLK framework or eMMC can be worth checking as it
> >>>>>> doesn't involve SCMI and have a working patch set before MW. I did
> >>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
> >>>>>> while booting from eMMC [3]
> >>>>>
> >>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
> >>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
> >>>>>
> >>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
> >>>>> and I have included some rk3568 patches and your rk3588 rfc series.
> >>>>> I added a few fixup on top of that and a few additional patches, please see commit message
> >>>>> for a very brief note on why the change was needed.
> >>>>> Feel free to squash fixups and pick commits up to and possible including
> >>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
> >>>>> for a v2 of this series.
> >>>>>
> >>>>> The remaining sdhci patches needs a little bit more work,
> >>>>> I can send a separate series with emmc patches once they are fully ready.
> >>>>>
> >>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
> >>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
> >>>>> I think this is a more appropriate way to work around this issue, instead of patching
> >>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
> >>>>>
> >>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
> >>>>>
> >>>> Hello Jagan, Jonas,
> >>>>
> >>>> I wanted to chip into this discussion, to ask whether you did anything
> >>>> more on the SD clock matter ?
> >>>
> >>> I have been busy this past week but have now had time to take a new look
> >>> at the sdmmc issue, along with completing some other fixes.
> >>>
> >>>>
> >>>> I am currently using your workaround that creates dummy clocks in the DT
> >>>> and then the SD node just uses those, and it works, in the SPL, if and
> >>>> only if the bootrom also loads the SPL from SD.
> >>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
> >>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
> >>>> utterly, namely, it cannot communicate with the card.
> >>>> I did some changes to have the pinctrl working at SPL level, which
> >>>> appears to be fine, but I would like to see what can be done about the
> >>>> clocks.
> >>>> Having the cru and all the required drivers at SPL level is the way to
> >>>> go ? The SPL should run before SCMI is required so it should be able to
> >>>> change all the clocks at the clock controller level ?
> >>>
> >>> I fully agree that we should have some sort of scmi clk driver so that
> >>> we can control the sdmmc clk in both SPL and U-Boot proper.
> >>>
> >>> As you have noticed the current workaround only works because bootrom
> >>> leave the clocks in a working state after it has loaded TPL/SPL from
> >>> the sdmmc device. When TPL/SPL is loaded from any other source it is
> >>> not be possible to read from the sdmmc device in u-boot.
> >>>
> >>> After having played around with the scmi agent driver and being inspired
> >>> by the dummy scmi clk driver in vendor u-boot I have managed to create
> >>> something that could work. See top three commits from [5] for a working
> >>> proof-of-concept.
> >>>
> >>> What I did was to enable the scmi agent driver for use in u-boot proper
> >>> and keeping it disabled in SPL build. Then added a new scmi clk driver
> >>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
> >>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
> >>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
> >>> be able to configure the sdmmc clocks.
> >>>
> >>> The initial fixes commits in that branch should hit the list soon.
> >>> Will send the sdmmc related commits once I have had some time to do
> >>> more testing.
> >>>
> >>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
> >>>
> >> Hi Jonas,
> >>
> >> I managed to get it working in SPL as well, with a similar code inspired
> >> from the vendor tree.
> >> About the solution, I am not sure whether it should be called a scmi
> >> clock, and whether it should be part of clk_rk3588
> >> Honestly by looking at the DT node, I find the description of the clock
> >> tree wrong to begin with.
> >> The SD should not have the 2 clocks tied to the scmi agent, because this
> >> is true only if it's running in normal world with a secure world agent
> >> that will act as a middle man. So if we are running at a higher EL, as
> >> in the SPL case, the clocks should be tied directly to the CRU.
> >> So the node itself is described bad IMO.
> >>
> >> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
> >> I am also thinking whether we should have the SCMI enabled in SPL as
> >> well, but the agent/clock should just access the CRU directly, meaning
> >> to do something at the agent level :
> >> #ifdef CONFIG_SPL_BUILD
> >> -> access CRU
> >> #else
> >> -> send SCMI message
> >> #endif
> >> Does this make more sense ?
> >>
> >> Or have some kind of wrapper driver that would act as a dispatcher
> >> depending on the SPL/proper build ?
> >
> > Looks like the sdmmc clock is controlled by the securecru registers and I
> > expect that this can only be configured in secure world, not sure how this
> > could have been modeled differently.
>
> Since it can work with a clock given by either scmi or securecru, I
> would expect all clocks to be in the list, and the driver could start
> the needed clock as per the EL level it's running into :)
>
> e.g.
> clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
> HCLK_SD> , <&cru basic other clocks..>
>
> Just my vision of how it could be modeled
That is a change to the device tree bindings. The goal is to have
U-Boot use the same bindings and device tree as the official device
tree (which currently is the one in mainline Linux).
> > With the approach that I took I think the normal clk framework will behave
> > as such dispatcher and clock gets tied to cru in SPL.
> >
> > #ifdef CONFIG_SPL_BUILD
> > -> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
> > #else
> > -> bind protocol@14 to scmi clk driver -> send SCMI message
> > #endif
>
> This looks right, just that we would have to bring a lot of bloat to SPL
> , firmware subsystem and things we may not want.
I don't see why this would bring in a lot of bloat into SPL. The SPL
device tree will grow a little bit since it will have to include the
scmi nodes. And a little bit of additional code in the rk3588 clock
driver. Navigating the Kconfig stuff is a bit hard, but I don't think
this needs to pull in the firmware subsystem in SPL.
> >
> > Naming and placement of the SPL securecru driver could be improved.
> > Not sure if any other soc beside rk3588 will need this at this moment.
>
> securecru sounds better for me, I don't think we can have a scmi clock
> fake driver like in vendor uboot, it has nothing 'scmi' about it.
>
> >> Meanwhile, I will test your patches to see how they work on my setup, I
> >> also have some things in progress including pinctrl in SPL for the rock5b.
> >> Thanks for your detailed description,
> >
> > Thanks for the hint at pinctrl, I made some updates to [5] and could verify
> > that sdmmc works when booting from emmc thanks to your pinctrl commit.
> > Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
> > and build a spi firmware image.
> >
> > There is an issue with non-DMA access in sdhci that requires the HACK commit
> > for proper loading of atf, was hoping to disable SDMA in SPL like what is done
> > using fifo-mode for sdmmc. But only first sector is read successfully then it
> > fails, see below. Will take a closer look before I post eMMC series.
>
> In your patches, I see this :
> https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
> Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
> sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
> but the sdmmc can ?
> one possible workaround is to have DMA to DRAM and then relocate it to
> SRAM using the CPU. Having DMA disabled for the whole IP may have
> downsides, but this is U-boot, we don't expect to have anything else to
> do with the CPU while the DMA master works its magic, and the CPU should
> be faster.
>
> I tested your patches together with the series I sent now
> ( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
> boot correctly from SD-Card
> Once you send them to the ML I can retest them.
> Thanks !
>
> >
> > Trying to boot from MMC2
> > 1
> > - 0 'mmc@fe2c0000'
> > - 1 'mmc@fe2e0000'
> > - found
> > blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> > blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> > clock is disabled (0Hz)
> > clock is enabled (400000Hz)
> > clk_set_rate(clk=5000d8, rate=400000)
> > size=200, ptr=3b8, limit=100000: 5001b8
> > clock is enabled (25000000Hz)
> > clk_set_rate(clk=5000d8, rate=25000000)
> > clk_set_rate(clk=5000d8, rate=25000000)
> > clock is enabled (52000000Hz)
> > clk_set_rate(clk=5000d8, rate=52000000)
> > spl: mmc boot mode: raw
> > blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> > blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> > hdr read sector 4000, count=1
> > Found FIT
> > size=a00, ptr=dc0, limit=100000: aligned to 5003c0
> > blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> > blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> > fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
> > mmc_load_image_raw_sector: mmc block read error
> > spl: mmc boot mode: fs
> > Trying to boot from MMC1
> >
> > [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
> >
> > Regards,
> > Jonas
> >
> >
> >> Eugen
> >>
> >>>
> >>> Regards,
> >>> Jonas
> >>>
> >>>>
> >>>> Thanks,
> >>>> Eugen
> >>>>
> >>>>>
> >>>>> Regards,
> >>>>> Jonas
> >>>>>
> >>>>>>
> >>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
> >>>>>>
> >>>>>> Jagan.
> >>>>>
> >>>>
> >>>
> >>
> >
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 15:07 ` Mark Kettenis
@ 2023-03-13 15:21 ` Eugen Hristev
2023-03-13 15:34 ` Mark Kettenis
0 siblings, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-03-13 15:21 UTC (permalink / raw)
To: Mark Kettenis
Cc: jonas, jagan, sjg, kever.yang, philipp.tomsich, fatorangecat, u-boot
On 3/13/23 17:07, Mark Kettenis wrote:
>> Date: Mon, 13 Mar 2023 16:21:36 +0200
>> From: Eugen Hristev <eugen.hristev@collabora.com>
>>
>> On 3/13/23 12:00, Jonas Karlman wrote:
>>> On 2023-03-13 09:42, Eugen Hristev wrote:
>>>> On 3/13/23 00:34, Jonas Karlman wrote:
>>>>> Hi Eugen,
>>>>>
>>>>> On 2023-03-08 09:57, Eugen Hristev wrote:
>>>>>> On 1/29/23 11:04, Jonas Karlman wrote:
>>>>>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>
>>>>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>>>>>> Hi Jagan,
>>>>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>>>>>
>>>>>>>>
>>>>>>>> < snip >
>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>>>>>>
>>>>>>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>>>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>>>>>>> startup.
>>>>>>>>>>
>>>>>>>>>> --------
>>>>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>>>>>> Trying to boot from MMC1
>>>>>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>>>>>> INFO: Preloader serial: 2
>>>>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>>>>>> INFO: spec: 0x1
>>>>>>>>>> INFO: ext 32k is not valid
>>>>>>>>>> INFO: ddr: stride-en 4CH
>>>>>>>>>> INFO: GICv3 without legacy support detected.
>>>>>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>>>>>> INFO: system boots from cpu-hwid-0
>>>>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>>>>>> INFO: BL31: Initializing runtime services
>>>>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>>>>>> INFO: Entry point address = 0xa00000
>>>>>>>>>> INFO: SPSR = 0x3c9
>>>>>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>>>>>
>>>>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>>>>>> Resetting CPU ...
>>>>>>>>>> --------
>>>>>>>>>>
>>>>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>>>>>
>>>>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>>>>>> fallback to default 400khz clock.
>>>>>>>>>>
>>>>>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>>>>>> last debug line before the crash.
>>>>>>>>>>
>>>>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>>>>>
>>>>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>>>>>
>>>>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>>>>>
>>>>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>>>>>>
>>>>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>>>>>
>>>>>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>>>>>> generically via the CLK framework or eMMC can be worth checking as it
>>>>>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>>>>>>> while booting from eMMC [3]
>>>>>>>
>>>>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>>>>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>>>>>
>>>>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>>>>>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>>>>>> I added a few fixup on top of that and a few additional patches, please see commit message
>>>>>>> for a very brief note on why the change was needed.
>>>>>>> Feel free to squash fixups and pick commits up to and possible including
>>>>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>>>>>>> for a v2 of this series.
>>>>>>>
>>>>>>> The remaining sdhci patches needs a little bit more work,
>>>>>>> I can send a separate series with emmc patches once they are fully ready.
>>>>>>>
>>>>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>>>>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>>>>>>> I think this is a more appropriate way to work around this issue, instead of patching
>>>>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>>>>>>
>>>>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>>>>>
>>>>>> Hello Jagan, Jonas,
>>>>>>
>>>>>> I wanted to chip into this discussion, to ask whether you did anything
>>>>>> more on the SD clock matter ?
>>>>>
>>>>> I have been busy this past week but have now had time to take a new look
>>>>> at the sdmmc issue, along with completing some other fixes.
>>>>>
>>>>>>
>>>>>> I am currently using your workaround that creates dummy clocks in the DT
>>>>>> and then the SD node just uses those, and it works, in the SPL, if and
>>>>>> only if the bootrom also loads the SPL from SD.
>>>>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>>>>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
>>>>>> utterly, namely, it cannot communicate with the card.
>>>>>> I did some changes to have the pinctrl working at SPL level, which
>>>>>> appears to be fine, but I would like to see what can be done about the
>>>>>> clocks.
>>>>>> Having the cru and all the required drivers at SPL level is the way to
>>>>>> go ? The SPL should run before SCMI is required so it should be able to
>>>>>> change all the clocks at the clock controller level ?
>>>>>
>>>>> I fully agree that we should have some sort of scmi clk driver so that
>>>>> we can control the sdmmc clk in both SPL and U-Boot proper.
>>>>>
>>>>> As you have noticed the current workaround only works because bootrom
>>>>> leave the clocks in a working state after it has loaded TPL/SPL from
>>>>> the sdmmc device. When TPL/SPL is loaded from any other source it is
>>>>> not be possible to read from the sdmmc device in u-boot.
>>>>>
>>>>> After having played around with the scmi agent driver and being inspired
>>>>> by the dummy scmi clk driver in vendor u-boot I have managed to create
>>>>> something that could work. See top three commits from [5] for a working
>>>>> proof-of-concept.
>>>>>
>>>>> What I did was to enable the scmi agent driver for use in u-boot proper
>>>>> and keeping it disabled in SPL build. Then added a new scmi clk driver
>>>>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
>>>>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
>>>>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
>>>>> be able to configure the sdmmc clocks.
>>>>>
>>>>> The initial fixes commits in that branch should hit the list soon.
>>>>> Will send the sdmmc related commits once I have had some time to do
>>>>> more testing.
>>>>>
>>>>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
>>>>>
>>>> Hi Jonas,
>>>>
>>>> I managed to get it working in SPL as well, with a similar code inspired
>>>> from the vendor tree.
>>>> About the solution, I am not sure whether it should be called a scmi
>>>> clock, and whether it should be part of clk_rk3588
>>>> Honestly by looking at the DT node, I find the description of the clock
>>>> tree wrong to begin with.
>>>> The SD should not have the 2 clocks tied to the scmi agent, because this
>>>> is true only if it's running in normal world with a secure world agent
>>>> that will act as a middle man. So if we are running at a higher EL, as
>>>> in the SPL case, the clocks should be tied directly to the CRU.
>>>> So the node itself is described bad IMO.
>>>>
>>>> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
>>>> I am also thinking whether we should have the SCMI enabled in SPL as
>>>> well, but the agent/clock should just access the CRU directly, meaning
>>>> to do something at the agent level :
>>>> #ifdef CONFIG_SPL_BUILD
>>>> -> access CRU
>>>> #else
>>>> -> send SCMI message
>>>> #endif
>>>> Does this make more sense ?
>>>>
>>>> Or have some kind of wrapper driver that would act as a dispatcher
>>>> depending on the SPL/proper build ?
>>>
>>> Looks like the sdmmc clock is controlled by the securecru registers and I
>>> expect that this can only be configured in secure world, not sure how this
>>> could have been modeled differently.
>>
>> Since it can work with a clock given by either scmi or securecru, I
>> would expect all clocks to be in the list, and the driver could start
>> the needed clock as per the EL level it's running into :)
>>
>> e.g.
>> clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
>> HCLK_SD> , <&cru basic other clocks..>
>>
>> Just my vision of how it could be modeled
>
> That is a change to the device tree bindings. The goal is to have
> U-Boot use the same bindings and device tree as the official device
> tree (which currently is the one in mainline Linux).
That's right. A change in the bindings (and Linux )
>
>>> With the approach that I took I think the normal clk framework will behave
>>> as such dispatcher and clock gets tied to cru in SPL.
>>>
>>> #ifdef CONFIG_SPL_BUILD
>>> -> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
>>> #else
>>> -> bind protocol@14 to scmi clk driver -> send SCMI message
>>> #endif
>>
>> This looks right, just that we would have to bring a lot of bloat to SPL
>> , firmware subsystem and things we may not want.
>
> I don't see why this would bring in a lot of bloat into SPL. The SPL
> device tree will grow a little bit since it will have to include the
> scmi nodes. And a little bit of additional code in the rk3588 clock
> driver. Navigating the Kconfig stuff is a bit hard, but I don't think
> this needs to pull in the firmware subsystem in SPL.
When I tried this, I noticed that only the scmi agents look inside the
subnodes (e.g. protocol@14) which do not have a compatible, and then
they bind the subnodes to a driver found by a hardcoded search for
'scmi_clock'.
So, to get there, an agent is required, and firmware node, probed
firmware, probed 'scmi clock' . Then, probing it requires additional
things, because the agent wants a shared memory 'shmem' node, and you
end up also probing a SRAM area, allocating it to the space... that's
what I mean when I say that there might be much more bloat added than
just an additional clock set/get for securecru clocks.
>
>>>
>>> Naming and placement of the SPL securecru driver could be improved.
>>> Not sure if any other soc beside rk3588 will need this at this moment.
>>
>> securecru sounds better for me, I don't think we can have a scmi clock
>> fake driver like in vendor uboot, it has nothing 'scmi' about it.
>>
>>>> Meanwhile, I will test your patches to see how they work on my setup, I
>>>> also have some things in progress including pinctrl in SPL for the rock5b.
>>>> Thanks for your detailed description,
>>>
>>> Thanks for the hint at pinctrl, I made some updates to [5] and could verify
>>> that sdmmc works when booting from emmc thanks to your pinctrl commit.
>>> Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
>>> and build a spi firmware image.
>>>
>>> There is an issue with non-DMA access in sdhci that requires the HACK commit
>>> for proper loading of atf, was hoping to disable SDMA in SPL like what is done
>>> using fifo-mode for sdmmc. But only first sector is read successfully then it
>>> fails, see below. Will take a closer look before I post eMMC series.
>>
>> In your patches, I see this :
>> https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
>> Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
>> sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
>> but the sdmmc can ?
>> one possible workaround is to have DMA to DRAM and then relocate it to
>> SRAM using the CPU. Having DMA disabled for the whole IP may have
>> downsides, but this is U-boot, we don't expect to have anything else to
>> do with the CPU while the DMA master works its magic, and the CPU should
>> be faster.
>>
>> I tested your patches together with the series I sent now
>> ( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
>> boot correctly from SD-Card
>> Once you send them to the ML I can retest them.
>> Thanks !
>>
>>>
>>> Trying to boot from MMC2
>>> 1
>>> - 0 'mmc@fe2c0000'
>>> - 1 'mmc@fe2e0000'
>>> - found
>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>> clock is disabled (0Hz)
>>> clock is enabled (400000Hz)
>>> clk_set_rate(clk=5000d8, rate=400000)
>>> size=200, ptr=3b8, limit=100000: 5001b8
>>> clock is enabled (25000000Hz)
>>> clk_set_rate(clk=5000d8, rate=25000000)
>>> clk_set_rate(clk=5000d8, rate=25000000)
>>> clock is enabled (52000000Hz)
>>> clk_set_rate(clk=5000d8, rate=52000000)
>>> spl: mmc boot mode: raw
>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>> hdr read sector 4000, count=1
>>> Found FIT
>>> size=a00, ptr=dc0, limit=100000: aligned to 5003c0
>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>> fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
>>> mmc_load_image_raw_sector: mmc block read error
>>> spl: mmc boot mode: fs
>>> Trying to boot from MMC1
>>>
>>> [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
>>>
>>> Regards,
>>> Jonas
>>>
>>>
>>>> Eugen
>>>>
>>>>>
>>>>> Regards,
>>>>> Jonas
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>> Eugen
>>>>>>
>>>>>>>
>>>>>>> Regards,
>>>>>>> Jonas
>>>>>>>
>>>>>>>>
>>>>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>>>>
>>>>>>>> Jagan.
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
>>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 15:21 ` Eugen Hristev
@ 2023-03-13 15:34 ` Mark Kettenis
2023-03-13 15:49 ` Eugen Hristev
0 siblings, 1 reply; 56+ messages in thread
From: Mark Kettenis @ 2023-03-13 15:34 UTC (permalink / raw)
To: Eugen Hristev
Cc: jonas, jagan, sjg, kever.yang, philipp.tomsich, fatorangecat, u-boot
> Date: Mon, 13 Mar 2023 17:21:05 +0200
> From: Eugen Hristev <eugen.hristev@collabora.com>
>
> On 3/13/23 17:07, Mark Kettenis wrote:
> >> Date: Mon, 13 Mar 2023 16:21:36 +0200
> >> From: Eugen Hristev <eugen.hristev@collabora.com>
> >>
> >> On 3/13/23 12:00, Jonas Karlman wrote:
> >>> On 2023-03-13 09:42, Eugen Hristev wrote:
> >>>> On 3/13/23 00:34, Jonas Karlman wrote:
> >>>>> Hi Eugen,
> >>>>>
> >>>>> On 2023-03-08 09:57, Eugen Hristev wrote:
> >>>>>> On 1/29/23 11:04, Jonas Karlman wrote:
> >>>>>>> On 2023-01-27 14:21, Jagan Teki wrote:
> >>>>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>
> >>>>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
> >>>>>>>>>> Hi Jagan,
> >>>>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
> >>>>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>>>>
> >>>>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
> >>>>>>>>>>>>> Hi Simon,
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>> Hi Jagan,
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>> Hi Jagan,
> >>>>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
> >>>>>>>>>>>>>>>>> Hi Jonas,
> >>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>>> Hi Jagan,
> >>>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
> >>>>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
> >>>>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
> >>>>>>>>>>>>>>>>>>> messages.
> >>>>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
> >>>>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
> >>>>>>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>>>>>> Verified below BL31 versions,
> >>>>>>>>>>>>>>>>>>> bl31-v1.15
> >>>>>>>>>>>>>>>>>>> bl31-v1.21
> >>>>>>>>>>>>>>>>>>> bl31-v1.22
> >>>>>>>>>>>>>>>>>>> bl31-v1.23
> >>>>>>>>>>>>>>>>>>> bl31-v1.24
> >>>>>>>>>>>>>>>>>>> bl31-v1.25
> >>>>>>>>>>>>>>>>>>> bl31-v1.26
> >>>>>>>>>>>>>>>>>>>
> >>>>>>>>
> >>>>>>>> < snip >
> >>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>> As you can see in the logs above there is timeout waiting for data.
> >>>>>>>>>>
> >>>>>>>>>> I managed to find the issue and have a workaround that gets me longer
> >>>>>>>>>> in the boot process, there still seem to be other issue with the rk3588
> >>>>>>>>>> startup.
> >>>>>>>>>>
> >>>>>>>>>> --------
> >>>>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
> >>>>>>>>>> Trying to boot from MMC1
> >>>>>>>>>> ## Checking hash(es) for config config-1 ... OK
> >>>>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
> >>>>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
> >>>>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
> >>>>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
> >>>>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
> >>>>>>>>>> INFO: Preloader serial: 2
> >>>>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
> >>>>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
> >>>>>>>>>> INFO: spec: 0x1
> >>>>>>>>>> INFO: ext 32k is not valid
> >>>>>>>>>> INFO: ddr: stride-en 4CH
> >>>>>>>>>> INFO: GICv3 without legacy support detected.
> >>>>>>>>>> INFO: ARM GICv3 driver initialized in EL3
> >>>>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
> >>>>>>>>>> INFO: system boots from cpu-hwid-0
> >>>>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
> >>>>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
> >>>>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
> >>>>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
> >>>>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
> >>>>>>>>>> INFO: BL31: Initialising Exception Handling Framework
> >>>>>>>>>> INFO: BL31: Initializing runtime services
> >>>>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
> >>>>>>>>>> ERROR: Error initializing runtime service opteed_fast
> >>>>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
> >>>>>>>>>> INFO: Entry point address = 0xa00000
> >>>>>>>>>> INFO: SPSR = 0x3c9
> >>>>>>>>>> "Synchronous Abort" handler, esr 0x96000000
> >>>>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
> >>>>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
> >>>>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
> >>>>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
> >>>>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
> >>>>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
> >>>>>>>>>> x10: 0000000000000034 x11: 0000000000000002
> >>>>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
> >>>>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
> >>>>>>>>>> x16: 0000000000000000 x17: 0000000000000000
> >>>>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
> >>>>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
> >>>>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
> >>>>>>>>>> x24: 0000000000000000 x25: 0000000000000000
> >>>>>>>>>> x26: 0000000000000000 x27: 0000000000000000
> >>>>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
> >>>>>>>>>>
> >>>>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
> >>>>>>>>>> Resetting CPU ...
> >>>>>>>>>> --------
> >>>>>>>>>>
> >>>>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
> >>>>>>>>>> with some rk3568 patches and this series, see [1].
> >>>>>>>>>>
> >>>>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
> >>>>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
> >>>>>>>>>> fallback to default 400khz clock.
> >>>>>>>>>>
> >>>>>>>>>> Next issue is the sync abort, looks it happens when u-boot
> >>>>>>>>>> tries to set clock rates based on devicetree. this is the
> >>>>>>>>>> last debug line before the crash.
> >>>>>>>>>>
> >>>>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
> >>>>>>>>>
> >>>>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
> >>>>>>>>>
> >>>>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
> >>>>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
> >>>>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
> >>>>>>>>>
> >>>>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
> >>>>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
> >>>>>>>>>
> >>>>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
> >>>>>>>>>
> >>>>>>>> Okay. We need to find a way to handle the clock value 400Khz
> >>>>>>>> generically via the CLK framework or eMMC can be worth checking as it
> >>>>>>>> doesn't involve SCMI and have a working patch set before MW. I did
> >>>>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
> >>>>>>>> while booting from eMMC [3]
> >>>>>>>
> >>>>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
> >>>>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
> >>>>>>>
> >>>>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
> >>>>>>> and I have included some rk3568 patches and your rk3588 rfc series.
> >>>>>>> I added a few fixup on top of that and a few additional patches, please see commit message
> >>>>>>> for a very brief note on why the change was needed.
> >>>>>>> Feel free to squash fixups and pick commits up to and possible including
> >>>>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
> >>>>>>> for a v2 of this series.
> >>>>>>>
> >>>>>>> The remaining sdhci patches needs a little bit more work,
> >>>>>>> I can send a separate series with emmc patches once they are fully ready.
> >>>>>>>
> >>>>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
> >>>>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
> >>>>>>> I think this is a more appropriate way to work around this issue, instead of patching
> >>>>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
> >>>>>>>
> >>>>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
> >>>>>>>
> >>>>>> Hello Jagan, Jonas,
> >>>>>>
> >>>>>> I wanted to chip into this discussion, to ask whether you did anything
> >>>>>> more on the SD clock matter ?
> >>>>>
> >>>>> I have been busy this past week but have now had time to take a new look
> >>>>> at the sdmmc issue, along with completing some other fixes.
> >>>>>
> >>>>>>
> >>>>>> I am currently using your workaround that creates dummy clocks in the DT
> >>>>>> and then the SD node just uses those, and it works, in the SPL, if and
> >>>>>> only if the bootrom also loads the SPL from SD.
> >>>>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
> >>>>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
> >>>>>> utterly, namely, it cannot communicate with the card.
> >>>>>> I did some changes to have the pinctrl working at SPL level, which
> >>>>>> appears to be fine, but I would like to see what can be done about the
> >>>>>> clocks.
> >>>>>> Having the cru and all the required drivers at SPL level is the way to
> >>>>>> go ? The SPL should run before SCMI is required so it should be able to
> >>>>>> change all the clocks at the clock controller level ?
> >>>>>
> >>>>> I fully agree that we should have some sort of scmi clk driver so that
> >>>>> we can control the sdmmc clk in both SPL and U-Boot proper.
> >>>>>
> >>>>> As you have noticed the current workaround only works because bootrom
> >>>>> leave the clocks in a working state after it has loaded TPL/SPL from
> >>>>> the sdmmc device. When TPL/SPL is loaded from any other source it is
> >>>>> not be possible to read from the sdmmc device in u-boot.
> >>>>>
> >>>>> After having played around with the scmi agent driver and being inspired
> >>>>> by the dummy scmi clk driver in vendor u-boot I have managed to create
> >>>>> something that could work. See top three commits from [5] for a working
> >>>>> proof-of-concept.
> >>>>>
> >>>>> What I did was to enable the scmi agent driver for use in u-boot proper
> >>>>> and keeping it disabled in SPL build. Then added a new scmi clk driver
> >>>>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
> >>>>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
> >>>>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
> >>>>> be able to configure the sdmmc clocks.
> >>>>>
> >>>>> The initial fixes commits in that branch should hit the list soon.
> >>>>> Will send the sdmmc related commits once I have had some time to do
> >>>>> more testing.
> >>>>>
> >>>>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
> >>>>>
> >>>> Hi Jonas,
> >>>>
> >>>> I managed to get it working in SPL as well, with a similar code inspired
> >>>> from the vendor tree.
> >>>> About the solution, I am not sure whether it should be called a scmi
> >>>> clock, and whether it should be part of clk_rk3588
> >>>> Honestly by looking at the DT node, I find the description of the clock
> >>>> tree wrong to begin with.
> >>>> The SD should not have the 2 clocks tied to the scmi agent, because this
> >>>> is true only if it's running in normal world with a secure world agent
> >>>> that will act as a middle man. So if we are running at a higher EL, as
> >>>> in the SPL case, the clocks should be tied directly to the CRU.
> >>>> So the node itself is described bad IMO.
> >>>>
> >>>> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
> >>>> I am also thinking whether we should have the SCMI enabled in SPL as
> >>>> well, but the agent/clock should just access the CRU directly, meaning
> >>>> to do something at the agent level :
> >>>> #ifdef CONFIG_SPL_BUILD
> >>>> -> access CRU
> >>>> #else
> >>>> -> send SCMI message
> >>>> #endif
> >>>> Does this make more sense ?
> >>>>
> >>>> Or have some kind of wrapper driver that would act as a dispatcher
> >>>> depending on the SPL/proper build ?
> >>>
> >>> Looks like the sdmmc clock is controlled by the securecru registers and I
> >>> expect that this can only be configured in secure world, not sure how this
> >>> could have been modeled differently.
> >>
> >> Since it can work with a clock given by either scmi or securecru, I
> >> would expect all clocks to be in the list, and the driver could start
> >> the needed clock as per the EL level it's running into :)
> >>
> >> e.g.
> >> clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
> >> HCLK_SD> , <&cru basic other clocks..>
> >>
> >> Just my vision of how it could be modeled
> >
> > That is a change to the device tree bindings. The goal is to have
> > U-Boot use the same bindings and device tree as the official device
> > tree (which currently is the one in mainline Linux).
>
> That's right. A change in the bindings (and Linux )
And OpenBSD, and NetBSD, and ...
The device tree bindings are ABI. You can't change them unless they
are really relly broken.
> >>> With the approach that I took I think the normal clk framework will behave
> >>> as such dispatcher and clock gets tied to cru in SPL.
> >>>
> >>> #ifdef CONFIG_SPL_BUILD
> >>> -> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
> >>> #else
> >>> -> bind protocol@14 to scmi clk driver -> send SCMI message
> >>> #endif
> >>
> >> This looks right, just that we would have to bring a lot of bloat to SPL
> >> , firmware subsystem and things we may not want.
> >
> > I don't see why this would bring in a lot of bloat into SPL. The SPL
> > device tree will grow a little bit since it will have to include the
> > scmi nodes. And a little bit of additional code in the rk3588 clock
> > driver. Navigating the Kconfig stuff is a bit hard, but I don't think
> > this needs to pull in the firmware subsystem in SPL.
>
> When I tried this, I noticed that only the scmi agents look inside the
> subnodes (e.g. protocol@14) which do not have a compatible, and then
> they bind the subnodes to a driver found by a hardcoded search for
> 'scmi_clock'.
> So, to get there, an agent is required, and firmware node, probed
> firmware, probed 'scmi clock' . Then, probing it requires additional
> things, because the agent wants a shared memory 'shmem' node, and you
> end up also probing a SRAM area, allocating it to the space... that's
> what I mean when I say that there might be much more bloat added than
> just an additional clock set/get for securecru clocks.
No, Jonas added code to find the clock protocol node and bind the
clock driver to it:
https://github.com/Kwiboo/u-boot-rockchip/blob/3209167d7a518291f912964186ee90f10b555084/drivers/clk/rockchip/clk_rk3588.c#L1953
> >>> Naming and placement of the SPL securecru driver could be improved.
> >>> Not sure if any other soc beside rk3588 will need this at this moment.
> >>
> >> securecru sounds better for me, I don't think we can have a scmi clock
> >> fake driver like in vendor uboot, it has nothing 'scmi' about it.
> >>
> >>>> Meanwhile, I will test your patches to see how they work on my setup, I
> >>>> also have some things in progress including pinctrl in SPL for the rock5b.
> >>>> Thanks for your detailed description,
> >>>
> >>> Thanks for the hint at pinctrl, I made some updates to [5] and could verify
> >>> that sdmmc works when booting from emmc thanks to your pinctrl commit.
> >>> Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
> >>> and build a spi firmware image.
> >>>
> >>> There is an issue with non-DMA access in sdhci that requires the HACK commit
> >>> for proper loading of atf, was hoping to disable SDMA in SPL like what is done
> >>> using fifo-mode for sdmmc. But only first sector is read successfully then it
> >>> fails, see below. Will take a closer look before I post eMMC series.
> >>
> >> In your patches, I see this :
> >> https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
> >> Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
> >> sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
> >> but the sdmmc can ?
> >> one possible workaround is to have DMA to DRAM and then relocate it to
> >> SRAM using the CPU. Having DMA disabled for the whole IP may have
> >> downsides, but this is U-boot, we don't expect to have anything else to
> >> do with the CPU while the DMA master works its magic, and the CPU should
> >> be faster.
> >>
> >> I tested your patches together with the series I sent now
> >> ( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
> >> boot correctly from SD-Card
> >> Once you send them to the ML I can retest them.
> >> Thanks !
> >>
> >>>
> >>> Trying to boot from MMC2
> >>> 1
> >>> - 0 'mmc@fe2c0000'
> >>> - 1 'mmc@fe2e0000'
> >>> - found
> >>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> >>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> >>> clock is disabled (0Hz)
> >>> clock is enabled (400000Hz)
> >>> clk_set_rate(clk=5000d8, rate=400000)
> >>> size=200, ptr=3b8, limit=100000: 5001b8
> >>> clock is enabled (25000000Hz)
> >>> clk_set_rate(clk=5000d8, rate=25000000)
> >>> clk_set_rate(clk=5000d8, rate=25000000)
> >>> clock is enabled (52000000Hz)
> >>> clk_set_rate(clk=5000d8, rate=52000000)
> >>> spl: mmc boot mode: raw
> >>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> >>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> >>> hdr read sector 4000, count=1
> >>> Found FIT
> >>> size=a00, ptr=dc0, limit=100000: aligned to 5003c0
> >>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
> >>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
> >>> fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
> >>> mmc_load_image_raw_sector: mmc block read error
> >>> spl: mmc boot mode: fs
> >>> Trying to boot from MMC1
> >>>
> >>> [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
> >>>
> >>> Regards,
> >>> Jonas
> >>>
> >>>
> >>>> Eugen
> >>>>
> >>>>>
> >>>>> Regards,
> >>>>> Jonas
> >>>>>
> >>>>>>
> >>>>>> Thanks,
> >>>>>> Eugen
> >>>>>>
> >>>>>>>
> >>>>>>> Regards,
> >>>>>>> Jonas
> >>>>>>>
> >>>>>>>>
> >>>>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
> >>>>>>>>
> >>>>>>>> Jagan.
> >>>>>>>
> >>>>>>
> >>>>>
> >>>>
> >>>
> >>
> >>
>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 15:34 ` Mark Kettenis
@ 2023-03-13 15:49 ` Eugen Hristev
2023-03-13 19:15 ` Jonas Karlman
0 siblings, 1 reply; 56+ messages in thread
From: Eugen Hristev @ 2023-03-13 15:49 UTC (permalink / raw)
To: Mark Kettenis
Cc: jonas, jagan, sjg, kever.yang, philipp.tomsich, fatorangecat, u-boot
On 3/13/23 17:34, Mark Kettenis wrote:
>> Date: Mon, 13 Mar 2023 17:21:05 +0200
>> From: Eugen Hristev <eugen.hristev@collabora.com>
>>
>> On 3/13/23 17:07, Mark Kettenis wrote:
>>>> Date: Mon, 13 Mar 2023 16:21:36 +0200
>>>> From: Eugen Hristev <eugen.hristev@collabora.com>
>>>>
>>>> On 3/13/23 12:00, Jonas Karlman wrote:
>>>>> On 2023-03-13 09:42, Eugen Hristev wrote:
>>>>>> On 3/13/23 00:34, Jonas Karlman wrote:
>>>>>>> Hi Eugen,
>>>>>>>
>>>>>>> On 2023-03-08 09:57, Eugen Hristev wrote:
>>>>>>>> On 1/29/23 11:04, Jonas Karlman wrote:
>>>>>>>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>>>>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> < snip >
>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>>>>>>>>
>>>>>>>>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>>>>>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>>>>>>>>> startup.
>>>>>>>>>>>>
>>>>>>>>>>>> --------
>>>>>>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>>>>>>>> Trying to boot from MMC1
>>>>>>>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>>>>>>>> INFO: Preloader serial: 2
>>>>>>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>>>>>>>> INFO: spec: 0x1
>>>>>>>>>>>> INFO: ext 32k is not valid
>>>>>>>>>>>> INFO: ddr: stride-en 4CH
>>>>>>>>>>>> INFO: GICv3 without legacy support detected.
>>>>>>>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>>>>>>>> INFO: system boots from cpu-hwid-0
>>>>>>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>>>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>>>>>>>> INFO: BL31: Initializing runtime services
>>>>>>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>>>>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>>>>>>>> INFO: Entry point address = 0xa00000
>>>>>>>>>>>> INFO: SPSR = 0x3c9
>>>>>>>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>>>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>>>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>>>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>>>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>>>>>>>
>>>>>>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>>>>>>>> Resetting CPU ...
>>>>>>>>>>>> --------
>>>>>>>>>>>>
>>>>>>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>>>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>>>>>>>
>>>>>>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>>>>>>>> fallback to default 400khz clock.
>>>>>>>>>>>>
>>>>>>>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>>>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>>>>>>>> last debug line before the crash.
>>>>>>>>>>>>
>>>>>>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>>>>>>>
>>>>>>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>>>>>>>
>>>>>>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>>>>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>>>>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>>>>>>>
>>>>>>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>>>>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>>>>>>>>
>>>>>>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>>>>>>>
>>>>>>>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>>>>>>>> generically via the CLK framework or eMMC can be worth checking as it
>>>>>>>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>>>>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>>>>>>>>> while booting from eMMC [3]
>>>>>>>>>
>>>>>>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>>>>>>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>>>>>>>
>>>>>>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>>>>>>>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>>>>>>>> I added a few fixup on top of that and a few additional patches, please see commit message
>>>>>>>>> for a very brief note on why the change was needed.
>>>>>>>>> Feel free to squash fixups and pick commits up to and possible including
>>>>>>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>>>>>>>>> for a v2 of this series.
>>>>>>>>>
>>>>>>>>> The remaining sdhci patches needs a little bit more work,
>>>>>>>>> I can send a separate series with emmc patches once they are fully ready.
>>>>>>>>>
>>>>>>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>>>>>>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>>>>>>>>> I think this is a more appropriate way to work around this issue, instead of patching
>>>>>>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>>>>>>>>
>>>>>>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>>>>>>>
>>>>>>>> Hello Jagan, Jonas,
>>>>>>>>
>>>>>>>> I wanted to chip into this discussion, to ask whether you did anything
>>>>>>>> more on the SD clock matter ?
>>>>>>>
>>>>>>> I have been busy this past week but have now had time to take a new look
>>>>>>> at the sdmmc issue, along with completing some other fixes.
>>>>>>>
>>>>>>>>
>>>>>>>> I am currently using your workaround that creates dummy clocks in the DT
>>>>>>>> and then the SD node just uses those, and it works, in the SPL, if and
>>>>>>>> only if the bootrom also loads the SPL from SD.
>>>>>>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>>>>>>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
>>>>>>>> utterly, namely, it cannot communicate with the card.
>>>>>>>> I did some changes to have the pinctrl working at SPL level, which
>>>>>>>> appears to be fine, but I would like to see what can be done about the
>>>>>>>> clocks.
>>>>>>>> Having the cru and all the required drivers at SPL level is the way to
>>>>>>>> go ? The SPL should run before SCMI is required so it should be able to
>>>>>>>> change all the clocks at the clock controller level ?
>>>>>>>
>>>>>>> I fully agree that we should have some sort of scmi clk driver so that
>>>>>>> we can control the sdmmc clk in both SPL and U-Boot proper.
>>>>>>>
>>>>>>> As you have noticed the current workaround only works because bootrom
>>>>>>> leave the clocks in a working state after it has loaded TPL/SPL from
>>>>>>> the sdmmc device. When TPL/SPL is loaded from any other source it is
>>>>>>> not be possible to read from the sdmmc device in u-boot.
>>>>>>>
>>>>>>> After having played around with the scmi agent driver and being inspired
>>>>>>> by the dummy scmi clk driver in vendor u-boot I have managed to create
>>>>>>> something that could work. See top three commits from [5] for a working
>>>>>>> proof-of-concept.
>>>>>>>
>>>>>>> What I did was to enable the scmi agent driver for use in u-boot proper
>>>>>>> and keeping it disabled in SPL build. Then added a new scmi clk driver
>>>>>>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
>>>>>>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
>>>>>>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
>>>>>>> be able to configure the sdmmc clocks.
>>>>>>>
>>>>>>> The initial fixes commits in that branch should hit the list soon.
>>>>>>> Will send the sdmmc related commits once I have had some time to do
>>>>>>> more testing.
>>>>>>>
>>>>>>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
>>>>>>>
>>>>>> Hi Jonas,
>>>>>>
>>>>>> I managed to get it working in SPL as well, with a similar code inspired
>>>>>> from the vendor tree.
>>>>>> About the solution, I am not sure whether it should be called a scmi
>>>>>> clock, and whether it should be part of clk_rk3588
>>>>>> Honestly by looking at the DT node, I find the description of the clock
>>>>>> tree wrong to begin with.
>>>>>> The SD should not have the 2 clocks tied to the scmi agent, because this
>>>>>> is true only if it's running in normal world with a secure world agent
>>>>>> that will act as a middle man. So if we are running at a higher EL, as
>>>>>> in the SPL case, the clocks should be tied directly to the CRU.
>>>>>> So the node itself is described bad IMO.
>>>>>>
>>>>>> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
>>>>>> I am also thinking whether we should have the SCMI enabled in SPL as
>>>>>> well, but the agent/clock should just access the CRU directly, meaning
>>>>>> to do something at the agent level :
>>>>>> #ifdef CONFIG_SPL_BUILD
>>>>>> -> access CRU
>>>>>> #else
>>>>>> -> send SCMI message
>>>>>> #endif
>>>>>> Does this make more sense ?
>>>>>>
>>>>>> Or have some kind of wrapper driver that would act as a dispatcher
>>>>>> depending on the SPL/proper build ?
>>>>>
>>>>> Looks like the sdmmc clock is controlled by the securecru registers and I
>>>>> expect that this can only be configured in secure world, not sure how this
>>>>> could have been modeled differently.
>>>>
>>>> Since it can work with a clock given by either scmi or securecru, I
>>>> would expect all clocks to be in the list, and the driver could start
>>>> the needed clock as per the EL level it's running into :)
>>>>
>>>> e.g.
>>>> clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
>>>> HCLK_SD> , <&cru basic other clocks..>
>>>>
>>>> Just my vision of how it could be modeled
>>>
>>> That is a change to the device tree bindings. The goal is to have
>>> U-Boot use the same bindings and device tree as the official device
>>> tree (which currently is the one in mainline Linux).
>>
>> That's right. A change in the bindings (and Linux )
>
> And OpenBSD, and NetBSD, and ...
>
> The device tree bindings are ABI. You can't change them unless they
> are really relly broken.
For me, it's broken. You can't describe an SD hardware block, with
clocks given by SCMI node . It's not right. It's not like this in hardware.
It *can* be through SCMI, but it can also be via another way.
And the purpose of the ABI is to describe the hardware.
Unless we describe all of it, the description is wrong or at least
incomplete.
>
>>>>> With the approach that I took I think the normal clk framework will behave
>>>>> as such dispatcher and clock gets tied to cru in SPL.
>>>>>
>>>>> #ifdef CONFIG_SPL_BUILD
>>>>> -> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
>>>>> #else
>>>>> -> bind protocol@14 to scmi clk driver -> send SCMI message
>>>>> #endif
>>>>
>>>> This looks right, just that we would have to bring a lot of bloat to SPL
>>>> , firmware subsystem and things we may not want.
>>>
>>> I don't see why this would bring in a lot of bloat into SPL. The SPL
>>> device tree will grow a little bit since it will have to include the
>>> scmi nodes. And a little bit of additional code in the rk3588 clock
>>> driver. Navigating the Kconfig stuff is a bit hard, but I don't think
>>> this needs to pull in the firmware subsystem in SPL.
>>
>> When I tried this, I noticed that only the scmi agents look inside the
>> subnodes (e.g. protocol@14) which do not have a compatible, and then
>> they bind the subnodes to a driver found by a hardcoded search for
>> 'scmi_clock'.
>> So, to get there, an agent is required, and firmware node, probed
>> firmware, probed 'scmi clock' . Then, probing it requires additional
>> things, because the agent wants a shared memory 'shmem' node, and you
>> end up also probing a SRAM area, allocating it to the space... that's
>> what I mean when I say that there might be much more bloat added than
>> just an additional clock set/get for securecru clocks.
>
> No, Jonas added code to find the clock protocol node and bind the
> clock driver to it:
>
> https://github.com/Kwiboo/u-boot-rockchip/blob/3209167d7a518291f912964186ee90f10b555084/drivers/clk/rockchip/clk_rk3588.c#L1953
While this works, I somehow dislike it.
I think the parent of the protocol@14 should search and bind the node to
a driver, and not the clock driver.
I find it odd and might lead to weird situations, e.g. disable the cru
node or driver, then a node under firmware will no longer be probed.
I think we should respect the parent-child order of probing and not
searching through the DT for other nodes and mess with them.
>
>>>>> Naming and placement of the SPL securecru driver could be improved.
>>>>> Not sure if any other soc beside rk3588 will need this at this moment.
>>>>
>>>> securecru sounds better for me, I don't think we can have a scmi clock
>>>> fake driver like in vendor uboot, it has nothing 'scmi' about it.
>>>>
>>>>>> Meanwhile, I will test your patches to see how they work on my setup, I
>>>>>> also have some things in progress including pinctrl in SPL for the rock5b.
>>>>>> Thanks for your detailed description,
>>>>>
>>>>> Thanks for the hint at pinctrl, I made some updates to [5] and could verify
>>>>> that sdmmc works when booting from emmc thanks to your pinctrl commit.
>>>>> Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
>>>>> and build a spi firmware image.
>>>>>
>>>>> There is an issue with non-DMA access in sdhci that requires the HACK commit
>>>>> for proper loading of atf, was hoping to disable SDMA in SPL like what is done
>>>>> using fifo-mode for sdmmc. But only first sector is read successfully then it
>>>>> fails, see below. Will take a closer look before I post eMMC series.
>>>>
>>>> In your patches, I see this :
>>>> https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
>>>> Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
>>>> sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
>>>> but the sdmmc can ?
>>>> one possible workaround is to have DMA to DRAM and then relocate it to
>>>> SRAM using the CPU. Having DMA disabled for the whole IP may have
>>>> downsides, but this is U-boot, we don't expect to have anything else to
>>>> do with the CPU while the DMA master works its magic, and the CPU should
>>>> be faster.
>>>>
>>>> I tested your patches together with the series I sent now
>>>> ( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
>>>> boot correctly from SD-Card
>>>> Once you send them to the ML I can retest them.
>>>> Thanks !
>>>>
>>>>>
>>>>> Trying to boot from MMC2
>>>>> 1
>>>>> - 0 'mmc@fe2c0000'
>>>>> - 1 'mmc@fe2e0000'
>>>>> - found
>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>>>> clock is disabled (0Hz)
>>>>> clock is enabled (400000Hz)
>>>>> clk_set_rate(clk=5000d8, rate=400000)
>>>>> size=200, ptr=3b8, limit=100000: 5001b8
>>>>> clock is enabled (25000000Hz)
>>>>> clk_set_rate(clk=5000d8, rate=25000000)
>>>>> clk_set_rate(clk=5000d8, rate=25000000)
>>>>> clock is enabled (52000000Hz)
>>>>> clk_set_rate(clk=5000d8, rate=52000000)
>>>>> spl: mmc boot mode: raw
>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>>>> hdr read sector 4000, count=1
>>>>> Found FIT
>>>>> size=a00, ptr=dc0, limit=100000: aligned to 5003c0
>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>>>> fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
>>>>> mmc_load_image_raw_sector: mmc block read error
>>>>> spl: mmc boot mode: fs
>>>>> Trying to boot from MMC1
>>>>>
>>>>> [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
>>>>>
>>>>> Regards,
>>>>> Jonas
>>>>>
>>>>>
>>>>>> Eugen
>>>>>>
>>>>>>>
>>>>>>> Regards,
>>>>>>> Jonas
>>>>>>>
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>> Eugen
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Regards,
>>>>>>>>> Jonas
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>>>>>>
>>>>>>>>>> Jagan.
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>>
>>
>>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
2023-03-13 15:49 ` Eugen Hristev
@ 2023-03-13 19:15 ` Jonas Karlman
0 siblings, 0 replies; 56+ messages in thread
From: Jonas Karlman @ 2023-03-13 19:15 UTC (permalink / raw)
To: Eugen Hristev, Mark Kettenis
Cc: jagan, sjg, kever.yang, philipp.tomsich, fatorangecat, u-boot
On 2023-03-13 16:49, Eugen Hristev wrote:
> On 3/13/23 17:34, Mark Kettenis wrote:
>>> Date: Mon, 13 Mar 2023 17:21:05 +0200
>>> From: Eugen Hristev <eugen.hristev@collabora.com>
>>>
>>> On 3/13/23 17:07, Mark Kettenis wrote:
>>>>> Date: Mon, 13 Mar 2023 16:21:36 +0200
>>>>> From: Eugen Hristev <eugen.hristev@collabora.com>
>>>>>
>>>>> On 3/13/23 12:00, Jonas Karlman wrote:
>>>>>> On 2023-03-13 09:42, Eugen Hristev wrote:
>>>>>>> On 3/13/23 00:34, Jonas Karlman wrote:
>>>>>>>> Hi Eugen,
>>>>>>>>
>>>>>>>> On 2023-03-08 09:57, Eugen Hristev wrote:
>>>>>>>>> On 1/29/23 11:04, Jonas Karlman wrote:
>>>>>>>>>> On 2023-01-27 14:21, Jagan Teki wrote:
>>>>>>>>>>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>> On 2023-01-26 23:16, Jonas Karlman wrote:
>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>> On 2023-01-26 20:17, Jagan Teki wrote:
>>>>>>>>>>>>>> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On 2023-01-26 19:26, Jagan Teki wrote:
>>>>>>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 23:34, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 10:42, Jagan Teki <jagan@edgeble.ai> wrote:
>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>>> On 2023-01-26 17:51, Jagan Teki wrote:
>>>>>>>>>>>>>>>>>>>> Hi Jonas,
>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>> On Thu, 26 Jan 2023 at 04:17, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>> Hi Jagan,
>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>> On 2023-01-25 23:27, Jagan Teki wrote:
>>>>>>>>>>>>>>>>>>>>>> This series support Rockchip RK3588. All the device tree files are
>>>>>>>>>>>>>>>>>>>>>> synced from linux-next with the proper SHA1 mentioned in the commit
>>>>>>>>>>>>>>>>>>>>>> messages.
>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>>> Unfortunately, the BL31 from rkbin is not compatible with U-Boot so
>>>>>>>>>>>>>>>>>>>>>> it is failing to load ATF entry from SPL and hang.
>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>>> Verified below BL31 versions,
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.15
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.21
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.22
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.23
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.24
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.25
>>>>>>>>>>>>>>>>>>>>>> bl31-v1.26
>>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> < snip >
>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> As you can see in the logs above there is timeout waiting for data.
>>>>>>>>>>>>>
>>>>>>>>>>>>> I managed to find the issue and have a workaround that gets me longer
>>>>>>>>>>>>> in the boot process, there still seem to be other issue with the rk3588
>>>>>>>>>>>>> startup.
>>>>>>>>>>>>>
>>>>>>>>>>>>> --------
>>>>>>>>>>>>> U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +0000)
>>>>>>>>>>>>> Trying to boot from MMC1
>>>>>>>>>>>>> ## Checking hash(es) for config config-1 ... OK
>>>>>>>>>>>>> ## Checking hash(es) for Image atf-1 ... sha256+ OK
>>>>>>>>>>>>> ## Checking hash(es) for Image u-boot ... sha256+ OK
>>>>>>>>>>>>> ## Checking hash(es) for Image fdt-1 ... sha256+ OK
>>>>>>>>>>>>> ## Checking hash(es) for Image atf-2 ... sha256+ OK
>>>>>>>>>>>>> ## Checking hash(es) for Image atf-3 ... sha256+ OK
>>>>>>>>>>>>> INFO: Preloader serial: 2
>>>>>>>>>>>>> NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang
>>>>>>>>>>>>> NOTICE: BL31: Built : 09:59:49, Nov 21 2022
>>>>>>>>>>>>> INFO: spec: 0x1
>>>>>>>>>>>>> INFO: ext 32k is not valid
>>>>>>>>>>>>> INFO: ddr: stride-en 4CH
>>>>>>>>>>>>> INFO: GICv3 without legacy support detected.
>>>>>>>>>>>>> INFO: ARM GICv3 driver initialized in EL3
>>>>>>>>>>>>> INFO: valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
>>>>>>>>>>>>> INFO: system boots from cpu-hwid-0
>>>>>>>>>>>>> INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
>>>>>>>>>>>>> INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
>>>>>>>>>>>>> INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
>>>>>>>>>>>>> INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
>>>>>>>>>>>>> INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
>>>>>>>>>>>>> INFO: BL31: Initialising Exception Handling Framework
>>>>>>>>>>>>> INFO: BL31: Initializing runtime services
>>>>>>>>>>>>> WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
>>>>>>>>>>>>> ERROR: Error initializing runtime service opteed_fast
>>>>>>>>>>>>> INFO: BL31: Preparing for EL3 exit to normal world
>>>>>>>>>>>>> INFO: Entry point address = 0xa00000
>>>>>>>>>>>>> INFO: SPSR = 0x3c9
>>>>>>>>>>>>> "Synchronous Abort" handler, esr 0x96000000
>>>>>>>>>>>>> elr: 0000000000a23650 lr : 0000000000a24d9c
>>>>>>>>>>>>> x0 : 0000000000b7fbe8 x1 : 350003402a0003f3
>>>>>>>>>>>>> x2 : 0000000000000000 x3 : 0000000000b80ff0
>>>>>>>>>>>>> x4 : 0000000000b80ff0 x5 : 0000000000b80e88
>>>>>>>>>>>>> x6 : 0000000000000054 x7 : 0000000000000044
>>>>>>>>>>>>> x8 : 000000000000000a x9 : 0000000000000000
>>>>>>>>>>>>> x10: 0000000000000034 x11: 0000000000000002
>>>>>>>>>>>>> x12: 0000000000001988 x13: 0000000000b7fadc
>>>>>>>>>>>>> x14: 0000000000a7e808 x15: 0000000000a7e808
>>>>>>>>>>>>> x16: 0000000000000000 x17: 0000000000000000
>>>>>>>>>>>>> x18: 0000000000b7fe50 x19: 0000000000b7fbe8
>>>>>>>>>>>>> x20: 000000003c14dc00 x21: 000000003c14dc00
>>>>>>>>>>>>> x22: 0000000000a7e808 x23: 0000000000000000
>>>>>>>>>>>>> x24: 0000000000000000 x25: 0000000000000000
>>>>>>>>>>>>> x26: 0000000000000000 x27: 0000000000000000
>>>>>>>>>>>>> x28: 0000000000000000 x29: 0000000000b7fb80
>>>>>>>>>>>>>
>>>>>>>>>>>>> Code: f90013f5 f9400001 b4000201 f9400021 (f9403435)
>>>>>>>>>>>>> Resetting CPU ...
>>>>>>>>>>>>> --------
>>>>>>>>>>>>>
>>>>>>>>>>>>> This was running on top of u-boot-dm/master 060a65e899859dcbf42049a18be20ce7118e7c0e
>>>>>>>>>>>>> with some rk3568 patches and this series, see [1].
>>>>>>>>>>>>>
>>>>>>>>>>>>> The last 3 commits contains workaround to issue with sdmmc clock.
>>>>>>>>>>>>> dwmmc driver set sclk to (uint)-2, my workaround just adds a
>>>>>>>>>>>>> fallback to default 400khz clock.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Next issue is the sync abort, looks it happens when u-boot
>>>>>>>>>>>>> tries to set clock rates based on devicetree. this is the
>>>>>>>>>>>>> last debug line before the crash.
>>>>>>>>>>>>>
>>>>>>>>>>>>> clk_set_rate(clk=0000000000b7fba8, rate=1008000000)
>>>>>>>>>>>>
>>>>>>>>>>>> With the commit at [2] I can now successfully run U-Boot proper.
>>>>>>>>>>>>
>>>>>>>>>>>> Source of the two main issues to get this series to run have been the scmi clocks.
>>>>>>>>>>>> Vendor u-boot first load its scmi driver before trying to set the cpu clocks.
>>>>>>>>>>>> We can just remove it and leave setting a faster cpu rate to linux.
>>>>>>>>>>>>
>>>>>>>>>>>> I also noticed that my sdram size series only detect the first two channels of memory,
>>>>>>>>>>>> will respin a v2 of that series to add detection of all 4 channels of memory.
>>>>>>>>>>>>
>>>>>>>>>>>> [2] https://github.com/Kwiboo/u-boot-rockchip/commit/7e4fee945e725c0ec9ef3905c41ce367e77833b3
>>>>>>>>>>>>
>>>>>>>>>>> Okay. We need to find a way to handle the clock value 400Khz
>>>>>>>>>>> generically via the CLK framework or eMMC can be worth checking as it
>>>>>>>>>>> doesn't involve SCMI and have a working patch set before MW. I did
>>>>>>>>>>> that and was able to detect eMMC in U-Boot proper but got some issues
>>>>>>>>>>> while booting from eMMC [3]
>>>>>>>>>>
>>>>>>>>>> I have an updated branch at [4] that should support booting from sdmmc and sdhci.
>>>>>>>>>> Tested booting from both sd-card and emmc on my Radxa ROCK 5 Model B.
>>>>>>>>>>
>>>>>>>>>> This branch is based on u-boot/master f147aa80f52989c7455022ca1ab959e8545feccc
>>>>>>>>>> and I have included some rk3568 patches and your rk3588 rfc series.
>>>>>>>>>> I added a few fixup on top of that and a few additional patches, please see commit message
>>>>>>>>>> for a very brief note on why the change was needed.
>>>>>>>>>> Feel free to squash fixups and pick commits up to and possible including
>>>>>>>>>> "board: rockchip: Sync evb-rk3568_defconfig with evb-rk3588_defconfig"
>>>>>>>>>> for a v2 of this series.
>>>>>>>>>>
>>>>>>>>>> The remaining sdhci patches needs a little bit more work,
>>>>>>>>>> I can send a separate series with emmc patches once they are fully ready.
>>>>>>>>>>
>>>>>>>>>> The last commit adds a hack to mkimage to keep the data for atf-3 embedded in the FIT.
>>>>>>>>>> This ensures we do not run into problems trying to use dma from emmc into secure pmu sram.
>>>>>>>>>> I think this is a more appropriate way to work around this issue, instead of patching
>>>>>>>>>> u-boot spl_fit or sdhci core to use bounce buffers in a very special case.
>>>>>>>>>>
>>>>>>>>>> [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-master-v2
>>>>>>>>>>
>>>>>>>>> Hello Jagan, Jonas,
>>>>>>>>>
>>>>>>>>> I wanted to chip into this discussion, to ask whether you did anything
>>>>>>>>> more on the SD clock matter ?
>>>>>>>>
>>>>>>>> I have been busy this past week but have now had time to take a new look
>>>>>>>> at the sdmmc issue, along with completing some other fixes.
>>>>>>>>
>>>>>>>>>
>>>>>>>>> I am currently using your workaround that creates dummy clocks in the DT
>>>>>>>>> and then the SD node just uses those, and it works, in the SPL, if and
>>>>>>>>> only if the bootrom also loads the SPL from SD.
>>>>>>>>> I tried to have the SPL inside the SPI flash, or load it to DDR using
>>>>>>>>> the rockusb protocol, and then, initializing the SD-Card from SPL fails
>>>>>>>>> utterly, namely, it cannot communicate with the card.
>>>>>>>>> I did some changes to have the pinctrl working at SPL level, which
>>>>>>>>> appears to be fine, but I would like to see what can be done about the
>>>>>>>>> clocks.
>>>>>>>>> Having the cru and all the required drivers at SPL level is the way to
>>>>>>>>> go ? The SPL should run before SCMI is required so it should be able to
>>>>>>>>> change all the clocks at the clock controller level ?
>>>>>>>>
>>>>>>>> I fully agree that we should have some sort of scmi clk driver so that
>>>>>>>> we can control the sdmmc clk in both SPL and U-Boot proper.
>>>>>>>>
>>>>>>>> As you have noticed the current workaround only works because bootrom
>>>>>>>> leave the clocks in a working state after it has loaded TPL/SPL from
>>>>>>>> the sdmmc device. When TPL/SPL is loaded from any other source it is
>>>>>>>> not be possible to read from the sdmmc device in u-boot.
>>>>>>>>
>>>>>>>> After having played around with the scmi agent driver and being inspired
>>>>>>>> by the dummy scmi clk driver in vendor u-boot I have managed to create
>>>>>>>> something that could work. See top three commits from [5] for a working
>>>>>>>> proof-of-concept.
>>>>>>>>
>>>>>>>> What I did was to enable the scmi agent driver for use in u-boot proper
>>>>>>>> and keeping it disabled in SPL build. Then added a new scmi clk driver
>>>>>>>> that is enabled in SPL build, the rk3588 clk driver hooks the new clk
>>>>>>>> driver to the scmi_clk ofnode. I only implemented the get/set rate ops
>>>>>>>> for the two sdmmc clocks. With this both SPL and U-Boot proper should
>>>>>>>> be able to configure the sdmmc clocks.
>>>>>>>>
>>>>>>>> The initial fixes commits in that branch should hit the list soon.
>>>>>>>> Will send the sdmmc related commits once I have had some time to do
>>>>>>>> more testing.
>>>>>>>>
>>>>>>>> [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-fixes
>>>>>>>>
>>>>>>> Hi Jonas,
>>>>>>>
>>>>>>> I managed to get it working in SPL as well, with a similar code inspired
>>>>>>> from the vendor tree.
>>>>>>> About the solution, I am not sure whether it should be called a scmi
>>>>>>> clock, and whether it should be part of clk_rk3588
>>>>>>> Honestly by looking at the DT node, I find the description of the clock
>>>>>>> tree wrong to begin with.
>>>>>>> The SD should not have the 2 clocks tied to the scmi agent, because this
>>>>>>> is true only if it's running in normal world with a secure world agent
>>>>>>> that will act as a middle man. So if we are running at a higher EL, as
>>>>>>> in the SPL case, the clocks should be tied directly to the CRU.
>>>>>>> So the node itself is described bad IMO.
>>>>>>>
>>>>>>> Anyway, if the node is set in stone from Linux, there isn;t much we can do.
>>>>>>> I am also thinking whether we should have the SCMI enabled in SPL as
>>>>>>> well, but the agent/clock should just access the CRU directly, meaning
>>>>>>> to do something at the agent level :
>>>>>>> #ifdef CONFIG_SPL_BUILD
>>>>>>> -> access CRU
>>>>>>> #else
>>>>>>> -> send SCMI message
>>>>>>> #endif
>>>>>>> Does this make more sense ?
>>>>>>>
>>>>>>> Or have some kind of wrapper driver that would act as a dispatcher
>>>>>>> depending on the SPL/proper build ?
>>>>>>
>>>>>> Looks like the sdmmc clock is controlled by the securecru registers and I
>>>>>> expect that this can only be configured in secure world, not sure how this
>>>>>> could have been modeled differently.
>>>>>
>>>>> Since it can work with a clock given by either scmi or securecru, I
>>>>> would expect all clocks to be in the list, and the driver could start
>>>>> the needed clock as per the EL level it's running into :)
>>>>>
>>>>> e.g.
>>>>> clocks = <&scru CCLK_SD>, <&scru HCLK_SD>, <&scmi CCLK_SD>, <&scmi
>>>>> HCLK_SD> , <&cru basic other clocks..>
>>>>>
>>>>> Just my vision of how it could be modeled
>>>>
>>>> That is a change to the device tree bindings. The goal is to have
>>>> U-Boot use the same bindings and device tree as the official device
>>>> tree (which currently is the one in mainline Linux).
>>>
>>> That's right. A change in the bindings (and Linux )
>>
>> And OpenBSD, and NetBSD, and ...
>>
>> The device tree bindings are ABI. You can't change them unless they
>> are really relly broken.
>
> For me, it's broken. You can't describe an SD hardware block, with
> clocks given by SCMI node . It's not right. It's not like this in hardware.
> It *can* be through SCMI, but it can also be via another way.
> And the purpose of the ABI is to describe the hardware.
> Unless we describe all of it, the description is wrong or at least
> incomplete.
>
>>
>>>>>> With the approach that I took I think the normal clk framework will behave
>>>>>> as such dispatcher and clock gets tied to cru in SPL.
>>>>>>
>>>>>> #ifdef CONFIG_SPL_BUILD
>>>>>> -> bind protocol@14 to rk3588 securecru driver -> read/write securecru regs
>>>>>> #else
>>>>>> -> bind protocol@14 to scmi clk driver -> send SCMI message
>>>>>> #endif
>>>>>
>>>>> This looks right, just that we would have to bring a lot of bloat to SPL
>>>>> , firmware subsystem and things we may not want.
>>>>
>>>> I don't see why this would bring in a lot of bloat into SPL. The SPL
>>>> device tree will grow a little bit since it will have to include the
>>>> scmi nodes. And a little bit of additional code in the rk3588 clock
>>>> driver. Navigating the Kconfig stuff is a bit hard, but I don't think
>>>> this needs to pull in the firmware subsystem in SPL.
>>>
>>> When I tried this, I noticed that only the scmi agents look inside the
>>> subnodes (e.g. protocol@14) which do not have a compatible, and then
>>> they bind the subnodes to a driver found by a hardcoded search for
>>> 'scmi_clock'.
>>> So, to get there, an agent is required, and firmware node, probed
>>> firmware, probed 'scmi clock' . Then, probing it requires additional
>>> things, because the agent wants a shared memory 'shmem' node, and you
>>> end up also probing a SRAM area, allocating it to the space... that's
>>> what I mean when I say that there might be much more bloat added than
>>> just an additional clock set/get for securecru clocks.
>>
>> No, Jonas added code to find the clock protocol node and bind the
>> clock driver to it:
>>
>> https://github.com/Kwiboo/u-boot-rockchip/blob/3209167d7a518291f912964186ee90f10b555084/drivers/clk/rockchip/clk_rk3588.c#L1953
>>
> While this works, I somehow dislike it.
> I think the parent of the protocol@14 should search and bind the node to
> a driver, and not the clock driver.
>
> I find it odd and might lead to weird situations, e.g. disable the cru
> node or driver, then a node under firmware will no longer be probed.
> I think we should respect the parent-child order of probing and not
> searching through the DT for other nodes and mess with them.
Initially I also tried to re-use existing scmi agent but that had other
issues and felt like a big hack. Another approach could be to implement
a stub scmi agent driver with same purpose as the function, to probe and
bind protocol subnode to a secturecru driver. However, that just adds
another driver and options into the mix, use of a more simple function
seemed like a good compromise.
>
>>
>>>>>> Naming and placement of the SPL securecru driver could be improved.
>>>>>> Not sure if any other soc beside rk3588 will need this at this moment.
>>>>>
>>>>> securecru sounds better for me, I don't think we can have a scmi clock
>>>>> fake driver like in vendor uboot, it has nothing 'scmi' about it.
>>>>>
>>>>>>> Meanwhile, I will test your patches to see how they work on my setup, I
>>>>>>> also have some things in progress including pinctrl in SPL for the rock5b.
>>>>>>> Thanks for your detailed description,
>>>>>>
>>>>>> Thanks for the hint at pinctrl, I made some updates to [5] and could verify
>>>>>> that sdmmc works when booting from emmc thanks to your pinctrl commit.
>>>>>> Also enabled SPI NOR and eMMC for rock5b in [6], and could do a sf probe
>>>>>> and build a spi firmware image.
>>>>>>
>>>>>> There is an issue with non-DMA access in sdhci that requires the HACK commit
>>>>>> for proper loading of atf, was hoping to disable SDMA in SPL like what is done
>>>>>> using fifo-mode for sdmmc. But only first sector is read successfully then it
>>>>>> fails, see below. Will take a closer look before I post eMMC series.
>>>>>
>>>>> In your patches, I see this :
>>>>> https://github.com/Kwiboo/u-boot-rockchip/blob/rk35xx-fixes/arch/arm/dts/rk3588s-u-boot.dtsi#L61
>>>>> Perhaps the fifo-mode is intended for the sdhci(emmc) and not for
>>>>> sdmmc(sd-card) ? My understanding was that sdhci cannot do DMA to SRAM,
>>>>> but the sdmmc can ?
This was intended for the sdmmc, I had issues loading atf from sdmmc
until I added this. Will re-test on top of pinctrl and other patches.
It is unclear to me what the exact limitation is in regard to DMA to SRAM,
on rk3568 the firewall is programmed to allow DMA to SRAM for both
sdmmc and emmc.
>>>>> one possible workaround is to have DMA to DRAM and then relocate it to
>>>>> SRAM using the CPU. Having DMA disabled for the whole IP may have
>>>>> downsides, but this is U-boot, we don't expect to have anything else to
>>>>> do with the CPU while the DMA master works its magic, and the CPU should
>>>>> be faster.
That is how it is done in vendor u-boot, it use a bounce buffer in spl
fit load code, it has been submitted in different forms in the past.
I have tested a few different approaches, but usually go back to just
disable use of DMA in SPL using existing flags/options.
The fifo-mode flag seem to be specific to the dw_mmc driver, and using
a SPL_MMC_SDHCI_SDMA Kconfig to disable SDMA in SPL seemed like similar
approach. Yet, reading more then a single block failed in my testing.
>>>>>
>>>>> I tested your patches together with the series I sent now
>>>>> ( https://marc.info/?l=u-boot&m=167871206530072&w=2 ) and it appears to
>>>>> boot correctly from SD-Card
>>>>> Once you send them to the ML I can retest them.
Thanks, I am hoping to be able to send something out later today and/or
tomorrow.
Regards,
Jonas
>>>>> Thanks !
>>>>>
>>>>>>
>>>>>> Trying to boot from MMC2
>>>>>> 1
>>>>>> - 0 'mmc@fe2c0000'
>>>>>> - 1 'mmc@fe2e0000'
>>>>>> - found
>>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>>>>> clock is disabled (0Hz)
>>>>>> clock is enabled (400000Hz)
>>>>>> clk_set_rate(clk=5000d8, rate=400000)
>>>>>> size=200, ptr=3b8, limit=100000: 5001b8
>>>>>> clock is enabled (25000000Hz)
>>>>>> clk_set_rate(clk=5000d8, rate=25000000)
>>>>>> clk_set_rate(clk=5000d8, rate=25000000)
>>>>>> clock is enabled (52000000Hz)
>>>>>> clk_set_rate(clk=5000d8, rate=52000000)
>>>>>> spl: mmc boot mode: raw
>>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>>>>> hdr read sector 4000, count=1
>>>>>> Found FIT
>>>>>> size=a00, ptr=dc0, limit=100000: aligned to 5003c0
>>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2c0000.blk, 67, 0
>>>>>> blk_find_device: uclass_id=67, devnum=1: mmc@fe2e0000.blk, 67, 1
>>>>>> fit read sector 4000, sectors=5, dst=5003c0, count=0, size=0xa00
>>>>>> mmc_load_image_raw_sector: mmc block read error
>>>>>> spl: mmc boot mode: fs
>>>>>> Trying to boot from MMC1
>>>>>>
>>>>>> [6] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3588-emmc
>>>>>>
>>>>>> Regards,
>>>>>> Jonas
>>>>>>
>>>>>>
>>>>>>> Eugen
>>>>>>>
>>>>>>>>
>>>>>>>> Regards,
>>>>>>>> Jonas
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>> Eugen
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Regards,
>>>>>>>>>> Jonas
>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> [3] https://github.com/edgeble/u-boot/commit/1389822228ac3dfe8d3cd3513db6a32a5c898b7f
>>>>>>>>>>>
>>>>>>>>>>> Jagan.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>>
>>>
>>>
>
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2023-03-13 19:15 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-25 22:27 [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 01/16] rockchip: mkimage: Add rk3588 support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 02/16] arm: rockchip: Add cru header for rk3588 Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 03/16] arm: rockchip: Add grf " Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 04/16] dt-bindings: clk: Add dt-binding header for RK3588 Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 05/16] clk: rockchip: Add rk3588 clk support Jagan Teki
2023-02-02 14:09 ` Eugen Hristev
2023-01-25 22:27 ` [RFC PATCH 06/16] clk: rockchip: pll: Add pll_rk3588 type for rk3588 Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 07/16] ram: rockchip: Add rk3588 ddr driver support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 08/16] dt-bindings: power: Add power-domain header for rk3588 Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 09/16] dt-bindings: reset: add rk3588 reset definitions Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 10/16] arm: rockchip: Add ioc header for rk3588 Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC Jagan Teki
2023-02-02 14:06 ` Eugen Hristev
2023-01-25 22:27 ` [RFC PATCH 12/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 13/16] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 14/16] arm: rockchip: Add RK3588 arch core support Jagan Teki
2023-01-25 22:27 ` [RFC PATCH 15/16] ARM: dts: rockchip: Add rk3588-u-boot.dtsi Jagan Teki
2023-01-27 13:33 ` Eugen Hristev
2023-01-27 13:37 ` Jagan Teki
2023-01-27 13:50 ` Eugen Hristev
2023-01-27 14:23 ` Jagan Teki
2023-01-27 15:19 ` Eugen Hristev
2023-01-25 22:27 ` [RFC PATCH 16/16] board: rockchip: Add Edgeble Neural Compute Module 6 Jagan Teki
2023-02-02 8:23 ` Eugen Hristev
2023-02-16 9:03 ` Jagan Teki
2023-01-25 22:47 ` [RFC PATCH 00/16] arm: Add Rockchip RK3588 support Jonas Karlman
2023-01-26 16:51 ` Jagan Teki
2023-01-26 16:58 ` Jonas Karlman
2023-01-26 17:42 ` Jagan Teki
2023-01-26 18:01 ` Jagan Teki
2023-01-26 18:04 ` Simon Glass
2023-01-26 18:26 ` Jagan Teki
2023-01-26 19:03 ` Jonas Karlman
2023-01-26 19:17 ` Jagan Teki
2023-01-26 22:16 ` Jonas Karlman
2023-01-26 23:43 ` Jonas Karlman
2023-01-27 13:21 ` Jagan Teki
2023-01-29 9:04 ` Jonas Karlman
2023-03-08 8:57 ` Eugen Hristev
2023-03-12 22:34 ` Jonas Karlman
2023-03-13 8:42 ` Eugen Hristev
2023-03-13 10:00 ` Jonas Karlman
2023-03-13 14:21 ` Eugen Hristev
2023-03-13 14:51 ` Eugen Hristev
2023-03-13 15:07 ` Mark Kettenis
2023-03-13 15:21 ` Eugen Hristev
2023-03-13 15:34 ` Mark Kettenis
2023-03-13 15:49 ` Eugen Hristev
2023-03-13 19:15 ` Jonas Karlman
2023-01-26 19:14 ` Simon Glass
2023-01-26 19:35 ` Jagan Teki
2023-01-29 9:47 ` Kever Yang
2023-01-29 9:58 ` Jonas Karlman
2023-01-30 0:55 ` Kever Yang
2023-01-30 5:19 ` Jagan Teki
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