* [Qemu-devel] [PATCH v4 01/20] hw/i386: Move ACPI header definitions in an arch-independent location
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-15 2:26 ` Shannon Zhao
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file Shannon Zhao
` (20 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
The ACPI related header file acpi-defs.h, includes definitions that
apply on other architectures as well. Move it in `include/hw/acpi/`
to sanely include it from other architectures.
Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/i386/acpi-build.c | 2 +-
hw/i386/acpi-defs.h | 368 --------------------------------------------
include/hw/acpi/acpi-defs.h | 368 ++++++++++++++++++++++++++++++++++++++++++++
tests/bios-tables-test.c | 2 +-
4 files changed, 370 insertions(+), 370 deletions(-)
delete mode 100644 hw/i386/acpi-defs.h
create mode 100644 include/hw/acpi/acpi-defs.h
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d0a5c85..83644e4 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -33,7 +33,7 @@
#include "hw/i386/pc.h"
#include "target-i386/cpu.h"
#include "hw/timer/hpet.h"
-#include "hw/i386/acpi-defs.h"
+#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/acpi/bios-linker-loader.h"
diff --git a/hw/i386/acpi-defs.h b/hw/i386/acpi-defs.h
deleted file mode 100644
index c4468f8..0000000
--- a/hw/i386/acpi-defs.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef QEMU_ACPI_DEFS_H
-#define QEMU_ACPI_DEFS_H
-
-enum {
- ACPI_FADT_F_WBINVD,
- ACPI_FADT_F_WBINVD_FLUSH,
- ACPI_FADT_F_PROC_C1,
- ACPI_FADT_F_P_LVL2_UP,
- ACPI_FADT_F_PWR_BUTTON,
- ACPI_FADT_F_SLP_BUTTON,
- ACPI_FADT_F_FIX_RTC,
- ACPI_FADT_F_RTC_S4,
- ACPI_FADT_F_TMR_VAL_EXT,
- ACPI_FADT_F_DCK_CAP,
- ACPI_FADT_F_RESET_REG_SUP,
- ACPI_FADT_F_SEALED_CASE,
- ACPI_FADT_F_HEADLESS,
- ACPI_FADT_F_CPU_SW_SLP,
- ACPI_FADT_F_PCI_EXP_WAK,
- ACPI_FADT_F_USE_PLATFORM_CLOCK,
- ACPI_FADT_F_S4_RTC_STS_VALID,
- ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
- ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
- ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
- ACPI_FADT_F_HW_REDUCED_ACPI,
- ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
-};
-
-/*
- * ACPI 2.0 Generic Address Space definition.
- */
-struct Acpi20GenericAddress {
- uint8_t address_space_id;
- uint8_t register_bit_width;
- uint8_t register_bit_offset;
- uint8_t reserved;
- uint64_t address;
-} QEMU_PACKED;
-typedef struct Acpi20GenericAddress Acpi20GenericAddress;
-
-struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
- uint64_t signature; /* ACPI signature, contains "RSD PTR " */
- uint8_t checksum; /* To make sum of struct == 0 */
- uint8_t oem_id [6]; /* OEM identification */
- uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
- uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
- uint32_t length; /* XSDT Length in bytes including hdr */
- uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
- uint8_t extended_checksum; /* Checksum of entire table */
- uint8_t reserved [3]; /* Reserved field must be 0 */
-} QEMU_PACKED;
-typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
-
-/* Table structure from Linux kernel (the ACPI tables are under the
- BSD license) */
-
-
-#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
- uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
- uint32_t length; /* Length of table, in bytes, including header */ \
- uint8_t revision; /* ACPI Specification minor version # */ \
- uint8_t checksum; /* To make sum of entire table == 0 */ \
- uint8_t oem_id [6]; /* OEM identification */ \
- uint8_t oem_table_id [8]; /* OEM table identification */ \
- uint32_t oem_revision; /* OEM revision number */ \
- uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \
- uint32_t asl_compiler_revision; /* ASL compiler revision number */
-
-
-struct AcpiTableHeader /* ACPI common table header */
-{
- ACPI_TABLE_HEADER_DEF
-} QEMU_PACKED;
-typedef struct AcpiTableHeader AcpiTableHeader;
-
-/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
- */
-struct AcpiFadtDescriptorRev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t firmware_ctrl; /* Physical address of FACS */
- uint32_t dsdt; /* Physical address of DSDT */
- uint8_t model; /* System Interrupt Model */
- uint8_t reserved1; /* Reserved */
- uint16_t sci_int; /* System vector of SCI interrupt */
- uint32_t smi_cmd; /* Port address of SMI command port */
- uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
- uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
- uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- uint8_t reserved2; /* Reserved - must be zero */
- uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
- uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
- uint8_t reserved3; /* Reserved */
- uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
- uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
- uint16_t flush_size; /* Size of area read to flush caches */
- uint16_t flush_stride; /* Stride used in flushing caches */
- uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
- uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
- uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
- uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
- uint8_t century; /* Index to century in RTC CMOS RAM */
- uint8_t reserved4; /* Reserved */
- uint8_t reserved4a; /* Reserved */
- uint8_t reserved4b; /* Reserved */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
-
-/*
- * ACPI 1.0 Root System Description Table (RSDT)
- */
-struct AcpiRsdtDescriptorRev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t table_offset_entry[0]; /* Array of pointers to other */
- /* ACPI tables */
-} QEMU_PACKED;
-typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
-
-/*
- * ACPI 1.0 Firmware ACPI Control Structure (FACS)
- */
-struct AcpiFacsDescriptorRev1
-{
- uint32_t signature; /* ACPI Signature */
- uint32_t length; /* Length of structure, in bytes */
- uint32_t hardware_signature; /* Hardware configuration signature */
- uint32_t firmware_waking_vector; /* ACPI OS waking vector */
- uint32_t global_lock; /* Global Lock */
- uint32_t flags;
- uint8_t resverved3 [40]; /* Reserved - must be zero */
-} QEMU_PACKED;
-typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
-
-/*
- * Differentiated System Description Table (DSDT)
- */
-
-/*
- * MADT values and structures
- */
-
-/* Values for MADT PCATCompat */
-
-#define ACPI_DUAL_PIC 0
-#define ACPI_MULTIPLE_APIC 1
-
-/* Master MADT */
-
-struct AcpiMultipleApicTable
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t local_apic_address; /* Physical address of local APIC */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
-
-/* Values for Type in APIC sub-headers */
-
-#define ACPI_APIC_PROCESSOR 0
-#define ACPI_APIC_IO 1
-#define ACPI_APIC_XRUPT_OVERRIDE 2
-#define ACPI_APIC_NMI 3
-#define ACPI_APIC_LOCAL_NMI 4
-#define ACPI_APIC_ADDRESS_OVERRIDE 5
-#define ACPI_APIC_IO_SAPIC 6
-#define ACPI_APIC_LOCAL_SAPIC 7
-#define ACPI_APIC_XRUPT_SOURCE 8
-#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
-
-/*
- * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
- */
-#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
- uint8_t type; \
- uint8_t length;
-
-/* Sub-structures for MADT */
-
-struct AcpiMadtProcessorApic
-{
- ACPI_SUB_HEADER_DEF
- uint8_t processor_id; /* ACPI processor id */
- uint8_t local_apic_id; /* Processor's local APIC id */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
-
-struct AcpiMadtIoApic
-{
- ACPI_SUB_HEADER_DEF
- uint8_t io_apic_id; /* I/O APIC ID */
- uint8_t reserved; /* Reserved - must be zero */
- uint32_t address; /* APIC physical address */
- uint32_t interrupt; /* Global system interrupt where INTI
- * lines start */
-} QEMU_PACKED;
-typedef struct AcpiMadtIoApic AcpiMadtIoApic;
-
-struct AcpiMadtIntsrcovr {
- ACPI_SUB_HEADER_DEF
- uint8_t bus;
- uint8_t source;
- uint32_t gsi;
- uint16_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
-
-struct AcpiMadtLocalNmi {
- ACPI_SUB_HEADER_DEF
- uint8_t processor_id; /* ACPI processor id */
- uint16_t flags; /* MPS INTI flags */
- uint8_t lint; /* Local APIC LINT# */
-} QEMU_PACKED;
-typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
-
-/*
- * HPET Description Table
- */
-struct Acpi20Hpet {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t timer_block_id;
- Acpi20GenericAddress addr;
- uint8_t hpet_number;
- uint16_t min_tick;
- uint8_t page_protect;
-} QEMU_PACKED;
-typedef struct Acpi20Hpet Acpi20Hpet;
-
-/*
- * SRAT (NUMA topology description) table
- */
-
-struct AcpiSystemResourceAffinityTable
-{
- ACPI_TABLE_HEADER_DEF
- uint32_t reserved1;
- uint32_t reserved2[2];
-} QEMU_PACKED;
-typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
-
-#define ACPI_SRAT_PROCESSOR 0
-#define ACPI_SRAT_MEMORY 1
-
-struct AcpiSratProcessorAffinity
-{
- ACPI_SUB_HEADER_DEF
- uint8_t proximity_lo;
- uint8_t local_apic_id;
- uint32_t flags;
- uint8_t local_sapic_eid;
- uint8_t proximity_hi[3];
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
-
-struct AcpiSratMemoryAffinity
-{
- ACPI_SUB_HEADER_DEF
- uint8_t proximity[4];
- uint16_t reserved1;
- uint64_t base_addr;
- uint64_t range_length;
- uint32_t reserved2;
- uint32_t flags;
- uint32_t reserved3[2];
-} QEMU_PACKED;
-typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
-
-/* PCI fw r3.0 MCFG table. */
-/* Subtable */
-struct AcpiMcfgAllocation {
- uint64_t address; /* Base address, processor-relative */
- uint16_t pci_segment; /* PCI segment group number */
- uint8_t start_bus_number; /* Starting PCI Bus number */
- uint8_t end_bus_number; /* Final PCI Bus number */
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
-
-struct AcpiTableMcfg {
- ACPI_TABLE_HEADER_DEF;
- uint8_t reserved[8];
- AcpiMcfgAllocation allocation[0];
-} QEMU_PACKED;
-typedef struct AcpiTableMcfg AcpiTableMcfg;
-
-/*
- * TCPA Description Table
- */
-struct Acpi20Tcpa {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint16_t platform_class;
- uint32_t log_area_minimum_length;
- uint64_t log_area_start_address;
-} QEMU_PACKED;
-typedef struct Acpi20Tcpa Acpi20Tcpa;
-
-/* DMAR - DMA Remapping table r2.2 */
-struct AcpiTableDmar {
- ACPI_TABLE_HEADER_DEF
- uint8_t host_address_width; /* Maximum DMA physical addressability */
- uint8_t flags;
- uint8_t reserved[10];
-} QEMU_PACKED;
-typedef struct AcpiTableDmar AcpiTableDmar;
-
-/* Masks for Flags field above */
-#define ACPI_DMAR_INTR_REMAP 1
-#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
-
-/* Values for sub-structure type for DMAR */
-enum {
- ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
- ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
- ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
- ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
- ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
- ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
-};
-
-/*
- * Sub-structures for DMAR
- */
-/* Type 0: Hardware Unit Definition */
-struct AcpiDmarHardwareUnit {
- uint16_t type;
- uint16_t length;
- uint8_t flags;
- uint8_t reserved;
- uint16_t pci_segment; /* The PCI Segment associated with this unit */
- uint64_t address; /* Base address of remapping hardware register-set */
-} QEMU_PACKED;
-typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
-
-/* Masks for Flags field above */
-#define ACPI_DMAR_INCLUDE_PCI_ALL 1
-
-#endif
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
new file mode 100644
index 0000000..c4468f8
--- /dev/null
+++ b/include/hw/acpi/acpi-defs.h
@@ -0,0 +1,368 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef QEMU_ACPI_DEFS_H
+#define QEMU_ACPI_DEFS_H
+
+enum {
+ ACPI_FADT_F_WBINVD,
+ ACPI_FADT_F_WBINVD_FLUSH,
+ ACPI_FADT_F_PROC_C1,
+ ACPI_FADT_F_P_LVL2_UP,
+ ACPI_FADT_F_PWR_BUTTON,
+ ACPI_FADT_F_SLP_BUTTON,
+ ACPI_FADT_F_FIX_RTC,
+ ACPI_FADT_F_RTC_S4,
+ ACPI_FADT_F_TMR_VAL_EXT,
+ ACPI_FADT_F_DCK_CAP,
+ ACPI_FADT_F_RESET_REG_SUP,
+ ACPI_FADT_F_SEALED_CASE,
+ ACPI_FADT_F_HEADLESS,
+ ACPI_FADT_F_CPU_SW_SLP,
+ ACPI_FADT_F_PCI_EXP_WAK,
+ ACPI_FADT_F_USE_PLATFORM_CLOCK,
+ ACPI_FADT_F_S4_RTC_STS_VALID,
+ ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
+ ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
+ ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
+ ACPI_FADT_F_HW_REDUCED_ACPI,
+ ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
+};
+
+/*
+ * ACPI 2.0 Generic Address Space definition.
+ */
+struct Acpi20GenericAddress {
+ uint8_t address_space_id;
+ uint8_t register_bit_width;
+ uint8_t register_bit_offset;
+ uint8_t reserved;
+ uint64_t address;
+} QEMU_PACKED;
+typedef struct Acpi20GenericAddress Acpi20GenericAddress;
+
+struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */
+ uint64_t signature; /* ACPI signature, contains "RSD PTR " */
+ uint8_t checksum; /* To make sum of struct == 0 */
+ uint8_t oem_id [6]; /* OEM identification */
+ uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
+ uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
+ uint32_t length; /* XSDT Length in bytes including hdr */
+ uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
+ uint8_t extended_checksum; /* Checksum of entire table */
+ uint8_t reserved [3]; /* Reserved field must be 0 */
+} QEMU_PACKED;
+typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
+
+/* Table structure from Linux kernel (the ACPI tables are under the
+ BSD license) */
+
+
+#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
+ uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
+ uint32_t length; /* Length of table, in bytes, including header */ \
+ uint8_t revision; /* ACPI Specification minor version # */ \
+ uint8_t checksum; /* To make sum of entire table == 0 */ \
+ uint8_t oem_id [6]; /* OEM identification */ \
+ uint8_t oem_table_id [8]; /* OEM table identification */ \
+ uint32_t oem_revision; /* OEM revision number */ \
+ uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \
+ uint32_t asl_compiler_revision; /* ASL compiler revision number */
+
+
+struct AcpiTableHeader /* ACPI common table header */
+{
+ ACPI_TABLE_HEADER_DEF
+} QEMU_PACKED;
+typedef struct AcpiTableHeader AcpiTableHeader;
+
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
+struct AcpiFadtDescriptorRev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t firmware_ctrl; /* Physical address of FACS */
+ uint32_t dsdt; /* Physical address of DSDT */
+ uint8_t model; /* System Interrupt Model */
+ uint8_t reserved1; /* Reserved */
+ uint16_t sci_int; /* System vector of SCI interrupt */
+ uint32_t smi_cmd; /* Port address of SMI command port */
+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
+ uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
+ uint8_t reserved2; /* Reserved - must be zero */
+ uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
+ uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
+ uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
+ uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
+ uint8_t reserved3; /* Reserved */
+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
+ uint16_t flush_size; /* Size of area read to flush caches */
+ uint16_t flush_stride; /* Stride used in flushing caches */
+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
+ uint8_t century; /* Index to century in RTC CMOS RAM */
+ uint8_t reserved4; /* Reserved */
+ uint8_t reserved4a; /* Reserved */
+ uint8_t reserved4b; /* Reserved */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+struct AcpiRsdtDescriptorRev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t table_offset_entry[0]; /* Array of pointers to other */
+ /* ACPI tables */
+} QEMU_PACKED;
+typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+struct AcpiFacsDescriptorRev1
+{
+ uint32_t signature; /* ACPI Signature */
+ uint32_t length; /* Length of structure, in bytes */
+ uint32_t hardware_signature; /* Hardware configuration signature */
+ uint32_t firmware_waking_vector; /* ACPI OS waking vector */
+ uint32_t global_lock; /* Global Lock */
+ uint32_t flags;
+ uint8_t resverved3 [40]; /* Reserved - must be zero */
+} QEMU_PACKED;
+typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
+
+/*
+ * Differentiated System Description Table (DSDT)
+ */
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define ACPI_DUAL_PIC 0
+#define ACPI_MULTIPLE_APIC 1
+
+/* Master MADT */
+
+struct AcpiMultipleApicTable
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t local_apic_address; /* Physical address of local APIC */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
+
+/* Values for Type in APIC sub-headers */
+
+#define ACPI_APIC_PROCESSOR 0
+#define ACPI_APIC_IO 1
+#define ACPI_APIC_XRUPT_OVERRIDE 2
+#define ACPI_APIC_NMI 3
+#define ACPI_APIC_LOCAL_NMI 4
+#define ACPI_APIC_ADDRESS_OVERRIDE 5
+#define ACPI_APIC_IO_SAPIC 6
+#define ACPI_APIC_LOCAL_SAPIC 7
+#define ACPI_APIC_XRUPT_SOURCE 8
+#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
+ uint8_t type; \
+ uint8_t length;
+
+/* Sub-structures for MADT */
+
+struct AcpiMadtProcessorApic
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t processor_id; /* ACPI processor id */
+ uint8_t local_apic_id; /* Processor's local APIC id */
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
+
+struct AcpiMadtIoApic
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t io_apic_id; /* I/O APIC ID */
+ uint8_t reserved; /* Reserved - must be zero */
+ uint32_t address; /* APIC physical address */
+ uint32_t interrupt; /* Global system interrupt where INTI
+ * lines start */
+} QEMU_PACKED;
+typedef struct AcpiMadtIoApic AcpiMadtIoApic;
+
+struct AcpiMadtIntsrcovr {
+ ACPI_SUB_HEADER_DEF
+ uint8_t bus;
+ uint8_t source;
+ uint32_t gsi;
+ uint16_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
+
+struct AcpiMadtLocalNmi {
+ ACPI_SUB_HEADER_DEF
+ uint8_t processor_id; /* ACPI processor id */
+ uint16_t flags; /* MPS INTI flags */
+ uint8_t lint; /* Local APIC LINT# */
+} QEMU_PACKED;
+typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+
+/*
+ * HPET Description Table
+ */
+struct Acpi20Hpet {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t timer_block_id;
+ Acpi20GenericAddress addr;
+ uint8_t hpet_number;
+ uint16_t min_tick;
+ uint8_t page_protect;
+} QEMU_PACKED;
+typedef struct Acpi20Hpet Acpi20Hpet;
+
+/*
+ * SRAT (NUMA topology description) table
+ */
+
+struct AcpiSystemResourceAffinityTable
+{
+ ACPI_TABLE_HEADER_DEF
+ uint32_t reserved1;
+ uint32_t reserved2[2];
+} QEMU_PACKED;
+typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
+
+#define ACPI_SRAT_PROCESSOR 0
+#define ACPI_SRAT_MEMORY 1
+
+struct AcpiSratProcessorAffinity
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t proximity_lo;
+ uint8_t local_apic_id;
+ uint32_t flags;
+ uint8_t local_sapic_eid;
+ uint8_t proximity_hi[3];
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
+
+struct AcpiSratMemoryAffinity
+{
+ ACPI_SUB_HEADER_DEF
+ uint8_t proximity[4];
+ uint16_t reserved1;
+ uint64_t base_addr;
+ uint64_t range_length;
+ uint32_t reserved2;
+ uint32_t flags;
+ uint32_t reserved3[2];
+} QEMU_PACKED;
+typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
+
+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct AcpiMcfgAllocation {
+ uint64_t address; /* Base address, processor-relative */
+ uint16_t pci_segment; /* PCI segment group number */
+ uint8_t start_bus_number; /* Starting PCI Bus number */
+ uint8_t end_bus_number; /* Final PCI Bus number */
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
+
+struct AcpiTableMcfg {
+ ACPI_TABLE_HEADER_DEF;
+ uint8_t reserved[8];
+ AcpiMcfgAllocation allocation[0];
+} QEMU_PACKED;
+typedef struct AcpiTableMcfg AcpiTableMcfg;
+
+/*
+ * TCPA Description Table
+ */
+struct Acpi20Tcpa {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint16_t platform_class;
+ uint32_t log_area_minimum_length;
+ uint64_t log_area_start_address;
+} QEMU_PACKED;
+typedef struct Acpi20Tcpa Acpi20Tcpa;
+
+/* DMAR - DMA Remapping table r2.2 */
+struct AcpiTableDmar {
+ ACPI_TABLE_HEADER_DEF
+ uint8_t host_address_width; /* Maximum DMA physical addressability */
+ uint8_t flags;
+ uint8_t reserved[10];
+} QEMU_PACKED;
+typedef struct AcpiTableDmar AcpiTableDmar;
+
+/* Masks for Flags field above */
+#define ACPI_DMAR_INTR_REMAP 1
+#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
+
+/* Values for sub-structure type for DMAR */
+enum {
+ ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
+ ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
+ ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
+ ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
+ ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
+ ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
+};
+
+/*
+ * Sub-structures for DMAR
+ */
+/* Type 0: Hardware Unit Definition */
+struct AcpiDmarHardwareUnit {
+ uint16_t type;
+ uint16_t length;
+ uint8_t flags;
+ uint8_t reserved;
+ uint16_t pci_segment; /* The PCI Segment associated with this unit */
+ uint64_t address; /* Base address of remapping hardware register-set */
+} QEMU_PACKED;
+typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
+
+/* Masks for Flags field above */
+#define ACPI_DMAR_INCLUDE_PCI_ALL 1
+
+#endif
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 735ac61..7e85dc4 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -17,7 +17,7 @@
#include "qemu-common.h"
#include "libqtest.h"
#include "qemu/compiler.h"
-#include "hw/i386/acpi-defs.h"
+#include "hw/acpi/acpi-defs.h"
#include "hw/i386/smbios.h"
#include "qemu/bitmap.h"
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 01/20] hw/i386: Move ACPI header definitions in an arch-independent location
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
@ 2015-04-15 2:26 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-15 2:26 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, peter.huangpeng, shannon.zhao
On 2015/4/3 18:03, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> The ACPI related header file acpi-defs.h, includes definitions that
> apply on other architectures as well. Move it in `include/hw/acpi/`
> to sanely include it from other architectures.
>
> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/i386/acpi-build.c | 2 +-
> hw/i386/acpi-defs.h | 368 --------------------------------------------
> include/hw/acpi/acpi-defs.h | 368 ++++++++++++++++++++++++++++++++++++++++++++
> tests/bios-tables-test.c | 2 +-
> 4 files changed, 370 insertions(+), 370 deletions(-)
> delete mode 100644 hw/i386/acpi-defs.h
> create mode 100644 include/hw/acpi/acpi-defs.h
Hi Igor, Michael，
Could you help review the patch 01, 02 of this patchset as they are releated to x86 ACPI?
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
` (19 subsequent siblings)
21 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Move generic acpi building helpers into dedictated file and this
can be shared with other machines.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 58 ++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 77 ---------------------------------------------
include/hw/acpi/aml-build.h | 29 +++++++++++++++++
3 files changed, 87 insertions(+), 77 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index d7945f6..8d01959 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -26,6 +26,7 @@
#include <string.h>
#include "hw/acpi/aml-build.h"
#include "qemu/bswap.h"
+#include "hw/acpi/bios-linker-loader.h"
static GArray *build_alloc_array(void)
{
@@ -891,3 +892,60 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
dec, addr_gran, addr_min, addr_max,
addr_trans, len, flags);
}
+
+void
+build_header(GArray *linker, GArray *table_data,
+ AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
+{
+ memcpy(&h->signature, sig, 4);
+ h->length = cpu_to_le32(len);
+ h->revision = rev;
+ memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
+ memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
+ memcpy(h->oem_table_id + 4, sig, 4);
+ h->oem_revision = cpu_to_le32(1);
+ memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
+ h->asl_compiler_revision = cpu_to_le32(1);
+ h->checksum = 0;
+ /* Checksum to be filled in by Guest linker */
+ bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
+ table_data->data, h, len, &h->checksum);
+}
+
+void *acpi_data_push(GArray *table_data, unsigned size)
+{
+ unsigned off = table_data->len;
+ g_array_set_size(table_data, off + size);
+ return table_data->data + off;
+}
+
+unsigned acpi_data_len(GArray *table)
+{
+#if GLIB_CHECK_VERSION(2, 22, 0)
+ assert(g_array_get_element_size(table) == 1);
+#endif
+ return table->len;
+}
+
+void acpi_add_table(GArray *table_offsets, GArray *table_data)
+{
+ uint32_t offset = cpu_to_le32(table_data->len);
+ g_array_append_val(table_offsets, offset);
+}
+
+void acpi_build_tables_init(AcpiBuildTables *tables)
+{
+ tables->rsdp = g_array_new(false, true /* clear */, 1);
+ tables->table_data = g_array_new(false, true /* clear */, 1);
+ tables->tcpalog = g_array_new(false, true /* clear */, 1);
+ tables->linker = bios_linker_loader_init();
+}
+
+void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
+{
+ void *linker_data = bios_linker_loader_cleanup(tables->linker);
+ g_free(linker_data);
+ g_array_free(tables->rsdp, true);
+ g_array_free(tables->table_data, true);
+ g_array_free(tables->tcpalog, mfre);
+}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 83644e4..7b5210e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -70,9 +70,6 @@
#define ACPI_BUILD_TABLE_SIZE 0x20000
-/* Reserve RAM space for tables: add another order of magnitude. */
-#define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
-
/* #define DEBUG_ACPI_BUILD */
#ifdef DEBUG_ACPI_BUILD
#define ACPI_BUILD_DPRINTF(fmt, ...) \
@@ -267,51 +264,8 @@ static void acpi_get_pci_info(PcPciInfo *info)
NULL);
}
-#define ACPI_BUILD_APPNAME "Bochs"
-#define ACPI_BUILD_APPNAME6 "BOCHS "
-#define ACPI_BUILD_APPNAME4 "BXPC"
-
-#define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
-#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
-#define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
-
-static void
-build_header(GArray *linker, GArray *table_data,
- AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
-{
- memcpy(&h->signature, sig, 4);
- h->length = cpu_to_le32(len);
- h->revision = rev;
- memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
- memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
- memcpy(h->oem_table_id + 4, sig, 4);
- h->oem_revision = cpu_to_le32(1);
- memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
- h->asl_compiler_revision = cpu_to_le32(1);
- h->checksum = 0;
- /* Checksum to be filled in by Guest linker */
- bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
- table_data->data, h, len, &h->checksum);
-}
-
-/* End here */
#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
-static inline void *acpi_data_push(GArray *table_data, unsigned size)
-{
- unsigned off = table_data->len;
- g_array_set_size(table_data, off + size);
- return table_data->data + off;
-}
-
-static unsigned acpi_data_len(GArray *table)
-{
-#if GLIB_CHECK_VERSION(2, 22, 0)
- assert(g_array_get_element_size(table) == 1);
-#endif
- return table->len;
-}
-
static void acpi_align_size(GArray *blob, unsigned align)
{
/* Align size to multiple of given size. This reduces the chance
@@ -320,12 +274,6 @@ static void acpi_align_size(GArray *blob, unsigned align)
g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
}
-static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
-{
- uint32_t offset = cpu_to_le32(table_data->len);
- g_array_append_val(table_offsets, offset);
-}
-
/* FACS */
static void
build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
@@ -1296,31 +1244,6 @@ build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
}
typedef
-struct AcpiBuildTables {
- GArray *table_data;
- GArray *rsdp;
- GArray *tcpalog;
- GArray *linker;
-} AcpiBuildTables;
-
-static inline void acpi_build_tables_init(AcpiBuildTables *tables)
-{
- tables->rsdp = g_array_new(false, true /* clear */, 1);
- tables->table_data = g_array_new(false, true /* clear */, 1);
- tables->tcpalog = g_array_new(false, true /* clear */, 1);
- tables->linker = bios_linker_loader_init();
-}
-
-static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
-{
- void *linker_data = bios_linker_loader_cleanup(tables->linker);
- g_free(linker_data);
- g_array_free(tables->rsdp, true);
- g_array_free(tables->table_data, true);
- g_array_free(tables->tcpalog, mfre);
-}
-
-typedef
struct AcpiBuildState {
/* Copy of table in RAM (for patching). */
ram_addr_t table_ram;
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 17d3beb..1705001 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -4,6 +4,18 @@
#include <stdint.h>
#include <glib.h>
#include "qemu/compiler.h"
+#include "hw/acpi/acpi-defs.h"
+
+/* Reserve RAM space for tables: add another order of magnitude. */
+#define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
+
+#define ACPI_BUILD_APPNAME "Bochs"
+#define ACPI_BUILD_APPNAME6 "BOCHS "
+#define ACPI_BUILD_APPNAME4 "BXPC"
+
+#define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
+#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
+#define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
typedef enum {
AML_NO_OPCODE = 0,/* has only data */
@@ -93,6 +105,14 @@ typedef enum {
aml_ReadWrite = 1,
} AmlReadAndWrite;
+typedef
+struct AcpiBuildTables {
+ GArray *table_data;
+ GArray *rsdp;
+ GArray *tcpalog;
+ GArray *linker;
+} AcpiBuildTables;
+
/**
* init_aml_allocator:
*
@@ -188,4 +208,13 @@ Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
Aml *aml_varpackage(uint32_t num_elements);
+void
+build_header(GArray *linker, GArray *table_data,
+ AcpiTableHeader *h, const char *sig, int len, uint8_t rev);
+void *acpi_data_push(GArray *table_data, unsigned size);
+unsigned acpi_data_len(GArray *table);
+void acpi_add_table(GArray *table_offsets, GArray *table_data);
+void acpi_build_tables_init(AcpiBuildTables *tables);
+void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre);
+
#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* [Qemu-devel] [PATCH v4 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 01/20] hw/i386: Move ACPI header definitions in an arch-independent location Shannon Zhao
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 02/20] hw/i386/acpi-build: move generic acpi building helpers into dedictated file Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-08 14:37 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
` (18 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Introduce a preliminary framework in virt-acpi-build.c with the main
ACPI build functions. It exposes the generated ACPI contents to
guest over fw_cfg.
The required ACPI v5.1 tables for ARM are:
- RSDP: Initial table that points to XSDT
- RSDT: Points to FADT GTDT MADT tables
- FADT: Generic information about the machine
- GTDT: Generic timer description table
- MADT: Multiple APIC description table
- DSDT: Holds all information about system devices/peripherals, pointed by FADT
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/Makefile.objs | 1 +
hw/arm/virt-acpi-build.c | 198 +++++++++++++++++++++++++++++++++++++++
include/hw/arm/virt-acpi-build.h | 65 +++++++++++++
3 files changed, 264 insertions(+)
create mode 100644 hw/arm/virt-acpi-build.c
create mode 100644 include/hw/arm/virt-acpi-build.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2577f68..a1bfb19 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
+obj-$(CONFIG_ACPI) += virt-acpi-build.o
obj-y += netduino2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
new file mode 100644
index 0000000..388838a
--- /dev/null
+++ b/hw/arm/virt-acpi-build.c
@@ -0,0 +1,198 @@
+/* Support for generating ACPI tables and passing them to Guests
+ *
+ * ARM virt ACPI generation
+ *
+ * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ *
+ * Author: Shannon Zhao <zhaoshenglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/arm/virt-acpi-build.h"
+#include <stddef.h>
+#include <glib.h>
+#include "qemu-common.h"
+#include "qemu/bitmap.h"
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "qemu/error-report.h"
+#include "qom/cpu.h"
+#include "target-arm/cpu.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/nvram/fw_cfg.h"
+#include "hw/acpi/bios-linker-loader.h"
+#include "hw/loader.h"
+#include "hw/hw.h"
+
+#include "hw/acpi/aml-build.h"
+
+#include "qapi/qmp/qint.h"
+#include "qom/qom-qobject.h"
+#include "exec/ram_addr.h"
+
+/* #define DEBUG_ACPI_BUILD */
+#ifdef DEBUG_ACPI_BUILD
+#define ACPI_BUILD_DPRINTF(fmt, ...) \
+ do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
+#else
+#define ACPI_BUILD_DPRINTF(fmt, ...)
+#endif
+
+typedef
+struct AcpiBuildState {
+ /* Copy of table in RAM (for patching). */
+ ram_addr_t table_ram;
+ ram_addr_t rsdp_ram;
+ ram_addr_t linker_ram;
+ /* Is table patched? */
+ uint8_t patched;
+ VirtGuestInfo *guest_info;
+} AcpiBuildState;
+
+static
+void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
+{
+ GArray *table_offsets;
+
+ table_offsets = g_array_new(false, true /* clear */,
+ sizeof(uint32_t));
+
+ bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
+ 64, false /* high memory */);
+
+ /*
+ * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
+ * RSDP
+ * RSDT
+ * FADT
+ * GTDT
+ * MADT
+ * DSDT
+ */
+
+ /* Cleanup memory that's no longer used. */
+ g_array_free(table_offsets, true);
+}
+
+static void acpi_ram_update(ram_addr_t ram, GArray *data)
+{
+ uint32_t size = acpi_data_len(data);
+
+ /* Make sure RAM size is correct - in case it got changed
+ * e.g. by migration */
+ qemu_ram_resize(ram, size, &error_abort);
+
+ memcpy(qemu_get_ram_ptr(ram), data->data, size);
+ cpu_physical_memory_set_dirty_range_nocode(ram, size);
+}
+
+static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
+{
+ AcpiBuildState *build_state = build_opaque;
+ AcpiBuildTables tables;
+
+ /* No state to update or already patched? Nothing to do. */
+ if (!build_state || build_state->patched) {
+ return;
+ }
+ build_state->patched = 1;
+
+ acpi_build_tables_init(&tables);
+
+ virt_acpi_build(build_state->guest_info, &tables);
+
+ acpi_ram_update(build_state->table_ram, tables.table_data);
+ acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
+ acpi_ram_update(build_state->linker_ram, tables.linker);
+
+
+ acpi_build_tables_cleanup(&tables, true);
+}
+
+static void virt_acpi_build_reset(void *build_opaque)
+{
+ AcpiBuildState *build_state = build_opaque;
+ build_state->patched = 0;
+}
+
+static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
+ const char *name, uint64_t max_size)
+{
+ return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
+ name, virt_acpi_build_update, build_state);
+}
+
+static const VMStateDescription vmstate_virt_acpi_build = {
+ .name = "virt_acpi_build",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(patched, AcpiBuildState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+void virt_acpi_setup(VirtGuestInfo *guest_info)
+{
+ AcpiBuildTables tables;
+ AcpiBuildState *build_state;
+
+ if (!guest_info->fw_cfg) {
+ ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
+ return;
+ }
+
+ if (!acpi_enabled) {
+ ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
+ return;
+ }
+
+ build_state = g_malloc0(sizeof *build_state);
+ build_state->guest_info = guest_info;
+
+ acpi_build_tables_init(&tables);
+ virt_acpi_build(build_state->guest_info, &tables);
+
+ /* Now expose it all to Guest */
+ build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
+ ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_MAX_SIZE);
+ assert(build_state->table_ram != RAM_ADDR_MAX);
+
+ build_state->linker_ram =
+ acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
+
+ fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
+ tables.tcpalog->data, acpi_data_len(tables.tcpalog));
+
+ build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
+ ACPI_BUILD_RSDP_FILE, 0);
+
+ qemu_register_reset(virt_acpi_build_reset, build_state);
+ virt_acpi_build_reset(build_state);
+ vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
+
+ /* Cleanup tables but don't free the memory: we track it
+ * in build_state.
+ */
+ acpi_build_tables_cleanup(&tables, false);
+}
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
new file mode 100644
index 0000000..175eac2
--- /dev/null
+++ b/include/hw/arm/virt-acpi-build.h
@@ -0,0 +1,65 @@
+/*
+ *
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ *
+ * Author: Shannon Zhao <zhaoshenglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_VIRT_ACPI_BUILD_H
+#define QEMU_VIRT_ACPI_BUILD_H
+
+#include "qemu-common.h"
+
+typedef struct acpi_gtdt_info {
+ uint32_t timer_virt;
+ uint32_t timer_s_el1;
+ uint32_t timer_ns_el1;
+ uint32_t timer_ns_el2;
+} acpi_gtdt_info;
+
+typedef struct acpi_madt_info {
+ const hwaddr *gic_cpu_base_addr;
+ const hwaddr *gic_dist_base_addr;
+} acpi_madt_info;
+
+typedef struct acpi_dsdt_info {
+ const hwaddr *uart_addr;
+ const int *uart_irq;
+ const hwaddr *virtio_mmio_addr;
+ const int *virtio_mmio_irq;
+ int virtio_mmio_num;
+ const hwaddr *rtc_addr;
+ const int *rtc_irq;
+ const hwaddr *flash_addr;
+} acpi_dsdt_info;
+
+typedef struct VirtGuestInfo {
+ int smp_cpus;
+ int max_cpus;
+ FWCfgState *fw_cfg;
+ acpi_madt_info *madt_info;
+ acpi_dsdt_info *dsdt_info;
+ acpi_gtdt_info *gtdt_info;
+} VirtGuestInfo;
+
+
+typedef struct VirtGuestInfoState {
+ VirtGuestInfo info;
+ Notifier machine_done;
+} VirtGuestInfoState;
+
+void virt_acpi_setup(VirtGuestInfo *guest_info);
+
+#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
@ 2015-04-08 14:37 ` Alex Bennée
2015-04-09 5:43 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Alex Bennée @ 2015-04-08 14:37 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Introduce a preliminary framework in virt-acpi-build.c with the main
> ACPI build functions. It exposes the generated ACPI contents to
> guest over fw_cfg.
>
> The required ACPI v5.1 tables for ARM are:
> - RSDP: Initial table that points to XSDT
> - RSDT: Points to FADT GTDT MADT tables
> - FADT: Generic information about the machine
> - GTDT: Generic timer description table
> - MADT: Multiple APIC description table
> - DSDT: Holds all information about system devices/peripherals, pointed by FADT
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/Makefile.objs | 1 +
> hw/arm/virt-acpi-build.c | 198 +++++++++++++++++++++++++++++++++++++++
> include/hw/arm/virt-acpi-build.h | 65 +++++++++++++
> 3 files changed, 264 insertions(+)
> create mode 100644 hw/arm/virt-acpi-build.c
> create mode 100644 include/hw/arm/virt-acpi-build.h
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 2577f68..a1bfb19 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
> obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
> obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> +obj-$(CONFIG_ACPI) += virt-acpi-build.o
> obj-y += netduino2.o
>
> obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> new file mode 100644
> index 0000000..388838a
> --- /dev/null
> +++ b/hw/arm/virt-acpi-build.c
> @@ -0,0 +1,198 @@
> +/* Support for generating ACPI tables and passing them to Guests
> + *
> + * ARM virt ACPI generation
> + *
> + * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
> + * Copyright (C) 2006 Fabrice Bellard
> + * Copyright (C) 2013 Red Hat Inc
> + *
> + * Author: Michael S. Tsirkin <mst@redhat.com>
> + *
> + * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
> + *
> + * Author: Shannon Zhao <zhaoshenglong@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/arm/virt-acpi-build.h"
> +#include <stddef.h>
> +#include <glib.h>
> +#include "qemu-common.h"
> +#include "qemu/bitmap.h"
> +#include "qemu/osdep.h"
> +#include "qemu/range.h"
> +#include "qemu/error-report.h"
> +#include "qom/cpu.h"
> +#include "target-arm/cpu.h"
> +#include "hw/acpi/acpi-defs.h"
> +#include "hw/acpi/acpi.h"
> +#include "hw/nvram/fw_cfg.h"
> +#include "hw/acpi/bios-linker-loader.h"
> +#include "hw/loader.h"
> +#include "hw/hw.h"
> +
> +#include "hw/acpi/aml-build.h"
> +
> +#include "qapi/qmp/qint.h"
> +#include "qom/qom-qobject.h"
> +#include "exec/ram_addr.h"
> +
> +/* #define DEBUG_ACPI_BUILD */
> +#ifdef DEBUG_ACPI_BUILD
> +#define ACPI_BUILD_DPRINTF(fmt, ...) \
> + do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
> +#else
> +#define ACPI_BUILD_DPRINTF(fmt, ...)
> +#endif
I'd be tempted to rename this to D or at a push VIRT_ACPI_DEBUG just to
make it distinct from where it was copied from.
You could also consider something like:
printf("%s: " fmt, __func__, ##__VA_ARGS__);
So log statements are pre-pended with their source functions.
> +
> +typedef
> +struct AcpiBuildState {
> + /* Copy of table in RAM (for patching). */
> + ram_addr_t table_ram;
> + ram_addr_t rsdp_ram;
> + ram_addr_t linker_ram;
> + /* Is table patched? */
> + uint8_t patched;
> + VirtGuestInfo *guest_info;
> +} AcpiBuildState;
> +
> +static
> +void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> +{
> + GArray *table_offsets;
> +
> + table_offsets = g_array_new(false, true /* clear */,
> + sizeof(uint32_t));
> +
> + bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
> + 64, false /* high memory */);
> +
> + /*
> + * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
> + * RSDP
> + * RSDT
> + * FADT
> + * GTDT
> + * MADT
> + * DSDT
> + */
> +
> + /* Cleanup memory that's no longer used. */
> + g_array_free(table_offsets, true);
> +}
> +
> +static void acpi_ram_update(ram_addr_t ram, GArray *data)
> +{
> + uint32_t size = acpi_data_len(data);
> +
> + /* Make sure RAM size is correct - in case it got changed
> + * e.g. by migration */
> + qemu_ram_resize(ram, size, &error_abort);
> +
> + memcpy(qemu_get_ram_ptr(ram), data->data, size);
> + cpu_physical_memory_set_dirty_range_nocode(ram, size);
> +}
> +
> +static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
> +{
> + AcpiBuildState *build_state = build_opaque;
> + AcpiBuildTables tables;
> +
> + /* No state to update or already patched? Nothing to do. */
> + if (!build_state || build_state->patched) {
> + return;
> + }
> + build_state->patched = 1;
> +
> + acpi_build_tables_init(&tables);
> +
> + virt_acpi_build(build_state->guest_info, &tables);
> +
> + acpi_ram_update(build_state->table_ram, tables.table_data);
> + acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
> + acpi_ram_update(build_state->linker_ram, tables.linker);
> +
> +
> + acpi_build_tables_cleanup(&tables, true);
> +}
> +
> +static void virt_acpi_build_reset(void *build_opaque)
> +{
> + AcpiBuildState *build_state = build_opaque;
> + build_state->patched = 0;
> +}
> +
> +static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
> + const char *name, uint64_t max_size)
> +{
> + return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
> + name, virt_acpi_build_update, build_state);
> +}
> +
> +static const VMStateDescription vmstate_virt_acpi_build = {
> + .name = "virt_acpi_build",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8(patched, AcpiBuildState),
> + VMSTATE_END_OF_LIST()
> + },
> +};
> +
> +void virt_acpi_setup(VirtGuestInfo *guest_info)
> +{
> + AcpiBuildTables tables;
> + AcpiBuildState *build_state;
> +
> + if (!guest_info->fw_cfg) {
> + ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
> + return;
> + }
> +
> + if (!acpi_enabled) {
> + ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
> + return;
> + }
Are these debug errors or something that should be error_report() to the user?
> +
> + build_state = g_malloc0(sizeof *build_state);
> + build_state->guest_info = guest_info;
> +
> + acpi_build_tables_init(&tables);
> + virt_acpi_build(build_state->guest_info, &tables);
> +
> + /* Now expose it all to Guest */
> + build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
> + ACPI_BUILD_TABLE_FILE,
> + ACPI_BUILD_TABLE_MAX_SIZE);
> + assert(build_state->table_ram != RAM_ADDR_MAX);
> +
> + build_state->linker_ram =
> + acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
> +
> + fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
> + tables.tcpalog->data, acpi_data_len(tables.tcpalog));
> +
> + build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
> + ACPI_BUILD_RSDP_FILE, 0);
> +
> + qemu_register_reset(virt_acpi_build_reset, build_state);
> + virt_acpi_build_reset(build_state);
> + vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
> +
> + /* Cleanup tables but don't free the memory: we track it
> + * in build_state.
> + */
> + acpi_build_tables_cleanup(&tables, false);
I'm confused here but I see it comes from the i386 code. What do we need
to keep track of after we've built the tables up?
> +}
> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
> new file mode 100644
> index 0000000..175eac2
> --- /dev/null
> +++ b/include/hw/arm/virt-acpi-build.h
> @@ -0,0 +1,65 @@
> +/*
> + *
> + * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
> + *
> + * Author: Shannon Zhao <zhaoshenglong@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef QEMU_VIRT_ACPI_BUILD_H
> +#define QEMU_VIRT_ACPI_BUILD_H
> +
> +#include "qemu-common.h"
> +
> +typedef struct acpi_gtdt_info {
> + uint32_t timer_virt;
> + uint32_t timer_s_el1;
> + uint32_t timer_ns_el1;
> + uint32_t timer_ns_el2;
> +} acpi_gtdt_info;
> +
> +typedef struct acpi_madt_info {
> + const hwaddr *gic_cpu_base_addr;
> + const hwaddr *gic_dist_base_addr;
> +} acpi_madt_info;
> +
> +typedef struct acpi_dsdt_info {
> + const hwaddr *uart_addr;
> + const int *uart_irq;
> + const hwaddr *virtio_mmio_addr;
> + const int *virtio_mmio_irq;
> + int virtio_mmio_num;
> + const hwaddr *rtc_addr;
> + const int *rtc_irq;
> + const hwaddr *flash_addr;
> +} acpi_dsdt_info;
> +
> +typedef struct VirtGuestInfo {
> + int smp_cpus;
> + int max_cpus;
> + FWCfgState *fw_cfg;
> + acpi_madt_info *madt_info;
> + acpi_dsdt_info *dsdt_info;
> + acpi_gtdt_info *gtdt_info;
> +} VirtGuestInfo;
> +
> +
> +typedef struct VirtGuestInfoState {
> + VirtGuestInfo info;
> + Notifier machine_done;
> +} VirtGuestInfoState;
> +
> +void virt_acpi_setup(VirtGuestInfo *guest_info);
> +
> +#endif
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM
2015-04-08 14:37 ` Alex Bennée
@ 2015-04-09 5:43 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-09 5:43 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/8 22:37, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Introduce a preliminary framework in virt-acpi-build.c with the main
>> ACPI build functions. It exposes the generated ACPI contents to
>> guest over fw_cfg.
>>
>> The required ACPI v5.1 tables for ARM are:
>> - RSDP: Initial table that points to XSDT
>> - RSDT: Points to FADT GTDT MADT tables
>> - FADT: Generic information about the machine
>> - GTDT: Generic timer description table
>> - MADT: Multiple APIC description table
>> - DSDT: Holds all information about system devices/peripherals, pointed by FADT
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/Makefile.objs | 1 +
>> hw/arm/virt-acpi-build.c | 198 +++++++++++++++++++++++++++++++++++++++
>> include/hw/arm/virt-acpi-build.h | 65 +++++++++++++
>> 3 files changed, 264 insertions(+)
>> create mode 100644 hw/arm/virt-acpi-build.c
>> create mode 100644 include/hw/arm/virt-acpi-build.h
>>
>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> index 2577f68..a1bfb19 100644
>> --- a/hw/arm/Makefile.objs
>> +++ b/hw/arm/Makefile.objs
>> @@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
>> obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
>> obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
>> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>> +obj-$(CONFIG_ACPI) += virt-acpi-build.o
>> obj-y += netduino2.o
>>
>> obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> new file mode 100644
>> index 0000000..388838a
>> --- /dev/null
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -0,0 +1,198 @@
>> +/* Support for generating ACPI tables and passing them to Guests
>> + *
>> + * ARM virt ACPI generation
>> + *
>> + * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
>> + * Copyright (C) 2006 Fabrice Bellard
>> + * Copyright (C) 2013 Red Hat Inc
>> + *
>> + * Author: Michael S. Tsirkin <mst@redhat.com>
>> + *
>> + * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
>> + *
>> + * Author: Shannon Zhao <zhaoshenglong@huawei.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> +
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> +
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "hw/arm/virt-acpi-build.h"
>> +#include <stddef.h>
>> +#include <glib.h>
>> +#include "qemu-common.h"
>> +#include "qemu/bitmap.h"
>> +#include "qemu/osdep.h"
>> +#include "qemu/range.h"
>> +#include "qemu/error-report.h"
>> +#include "qom/cpu.h"
>> +#include "target-arm/cpu.h"
>> +#include "hw/acpi/acpi-defs.h"
>> +#include "hw/acpi/acpi.h"
>> +#include "hw/nvram/fw_cfg.h"
>> +#include "hw/acpi/bios-linker-loader.h"
>> +#include "hw/loader.h"
>> +#include "hw/hw.h"
>> +
>> +#include "hw/acpi/aml-build.h"
>> +
>> +#include "qapi/qmp/qint.h"
>> +#include "qom/qom-qobject.h"
>> +#include "exec/ram_addr.h"
>> +
>> +/* #define DEBUG_ACPI_BUILD */
>> +#ifdef DEBUG_ACPI_BUILD
>> +#define ACPI_BUILD_DPRINTF(fmt, ...) \
>> + do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
>> +#else
>> +#define ACPI_BUILD_DPRINTF(fmt, ...)
>> +#endif
>
> I'd be tempted to rename this to D or at a push VIRT_ACPI_DEBUG just to
> make it distinct from where it was copied from.
>
> You could also consider something like:
>
> printf("%s: " fmt, __func__, ##__VA_ARGS__);
>
> So log statements are pre-pended with their source functions.
>
Thanks, will fix it.
>> +
>> +typedef
>> +struct AcpiBuildState {
>> + /* Copy of table in RAM (for patching). */
>> + ram_addr_t table_ram;
>> + ram_addr_t rsdp_ram;
>> + ram_addr_t linker_ram;
>> + /* Is table patched? */
>> + uint8_t patched;
>> + VirtGuestInfo *guest_info;
>> +} AcpiBuildState;
>> +
>> +static
>> +void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> +{
>> + GArray *table_offsets;
>> +
>> + table_offsets = g_array_new(false, true /* clear */,
>> + sizeof(uint32_t));
>> +
>> + bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
>> + 64, false /* high memory */);
>> +
>> + /*
>> + * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
>> + * RSDP
>> + * RSDT
>> + * FADT
>> + * GTDT
>> + * MADT
>> + * DSDT
>> + */
>> +
>> + /* Cleanup memory that's no longer used. */
>> + g_array_free(table_offsets, true);
>> +}
>> +
>> +static void acpi_ram_update(ram_addr_t ram, GArray *data)
>> +{
>> + uint32_t size = acpi_data_len(data);
>> +
>> + /* Make sure RAM size is correct - in case it got changed
>> + * e.g. by migration */
>> + qemu_ram_resize(ram, size, &error_abort);
>> +
>> + memcpy(qemu_get_ram_ptr(ram), data->data, size);
>> + cpu_physical_memory_set_dirty_range_nocode(ram, size);
>> +}
>> +
>> +static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
>> +{
>> + AcpiBuildState *build_state = build_opaque;
>> + AcpiBuildTables tables;
>> +
>> + /* No state to update or already patched? Nothing to do. */
>> + if (!build_state || build_state->patched) {
>> + return;
>> + }
>> + build_state->patched = 1;
>> +
>> + acpi_build_tables_init(&tables);
>> +
>> + virt_acpi_build(build_state->guest_info, &tables);
>> +
>> + acpi_ram_update(build_state->table_ram, tables.table_data);
>> + acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
>> + acpi_ram_update(build_state->linker_ram, tables.linker);
>> +
>> +
>> + acpi_build_tables_cleanup(&tables, true);
>> +}
>> +
>> +static void virt_acpi_build_reset(void *build_opaque)
>> +{
>> + AcpiBuildState *build_state = build_opaque;
>> + build_state->patched = 0;
>> +}
>> +
>> +static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
>> + const char *name, uint64_t max_size)
>> +{
>> + return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
>> + name, virt_acpi_build_update, build_state);
>> +}
>> +
>> +static const VMStateDescription vmstate_virt_acpi_build = {
>> + .name = "virt_acpi_build",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT8(patched, AcpiBuildState),
>> + VMSTATE_END_OF_LIST()
>> + },
>> +};
>> +
>> +void virt_acpi_setup(VirtGuestInfo *guest_info)
>> +{
>> + AcpiBuildTables tables;
>> + AcpiBuildState *build_state;
>> +
>> + if (!guest_info->fw_cfg) {
>> + ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
>> + return;
>> + }
>> +
>> + if (!acpi_enabled) {
>> + ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
>> + return;
>> + }
>
> Are these debug errors or something that should be error_report() to the user?
>
This is not an error. It works when user appends "-no-acpi" option to qemu command line.
I should add this option support on ARM in the qemu-options.hx. Will add at next version.
diff --git a/qemu-options.hx b/qemu-options.hx
index 319d971..82bcc9b 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1352,7 +1352,7 @@ be needed to boot from old floppy disks.
ETEXI
DEF("no-acpi", 0, QEMU_OPTION_no_acpi,
- "-no-acpi disable ACPI\n", QEMU_ARCH_I386)
+ "-no-acpi disable ACPI\n", QEMU_ARCH_I386 | QEMU_ARCH_ARM)
STEXI
@item -no-acpi
@findex -no-acpi
>> +
>> + build_state = g_malloc0(sizeof *build_state);
>> + build_state->guest_info = guest_info;
>> +
>> + acpi_build_tables_init(&tables);
>> + virt_acpi_build(build_state->guest_info, &tables);
>> +
>> + /* Now expose it all to Guest */
>> + build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
>> + ACPI_BUILD_TABLE_FILE,
>> + ACPI_BUILD_TABLE_MAX_SIZE);
>> + assert(build_state->table_ram != RAM_ADDR_MAX);
>> +
>> + build_state->linker_ram =
>> + acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
>> +
>> + fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
>> + tables.tcpalog->data, acpi_data_len(tables.tcpalog));
>> +
>> + build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
>> + ACPI_BUILD_RSDP_FILE, 0);
>> +
>> + qemu_register_reset(virt_acpi_build_reset, build_state);
>> + virt_acpi_build_reset(build_state);
>> + vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
>> +
>> + /* Cleanup tables but don't free the memory: we track it
>> + * in build_state.
>> + */
>> + acpi_build_tables_cleanup(&tables, false);
>
> I'm confused here but I see it comes from the i386 code. What do we need
> to keep track of after we've built the tables up?
>
We track it for updating tables.
>> +}
>> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
>> new file mode 100644
>> index 0000000..175eac2
>> --- /dev/null
>> +++ b/include/hw/arm/virt-acpi-build.h
>> @@ -0,0 +1,65 @@
>> +/*
>> + *
>> + * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
>> + *
>> + * Author: Shannon Zhao <zhaoshenglong@huawei.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef QEMU_VIRT_ACPI_BUILD_H
>> +#define QEMU_VIRT_ACPI_BUILD_H
>> +
>> +#include "qemu-common.h"
>> +
>> +typedef struct acpi_gtdt_info {
>> + uint32_t timer_virt;
>> + uint32_t timer_s_el1;
>> + uint32_t timer_ns_el1;
>> + uint32_t timer_ns_el2;
>> +} acpi_gtdt_info;
>> +
>> +typedef struct acpi_madt_info {
>> + const hwaddr *gic_cpu_base_addr;
>> + const hwaddr *gic_dist_base_addr;
>> +} acpi_madt_info;
>> +
>> +typedef struct acpi_dsdt_info {
>> + const hwaddr *uart_addr;
>> + const int *uart_irq;
>> + const hwaddr *virtio_mmio_addr;
>> + const int *virtio_mmio_irq;
>> + int virtio_mmio_num;
>> + const hwaddr *rtc_addr;
>> + const int *rtc_irq;
>> + const hwaddr *flash_addr;
>> +} acpi_dsdt_info;
>> +
>> +typedef struct VirtGuestInfo {
>> + int smp_cpus;
>> + int max_cpus;
>> + FWCfgState *fw_cfg;
>> + acpi_madt_info *madt_info;
>> + acpi_dsdt_info *dsdt_info;
>> + acpi_gtdt_info *gtdt_info;
>> +} VirtGuestInfo;
>> +
>> +
>> +typedef struct VirtGuestInfoState {
>> + VirtGuestInfo info;
>> + Notifier machine_done;
>> +} VirtGuestInfoState;
>> +
>> +void virt_acpi_setup(VirtGuestInfo *guest_info);
>> +
>> +#endif
>
^ permalink raw reply related [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (2 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 03/20] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-08 14:54 ` Alex Bennée
2015-04-09 12:42 ` Igor Mammedov
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
` (17 subsequent siblings)
21 siblings, 2 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_memory32_fixed() for describing device mmio region in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 22 ++++++++++++++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 8d01959..fefe7c7 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
return var;
}
+/*
+ * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
+ */
+Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */
+ build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */
+ build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */
+ build_append_byte(var->buf, rw_flag); /* Write status, 1 rw 0 ro */
+ build_append_byte(var->buf, addr & 0xff); /* Range base address bits[7:0] */
+ build_append_byte(var->buf, (addr >> 8) & 0xff); /* Range base address bits[15:8] */
+ build_append_byte(var->buf, (addr >> 16) & 0xff); /* Range base address bits[23:16] */
+ build_append_byte(var->buf, (addr >> 24) & 0xff); /* Range base address bits[31:24] */
+
+ build_append_byte(var->buf, size & 0xff); /* Range length bits[7:0] */
+ build_append_byte(var->buf, (size >> 8) & 0xff); /* Range length bits[15:8] */
+ build_append_byte(var->buf, (size >> 16) & 0xff); /* Range length bits[23:16] */
+ build_append_byte(var->buf, (size >> 24) & 0xff); /* Range length bits[31:24] */
+ return var;
+}
+
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 1705001..baa0652 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -162,6 +162,7 @@ Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
+Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
@ 2015-04-08 14:54 ` Alex Bennée
2015-04-08 18:42 ` Michael S. Tsirkin
2015-04-09 5:46 ` Shannon Zhao
2015-04-09 12:42 ` Igor Mammedov
1 sibling, 2 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-08 14:54 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add aml_memory32_fixed() for describing device mmio region in resource template.
> These can be used to generating DSDT table for ACPI on ARM.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 22 ++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 23 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 8d01959..fefe7c7 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
> return var;
> }
>
> +/*
> + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
> + */
> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
> +{
> + Aml *var = aml_alloc();
This is more aimed at the ACPI maintainers but I wonder if there should
be an aml_alloc_sized that pre-allocates the GArray? Otherwise we spend
a lot of time realloc'ing while building these entries up. Or even a
varidac build_append_bytes?
> + build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */
> + build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */
> + build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */
> + build_append_byte(var->buf, rw_flag); /* Write status, 1 rw 0 ro */
> + build_append_byte(var->buf, addr & 0xff); /* Range base address bits[7:0] */
> + build_append_byte(var->buf, (addr >> 8) & 0xff); /* Range base address bits[15:8] */
> + build_append_byte(var->buf, (addr >> 16) & 0xff); /* Range base address bits[23:16] */
> + build_append_byte(var->buf, (addr >> 24) & 0xff); /* Range base
> address bits[31:24] */
I'm should point out we have handy utility functions for bit fiddling:
build_append_byte(var->buf, extract64(addr, 8, 8)); /* Range base address bits[15:8] */
> +
> + build_append_byte(var->buf, size & 0xff); /* Range length bits[7:0] */
> + build_append_byte(var->buf, (size >> 8) & 0xff); /* Range length bits[15:8] */
> + build_append_byte(var->buf, (size >> 16) & 0xff); /* Range length bits[23:16] */
> + build_append_byte(var->buf, (size >> 24) & 0xff); /* Range length
> bits[31:24] */
Hmm we seem to have two 64 bit inputs which we only use 32 bits worth
of. Maybe the prototype should be fixed to avoid accidents of accidentally
passing in 64 bit values.
> + return var;
> +}
> +
> /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> uint8_t aln, uint8_t len)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 1705001..baa0652 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -162,6 +162,7 @@ Aml *aml_call1(const char *method, Aml *arg1);
> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
> Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> uint8_t aln, uint8_t len);
> Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-08 14:54 ` Alex Bennée
@ 2015-04-08 18:42 ` Michael S. Tsirkin
2015-04-09 9:27 ` Alex Bennée
2015-04-09 5:46 ` Shannon Zhao
1 sibling, 1 reply; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-08 18:42 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, imammedo, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Wed, Apr 08, 2015 at 03:54:45PM +0100, Alex Bennée wrote:
> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > index 8d01959..fefe7c7 100644
> > --- a/hw/acpi/aml-build.c
> > +++ b/hw/acpi/aml-build.c
> > @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
> > return var;
> > }
> >
> > +/*
> > + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
> > + */
> > +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
> > +{
> > + Aml *var = aml_alloc();
>
> This is more aimed at the ACPI maintainers but I wonder if there should
> be an aml_alloc_sized that pre-allocates the GArray? Otherwise we spend
> a lot of time realloc'ing while building these entries up. Or even a
> varidac build_append_bytes?
Can you show measureable VM boot speedup from this?
If not, it's not worth bothering with.
--
MST
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-08 18:42 ` Michael S. Tsirkin
@ 2015-04-09 9:27 ` Alex Bennée
0 siblings, 0 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 9:27 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, hangaohuai, imammedo, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
Michael S. Tsirkin <mst@redhat.com> writes:
> On Wed, Apr 08, 2015 at 03:54:45PM +0100, Alex Bennée wrote:
>> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> > index 8d01959..fefe7c7 100644
>> > --- a/hw/acpi/aml-build.c
>> > +++ b/hw/acpi/aml-build.c
>> > @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
>> > return var;
>> > }
>> >
>> > +/*
>> > + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
>> > + */
>> > +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
>> > +{
>> > + Aml *var = aml_alloc();
>>
>> This is more aimed at the ACPI maintainers but I wonder if there should
>> be an aml_alloc_sized that pre-allocates the GArray? Otherwise we spend
>> a lot of time realloc'ing while building these entries up. Or even a
>> varidac build_append_bytes?
>
> Can you show measureable VM boot speedup from this?
> If not, it's not worth bothering with.
Fair enough, this is a start-up thing and I guess you could probably
only measure a difference in a highly targeted pathaological test case.
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-08 14:54 ` Alex Bennée
2015-04-08 18:42 ` Michael S. Tsirkin
@ 2015-04-09 5:46 ` Shannon Zhao
1 sibling, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-09 5:46 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/8 22:54, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Add aml_memory32_fixed() for describing device mmio region in resource template.
>> These can be used to generating DSDT table for ACPI on ARM.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/acpi/aml-build.c | 22 ++++++++++++++++++++++
>> include/hw/acpi/aml-build.h | 1 +
>> 2 files changed, 23 insertions(+)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 8d01959..fefe7c7 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
>> return var;
>> }
>>
>> +/*
>> + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
>> + */
>> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
>> +{
>> + Aml *var = aml_alloc();
>
> This is more aimed at the ACPI maintainers but I wonder if there should
> be an aml_alloc_sized that pre-allocates the GArray? Otherwise we spend
> a lot of time realloc'ing while building these entries up. Or even a
> varidac build_append_bytes?
>
>> + build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */
>> + build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */
>> + build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */
>> + build_append_byte(var->buf, rw_flag); /* Write status, 1 rw 0 ro */
>> + build_append_byte(var->buf, addr & 0xff); /* Range base address bits[7:0] */
>> + build_append_byte(var->buf, (addr >> 8) & 0xff); /* Range base address bits[15:8] */
>> + build_append_byte(var->buf, (addr >> 16) & 0xff); /* Range base address bits[23:16] */
>> + build_append_byte(var->buf, (addr >> 24) & 0xff); /* Range base
>> address bits[31:24] */
>
> I'm should point out we have handy utility functions for bit fiddling:
>
> build_append_byte(var->buf, extract64(addr, 8, 8)); /* Range base address bits[15:8] */
>
Great, will use these utility functions. Same with the other patch.
>> +
>> + build_append_byte(var->buf, size & 0xff); /* Range length bits[7:0] */
>> + build_append_byte(var->buf, (size >> 8) & 0xff); /* Range length bits[15:8] */
>> + build_append_byte(var->buf, (size >> 16) & 0xff); /* Range length bits[23:16] */
>> + build_append_byte(var->buf, (size >> 24) & 0xff); /* Range length
>> bits[31:24] */
>
> Hmm we seem to have two 64 bit inputs which we only use 32 bits worth
> of. Maybe the prototype should be fixed to avoid accidents of accidentally
> passing in 64 bit values.
>
Thanks, will fix this.
>
>> + return var;
>> +}
>> +
>> /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
>> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
>> uint8_t aln, uint8_t len)
>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>> index 1705001..baa0652 100644
>> --- a/include/hw/acpi/aml-build.h
>> +++ b/include/hw/acpi/aml-build.h
>> @@ -162,6 +162,7 @@ Aml *aml_call1(const char *method, Aml *arg1);
>> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
>> Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
>> Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
>> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
>> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
>> uint8_t aln, uint8_t len);
>> Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
>
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
2015-04-08 14:54 ` Alex Bennée
@ 2015-04-09 12:42 ` Igor Mammedov
2015-04-10 5:49 ` Shannon Zhao
1 sibling, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 12:42 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Fri, 3 Apr 2015 18:03:36 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add aml_memory32_fixed() for describing device mmio region in resource template.
> These can be used to generating DSDT table for ACPI on ARM.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 22 ++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 23 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 8d01959..fefe7c7 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
> return var;
> }
>
> +/*
> + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
> + */
> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
perhaps
s/uint64_t/uint32_t/
don't use uintXX for bitfields if could be helped.
Probably in this case existing AmlReadAndWrite enum should be used.
> +{
> + Aml *var = aml_alloc();
> + build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */
> + build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */
> + build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */
> + build_append_byte(var->buf, rw_flag); /* Write status, 1 rw 0 ro */
> + build_append_byte(var->buf, addr & 0xff); /* Range base address bits[7:0] */
> + build_append_byte(var->buf, (addr >> 8) & 0xff); /* Range base address bits[15:8] */
> + build_append_byte(var->buf, (addr >> 16) & 0xff); /* Range base address bits[23:16] */
> + build_append_byte(var->buf, (addr >> 24) & 0xff); /* Range base address bits[31:24] */
> +
> + build_append_byte(var->buf, size & 0xff); /* Range length bits[7:0] */
> + build_append_byte(var->buf, (size >> 8) & 0xff); /* Range length bits[15:8] */
> + build_append_byte(var->buf, (size >> 16) & 0xff); /* Range length bits[23:16] */
> + build_append_byte(var->buf, (size >> 24) & 0xff); /* Range length bits[31:24] */
> + return var;
> +}
> +
> /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> uint8_t aln, uint8_t len)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 1705001..baa0652 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -162,6 +162,7 @@ Aml *aml_call1(const char *method, Aml *arg1);
> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
> Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> uint8_t aln, uint8_t len);
> Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-04-09 12:42 ` Igor Mammedov
@ 2015-04-10 5:49 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 5:49 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/9 20:42, Igor Mammedov wrote:
> On Fri, 3 Apr 2015 18:03:36 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Add aml_memory32_fixed() for describing device mmio region in resource template.
>> These can be used to generating DSDT table for ACPI on ARM.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/acpi/aml-build.c | 22 ++++++++++++++++++++++
>> include/hw/acpi/aml-build.h | 1 +
>> 2 files changed, 23 insertions(+)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 8d01959..fefe7c7 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
>> return var;
>> }
>>
>> +/*
>> + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
>> + */
>> +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
> perhaps
> s/uint64_t/uint32_t/
>
> don't use uintXX for bitfields if could be helped.
> Probably in this case existing AmlReadAndWrite enum should be used.
>
Ok, will use the enum.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (3 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-08 14:57 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
` (16 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_interrupt() for describing device interrupt in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 18 ++++++++++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index fefe7c7..bd1713c 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -527,6 +527,24 @@ Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
return var;
}
+/*
+ * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro)
+ */
+Aml *aml_interrupt(uint8_t irq_flags, int irq)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
+ build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
+ build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
+ build_append_byte(var->buf, irq_flags); /* Interrupt Vector Information. */
+ build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */
+ build_append_byte(var->buf, irq & 0xff); /* Interrupt Number bits[7:0] */
+ build_append_byte(var->buf, (irq >> 8) & 0xff); /* Interrupt Number bits[15:8] */
+ build_append_byte(var->buf, (irq >> 16) & 0xff); /* Interrupt Number bits[23:16] */
+ build_append_byte(var->buf, (irq >> 24) & 0xff); /* Interrupt Number bits[31:24] */
+ return var;
+}
+
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index baa0652..315c729 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -163,6 +163,7 @@ Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
+Aml *aml_interrupt(uint8_t irq_flags, int irq);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
@ 2015-04-08 14:57 ` Alex Bennée
2015-04-09 6:09 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Alex Bennée @ 2015-04-08 14:57 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add aml_interrupt() for describing device interrupt in resource template.
> These can be used to generating DSDT table for ACPI on ARM.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 18 ++++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 19 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index fefe7c7..bd1713c 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -527,6 +527,24 @@ Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
> return var;
> }
>
> +/*
> + * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro)
> + */
> +Aml *aml_interrupt(uint8_t irq_flags, int irq)
> +{
> + Aml *var = aml_alloc();
> + build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
> + build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
> + build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
> + build_append_byte(var->buf, irq_flags); /* Interrupt Vector
> Information. */
As the spec says [7:4] is RES0 we might want to assert this is the case.
> + build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */
> + build_append_byte(var->buf, irq & 0xff); /* Interrupt Number bits[7:0] */
> + build_append_byte(var->buf, (irq >> 8) & 0xff); /* Interrupt Number bits[15:8] */
> + build_append_byte(var->buf, (irq >> 16) & 0xff); /* Interrupt Number bits[23:16] */
> + build_append_byte(var->buf, (irq >> 24) & 0xff); /* Interrupt
> Number bits[31:24] */
Again extractNN bitops?
> + return var;
> +}
> +
> /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> uint8_t aln, uint8_t len)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index baa0652..315c729 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -163,6 +163,7 @@ Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
> Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
> Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
> +Aml *aml_interrupt(uint8_t irq_flags, int irq);
> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> uint8_t aln, uint8_t len);
> Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term
2015-04-08 14:57 ` Alex Bennée
@ 2015-04-09 6:09 ` Shannon Zhao
2015-04-09 9:54 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-09 6:09 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/8 22:57, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Add aml_interrupt() for describing device interrupt in resource template.
>> These can be used to generating DSDT table for ACPI on ARM.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/acpi/aml-build.c | 18 ++++++++++++++++++
>> include/hw/acpi/aml-build.h | 1 +
>> 2 files changed, 19 insertions(+)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index fefe7c7..bd1713c 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -527,6 +527,24 @@ Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
>> return var;
>> }
>>
>> +/*
>> + * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro)
>> + */
>> +Aml *aml_interrupt(uint8_t irq_flags, int irq)
>> +{
>> + Aml *var = aml_alloc();
>> + build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
>> + build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
>> + build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
>> + build_append_byte(var->buf, irq_flags); /* Interrupt Vector
>> Information. */
>
> As the spec says [7:4] is RES0 we might want to assert this is the case.
>
Yes, we should check although the probability is very small.
But the reserve bits are different in ACPI 5.1.
Bit[7:5] Reserved (must be 0)
Bit[4] Wake Capability, _WKC
>> + build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */
>> + build_append_byte(var->buf, irq & 0xff); /* Interrupt Number bits[7:0] */
>> + build_append_byte(var->buf, (irq >> 8) & 0xff); /* Interrupt Number bits[15:8] */
>> + build_append_byte(var->buf, (irq >> 16) & 0xff); /* Interrupt Number bits[23:16] */
>> + build_append_byte(var->buf, (irq >> 24) & 0xff); /* Interrupt
>> Number bits[31:24] */
>
> Again extractNN bitops?
>
>> + return var;
>> +}
>> +
>> /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
>> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
>> uint8_t aln, uint8_t len)
>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>> index baa0652..315c729 100644
>> --- a/include/hw/acpi/aml-build.h
>> +++ b/include/hw/acpi/aml-build.h
>> @@ -163,6 +163,7 @@ Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
>> Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
>> Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
>> Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
>> +Aml *aml_interrupt(uint8_t irq_flags, int irq);
>> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
>> uint8_t aln, uint8_t len);
>> Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term
2015-04-09 6:09 ` Shannon Zhao
@ 2015-04-09 9:54 ` Igor Mammedov
2015-04-10 5:50 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 9:54 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, lersek, hanjun.guo, msalter, pbonzini,
peter.huangpeng, Alex Bennée, christoffer.dall,
shannon.zhao
On Thu, 9 Apr 2015 14:09:23 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/8 22:57, Alex Bennée wrote:
> >
> > Shannon Zhao <zhaoshenglong@huawei.com> writes:
> >
> >> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>
> >> Add aml_interrupt() for describing device interrupt in resource template.
> >> These can be used to generating DSDT table for ACPI on ARM.
> >>
> >> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> ---
> >> hw/acpi/aml-build.c | 18 ++++++++++++++++++
> >> include/hw/acpi/aml-build.h | 1 +
> >> 2 files changed, 19 insertions(+)
> >>
> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >> index fefe7c7..bd1713c 100644
> >> --- a/hw/acpi/aml-build.c
> >> +++ b/hw/acpi/aml-build.c
> >> @@ -527,6 +527,24 @@ Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
> >> return var;
> >> }
> >>
> >> +/*
> >> + * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro)
> >> + */
> >> +Aml *aml_interrupt(uint8_t irq_flags, int irq)
> >> +{
> >> + Aml *var = aml_alloc();
> >> + build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
> >> + build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
> >> + build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
> >> + build_append_byte(var->buf, irq_flags); /* Interrupt Vector
> >> Information. */
> >
> > As the spec says [7:4] is RES0 we might want to assert this is the case.
> >
>
> Yes, we should check although the probability is very small.
It's revision specific and we don't have infrastructure to check/validate
per revision differences.
I'd split irq_flags from bitmask to a several args, a enum for each implemented
bit to avoid user setting reserved bits.
/* ACPI X.X: ... */
AmlWakeCap {
aml_not_wake_capable = 0,
aml_wake_capable = 1
}
...
> But the reserve bits are different in ACPI 5.1.
>
> Bit[7:5] Reserved (must be 0)
> Bit[4] Wake Capability, _WKC
>
> >> + build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */
> >> + build_append_byte(var->buf, irq & 0xff); /* Interrupt Number bits[7:0] */
> >> + build_append_byte(var->buf, (irq >> 8) & 0xff); /* Interrupt Number bits[15:8] */
> >> + build_append_byte(var->buf, (irq >> 16) & 0xff); /* Interrupt Number bits[23:16] */
> >> + build_append_byte(var->buf, (irq >> 24) & 0xff); /* Interrupt
> >> Number bits[31:24] */
> >
> > Again extractNN bitops?
> >
> >> + return var;
> >> +}
> >> +
> >> /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
> >> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> >> uint8_t aln, uint8_t len)
> >> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> >> index baa0652..315c729 100644
> >> --- a/include/hw/acpi/aml-build.h
> >> +++ b/include/hw/acpi/aml-build.h
> >> @@ -163,6 +163,7 @@ Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> >> Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
> >> Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
> >> Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag);
> >> +Aml *aml_interrupt(uint8_t irq_flags, int irq);
> >> Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
> >> uint8_t aln, uint8_t len);
> >> Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
> >
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term
2015-04-09 9:54 ` Igor Mammedov
@ 2015-04-10 5:50 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 5:50 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, lersek, hanjun.guo, msalter, pbonzini,
peter.huangpeng, Alex Bennée, christoffer.dall,
shannon.zhao
On 2015/4/9 17:54, Igor Mammedov wrote:
> On Thu, 9 Apr 2015 14:09:23 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> > On 2015/4/8 22:57, Alex Bennée wrote:
>>> > >
>>> > > Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>> > >
>>>> > >> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>> > >>
>>>> > >> Add aml_interrupt() for describing device interrupt in resource template.
>>>> > >> These can be used to generating DSDT table for ACPI on ARM.
>>>> > >>
>>>> > >> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>>> > >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>> > >> ---
>>>> > >> hw/acpi/aml-build.c | 18 ++++++++++++++++++
>>>> > >> include/hw/acpi/aml-build.h | 1 +
>>>> > >> 2 files changed, 19 insertions(+)
>>>> > >>
>>>> > >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>>>> > >> index fefe7c7..bd1713c 100644
>>>> > >> --- a/hw/acpi/aml-build.c
>>>> > >> +++ b/hw/acpi/aml-build.c
>>>> > >> @@ -527,6 +527,24 @@ Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag)
>>>> > >> return var;
>>>> > >> }
>>>> > >>
>>>> > >> +/*
>>>> > >> + * ACPI 1.0: 6.4.3.6 Interrupt (Interrupt Resource Descriptor Macro)
>>>> > >> + */
>>>> > >> +Aml *aml_interrupt(uint8_t irq_flags, int irq)
>>>> > >> +{
>>>> > >> + Aml *var = aml_alloc();
>>>> > >> + build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
>>>> > >> + build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
>>>> > >> + build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
>>>> > >> + build_append_byte(var->buf, irq_flags); /* Interrupt Vector
>>>> > >> Information. */
>>> > >
>>> > > As the spec says [7:4] is RES0 we might want to assert this is the case.
>>> > >
>> >
>> > Yes, we should check although the probability is very small.
> It's revision specific and we don't have infrastructure to check/validate
> per revision differences.
>
> I'd split irq_flags from bitmask to a several args, a enum for each implemented
> bit to avoid user setting reserved bits.
>
> /* ACPI X.X: ... */
> AmlWakeCap {
> aml_not_wake_capable = 0,
> aml_wake_capable = 1
> }
>
> ...
>
Thanks, will try this way.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (4 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 05/20] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 9:51 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
` (15 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
DSDT consists of the usual common table header plus a definition
block in AML encoding which describes all devices in the platform.
After initializing DSDT with header information the namespace is
created which is followed by the device encodings. The devices are
described using the Resource Template for the 32-Bit Fixed Memory
Range and the Extended Interrupt Descriptors.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 388838a..516c1d0 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -57,6 +57,139 @@
#define ACPI_BUILD_DPRINTF(fmt, ...)
#endif
+static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
+{
+ Aml *dev, *crs;
+ int i;
+ char name[5];
+ for (i = 0; i < max_cpus; i++) {
+ snprintf(name, 5, "CPU%u", i);
+ dev = aml_device("%s", name);
+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+ crs = aml_resource_template();
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ }
+}
+
+static void acpi_dsdt_add_uart(Aml *scope, const hwaddr *uart_addr,
+ const int *uart_irq)
+{
+ Aml *dev, *crs;
+
+ dev = aml_device("COM0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_memory32_fixed(uart_addr[0], uart_addr[1], 0x01));
+ aml_append(crs,
+ aml_interrupt(0x01, *uart_irq + 32));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_rtc(Aml *scope, const hwaddr *rtc_addr,
+ const int *rtc_irq)
+{
+ Aml *dev, *crs;
+
+ dev = aml_device("RTC0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_memory32_fixed(rtc_addr[0], rtc_addr[1], 0x01));
+ aml_append(crs,
+ aml_interrupt(0x01, *rtc_irq + 32));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_flash(Aml *scope, const hwaddr *flash_addr)
+{
+ Aml *dev, *crs;
+ hwaddr base = flash_addr[0];
+ hwaddr size = flash_addr[1];
+
+ dev = aml_device("FLS0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_memory32_fixed(base, size, 0x01));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+
+ dev = aml_device("FLS1");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_memory32_fixed(base + size, size, 0x01));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
+ const int *mmio_irq, int num)
+{
+ Aml *dev, *crs;
+ hwaddr base = mmio_addrs[0];
+ hwaddr size = mmio_addrs[1];
+ int irq = *mmio_irq + 32;
+ int i;
+ char name[5];
+
+ for (i = 0; i < num; i++) {
+ snprintf(name, 5, "VR%02u", i);
+ dev = aml_device("%s", name);
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_memory32_fixed(base, size, 0x01));
+ aml_append(crs,
+ aml_interrupt(0x01, irq + i));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ base += size;
+ }
+}
+
+/* DSDT */
+static void
+build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ Aml *scope, *dsdt;
+ acpi_dsdt_info *info = guest_info->dsdt_info;
+
+ dsdt = init_aml_allocator();
+ /* Reserve space for header */
+ acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
+
+ scope = aml_scope("\\_SB");
+ acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
+ acpi_dsdt_add_uart(scope, info->uart_addr, info->uart_irq);
+ acpi_dsdt_add_rtc(scope, info->rtc_addr, info->rtc_irq);
+ acpi_dsdt_add_flash(scope, info->flash_addr);
+ acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
+ info->virtio_mmio_irq, info->virtio_mmio_num);
+
+ aml_append(dsdt, scope);
+ /* copy AML table into ACPI tables blob and patch header there */
+ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
+ build_header(linker, table_data,
+ (void *)(table_data->data + table_data->len - dsdt->buf->len),
+ "DSDT", dsdt->buf->len, 1);
+ free_aml_allocator();
+}
+
typedef
struct AcpiBuildState {
/* Copy of table in RAM (for patching). */
@@ -72,6 +205,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
+ GArray *tables_blob = tables->table_data;
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -89,6 +223,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
* DSDT
*/
+ /* DSDT is pointed to by FADT */
+ build_dsdt(tables_blob, tables->linker, guest_info);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
@ 2015-04-09 9:51 ` Alex Bennée
2015-04-09 13:03 ` Igor Mammedov
2015-04-10 5:57 ` Shannon Zhao
0 siblings, 2 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 9:51 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> DSDT consists of the usual common table header plus a definition
> block in AML encoding which describes all devices in the platform.
>
> After initializing DSDT with header information the namespace is
> created which is followed by the device encodings. The devices are
> described using the Resource Template for the 32-Bit Fixed Memory
> Range and the Extended Interrupt Descriptors.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 137 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 388838a..516c1d0 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -57,6 +57,139 @@
> #define ACPI_BUILD_DPRINTF(fmt, ...)
> #endif
>
> +static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
> +{
> + Aml *dev, *crs;
> + int i;
> + char name[5];
name, dev and crs could be declared inside the for() loop.
> + for (i = 0; i < max_cpus; i++) {
> + snprintf(name, 5, "CPU%u", i);
What happens here if you have 10 or 100 CPUs?
> + dev = aml_device("%s", name);
Also aml_device seems to take a format string so why not simply:
dev = aml_device("CPU%u", i)
> + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> + crs = aml_resource_template();
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + }
> +}
> +
> +static void acpi_dsdt_add_uart(Aml *scope, const hwaddr *uart_addr,
> + const int *uart_irq)
> +{
> + Aml *dev, *crs;
> +
> + dev = aml_device("COM0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_memory32_fixed(uart_addr[0], uart_addr[1], 0x01));
> + aml_append(crs,
> + aml_interrupt(0x01, *uart_irq + 32));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> +
> +static void acpi_dsdt_add_rtc(Aml *scope, const hwaddr *rtc_addr,
> + const int *rtc_irq)
> +{
> + Aml *dev, *crs;
> +
> + dev = aml_device("RTC0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_memory32_fixed(rtc_addr[0], rtc_addr[1], 0x01));
> + aml_append(crs,
> + aml_interrupt(0x01, *rtc_irq + 32));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> +
> +static void acpi_dsdt_add_flash(Aml *scope, const hwaddr *flash_addr)
> +{
> + Aml *dev, *crs;
> + hwaddr base = flash_addr[0];
> + hwaddr size = flash_addr[1];
> +
> + dev = aml_device("FLS0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_memory32_fixed(base, size, 0x01));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +
> + dev = aml_device("FLS1");
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(1)));
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_memory32_fixed(base + size, size, 0x01));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> +
> +static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> + const int *mmio_irq, int num)
> +{
> + Aml *dev, *crs;
> + hwaddr base = mmio_addrs[0];
> + hwaddr size = mmio_addrs[1];
What ensures all these hw addresses are in 32 bit space on 64 bit platforms?
> + int irq = *mmio_irq + 32;
> + int i;
> + char name[5];
> +
> + for (i = 0; i < num; i++) {
> + snprintf(name, 5, "VR%02u", i);
> + dev = aml_device("%s", name);
Again why not call aml_device directly?
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> +
> + crs = aml_resource_template();
> + aml_append(crs,
> + aml_memory32_fixed(base, size, 0x01));
> + aml_append(crs,
> + aml_interrupt(0x01, irq + i));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + base += size;
> + }
> +}
> +
> +/* DSDT */
> +static void
> +build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> +{
> + Aml *scope, *dsdt;
> + acpi_dsdt_info *info = guest_info->dsdt_info;
> +
> + dsdt = init_aml_allocator();
> + /* Reserve space for header */
> + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
> +
> + scope = aml_scope("\\_SB");
> + acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
> + acpi_dsdt_add_uart(scope, info->uart_addr, info->uart_irq);
> + acpi_dsdt_add_rtc(scope, info->rtc_addr, info->rtc_irq);
> + acpi_dsdt_add_flash(scope, info->flash_addr);
> + acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
> + info->virtio_mmio_irq, info->virtio_mmio_num);
> +
> + aml_append(dsdt, scope);
> + /* copy AML table into ACPI tables blob and patch header there */
> + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
> + build_header(linker, table_data,
> + (void *)(table_data->data + table_data->len - dsdt->buf->len),
> + "DSDT", dsdt->buf->len, 1);
> + free_aml_allocator();
> +}
> +
> typedef
> struct AcpiBuildState {
> /* Copy of table in RAM (for patching). */
> @@ -72,6 +205,7 @@ static
> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> + GArray *tables_blob = tables->table_data;
>
> table_offsets = g_array_new(false, true /* clear */,
> sizeof(uint32_t));
> @@ -89,6 +223,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> * DSDT
> */
>
> + /* DSDT is pointed to by FADT */
> + build_dsdt(tables_blob, tables->linker, guest_info);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-09 9:51 ` Alex Bennée
@ 2015-04-09 13:03 ` Igor Mammedov
2015-04-10 5:59 ` Shannon Zhao
2015-04-10 5:57 ` Shannon Zhao
1 sibling, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 13:03 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Thu, 09 Apr 2015 10:51:33 +0100
Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >
> > DSDT consists of the usual common table header plus a definition
> > block in AML encoding which describes all devices in the platform.
> >
> > After initializing DSDT with header information the namespace is
> > created which is followed by the device encodings. The devices are
> > described using the Resource Template for the 32-Bit Fixed Memory
> > Range and the Extended Interrupt Descriptors.
> >
> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> > ---
> > hw/arm/virt-acpi-build.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 137 insertions(+)
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > index 388838a..516c1d0 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -57,6 +57,139 @@
> > #define ACPI_BUILD_DPRINTF(fmt, ...)
I wonder if all this DPRINTF crap should be replaced by tracepoints.
Oo at least it shouldn't be used in new code.
> > #endif
> >
> > +static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
> > +{
> > + Aml *dev, *crs;
> > + int i;
> > + char name[5];
>
> name, dev and crs could be declared inside the for() loop.
>
> > + for (i = 0; i < max_cpus; i++) {
> > + snprintf(name, 5, "CPU%u", i);
>
> What happens here if you have 10 or 100 CPUs?
>
> > + dev = aml_device("%s", name);
>
> Also aml_device seems to take a format string so why not simply:
>
> dev = aml_device("CPU%u", i)
On top of that, ACPI name is limited to 4 characters so
CPU%u will allow to specify only 10 cpus, to support more
shrink CPU part and do something like:
Scope(CPUS) {
Device(C000) {}
...
Device(CFFF) {}
}
that would give us upto max 4096 CPU,
I have on TODO list to convert bitmap based x86 cpu hotplug to
memory hotplug based interface so that we could easily
switch to more CPUs when KVM starts support it.
And for ARM there is no point to have/maintain 2 interfaces
as we would have to do on x86.
>
> > + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> > + crs = aml_resource_template();
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > + }
> > +}
> > +
> > +static void acpi_dsdt_add_uart(Aml *scope, const hwaddr *uart_addr,
> > + const int *uart_irq)
> > +{
> > + Aml *dev, *crs;
> > +
> > + dev = aml_device("COM0");
> > + aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> > +
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_memory32_fixed(uart_addr[0], uart_addr[1], 0x01));
uart_addr[0], uart_addr[1] doesn't tell anything about what they are.
and doing array of it when it's not dynamic sized is confusing not to
mention passing addresses and sizes in it.
The same goes for the rest of foo_addr[] used in this patch/series,
if it's _addr then it shouldn't contain sizes.
how about:
acpi_dsdt_add_uart(scope, uint32_t uart_addr, uint32_t uart_size, ...)
> > + aml_append(crs,
> > + aml_interrupt(0x01, *uart_irq + 32));
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > +}
> > +
> > +static void acpi_dsdt_add_rtc(Aml *scope, const hwaddr *rtc_addr,
> > + const int *rtc_irq)
> > +{
> > + Aml *dev, *crs;
> > +
> > + dev = aml_device("RTC0");
> > + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> > +
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_memory32_fixed(rtc_addr[0], rtc_addr[1], 0x01));
> > + aml_append(crs,
> > + aml_interrupt(0x01, *rtc_irq + 32));
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > +}
> > +
> > +static void acpi_dsdt_add_flash(Aml *scope, const hwaddr *flash_addr)
> > +{
> > + Aml *dev, *crs;
> > + hwaddr base = flash_addr[0];
> > + hwaddr size = flash_addr[1];
> > +
> > + dev = aml_device("FLS0");
> > + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> > +
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_memory32_fixed(base, size, 0x01));
join it with line above it if it doesn't exceed 80 chr
same goes for other places.
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > +
> > + dev = aml_device("FLS1");
> > + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(1)));
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_memory32_fixed(base + size, size, 0x01));
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > +}
> > +
> > +static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> > + const int *mmio_irq, int num)
> > +{
> > + Aml *dev, *crs;
> > + hwaddr base = mmio_addrs[0];
> > + hwaddr size = mmio_addrs[1];
>
> What ensures all these hw addresses are in 32 bit space on 64 bit platforms?
>
> > + int irq = *mmio_irq + 32;
> > + int i;
> > + char name[5];
> > +
> > + for (i = 0; i < num; i++) {
> > + snprintf(name, 5, "VR%02u", i);
> > + dev = aml_device("%s", name);
>
> Again why not call aml_device directly?
>
> > + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> > +
> > + crs = aml_resource_template();
> > + aml_append(crs,
> > + aml_memory32_fixed(base, size, 0x01));
> > + aml_append(crs,
> > + aml_interrupt(0x01, irq + i));
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > + base += size;
> > + }
> > +}
> > +
> > +/* DSDT */
> > +static void
> > +build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> > +{
> > + Aml *scope, *dsdt;
> > + acpi_dsdt_info *info = guest_info->dsdt_info;
> > +
> > + dsdt = init_aml_allocator();
> > + /* Reserve space for header */
> > + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
> > +
> > + scope = aml_scope("\\_SB");
> > + acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
> > + acpi_dsdt_add_uart(scope, info->uart_addr, info->uart_irq);
> > + acpi_dsdt_add_rtc(scope, info->rtc_addr, info->rtc_irq);
> > + acpi_dsdt_add_flash(scope, info->flash_addr);
> > + acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
> > + info->virtio_mmio_irq, info->virtio_mmio_num);
> > +
and drop this newline
> > + aml_append(dsdt, scope);
a newline here pls
> > + /* copy AML table into ACPI tables blob and patch header there */
> > + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
> > + build_header(linker, table_data,
> > + (void *)(table_data->data + table_data->len - dsdt->buf->len),
> > + "DSDT", dsdt->buf->len, 1);
> > + free_aml_allocator();
> > +}
> > +
> > typedef
> > struct AcpiBuildState {
> > /* Copy of table in RAM (for patching). */
> > @@ -72,6 +205,7 @@ static
> > void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> > {
> > GArray *table_offsets;
> > + GArray *tables_blob = tables->table_data;
> >
> > table_offsets = g_array_new(false, true /* clear */,
> > sizeof(uint32_t));
> > @@ -89,6 +223,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> > * DSDT
> > */
> >
> > + /* DSDT is pointed to by FADT */
> > + build_dsdt(tables_blob, tables->linker, guest_info);
> > +
> > /* Cleanup memory that's no longer used. */
> > g_array_free(table_offsets, true);
> > }
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-09 13:03 ` Igor Mammedov
@ 2015-04-10 5:59 ` Shannon Zhao
2015-04-10 7:35 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 5:59 UTC (permalink / raw)
To: Igor Mammedov, Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/9 21:03, Igor Mammedov wrote:
> On Thu, 09 Apr 2015 10:51:33 +0100
> Alex Bennée <alex.bennee@linaro.org> wrote:
>
>> >
>> > Shannon Zhao <zhaoshenglong@huawei.com> writes:
>> >
>>> > > From: Shannon Zhao <shannon.zhao@linaro.org>
>>> > >
>>> > > DSDT consists of the usual common table header plus a definition
>>> > > block in AML encoding which describes all devices in the platform.
>>> > >
>>> > > After initializing DSDT with header information the namespace is
>>> > > created which is followed by the device encodings. The devices are
>>> > > described using the Resource Template for the 32-Bit Fixed Memory
>>> > > Range and the Extended Interrupt Descriptors.
>>> > >
>>> > > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>> > > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>> > > ---
>>> > > hw/arm/virt-acpi-build.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++
>>> > > 1 file changed, 137 insertions(+)
>>> > >
>>> > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>> > > index 388838a..516c1d0 100644
>>> > > --- a/hw/arm/virt-acpi-build.c
>>> > > +++ b/hw/arm/virt-acpi-build.c
>>> > > @@ -57,6 +57,139 @@
>>> > > #define ACPI_BUILD_DPRINTF(fmt, ...)
> I wonder if all this DPRINTF crap should be replaced by tracepoints.
> Oo at least it shouldn't be used in new code.
>
Anything wrong with using DPRINTF?
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-10 5:59 ` Shannon Zhao
@ 2015-04-10 7:35 ` Igor Mammedov
0 siblings, 0 replies; 90+ messages in thread
From: Igor Mammedov @ 2015-04-10 7:35 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, lersek, mst, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
msalter, pbonzini, Alex Bennée, christoffer.dall,
shannon.zhao
On Fri, 10 Apr 2015 13:59:25 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/9 21:03, Igor Mammedov wrote:
> > On Thu, 09 Apr 2015 10:51:33 +0100
> > Alex Bennée <alex.bennee@linaro.org> wrote:
> >
> >> >
> >> > Shannon Zhao <zhaoshenglong@huawei.com> writes:
> >> >
> >>> > > From: Shannon Zhao <shannon.zhao@linaro.org>
> >>> > >
> >>> > > DSDT consists of the usual common table header plus a
> >>> > > definition block in AML encoding which describes all devices
> >>> > > in the platform.
> >>> > >
> >>> > > After initializing DSDT with header information the namespace
> >>> > > is created which is followed by the device encodings. The
> >>> > > devices are described using the Resource Template for the
> >>> > > 32-Bit Fixed Memory Range and the Extended Interrupt
> >>> > > Descriptors.
> >>> > >
> >>> > > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >>> > > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >>> > > ---
> >>> > > hw/arm/virt-acpi-build.c | 137
> >>> > > +++++++++++++++++++++++++++++++++++++++++++++++ 1 file
> >>> > > changed, 137 insertions(+)
> >>> > >
> >>> > > diff --git a/hw/arm/virt-acpi-build.c
> >>> > > b/hw/arm/virt-acpi-build.c index 388838a..516c1d0 100644
> >>> > > --- a/hw/arm/virt-acpi-build.c
> >>> > > +++ b/hw/arm/virt-acpi-build.c
> >>> > > @@ -57,6 +57,139 @@
> >>> > > #define ACPI_BUILD_DPRINTF(fmt, ...)
> > I wonder if all this DPRINTF crap should be replaced by tracepoints.
> > Oo at least it shouldn't be used in new code.
> >
>
> Anything wrong with using DPRINTF?
tracepoints could be enabled without rebuilding qemu
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-04-09 9:51 ` Alex Bennée
2015-04-09 13:03 ` Igor Mammedov
@ 2015-04-10 5:57 ` Shannon Zhao
1 sibling, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 5:57 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/9 17:51, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> DSDT consists of the usual common table header plus a definition
>> block in AML encoding which describes all devices in the platform.
>>
>> After initializing DSDT with header information the namespace is
>> created which is followed by the device encodings. The devices are
>> described using the Resource Template for the 32-Bit Fixed Memory
>> Range and the Extended Interrupt Descriptors.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 137 insertions(+)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index 388838a..516c1d0 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -57,6 +57,139 @@
>> #define ACPI_BUILD_DPRINTF(fmt, ...)
>> #endif
>>
>> +static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
>> +{
>> + Aml *dev, *crs;
>> + int i;
>> + char name[5];
>
> name, dev and crs could be declared inside the for() loop.
>
>> + for (i = 0; i < max_cpus; i++) {
>> + snprintf(name, 5, "CPU%u", i);
>
> What happens here if you have 10 or 100 CPUs?
>
>> + dev = aml_device("%s", name);
>
> Also aml_device seems to take a format string so why not simply:
>
> dev = aml_device("CPU%u", i)
>
Ok, it's better.
>> + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
>> + crs = aml_resource_template();
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> + }
>> +}
>> +
>> +static void acpi_dsdt_add_uart(Aml *scope, const hwaddr *uart_addr,
>> + const int *uart_irq)
>> +{
>> + Aml *dev, *crs;
>> +
>> + dev = aml_device("COM0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>> +
>> + crs = aml_resource_template();
>> + aml_append(crs,
>> + aml_memory32_fixed(uart_addr[0], uart_addr[1], 0x01));
>> + aml_append(crs,
>> + aml_interrupt(0x01, *uart_irq + 32));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +}
>> +
>> +static void acpi_dsdt_add_rtc(Aml *scope, const hwaddr *rtc_addr,
>> + const int *rtc_irq)
>> +{
>> + Aml *dev, *crs;
>> +
>> + dev = aml_device("RTC0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>> +
>> + crs = aml_resource_template();
>> + aml_append(crs,
>> + aml_memory32_fixed(rtc_addr[0], rtc_addr[1], 0x01));
>> + aml_append(crs,
>> + aml_interrupt(0x01, *rtc_irq + 32));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +}
>> +
>> +static void acpi_dsdt_add_flash(Aml *scope, const hwaddr *flash_addr)
>> +{
>> + Aml *dev, *crs;
>> + hwaddr base = flash_addr[0];
>> + hwaddr size = flash_addr[1];
>> +
>> + dev = aml_device("FLS0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>> +
>> + crs = aml_resource_template();
>> + aml_append(crs,
>> + aml_memory32_fixed(base, size, 0x01));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +
>> + dev = aml_device("FLS1");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(1)));
>> + crs = aml_resource_template();
>> + aml_append(crs,
>> + aml_memory32_fixed(base + size, size, 0x01));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> +}
>> +
>> +static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
>> + const int *mmio_irq, int num)
>> +{
>> + Aml *dev, *crs;
>> + hwaddr base = mmio_addrs[0];
>> + hwaddr size = mmio_addrs[1];
>
> What ensures all these hw addresses are in 32 bit space on 64 bit platforms?
>
As we're generating the ACPI tables for machine virt, from a15memmap[] we know the hw addresses are below 1GB.
>> + int irq = *mmio_irq + 32;
>> + int i;
>> + char name[5];
>> +
>> + for (i = 0; i < num; i++) {
>> + snprintf(name, 5, "VR%02u", i);
>> + dev = aml_device("%s", name);
>
> Again why not call aml_device directly?
>
>> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
>> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
>> +
>> + crs = aml_resource_template();
>> + aml_append(crs,
>> + aml_memory32_fixed(base, size, 0x01));
>> + aml_append(crs,
>> + aml_interrupt(0x01, irq + i));
>> + aml_append(dev, aml_name_decl("_CRS", crs));
>> + aml_append(scope, dev);
>> + base += size;
>> + }
>> +}
>> +
>> +/* DSDT */
>> +static void
>> +build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>> +{
>> + Aml *scope, *dsdt;
>> + acpi_dsdt_info *info = guest_info->dsdt_info;
>> +
>> + dsdt = init_aml_allocator();
>> + /* Reserve space for header */
>> + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
>> +
>> + scope = aml_scope("\\_SB");
>> + acpi_dsdt_add_cpus(scope, guest_info->max_cpus);
>> + acpi_dsdt_add_uart(scope, info->uart_addr, info->uart_irq);
>> + acpi_dsdt_add_rtc(scope, info->rtc_addr, info->rtc_irq);
>> + acpi_dsdt_add_flash(scope, info->flash_addr);
>> + acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
>> + info->virtio_mmio_irq, info->virtio_mmio_num);
>> +
>> + aml_append(dsdt, scope);
>> + /* copy AML table into ACPI tables blob and patch header there */
>> + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
>> + build_header(linker, table_data,
>> + (void *)(table_data->data + table_data->len - dsdt->buf->len),
>> + "DSDT", dsdt->buf->len, 1);
>> + free_aml_allocator();
>> +}
>> +
>> typedef
>> struct AcpiBuildState {
>> /* Copy of table in RAM (for patching). */
>> @@ -72,6 +205,7 @@ static
>> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> {
>> GArray *table_offsets;
>> + GArray *tables_blob = tables->table_data;
>>
>> table_offsets = g_array_new(false, true /* clear */,
>> sizeof(uint32_t));
>> @@ -89,6 +223,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> * DSDT
>> */
>>
>> + /* DSDT is pointed to by FADT */
>> + build_dsdt(tables_blob, tables->linker, guest_info);
>> +
>> /* Cleanup memory that's no longer used. */
>> g_array_free(table_offsets, true);
>> }
>
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (5 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 06/20] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-08 18:53 ` Michael S. Tsirkin
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
` (14 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
In the case of mach virt, it is used to set the Hardware Reduced bit
and enable PSCI SMP booting through HVC. So ignore FACS and FADT
points to DSDT.
Update the header definitions for FADT taking into account the new
additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 31 ++++++++++++
include/hw/acpi/acpi-defs.h | 114 ++++++++++++++++++++++++++++++--------------
2 files changed, 108 insertions(+), 37 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 516c1d0..cb8b030 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -162,6 +162,31 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
}
}
+/* FADT */
+static void
+build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
+{
+ AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
+
+ /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
+ fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
+ fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
+ (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
+
+ /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
+ fadt->minor_revision = 0x1;
+
+ fadt->dsdt = cpu_to_le32(dsdt);
+ /* DSDT address to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ table_data, &fadt->dsdt,
+ sizeof fadt->dsdt);
+
+ build_header(linker, table_data,
+ (void *)fadt, "FACP", sizeof(*fadt), 5);
+}
+
/* DSDT */
static void
build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -205,6 +230,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
+ unsigned dsdt;
GArray *tables_blob = tables->table_data;
table_offsets = g_array_new(false, true /* clear */,
@@ -224,8 +250,13 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
*/
/* DSDT is pointed to by FADT */
+ dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, guest_info);
+ /* FADT MADT GTDT pointed to by RSDT */
+ acpi_add_table(table_offsets, tables_blob);
+ build_fadt(tables_blob, tables->linker, dsdt);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index c4468f8..e588df5 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -88,46 +88,49 @@ struct AcpiTableHeader /* ACPI common table header */
typedef struct AcpiTableHeader AcpiTableHeader;
/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ * ACPI Fixed ACPI Description Table (FADT)
*/
+#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
+ uint32_t firmware_ctrl; /* Physical address of FACS */ \
+ uint32_t dsdt; /* Physical address of DSDT */ \
+ uint8_t model; /* System Interrupt Model */ \
+ uint8_t reserved1; /* Reserved */ \
+ uint16_t sci_int; /* System vector of SCI interrupt */ \
+ uint32_t smi_cmd; /* Port address of SMI command port */ \
+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
+ uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ \
+ uint8_t reserved2; /* Reserved - must be zero */ \
+ uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ \
+ uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ \
+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
+ uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
+ uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
+ uint8_t reserved3; /* Reserved */ \
+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
+ uint16_t flush_size; /* Size of area read to flush caches */ \
+ uint16_t flush_stride; /* Stride used in flushing caches */ \
+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
+ uint8_t century; /* Index to century in RTC CMOS RAM */
+
struct AcpiFadtDescriptorRev1
{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t firmware_ctrl; /* Physical address of FACS */
- uint32_t dsdt; /* Physical address of DSDT */
- uint8_t model; /* System Interrupt Model */
- uint8_t reserved1; /* Reserved */
- uint16_t sci_int; /* System vector of SCI interrupt */
- uint32_t smi_cmd; /* Port address of SMI command port */
- uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
- uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
- uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- uint8_t reserved2; /* Reserved - must be zero */
- uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
- uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
- uint8_t reserved3; /* Reserved */
- uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
- uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
- uint16_t flush_size; /* Size of area read to flush caches */
- uint16_t flush_stride; /* Stride used in flushing caches */
- uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
- uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
- uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
- uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
- uint8_t century; /* Index to century in RTC CMOS RAM */
+ ACPI_FADT_COMMON_DEF
uint8_t reserved4; /* Reserved */
uint8_t reserved4a; /* Reserved */
uint8_t reserved4b; /* Reserved */
@@ -135,6 +138,43 @@ struct AcpiFadtDescriptorRev1
} QEMU_PACKED;
typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+struct acpi_generic_address {
+ uint8_t space_id; /* Address space where struct or register exists */
+ uint8_t bit_width; /* Size in bits of given register */
+ uint8_t bit_offset; /* Bit offset within the register */
+ uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
+ uint64_t address; /* 64-bit address of struct or register */
+} QEMU_PACKED;
+
+struct AcpiFadtDescriptorRev5_1 {
+ ACPI_FADT_COMMON_DEF
+ uint16_t boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
+ uint8_t reserved; /* Reserved, must be zero */
+ uint32_t flags; /* Miscellaneous flag bits (see below for individual flags) */
+ struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
+ uint8_t reset_value; /* Value to write to the reset_register port to reset the system */
+ uint16_t arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
+ uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
+ uint64_t Xfacs; /* 64-bit physical address of FACS */
+ uint64_t Xdsdt; /* 64-bit physical address of DSDT */
+ struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
+ struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
+ struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
+ struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
+ struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
+ struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
+ struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
+ struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
+ struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
+ struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
+} QEMU_PACKED;
+typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
+
+enum {
+ ACPI_FADT_ARM_USE_PSCI_G_0_2,
+ ACPI_FADT_ARM_PSCI_USE_HVC,
+};
+
/*
* ACPI 1.0 Root System Description Table (RSDT)
*/
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
@ 2015-04-08 18:53 ` Michael S. Tsirkin
2015-04-09 2:55 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-08 18:53 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Fri, Apr 03, 2015 at 06:03:39PM +0800, Shannon Zhao wrote:
> @@ -135,6 +138,43 @@ struct AcpiFadtDescriptorRev1
> } QEMU_PACKED;
> typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
>
> +struct acpi_generic_address {
> + uint8_t space_id; /* Address space where struct or register exists */
> + uint8_t bit_width; /* Size in bits of given register */
> + uint8_t bit_offset; /* Bit offset within the register */
> + uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
> + uint64_t address; /* 64-bit address of struct or register */
> +} QEMU_PACKED;
Pls use standard QEMU style for structs.
There are more like this in the patchset, pls find and fix them.
> +
> +struct AcpiFadtDescriptorRev5_1 {
> + ACPI_FADT_COMMON_DEF
> + uint16_t boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
> + uint8_t reserved; /* Reserved, must be zero */
> + uint32_t flags; /* Miscellaneous flag bits (see below for individual flags) */
> + struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
> + uint8_t reset_value; /* Value to write to the reset_register port to reset the system */
> + uint16_t arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
> + uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
> + uint64_t Xfacs; /* 64-bit physical address of FACS */
> + uint64_t Xdsdt; /* 64-bit physical address of DSDT */
> + struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
> + struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
> + struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
> + struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
> + struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
> + struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
> + struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
> + struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
> + struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
> + struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
> +} QEMU_PACKED;
empty line missing.
> +typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
> +
> +enum {
> + ACPI_FADT_ARM_USE_PSCI_G_0_2,
> + ACPI_FADT_ARM_PSCI_USE_HVC,
> +};
These are part of tables, are they not?
Pls add = 0, = 1, so we don't change them by mistake.
> +
> /*
> * ACPI 1.0 Root System Description Table (RSDT)
> */
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-04-08 18:53 ` Michael S. Tsirkin
@ 2015-04-09 2:55 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-09 2:55 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, hangaohuai, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/9 2:53, Michael S. Tsirkin wrote:
> On Fri, Apr 03, 2015 at 06:03:39PM +0800, Shannon Zhao wrote:
>> @@ -135,6 +138,43 @@ struct AcpiFadtDescriptorRev1
>> } QEMU_PACKED;
>> typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
>>
>> +struct acpi_generic_address {
>> + uint8_t space_id; /* Address space where struct or register exists */
>> + uint8_t bit_width; /* Size in bits of given register */
>> + uint8_t bit_offset; /* Bit offset within the register */
>> + uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
>> + uint64_t address; /* 64-bit address of struct or register */
>> +} QEMU_PACKED;
>
> Pls use standard QEMU style for structs.
> There are more like this in the patchset, pls find and fix them.
>
Ok, thanks.
>
>> +
>> +struct AcpiFadtDescriptorRev5_1 {
>> + ACPI_FADT_COMMON_DEF
>> + uint16_t boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
>> + uint8_t reserved; /* Reserved, must be zero */
>> + uint32_t flags; /* Miscellaneous flag bits (see below for individual flags) */
>> + struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
>> + uint8_t reset_value; /* Value to write to the reset_register port to reset the system */
>> + uint16_t arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
>> + uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
>> + uint64_t Xfacs; /* 64-bit physical address of FACS */
>> + uint64_t Xdsdt; /* 64-bit physical address of DSDT */
>> + struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
>> + struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
>> + struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
>> + struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
>> + struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
>> + struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
>> + struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
>> + struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
>> + struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
>> + struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
>> +} QEMU_PACKED;
>
> empty line missing.
>
ok.
>> +typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
>> +
>> +enum {
>> + ACPI_FADT_ARM_USE_PSCI_G_0_2,
>> + ACPI_FADT_ARM_PSCI_USE_HVC,
>> +};
>
> These are part of tables, are they not?
They are the values of arm_boot_flags in AcpiFadtDescriptorRev5_1.
> Pls add = 0, = 1, so we don't change them by mistake.
Ok, thanks.
>
>> +
>> /*
>> * ACPI 1.0 Root System Description Table (RSDT)
>> */
>> --
>> 2.0.4
>>
>
> .
>
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 08/20] hw/arm/virt-acpi-build: Generate MADT table
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (6 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 07/20] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 12:33 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 09/20] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
` (13 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
MADT describes GIC enabled ARM platforms. The GICC and GICD
subtables are used to define the GIC regions.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 61 ++++++++++++++++++++++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 36 +++++++++++++++++++++++-
include/hw/arm/virt-acpi-build.h | 2 ++
3 files changed, 98 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index cb8b030..c8245ef 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -57,6 +57,20 @@
#define ACPI_BUILD_DPRINTF(fmt, ...)
#endif
+typedef struct VirtAcpiCpuInfo {
+ DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
+} VirtAcpiCpuInfo;
+
+static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
+{
+ CPUState *cpu;
+
+ memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
+ CPU_FOREACH(cpu) {
+ set_bit(cpu->cpu_index, cpuinfo->found_cpus);
+ }
+}
+
static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
{
Aml *dev, *crs;
@@ -162,6 +176,47 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
}
}
+/* MADT */
+static void
+build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
+ VirtAcpiCpuInfo *cpuinfo)
+{
+ int madt_start = table_data->len;
+ const struct acpi_madt_info *info = guest_info->madt_info;
+ AcpiMultipleApicTable *madt;
+ AcpiMadtGenericDistributor *gicd;
+ int i;
+
+ madt = acpi_data_push(table_data, sizeof *madt);
+ madt->local_apic_address = *info->gic_cpu_base_addr;
+ madt->flags = cpu_to_le32(1);
+
+ for (i = 0; i < guest_info->max_cpus; i++) {
+ AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
+ sizeof *gicc);
+ gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
+ gicc->length = sizeof(*gicc);
+ gicc->base_address = *info->gic_cpu_base_addr;
+ gicc->cpu_interface_number = i;
+ gicc->arm_mpidr = i;
+ gicc->uid = i;
+ if (test_bit(i, cpuinfo->found_cpus)) {
+ gicc->flags = cpu_to_le32(1);
+ } else {
+ gicc->flags = cpu_to_le32(0);
+ }
+ }
+
+ gicd = acpi_data_push(table_data, sizeof *gicd);
+ gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
+ gicd->length = sizeof(*gicd);
+ gicd->base_address = *info->gic_dist_base_addr;
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + madt_start), "APIC",
+ table_data->len - madt_start, 1);
+}
+
/* FADT */
static void
build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
@@ -231,8 +286,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
unsigned dsdt;
+ VirtAcpiCpuInfo cpuinfo;
GArray *tables_blob = tables->table_data;
+ virt_acpi_get_cpu_info(&cpuinfo);
+
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -257,6 +315,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, tables->linker, dsdt);
+ acpi_add_table(table_offsets, tables_blob);
+ build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index e588df5..e343728 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -235,7 +235,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_IO_SAPIC 6
#define ACPI_APIC_LOCAL_SAPIC 7
#define ACPI_APIC_XRUPT_SOURCE 8
-#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
+#define ACPI_APIC_LOCAL_X2APIC 9
+#define ACPI_APIC_LOCAL_X2APIC_NMI 10
+#define ACPI_APIC_GENERIC_INTERRUPT 11
+#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
+#define ACPI_APIC_GENERIC_MSI_FRAME 13
+#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
+#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
@@ -283,6 +289,34 @@ struct AcpiMadtLocalNmi {
} QEMU_PACKED;
typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+struct AcpiMadtGenericInterrupt {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t cpu_interface_number;
+ uint32_t uid;
+ uint32_t flags;
+ uint32_t parking_version;
+ uint32_t performance_interrupt;
+ uint64_t parked_address;
+ uint64_t base_address;
+ uint64_t gicv_base_address;
+ uint64_t gich_base_address;
+ uint32_t vgic_interrupt;
+ uint64_t gicr_base_address;
+ uint64_t arm_mpidr;
+} QEMU_PACKED;
+typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
+
+struct AcpiMadtGenericDistributor {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t gic_id;
+ uint64_t base_address;
+ uint32_t global_irq_base;
+ uint32_t reserved2;
+} QEMU_PACKED;
+typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
+
/*
* HPET Description Table
*/
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
index 175eac2..2780856 100644
--- a/include/hw/arm/virt-acpi-build.h
+++ b/include/hw/arm/virt-acpi-build.h
@@ -22,6 +22,8 @@
#include "qemu-common.h"
+#define VIRT_ACPI_CPU_ID_LIMIT 8
+
typedef struct acpi_gtdt_info {
uint32_t timer_virt;
uint32_t timer_s_el1;
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 08/20] hw/arm/virt-acpi-build: Generate MADT table
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
@ 2015-04-09 12:33 ` Alex Bennée
0 siblings, 0 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 12:33 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> MADT describes GIC enabled ARM platforms. The GICC and GICD
> subtables are used to define the GIC regions.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 61 ++++++++++++++++++++++++++++++++++++++++
> include/hw/acpi/acpi-defs.h | 36 +++++++++++++++++++++++-
> include/hw/arm/virt-acpi-build.h | 2 ++
> 3 files changed, 98 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index cb8b030..c8245ef 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -57,6 +57,20 @@
> #define ACPI_BUILD_DPRINTF(fmt, ...)
> #endif
>
> +typedef struct VirtAcpiCpuInfo {
> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> +} VirtAcpiCpuInfo;
> +
> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
> +{
> + CPUState *cpu;
> +
> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
> + CPU_FOREACH(cpu) {
> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
> + }
> +}
> +
> static void acpi_dsdt_add_cpus(Aml *scope, int max_cpus)
> {
> Aml *dev, *crs;
> @@ -162,6 +176,47 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> }
> }
>
> +/* MADT */
> +static void
> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
> + VirtAcpiCpuInfo *cpuinfo)
> +{
> + int madt_start = table_data->len;
> + const struct acpi_madt_info *info = guest_info->madt_info;
> + AcpiMultipleApicTable *madt;
> + AcpiMadtGenericDistributor *gicd;
> + int i;
> +
> + madt = acpi_data_push(table_data, sizeof *madt);
> + madt->local_apic_address = *info->gic_cpu_base_addr;
> + madt->flags = cpu_to_le32(1);
> +
> + for (i = 0; i < guest_info->max_cpus; i++) {
> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
> + sizeof *gicc);
> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
> + gicc->length = sizeof(*gicc);
> + gicc->base_address = *info->gic_cpu_base_addr;
> + gicc->cpu_interface_number = i;
> + gicc->arm_mpidr = i;
> + gicc->uid = i;
> + if (test_bit(i, cpuinfo->found_cpus)) {
> + gicc->flags = cpu_to_le32(1);
> + } else {
> + gicc->flags = cpu_to_le32(0);
> + }
> + }
> +
> + gicd = acpi_data_push(table_data, sizeof *gicd);
> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
> + gicd->length = sizeof(*gicd);
> + gicd->base_address = *info->gic_dist_base_addr;
> +
> + build_header(linker, table_data,
> + (void *)(table_data->data + madt_start), "APIC",
> + table_data->len - madt_start, 1);
> +}
> +
> /* FADT */
> static void
> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
> @@ -231,8 +286,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> unsigned dsdt;
> + VirtAcpiCpuInfo cpuinfo;
> GArray *tables_blob = tables->table_data;
>
> + virt_acpi_get_cpu_info(&cpuinfo);
> +
> table_offsets = g_array_new(false, true /* clear */,
> sizeof(uint32_t));
>
> @@ -257,6 +315,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_fadt(tables_blob, tables->linker, dsdt);
>
> + acpi_add_table(table_offsets, tables_blob);
> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index e588df5..e343728 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -235,7 +235,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
> #define ACPI_APIC_IO_SAPIC 6
> #define ACPI_APIC_LOCAL_SAPIC 7
> #define ACPI_APIC_XRUPT_SOURCE 8
> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
> +#define ACPI_APIC_LOCAL_X2APIC 9
> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
> +#define ACPI_APIC_GENERIC_INTERRUPT 11
> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>
> /*
> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
> @@ -283,6 +289,34 @@ struct AcpiMadtLocalNmi {
> } QEMU_PACKED;
> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
>
> +struct AcpiMadtGenericInterrupt {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t cpu_interface_number;
> + uint32_t uid;
> + uint32_t flags;
> + uint32_t parking_version;
> + uint32_t performance_interrupt;
> + uint64_t parked_address;
> + uint64_t base_address;
> + uint64_t gicv_base_address;
> + uint64_t gich_base_address;
> + uint32_t vgic_interrupt;
> + uint64_t gicr_base_address;
> + uint64_t arm_mpidr;
> +} QEMU_PACKED;
> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
> +
> +struct AcpiMadtGenericDistributor {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t gic_id;
> + uint64_t base_address;
> + uint32_t global_irq_base;
> + uint32_t reserved2;
> +} QEMU_PACKED;
> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
> +
> /*
> * HPET Description Table
> */
> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
> index 175eac2..2780856 100644
> --- a/include/hw/arm/virt-acpi-build.h
> +++ b/include/hw/arm/virt-acpi-build.h
> @@ -22,6 +22,8 @@
>
> #include "qemu-common.h"
>
> +#define VIRT_ACPI_CPU_ID_LIMIT 8
> +
> typedef struct acpi_gtdt_info {
> uint32_t timer_virt;
> uint32_t timer_s_el1;
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 09/20] hw/arm/virt-acpi-build: Generate GTDT table
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (7 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 08/20] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 12:42 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
` (12 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
related information in the system. The Arch Timer interrupts must
be provided for GTDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 30 ++++++++++++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index c8245ef..a7aba75 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -176,6 +176,33 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
}
}
+/* GTDT */
+static void
+build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ int gtdt_start = table_data->len;
+ const struct acpi_gtdt_info *info = guest_info->gtdt_info;
+ AcpiGenericTimerTable *gtdt;
+
+ gtdt = acpi_data_push(table_data, sizeof *gtdt);
+ /* The interrupt values are the same with the device tree when adding 16 */
+ gtdt->secure_el1_interrupt = info->timer_s_el1;
+ gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->non_secure_el1_interrupt = info->timer_ns_el1;
+ gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->virtual_timer_interrupt = info->timer_virt;
+ gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->non_secure_el2_interrupt = info->timer_ns_el2;
+ gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + gtdt_start), "GTDT",
+ table_data->len - gtdt_start, 1);
+}
+
/* MADT */
static void
build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
@@ -318,6 +345,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
+ acpi_add_table(table_offsets, tables_blob);
+ build_gtdt(tables_blob, tables->linker, guest_info);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index e343728..ee40a5e 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -318,6 +318,43 @@ struct AcpiMadtGenericDistributor {
typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
/*
+ * Generic Timer Description Table (GTDT)
+ */
+
+#define ACPI_GTDT_INTERRUPT_MODE (1)
+#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
+#define ACPI_GTDT_ALWAYS_ON (1<<2)
+
+/* Triggering */
+
+#define ACPI_LEVEL_SENSITIVE (uint8_t) 0x00
+#define ACPI_EDGE_SENSITIVE (uint8_t) 0x01
+
+/* Polarity */
+
+#define ACPI_ACTIVE_HIGH (uint8_t) 0x00
+#define ACPI_ACTIVE_LOW (uint8_t) 0x01
+#define ACPI_ACTIVE_BOTH (uint8_t) 0x02
+
+struct AcpiGenericTimerTable {
+ ACPI_TABLE_HEADER_DEF
+ uint64_t counter_block_addresss;
+ uint32_t reserved;
+ uint32_t secure_el1_interrupt;
+ uint32_t secure_el1_flags;
+ uint32_t non_secure_el1_interrupt;
+ uint32_t non_secure_el1_flags;
+ uint32_t virtual_timer_interrupt;
+ uint32_t virtual_timer_flags;
+ uint32_t non_secure_el2_interrupt;
+ uint32_t non_secure_el2_flags;
+ uint64_t counter_read_block_address;
+ uint32_t platform_timer_count;
+ uint32_t platform_timer_offset;
+} QEMU_PACKED;
+typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
+
+/*
* HPET Description Table
*/
struct Acpi20Hpet {
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 09/20] hw/arm/virt-acpi-build: Generate GTDT table
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 09/20] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
@ 2015-04-09 12:42 ` Alex Bennée
2015-04-10 6:01 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 12:42 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
> related information in the system. The Arch Timer interrupts must
> be provided for GTDT.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 30 ++++++++++++++++++++++++++++++
> include/hw/acpi/acpi-defs.h | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 67 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index c8245ef..a7aba75 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -176,6 +176,33 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> }
> }
>
> +/* GTDT */
> +static void
> +build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> +{
> + int gtdt_start = table_data->len;
> + const struct acpi_gtdt_info *info = guest_info->gtdt_info;
> + AcpiGenericTimerTable *gtdt;
> +
> + gtdt = acpi_data_push(table_data, sizeof *gtdt);
> + /* The interrupt values are the same with the device tree when adding 16 */
> + gtdt->secure_el1_interrupt = info->timer_s_el1;
> + gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
> +
> + gtdt->non_secure_el1_interrupt = info->timer_ns_el1;
> + gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
> +
> + gtdt->virtual_timer_interrupt = info->timer_virt;
> + gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
> +
> + gtdt->non_secure_el2_interrupt = info->timer_ns_el2;
> + gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
> +
> + build_header(linker, table_data,
> + (void *)(table_data->data + gtdt_start), "GTDT",
> + table_data->len - gtdt_start, 1);
> +}
> +
> /* MADT */
> static void
> build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
> @@ -318,6 +345,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
>
> + acpi_add_table(table_offsets, tables_blob);
> + build_gtdt(tables_blob, tables->linker, guest_info);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index e343728..ee40a5e 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -318,6 +318,43 @@ struct AcpiMadtGenericDistributor {
> typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
>
> /*
> + * Generic Timer Description Table (GTDT)
> + */
> +
> +#define ACPI_GTDT_INTERRUPT_MODE (1)
(1 << 0) would be consistent
> +#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
> +#define ACPI_GTDT_ALWAYS_ON (1<<2)
Also spaces (n << m)
> +
> +/* Triggering */
> +
> +#define ACPI_LEVEL_SENSITIVE (uint8_t) 0x00
> +#define ACPI_EDGE_SENSITIVE (uint8_t) 0x01
> +
> +/* Polarity */
> +
> +#define ACPI_ACTIVE_HIGH (uint8_t) 0x00
> +#define ACPI_ACTIVE_LOW (uint8_t) 0x01
> +#define ACPI_ACTIVE_BOTH (uint8_t) 0x02
I'd wrap those cast defines, e.g:
#define ACPI_ACTIVE_BOTH ((uint8_t) 0x02)
> +
> +struct AcpiGenericTimerTable {
> + ACPI_TABLE_HEADER_DEF
> + uint64_t counter_block_addresss;
> + uint32_t reserved;
> + uint32_t secure_el1_interrupt;
> + uint32_t secure_el1_flags;
> + uint32_t non_secure_el1_interrupt;
> + uint32_t non_secure_el1_flags;
> + uint32_t virtual_timer_interrupt;
> + uint32_t virtual_timer_flags;
> + uint32_t non_secure_el2_interrupt;
> + uint32_t non_secure_el2_flags;
> + uint64_t counter_read_block_address;
> + uint32_t platform_timer_count;
> + uint32_t platform_timer_offset;
> +} QEMU_PACKED;
> +typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
> +
> +/*
> * HPET Description Table
> */
> struct Acpi20Hpet {
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 09/20] hw/arm/virt-acpi-build: Generate GTDT table
2015-04-09 12:42 ` Alex Bennée
@ 2015-04-10 6:01 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 6:01 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/9 20:42, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
>> related information in the system. The Arch Timer interrupts must
>> be provided for GTDT.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 30 ++++++++++++++++++++++++++++++
>> include/hw/acpi/acpi-defs.h | 37 +++++++++++++++++++++++++++++++++++++
>> 2 files changed, 67 insertions(+)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index c8245ef..a7aba75 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -176,6 +176,33 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
>> }
>> }
>>
>> +/* GTDT */
>> +static void
>> +build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>> +{
>> + int gtdt_start = table_data->len;
>> + const struct acpi_gtdt_info *info = guest_info->gtdt_info;
>> + AcpiGenericTimerTable *gtdt;
>> +
>> + gtdt = acpi_data_push(table_data, sizeof *gtdt);
>> + /* The interrupt values are the same with the device tree when adding 16 */
>> + gtdt->secure_el1_interrupt = info->timer_s_el1;
>> + gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
>> +
>> + gtdt->non_secure_el1_interrupt = info->timer_ns_el1;
>> + gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
>> +
>> + gtdt->virtual_timer_interrupt = info->timer_virt;
>> + gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
>> +
>> + gtdt->non_secure_el2_interrupt = info->timer_ns_el2;
>> + gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
>> +
>> + build_header(linker, table_data,
>> + (void *)(table_data->data + gtdt_start), "GTDT",
>> + table_data->len - gtdt_start, 1);
>> +}
>> +
>> /* MADT */
>> static void
>> build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
>> @@ -318,6 +345,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> acpi_add_table(table_offsets, tables_blob);
>> build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
>>
>> + acpi_add_table(table_offsets, tables_blob);
>> + build_gtdt(tables_blob, tables->linker, guest_info);
>> +
>> /* Cleanup memory that's no longer used. */
>> g_array_free(table_offsets, true);
>> }
>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>> index e343728..ee40a5e 100644
>> --- a/include/hw/acpi/acpi-defs.h
>> +++ b/include/hw/acpi/acpi-defs.h
>> @@ -318,6 +318,43 @@ struct AcpiMadtGenericDistributor {
>> typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
>>
>> /*
>> + * Generic Timer Description Table (GTDT)
>> + */
>> +
>> +#define ACPI_GTDT_INTERRUPT_MODE (1)
>
> (1 << 0) would be consistent
>
Ok
>> +#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
>> +#define ACPI_GTDT_ALWAYS_ON (1<<2)
>
> Also spaces (n << m)
>
will fix.
>> +
>> +/* Triggering */
>> +
>> +#define ACPI_LEVEL_SENSITIVE (uint8_t) 0x00
>> +#define ACPI_EDGE_SENSITIVE (uint8_t) 0x01
>> +
>> +/* Polarity */
>> +
>> +#define ACPI_ACTIVE_HIGH (uint8_t) 0x00
>> +#define ACPI_ACTIVE_LOW (uint8_t) 0x01
>> +#define ACPI_ACTIVE_BOTH (uint8_t) 0x02
>
> I'd wrap those cast defines, e.g:
>
> #define ACPI_ACTIVE_BOTH ((uint8_t) 0x02)
>
Ok, will fix. Thanks.
>> +
>> +struct AcpiGenericTimerTable {
>> + ACPI_TABLE_HEADER_DEF
>> + uint64_t counter_block_addresss;
>> + uint32_t reserved;
>> + uint32_t secure_el1_interrupt;
>> + uint32_t secure_el1_flags;
>> + uint32_t non_secure_el1_interrupt;
>> + uint32_t non_secure_el1_flags;
>> + uint32_t virtual_timer_interrupt;
>> + uint32_t virtual_timer_flags;
>> + uint32_t non_secure_el2_interrupt;
>> + uint32_t non_secure_el2_flags;
>> + uint64_t counter_read_block_address;
>> + uint32_t platform_timer_count;
>> + uint32_t platform_timer_offset;
>> +} QEMU_PACKED;
>> +typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
>> +
>> +/*
>> * HPET Description Table
>> */
>> struct Acpi20Hpet {
>
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (8 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 09/20] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 12:50 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 11/20] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
` (11 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
RSDT points to other tables FADT, MADT, GTDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index a7aba75..85e84b1 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -176,6 +176,30 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
}
}
+/* RSDT */
+static void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
+{
+ AcpiRsdtDescriptorRev1 *rsdt;
+ size_t rsdt_len;
+ int i;
+
+ rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
+ rsdt = acpi_data_push(table_data, rsdt_len);
+ memcpy(rsdt->table_offset_entry, table_offsets->data,
+ sizeof(uint32_t) * table_offsets->len);
+ for (i = 0; i < table_offsets->len; ++i) {
+ /* rsdt->table_offset_entry to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker,
+ ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ table_data, &rsdt->table_offset_entry[i],
+ sizeof(uint32_t));
+ }
+ build_header(linker, table_data,
+ (void *)rsdt, "RSDT", rsdt_len, 1);
+}
+
/* GTDT */
static void
build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -348,6 +372,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker, guest_info);
+ /* RSDT is pointed to by RSDP */
+ build_rsdt(tables_blob, tables->linker, table_offsets);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
@ 2015-04-09 12:50 ` Alex Bennée
2015-04-09 13:17 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 12:50 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> RSDT points to other tables FADT, MADT, GTDT.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index a7aba75..85e84b1 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -176,6 +176,30 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> }
> }
>
> +/* RSDT */
> +static void
> +build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
> +{
> + AcpiRsdtDescriptorRev1 *rsdt;
> + size_t rsdt_len;
> + int i;
> +
> + rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
You should use explicit brackets to be unambiguous:
rsdt_len = sizeof(*rsdt) + (sizeof(uint32_t) * table_offsets->len);
> + rsdt = acpi_data_push(table_data, rsdt_len);
> + memcpy(rsdt->table_offset_entry, table_offsets->data,
> + sizeof(uint32_t) * table_offsets->len);
Or perhaps split the sizes:
const int table_data_len = (sizeof(uint32_t) * table_offsets->len);
rsdt_len = sizeof(*rsdt) + table_data_len;
rsdt = acpi_data_push(table_data, rsdt_len);
memcpy(rsdt->table_offset_entry, table_offsets->data, table_data_len)
Maybe?
> + for (i = 0; i < table_offsets->len; ++i) {
> + /* rsdt->table_offset_entry to be filled by Guest linker */
> + bios_linker_loader_add_pointer(linker,
> + ACPI_BUILD_TABLE_FILE,
> + ACPI_BUILD_TABLE_FILE,
> + table_data, &rsdt->table_offset_entry[i],
> + sizeof(uint32_t));
Why are these pointers always 32 bit? Can they ever be 64 bit?
> + }
> + build_header(linker, table_data,
> + (void *)rsdt, "RSDT", rsdt_len, 1);
> +}
> +
> /* GTDT */
> static void
> build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> @@ -348,6 +372,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_gtdt(tables_blob, tables->linker, guest_info);
>
> + /* RSDT is pointed to by RSDP */
> + build_rsdt(tables_blob, tables->linker, table_offsets);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 12:50 ` Alex Bennée
@ 2015-04-09 13:17 ` Igor Mammedov
2015-04-09 13:27 ` Peter Maydell
0 siblings, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 13:17 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Thu, 09 Apr 2015 13:50:52 +0100
Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >
> > RSDT points to other tables FADT, MADT, GTDT.
> >
> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> > ---
> > hw/arm/virt-acpi-build.c | 27 +++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > index a7aba75..85e84b1 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -176,6 +176,30 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> > }
> > }
> >
> > +/* RSDT */
> > +static void
> > +build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
this function looks like exact copy of x86 impl.,
could you reuse that?
> > +{
> > + AcpiRsdtDescriptorRev1 *rsdt;
> > + size_t rsdt_len;
> > + int i;
> > +
> > + rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
>
> You should use explicit brackets to be unambiguous:
>
> rsdt_len = sizeof(*rsdt) + (sizeof(uint32_t) * table_offsets->len);
>
> > + rsdt = acpi_data_push(table_data, rsdt_len);
> > + memcpy(rsdt->table_offset_entry, table_offsets->data,
> > + sizeof(uint32_t) * table_offsets->len);
>
> Or perhaps split the sizes:
>
> const int table_data_len = (sizeof(uint32_t) * table_offsets->len);
>
> rsdt_len = sizeof(*rsdt) + table_data_len;
> rsdt = acpi_data_push(table_data, rsdt_len);
> memcpy(rsdt->table_offset_entry, table_offsets->data, table_data_len)
>
> Maybe?
>
> > + for (i = 0; i < table_offsets->len; ++i) {
> > + /* rsdt->table_offset_entry to be filled by Guest linker */
> > + bios_linker_loader_add_pointer(linker,
> > + ACPI_BUILD_TABLE_FILE,
> > + ACPI_BUILD_TABLE_FILE,
> > + table_data, &rsdt->table_offset_entry[i],
> > + sizeof(uint32_t));
>
> Why are these pointers always 32 bit? Can they ever be 64 bit?
Laszlo, can you confirm that UEFI puts APCI tables below 4G address space?
>
> > + }
> > + build_header(linker, table_data,
> > + (void *)rsdt, "RSDT", rsdt_len, 1);
> > +}
> > +
> > /* GTDT */
> > static void
> > build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> > @@ -348,6 +372,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> > acpi_add_table(table_offsets, tables_blob);
> > build_gtdt(tables_blob, tables->linker, guest_info);
> >
> > + /* RSDT is pointed to by RSDP */
> > + build_rsdt(tables_blob, tables->linker, table_offsets);
> > +
> > /* Cleanup memory that's no longer used. */
> > g_array_free(table_offsets, true);
> > }
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 13:17 ` Igor Mammedov
@ 2015-04-09 13:27 ` Peter Maydell
2015-04-09 13:51 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2015-04-09 13:27 UTC (permalink / raw)
To: Igor Mammedov
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Mark Salter, Claudio Fontana, QEMU Developers, Laszlo Ersek,
Hanjun Guo, Shannon Zhao, Paolo Bonzini, Huangpeng (Peter),
Alex Bennée, Christoffer Dall, Shannon Zhao
On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
> On Thu, 09 Apr 2015 13:50:52 +0100
> Alex Bennée <alex.bennee@linaro.org> wrote:
>
>>
>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>> > + for (i = 0; i < table_offsets->len; ++i) {
>> > + /* rsdt->table_offset_entry to be filled by Guest linker */
>> > + bios_linker_loader_add_pointer(linker,
>> > + ACPI_BUILD_TABLE_FILE,
>> > + ACPI_BUILD_TABLE_FILE,
>> > + table_data, &rsdt->table_offset_entry[i],
>> > + sizeof(uint32_t));
>>
>> Why are these pointers always 32 bit? Can they ever be 64 bit?
> Laszlo, can you confirm that UEFI puts APCI tables below 4G address space?
In the general case you can't guarantee that there will
be any RAM at all below the 4G point. (The virt board
isn't like that, obviously, but I believe there's real
hardware out there that's designed that way.) I don't
think we should have any 32 bit assumptions in the
code at all -- pointer values should always be 64 bits
everywhere.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 13:27 ` Peter Maydell
@ 2015-04-09 13:51 ` Igor Mammedov
2015-04-09 13:59 ` Peter Maydell
0 siblings, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 13:51 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Shannon Zhao, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Alex Bennée, Hanjun Guo, Mark Salter, Paolo Bonzini,
Laszlo Ersek, Christoffer Dall, Shannon Zhao
On Thu, 9 Apr 2015 14:27:58 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
> > On Thu, 09 Apr 2015 13:50:52 +0100
> > Alex Bennée <alex.bennee@linaro.org> wrote:
> >
> >>
> >> Shannon Zhao <zhaoshenglong@huawei.com> writes:
> >> > + for (i = 0; i < table_offsets->len; ++i) {
> >> > + /* rsdt->table_offset_entry to be filled by Guest linker */
> >> > + bios_linker_loader_add_pointer(linker,
> >> > + ACPI_BUILD_TABLE_FILE,
> >> > + ACPI_BUILD_TABLE_FILE,
> >> > + table_data, &rsdt->table_offset_entry[i],
> >> > + sizeof(uint32_t));
> >>
> >> Why are these pointers always 32 bit? Can they ever be 64 bit?
> > Laszlo, can you confirm that UEFI puts APCI tables below 4G address space?
>
> In the general case you can't guarantee that there will
> be any RAM at all below the 4G point. (The virt board
> isn't like that, obviously, but I believe there's real
> hardware out there that's designed that way.) I don't
> think we should have any 32 bit assumptions in the
> code at all -- pointer values should always be 64 bits
> everywhere.
then that forces us to use xsdt instead of 32-bit rsdt
> -- PMM
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 13:51 ` Igor Mammedov
@ 2015-04-09 13:59 ` Peter Maydell
2015-04-09 14:43 ` Igor Mammedov
2015-04-09 16:00 ` Laszlo Ersek
0 siblings, 2 replies; 90+ messages in thread
From: Peter Maydell @ 2015-04-09 13:59 UTC (permalink / raw)
To: Igor Mammedov
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Shannon Zhao, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Alex Bennée, Hanjun Guo, Mark Salter, Paolo Bonzini,
Laszlo Ersek, Christoffer Dall, Shannon Zhao
On 9 April 2015 at 14:51, Igor Mammedov <imammedo@redhat.com> wrote:
> On Thu, 9 Apr 2015 14:27:58 +0100
> Peter Maydell <peter.maydell@linaro.org> wrote:
>
>> On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
>> > On Thu, 09 Apr 2015 13:50:52 +0100
>> > Alex Bennée <alex.bennee@linaro.org> wrote:
>> >
>> >>
>> >> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>> >> > + for (i = 0; i < table_offsets->len; ++i) {
>> >> > + /* rsdt->table_offset_entry to be filled by Guest linker */
>> >> > + bios_linker_loader_add_pointer(linker,
>> >> > + ACPI_BUILD_TABLE_FILE,
>> >> > + ACPI_BUILD_TABLE_FILE,
>> >> > + table_data, &rsdt->table_offset_entry[i],
>> >> > + sizeof(uint32_t));
>> >>
>> >> Why are these pointers always 32 bit? Can they ever be 64 bit?
>> > Laszlo, can you confirm that UEFI puts APCI tables below 4G address space?
>>
>> In the general case you can't guarantee that there will
>> be any RAM at all below the 4G point. (The virt board
>> isn't like that, obviously, but I believe there's real
>> hardware out there that's designed that way.) I don't
>> think we should have any 32 bit assumptions in the
>> code at all -- pointer values should always be 64 bits
>> everywhere.
>
> then that forces us to use xsdt instead of 32-bit rsdt
Does that matter much?
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 13:59 ` Peter Maydell
@ 2015-04-09 14:43 ` Igor Mammedov
2015-04-09 16:00 ` Laszlo Ersek
1 sibling, 0 replies; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 14:43 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Laszlo Ersek, Michael S. Tsirkin,
Alexander Spyridakis, Mark Salter, Claudio Fontana,
QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Shannon Zhao, Paolo Bonzini, Alex Bennée,
Christoffer Dall, Shannon Zhao
On Thu, 9 Apr 2015 14:59:09 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 9 April 2015 at 14:51, Igor Mammedov <imammedo@redhat.com> wrote:
> > On Thu, 9 Apr 2015 14:27:58 +0100
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> >> On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
> >> > On Thu, 09 Apr 2015 13:50:52 +0100
> >> > Alex Bennée <alex.bennee@linaro.org> wrote:
> >> >
> >> >>
> >> >> Shannon Zhao <zhaoshenglong@huawei.com> writes:
> >> >> > + for (i = 0; i < table_offsets->len; ++i) {
> >> >> > + /* rsdt->table_offset_entry to be filled by Guest linker */
> >> >> > + bios_linker_loader_add_pointer(linker,
> >> >> > + ACPI_BUILD_TABLE_FILE,
> >> >> > + ACPI_BUILD_TABLE_FILE,
> >> >> > + table_data, &rsdt->table_offset_entry[i],
> >> >> > + sizeof(uint32_t));
> >> >>
> >> >> Why are these pointers always 32 bit? Can they ever be 64 bit?
> >> > Laszlo, can you confirm that UEFI puts APCI tables below 4G address space?
> >>
> >> In the general case you can't guarantee that there will
> >> be any RAM at all below the 4G point. (The virt board
> >> isn't like that, obviously, but I believe there's real
> >> hardware out there that's designed that way.) I don't
> >> think we should have any 32 bit assumptions in the
> >> code at all -- pointer values should always be 64 bits
> >> everywhere.
> >
> > then that forces us to use xsdt instead of 32-bit rsdt
>
> Does that matter much?
not much, using rsdt would allow to share this code with x86.
also having tables below 4Gb in rsdt would make life of
32 bit guests easier, not that there are such guests now and may be
there wouldn't be any.
>
> -- PMM
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 13:59 ` Peter Maydell
2015-04-09 14:43 ` Igor Mammedov
@ 2015-04-09 16:00 ` Laszlo Ersek
2015-04-09 16:03 ` Peter Maydell
1 sibling, 1 reply; 90+ messages in thread
From: Laszlo Ersek @ 2015-04-09 16:00 UTC (permalink / raw)
To: Peter Maydell, Igor Mammedov
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Shannon Zhao, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Alex Bennée,
Christoffer Dall, Shannon Zhao
On 04/09/15 15:59, Peter Maydell wrote:
> On 9 April 2015 at 14:51, Igor Mammedov <imammedo@redhat.com> wrote:
>> On Thu, 9 Apr 2015 14:27:58 +0100
>> Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>>> On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
>>>> On Thu, 09 Apr 2015 13:50:52 +0100
>>>> Alex Bennée <alex.bennee@linaro.org> wrote:
>>>>
>>>>>
>>>>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>>>>> + for (i = 0; i < table_offsets->len; ++i) {
>>>>>> + /* rsdt->table_offset_entry to be filled by Guest linker */
>>>>>> + bios_linker_loader_add_pointer(linker,
>>>>>> + ACPI_BUILD_TABLE_FILE,
>>>>>> + ACPI_BUILD_TABLE_FILE,
>>>>>> + table_data, &rsdt->table_offset_entry[i],
>>>>>> + sizeof(uint32_t));
>>>>>
>>>>> Why are these pointers always 32 bit? Can they ever be 64 bit?
>>>> Laszlo, can you confirm that UEFI puts APCI tables below 4G address
>>>> space?
I confirmed that before, in the v2 discussion:
http://thread.gmane.org/gmane.comp.emulators.qemu/316670/focus=317560
But in fact the RSDT / XSDT that QEMU exports for UEFI doesn't matter.
See below.
>>> In the general case you can't guarantee that there will
>>> be any RAM at all below the 4G point. (The virt board
>>> isn't like that, obviously, but I believe there's real
>>> hardware out there that's designed that way.) I don't
>>> think we should have any 32 bit assumptions in the
>>> code at all -- pointer values should always be 64 bits
>>> everywhere.
>>
>> then that forces us to use xsdt instead of 32-bit rsdt
>
> Does that matter much?
I can mention two points here.
(1) See this kernel patch:
http://thread.gmane.org/gmane.linux.acpi.devel/74369/focus=1915858
> +The ACPI core will ignore any provided RSDT (Root System Description Table).
> +RSDTs have been deprecated and are ignored on arm64 since they only allow
> +for 32-bit addresses.
So you could argue that providing an XSDT instead of an RSDT is
justified by this alone.
(2) the ACPI linker/loader client in edk2 (used for both OVMF and AAVMF)
*does* restrict initial allocations to under 4GB. This is a super hairy
subject, but I'll try to summarize it quickly.
The ACPI linker/loader interface was originally designed for SeaBIOS.
The central structure of the interface is a command table, which
contains three kinds of commands:
(a) "allocate blob" (which includes "download blob" as well),
(b) "relocate pointer" (also known as "update pointer"), and
(c) "checksum blob segment".
Importantly, the "allocate" command comes with allocation hints; it can
instruct the firmware to allocate the blob in some specific zone.
So, the general process (as designed) is something like this:
- The firmware allocates and downloads the blobs -- the allocate
commands always come first in the table. Each blob can contain several
ACPI tables, in any kind of arrangement.
- Then the "relocate pointer" commands are processed (simply because
they come later in the command table, that's guaranteed), which update
pointers in some tables (residing in some blobs) to some other tables
(residing in some other, or the same, blob(s)). In more detail, the
pointers in the tables in the blobs are pre-initialized with relative
offsets (into other blobs), and the relocation means that these
relative offsets are made absolute -- they are incremented with the
actual allocation base addresses that are the results of the
allocation command processing (see previous step).
- Finally (in fact, intermixed with "relocate pointer" commands),
checksums are updated.
The idea is that after the initial allocations, everything is processed
*in place*. (This is what SeaBIOS does.) Because pointer fields, updated
by the "relocate pointer" commands (which basically mean increments by
actual blob base addresses) can come in various sizes (1, 2, 4, 8
bytes), the allocation commands must take care to instruct the firmware
to allocate the "target" blobs "low enough" so that the referring
pointers can accommodate these actual base addresses.
All fine; again, SeaBIOS does exactly this; the important thing to note
is that everything is processed, and then left for the runtime OS, *in
place*.
And then UEFI / edk2 came along. :)
The problem with UEFI is that you are not supposed to just throw a bunch
of binary stuff into RAM. Instead, the RSD PTR table needs to be linked
into the UEFI system config table, plus each table needs to be installed
*individually*, by passing it to EFI_ACPI_TABLE_PROTOCOL.InstallTable().
The first requirement is actually a relaxation -- the RSD PTR can be
anywhere in memory, it doesn't need to be low. However, the second
requirement is a huge pain, because it doesn't match the design of the
ACPI linker/loader interface. EFI_ACPI_TABLE_PROTOCOL is "smart" about
the specification, and knows what to allocate where -- it copies tables,
links the copies together, checksums them, handles the RSD PTR
internally, and so on; but it does need to *receive* tables
individually.
So, what the OVMF (and AAVMF) code does is: we first implement the above
algorithm, but only as a first pass. (*) Once we're done with that, we
process the "relocate pointer" commands in a second pass, the idea being
that wherever these pointers point *to*, after the first pass, those
things must be actual ACPI tables, *or* operation regions.
Therefore, we check the targets of these pointers, and if the target
looks like an ACPI table (has the appropriate header, checksum is okay
etc -- it's heuristical, yes), then we pass it to
EFI_ACPI_TABLE_PROTOCOL.InstallTable(). Otherwise, the target area is
considered an operation region referenced by some other ACPI table, and
then the hosting *blob* is marked as "this blob hosts something else
than *just* ACPI tables".
Finally, after the second pass, we check our blobs -- each blob that is
left marked as "hosts *only* ACPI tables" is released (because those
tables have been installed already, individually), and the rest of the
blobs are preserved in-place. These could be considered "leaked" to some
extent, because any ACPI tables in those blobs *have* been installed
(deeply copied and linked). Nevertheless, we can't do any better than
keep the full blob even if it hosts only one non-ACPI-table "thing" (ie.
an operation region).
(*) I'll note here that the first pass in edk2 is extremely careful; it
checks *everything* about pointer arithmetic. And, indeed, that has
caught errors in Shannon's v1 submission.
Okay, with the above wall of text out of the way, why is it relevant? It
is relevant for several points:
- whether you provide an RSDT or an XSDT, it won't matter, because OVMF
& AAVMF skip both of those tables, intentionally. They are handled
automatically by EFI_ACPI_TABLE_PROTOCOL.
- The allocation (and alignment) hints in the "allocate & download blob"
command do not map to UEFI cleanly:
- BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG is both nonsensical and
unnecessary for UEFI: Allocating in the F segment would be important
for RSD PTR in the BIOS case only, but under UEFI, RSD PTR is
located differently (see above). So this hint is simply ignored.
- BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH just means "allocate up to 4GB"
(for BIOS).
- the alignment hint can request any power of two.
Now, the UEFI memory allocation services can only accommodate a subset
of all the possible *combinations* of the last two points. Staying under
4GB is important in the first pass, because SeaBIOS simply wouldn't
allocate blobs higher than that (even with
BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH), and we need to be prepared for
permanently preserving a blob that hosts an operation region. If I
allowed edk2 to allocate a blob anywhere at all in the first pass, given
BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH, then I could run into a situation
where I can't relocate a 4-byte wide pointer *into* that blob. And, I
couldn't even do the relocation temporarily in a UINT64 (just stashing
it for pass 2), because the target area might be an operation region
(not an ACPI table), which would have to remain in place after pass 2,
*and* be referenced by the relocated, 4-byte wide pointer.
So, allocating under 4GB is a requirement, and the memory allocation
services in UEFI do allow me to request such a top address. But that
service (gBS->AllocatePages(), to be exact) *also* implies that the
allocations will be aligned to 4KB exactly -- no lower and no higher
granularities are guaranteed. Therefore in edk2 we check the alignment
hint as well, and as long as it does not *exceed* 4KB, we silently
succeed. If the alignment hint wants something bigger than 4KB, we abort
the first pass. (This has never happened yet.)
Summary:
- it doesn't matter if you give UEFI an RSDT or an XSDT, it'll ignore
either anyway (beyond processing the opaque "relocate pointer"
commands that happen to reference these tables, of course) --
EFI_ACPI_TABLE_PROTOCOL will create and populate these tables
automatically.
- the described edk2 code, as-is, will fail on platforms where there is
no system RAM under 4GB -- gracefully, but certainly
- The 4GB limit will permanently affect operation regions *only*. For
ACPI tables hosted in the blobs, the 4GB limit is just a temporary
limit, until the second pass completes; EFI_ACPI_TABLE_PROTOCOL will
put their copies wherever they belong, even above 4GB if possible.
Basically, the current ACPI linker/loader interface comes with the
silent assumption:
any 4-byte pointer can be successfully relocated to a
BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH blob
This assumption is automatically satisfied by SeaBIOS, but edk2 needs to
ensure it specifically, and it does.
Therefore it doesn't matter if you push down an RSDT (with 4-byte
pointer entries) or an XSDT (with 8-byte pointer entries); the "relocate
pointer" commands that happen to modify either will *always* succeed in
the first pass (as long as the relative offsets are valid) -- the target
base addresses will never exceed 4GB.
If, however, even the above "mostly temporary" 4GB limit should be
lifted, then two things are necessary:
- an XSDT must be pushed down (so that the first pass relocations
succeed, regardless of actual blob base addresses),
- a new allocation hint is necessary (in the "allocate blob" command),
so that edk2 knows it is safe to allocate the blob anywhere at all
(ie. only 8-byte pointers will be referencing it).
... I hope you guys enjoyed this. :)
Laszlo
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 16:00 ` Laszlo Ersek
@ 2015-04-09 16:03 ` Peter Maydell
2015-04-09 16:21 ` Laszlo Ersek
0 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2015-04-09 16:03 UTC (permalink / raw)
To: Laszlo Ersek
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Shannon Zhao, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Paolo Bonzini, Hanjun Guo, Mark Salter, Igor Mammedov,
Alex Bennée, Christoffer Dall, Shannon Zhao
On 9 April 2015 at 17:00, Laszlo Ersek <lersek@redhat.com> wrote:
> On 04/09/15 15:59, Peter Maydell wrote:
>> On 9 April 2015 at 14:51, Igor Mammedov <imammedo@redhat.com> wrote:
>>> On Thu, 9 Apr 2015 14:27:58 +0100
>>> Peter Maydell <peter.maydell@linaro.org> wrote:
>>>
>>>> On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
>>>>> On Thu, 09 Apr 2015 13:50:52 +0100
>>>>> Alex Bennée <alex.bennee@linaro.org> wrote:
>>>>>
>>>>>>
>>>>>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>>>>>> + for (i = 0; i < table_offsets->len; ++i) {
>>>>>>> + /* rsdt->table_offset_entry to be filled by Guest linker */
>>>>>>> + bios_linker_loader_add_pointer(linker,
>>>>>>> + ACPI_BUILD_TABLE_FILE,
>>>>>>> + ACPI_BUILD_TABLE_FILE,
>>>>>>> + table_data, &rsdt->table_offset_entry[i],
>>>>>>> + sizeof(uint32_t));
>>>>>>
>>>>>> Why are these pointers always 32 bit? Can they ever be 64 bit?
>>>>> Laszlo, can you confirm that UEFI puts APCI tables below 4G address
>>>>> space?
>
> I confirmed that before, in the v2 discussion:
>
> http://thread.gmane.org/gmane.comp.emulators.qemu/316670/focus=317560
>
> But in fact the RSDT / XSDT that QEMU exports for UEFI doesn't matter.
If this table is never used, presumably we should just
not generate it at all, then?
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table
2015-04-09 16:03 ` Peter Maydell
@ 2015-04-09 16:21 ` Laszlo Ersek
0 siblings, 0 replies; 90+ messages in thread
From: Laszlo Ersek @ 2015-04-09 16:21 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Shannon Zhao, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Paolo Bonzini, Hanjun Guo, Mark Salter, Igor Mammedov,
Alex Bennée, Christoffer Dall, Shannon Zhao
On 04/09/15 18:03, Peter Maydell wrote:
> On 9 April 2015 at 17:00, Laszlo Ersek <lersek@redhat.com> wrote:
>> On 04/09/15 15:59, Peter Maydell wrote:
>>> On 9 April 2015 at 14:51, Igor Mammedov <imammedo@redhat.com> wrote:
>>>> On Thu, 9 Apr 2015 14:27:58 +0100
>>>> Peter Maydell <peter.maydell@linaro.org> wrote:
>>>>
>>>>> On 9 April 2015 at 14:17, Igor Mammedov <imammedo@redhat.com> wrote:
>>>>>> On Thu, 09 Apr 2015 13:50:52 +0100
>>>>>> Alex Bennée <alex.bennee@linaro.org> wrote:
>>>>>>
>>>>>>>
>>>>>>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>>>>>>> + for (i = 0; i < table_offsets->len; ++i) {
>>>>>>>> + /* rsdt->table_offset_entry to be filled by Guest linker */
>>>>>>>> + bios_linker_loader_add_pointer(linker,
>>>>>>>> + ACPI_BUILD_TABLE_FILE,
>>>>>>>> + ACPI_BUILD_TABLE_FILE,
>>>>>>>> + table_data, &rsdt->table_offset_entry[i],
>>>>>>>> + sizeof(uint32_t));
>>>>>>>
>>>>>>> Why are these pointers always 32 bit? Can they ever be 64 bit?
>>>>>> Laszlo, can you confirm that UEFI puts APCI tables below 4G address
>>>>>> space?
>>
>> I confirmed that before, in the v2 discussion:
>>
>> http://thread.gmane.org/gmane.comp.emulators.qemu/316670/focus=317560
>>
>> But in fact the RSDT / XSDT that QEMU exports for UEFI doesn't matter.
>
> If this table is never used, presumably we should just
> not generate it at all, then?
Unfortunately, this is not the case. In order to identify ACPI tables *at all* in UEFI, I need "relocate pointer" commands for pointers that point to those tables. And those pointers must *reside* somewhere, in some blob.
Here's how the "relocate pointer" command is defined in edk2 (OvmfPkg/AcpiPlatformDxe/QemuLoader.h):
//
// QemuLoaderCmdAddPointer: the bytes at
// [PointerOffset..PointerOffset+PointerSize) in the file PointerFile contain a
// relative pointer (an offset) into PointeeFile. Increment the relative
// pointer's value by the base address of where PointeeFile's contents have
// been placed (when QemuLoaderCmdAllocate has been executed for PointeeFile).
//
typedef struct {
UINT8 PointerFile[QEMU_LOADER_FNAME_SIZE]; // NUL-terminated
UINT8 PointeeFile[QEMU_LOADER_FNAME_SIZE]; // NUL-terminated
UINT32 PointerOffset;
UINT8 PointerSize; // one of 1, 2, 4, 8
} QEMU_LOADER_ADD_POINTER;
In the qemu tree, see COMMAND_ADD_POINTER in "hw/acpi/bios-linker-loader.c", for the same. (I rewrote the types and the comments in edk2 from scratch, both for coding style reasons and for clearer documentation.)
... To be clear: the top-level pointers must exist somewhere (in some blob), because that helps edk2 find the tables (in some other blobs). However, the top-level pointers themselves don't need to reside in any ACPI table (RSDT, XSDT); they can just live in an otherwise unreferenced portion of one of the blobs.
But, IMO, implementing that wouldn't be much easier (and it would certainly be uglier) than composing a correct RSDT or XSDT. The latter would also keep the similarity with the x86 SeaBIOS case (where the RSDT is a hard requirement).
Thanks
Laszlo
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 11/20] hw/arm/virt-acpi-build: Generate RSDP table
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (9 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 10/20] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 14:45 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table Shannon Zhao
` (10 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
RSDP points to RSDT which in turn points to other tables.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 85e84b1..dd5538b 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -176,6 +176,35 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
}
}
+/* RSDP */
+static GArray *
+build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
+{
+ AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
+
+ bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
+ true /* fseg memory */);
+
+ memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
+ memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
+ rsdp->length = cpu_to_le32(sizeof(*rsdp));
+ rsdp->revision = 0x02;
+
+ /* Point to RSDT */
+ rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
+ /* Address to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ rsdp_table, &rsdp->rsdt_physical_address,
+ sizeof rsdp->rsdt_physical_address);
+ rsdp->checksum = 0;
+ /* Checksum to be filled by Guest linker */
+ bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
+ rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
+
+ return rsdp_table;
+}
+
/* RSDT */
static void
build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
@@ -336,7 +365,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
- unsigned dsdt;
+ unsigned dsdt, rsdt;
VirtAcpiCpuInfo cpuinfo;
GArray *tables_blob = tables->table_data;
@@ -373,8 +402,12 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
build_gtdt(tables_blob, tables->linker, guest_info);
/* RSDT is pointed to by RSDP */
+ rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
+ /* RSDP is in FSEG memory, so allocate it separately */
+ build_rsdp(tables->rsdp, tables->linker, rsdt);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 11/20] hw/arm/virt-acpi-build: Generate RSDP table
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 11/20] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
@ 2015-04-09 14:45 ` Alex Bennée
0 siblings, 0 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 14:45 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> RSDP points to RSDT which in turn points to other tables.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 35 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 85e84b1..dd5538b 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -176,6 +176,35 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> }
> }
>
> +/* RSDP */
> +static GArray *
> +build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> +{
> + AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
> +
> + bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
> + true /* fseg memory */);
> +
> + memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
> + memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
> + rsdp->length = cpu_to_le32(sizeof(*rsdp));
> + rsdp->revision = 0x02;
> +
> + /* Point to RSDT */
> + rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
> + /* Address to be filled by Guest linker */
> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
> + ACPI_BUILD_TABLE_FILE,
> + rsdp_table, &rsdp->rsdt_physical_address,
> + sizeof rsdp->rsdt_physical_address);
> + rsdp->checksum = 0;
> + /* Checksum to be filled by Guest linker */
> + bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
> + rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
> +
> + return rsdp_table;
> +}
> +
> /* RSDT */
> static void
> build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
> @@ -336,7 +365,7 @@ static
> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> - unsigned dsdt;
> + unsigned dsdt, rsdt;
> VirtAcpiCpuInfo cpuinfo;
> GArray *tables_blob = tables->table_data;
>
> @@ -373,8 +402,12 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> build_gtdt(tables_blob, tables->linker, guest_info);
>
> /* RSDT is pointed to by RSDP */
> + rsdt = tables_blob->len;
> build_rsdt(tables_blob, tables->linker, table_offsets);
>
> + /* RSDP is in FSEG memory, so allocate it separately */
> + build_rsdp(tables->rsdp, tables->linker, rsdt);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (10 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 11/20] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 15:54 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
` (9 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add PCIe info struct, prepare for building PCIe table.
And generate MCFG table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 21 +++++++++++++++++++++
include/hw/arm/virt-acpi-build.h | 12 ++++++++++++
2 files changed, 33 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index dd5538b..a979582 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -229,6 +229,24 @@ build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
(void *)rsdt, "RSDT", rsdt_len, 1);
}
+static void
+build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ AcpiTableMcfg *mcfg;
+ acpi_pcie_info *info = guest_info->pcie_info;
+ int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
+
+ mcfg = acpi_data_push(table_data, len);
+ mcfg->allocation[0].address = cpu_to_le64(info->pcie_ecam_base);
+
+ /* Only a single allocation so no need to play with segments */
+ mcfg->allocation[0].pci_segment = cpu_to_le16(0);
+ mcfg->allocation[0].start_bus_number = 0;
+ mcfg->allocation[0].end_bus_number = info->nr_pcie_buses - 1;
+
+ build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1);
+}
+
/* GTDT */
static void
build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -401,6 +419,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker, guest_info);
+ acpi_add_table(table_offsets, tables_blob);
+ build_mcfg(tables_blob, tables->linker, guest_info);
+
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
index 2780856..d534489 100644
--- a/include/hw/arm/virt-acpi-build.h
+++ b/include/hw/arm/virt-acpi-build.h
@@ -47,6 +47,17 @@ typedef struct acpi_dsdt_info {
const hwaddr *flash_addr;
} acpi_dsdt_info;
+typedef struct acpi_pcie_info {
+ const int *pcie_irq;
+ hwaddr pcie_mmio_base;
+ hwaddr pcie_mmio_size;
+ hwaddr pcie_ioport_base;
+ hwaddr pcie_ioport_size;
+ hwaddr pcie_ecam_base;
+ hwaddr pcie_ecam_size;
+ int nr_pcie_buses;
+} acpi_pcie_info;
+
typedef struct VirtGuestInfo {
int smp_cpus;
int max_cpus;
@@ -54,6 +65,7 @@ typedef struct VirtGuestInfo {
acpi_madt_info *madt_info;
acpi_dsdt_info *dsdt_info;
acpi_gtdt_info *gtdt_info;
+ acpi_pcie_info *pcie_info;
} VirtGuestInfo;
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table Shannon Zhao
@ 2015-04-09 15:54 ` Alex Bennée
2015-04-09 16:00 ` Peter Maydell
0 siblings, 1 reply; 90+ messages in thread
From: Alex Bennée @ 2015-04-09 15:54 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add PCIe info struct, prepare for building PCIe table.
> And generate MCFG table.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 21 +++++++++++++++++++++
> include/hw/arm/virt-acpi-build.h | 12 ++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index dd5538b..a979582 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -229,6 +229,24 @@ build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
> (void *)rsdt, "RSDT", rsdt_len, 1);
> }
>
> +static void
> +build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> +{
> + AcpiTableMcfg *mcfg;
> + acpi_pcie_info *info = guest_info->pcie_info;
> + int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
Explicit bracketing around the maths please.
> +
> + mcfg = acpi_data_push(table_data, len);
> + mcfg->allocation[0].address = cpu_to_le64(info->pcie_ecam_base);
> +
> + /* Only a single allocation so no need to play with segments */
> + mcfg->allocation[0].pci_segment = cpu_to_le16(0);
> + mcfg->allocation[0].start_bus_number = 0;
> + mcfg->allocation[0].end_bus_number = info->nr_pcie_buses - 1;
> +
> + build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1);
> +}
> +
> /* GTDT */
> static void
> build_gtdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> @@ -401,6 +419,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_gtdt(tables_blob, tables->linker, guest_info);
>
> + acpi_add_table(table_offsets, tables_blob);
> + build_mcfg(tables_blob, tables->linker, guest_info);
> +
> /* RSDT is pointed to by RSDP */
> rsdt = tables_blob->len;
> build_rsdt(tables_blob, tables->linker, table_offsets);
> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
> index 2780856..d534489 100644
> --- a/include/hw/arm/virt-acpi-build.h
> +++ b/include/hw/arm/virt-acpi-build.h
> @@ -47,6 +47,17 @@ typedef struct acpi_dsdt_info {
> const hwaddr *flash_addr;
> } acpi_dsdt_info;
>
> +typedef struct acpi_pcie_info {
> + const int *pcie_irq;
> + hwaddr pcie_mmio_base;
> + hwaddr pcie_mmio_size;
> + hwaddr pcie_ioport_base;
> + hwaddr pcie_ioport_size;
> + hwaddr pcie_ecam_base;
> + hwaddr pcie_ecam_size;
> + int nr_pcie_buses;
> +} acpi_pcie_info;
> +
> typedef struct VirtGuestInfo {
> int smp_cpus;
> int max_cpus;
> @@ -54,6 +65,7 @@ typedef struct VirtGuestInfo {
> acpi_madt_info *madt_info;
> acpi_dsdt_info *dsdt_info;
> acpi_gtdt_info *gtdt_info;
> + acpi_pcie_info *pcie_info;
> } VirtGuestInfo;
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
2015-04-09 15:54 ` Alex Bennée
@ 2015-04-09 16:00 ` Peter Maydell
2015-04-10 6:04 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2015-04-09 16:00 UTC (permalink / raw)
To: Alex Bennée
Cc: Mark Salter, hangaohuai, Igor Mammedov, Alexander Spyridakis,
Michael S. Tsirkin, Claudio Fontana, QEMU Developers,
Huangpeng (Peter),
Hanjun Guo, Shannon Zhao, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 9 April 2015 at 16:54, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>> +build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>> +{
>> + AcpiTableMcfg *mcfg;
>> + acpi_pcie_info *info = guest_info->pcie_info;
>> + int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
>
> Explicit bracketing around the maths please.
This doesn't seem to make much sense anyway:
if the addition was intended to take precedence
then we're adding 1 to a size-of-a-struct, which is
a bit weird. And if the multiplication was intended
to take precedence then it's doing a pointless multiply
by one. Please can you check that this is actually
calculating the right value?
thanks
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
2015-04-09 16:00 ` Peter Maydell
@ 2015-04-10 6:04 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 6:04 UTC (permalink / raw)
To: Peter Maydell, Alex Bennée
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Mark Salter, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Igor Mammedov, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 2015/4/10 0:00, Peter Maydell wrote:
> On 9 April 2015 at 16:54, Alex Bennée <alex.bennee@linaro.org> wrote:
>> >
>> > Shannon Zhao <zhaoshenglong@huawei.com> writes:
>> >
>>> >> From: Shannon Zhao <shannon.zhao@linaro.org>
>>> >> +build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>>> >> +{
>>> >> + AcpiTableMcfg *mcfg;
>>> >> + acpi_pcie_info *info = guest_info->pcie_info;
>>> >> + int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
>> >
>> > Explicit bracketing around the maths please.
> This doesn't seem to make much sense anyway:
> if the addition was intended to take precedence
> then we're adding 1 to a size-of-a-struct, which is
> a bit weird. And if the multiplication was intended
> to take precedence then it's doing a pointless multiply
> by one. Please can you check that this is actually
> calculating the right value?
The 1 means here only a single allocation for use.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (11 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 12/20] hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 13:22 ` Igor Mammedov
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
` (8 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add ToUUID macro, this is useful for generating PCIe ACPI table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 23 +++++++++++++++++++++++
include/hw/acpi/aml-build.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index bd1713c..5a94fc9 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -933,6 +933,29 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
addr_trans, len, flags);
}
+/*
+ * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
+ * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
+ * call aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117, 0xEA4D19C3434D);
+ */
+Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
+ int16_t val4, int64_t val5)
+{
+ int i;
+ Aml *UUID = aml_buffer();
+
+ build_append_int_noprefix(UUID->buf, val1, 4);
+ build_append_int_noprefix(UUID->buf, val2, 2);
+ build_append_int_noprefix(UUID->buf, val3, 2);
+ build_append_int_noprefix(UUID->buf, (val4 >> 8) & 0xFF, 1);
+ build_append_int_noprefix(UUID->buf, val4 & 0xFF, 1);
+ for (i = 40; i >= 0; i -= 8) {
+ build_append_int_noprefix(UUID->buf, (val5 >> i) & 0xFF, 1);
+ }
+
+ return UUID;
+}
+
void
build_header(GArray *linker, GArray *table_data,
AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 315c729..942d986 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -209,6 +209,8 @@ Aml *aml_buffer(void);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
Aml *aml_varpackage(uint32_t num_elements);
+Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
+ int16_t val4, int64_t val5);
void
build_header(GArray *linker, GArray *table_data,
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
@ 2015-04-09 13:22 ` Igor Mammedov
2015-04-10 6:10 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 13:22 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Fri, 3 Apr 2015 18:03:45 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add ToUUID macro, this is useful for generating PCIe ACPI table.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 23 +++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 2 ++
> 2 files changed, 25 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index bd1713c..5a94fc9 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -933,6 +933,29 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
> addr_trans, len, flags);
> }
>
> +/*
> + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
> + * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> + * call aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117, 0xEA4D19C3434D);
hmm, ^^^^ that's definitely no string
> + */
> +Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
> + int16_t val4, int64_t val5)
> +{
> + int i;
> + Aml *UUID = aml_buffer();
> +
> + build_append_int_noprefix(UUID->buf, val1, 4);
> + build_append_int_noprefix(UUID->buf, val2, 2);
> + build_append_int_noprefix(UUID->buf, val3, 2);
> + build_append_int_noprefix(UUID->buf, (val4 >> 8) & 0xFF, 1);
> + build_append_int_noprefix(UUID->buf, val4 & 0xFF, 1);
> + for (i = 40; i >= 0; i -= 8) {
> + build_append_int_noprefix(UUID->buf, (val5 >> i) & 0xFF, 1);
> + }
> +
> + return UUID;
> +}
> +
> void
> build_header(GArray *linker, GArray *table_data,
> AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 315c729..942d986 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -209,6 +209,8 @@ Aml *aml_buffer(void);
> Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlFieldFlags flags);
> Aml *aml_varpackage(uint32_t num_elements);
> +Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
> + int16_t val4, int64_t val5);
>
> void
> build_header(GArray *linker, GArray *table_data,
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-09 13:22 ` Igor Mammedov
@ 2015-04-10 6:10 ` Shannon Zhao
2015-04-10 7:40 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 6:10 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/9 21:22, Igor Mammedov wrote:
> On Fri, 3 Apr 2015 18:03:45 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> > From: Shannon Zhao <shannon.zhao@linaro.org>
>> >
>> > Add ToUUID macro, this is useful for generating PCIe ACPI table.
>> >
>> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> > hw/acpi/aml-build.c | 23 +++++++++++++++++++++++
>> > include/hw/acpi/aml-build.h | 2 ++
>> > 2 files changed, 25 insertions(+)
>> >
>> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> > index bd1713c..5a94fc9 100644
>> > --- a/hw/acpi/aml-build.c
>> > +++ b/hw/acpi/aml-build.c
>> > @@ -933,6 +933,29 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
>> > addr_trans, len, flags);
>> > }
>> >
>> > +/*
>> > + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
>> > + * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
>> > + * call aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117, 0xEA4D19C3434D);
> hmm, ^^^^ that's definitely no string
>
Yes, the args are not string. When I implemented this function I thought about this.
In order to make it simple, I use HEX here. If we have to use string, I could modify this.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro
2015-04-10 6:10 ` Shannon Zhao
@ 2015-04-10 7:40 ` Igor Mammedov
0 siblings, 0 replies; 90+ messages in thread
From: Igor Mammedov @ 2015-04-10 7:40 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Fri, 10 Apr 2015 14:10:08 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/9 21:22, Igor Mammedov wrote:
> > On Fri, 3 Apr 2015 18:03:45 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >> >
> >> > Add ToUUID macro, this is useful for generating PCIe ACPI table.
> >> >
> >> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> > ---
> >> > hw/acpi/aml-build.c | 23 +++++++++++++++++++++++
> >> > include/hw/acpi/aml-build.h | 2 ++
> >> > 2 files changed, 25 insertions(+)
> >> >
> >> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >> > index bd1713c..5a94fc9 100644
> >> > --- a/hw/acpi/aml-build.c
> >> > +++ b/hw/acpi/aml-build.c
> >> > @@ -933,6 +933,29 @@ Aml *aml_qword_memory(AmlDecode dec,
> >> > AmlMinFixed min_fixed, addr_trans, len, flags);
> >> > }
> >> >
> >> > +/*
> >> > + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
> >> > + * e.g. UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> >> > + * call aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117,
> >> > 0xEA4D19C3434D);
> > hmm, ^^^^ that's definitely no string
> >
> Yes, the args are not string. When I implemented this function I
> thought about this. In order to make it simple, I use HEX here. If we
> have to use string, I could modify this.
I'd prefer stirngs as it's written in spec
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (12 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 13/20] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-09 13:35 ` Igor Mammedov
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
` (7 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_or() term and make aml_and can take three args.
Expose build_append_int_noprefix as it wiil be used by
creating a buffer.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 24 +++++++++++++++++++++---
hw/i386/acpi-build.c | 2 +-
include/hw/acpi/aml-build.h | 4 +++-
3 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 5a94fc9..312afb6 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -240,7 +240,7 @@ static void build_extop_package(GArray *package, uint8_t op)
build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
}
-static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
+void build_append_int_noprefix(GArray *table, uint64_t value, int size)
{
int i;
@@ -445,12 +445,30 @@ Aml *aml_store(Aml *val, Aml *target)
}
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
-Aml *aml_and(Aml *arg1, Aml *arg2)
+Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3)
{
Aml *var = aml_opcode(0x7B /* AndOp */);
aml_append(var, arg1);
aml_append(var, arg2);
- build_append_byte(var->buf, 0x00 /* NullNameOp */);
+ if (arg3 == NULL) {
+ build_append_byte(var->buf, 0x00 /* NullNameOp */);
+ } else {
+ aml_append(var, arg3);
+ }
+ return var;
+}
+
+/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
+Aml *aml_or(Aml *arg1, Aml *arg2, Aml *arg3)
+{
+ Aml *var = aml_opcode(0x7D /* OrOp */);
+ aml_append(var, arg1);
+ aml_append(var, arg2);
+ if (arg3 == NULL) {
+ build_append_byte(var->buf, 0x00 /* NullNameOp */);
+ } else {
+ aml_append(var, arg3);
+ }
return var;
}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 7b5210e..133685e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -452,7 +452,7 @@ static void build_append_pcihp_notify_entry(Aml *method, int slot)
Aml *if_ctx;
int32_t devfn = PCI_DEVFN(slot, 0);
- if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot)));
+ if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
aml_append(method, if_ctx);
}
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 942d986..3473d6e 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -156,7 +156,8 @@ Aml *aml_return(Aml *val);
Aml *aml_int(const uint64_t val);
Aml *aml_arg(int pos);
Aml *aml_store(Aml *val, Aml *target);
-Aml *aml_and(Aml *arg1, Aml *arg2);
+Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3);
+Aml *aml_or(Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_notify(Aml *arg1, Aml *arg2);
Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
@@ -211,6 +212,7 @@ Aml *aml_field(const char *name, AmlFieldFlags flags);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
int16_t val4, int64_t val5);
+void build_append_int_noprefix(GArray *table, uint64_t value, int size);
void
build_header(GArray *linker, GArray *table_data,
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
@ 2015-04-09 13:35 ` Igor Mammedov
2015-04-10 6:15 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-09 13:35 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Fri, 3 Apr 2015 18:03:46 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add aml_or() term and make aml_and can take three args.
> Expose build_append_int_noprefix as it wiil be used by
> creating a buffer.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/acpi/aml-build.c | 24 +++++++++++++++++++++---
> hw/i386/acpi-build.c | 2 +-
> include/hw/acpi/aml-build.h | 4 +++-
> 3 files changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 5a94fc9..312afb6 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -240,7 +240,7 @@ static void build_extop_package(GArray *package, uint8_t op)
> build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
> }
>
> -static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
> +void build_append_int_noprefix(GArray *table, uint64_t value, int size)
> {
> int i;
>
> @@ -445,12 +445,30 @@ Aml *aml_store(Aml *val, Aml *target)
> }
>
> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
> -Aml *aml_and(Aml *arg1, Aml *arg2)
> +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3)
I know that it's possible to Store inside of And(a, b, save_here) ASL op,
but could you instead rewrite it to
Store(And(a, b), save_here)
so it wouldn't clatter trivial And(a,b) uses and drop this hunk.
> {
> Aml *var = aml_opcode(0x7B /* AndOp */);
> aml_append(var, arg1);
> aml_append(var, arg2);
> - build_append_byte(var->buf, 0x00 /* NullNameOp */);
> + if (arg3 == NULL) {
> + build_append_byte(var->buf, 0x00 /* NullNameOp */);
> + } else {
> + aml_append(var, arg3);
> + }
> + return var;
> +}
> +
> +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
> +Aml *aml_or(Aml *arg1, Aml *arg2, Aml *arg3)
same here for arg3
> +{
> + Aml *var = aml_opcode(0x7D /* OrOp */);
> + aml_append(var, arg1);
> + aml_append(var, arg2);
> + if (arg3 == NULL) {
> + build_append_byte(var->buf, 0x00 /* NullNameOp */);
> + } else {
> + aml_append(var, arg3);
> + }
> return var;
> }
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 7b5210e..133685e 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -452,7 +452,7 @@ static void build_append_pcihp_notify_entry(Aml *method, int slot)
> Aml *if_ctx;
> int32_t devfn = PCI_DEVFN(slot, 0);
>
> - if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot)));
> + if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
> aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
> aml_append(method, if_ctx);
> }
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 942d986..3473d6e 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -156,7 +156,8 @@ Aml *aml_return(Aml *val);
> Aml *aml_int(const uint64_t val);
> Aml *aml_arg(int pos);
> Aml *aml_store(Aml *val, Aml *target);
> -Aml *aml_and(Aml *arg1, Aml *arg2);
> +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3);
> +Aml *aml_or(Aml *arg1, Aml *arg2, Aml *arg3);
> Aml *aml_notify(Aml *arg1, Aml *arg2);
> Aml *aml_call1(const char *method, Aml *arg1);
> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> @@ -211,6 +212,7 @@ Aml *aml_field(const char *name, AmlFieldFlags flags);
> Aml *aml_varpackage(uint32_t num_elements);
> Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
> int16_t val4, int64_t val5);
> +void build_append_int_noprefix(GArray *table, uint64_t value, int size);
>
> void
> build_header(GArray *linker, GArray *table_data,
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-09 13:35 ` Igor Mammedov
@ 2015-04-10 6:15 ` Shannon Zhao
2015-04-10 7:46 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 6:15 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/9 21:35, Igor Mammedov wrote:
> On Fri, 3 Apr 2015 18:03:46 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> > From: Shannon Zhao <shannon.zhao@linaro.org>
>> >
>> > Add aml_or() term and make aml_and can take three args.
>> > Expose build_append_int_noprefix as it wiil be used by
>> > creating a buffer.
>> >
>> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> > hw/acpi/aml-build.c | 24 +++++++++++++++++++++---
>> > hw/i386/acpi-build.c | 2 +-
>> > include/hw/acpi/aml-build.h | 4 +++-
>> > 3 files changed, 25 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> > index 5a94fc9..312afb6 100644
>> > --- a/hw/acpi/aml-build.c
>> > +++ b/hw/acpi/aml-build.c
>> > @@ -240,7 +240,7 @@ static void build_extop_package(GArray *package, uint8_t op)
>> > build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
>> > }
>> >
>> > -static void build_append_int_noprefix(GArray *table, uint64_t value, int size)
>> > +void build_append_int_noprefix(GArray *table, uint64_t value, int size)
>> > {
>> > int i;
>> >
>> > @@ -445,12 +445,30 @@ Aml *aml_store(Aml *val, Aml *target)
>> > }
>> >
>> > /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
>> > -Aml *aml_and(Aml *arg1, Aml *arg2)
>> > +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3)
> I know that it's possible to Store inside of And(a, b, save_here) ASL op,
> but could you instead rewrite it to
>
> Store(And(a, b), save_here)
>
> so it wouldn't clatter trivial And(a,b) uses and drop this hunk.
>
Yes, we can use Store(And(a, b), save_here) but according to the SPEC
the And op can have 3 args. We don't support it?
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-10 6:15 ` Shannon Zhao
@ 2015-04-10 7:46 ` Igor Mammedov
2015-04-10 8:04 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-10 7:46 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Fri, 10 Apr 2015 14:15:32 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/9 21:35, Igor Mammedov wrote:
> > On Fri, 3 Apr 2015 18:03:46 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >> >
> >> > Add aml_or() term and make aml_and can take three args.
> >> > Expose build_append_int_noprefix as it wiil be used by
> >> > creating a buffer.
> >> >
> >> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> > ---
> >> > hw/acpi/aml-build.c | 24 +++++++++++++++++++++---
> >> > hw/i386/acpi-build.c | 2 +-
> >> > include/hw/acpi/aml-build.h | 4 +++-
> >> > 3 files changed, 25 insertions(+), 5 deletions(-)
> >> >
> >> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >> > index 5a94fc9..312afb6 100644
> >> > --- a/hw/acpi/aml-build.c
> >> > +++ b/hw/acpi/aml-build.c
> >> > @@ -240,7 +240,7 @@ static void build_extop_package(GArray
> >> > *package, uint8_t op) build_prepend_byte(package, 0x5B); /*
> >> > ExtOpPrefix */ }
> >> >
> >> > -static void build_append_int_noprefix(GArray *table, uint64_t
> >> > value, int size) +void build_append_int_noprefix(GArray *table,
> >> > uint64_t value, int size) {
> >> > int i;
> >> >
> >> > @@ -445,12 +445,30 @@ Aml *aml_store(Aml *val, Aml *target)
> >> > }
> >> >
> >> > /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
> >> > -Aml *aml_and(Aml *arg1, Aml *arg2)
> >> > +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3)
> > I know that it's possible to Store inside of And(a, b, save_here)
> > ASL op, but could you instead rewrite it to
> >
> > Store(And(a, b), save_here)
> >
> > so it wouldn't clatter trivial And(a,b) uses and drop this hunk.
> >
> Yes, we can use Store(And(a, b), save_here) but according to the SPEC
> the And op can have 3 args. We don't support it?
I don't think that we should do it if it could be implemented
using 2 already existing API calls to keep it simple and not to
pollute code with extra ", NULL" argument in most cases.
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term
2015-04-10 7:46 ` Igor Mammedov
@ 2015-04-10 8:04 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-10 8:04 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, msalter, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/4/10 15:46, Igor Mammedov wrote:
> On Fri, 10 Apr 2015 14:15:32 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> > On 2015/4/9 21:35, Igor Mammedov wrote:
>>> > > On Fri, 3 Apr 2015 18:03:46 +0800
>>> > > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>> > >
>>>>> > >> > From: Shannon Zhao <shannon.zhao@linaro.org>
>>>>> > >> >
>>>>> > >> > Add aml_or() term and make aml_and can take three args.
>>>>> > >> > Expose build_append_int_noprefix as it wiil be used by
>>>>> > >> > creating a buffer.
>>>>> > >> >
>>>>> > >> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>>>> > >> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>>> > >> > ---
>>>>> > >> > hw/acpi/aml-build.c | 24 +++++++++++++++++++++---
>>>>> > >> > hw/i386/acpi-build.c | 2 +-
>>>>> > >> > include/hw/acpi/aml-build.h | 4 +++-
>>>>> > >> > 3 files changed, 25 insertions(+), 5 deletions(-)
>>>>> > >> >
>>>>> > >> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>>>>> > >> > index 5a94fc9..312afb6 100644
>>>>> > >> > --- a/hw/acpi/aml-build.c
>>>>> > >> > +++ b/hw/acpi/aml-build.c
>>>>> > >> > @@ -240,7 +240,7 @@ static void build_extop_package(GArray
>>>>> > >> > *package, uint8_t op) build_prepend_byte(package, 0x5B); /*
>>>>> > >> > ExtOpPrefix */ }
>>>>> > >> >
>>>>> > >> > -static void build_append_int_noprefix(GArray *table, uint64_t
>>>>> > >> > value, int size) +void build_append_int_noprefix(GArray *table,
>>>>> > >> > uint64_t value, int size) {
>>>>> > >> > int i;
>>>>> > >> >
>>>>> > >> > @@ -445,12 +445,30 @@ Aml *aml_store(Aml *val, Aml *target)
>>>>> > >> > }
>>>>> > >> >
>>>>> > >> > /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefAnd */
>>>>> > >> > -Aml *aml_and(Aml *arg1, Aml *arg2)
>>>>> > >> > +Aml *aml_and(Aml *arg1, Aml *arg2, Aml *arg3)
>>> > > I know that it's possible to Store inside of And(a, b, save_here)
>>> > > ASL op, but could you instead rewrite it to
>>> > >
>>> > > Store(And(a, b), save_here)
>>> > >
>>> > > so it wouldn't clatter trivial And(a,b) uses and drop this hunk.
>>> > >
>> > Yes, we can use Store(And(a, b), save_here) but according to the SPEC
>> > the And op can have 3 args. We don't support it?
> I don't think that we should do it if it could be implemented
> using 2 already existing API calls to keep it simple and not to
> pollute code with extra ", NULL" argument in most cases.
Ok, will replace that.
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 15/20] hw/acpi/aml-build: Add aml_not() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (13 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 14/20] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-13 15:56 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
` (6 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 9 +++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 312afb6..4f936f7 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -600,6 +600,15 @@ Aml *aml_irq_no_flags(uint8_t irq)
return var;
}
+/* ACPI 1.0: 16.2.3 Operators: DefLNot */
+Aml *aml_not(Aml *arg)
+{
+ Aml *var = aml_opcode(0x92 /* LNotOp */);
+ aml_append(var, arg);
+ build_append_int(var->buf, 0x00); /* NullNameOp */
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
Aml *aml_equal(Aml *arg1, Aml *arg2)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 3473d6e..6b407d5 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -174,6 +174,7 @@ Aml *aml_named_field(const char *name, unsigned length);
Aml *aml_reserved_field(unsigned length);
Aml *aml_local(int num);
Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
+Aml *aml_not(Aml *arg);
Aml *aml_equal(Aml *arg1, Aml *arg2);
Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
const char *name_format, ...) GCC_FMT_ATTR(4, 5);
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 15/20] hw/acpi/aml-build: Add aml_not() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
@ 2015-04-13 15:56 ` Alex Bennée
0 siblings, 0 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-13 15:56 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/acpi/aml-build.c | 9 +++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 312afb6..4f936f7 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -600,6 +600,15 @@ Aml *aml_irq_no_flags(uint8_t irq)
> return var;
> }
>
> +/* ACPI 1.0: 16.2.3 Operators: DefLNot */
> +Aml *aml_not(Aml *arg)
> +{
> + Aml *var = aml_opcode(0x92 /* LNotOp */);
> + aml_append(var, arg);
> + build_append_int(var->buf, 0x00); /* NullNameOp */
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
> Aml *aml_equal(Aml *arg1, Aml *arg2)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 3473d6e..6b407d5 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -174,6 +174,7 @@ Aml *aml_named_field(const char *name, unsigned length);
> Aml *aml_reserved_field(unsigned length);
> Aml *aml_local(int num);
> Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> +Aml *aml_not(Aml *arg);
> Aml *aml_equal(Aml *arg1, Aml *arg2);
> Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
> const char *name_format, ...) GCC_FMT_ATTR(4, 5);
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (14 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 15/20] hw/acpi/aml-build: Add aml_not() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-13 15:55 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
` (5 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 7 +++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 4f936f7..9b8b422 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -626,6 +626,13 @@ Aml *aml_if(Aml *predicate)
return var;
}
+/* ACPI 1.0: 16.2.3 Operators: DefElse */
+Aml *aml_else(void)
+{
+ Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
Aml *aml_method(const char *name, int arg_count)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 6b407d5..3901515 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -206,6 +206,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_method(const char *name, int arg_count);
Aml *aml_if(Aml *predicate);
+Aml *aml_else(void);
Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(void);
Aml *aml_resource_template(void);
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
@ 2015-04-13 15:55 ` Alex Bennée
2015-04-14 2:25 ` Shannon Zhao
2015-04-14 5:56 ` Michael S. Tsirkin
0 siblings, 2 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-13 15:55 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
I was considering if the magic numbers should be defined somewhere but I
guess that is the point of the stub functions.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/acpi/aml-build.c | 7 +++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 4f936f7..9b8b422 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -626,6 +626,13 @@ Aml *aml_if(Aml *predicate)
> return var;
> }
>
> +/* ACPI 1.0: 16.2.3 Operators: DefElse */
> +Aml *aml_else(void)
> +{
> + Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
> Aml *aml_method(const char *name, int arg_count)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 6b407d5..3901515 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -206,6 +206,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> Aml *aml_method(const char *name, int arg_count);
> Aml *aml_if(Aml *predicate);
> +Aml *aml_else(void);
> Aml *aml_package(uint8_t num_elements);
> Aml *aml_buffer(void);
> Aml *aml_resource_template(void);
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-13 15:55 ` Alex Bennée
@ 2015-04-14 2:25 ` Shannon Zhao
2015-04-14 5:56 ` Michael S. Tsirkin
1 sibling, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-14 2:25 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/13 23:55, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>
> I was considering if the magic numbers should be defined somewhere but I
> guess that is the point of the stub functions.
>
Yes, I think so. We can add another patch to do this.
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
>
>> ---
>> hw/acpi/aml-build.c | 7 +++++++
>> include/hw/acpi/aml-build.h | 1 +
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 4f936f7..9b8b422 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -626,6 +626,13 @@ Aml *aml_if(Aml *predicate)
>> return var;
>> }
>>
>> +/* ACPI 1.0: 16.2.3 Operators: DefElse */
>> +Aml *aml_else(void)
>> +{
>> + Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
>> + return var;
>> +}
>> +
>> /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
>> Aml *aml_method(const char *name, int arg_count)
>> {
>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>> index 6b407d5..3901515 100644
>> --- a/include/hw/acpi/aml-build.h
>> +++ b/include/hw/acpi/aml-build.h
>> @@ -206,6 +206,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
>> Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
>> Aml *aml_method(const char *name, int arg_count);
>> Aml *aml_if(Aml *predicate);
>> +Aml *aml_else(void);
>> Aml *aml_package(uint8_t num_elements);
>> Aml *aml_buffer(void);
>> Aml *aml_resource_template(void);
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-13 15:55 ` Alex Bennée
2015-04-14 2:25 ` Shannon Zhao
@ 2015-04-14 5:56 ` Michael S. Tsirkin
2015-04-14 6:38 ` Shannon Zhao
1 sibling, 1 reply; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-14 5:56 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, imammedo, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, Apr 13, 2015 at 04:55:13PM +0100, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >
> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>
> I was considering if the magic numbers should be defined somewhere but I
> guess that is the point of the stub functions.
I don't think so: wrappers make sure each is used
only once. enums would just obfuscate code.
comments are better in that they match the language
used in the acpi spec, exactly.
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> > ---
> > hw/acpi/aml-build.c | 7 +++++++
> > include/hw/acpi/aml-build.h | 1 +
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > index 4f936f7..9b8b422 100644
> > --- a/hw/acpi/aml-build.c
> > +++ b/hw/acpi/aml-build.c
> > @@ -626,6 +626,13 @@ Aml *aml_if(Aml *predicate)
> > return var;
> > }
> >
> > +/* ACPI 1.0: 16.2.3 Operators: DefElse */
> > +Aml *aml_else(void)
> > +{
> > + Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
> > + return var;
> > +}
> > +
> > /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
> > Aml *aml_method(const char *name, int arg_count)
> > {
> > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> > index 6b407d5..3901515 100644
> > --- a/include/hw/acpi/aml-build.h
> > +++ b/include/hw/acpi/aml-build.h
> > @@ -206,6 +206,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> > Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> > Aml *aml_method(const char *name, int arg_count);
> > Aml *aml_if(Aml *predicate);
> > +Aml *aml_else(void);
> > Aml *aml_package(uint8_t num_elements);
> > Aml *aml_buffer(void);
> > Aml *aml_resource_template(void);
>
> --
> Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-14 5:56 ` Michael S. Tsirkin
@ 2015-04-14 6:38 ` Shannon Zhao
2015-04-14 10:15 ` Igor Mammedov
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-14 6:38 UTC (permalink / raw)
To: Michael S. Tsirkin, Alex Bennée
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, pbonzini, hanjun.guo, msalter,
imammedo, lersek, christoffer.dall, shannon.zhao
On 2015/4/14 13:56, Michael S. Tsirkin wrote:
> On Mon, Apr 13, 2015 at 04:55:13PM +0100, Alex Bennée wrote:
>>
>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>
>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>
>>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> I was considering if the magic numbers should be defined somewhere but I
>> guess that is the point of the stub functions.
>
> I don't think so: wrappers make sure each is used
> only once. enums would just obfuscate code.
> comments are better in that they match the language
> used in the acpi spec, exactly.
>
I think this has nothing to do with the Opcode used once or other.
Maybe the Opcodes should be defined at one place, then have a whole
scope of the Opcodes and drop the magic numbers.
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
>>
>>> ---
>>> hw/acpi/aml-build.c | 7 +++++++
>>> include/hw/acpi/aml-build.h | 1 +
>>> 2 files changed, 8 insertions(+)
>>>
>>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>>> index 4f936f7..9b8b422 100644
>>> --- a/hw/acpi/aml-build.c
>>> +++ b/hw/acpi/aml-build.c
>>> @@ -626,6 +626,13 @@ Aml *aml_if(Aml *predicate)
>>> return var;
>>> }
>>>
>>> +/* ACPI 1.0: 16.2.3 Operators: DefElse */
>>> +Aml *aml_else(void)
>>> +{
>>> + Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
>>> + return var;
>>> +}
>>> +
>>> /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
>>> Aml *aml_method(const char *name, int arg_count)
>>> {
>>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>>> index 6b407d5..3901515 100644
>>> --- a/include/hw/acpi/aml-build.h
>>> +++ b/include/hw/acpi/aml-build.h
>>> @@ -206,6 +206,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
>>> Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
>>> Aml *aml_method(const char *name, int arg_count);
>>> Aml *aml_if(Aml *predicate);
>>> +Aml *aml_else(void);
>>> Aml *aml_package(uint8_t num_elements);
>>> Aml *aml_buffer(void);
>>> Aml *aml_resource_template(void);
>>
>> --
>> Alex Bennée
>
>
> .
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term
2015-04-14 6:38 ` Shannon Zhao
@ 2015-04-14 10:15 ` Igor Mammedov
0 siblings, 0 replies; 90+ messages in thread
From: Igor Mammedov @ 2015-04-14 10:15 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, lersek, Michael S. Tsirkin,
a.spyridakis, claudio.fontana, qemu-devel, peter.huangpeng,
hanjun.guo, msalter, pbonzini, Alex Bennée,
christoffer.dall, shannon.zhao
On Tue, 14 Apr 2015 14:38:18 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/14 13:56, Michael S. Tsirkin wrote:
> > On Mon, Apr 13, 2015 at 04:55:13PM +0100, Alex Bennée wrote:
> >>
> >> Shannon Zhao <zhaoshenglong@huawei.com> writes:
> >>
> >>> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>>
> >>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >>
> >> I was considering if the magic numbers should be defined somewhere
> >> but I guess that is the point of the stub functions.
> >
> > I don't think so: wrappers make sure each is used
> > only once. enums would just obfuscate code.
> > comments are better in that they match the language
> > used in the acpi spec, exactly.
> >
>
> I think this has nothing to do with the Opcode used once or other.
> Maybe the Opcodes should be defined at one place, then have a whole
> scope of the Opcodes and drop the magic numbers.
I agree with Michael,
With one off usage, It's easier to read code with magic numbers and
comments, without having to jump around to find out what define or enum
equals.
>
> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> >
> >>
> >>> ---
> >>> hw/acpi/aml-build.c | 7 +++++++
> >>> include/hw/acpi/aml-build.h | 1 +
> >>> 2 files changed, 8 insertions(+)
> >>>
> >>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >>> index 4f936f7..9b8b422 100644
> >>> --- a/hw/acpi/aml-build.c
> >>> +++ b/hw/acpi/aml-build.c
> >>> @@ -626,6 +626,13 @@ Aml *aml_if(Aml *predicate)
> >>> return var;
> >>> }
> >>>
> >>> +/* ACPI 1.0: 16.2.3 Operators: DefElse */
> >>> +Aml *aml_else(void)
> >>> +{
> >>> + Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
> >>> + return var;
> >>> +}
> >>> +
> >>> /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
> >>> Aml *aml_method(const char *name, int arg_count)
> >>> {
> >>> diff --git a/include/hw/acpi/aml-build.h
> >>> b/include/hw/acpi/aml-build.h index 6b407d5..3901515 100644
> >>> --- a/include/hw/acpi/aml-build.h
> >>> +++ b/include/hw/acpi/aml-build.h
> >>> @@ -206,6 +206,7 @@ Aml *aml_scope(const char *name_format, ...)
> >>> GCC_FMT_ATTR(1, 2); Aml *aml_device(const char *name_format, ...)
> >>> GCC_FMT_ATTR(1, 2); Aml *aml_method(const char *name, int
> >>> arg_count); Aml *aml_if(Aml *predicate);
> >>> +Aml *aml_else(void);
> >>> Aml *aml_package(uint8_t num_elements);
> >>> Aml *aml_buffer(void);
> >>> Aml *aml_resource_template(void);
> >>
> >> --
> >> Alex Bennée
> >
> >
> > .
> >
>
>
>
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (15 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 16/20] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-13 15:55 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 18/20] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
` (4 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 11 +++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 9b8b422..221d054 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -718,6 +718,17 @@ Aml *aml_field(const char *name, AmlFieldFlags flags)
return var;
}
+/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefCreateDWordField */
+Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x8A); /* CreateDWordFieldOp */
+ aml_append(var, srcbuf);
+ aml_append(var, index);
+ build_append_namestring(var->buf, "%s", name);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.3 Data Objects Encoding: String */
Aml *aml_string(const char *name_format, ...)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 3901515..0d923e8 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -211,6 +211,7 @@ Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(void);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlFieldFlags flags);
+Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
int16_t val4, int64_t val5);
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
@ 2015-04-13 15:55 ` Alex Bennée
0 siblings, 0 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-13 15:55 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/acpi/aml-build.c | 11 +++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 9b8b422..221d054 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -718,6 +718,17 @@ Aml *aml_field(const char *name, AmlFieldFlags flags)
> return var;
> }
>
> +/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefCreateDWordField */
> +Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name)
> +{
> + Aml *var = aml_alloc();
> + build_append_byte(var->buf, 0x8A); /* CreateDWordFieldOp */
> + aml_append(var, srcbuf);
> + aml_append(var, index);
> + build_append_namestring(var->buf, "%s", name);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.3 Data Objects Encoding: String */
> Aml *aml_string(const char *name_format, ...)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 3901515..0d923e8 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -211,6 +211,7 @@ Aml *aml_package(uint8_t num_elements);
> Aml *aml_buffer(void);
> Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlFieldFlags flags);
> +Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
> Aml *aml_varpackage(uint32_t num_elements);
> Aml *aml_touuid(int32_t val1, int16_t val2, int16_t val3,
> int16_t val4, int64_t val5);
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 18/20] hw/acpi/aml-build: Add aml_dword_io() term
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (16 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 17/20] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-13 15:56 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
` (3 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/acpi/aml-build.c | 17 +++++++++++++++++
include/hw/acpi/aml-build.h | 5 +++++
2 files changed, 22 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 221d054..2076ba1 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -937,6 +937,23 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
addr_gran, addr_min, addr_max, addr_trans, len,
isa_ranges);
}
+/*
+ * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Descriptor
+ *
+ * More verbose description at:
+ * ACPI 5.0: 19.5.33 DWordIO (DWord IO Resource Descriptor Macro)
+ */
+Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
+ AmlDecode dec, AmlISARanges isa_ranges,
+ uint32_t addr_gran, uint32_t addr_min,
+ uint32_t addr_max, uint32_t addr_trans,
+ uint32_t len)
+
+{
+ return aml_dword_as_desc(aml_io_range, min_fixed, max_fixed, dec,
+ addr_gran, addr_min, addr_max, addr_trans, len,
+ isa_ranges);
+}
/*
* ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Space Descriptor
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 0d923e8..adefc25 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -188,6 +188,11 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
uint16_t addr_gran, uint16_t addr_min,
uint16_t addr_max, uint16_t addr_trans,
uint16_t len);
+Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
+ AmlDecode dec, AmlISARanges isa_ranges,
+ uint32_t addr_gran, uint32_t addr_min,
+ uint32_t addr_max, uint32_t addr_trans,
+ uint32_t len);
Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlCacheble cacheable,
AmlReadAndWrite read_and_write,
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 18/20] hw/acpi/aml-build: Add aml_dword_io() term
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 18/20] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
@ 2015-04-13 15:56 ` Alex Bennée
0 siblings, 0 replies; 90+ messages in thread
From: Alex Bennée @ 2015-04-13 15:56 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/acpi/aml-build.c | 17 +++++++++++++++++
> include/hw/acpi/aml-build.h | 5 +++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 221d054..2076ba1 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -937,6 +937,23 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> addr_gran, addr_min, addr_max, addr_trans, len,
> isa_ranges);
> }
> +/*
> + * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Descriptor
> + *
> + * More verbose description at:
> + * ACPI 5.0: 19.5.33 DWordIO (DWord IO Resource Descriptor Macro)
> + */
> +Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> + AmlDecode dec, AmlISARanges isa_ranges,
> + uint32_t addr_gran, uint32_t addr_min,
> + uint32_t addr_max, uint32_t addr_trans,
> + uint32_t len)
> +
> +{
> + return aml_dword_as_desc(aml_io_range, min_fixed, max_fixed, dec,
> + addr_gran, addr_min, addr_max, addr_trans, len,
> + isa_ranges);
> +}
>
> /*
> * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Space Descriptor
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 0d923e8..adefc25 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -188,6 +188,11 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> uint16_t addr_gran, uint16_t addr_min,
> uint16_t addr_max, uint16_t addr_trans,
> uint16_t len);
> +Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> + AmlDecode dec, AmlISARanges isa_ranges,
> + uint32_t addr_gran, uint32_t addr_min,
> + uint32_t addr_max, uint32_t addr_trans,
> + uint32_t len);
> Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
> AmlMaxFixed max_fixed, AmlCacheble cacheable,
> AmlReadAndWrite read_and_write,
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (17 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 18/20] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-13 15:58 ` Alex Bennée
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
` (2 subsequent siblings)
21 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Add PCIe controller in ACPI DSDT table, so the guest can detect
the PCIe.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 140 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index a979582..11574c9 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -48,6 +48,8 @@
#include "qapi/qmp/qint.h"
#include "qom/qom-qobject.h"
#include "exec/ram_addr.h"
+#include "hw/pci/pcie_host.h"
+#include "hw/pci/pci.h"
/* #define DEBUG_ACPI_BUILD */
#ifdef DEBUG_ACPI_BUILD
@@ -176,6 +178,143 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
}
}
+static void acpi_dsdt_add_pci(Aml *scope, acpi_pcie_info *info)
+{
+ Aml *dev, *rt_pkg, *pkg, *method, *rbuf, *crs;
+ Aml *ifctx, *UUID, *ifctx1, *elsectx, *buf, *dev_rp0, *dev_gsi;
+ int i, devfn;
+ int irq = *info->pcie_irq + 32;
+
+ dev = aml_device("%s", "PCI0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
+ aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
+
+ /* Declare the PCI Routing Table. */
+ rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
+ for (devfn = 0; devfn < info->nr_pcie_buses; devfn++) {
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ int gsi = (i + devfn) % PCI_NUM_PINS;
+ pkg = aml_package(4);
+ aml_append(pkg, aml_int((devfn << 16) | 0xFFFF));
+ aml_append(pkg, aml_int(i));
+ aml_append(pkg, aml_name("GSI%d", gsi));
+ aml_append(pkg, aml_int(0));
+ aml_append(rt_pkg, pkg);
+ }
+ }
+ aml_append(dev, aml_name_decl("_PRT", rt_pkg));
+
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ dev_gsi = aml_device("GSI%d", i);
+ aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
+ aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
+ crs = aml_resource_template();
+ aml_append(crs, aml_interrupt(0x01, irq + i));
+ aml_append(dev_gsi, aml_name_decl("_PRS", crs));
+ crs = aml_resource_template();
+ aml_append(crs, aml_interrupt(0x01, irq + i));
+ aml_append(dev_gsi, aml_name_decl("_CRS", crs));
+ method = aml_method("_SRS", 1);
+ aml_append(dev_gsi, method);
+ aml_append(dev, dev_gsi);
+ }
+
+ method = aml_method("_CBA", 0);
+ aml_append(method, aml_return(aml_int(info->pcie_ecam_base)));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0);
+ rbuf = aml_resource_template();
+ aml_append(rbuf,
+ aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
+ 0x0000, 0x0000, info->nr_pcie_buses - 1,
+ 0x0000, info->nr_pcie_buses));
+ aml_append(rbuf,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
+ aml_cacheable, aml_ReadWrite,
+ 0x0000, info->pcie_mmio_base,
+ info->pcie_mmio_base + info->pcie_mmio_size - 1,
+ 0x0000, info->pcie_mmio_size));
+ aml_append(rbuf,
+ aml_dword_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0x0000, info->pcie_ioport_base,
+ info->pcie_ioport_base + info->pcie_ioport_size - 1,
+ 0x0000, info->pcie_ioport_size));
+
+ aml_append(method, aml_name_decl("RBUF", rbuf));
+ aml_append(method, aml_return(rbuf));
+ aml_append(dev, method);
+
+ /* Declare an _OSC (OS Control Handoff) method */
+ aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
+ aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
+ method = aml_method("_OSC", 4);
+ aml_append(method,
+ aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+ UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657, 0x7441C03DD766);
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ aml_append(ifctx,
+ aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+ aml_append(ifctx,
+ aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+ aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
+ aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
+
+ aml_append(ifctx, aml_and(aml_name("CTRL"),
+ aml_int(0x1D), aml_name("CTRL")));
+
+ ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
+ aml_append(ifctx1, aml_or(aml_name("CDW1"),
+ aml_int(0x08), aml_name("CDW1")));
+ aml_append(ifctx, ifctx1);
+
+ ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
+ aml_append(ifctx1, aml_or(aml_name("CDW1"),
+ aml_int(0x10), aml_name("CDW1")));
+ aml_append(ifctx, ifctx1);
+
+ aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
+ aml_append(ifctx, aml_return(aml_arg(3)));
+
+ aml_append(method, ifctx);
+
+ elsectx = aml_else();
+ aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), aml_name("CDW1")));
+ aml_append(elsectx, aml_return(aml_arg(3)));
+ aml_append(method, elsectx);
+
+ aml_append(dev, method);
+
+ method = aml_method("_DSM", 4);
+ UUID = aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117, 0xEA4D19C3434D);
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
+ buf = aml_buffer();
+ build_append_int_noprefix(buf->buf, 0x01, 1);
+ aml_append(ifctx1, aml_return(buf));
+ aml_append(ifctx, ifctx1);
+ aml_append(method, ifctx);
+
+ buf = aml_buffer();
+ build_append_int_noprefix(buf->buf, 0x00, 1);
+ aml_append(method, aml_return(buf));
+
+ aml_append(dev, method);
+
+ dev_rp0 = aml_device("%s", "RP0");
+ aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, dev_rp0);
+
+ aml_append(scope, dev);
+}
+
/* RSDP */
static GArray *
build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
@@ -358,6 +497,7 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
acpi_dsdt_add_flash(scope, info->flash_addr);
acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
info->virtio_mmio_irq, info->virtio_mmio_num);
+ acpi_dsdt_add_pci(scope, guest_info->pcie_info);
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
@ 2015-04-13 15:58 ` Alex Bennée
2015-04-14 1:10 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Alex Bennée @ 2015-04-13 15:58 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add PCIe controller in ACPI DSDT table, so the guest can detect
> the PCIe.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 140 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index a979582..11574c9 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -48,6 +48,8 @@
> #include "qapi/qmp/qint.h"
> #include "qom/qom-qobject.h"
> #include "exec/ram_addr.h"
> +#include "hw/pci/pcie_host.h"
> +#include "hw/pci/pci.h"
>
> /* #define DEBUG_ACPI_BUILD */
> #ifdef DEBUG_ACPI_BUILD
> @@ -176,6 +178,143 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
> }
> }
>
> +static void acpi_dsdt_add_pci(Aml *scope, acpi_pcie_info *info)
> +{
> + Aml *dev, *rt_pkg, *pkg, *method, *rbuf, *crs;
> + Aml *ifctx, *UUID, *ifctx1, *elsectx, *buf, *dev_rp0, *dev_gsi;
> + int i, devfn;
> + int irq = *info->pcie_irq + 32;
> +
> + dev = aml_device("%s", "PCI0");
> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
> +
> + /* Declare the PCI Routing Table. */
> + rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
> + for (devfn = 0; devfn < info->nr_pcie_buses; devfn++) {
> + for (i = 0; i < PCI_NUM_PINS; i++) {
> + int gsi = (i + devfn) % PCI_NUM_PINS;
> + pkg = aml_package(4);
> + aml_append(pkg, aml_int((devfn << 16) | 0xFFFF));
> + aml_append(pkg, aml_int(i));
> + aml_append(pkg, aml_name("GSI%d", gsi));
> + aml_append(pkg, aml_int(0));
> + aml_append(rt_pkg, pkg);
> + }
> + }
> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
> +
> + for (i = 0; i < PCI_NUM_PINS; i++) {
> + dev_gsi = aml_device("GSI%d", i);
> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
> + crs = aml_resource_template();
> + aml_append(crs, aml_interrupt(0x01, irq + i));
> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
> + crs = aml_resource_template();
> + aml_append(crs, aml_interrupt(0x01, irq + i));
> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
> + method = aml_method("_SRS", 1);
> + aml_append(dev_gsi, method);
> + aml_append(dev, dev_gsi);
> + }
> +
> + method = aml_method("_CBA", 0);
> + aml_append(method, aml_return(aml_int(info->pcie_ecam_base)));
> + aml_append(dev, method);
> +
> + method = aml_method("_CRS", 0);
> + rbuf = aml_resource_template();
> + aml_append(rbuf,
> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
> + 0x0000, info->nr_pcie_buses));
> + aml_append(rbuf,
> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
> + aml_cacheable, aml_ReadWrite,
> + 0x0000, info->pcie_mmio_base,
> + info->pcie_mmio_base + info->pcie_mmio_size - 1,
> + 0x0000, info->pcie_mmio_size));
> + aml_append(rbuf,
> + aml_dword_io(aml_min_fixed, aml_max_fixed,
> + aml_pos_decode, aml_entire_range,
> + 0x0000, info->pcie_ioport_base,
> + info->pcie_ioport_base + info->pcie_ioport_size - 1,
> + 0x0000, info->pcie_ioport_size));
> +
> + aml_append(method, aml_name_decl("RBUF", rbuf));
> + aml_append(method, aml_return(rbuf));
> + aml_append(dev, method);
> +
> + /* Declare an _OSC (OS Control Handoff) method */
> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
> + method = aml_method("_OSC", 4);
> + aml_append(method,
> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
> +
> + UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
> 0x7441C03DD766);
This looks like a fairly unreadable uuid already. What are these magic numbers?
> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> + aml_append(ifctx,
> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
> + aml_append(ifctx,
> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
> +
> + aml_append(ifctx, aml_and(aml_name("CTRL"),
> + aml_int(0x1D), aml_name("CTRL")));
> +
> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
> + aml_append(ifctx1, aml_or(aml_name("CDW1"),
> + aml_int(0x08), aml_name("CDW1")));
> + aml_append(ifctx, ifctx1);
> +
> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
> + aml_append(ifctx1, aml_or(aml_name("CDW1"),
> + aml_int(0x10), aml_name("CDW1")));
> + aml_append(ifctx, ifctx1);
> +
> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
> + aml_append(ifctx, aml_return(aml_arg(3)));
> +
> + aml_append(method, ifctx);
> +
> + elsectx = aml_else();
> + aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), aml_name("CDW1")));
> + aml_append(elsectx, aml_return(aml_arg(3)));
> + aml_append(method, elsectx);
> +
> + aml_append(dev, method);
> +
> + method = aml_method("_DSM", 4);
> + UUID = aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117,
> 0xEA4D19C3434D);
Again lots of magic numbers.
> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
> + buf = aml_buffer();
> + build_append_int_noprefix(buf->buf, 0x01, 1);
> + aml_append(ifctx1, aml_return(buf));
> + aml_append(ifctx, ifctx1);
> + aml_append(method, ifctx);
> +
> + buf = aml_buffer();
> + build_append_int_noprefix(buf->buf, 0x00, 1);
> + aml_append(method, aml_return(buf));
> +
> + aml_append(dev, method);
> +
> + dev_rp0 = aml_device("%s", "RP0");
> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
> + aml_append(dev, dev_rp0);
> +
> + aml_append(scope, dev);
> +}
> +
> /* RSDP */
> static GArray *
> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
> @@ -358,6 +497,7 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> acpi_dsdt_add_flash(scope, info->flash_addr);
> acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
> info->virtio_mmio_irq, info->virtio_mmio_num);
> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>
> aml_append(dsdt, scope);
> /* copy AML table into ACPI tables blob and patch header there */
--
Alex Bennée
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-13 15:58 ` Alex Bennée
@ 2015-04-14 1:10 ` Shannon Zhao
2015-04-14 9:30 ` Peter Maydell
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-14 1:10 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/13 23:58, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> Add PCIe controller in ACPI DSDT table, so the guest can detect
>> the PCIe.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 140 +++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 140 insertions(+)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index a979582..11574c9 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -48,6 +48,8 @@
>> #include "qapi/qmp/qint.h"
>> #include "qom/qom-qobject.h"
>> #include "exec/ram_addr.h"
>> +#include "hw/pci/pcie_host.h"
>> +#include "hw/pci/pci.h"
>>
>> /* #define DEBUG_ACPI_BUILD */
>> #ifdef DEBUG_ACPI_BUILD
>> @@ -176,6 +178,143 @@ static void acpi_dsdt_add_virtio(Aml *scope, const hwaddr *mmio_addrs,
>> }
>> }
>>
>> +static void acpi_dsdt_add_pci(Aml *scope, acpi_pcie_info *info)
>> +{
>> + Aml *dev, *rt_pkg, *pkg, *method, *rbuf, *crs;
>> + Aml *ifctx, *UUID, *ifctx1, *elsectx, *buf, *dev_rp0, *dev_gsi;
>> + int i, devfn;
>> + int irq = *info->pcie_irq + 32;
>> +
>> + dev = aml_device("%s", "PCI0");
>> + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
>> + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
>> + aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
>> + aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
>> + aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
>> + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
>> + aml_append(dev, aml_name_decl("_STR", aml_string("PCIe 0 Device")));
>> +
>> + /* Declare the PCI Routing Table. */
>> + rt_pkg = aml_package(info->nr_pcie_buses * PCI_NUM_PINS);
>> + for (devfn = 0; devfn < info->nr_pcie_buses; devfn++) {
>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>> + int gsi = (i + devfn) % PCI_NUM_PINS;
>> + pkg = aml_package(4);
>> + aml_append(pkg, aml_int((devfn << 16) | 0xFFFF));
>> + aml_append(pkg, aml_int(i));
>> + aml_append(pkg, aml_name("GSI%d", gsi));
>> + aml_append(pkg, aml_int(0));
>> + aml_append(rt_pkg, pkg);
>> + }
>> + }
>> + aml_append(dev, aml_name_decl("_PRT", rt_pkg));
>> +
>> + for (i = 0; i < PCI_NUM_PINS; i++) {
>> + dev_gsi = aml_device("GSI%d", i);
>> + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
>> + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
>> + crs = aml_resource_template();
>> + aml_append(crs, aml_interrupt(0x01, irq + i));
>> + aml_append(dev_gsi, aml_name_decl("_PRS", crs));
>> + crs = aml_resource_template();
>> + aml_append(crs, aml_interrupt(0x01, irq + i));
>> + aml_append(dev_gsi, aml_name_decl("_CRS", crs));
>> + method = aml_method("_SRS", 1);
>> + aml_append(dev_gsi, method);
>> + aml_append(dev, dev_gsi);
>> + }
>> +
>> + method = aml_method("_CBA", 0);
>> + aml_append(method, aml_return(aml_int(info->pcie_ecam_base)));
>> + aml_append(dev, method);
>> +
>> + method = aml_method("_CRS", 0);
>> + rbuf = aml_resource_template();
>> + aml_append(rbuf,
>> + aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
>> + 0x0000, 0x0000, info->nr_pcie_buses - 1,
>> + 0x0000, info->nr_pcie_buses));
>> + aml_append(rbuf,
>> + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
>> + aml_cacheable, aml_ReadWrite,
>> + 0x0000, info->pcie_mmio_base,
>> + info->pcie_mmio_base + info->pcie_mmio_size - 1,
>> + 0x0000, info->pcie_mmio_size));
>> + aml_append(rbuf,
>> + aml_dword_io(aml_min_fixed, aml_max_fixed,
>> + aml_pos_decode, aml_entire_range,
>> + 0x0000, info->pcie_ioport_base,
>> + info->pcie_ioport_base + info->pcie_ioport_size - 1,
>> + 0x0000, info->pcie_ioport_size));
>> +
>> + aml_append(method, aml_name_decl("RBUF", rbuf));
>> + aml_append(method, aml_return(rbuf));
>> + aml_append(dev, method);
>> +
>> + /* Declare an _OSC (OS Control Handoff) method */
>> + aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
>> + aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
>> + method = aml_method("_OSC", 4);
>> + aml_append(method,
>> + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
>> +
>> + UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
>> 0x7441C03DD766);
>
> This looks like a fairly unreadable uuid already. What are these magic numbers?
>
Yes, this will be modified to use string according to the spec. Like below way:
UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
>> + aml_append(ifctx,
>> + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
>> + aml_append(ifctx,
>> + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
>> + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
>> + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
>> +
>> + aml_append(ifctx, aml_and(aml_name("CTRL"),
>> + aml_int(0x1D), aml_name("CTRL")));
>> +
>> + ifctx1 = aml_if(aml_not(aml_equal(aml_arg(1), aml_int(0x1))));
>> + aml_append(ifctx1, aml_or(aml_name("CDW1"),
>> + aml_int(0x08), aml_name("CDW1")));
>> + aml_append(ifctx, ifctx1);
>> +
>> + ifctx1 = aml_if(aml_not(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
>> + aml_append(ifctx1, aml_or(aml_name("CDW1"),
>> + aml_int(0x10), aml_name("CDW1")));
>> + aml_append(ifctx, ifctx1);
>> +
>> + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
>> + aml_append(ifctx, aml_return(aml_arg(3)));
>> +
>> + aml_append(method, ifctx);
>> +
>> + elsectx = aml_else();
>> + aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), aml_name("CDW1")));
>> + aml_append(elsectx, aml_return(aml_arg(3)));
>> + aml_append(method, elsectx);
>> +
>> + aml_append(dev, method);
>> +
>> + method = aml_method("_DSM", 4);
>> + UUID = aml_touuid(0xE5C937D0, 0x3553, 0x4d7a, 0x9117,
>> 0xEA4D19C3434D);
>
> Again lots of magic numbers.
>
>> + ifctx = aml_if(aml_equal(aml_arg(0), UUID));
>> + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
>> + buf = aml_buffer();
>> + build_append_int_noprefix(buf->buf, 0x01, 1);
>> + aml_append(ifctx1, aml_return(buf));
>> + aml_append(ifctx, ifctx1);
>> + aml_append(method, ifctx);
>> +
>> + buf = aml_buffer();
>> + build_append_int_noprefix(buf->buf, 0x00, 1);
>> + aml_append(method, aml_return(buf));
>> +
>> + aml_append(dev, method);
>> +
>> + dev_rp0 = aml_device("%s", "RP0");
>> + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
>> + aml_append(dev, dev_rp0);
>> +
>> + aml_append(scope, dev);
>> +}
>> +
>> /* RSDP */
>> static GArray *
>> build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
>> @@ -358,6 +497,7 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>> acpi_dsdt_add_flash(scope, info->flash_addr);
>> acpi_dsdt_add_virtio(scope, info->virtio_mmio_addr,
>> info->virtio_mmio_irq, info->virtio_mmio_num);
>> + acpi_dsdt_add_pci(scope, guest_info->pcie_info);
>>
>> aml_append(dsdt, scope);
>> /* copy AML table into ACPI tables blob and patch header there */
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-14 1:10 ` Shannon Zhao
@ 2015-04-14 9:30 ` Peter Maydell
2015-04-14 9:55 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Peter Maydell @ 2015-04-14 9:30 UTC (permalink / raw)
To: Shannon Zhao
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Mark Salter, Claudio Fontana, QEMU Developers, Laszlo Ersek,
Hanjun Guo, Igor Mammedov, Paolo Bonzini, Huangpeng (Peter),
Alex Bennée, Christoffer Dall, Shannon Zhao
On 14 April 2015 at 02:10, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> On 2015/4/13 23:58, Alex Bennée wrote:
>>
>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>> + UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
>>> 0x7441C03DD766);
>>
>> This looks like a fairly unreadable uuid already. What are these magic numbers?
>>
>
> Yes, this will be modified to use string according to the spec. Like below way:
>
> UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
Those are still magic numbers, you've just put them into
a different format. Where do they come from? What do they mean?
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-14 9:30 ` Peter Maydell
@ 2015-04-14 9:55 ` Shannon Zhao
2015-04-14 9:59 ` Michael S. Tsirkin
0 siblings, 1 reply; 90+ messages in thread
From: Shannon Zhao @ 2015-04-14 9:55 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Mark Salter, Claudio Fontana, QEMU Developers, Laszlo Ersek,
Hanjun Guo, Igor Mammedov, Paolo Bonzini, Huangpeng (Peter),
Alex Bennée, Christoffer Dall, Shannon Zhao
On 2015/4/14 17:30, Peter Maydell wrote:
> On 14 April 2015 at 02:10, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>> On 2015/4/13 23:58, Alex Bennée wrote:
>>>
>>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>>> + UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
>>>> 0x7441C03DD766);
>>>
>>> This looks like a fairly unreadable uuid already. What are these magic numbers?
>>>
>>
>> Yes, this will be modified to use string according to the spec. Like below way:
>>
>> UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
>
> Those are still magic numbers, you've just put them into
> a different format. Where do they come from? What do they mean?
>
This is from the PCI Firmware Spec.
"The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is identified by the Universal Unique
IDentifier (UUID) 33db4d5b-1ff7-401c-9657-7441c03dd766."
"The UUID in _DSM in this context is {E5C937D0-3553-4d7a-9117-EA4D19C3434D}"
Maybe I should use a macro definition for them.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-14 9:55 ` Shannon Zhao
@ 2015-04-14 9:59 ` Michael S. Tsirkin
2015-04-14 10:13 ` Shannon Zhao
0 siblings, 1 reply; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-14 9:59 UTC (permalink / raw)
To: Shannon Zhao
Cc: Peter Maydell, hangaohuai, Alexander Spyridakis, Mark Salter,
Claudio Fontana, QEMU Developers, Laszlo Ersek, Hanjun Guo,
Igor Mammedov, Paolo Bonzini, Huangpeng (Peter),
Alex Bennée, Christoffer Dall, Shannon Zhao
On Tue, Apr 14, 2015 at 05:55:39PM +0800, Shannon Zhao wrote:
> On 2015/4/14 17:30, Peter Maydell wrote:
> > On 14 April 2015 at 02:10, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >> On 2015/4/13 23:58, Alex Bennée wrote:
> >>>
> >>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
> >>>> + UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
> >>>> 0x7441C03DD766);
> >>>
> >>> This looks like a fairly unreadable uuid already. What are these magic numbers?
> >>>
> >>
> >> Yes, this will be modified to use string according to the spec. Like below way:
> >>
> >> UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
> >
> > Those are still magic numbers, you've just put them into
> > a different format. Where do they come from? What do they mean?
> >
>
> This is from the PCI Firmware Spec.
>
> "The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is identified by the Universal Unique
> IDentifier (UUID) 33db4d5b-1ff7-401c-9657-7441c03dd766."
>
> "The UUID in _DSM in this context is {E5C937D0-3553-4d7a-9117-EA4D19C3434D}"
>
> Maybe I should use a macro definition for them.
If there's a single instance of use, a comment would
do as well.
> --
> Thanks,
> Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-04-14 9:59 ` Michael S. Tsirkin
@ 2015-04-14 10:13 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-14 10:13 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Peter Maydell, hangaohuai, Alexander Spyridakis, Mark Salter,
Claudio Fontana, QEMU Developers, Laszlo Ersek, Hanjun Guo,
Igor Mammedov, Paolo Bonzini, Huangpeng (Peter),
Alex Bennée, Christoffer Dall, Shannon Zhao
On 2015/4/14 17:59, Michael S. Tsirkin wrote:
> On Tue, Apr 14, 2015 at 05:55:39PM +0800, Shannon Zhao wrote:
>> On 2015/4/14 17:30, Peter Maydell wrote:
>>> On 14 April 2015 at 02:10, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>>> On 2015/4/13 23:58, Alex Bennée wrote:
>>>>>
>>>>> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>>>>>> + UUID = aml_touuid(0x33DB4D5B, 0x1FF7, 0x401C, 0x9657,
>>>>>> 0x7441C03DD766);
>>>>>
>>>>> This looks like a fairly unreadable uuid already. What are these magic numbers?
>>>>>
>>>>
>>>> Yes, this will be modified to use string according to the spec. Like below way:
>>>>
>>>> UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
>>>
>>> Those are still magic numbers, you've just put them into
>>> a different format. Where do they come from? What do they mean?
>>>
>>
>> This is from the PCI Firmware Spec.
>>
>> "The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is identified by the Universal Unique
>> IDentifier (UUID) 33db4d5b-1ff7-401c-9657-7441c03dd766."
>>
>> "The UUID in _DSM in this context is {E5C937D0-3553-4d7a-9117-EA4D19C3434D}"
>>
>> Maybe I should use a macro definition for them.
>
> If there's a single instance of use, a comment would
> do as well.
>
Ok, will add.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread
* [Qemu-devel] [PATCH v4 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (18 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 19/20] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
@ 2015-04-03 10:03 ` Shannon Zhao
2015-04-06 18:47 ` [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Mark Salter
2015-04-15 10:10 ` Michael S. Tsirkin
21 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-03 10:03 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
msalter
Cc: hangaohuai, shannon.zhao, peter.huangpeng, zhaoshenglong
From: Shannon Zhao <shannon.zhao@linaro.org>
Expose the needed device information to the table generation
insfrastructure and register a machine_init_done notify to
call virt_acpi_build().
Add CONFIG_ACPI to arm-softmmu.mak.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
default-configs/i386-softmmu.mak | 3 ++
default-configs/mips-softmmu.mak | 3 ++
default-configs/mips64-softmmu.mak | 3 ++
default-configs/mips64el-softmmu.mak | 3 ++
default-configs/mipsel-softmmu.mak | 3 ++
default-configs/x86_64-softmmu.mak | 3 ++
hw/acpi/Makefile.objs | 5 ++-
hw/arm/virt.c | 78 ++++++++++++++++++++++++++++++++----
hw/i2c/Makefile.objs | 2 +-
10 files changed, 94 insertions(+), 10 deletions(-)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a767e4b..74f1db3 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -101,3 +101,4 @@ CONFIG_ALLWINNER_A10=y
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
+CONFIG_ACPI=y
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 6a74e00..d2de500 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_IDE_ISA=y
diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak
index cce2c81..c96d42d 100644
--- a/default-configs/mips-softmmu.mak
+++ b/default-configs/mips-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak
index 7a88a08..d229f9e 100644
--- a/default-configs/mips64-softmmu.mak
+++ b/default-configs/mips64-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
index 095de43..ea31b8b 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak
index 0e25108..9a4462e 100644
--- a/default-configs/mipsel-softmmu.mak
+++ b/default-configs/mipsel-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 46b87dd..11019b6 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_CORE=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_IDE_ISA=y
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index b9fefa7..511771a 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -1,5 +1,6 @@
-common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o cpu_hotplug.o
-common-obj-$(CONFIG_ACPI) += memory_hotplug.o
+common-obj-$(CONFIG_ACPI_CORE) += core.o piix4.o ich9.o pcihp.o
+common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
+common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI) += acpi_interface.o
common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
common-obj-$(CONFIG_ACPI) += aml-build.o
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b652b07..c0abaab 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -43,6 +43,7 @@
#include "qemu/bitops.h"
#include "qemu/error-report.h"
#include "hw/pci-host/gpex.h"
+#include "hw/arm/virt-acpi-build.h"
#define NUM_VIRTIO_TRANSPORTS 32
@@ -60,6 +61,11 @@
#define GIC_FDT_IRQ_PPI_CPU_START 8
#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
+#define ARCH_TIMER_VIRT_IRQ 11
+#define ARCH_TIMER_S_EL1_IRQ 13
+#define ARCH_TIMER_NS_EL1_IRQ 14
+#define ARCH_TIMER_NS_EL2_IRQ 10
+
enum {
VIRT_FLASH,
VIRT_MEM,
@@ -149,6 +155,29 @@ static const int a15irqmap[] = {
[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
};
+static acpi_madt_info madt_info = {
+ &a15memmap[VIRT_GIC_CPU].base,
+ &a15memmap[VIRT_GIC_DIST].base
+};
+
+static acpi_dsdt_info dsdt_info = {
+ .uart_addr = &a15memmap[VIRT_UART].base,
+ .uart_irq = &a15irqmap[VIRT_UART],
+ .virtio_mmio_addr = &a15memmap[VIRT_MMIO].base,
+ .virtio_mmio_irq = &a15irqmap[VIRT_MMIO],
+ .virtio_mmio_num = NUM_VIRTIO_TRANSPORTS,
+ .rtc_addr = &a15memmap[VIRT_RTC].base,
+ .rtc_irq = &a15irqmap[VIRT_RTC],
+ .flash_addr = &a15memmap[VIRT_FLASH].base,
+};
+
+static acpi_gtdt_info gtdt_info = {
+ ARCH_TIMER_VIRT_IRQ + 16,
+ ARCH_TIMER_S_EL1_IRQ + 16,
+ ARCH_TIMER_NS_EL1_IRQ + 16,
+ ARCH_TIMER_NS_EL2_IRQ + 16
+};
+
static VirtBoardInfo machines[] = {
{
.cpu_model = "cortex-a15",
@@ -289,10 +318,10 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
"arm,armv7-timer");
}
qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, 13, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 14, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 11, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 10, irqflags);
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
}
static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
@@ -633,8 +662,8 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
0x7 /* PCI irq */);
}
-static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
- uint32_t gic_phandle)
+static acpi_pcie_info *create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
+ uint32_t gic_phandle)
{
hwaddr base = vbi->memmap[VIRT_PCIE].base;
hwaddr size = vbi->memmap[VIRT_PCIE].size;
@@ -654,6 +683,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
DeviceState *dev;
char *nodename;
int i;
+ acpi_pcie_info *pcie_info;
base_ecam = QEMU_ALIGN_DOWN(end - size_ecam, size_ecam);
base_ioport = QEMU_ALIGN_DOWN(base_ecam - size_ioport, size_ioport);
@@ -709,6 +739,18 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
create_pcie_irq_map(vbi, gic_phandle, irq, nodename);
g_free(nodename);
+
+ pcie_info = g_malloc0(sizeof *pcie_info);
+ pcie_info->pcie_mmio_base = base_mmio;
+ pcie_info->pcie_mmio_size = size_mmio;
+ pcie_info->pcie_ioport_base = base_ioport;
+ pcie_info->pcie_ioport_size = size_ioport;
+ pcie_info->pcie_ecam_base = base_ecam;
+ pcie_info->pcie_ecam_size = size_ecam;
+ pcie_info->nr_pcie_buses = nr_pcie_buses;
+ pcie_info->pcie_irq = &a15irqmap[VIRT_PCIE];
+
+ return pcie_info;
}
static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
@@ -719,6 +761,15 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
return board->fdt;
}
+static
+void virt_guest_info_machine_done(Notifier *notifier, void *data)
+{
+ VirtGuestInfoState *guest_info_state = container_of(notifier,
+ VirtGuestInfoState,
+ machine_done);
+ virt_acpi_setup(&guest_info_state->info);
+}
+
static void machvirt_init(MachineState *machine)
{
VirtMachineState *vms = VIRT_MACHINE(machine);
@@ -728,6 +779,8 @@ static void machvirt_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
const char *cpu_model = machine->cpu_model;
VirtBoardInfo *vbi;
+ VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
+ VirtGuestInfo *guest_info = &guest_info_state->info;
uint32_t gic_phandle;
char **cpustr;
@@ -812,7 +865,7 @@ static void machvirt_init(MachineState *machine)
create_rtc(vbi, pic);
- create_pcie(vbi, pic, gic_phandle);
+ guest_info->pcie_info = create_pcie(vbi, pic, gic_phandle);
/* Create mmio transports, so the user can create virtio backends
* (which will be automatically plugged in to the transports). If
@@ -821,6 +874,7 @@ static void machvirt_init(MachineState *machine)
create_virtio_devices(vbi, pic);
create_fw_cfg(vbi);
+ rom_set_fw(fw_cfg_find());
vbi->bootinfo.ram_size = machine->ram_size;
vbi->bootinfo.kernel_filename = machine->kernel_filename;
@@ -831,6 +885,16 @@ static void machvirt_init(MachineState *machine)
vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base;
vbi->bootinfo.get_dtb = machvirt_dtb;
vbi->bootinfo.firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
+
+ guest_info->smp_cpus = smp_cpus;
+ guest_info->max_cpus = max_cpus;
+ guest_info->fw_cfg = fw_cfg_find();
+ guest_info->madt_info = &madt_info;
+ guest_info->dsdt_info = &dsdt_info;
+ guest_info->gtdt_info = >dt_info;
+ guest_info_state->machine_done.notify = virt_guest_info_machine_done;
+ qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
+
arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo);
}
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 648278e..c94e6e6 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,6 +1,6 @@
common-obj-y += core.o smbus.o smbus_eeprom.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
-common-obj-$(CONFIG_ACPI) += smbus_ich9.o
+common-obj-$(CONFIG_ACPI_CORE) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o
common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
--
2.0.4
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (19 preceding siblings ...)
2015-04-03 10:03 ` [Qemu-devel] [PATCH v4 20/20] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
@ 2015-04-06 18:47 ` Mark Salter
2015-04-07 2:43 ` Shannon Zhao
2015-04-15 10:10 ` Michael S. Tsirkin
21 siblings, 1 reply; 90+ messages in thread
From: Mark Salter @ 2015-04-06 18:47 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Fri, 2015-04-03 at 18:03 +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> This patch series generate six ACPI v5.1 tables for machine virt on ARM.
> The set of generated tables are:
> - RSDP
> - RSDT
> - MADT
> - GTDT
> - FADT
> - DSDT
> - MCFG (For PCIe host bridge)
>
> These tables are created dynamically using the function of aml-build.c,
> taking into account the needed information passed from the virt machine model.
> When the generation is finalized, it use fw_cfg to expose the tables to guest.
>
> You can fetch this from following repo:
> http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v4
>
> And this patchset refers to Alexander Spyridakis's patches which are sent to
> qemu-devel mailing list before.
> http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
>
> Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
> ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
> startup test:
>
> xp, windows2008, sles11 on X86
> Fedora Linux kernel on ARM64
>
> Note:
> As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
> Fedora Linux kernel from following address:
> https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
> But maybe this has a bug which cause unsuccessfully initializing BAR, therefore
> virtio-pci can't work. I apply the following patch and the virtio-pci, e1000
> work well.
>
> diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
> index 8456e72..32f8869 100644
> --- a/arch/arm64/kernel/pci.c
> +++ b/arch/arm64/kernel/pci.c
> @@ -240,7 +240,7 @@ static acpi_status setup_resource(struct acpi_resource *acpi_res, void *data)
> if (pci_remap_iospace(res, start) < 0)
> return AE_OK;
>
> - info->res_offset[info->res_num] = port - addr.address.minimum;
> + info->res_offset[info->res_num] = port;
> } else
> info->res_offset[info->res_num] = addr.address.translation_offset;
I don't think this is right. What does the working devicetree node look
like? What does the non-working PCIe table entry look like? What is the
range of PCI bus ioport addresses supported by the virtual device and
what CPU physical range is used to access that PCI ioport range?
> changes since v3:
> * rebase on upstream qemu
> * fix _HID of CPU (Heyi Guo)
> * Add PCIe host bridge
>
> changes since v2:
> * rebase on Igor Mammedov's new branch ASL_API_v3
> * use rsdt instead of xsdt according to Igor Mammedov's suggestion
>
> changes since v1:
> * fix bug found by Laszlo
> * move common helpers into dedictated file and change generating
> table order according to Igor's comments
> * fix copyright and function name according to Michael's comments
>
>
> Shannon Zhao (20):
> hw/i386: Move ACPI header definitions in an arch-independent location
> hw/i386/acpi-build: move generic acpi building helpers into dedictated
> file
> hw/arm/virt-acpi-build: Basic framework for building ACPI tables on
> ARM
> hw/acpi/aml-build: Add aml_memory32_fixed() term
> hw/acpi/aml-build: Add aml_interrupt() term
> hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
> hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
> hw/arm/virt-acpi-build: Generate MADT table
> hw/arm/virt-acpi-build: Generate GTDT table
> hw/arm/virt-acpi-build: Generate RSDT table
> hw/arm/virt-acpi-build: Generate RSDP table
> hw/arm/virt-acpi-build: Add PCIe info and generate MCFG table
> hw/acpi/aml-build: Add ToUUID macro
> hw/acpi/aml-build: Add aml_or() term
> hw/acpi/aml-build: Add aml_not() term
> hw/acpi/aml-build: Add aml_else() term
> hw/acpi/aml-build: Add aml_create_dword_field() term
> hw/acpi/aml-build: Add aml_dword_io() term
> hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
> hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
>
> default-configs/arm-softmmu.mak | 1 +
> default-configs/i386-softmmu.mak | 3 +
> default-configs/mips-softmmu.mak | 3 +
> default-configs/mips64-softmmu.mak | 3 +
> default-configs/mips64el-softmmu.mak | 3 +
> default-configs/mipsel-softmmu.mak | 3 +
> default-configs/x86_64-softmmu.mak | 3 +
> hw/acpi/Makefile.objs | 5 +-
> hw/acpi/aml-build.c | 189 +++++++++-
> hw/arm/Makefile.objs | 1 +
> hw/arm/virt-acpi-build.c | 678 +++++++++++++++++++++++++++++++++++
> hw/arm/virt.c | 78 +++-
> hw/i2c/Makefile.objs | 2 +-
> hw/i386/acpi-build.c | 81 +----
> hw/i386/acpi-defs.h | 368 -------------------
> include/hw/acpi/acpi-defs.h | 479 +++++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 45 ++-
> include/hw/arm/virt-acpi-build.h | 79 ++++
> tests/bios-tables-test.c | 2 +-
> 19 files changed, 1564 insertions(+), 462 deletions(-)
> create mode 100644 hw/arm/virt-acpi-build.c
> delete mode 100644 hw/i386/acpi-defs.h
> create mode 100644 include/hw/acpi/acpi-defs.h
> create mode 100644 include/hw/arm/virt-acpi-build.h
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-06 18:47 ` [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Mark Salter
@ 2015-04-07 2:43 ` Shannon Zhao
2015-04-07 9:19 ` Peter Maydell
2015-04-07 12:07 ` Peter Maydell
0 siblings, 2 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-07 2:43 UTC (permalink / raw)
To: Mark Salter
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
[-- Attachment #1: Type: text/plain, Size: 4650 bytes --]
On 2015/4/7 2:47, Mark Salter wrote:
> On Fri, 2015-04-03 at 18:03 +0800, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.zhao@linaro.org>
>> >
>> > This patch series generate six ACPI v5.1 tables for machine virt on ARM.
>> > The set of generated tables are:
>> > - RSDP
>> > - RSDT
>> > - MADT
>> > - GTDT
>> > - FADT
>> > - DSDT
>> > - MCFG (For PCIe host bridge)
>> >
>> > These tables are created dynamically using the function of aml-build.c,
>> > taking into account the needed information passed from the virt machine model.
>> > When the generation is finalized, it use fw_cfg to expose the tables to guest.
>> >
>> > You can fetch this from following repo:
>> > http://git.linaro.org/people/shannon.zhao/qemu.git ACPI_ARM_v4
>> >
>> > And this patchset refers to Alexander Spyridakis's patches which are sent to
>> > qemu-devel mailing list before.
>> > http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
>> >
>> > Thanks to Laszlo's work on UEFI (ArmVirtualizationQemu) supporting downloading
>> > ACPI tables over fw_cfg, we now can use ACPI in VM. I have done following vm
>> > startup test:
>> >
>> > xp, windows2008, sles11 on X86
>> > Fedora Linux kernel on ARM64
>> >
>> > Note:
>> > As upstream kernel doesn't support ACPI PCI host bridge on ARM64, so I use the
>> > Fedora Linux kernel from following address:
>> > https://git.fedorahosted.org/cgit/kernel-arm64.git/log/?h=devel
>> > But maybe this has a bug which cause unsuccessfully initializing BAR, therefore
>> > virtio-pci can't work. I apply the following patch and the virtio-pci, e1000
>> > work well.
>> >
>> > diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
>> > index 8456e72..32f8869 100644
>> > --- a/arch/arm64/kernel/pci.c
>> > +++ b/arch/arm64/kernel/pci.c
>> > @@ -240,7 +240,7 @@ static acpi_status setup_resource(struct acpi_resource *acpi_res, void *data)
>> > if (pci_remap_iospace(res, start) < 0)
>> > return AE_OK;
>> >
>> > - info->res_offset[info->res_num] = port - addr.address.minimum;
>> > + info->res_offset[info->res_num] = port;
>> > } else
>> > info->res_offset[info->res_num] = addr.address.translation_offset;
> I don't think this is right. What does the working devicetree node look
> like? What does the non-working PCIe table entry look like? What is the
> range of PCI bus ioport addresses supported by the virtual device and
> what CPU physical range is used to access that PCI ioport range?
>
Hi Mark,
I just pick up the related part of the dts and acpi table. I think at this case the pci bus
address and cpu physical address is 1:1 mapped.
The dts node is:
ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
reg = <0x0 0x3f000000 0x0 0x1000000>;
bus-range = <0x0 0xf>;
The ACPI table entry:
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
Return (0x3F000000)
}
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x000F, // Range Maximum
0x0000, // Translation Offset
0x0010, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFF0000, // Range Maximum
0x00000000, // Translation Offset
0x2EFF0000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x3EFF0000, // Range Minimum
0x3F000000, // Range Maximum
0x00000000, // Translation Offset
0x00010000, // Length
,, , TypeStatic)
})
Return(RBUF)
}
--
Thanks,
Shannon
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: dts-pcie --]
[-- Type: text/plain; charset="gb18030"; name="dts-pcie", Size: 1158 bytes --]
pcie@10000000 {
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x8001 0x0 0x3 0x4 0x0 0x0 0x0 0x2 0x8001 0x0 0x4 0x4 0x0 0x0 0x0 0x3 0x8001 0x0 0x5 0x4 0x0 0x0 0x0 0x4 0x8001 0x0 0x6 0x4 0x800 0x0 0x0 0x1 0x8001 0x0 0x4 0x4 0x800 0x0 0x0 0x2 0x8001 0x0 0x5 0x4 0x800 0x0 0x0 0x3 0x8001 0x0 0x6 0x4 0x800 0x0 0x0 0x4 0x8001 0x0 0x3 0x4 0x1000 0x0 0x0 0x1 0x8001 0x0 0x5 0x4 0x1000 0x0 0x0 0x2 0x8001 0x0 0x6 0x4 0x1000 0x0 0x0 0x3 0x8001 0x0 0x3 0x4 0x1000 0x0 0x0 0x4 0x8001 0x0 0x4 0x4 0x1800 0x0 0x0 0x1 0x8001 0x0 0x6 0x4 0x1800 0x0 0x0 0x2 0x8001 0x0 0x3 0x4 0x1800 0x0 0x0 0x3 0x8001 0x0 0x4 0x4 0x1800 0x0 0x0 0x4 0x8001 0x0 0x5 0x4>;
#interrupt-cells = <0x1>;
ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
reg = <0x0 0x3f000000 0x0 0x1000000>;
bus-range = <0x0 0xf>;
#size-cells = <0x2>;
#address-cells = <0x3>;
device_type = "pci";
compatible = "pci-host-ecam-generic";
};
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #3: ACPI-PCIe-entry --]
[-- Type: text/plain; charset="gb18030"; name="ACPI-PCIe-entry", Size: 2084 bytes --]
Device (PCI0)
{
Name (_HID, "PNP0A08") // _HID: Hardware ID
Name (_CID, "PNP0A03") // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI0") // _UID: Unique ID
Name (_STR, "PCIe 0 Device") // _STR: Description String
Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
{
Return (0x3F000000)
}
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x000F, // Range Maximum
0x0000, // Translation Offset
0x0010, // Length
,, )
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Granularity
0x10000000, // Range Minimum
0x3EFF0000, // Range Maximum
0x00000000, // Translation Offset
0x2EFF0000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x3EFF0000, // Range Minimum
0x3F000000, // Range Maximum
0x00000000, // Translation Offset
0x00010000, // Length
,, , TypeStatic)
})
Return(RBUF)
}
}
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 2:43 ` Shannon Zhao
@ 2015-04-07 9:19 ` Peter Maydell
2015-04-07 9:32 ` Michael S. Tsirkin
2015-04-07 11:50 ` Shannon Zhao
2015-04-07 12:07 ` Peter Maydell
1 sibling, 2 replies; 90+ messages in thread
From: Peter Maydell @ 2015-04-07 9:19 UTC (permalink / raw)
To: Shannon Zhao
Cc: hangaohuai, Igor Mammedov, Alexander Spyridakis,
Michael S. Tsirkin, Claudio Fontana, QEMU Developers,
Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> The dts node is:
> ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
> 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
> reg = <0x0 0x3f000000 0x0 0x1000000>;
> bus-range = <0x0 0xf>;
>
> The ACPI table entry:
> Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
> {
> Return (0x3F000000)
> }
> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
> {
> Name (RBUF, ResourceTemplate ()
> {
> WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
> 0x0000, // Granularity
> 0x0000, // Range Minimum
> 0x000F, // Range Maximum
> 0x0000, // Translation Offset
> 0x0010, // Length
> ,, )
> DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
Is this claiming that the non-cacheable PCI MMIO region is cacheable?
If so that isn't right...
> 0x00000000, // Granularity
> 0x10000000, // Range Minimum
> 0x3EFF0000, // Range Maximum
> 0x00000000, // Translation Offset
> 0x2EFF0000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
> 0x00000000, // Granularity
> 0x3EFF0000, // Range Minimum
> 0x3F000000, // Range Maximum
> 0x00000000, // Translation Offset
I rather suspect this is wrong, since (my guess without looking
at the spec) it looks like it defines a 1:1 mapping between
the addresses used to interact with the PCIe IO window and
the IO addresses, which is obviously not what you want.
My guess is you need to set the translation offset at least,
but check the spec.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 9:19 ` Peter Maydell
@ 2015-04-07 9:32 ` Michael S. Tsirkin
2015-04-07 9:43 ` Peter Maydell
2015-04-07 11:50 ` Shannon Zhao
1 sibling, 1 reply; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-07 9:32 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Igor Mammedov, Alexander Spyridakis, Shannon Zhao,
Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On Tue, Apr 07, 2015 at 10:19:22AM +0100, Peter Maydell wrote:
> On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> > The dts node is:
> > ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
> > 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
> > reg = <0x0 0x3f000000 0x0 0x1000000>;
> > bus-range = <0x0 0xf>;
> >
> > The ACPI table entry:
> > Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
> > {
> > Return (0x3F000000)
> > }
> > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
> > {
> > Name (RBUF, ResourceTemplate ()
> > {
> > WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
> > 0x0000, // Granularity
> > 0x0000, // Range Minimum
> > 0x000F, // Range Maximum
> > 0x0000, // Translation Offset
> > 0x0010, // Length
> > ,, )
> > DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>
> Is this claiming that the non-cacheable PCI MMIO region is cacheable?
> If so that isn't right...
I suspect that's fine.
Some parts of MMIO might be cacheable. This really depends on the
device.
> > 0x00000000, // Granularity
> > 0x10000000, // Range Minimum
> > 0x3EFF0000, // Range Maximum
> > 0x00000000, // Translation Offset
> > 0x2EFF0000, // Length
> > ,, , AddressRangeMemory, TypeStatic)
> > DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
> > 0x00000000, // Granularity
> > 0x3EFF0000, // Range Minimum
> > 0x3F000000, // Range Maximum
> > 0x00000000, // Translation Offset
>
> I rather suspect this is wrong, since (my guess without looking
> at the spec) it looks like it defines a 1:1 mapping between
> the addresses used to interact with the PCIe IO window and
> the IO addresses, which is obviously not what you want.
> My guess is you need to set the translation offset at least,
> but check the spec.
>
> -- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 9:32 ` Michael S. Tsirkin
@ 2015-04-07 9:43 ` Peter Maydell
0 siblings, 0 replies; 90+ messages in thread
From: Peter Maydell @ 2015-04-07 9:43 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: hangaohuai, Igor Mammedov, Alexander Spyridakis, Shannon Zhao,
Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 7 April 2015 at 10:32, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Tue, Apr 07, 2015 at 10:19:22AM +0100, Peter Maydell wrote:
>> On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>> > The dts node is:
>> > ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
>> > 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
>> > reg = <0x0 0x3f000000 0x0 0x1000000>;
>> > bus-range = <0x0 0xf>;
>> >
>> > The ACPI table entry:
>> > Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
>> > {
>> > Return (0x3F000000)
>> > }
>> > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
>> > {
>> > Name (RBUF, ResourceTemplate ()
>> > {
>> > WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
>> > 0x0000, // Granularity
>> > 0x0000, // Range Minimum
>> > 0x000F, // Range Maximum
>> > 0x0000, // Translation Offset
>> > 0x0010, // Length
>> > ,, )
>> > DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>>
>> Is this claiming that the non-cacheable PCI MMIO region is cacheable?
>> If so that isn't right...
>
> I suspect that's fine.
> Some parts of MMIO might be cacheable. This really depends on the
> device
No, this is the PCI "non-cacheable MMIO" window. (We don't have
a cacheable MMIO window on this board). In the DTB we advertise
it as non-cacheable, and we should do the same in ACPI.
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 9:19 ` Peter Maydell
2015-04-07 9:32 ` Michael S. Tsirkin
@ 2015-04-07 11:50 ` Shannon Zhao
1 sibling, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-07 11:50 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Igor Mammedov, Alexander Spyridakis,
Michael S. Tsirkin, Claudio Fontana, QEMU Developers,
Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 2015/4/7 17:19, Peter Maydell wrote:
> On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>> The dts node is:
>> ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
>> 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
>> reg = <0x0 0x3f000000 0x0 0x1000000>;
>> bus-range = <0x0 0xf>;
>>
>> The ACPI table entry:
>> Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
>> {
>> Return (0x3F000000)
>> }
>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
>> {
>> Name (RBUF, ResourceTemplate ()
>> {
>> WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
>> 0x0000, // Granularity
>> 0x0000, // Range Minimum
>> 0x000F, // Range Maximum
>> 0x0000, // Translation Offset
>> 0x0010, // Length
>> ,, )
>> DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>
> Is this claiming that the non-cacheable PCI MMIO region is cacheable?
> If so that isn't right...
ok, will fix this.
>
>> 0x00000000, // Granularity
>> 0x10000000, // Range Minimum
>> 0x3EFF0000, // Range Maximum
>> 0x00000000, // Translation Offset
>> 0x2EFF0000, // Length
>> ,, , AddressRangeMemory, TypeStatic)
>> DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
>> 0x00000000, // Granularity
>> 0x3EFF0000, // Range Minimum
>> 0x3F000000, // Range Maximum
>> 0x00000000, // Translation Offset
>
> I rather suspect this is wrong, since (my guess without looking
> at the spec) it looks like it defines a 1:1 mapping between
> the addresses used to interact with the PCIe IO window and
> the IO addresses, which is obviously not what you want.
> My guess is you need to set the translation offset at least,
> but check the spec.
>
Yes, it's not right. I think it should be the following:
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x00000000, // Granularity
0x00000000, // Range Minimum
0x0000FFFF, // Range Maximum
0x3EFF0000, // Translation Offset
0x00010000, // Length
,, , TypeStatic)
With following patch on top of this patchset, the guest with e1000 and virtio-pci works well.
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 11574c9..faa5042 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -236,16 +236,15 @@ static void acpi_dsdt_add_pci(Aml *scope, acpi_pcie_info *info)
0x0000, info->nr_pcie_buses));
aml_append(rbuf,
aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
- aml_cacheable, aml_ReadWrite,
+ aml_non_cacheable, aml_ReadWrite,
0x0000, info->pcie_mmio_base,
info->pcie_mmio_base + info->pcie_mmio_size - 1,
0x0000, info->pcie_mmio_size));
aml_append(rbuf,
aml_dword_io(aml_min_fixed, aml_max_fixed,
aml_pos_decode, aml_entire_range,
- 0x0000, info->pcie_ioport_base,
- info->pcie_ioport_base + info->pcie_ioport_size - 1,
- 0x0000, info->pcie_ioport_size));
+ 0x0000, 0x0000,info->pcie_ioport_size - 1,
+ info->pcie_ioport_base, info->pcie_ioport_size));
Thanks,
Shannon
^ permalink raw reply related [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 2:43 ` Shannon Zhao
2015-04-07 9:19 ` Peter Maydell
@ 2015-04-07 12:07 ` Peter Maydell
2015-04-07 12:18 ` Shannon Zhao
2015-04-07 13:35 ` Igor Mammedov
1 sibling, 2 replies; 90+ messages in thread
From: Peter Maydell @ 2015-04-07 12:07 UTC (permalink / raw)
To: Shannon Zhao
Cc: hangaohuai, Igor Mammedov, Alexander Spyridakis,
Michael S. Tsirkin, Claudio Fontana, QEMU Developers,
Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> The ACPI table entry:
> Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
> {
> Return (0x3F000000)
> }
> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
> {
> Name (RBUF, ResourceTemplate ()
> {
> WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
> 0x0000, // Granularity
> 0x0000, // Range Minimum
> 0x000F, // Range Maximum
> 0x0000, // Translation Offset
> 0x0010, // Length
> ,, )
> DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> 0x00000000, // Granularity
> 0x10000000, // Range Minimum
> 0x3EFF0000, // Range Maximum
> 0x00000000, // Translation Offset
> 0x2EFF0000, // Length
In all the other sections, the Length entry is (rangemax - rangemin) + 1,
but in this one it is not, which suggests an error. Probably your
rangemax here is wrong, since 0x3eff0000 is actually the first address
in the IO window.
(If ACPI is effectively describing the length of the range in
two separate places, it's a shame it doesn't sanity check that
they both agree...)
-- PMM
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 12:07 ` Peter Maydell
@ 2015-04-07 12:18 ` Shannon Zhao
2015-04-07 13:35 ` Igor Mammedov
1 sibling, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-07 12:18 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Igor Mammedov, Alexander Spyridakis,
Michael S. Tsirkin, Claudio Fontana, QEMU Developers,
Huangpeng (Peter),
Hanjun Guo, Mark Salter, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On 2015/4/7 20:07, Peter Maydell wrote:
> On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>> The ACPI table entry:
>> Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
>> {
>> Return (0x3F000000)
>> }
>> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
>> {
>> Name (RBUF, ResourceTemplate ()
>> {
>> WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
>> 0x0000, // Granularity
>> 0x0000, // Range Minimum
>> 0x000F, // Range Maximum
>> 0x0000, // Translation Offset
>> 0x0010, // Length
>> ,, )
>> DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
>> 0x00000000, // Granularity
>> 0x10000000, // Range Minimum
>> 0x3EFF0000, // Range Maximum
>> 0x00000000, // Translation Offset
>> 0x2EFF0000, // Length
>
> In all the other sections, the Length entry is (rangemax - rangemin) + 1,
> but in this one it is not, which suggests an error. Probably your
> rangemax here is wrong, since 0x3eff0000 is actually the first address
> in the IO window.
>
So sorry that the ACPI table entry I pasted is the old version while the code is update.
+ aml_append(rbuf,
+ aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
+ aml_cacheable, aml_ReadWrite,
+ 0x0000, info->pcie_mmio_base,
+ info->pcie_mmio_base + info->pcie_mmio_size - 1,
+ 0x0000, info->pcie_mmio_size));
> (If ACPI is effectively describing the length of the range in
> two separate places, it's a shame it doesn't sanity check that
> they both agree...)
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 12:07 ` Peter Maydell
2015-04-07 12:18 ` Shannon Zhao
@ 2015-04-07 13:35 ` Igor Mammedov
2015-04-08 18:50 ` Michael S. Tsirkin
1 sibling, 1 reply; 90+ messages in thread
From: Igor Mammedov @ 2015-04-07 13:35 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Michael S. Tsirkin, Alexander Spyridakis,
Mark Salter, Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Shannon Zhao, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On Tue, 7 Apr 2015 13:07:31 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com>
> wrote:
> > The ACPI table entry:
> > Method (_CBA, 0, NotSerialized) // _CBA: Configuration
> > Base Address {
> > Return (0x3F000000)
> > }
> > Method (_CRS, 0, NotSerialized) // _CRS: Current
> > Resource Settings {
> > Name (RBUF, ResourceTemplate ()
> > {
> > WordBusNumber (ResourceProducer, MinFixed,
> > MaxFixed, PosDecode, 0x0000, // Granularity
> > 0x0000, // Range Minimum
> > 0x000F, // Range Maximum
> > 0x0000, // Translation Offset
> > 0x0010, // Length
> > ,, )
> > DWordMemory (ResourceProducer, PosDecode,
> > MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, //
> > Granularity 0x10000000, // Range Minimum
> > 0x3EFF0000, // Range Maximum
> > 0x00000000, // Translation Offset
> > 0x2EFF0000, // Length
>
> In all the other sections, the Length entry is (rangemax - rangemin)
> + 1, but in this one it is not, which suggests an error. Probably your
> rangemax here is wrong, since 0x3eff0000 is actually the first address
> in the IO window.
>
> (If ACPI is effectively describing the length of the range in
> two separate places, it's a shame it doesn't sanity check that
> they both agree...)
According to spec Range Minimum & Range Maximum are
lowest/highest possible base address
and have nothing to do with range size.
In x86 target that insanity was since the beginning, I guest it works
because no OS tries to use anything other than Range Minimum.
For example If guest has mapped region at Range Maximum, then access to
it would go beyond on real memory region mapped in QEMU.
In general Range Minimum & Range Maximum should be the same unless
HW side covers access up to Range Maximum + Length.
>
> -- PMM
>
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-07 13:35 ` Igor Mammedov
@ 2015-04-08 18:50 ` Michael S. Tsirkin
0 siblings, 0 replies; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-08 18:50 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, hangaohuai, Alexander Spyridakis, Mark Salter,
Claudio Fontana, QEMU Developers, Huangpeng (Peter),
Hanjun Guo, Shannon Zhao, Paolo Bonzini, Laszlo Ersek,
Christoffer Dall, Shannon Zhao
On Tue, Apr 07, 2015 at 03:35:57PM +0200, Igor Mammedov wrote:
> On Tue, 7 Apr 2015 13:07:31 +0100
> Peter Maydell <peter.maydell@linaro.org> wrote:
>
> > On 7 April 2015 at 03:43, Shannon Zhao <zhaoshenglong@huawei.com>
> > wrote:
> > > The ACPI table entry:
> > > Method (_CBA, 0, NotSerialized) // _CBA: Configuration
> > > Base Address {
> > > Return (0x3F000000)
> > > }
> > > Method (_CRS, 0, NotSerialized) // _CRS: Current
> > > Resource Settings {
> > > Name (RBUF, ResourceTemplate ()
> > > {
> > > WordBusNumber (ResourceProducer, MinFixed,
> > > MaxFixed, PosDecode, 0x0000, // Granularity
> > > 0x0000, // Range Minimum
> > > 0x000F, // Range Maximum
> > > 0x0000, // Translation Offset
> > > 0x0010, // Length
> > > ,, )
> > > DWordMemory (ResourceProducer, PosDecode,
> > > MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, //
> > > Granularity 0x10000000, // Range Minimum
> > > 0x3EFF0000, // Range Maximum
> > > 0x00000000, // Translation Offset
> > > 0x2EFF0000, // Length
> >
> > In all the other sections, the Length entry is (rangemax - rangemin)
> > + 1, but in this one it is not, which suggests an error. Probably your
> > rangemax here is wrong, since 0x3eff0000 is actually the first address
> > in the IO window.
> >
> > (If ACPI is effectively describing the length of the range in
> > two separate places, it's a shame it doesn't sanity check that
> > they both agree...)
> According to spec Range Minimum & Range Maximum are
> lowest/highest possible base address
> and have nothing to do with range size.
> In x86 target that insanity was since the beginning, I guest it works
> because no OS tries to use anything other than Range Minimum.
> For example If guest has mapped region at Range Maximum, then access to
> it would go beyond on real memory region mapped in QEMU.
>
> In general Range Minimum & Range Maximum should be the same unless
> HW side covers access up to Range Maximum + Length.
>
I think it's because the same structure can be used to define memory
resources for devices with programmable base addresses (e.g. like PCI).
Thus you can separately define range of base addresses
(legal BAR values) and separately - the length that is
claimed by the BAR (BAR size).
OTOH IIUC if base address is not programmable, min and max
must always be the same since it's the only valid value.
> >
> > -- PMM
> >
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-03 10:03 [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Shannon Zhao
` (20 preceding siblings ...)
2015-04-06 18:47 ` [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM Mark Salter
@ 2015-04-15 10:10 ` Michael S. Tsirkin
2015-04-15 10:51 ` Shannon Zhao
21 siblings, 1 reply; 90+ messages in thread
From: Michael S. Tsirkin @ 2015-04-15 10:10 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Fri, Apr 03, 2015 at 06:03:32PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> This patch series generate six ACPI v5.1 tables for machine virt on ARM.
> The set of generated tables are:
> - RSDP
> - RSDT
> - MADT
> - GTDT
> - FADT
> - DSDT
> - MCFG (For PCIe host bridge)
>
> These tables are created dynamically using the function of aml-build.c,
> taking into account the needed information passed from the virt machine model.
> When the generation is finalized, it use fw_cfg to expose the tables to guest.
Patches 1 and 2 are good to go.
In fact, I'll happily merge them through my tree.
Thanks!
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM
2015-04-15 10:10 ` Michael S. Tsirkin
@ 2015-04-15 10:51 ` Shannon Zhao
0 siblings, 0 replies; 90+ messages in thread
From: Shannon Zhao @ 2015-04-15 10:51 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: peter.maydell, hangaohuai, a.spyridakis, msalter,
claudio.fontana, qemu-devel, peter.huangpeng, hanjun.guo,
imammedo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/4/15 18:10, Michael S. Tsirkin wrote:
> On Fri, Apr 03, 2015 at 06:03:32PM +0800, Shannon Zhao wrote:
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> This patch series generate six ACPI v5.1 tables for machine virt on ARM.
>> The set of generated tables are:
>> - RSDP
>> - RSDT
>> - MADT
>> - GTDT
>> - FADT
>> - DSDT
>> - MCFG (For PCIe host bridge)
>>
>> These tables are created dynamically using the function of aml-build.c,
>> taking into account the needed information passed from the virt machine model.
>> When the generation is finalized, it use fw_cfg to expose the tables to guest.
>
> Patches 1 and 2 are good to go.
> In fact, I'll happily merge them through my tree.
> Thanks!
>
Cool! Thanks, Michael. Then I will prepare for next version.
--
Thanks,
Shannon
^ permalink raw reply [flat|nested] 90+ messages in thread