[PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[Tomer Maimon]

This patchset  adds initial support for the Nuvoton 
Arbel NPCM8XX Board Management controller (BMC) SoC family. 

The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
The NPCM8XX computing subsystem comprises a quadcore ARM 
Cortex A35 ARM-V8 architecture.

This patchset adds minimal architecture and drivers such as:
Clocksource, Clock, Reset, and WD.

Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

This patchset was tested on the Arbel NPCM8XX evaluation board.

Tomer Maimon (19):
  dt-bindings: timer: npcm: Add npcm845 compatible string
  clocksource: timer-npcm7xx: Add NPCM845 timer support
  dt-bindings: serial: 8250: Add npcm845 compatible string
  tty: serial: 8250: Add NPCM845 UART support
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  watchdog: npcm_wdt: Add NPCM845 watchdog support
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  clk: npcm8xx: add clock controller
  dt-bindings: reset: add syscon property
  reset: npcm: using syscon instead of device data
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: Add NPCM8XX support
  dt-bindings: arm: npcm: Add maintainer
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: defconfig: Add Nuvoton NPCM family support

 .../devicetree/bindings/arm/npcm/npcm.yaml    |   7 +
 .../bindings/arm/npcm/nuvoton,gcr.yaml        |   2 +
 .../bindings/clock/nuvoton,npcm845-clk.yaml   |  68 ++
 .../bindings/reset/nuvoton,npcm-reset.txt     |  19 +-
 .../devicetree/bindings/serial/8250.yaml      |   1 +
 .../bindings/timer/nuvoton,npcm7xx-timer.yaml |   2 +
 .../bindings/watchdog/nuvoton,npcm-wdt.txt    |   3 +-
 MAINTAINERS                                   |   3 +
 arch/arm64/Kconfig.platforms                  |  11 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/nuvoton/Makefile          |   2 +
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 197 +++++
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  |  50 ++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  77 ++
 arch/arm64/configs/defconfig                  |   3 +
 drivers/clk/Kconfig                           |   7 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-npcm8xx.c                     | 767 ++++++++++++++++++
 drivers/clocksource/timer-npcm7xx.c           |   1 +
 drivers/reset/reset-npcm.c                    | 164 +++-
 drivers/tty/serial/8250/8250_of.c             |   1 +
 drivers/watchdog/npcm_wdt.c                   |   1 +
 .../dt-bindings/clock/nuvoton,npcm8xx-clock.h |  50 ++
 .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 +++
 24 files changed, 1526 insertions(+), 36 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
 create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
 create mode 100644 drivers/clk/clk-npcm8xx.c
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
 create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h

-- 
2.33.0

[PATCH v1 01/19] dt-bindings: timer: npcm: Add npcm845 compatible string

[Tomer Maimon]

Add a compatible string for Nuvoton BMC NPCM845 timer.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
index 0cbc26a72151..737af78ad70c 100644
--- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
@@ -8,12 +8,14 @@ title: Nuvoton NPCM7xx timer
 
 maintainers:
   - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+  - Tomer Maimon <tmaimon77@gmail.com>
 
 properties:
   compatible:
     enum:
       - nuvoton,wpcm450-timer  # for Hermon WPCM450
       - nuvoton,npcm750-timer  # for Poleg NPCM750
+      - nuvoton,npcm845-timer  # for Arbel NPCM845
 
   reg:
     maxItems: 1
-- 
2.33.0

Re: [PATCH v1 01/19] dt-bindings: timer: npcm: Add npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 timer.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml        | 2 ++
>  1 file changed, 2 insertions(+)
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 01/19] dt-bindings: timer: npcm: Add npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 timer.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml        | 2 ++
>  1 file changed, 2 insertions(+)
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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[PATCH v1 02/19] clocksource: timer-npcm7xx: Add NPCM845 timer support

[Tomer Maimon]

Add Nuvoton BMC NPCM845 timer support.
The NPCM845 uses the same timer controller as the NPCM750.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/clocksource/timer-npcm7xx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c
index a00520cbb660..1630daad4df5 100644
--- a/drivers/clocksource/timer-npcm7xx.c
+++ b/drivers/clocksource/timer-npcm7xx.c
@@ -210,4 +210,5 @@ static int __init npcm7xx_timer_init(struct device_node *np)
 
 TIMER_OF_DECLARE(wpcm450, "nuvoton,wpcm450-timer", npcm7xx_timer_init);
 TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init);
+TIMER_OF_DECLARE(npcm8xx, "nuvoton,npcm845-timer", npcm7xx_timer_init);
 
-- 
2.33.0

[PATCH v1 03/19] dt-bindings: serial: 8250: Add npcm845 compatible string

[Tomer Maimon]

Add a compatible string for Nuvoton BMC NPCM845 UART.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 Documentation/devicetree/bindings/serial/8250.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 3bab2f27b970..b03118e8e056 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -62,6 +62,7 @@ properties:
       - const: mrvl,pxa-uart
       - const: nuvoton,wpcm450-uart
       - const: nuvoton,npcm750-uart
+      - const: nuvoton,npcm845-uart
       - const: nvidia,tegra20-uart
       - const: nxp,lpc3220-uart
       - items:
-- 
2.33.0

Re: [PATCH v1 03/19] dt-bindings: serial: 8250: Add npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 UART.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 03/19] dt-bindings: serial: 8250: Add npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 UART.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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[PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Tomer Maimon]

Add Nuvoton BMC NPCM845 UART support.
The NPCM845 uses the same UART as the NPCM750.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/tty/serial/8250/8250_of.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
index be8626234627..b155c596e614 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -333,6 +333,7 @@ static const struct of_device_id of_platform_serial_table[] = {
 	{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
 	{ .compatible = "nuvoton,wpcm450-uart", .data = (void *)PORT_NPCM, },
 	{ .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
+	{ .compatible = "nuvoton,npcm845-uart", .data = (void *)PORT_NPCM, },
 	{ /* end of list */ },
 };
 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
-- 
2.33.0

Re: [PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> +++ b/drivers/tty/serial/8250/8250_of.c
> @@ -333,6 +333,7 @@ static const struct of_device_id of_platform_serial_table[] = {
>         { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
>         { .compatible = "nuvoton,wpcm450-uart", .data = (void *)PORT_NPCM, },
>         { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
> +       { .compatible = "nuvoton,npcm845-uart", .data = (void *)PORT_NPCM, },
>         { /* end of list */ },

If these are compatible devices, it's usually easier to claim
compatibility with both the specific chip and the older model
as a fallback, to avoid driver changes. This seems to apply to
the timer and watchdog devices as well.

       Arnd

Re: [PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> +++ b/drivers/tty/serial/8250/8250_of.c
> @@ -333,6 +333,7 @@ static const struct of_device_id of_platform_serial_table[] = {
>         { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
>         { .compatible = "nuvoton,wpcm450-uart", .data = (void *)PORT_NPCM, },
>         { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
> +       { .compatible = "nuvoton,npcm845-uart", .data = (void *)PORT_NPCM, },
>         { /* end of list */ },

If these are compatible devices, it's usually easier to claim
compatibility with both the specific chip and the older model
as a fallback, to avoid driver changes. This seems to apply to
the timer and watchdog devices as well.

       Arnd

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Re: [PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Tomer Maimon]

[-- Attachment #1: Type: text/plain, Size: 1080 bytes --]

Hi Arnd,

Thanks for your comment.

On Mon, 23 May 2022 at 14:48, Arnd Bergmann <arnd@arndb.de> wrote:

> On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> > +++ b/drivers/tty/serial/8250/8250_of.c
> > @@ -333,6 +333,7 @@ static const struct of_device_id
> of_platform_serial_table[] = {
> >         { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
> >         { .compatible = "nuvoton,wpcm450-uart", .data = (void
> *)PORT_NPCM, },
> >         { .compatible = "nuvoton,npcm750-uart", .data = (void
> *)PORT_NPCM, },
> > +       { .compatible = "nuvoton,npcm845-uart", .data = (void
> *)PORT_NPCM, },
> >         { /* end of list */ },
>
> If these are compatible devices, it's usually easier to claim
> compatibility with both the specific chip and the older model
> as a fallback, to avoid driver changes. This seems to apply to
> the timer and watchdog devices as well.
>
Just to make sure, Do you mean claim in the device tree?
like

compatible = "nuvoton,npcm845-timer", "nuvoton,npcm-timer";


>        Arnd
>

 Best regards,

Tomer

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Re: [PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Krzysztof Kozlowski]

On 23/05/2022 14:58, Tomer Maimon wrote:
> Hi Arnd,
> 
> Thanks for your comment.
> 
> On Mon, 23 May 2022 at 14:48, Arnd Bergmann <arnd@arndb.de
> <mailto:arnd@arndb.de>> wrote:
> 
>     On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com
>     <mailto:tmaimon77@gmail.com>> wrote:
>     > +++ b/drivers/tty/serial/8250/8250_of.c
>     > @@ -333,6 +333,7 @@ static const struct of_device_id
>     of_platform_serial_table[] = {
>     >         { .compatible = "ti,da830-uart", .data = (void
>     *)PORT_DA830, },
>     >         { .compatible = "nuvoton,wpcm450-uart", .data = (void
>     *)PORT_NPCM, },
>     >         { .compatible = "nuvoton,npcm750-uart", .data = (void
>     *)PORT_NPCM, },
>     > +       { .compatible = "nuvoton,npcm845-uart", .data = (void
>     *)PORT_NPCM, },
>     >         { /* end of list */ },
> 
>     If these are compatible devices, it's usually easier to claim
>     compatibility with both the specific chip and the older model
>     as a fallback, to avoid driver changes. This seems to apply to
>     the timer and watchdog devices as well.
> 
> Just to make sure, Do you mean claim in the device tree?
> like
> 
> compatible = "nuvoton,npcm845-timer", "nuvoton,npcm-timer";

compatible = "nuvoton,npcm845-timer", "nuvoton,npcm750-timer"";


Best regards,
Krzysztof

Re: [PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Krzysztof Kozlowski]

On 23/05/2022 14:58, Tomer Maimon wrote:
> Hi Arnd,
> 
> Thanks for your comment.
> 
> On Mon, 23 May 2022 at 14:48, Arnd Bergmann <arnd@arndb.de
> <mailto:arnd@arndb.de>> wrote:
> 
>     On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com
>     <mailto:tmaimon77@gmail.com>> wrote:
>     > +++ b/drivers/tty/serial/8250/8250_of.c
>     > @@ -333,6 +333,7 @@ static const struct of_device_id
>     of_platform_serial_table[] = {
>     >         { .compatible = "ti,da830-uart", .data = (void
>     *)PORT_DA830, },
>     >         { .compatible = "nuvoton,wpcm450-uart", .data = (void
>     *)PORT_NPCM, },
>     >         { .compatible = "nuvoton,npcm750-uart", .data = (void
>     *)PORT_NPCM, },
>     > +       { .compatible = "nuvoton,npcm845-uart", .data = (void
>     *)PORT_NPCM, },
>     >         { /* end of list */ },
> 
>     If these are compatible devices, it's usually easier to claim
>     compatibility with both the specific chip and the older model
>     as a fallback, to avoid driver changes. This seems to apply to
>     the timer and watchdog devices as well.
> 
> Just to make sure, Do you mean claim in the device tree?
> like
> 
> compatible = "nuvoton,npcm845-timer", "nuvoton,npcm-timer";

compatible = "nuvoton,npcm845-timer", "nuvoton,npcm750-timer"";


Best regards,
Krzysztof

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Re: [PATCH v1 04/19] tty: serial: 8250: Add NPCM845 UART support

[Tomer Maimon]

[-- Attachment #1: Type: text/plain, Size: 1545 bytes --]

Yes, that's what I mean forgot the 750...

Thanks Krzysztof

On Mon, 23 May 2022 at 16:06, Krzysztof Kozlowski <
krzysztof.kozlowski@linaro.org> wrote:

> On 23/05/2022 14:58, Tomer Maimon wrote:
> > Hi Arnd,
> >
> > Thanks for your comment.
> >
> > On Mon, 23 May 2022 at 14:48, Arnd Bergmann <arnd@arndb.de
> > <mailto:arnd@arndb.de>> wrote:
> >
> >     On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com
> >     <mailto:tmaimon77@gmail.com>> wrote:
> >     > +++ b/drivers/tty/serial/8250/8250_of.c
> >     > @@ -333,6 +333,7 @@ static const struct of_device_id
> >     of_platform_serial_table[] = {
> >     >         { .compatible = "ti,da830-uart", .data = (void
> >     *)PORT_DA830, },
> >     >         { .compatible = "nuvoton,wpcm450-uart", .data = (void
> >     *)PORT_NPCM, },
> >     >         { .compatible = "nuvoton,npcm750-uart", .data = (void
> >     *)PORT_NPCM, },
> >     > +       { .compatible = "nuvoton,npcm845-uart", .data = (void
> >     *)PORT_NPCM, },
> >     >         { /* end of list */ },
> >
> >     If these are compatible devices, it's usually easier to claim
> >     compatibility with both the specific chip and the older model
> >     as a fallback, to avoid driver changes. This seems to apply to
> >     the timer and watchdog devices as well.
> >
> > Just to make sure, Do you mean claim in the device tree?
> > like
> >
> > compatible = "nuvoton,npcm845-timer", "nuvoton,npcm-timer";
>
> compatible = "nuvoton,npcm845-timer", "nuvoton,npcm750-timer"";
>
>
> Best regards,
> Krzysztof
>

[-- Attachment #2: Type: text/html, Size: 2506 bytes --]

[PATCH v1 05/19] dt-bindings: watchdog: npcm: Add npcm845 compatible string

[Tomer Maimon]

Add a compatible string for Nuvoton BMC NPCM845 watchdog.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt          | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
index 9059f54dc023..866a958b8a2b 100644
--- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
@@ -6,7 +6,8 @@ expiry.
 
 Required properties:
 - compatible      : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
-                    "nuvoton,wpcm450-wdt" for WPCM450 (Hermon).
+                    "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
+                    "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
 - reg             : Offset and length of the register set for the device.
 - interrupts      : Contain the timer interrupt with flags for
                     falling edge.
-- 
2.33.0

Re: [PATCH v1 05/19] dt-bindings: watchdog: npcm: Add npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 watchdog.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 05/19] dt-bindings: watchdog: npcm: Add npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 watchdog.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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[PATCH v1 06/19] watchdog: npcm_wdt: Add NPCM845 watchdog support

[Tomer Maimon]

Add Nuvoton BMC NPCM845 watchdog support.
The NPCM845 uses the same watchdog as the NPCM750.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/watchdog/npcm_wdt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
index 28a24caa2627..0b91a3fbec09 100644
--- a/drivers/watchdog/npcm_wdt.c
+++ b/drivers/watchdog/npcm_wdt.c
@@ -231,6 +231,7 @@ static int npcm_wdt_probe(struct platform_device *pdev)
 static const struct of_device_id npcm_wdt_match[] = {
 	{.compatible = "nuvoton,wpcm450-wdt"},
 	{.compatible = "nuvoton,npcm750-wdt"},
+	{.compatible = "nuvoton,npcm845-wdt"},
 	{},
 };
 MODULE_DEVICE_TABLE(of, npcm_wdt_match);
-- 
2.33.0

Re: [PATCH v1 06/19] watchdog: npcm_wdt: Add NPCM845 watchdog support

[Guenter Roeck]

On 5/22/22 08:50, Tomer Maimon wrote:
> Add Nuvoton BMC NPCM845 watchdog support.
> The NPCM845 uses the same watchdog as the NPCM750.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>   drivers/watchdog/npcm_wdt.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
> index 28a24caa2627..0b91a3fbec09 100644
> --- a/drivers/watchdog/npcm_wdt.c
> +++ b/drivers/watchdog/npcm_wdt.c
> @@ -231,6 +231,7 @@ static int npcm_wdt_probe(struct platform_device *pdev)
>   static const struct of_device_id npcm_wdt_match[] = {
>   	{.compatible = "nuvoton,wpcm450-wdt"},
>   	{.compatible = "nuvoton,npcm750-wdt"},
> +	{.compatible = "nuvoton,npcm845-wdt"},
>   	{},
>   };
>   MODULE_DEVICE_TABLE(of, npcm_wdt_match);

Acked-by: Guenter Roeck <linux@roeck-us.net>

Re: [PATCH v1 06/19] watchdog: npcm_wdt: Add NPCM845 watchdog support

[Guenter Roeck]

On 5/22/22 08:50, Tomer Maimon wrote:
> Add Nuvoton BMC NPCM845 watchdog support.
> The NPCM845 uses the same watchdog as the NPCM750.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>   drivers/watchdog/npcm_wdt.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
> index 28a24caa2627..0b91a3fbec09 100644
> --- a/drivers/watchdog/npcm_wdt.c
> +++ b/drivers/watchdog/npcm_wdt.c
> @@ -231,6 +231,7 @@ static int npcm_wdt_probe(struct platform_device *pdev)
>   static const struct of_device_id npcm_wdt_match[] = {
>   	{.compatible = "nuvoton,wpcm450-wdt"},
>   	{.compatible = "nuvoton,npcm750-wdt"},
> +	{.compatible = "nuvoton,npcm845-wdt"},
>   	{},
>   };
>   MODULE_DEVICE_TABLE(of, npcm_wdt_match);

Acked-by: Guenter Roeck <linux@roeck-us.net>

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[PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Tomer Maimon]

Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../bindings/clock/nuvoton,npcm845-clk.yaml   | 68 +++++++++++++++++++
 .../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 50 ++++++++++++++
 2 files changed, 118 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h

diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
new file mode 100644
index 000000000000..f305c7c7eaf0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM8XX Clock Controller Binding
+
+maintainers:
+  - Tomer Maimon <tmaimon77@gmail.com>
+
+description: |
+  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
+  generates and supplies clocks to all modules within the BMC.
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,npcm845-clk
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description:
+      specify the external clocks used by the NPCM8XX clock module.
+    items:
+      - description: 25M reference clock
+      - description: CPU reference clock
+      - description: MC reference clock
+
+  clock-names:
+    description:
+      specify the external clocks names used by the NPCM8XX clock module.
+    items:
+      - const: refclk
+      - const: sysbypck
+      - const: mcbypck
+
+  '#clock-cells':
+    const: 1
+    description:
+      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
+      list of NPCM8XX clock IDs.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  # Clock Control Module node:
+  - |
+
+    ahb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clk: clock-controller@f0801000 {
+            compatible = "nuvoton,npcm845-clk";
+            reg = <0x0 0xf0801000 0x0 0x1000>;
+            #clock-cells = <1>;
+        };
+    };
+
+...
diff --git a/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
new file mode 100644
index 000000000000..d76f606bf88b
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM8xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm8xx-clk
+ *
+ * Copyright (C) 2021 Nuvoton Technologies tomer.maimon@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
+#define __DT_BINDINGS_CLOCK_NPCM8XX_H
+
+#define NPCM8XX_CLK_CPU		0
+#define NPCM8XX_CLK_GFX_PIXEL	1
+#define NPCM8XX_CLK_MC		2
+#define NPCM8XX_CLK_ADC		3
+#define NPCM8XX_CLK_AHB		4
+#define NPCM8XX_CLK_TIMER	5
+#define NPCM8XX_CLK_UART	6
+#define NPCM8XX_CLK_UART2	7
+#define NPCM8XX_CLK_MMC		8
+#define NPCM8XX_CLK_SPI3	9
+#define NPCM8XX_CLK_PCI		10
+#define NPCM8XX_CLK_AXI		11
+#define NPCM8XX_CLK_APB4	12
+#define NPCM8XX_CLK_APB3	13
+#define NPCM8XX_CLK_APB2	14
+#define NPCM8XX_CLK_APB1	15
+#define NPCM8XX_CLK_APB5	16
+#define NPCM8XX_CLK_CLKOUT	17
+#define NPCM8XX_CLK_GFX		18
+#define NPCM8XX_CLK_SU		19
+#define NPCM8XX_CLK_SU48	20
+#define NPCM8XX_CLK_SDHC	21
+#define NPCM8XX_CLK_SPI0	22
+#define NPCM8XX_CLK_SPI1	23
+#define NPCM8XX_CLK_SPIX	24
+#define NPCM8XX_CLK_RG		25
+#define NPCM8XX_CLK_RCP		26
+#define NPCM8XX_CLK_PRE_ADC	27
+#define NPCM8XX_CLK_ATB		28
+#define NPCM8XX_CLK_PRE_CLK	29
+#define NPCM8XX_CLK_TH		30
+#define NPCM8XX_CLK_REFCLK	31
+#define NPCM8XX_CLK_SYSBYPCK	32
+#define NPCM8XX_CLK_MCBYPCK	33
+
+#define NPCM8XX_NUM_CLOCKS	(NPCM8XX_CLK_MCBYPCK + 1)
+
+#endif
-- 
2.33.0

Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
> generates and supplies clocks to all modules within the BMC.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../bindings/clock/nuvoton,npcm845-clk.yaml   | 68 +++++++++++++++++++
>  .../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 50 ++++++++++++++
>  2 files changed, 118 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
>  create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> new file mode 100644
> index 000000000000..f305c7c7eaf0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton NPCM8XX Clock Controller Binding
> +
> +maintainers:
> +  - Tomer Maimon <tmaimon77@gmail.com>
> +
> +description: |
> +  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
> +  generates and supplies clocks to all modules within the BMC.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - nuvoton,npcm845-clk
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description:
> +      specify the external clocks used by the NPCM8XX clock module.

Skip description, it's obvious.

> +    items:
> +      - description: 25M reference clock
> +      - description: CPU reference clock
> +      - description: MC reference clock
> +
> +  clock-names:
> +    description:
> +      specify the external clocks names used by the NPCM8XX clock module.

Skip description, it's obvious.

> +    items:
> +      - const: refclk

Just "ref"

> +      - const: sysbypck
> +      - const: mcbypck

Is "ck" short for "clk"? If yes, then just skip the suffix.

> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
> +      list of NPCM8XX clock IDs.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +

No need for blank line.

> +    ahb {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        clk: clock-controller@f0801000 {
> +            compatible = "nuvoton,npcm845-clk";
> +            reg = <0x0 0xf0801000 0x0 0x1000>;
> +            #clock-cells = <1>;
> +        };
> +    };
> +
> +...
> diff --git a/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> new file mode 100644
> index 000000000000..d76f606bf88b
> --- /dev/null
> +++ b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h

Filename - same as bindings, so nuvoton,npcm845-clk.h

> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license, same as bindings.

> +/*
> + * Nuvoton NPCM8xx Clock Generator binding
> + * clock binding number for all clocks supportted by nuvoton,npcm8xx-clk
> + *
> + * Copyright (C) 2021 Nuvoton Technologies tomer.maimon@nuvoton.com
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
> +#define __DT_BINDINGS_CLOCK_NPCM8XX_H
> +
> +#define NPCM8XX_CLK_CPU		0
> +#define NPCM8XX_CLK_GFX_PIXEL	1
> +#define NPCM8XX_CLK_MC		2
> +#define NPCM8XX_CLK_ADC		3
> +#define NPCM8XX_CLK_AHB		4
> +#define NPCM8XX_CLK_TIMER	5
> +#define NPCM8XX_CLK_UART	6
> +#define NPCM8XX_CLK_UART2	7
> +#define NPCM8XX_CLK_MMC		8
> +#define NPCM8XX_CLK_SPI3	9
> +#define NPCM8XX_CLK_PCI		10
> +#define NPCM8XX_CLK_AXI		11
> +#define NPCM8XX_CLK_APB4	12
> +#define NPCM8XX_CLK_APB3	13
> +#define NPCM8XX_CLK_APB2	14
> +#define NPCM8XX_CLK_APB1	15
> +#define NPCM8XX_CLK_APB5	16
> +#define NPCM8XX_CLK_CLKOUT	17
> +#define NPCM8XX_CLK_GFX		18
> +#define NPCM8XX_CLK_SU		19
> +#define NPCM8XX_CLK_SU48	20
> +#define NPCM8XX_CLK_SDHC	21
> +#define NPCM8XX_CLK_SPI0	22
> +#define NPCM8XX_CLK_SPI1	23
> +#define NPCM8XX_CLK_SPIX	24
> +#define NPCM8XX_CLK_RG		25
> +#define NPCM8XX_CLK_RCP		26
> +#define NPCM8XX_CLK_PRE_ADC	27
> +#define NPCM8XX_CLK_ATB		28
> +#define NPCM8XX_CLK_PRE_CLK	29
> +#define NPCM8XX_CLK_TH		30
> +#define NPCM8XX_CLK_REFCLK	31
> +#define NPCM8XX_CLK_SYSBYPCK	32
> +#define NPCM8XX_CLK_MCBYPCK	33
> +
> +#define NPCM8XX_NUM_CLOCKS	(NPCM8XX_CLK_MCBYPCK + 1)
> +
> +#endif


Best regards,
Krzysztof

Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
> generates and supplies clocks to all modules within the BMC.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../bindings/clock/nuvoton,npcm845-clk.yaml   | 68 +++++++++++++++++++
>  .../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 50 ++++++++++++++
>  2 files changed, 118 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
>  create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> new file mode 100644
> index 000000000000..f305c7c7eaf0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton NPCM8XX Clock Controller Binding
> +
> +maintainers:
> +  - Tomer Maimon <tmaimon77@gmail.com>
> +
> +description: |
> +  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
> +  generates and supplies clocks to all modules within the BMC.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - nuvoton,npcm845-clk
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    description:
> +      specify the external clocks used by the NPCM8XX clock module.

Skip description, it's obvious.

> +    items:
> +      - description: 25M reference clock
> +      - description: CPU reference clock
> +      - description: MC reference clock
> +
> +  clock-names:
> +    description:
> +      specify the external clocks names used by the NPCM8XX clock module.

Skip description, it's obvious.

> +    items:
> +      - const: refclk

Just "ref"

> +      - const: sysbypck
> +      - const: mcbypck

Is "ck" short for "clk"? If yes, then just skip the suffix.

> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
> +      list of NPCM8XX clock IDs.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +

No need for blank line.

> +    ahb {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        clk: clock-controller@f0801000 {
> +            compatible = "nuvoton,npcm845-clk";
> +            reg = <0x0 0xf0801000 0x0 0x1000>;
> +            #clock-cells = <1>;
> +        };
> +    };
> +
> +...
> diff --git a/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> new file mode 100644
> index 000000000000..d76f606bf88b
> --- /dev/null
> +++ b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h

Filename - same as bindings, so nuvoton,npcm845-clk.h

> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license, same as bindings.

> +/*
> + * Nuvoton NPCM8xx Clock Generator binding
> + * clock binding number for all clocks supportted by nuvoton,npcm8xx-clk
> + *
> + * Copyright (C) 2021 Nuvoton Technologies tomer.maimon@nuvoton.com
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
> +#define __DT_BINDINGS_CLOCK_NPCM8XX_H
> +
> +#define NPCM8XX_CLK_CPU		0
> +#define NPCM8XX_CLK_GFX_PIXEL	1
> +#define NPCM8XX_CLK_MC		2
> +#define NPCM8XX_CLK_ADC		3
> +#define NPCM8XX_CLK_AHB		4
> +#define NPCM8XX_CLK_TIMER	5
> +#define NPCM8XX_CLK_UART	6
> +#define NPCM8XX_CLK_UART2	7
> +#define NPCM8XX_CLK_MMC		8
> +#define NPCM8XX_CLK_SPI3	9
> +#define NPCM8XX_CLK_PCI		10
> +#define NPCM8XX_CLK_AXI		11
> +#define NPCM8XX_CLK_APB4	12
> +#define NPCM8XX_CLK_APB3	13
> +#define NPCM8XX_CLK_APB2	14
> +#define NPCM8XX_CLK_APB1	15
> +#define NPCM8XX_CLK_APB5	16
> +#define NPCM8XX_CLK_CLKOUT	17
> +#define NPCM8XX_CLK_GFX		18
> +#define NPCM8XX_CLK_SU		19
> +#define NPCM8XX_CLK_SU48	20
> +#define NPCM8XX_CLK_SDHC	21
> +#define NPCM8XX_CLK_SPI0	22
> +#define NPCM8XX_CLK_SPI1	23
> +#define NPCM8XX_CLK_SPIX	24
> +#define NPCM8XX_CLK_RG		25
> +#define NPCM8XX_CLK_RCP		26
> +#define NPCM8XX_CLK_PRE_ADC	27
> +#define NPCM8XX_CLK_ATB		28
> +#define NPCM8XX_CLK_PRE_CLK	29
> +#define NPCM8XX_CLK_TH		30
> +#define NPCM8XX_CLK_REFCLK	31
> +#define NPCM8XX_CLK_SYSBYPCK	32
> +#define NPCM8XX_CLK_MCBYPCK	33
> +
> +#define NPCM8XX_NUM_CLOCKS	(NPCM8XX_CLK_MCBYPCK + 1)
> +
> +#endif


Best regards,
Krzysztof

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Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Tomer Maimon]

[-- Attachment #1: Type: text/plain, Size: 5465 bytes --]

Hi Krzysztof,

Thanks for your comments.

the patch will modify according to your comments and will be sent in the
next kernel revision 5.19.rc1

On Mon, 23 May 2022 at 10:36, Krzysztof Kozlowski <
krzysztof.kozlowski@linaro.org> wrote:

> On 22/05/2022 17:50, Tomer Maimon wrote:
> > Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
> > generates and supplies clocks to all modules within the BMC.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  .../bindings/clock/nuvoton,npcm845-clk.yaml   | 68 +++++++++++++++++++
> >  .../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 50 ++++++++++++++
> >  2 files changed, 118 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> >  create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> >
> > diff --git
> a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> > new file mode 100644
> > index 000000000000..f305c7c7eaf0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> > @@ -0,0 +1,68 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Nuvoton NPCM8XX Clock Controller Binding
> > +
> > +maintainers:
> > +  - Tomer Maimon <tmaimon77@gmail.com>
> > +
> > +description: |
> > +  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller,
> which
> > +  generates and supplies clocks to all modules within the BMC.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - nuvoton,npcm845-clk
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    description:
> > +      specify the external clocks used by the NPCM8XX clock module.
>
> Skip description, it's obvious.
>
> > +    items:
> > +      - description: 25M reference clock
> > +      - description: CPU reference clock
> > +      - description: MC reference clock
> > +
> > +  clock-names:
> > +    description:
> > +      specify the external clocks names used by the NPCM8XX clock
> module.
>
> Skip description, it's obvious.
>
> > +    items:
> > +      - const: refclk
>
> Just "ref"
>
> > +      - const: sysbypck
> > +      - const: mcbypck
>
> Is "ck" short for "clk"? If yes, then just skip the suffix.
>
ck

>
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +    description:
> > +      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
> > +      list of NPCM8XX clock IDs.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#clock-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  # Clock Control Module node:
> > +  - |
> > +
>
> No need for blank line.
>
> > +    ahb {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        clk: clock-controller@f0801000 {
> > +            compatible = "nuvoton,npcm845-clk";
> > +            reg = <0x0 0xf0801000 0x0 0x1000>;
> > +            #clock-cells = <1>;
> > +        };
> > +    };
> > +
> > +...
> > diff --git a/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
> > new file mode 100644
> > index 000000000000..d76f606bf88b
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
>
> Filename - same as bindings, so nuvoton,npcm845-clk.h
>
> > @@ -0,0 +1,50 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> Dual license, same as bindings.
>
> > +/*
> > + * Nuvoton NPCM8xx Clock Generator binding
> > + * clock binding number for all clocks supportted by nuvoton,npcm8xx-clk
> > + *
> > + * Copyright (C) 2021 Nuvoton Technologies tomer.maimon@nuvoton.com
> > + *
> > + */
> > +
> > +#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
> > +#define __DT_BINDINGS_CLOCK_NPCM8XX_H
> > +
> > +#define NPCM8XX_CLK_CPU              0
> > +#define NPCM8XX_CLK_GFX_PIXEL        1
> > +#define NPCM8XX_CLK_MC               2
> > +#define NPCM8XX_CLK_ADC              3
> > +#define NPCM8XX_CLK_AHB              4
> > +#define NPCM8XX_CLK_TIMER    5
> > +#define NPCM8XX_CLK_UART     6
> > +#define NPCM8XX_CLK_UART2    7
> > +#define NPCM8XX_CLK_MMC              8
> > +#define NPCM8XX_CLK_SPI3     9
> > +#define NPCM8XX_CLK_PCI              10
> > +#define NPCM8XX_CLK_AXI              11
> > +#define NPCM8XX_CLK_APB4     12
> > +#define NPCM8XX_CLK_APB3     13
> > +#define NPCM8XX_CLK_APB2     14
> > +#define NPCM8XX_CLK_APB1     15
> > +#define NPCM8XX_CLK_APB5     16
> > +#define NPCM8XX_CLK_CLKOUT   17
> > +#define NPCM8XX_CLK_GFX              18
> > +#define NPCM8XX_CLK_SU               19
> > +#define NPCM8XX_CLK_SU48     20
> > +#define NPCM8XX_CLK_SDHC     21
> > +#define NPCM8XX_CLK_SPI0     22
> > +#define NPCM8XX_CLK_SPI1     23
> > +#define NPCM8XX_CLK_SPIX     24
> > +#define NPCM8XX_CLK_RG               25
> > +#define NPCM8XX_CLK_RCP              26
> > +#define NPCM8XX_CLK_PRE_ADC  27
> > +#define NPCM8XX_CLK_ATB              28
> > +#define NPCM8XX_CLK_PRE_CLK  29
> > +#define NPCM8XX_CLK_TH               30
> > +#define NPCM8XX_CLK_REFCLK   31
> > +#define NPCM8XX_CLK_SYSBYPCK 32
> > +#define NPCM8XX_CLK_MCBYPCK  33
> > +
> > +#define NPCM8XX_NUM_CLOCKS   (NPCM8XX_CLK_MCBYPCK + 1)
> > +
> > +#endif
>
>
> Best regards,
> Krzysztof
>

Best regards,

Tomer

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Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Stephen Boyd]

Quoting Tomer Maimon (2022-05-22 08:50:34)
> diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> new file mode 100644
> index 000000000000..f305c7c7eaf0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> @@ -0,0 +1,68 @@
[...]
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"

Are clocks not required because sometimes the reference clk isn't
connected?

> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +
> +    ahb {

drop ahb node please.

> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        clk: clock-controller@f0801000 {

Drop label 'clk' as well please.

> +            compatible = "nuvoton,npcm845-clk";
> +            reg = <0x0 0xf0801000 0x0 0x1000>;
> +            #clock-cells = <1>;
> +        };
> +    };
> +
> +...

Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Stephen Boyd]

Quoting Tomer Maimon (2022-05-22 08:50:34)
> diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> new file mode 100644
> index 000000000000..f305c7c7eaf0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> @@ -0,0 +1,68 @@
[...]
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"

Are clocks not required because sometimes the reference clk isn't
connected?

> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +
> +    ahb {

drop ahb node please.

> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        clk: clock-controller@f0801000 {

Drop label 'clk' as well please.

> +            compatible = "nuvoton,npcm845-clk";
> +            reg = <0x0 0xf0801000 0x0 0x1000>;
> +            #clock-cells = <1>;
> +        };
> +    };
> +
> +...

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Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Tomer Maimon]

Hi Stephen,

Thanks for your comments.

The patch will modify according to your comments and will be sent in
the next kernel revision 5.19.rc1

On Thu, 26 May 2022 at 22:24, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Tomer Maimon (2022-05-22 08:50:34)
> > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> > new file mode 100644
> > index 000000000000..f305c7c7eaf0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> > @@ -0,0 +1,68 @@
> [...]
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#clock-cells"
>
> Are clocks not required because sometimes the reference clk isn't
> connected?
require, will be fixed
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  # Clock Control Module node:
> > +  - |
> > +
> > +    ahb {
>
> drop ahb node please.
>
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        clk: clock-controller@f0801000 {
>
> Drop label 'clk' as well please.
>
> > +            compatible = "nuvoton,npcm845-clk";
> > +            reg = <0x0 0xf0801000 0x0 0x1000>;
> > +            #clock-cells = <1>;
> > +        };
> > +    };
> > +
> > +...

Best regards,

Tomer

Re: [PATCH v1 07/19] dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock

[Tomer Maimon]

Hi Stephen,

Thanks for your comments.

The patch will modify according to your comments and will be sent in
the next kernel revision 5.19.rc1

On Thu, 26 May 2022 at 22:24, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Tomer Maimon (2022-05-22 08:50:34)
> > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> > new file mode 100644
> > index 000000000000..f305c7c7eaf0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
> > @@ -0,0 +1,68 @@
> [...]
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#clock-cells"
>
> Are clocks not required because sometimes the reference clk isn't
> connected?
require, will be fixed
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  # Clock Control Module node:
> > +  - |
> > +
> > +    ahb {
>
> drop ahb node please.
>
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        clk: clock-controller@f0801000 {
>
> Drop label 'clk' as well please.
>
> > +            compatible = "nuvoton,npcm845-clk";
> > +            reg = <0x0 0xf0801000 0x0 0x1000>;
> > +            #clock-cells = <1>;
> > +        };
> > +    };
> > +
> > +...

Best regards,

Tomer

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[PATCH v1 08/19] clk: npcm8xx: add clock controller

[Tomer Maimon]

Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/clk/Kconfig       |   7 +
 drivers/clk/Makefile      |   1 +
 drivers/clk/clk-npcm8xx.c | 767 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 775 insertions(+)
 create mode 100644 drivers/clk/clk-npcm8xx.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 5d596e778ff4..b9f3202de872 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -414,6 +414,13 @@ config COMMON_CLK_K210
 	help
 	  Support for the Canaan Kendryte K210 RISC-V SoC clocks.
 
+config COMMON_CLK_NPCM8XX
+	tristate "Clock driver for the NPCM8XX SoC Family"
+	depends on ARCH_NPCM || COMPILE_TEST
+	depends on OF
+	help
+          This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family.
+
 source "drivers/clk/actions/Kconfig"
 source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/baikal-t1/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2bd5ffd595bf..91924f115fdb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_ARCH_MILBEAUT_M10V)	+= clk-milbeaut.o
 obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o
 obj-$(CONFIG_ARCH_NPCM7XX)	    	+= clk-npcm7xx.o
+obj-$(CONFIG_COMMON_CLK_NPCM8XX)	+= clk-npcm8xx.o
 obj-$(CONFIG_ARCH_NSPIRE)		+= clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_OXNAS)		+= clk-oxnas.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
new file mode 100644
index 000000000000..6d0ab7f97ae6
--- /dev/null
+++ b/drivers/clk/clk-npcm8xx.c
@@ -0,0 +1,767 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Nuvoton NPCM8xx Clock Generator
+ * All the clocks are initialized by the bootloader, so this driver allow only
+ * reading of current settings directly from the hardware.
+ *
+ * Copyright (C) 2020 Nuvoton Technologies tomer.maimon@nuvoton.com
+ */
+
+#include <asm/cputype.h>
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/bitfield.h>
+
+#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
+
+struct npcm8xx_clk_pll {
+	struct clk_hw	hw;
+	void __iomem	*pllcon;
+	u8		flags;
+};
+
+#define to_npcm8xx_clk_pll(_hw) container_of(_hw, struct npcm8xx_clk_pll, hw)
+
+#define PLLCON_LOKI	BIT(31)
+#define PLLCON_LOKS	BIT(30)
+#define PLLCON_FBDV	GENMASK(27, 16)
+#define PLLCON_OTDV2	GENMASK(15, 13)
+#define PLLCON_PWDEN	BIT(12)
+#define PLLCON_OTDV1	GENMASK(10, 8)
+#define PLLCON_INDV	GENMASK(5, 0)
+
+static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
+						 unsigned long parent_rate)
+{
+	struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
+	unsigned long fbdv, indv, otdv1, otdv2;
+	unsigned int val;
+	u64 ret;
+
+	if (parent_rate == 0) {
+		pr_err("%s: parent rate is zero", __func__);
+		return 0;
+	}
+
+	val = readl_relaxed(pll->pllcon);
+
+	indv = FIELD_GET(PLLCON_INDV, val);
+	fbdv = FIELD_GET(PLLCON_FBDV, val);
+	otdv1 = FIELD_GET(PLLCON_OTDV1, val);
+	otdv2 = FIELD_GET(PLLCON_OTDV2, val);
+
+	ret = (u64)parent_rate * fbdv;
+	do_div(ret, indv * otdv1 * otdv2);
+
+	return ret;
+}
+
+static const struct clk_ops npcm8xx_clk_pll_ops = {
+	.recalc_rate = npcm8xx_clk_pll_recalc_rate,
+};
+
+static struct clk_hw *
+npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
+			 const char *parent_name, unsigned long flags)
+{
+	struct npcm8xx_clk_pll *pll;
+	struct clk_init_data init;
+	struct clk_hw *hw;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
+
+	init.name = name;
+	init.ops = &npcm8xx_clk_pll_ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+	init.flags = flags;
+
+	pll->pllcon = pllcon;
+	pll->hw.init = &init;
+
+	hw = &pll->hw;
+
+	ret = clk_hw_register(NULL, hw);
+	if (ret) {
+		kfree(pll);
+		hw = ERR_PTR(ret);
+	}
+
+	return hw;
+}
+
+#define NPCM8XX_CLKEN1          (0x00)
+#define NPCM8XX_CLKEN2          (0x28)
+#define NPCM8XX_CLKEN3          (0x30)
+#define NPCM8XX_CLKEN4          (0x70)
+#define NPCM8XX_CLKSEL          (0x04)
+#define NPCM8XX_CLKDIV1         (0x08)
+#define NPCM8XX_CLKDIV2         (0x2C)
+#define NPCM8XX_CLKDIV3         (0x58)
+#define NPCM8XX_CLKDIV4         (0x7C)
+#define NPCM8XX_PLLCON0         (0x0C)
+#define NPCM8XX_PLLCON1         (0x10)
+#define NPCM8XX_PLLCON2         (0x54)
+#define NPCM8XX_SWRSTR          (0x14)
+#define NPCM8XX_IRQWAKECON      (0x18)
+#define NPCM8XX_IRQWAKEFLAG     (0x1C)
+#define NPCM8XX_IPSRST1         (0x20)
+#define NPCM8XX_IPSRST2         (0x24)
+#define NPCM8XX_IPSRST3         (0x34)
+#define NPCM8XX_WD0RCR          (0x38)
+#define NPCM8XX_WD1RCR          (0x3C)
+#define NPCM8XX_WD2RCR          (0x40)
+#define NPCM8XX_SWRSTC1         (0x44)
+#define NPCM8XX_SWRSTC2         (0x48)
+#define NPCM8XX_SWRSTC3         (0x4C)
+#define NPCM8XX_SWRSTC4         (0x50)
+#define NPCM8XX_CORSTC          (0x5C)
+#define NPCM8XX_PLLCONG         (0x60)
+#define NPCM8XX_AHBCKFI         (0x64)
+#define NPCM8XX_SECCNT          (0x68)
+#define NPCM8XX_CNTR25M         (0x6C)
+#define NPCM8XX_THRTL_CNT       (0xC0)
+
+struct npcm8xx_clk_gate_data {
+	u32 reg;
+	u8 bit_idx;
+	const char *name;
+	const char *parent_name;
+	unsigned long flags;
+	/*
+	 * If this clock is exported via DT, set onecell_idx to constant
+	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+	 * this specific clock.  Otherwise, set to -1.
+	 */
+	int onecell_idx;
+};
+
+struct npcm8xx_clk_mux_data {
+	u8 shift;
+	u8 mask;
+	u32 *table;
+	const char *name;
+	const char * const *parent_names;
+	u8 num_parents;
+	unsigned long flags;
+	/*
+	 * If this clock is exported via DT, set onecell_idx to constant
+	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+	 * this specific clock.  Otherwise, set to -1.
+	 */
+	int onecell_idx;
+
+};
+
+struct npcm8xx_clk_div_fixed_data {
+	u8 mult;
+	u8 div;
+	const char *name;
+	const char *parent_name;
+	u8 clk_divider_flags;
+	/*
+	 * If this clock is exported via DT, set onecell_idx to constant
+	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+	 * this specific clock.  Otherwise, set to -1.
+	 */
+	int onecell_idx;
+};
+
+struct npcm8xx_clk_div_data {
+	u32 reg;
+	u8 shift;
+	u8 width;
+	const char *name;
+	const char *parent_name;
+	u8 clk_divider_flags;
+	unsigned long flags;
+	/*
+	 * If this clock is exported via DT, set onecell_idx to constant
+	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+	 * this specific clock.  Otherwise, set to -1.
+	 */
+	int onecell_idx;
+};
+
+struct npcm8xx_clk_pll_data {
+	u32 reg;
+	const char *name;
+	const char *parent_name;
+	unsigned long flags;
+	/*
+	 * If this clock is exported via DT, set onecell_idx to constant
+	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+	 * this specific clock.  Otherwise, set to -1.
+	 */
+	int onecell_idx;
+};
+
+/*
+ * Single copy of strings used to refer to clocks within this driver indexed by
+ * above enum.
+ */
+#define NPCM8XX_CLK_S_REFCLK      "refclk"
+#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
+#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
+#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
+#define NPCM8XX_CLK_S_PLL0        "pll0"
+#define NPCM8XX_CLK_S_PLL1        "pll1"
+#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
+#define NPCM8XX_CLK_S_PLL2        "pll2"
+#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
+#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
+#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
+#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
+#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
+#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
+#define NPCM8XX_CLK_S_MC          "mc"
+#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
+#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
+#define NPCM8XX_CLK_S_CLKOUT_MUX  "clkout_mux"
+#define NPCM8XX_CLK_S_UART_MUX    "uart_mux"
+#define NPCM8XX_CLK_S_UART2_MUX   "uart2_mux"
+#define NPCM8XX_CLK_S_TIM_MUX     "timer_mux"
+#define NPCM8XX_CLK_S_PRE_ADC_MUX "pre_adc_mux"
+#define NPCM8XX_CLK_S_SD_MUX      "sd_mux"
+#define NPCM8XX_CLK_S_GFXM_MUX    "gfxm_mux"
+#define NPCM8XX_CLK_S_SU_MUX      "serial_usb_mux"
+#define NPCM8XX_CLK_S_DVC_MUX     "dvc_mux"
+#define NPCM8XX_CLK_S_GFX_MUX     "gfx_mux"
+#define NPCM8XX_CLK_S_ADC_MUX     "adc_mux"
+#define NPCM8XX_CLK_S_GFX_PIXEL   "gfx_pixel"
+#define NPCM8XX_CLK_S_SPI0        "spi0"
+#define NPCM8XX_CLK_S_SPI1        "spi1"
+#define NPCM8XX_CLK_S_SPI3        "spi3"
+#define NPCM8XX_CLK_S_SPIX        "spix"
+#define NPCM8XX_CLK_S_APB1        "apb1"
+#define NPCM8XX_CLK_S_APB2        "apb2"
+#define NPCM8XX_CLK_S_APB3        "apb3"
+#define NPCM8XX_CLK_S_APB4        "apb4"
+#define NPCM8XX_CLK_S_APB5        "apb5"
+#define NPCM8XX_CLK_S_APB19       "apb19"
+#define NPCM8XX_CLK_S_TOCK        "tock"
+#define NPCM8XX_CLK_S_CLKOUT      "clkout"
+#define NPCM8XX_CLK_S_PRE_ADC     "pre adc"
+#define NPCM8XX_CLK_S_UART        "uart"
+#define NPCM8XX_CLK_S_UART2       "uart2"
+#define NPCM8XX_CLK_S_TIMER       "timer"
+#define NPCM8XX_CLK_S_MMC         "mmc"
+#define NPCM8XX_CLK_S_SDHC        "sdhc"
+#define NPCM8XX_CLK_S_ADC         "adc"
+#define NPCM8XX_CLK_S_AMBA        "amba"
+#define NPCM8XX_CLK_S_GFX         "gfx0_gfx1_mem"
+#define NPCM8XX_CLK_S_USBIF       "serial_usbif"
+#define NPCM8XX_CLK_S_USB_HOST    "usb_host"
+#define NPCM8XX_CLK_S_USB_BRIDGE  "usb_bridge"
+#define NPCM8XX_CLK_S_PCI         "pci"
+#define NPCM8XX_CLK_S_TH          "th"
+#define NPCM8XX_CLK_S_ATB         "atb"
+#define NPCM8XX_CLK_S_PRE_CLK     "pre_clk"
+
+#define NPCM8XX_CLK_S_RG_MUX	  "rg_mux"
+#define NPCM8XX_CLK_S_RCP_MUX	  "rcp_mux"
+#define NPCM8XX_CLK_S_RG	  "rg"
+#define NPCM8XX_CLK_S_RCP	  "rcp"
+
+static u32 pll_mux_table[] = {0, 1, 2, 3};
+static const char * const pll_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_PLL0,
+	NPCM8XX_CLK_S_PLL1,
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 cpuck_mux_table[] = {0, 1, 2, 3, 7};
+static const char * const cpuck_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_PLL0,
+	NPCM8XX_CLK_S_PLL1,
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_SYSBYPCK,
+	NPCM8XX_CLK_S_PLL2,
+};
+
+static u32 pixcksel_mux_table[] = {0, 2};
+static const char * const pixcksel_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_PLL_GFX,
+	NPCM8XX_CLK_S_REFCLK,
+};
+
+static u32 sucksel_mux_table[] = {2, 3};
+static const char * const sucksel_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 mccksel_mux_table[] = {0, 2, 3};
+static const char * const mccksel_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_PLL1_DIV2,
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_MCBYPCK,
+};
+
+static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
+static const char * const clkoutsel_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_PLL0,
+	NPCM8XX_CLK_S_PLL1,
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_PLL_GFX, // divided by 2
+	NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 gfxmsel_mux_table[] = {2, 3};
+static const char * const gfxmsel_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 dvcssel_mux_table[] = {2, 3};
+static const char * const dvcssel_mux_parents[] __initconst = {
+	NPCM8XX_CLK_S_REFCLK,
+	NPCM8XX_CLK_S_PLL2,
+};
+
+static const struct npcm8xx_clk_pll_data npcm8xx_plls[] __initconst = {
+	{NPCM8XX_PLLCON0, NPCM8XX_CLK_S_PLL0, NPCM8XX_CLK_S_REFCLK, 0, -1},
+
+	{NPCM8XX_PLLCON1, NPCM8XX_CLK_S_PLL1,
+	NPCM8XX_CLK_S_REFCLK, 0, -1},
+
+	{NPCM8XX_PLLCON2, NPCM8XX_CLK_S_PLL2,
+	NPCM8XX_CLK_S_REFCLK, 0, -1},
+
+	{NPCM8XX_PLLCONG, NPCM8XX_CLK_S_PLL_GFX,
+	NPCM8XX_CLK_S_REFCLK, 0, -1},
+};
+
+static const struct npcm8xx_clk_mux_data npcm8xx_muxes[] __initconst = {
+	{0, GENMASK(1, 0), cpuck_mux_table, NPCM8XX_CLK_S_CPU_MUX,
+	cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
+	NPCM8XX_CLK_CPU},
+
+	{4, GENMASK(1, 0), pixcksel_mux_table, NPCM8XX_CLK_S_PIX_MUX,
+	pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
+	NPCM8XX_CLK_GFX_PIXEL},
+
+	{6, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_SD_MUX,
+	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+	{8, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_UART_MUX,
+	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+	{10, GENMASK(1, 0), sucksel_mux_table, NPCM8XX_CLK_S_SU_MUX,
+	sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
+
+	{12, GENMASK(1, 0), mccksel_mux_table, NPCM8XX_CLK_S_MC_MUX,
+	mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
+
+	{14, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_ADC_MUX,
+	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+	{16, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_GFX_MUX,
+	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+	{18, GENMASK(2, 0), clkoutsel_mux_table, NPCM8XX_CLK_S_CLKOUT_MUX,
+	clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
+
+	{21, GENMASK(1, 0), gfxmsel_mux_table, NPCM8XX_CLK_S_GFXM_MUX,
+	gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
+
+	{23, GENMASK(1, 0), dvcssel_mux_table, NPCM8XX_CLK_S_DVC_MUX,
+	dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
+
+	{25, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RG_MUX,
+	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+	{27, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RCP_MUX,
+	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+};
+
+/* fixed ratio dividers (no register): */
+static const struct npcm8xx_clk_div_fixed_data npcm8xx_divs_fx[] __initconst = {
+	{ 1, 2, NPCM8XX_CLK_S_MC, NPCM8XX_CLK_S_MC_MUX, 0, NPCM8XX_CLK_MC},
+	{ 1, 2, NPCM8XX_CLK_S_AXI, NPCM8XX_CLK_S_TH, 0, NPCM8XX_CLK_AXI},
+	{ 1, 2, NPCM8XX_CLK_S_ATB, NPCM8XX_CLK_S_AXI, 0, NPCM8XX_CLK_ATB},
+	{ 1, 2, NPCM8XX_CLK_S_PRE_CLK, NPCM8XX_CLK_S_CPU_MUX, 0, -1},
+	{ 1, 2, NPCM8XX_CLK_S_PLL1_DIV2, NPCM8XX_CLK_S_PLL1, 0, -1},
+	{ 1, 2, NPCM8XX_CLK_S_PLL2_DIV2, NPCM8XX_CLK_S_PLL2, 0, -1},
+};
+
+/* configurable dividers: */
+static const struct npcm8xx_clk_div_data npcm8xx_divs[] __initconst = {
+	{NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, NPCM8XX_CLK_S_PRE_ADC,
+		CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+		NPCM8XX_CLK_ADC},
+	/*30-28 ADCCKDIV*/
+	{NPCM8XX_CLKDIV1, 26, 2, NPCM8XX_CLK_S_AHB, NPCM8XX_CLK_S_PRE_CLK,
+		CLK_DIVIDER_READ_ONLY, CLK_IS_CRITICAL, NPCM8XX_CLK_AHB},
+	/*28-26 CLK4DIV*/
+	{NPCM8XX_CLKDIV1, 21, 5, NPCM8XX_CLK_S_PRE_ADC,
+	NPCM8XX_CLK_S_ADC_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PRE_ADC},
+	/*25-21 PRE-ADCCKDIV*/
+	{NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART,
+	NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART},
+	/*20-16 UARTDIV*/
+	{NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC,
+	NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC},
+	/*15-11 MMCCKDIV*/
+	{NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3,
+	NPCM8XX_CLK_S_AHB, 0, 0, NPCM8XX_CLK_SPI3},
+	/*10-6 AHB3CKDIV*/
+	{NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI,
+	NPCM8XX_CLK_S_GFX_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI},
+	/*5-2 PCICKDIV*/
+
+	{NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, NPCM8XX_CLK_S_AHB,
+		CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+		NPCM8XX_CLK_APB4},
+	/*31-30 APB4CKDIV*/
+	{NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, NPCM8XX_CLK_S_AHB,
+		CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+		NPCM8XX_CLK_APB3},
+	/*29-28 APB3CKDIV*/
+	{NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, NPCM8XX_CLK_S_AHB,
+		CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+		NPCM8XX_CLK_APB2},
+	/*28-26 APB2CKDIV*/
+	{NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, NPCM8XX_CLK_S_AHB,
+		CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+		NPCM8XX_CLK_APB1},
+	/*25-24 APB1CKDIV*/
+	{NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, NPCM8XX_CLK_S_AHB,
+		CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+		NPCM8XX_CLK_APB5},
+	/*23-22 APB5CKDIV*/
+	{NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, NPCM8XX_CLK_S_CLKOUT_MUX,
+		 CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT},
+	/*20-16 CLKOUTDIV*/
+	{NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, NPCM8XX_CLK_S_GFX_MUX,
+		CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX},
+	/*15-13 GFXCKDIV*/
+	{NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, NPCM8XX_CLK_S_SU_MUX,
+		CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU},
+	/*12-8 SUCKDIV*/
+	{NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, NPCM8XX_CLK_S_SU_MUX,
+		CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48},
+	/*8-4 SU48CKDIV*/
+	{NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC,
+	NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC}
+	,/*3-0 SD1CKDIV*/
+
+	{NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1,
+	NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1},
+	/*23-16 SPI1CKDV*/
+	{NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2,
+	NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2},
+	/*15-11 UARTDIV2*/
+	{NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0,
+	NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0},
+	/*10-6 SPI0CKDV*/
+	{NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX,
+	NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX},
+
+	/*5-1 SPIXCKDV*/
+	{NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, NPCM8XX_CLK_S_RG_MUX,
+	CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG},
+
+	/*31-28 RGREFDIV*/
+	{NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, NPCM8XX_CLK_S_RCP_MUX,
+	CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP},
+
+	/*15-12 RCPREFDIV*/
+	{NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, NPCM8XX_CLK_S_CPU_MUX,
+	CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH},
+	/*1-0 TH_DIV*/
+};
+
+static const struct npcm8xx_clk_gate_data npcm8xx_gates[] __initconst = {
+	{NPCM8XX_CLKEN1, 31, "smb1-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 30, "smb0-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 29, "smb7-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 28, "smb6-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 27, "adc-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN1, 26, "wdt-gate", NPCM8XX_CLK_S_TIMER, 0},
+	{NPCM8XX_CLKEN1, 25, "usbdev3-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 24, "usbdev6-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 23, "usbdev5-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 22, "usbdev4-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 21, "gmac4-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 20, "timer5_9-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN1, 19, "timer0_4-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN1, 18, "pwmm0-gate", NPCM8XX_CLK_S_APB3, 0},
+	{NPCM8XX_CLKEN1, 17, "huart-gate", NPCM8XX_CLK_S_UART, 0},
+	{NPCM8XX_CLKEN1, 16, "smb5-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 15, "smb4-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 14, "smb3-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 13, "smb2-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN1, 12, "mc-gate", NPCM8XX_CLK_S_MC, 0},
+	{NPCM8XX_CLKEN1, 11, "uart01-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN1, 10, "aes-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 9, "peci-gate", NPCM8XX_CLK_S_APB3, 0},
+	{NPCM8XX_CLKEN1, 8, "usbdev2-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 7, "uart23-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN1, 6, "gmac3-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 5, "usbdev1-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 4, "shm-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 3, "gdma0-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 2, "kcs-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN1, 1, "spi3-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN1, 0, "spi0-gate", NPCM8XX_CLK_S_AHB, 0},
+
+	{NPCM8XX_CLKEN2, 31, "cp-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 30, "tock-gate", NPCM8XX_CLK_S_TOCK, 0},
+	/* bit 29 is reserved */
+	{NPCM8XX_CLKEN2, 28, "gmac1-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 27, "usbif-gate", NPCM8XX_CLK_S_USBIF, 0},
+	{NPCM8XX_CLKEN2, 26, "usbhost1-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 25, "gmac2-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 24, "spi1-gate", NPCM8XX_CLK_S_APB5, 0},
+	{NPCM8XX_CLKEN2, 23, "pspi2-gate", NPCM8XX_CLK_S_APB5, 0},
+	/* bit 22 is reserved */
+	{NPCM8XX_CLKEN2, 21, "3des-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 20, "bt-gate", NPCM8XX_CLK_S_APB3, 0},
+	{NPCM8XX_CLKEN2, 19, "siox2-gate", NPCM8XX_CLK_S_APB3, 0},
+	{NPCM8XX_CLKEN2, 18, "siox1-gate", NPCM8XX_CLK_S_APB3, 0},
+	{NPCM8XX_CLKEN2, 17, "viruart2-gate", NPCM8XX_CLK_S_APB5, 0},
+	{NPCM8XX_CLKEN2, 16, "viruart1-gate", NPCM8XX_CLK_S_APB5, 0},
+	/*  bit 15 is reserved */
+	{NPCM8XX_CLKEN2, 14, "vcd-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 13, "ece-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 12, "vdma-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 10, "gfxsys-gate", NPCM8XX_CLK_S_APB1, 0},
+	//{NPCM8XX_CLKEN2, 9, "sdhc-gate", NPCM8XX_CLK_S_AHB, 0},
+	/*  bit 9 is reserved */
+	{NPCM8XX_CLKEN2, 8, "mmc-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN2, 7, "mft7-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 6, "mft6-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 5, "mft5-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 4, "mft4-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 3, "mft3-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 2, "mft2-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 1, "mft1-gate", NPCM8XX_CLK_S_APB4, 0},
+	{NPCM8XX_CLKEN2, 0, "mft0-gate", NPCM8XX_CLK_S_APB4, 0},
+
+	{NPCM8XX_CLKEN3, 31, "gpiom7-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 30, "gpiom6-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 29, "gpiom5-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 28, "gpiom4-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 27, "gpiom3-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 26, "gpiom2-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 25, "gpiom1-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 24, "gpiom0-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 23, "espi-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 22, "smb11-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 21, "smb10-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 20, "smb9-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 19, "smb8-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 18, "smb15-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 17, "rng-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 16, "timer10_14-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN3, 15, "pcirc-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 14, "sececc-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 13, "sha-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 12, "smb14-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 11, "gdma2-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 10, "gdma1-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 9, "pcimbx-gate", NPCM8XX_CLK_S_AHB, 0},
+	/* bit 8 is reserved */
+	{NPCM8XX_CLKEN3, 7, "usbdev9-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 6, "usbdev8-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 5, "usbdev7-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 4, "usbdev0-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 3, "smb13-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 2, "spix-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN3, 1, "smb12-gate", NPCM8XX_CLK_S_APB2, 0},
+	{NPCM8XX_CLKEN3, 0, "pwmm1-gate", NPCM8XX_CLK_S_APB3, 0},
+
+	{NPCM8XX_CLKEN4, 31, "usbhost2-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN4, 30, "jtm2-gate", NPCM8XX_CLK_S_APB5, 0},
+	{NPCM8XX_CLKEN4, 29, "jtm1-gate", NPCM8XX_CLK_S_APB5, 0},
+	{NPCM8XX_CLKEN4, 28, "pwmm2-gate", NPCM8XX_CLK_S_APB3, 0},
+	/* bit 27 is reserved */
+	/* bit 26 is reserved */
+	/* bit 25 is reserved */
+	{NPCM8XX_CLKEN4, 24, "smb26-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 23, "smb25-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 22, "smb24-gate", NPCM8XX_CLK_S_APB19, 0},
+	/* bit 21 is reserved */
+	/* bit 20 is reserved */
+	{NPCM8XX_CLKEN4, 19, "pcimbx2-gate", NPCM8XX_CLK_S_AHB, 0},
+	{NPCM8XX_CLKEN4, 18, "uart6-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN4, 17, "uart5-gate", NPCM8XX_CLK_S_APB1, 0},
+	{NPCM8XX_CLKEN4, 16, "uart4-gate", NPCM8XX_CLK_S_APB1, 0},
+	/* bit 15 is reserved */
+	/* bit 14 is reserved */
+	{NPCM8XX_CLKEN4, 13, "i3c5-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 12, "i3c4-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 11, "i3c3-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 10, "i3c2-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 9, "i3c1-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 8, "i3c0-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 7, "smb23-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 6, "smb22-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 5, "smb21-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 4, "smb20-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 3, "smb19-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 2, "smb18-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 1, "smb17-gate", NPCM8XX_CLK_S_APB19, 0},
+	{NPCM8XX_CLKEN4, 0, "smb16-gate", NPCM8XX_CLK_S_APB19, 0},
+
+};
+
+static DEFINE_SPINLOCK(npcm8xx_clk_lock);
+
+static void __init npcm8xx_clk_init(struct device_node *clk_np)
+{
+	struct clk_hw_onecell_data *npcm8xx_clk_data;
+	void __iomem *clk_base;
+	struct resource res;
+	struct clk_hw *hw;
+	int ret;
+	int i;
+
+	ret = of_address_to_resource(clk_np, 0, &res);
+	if (ret) {
+		pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
+		return;
+	}
+
+	clk_base = ioremap(res.start, resource_size(&res));
+	if (!clk_base)
+		goto npcm8xx_init_error;
+
+	npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
+					       NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
+	if (!npcm8xx_clk_data)
+		goto npcm8xx_init_np_err;
+
+	npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
+
+	for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
+		npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+	/* Register plls */
+	for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
+		const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
+
+		hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
+					      pll_data->name,
+					      pll_data->parent_name,
+					      pll_data->flags);
+		if (IS_ERR(hw)) {
+			pr_err("npcm8xx_clk: Can't register pll\n");
+			goto npcm8xx_init_fail;
+		}
+
+		if (pll_data->onecell_idx >= 0)
+			npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
+	}
+
+	/* Register fixed dividers */
+	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
+					  NPCM8XX_CLK_S_PLL1, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		pr_err("npcm8xx_clk: Can't register fixed div\n");
+		goto npcm8xx_init_fail;
+	}
+
+	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
+					  NPCM8XX_CLK_S_PLL2, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		pr_err("npcm8xx_clk: Can't register pll div2\n");
+		goto npcm8xx_init_fail;
+	}
+
+	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
+					  NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		pr_err("npcm8xx_clk: Can't register ckclk div2\n");
+		goto npcm8xx_init_fail;
+	}
+
+	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
+					  NPCM8XX_CLK_S_TH, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		pr_err("npcm8xx_clk: Can't register axi div2\n");
+		goto npcm8xx_init_fail;
+	}
+
+	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
+					  NPCM8XX_CLK_S_AXI, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		pr_err("npcm8xx_clk: Can't register atb div2\n");
+		goto npcm8xx_init_fail;
+	}
+
+	/* Register muxes */
+	for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
+		const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
+
+		hw = clk_hw_register_mux_table(NULL, mux_data->name,
+					       mux_data->parent_names,
+					       mux_data->num_parents,
+					       mux_data->flags,
+					       clk_base + NPCM8XX_CLKSEL,
+					       mux_data->shift,
+					       mux_data->mask, 0,
+					       mux_data->table,
+					       &npcm8xx_clk_lock);
+
+		if (IS_ERR(hw)) {
+			pr_err("npcm8xx_clk: Can't register mux\n");
+			goto npcm8xx_init_fail;
+		}
+
+		if (mux_data->onecell_idx >= 0)
+			npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
+	}
+
+	/* Register clock dividers specified in npcm8xx_divs */
+	for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
+		const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
+
+		hw = clk_hw_register_divider(NULL, div_data->name,
+					     div_data->parent_name,
+					     div_data->flags,
+					     clk_base + div_data->reg,
+					     div_data->shift, div_data->width,
+					     div_data->clk_divider_flags,
+					     &npcm8xx_clk_lock);
+		if (IS_ERR(hw)) {
+			pr_err("npcm8xx_clk: Can't register div table\n");
+			goto npcm8xx_init_fail;
+		}
+
+		if (div_data->onecell_idx >= 0)
+			npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
+	}
+
+	ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
+				     npcm8xx_clk_data);
+	if (ret)
+		pr_err("failed to add DT provider: %d\n", ret);
+
+	of_node_put(clk_np);
+
+	return;
+
+npcm8xx_init_fail:
+	kfree(npcm8xx_clk_data->hws);
+npcm8xx_init_np_err:
+	iounmap(clk_base);
+npcm8xx_init_error:
+	of_node_put(clk_np);
+}
+
+CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);
-- 
2.33.0

Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Ilpo Järvinen]

On Sun, 22 May 2022, Tomer Maimon wrote:

> Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
> generates and supplies clocks to all modules within the BMC.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

> +static struct clk_hw *
> +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> +			 const char *parent_name, unsigned long flags)
> +{
> +	struct npcm8xx_clk_pll *pll;
> +	struct clk_init_data init;
> +	struct clk_hw *hw;
> +	int ret;
> +
> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +	if (!pll)
> +		return ERR_PTR(-ENOMEM);
> +
> +	pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> +
> +	init.name = name;
> +	init.ops = &npcm8xx_clk_pll_ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.flags = flags;
> +
> +	pll->pllcon = pllcon;
> +	pll->hw.init = &init;
> +
> +	hw = &pll->hw;
> +
> +	ret = clk_hw_register(NULL, hw);
> +	if (ret) {
> +		kfree(pll);
> +		hw = ERR_PTR(ret);
> +	}
> +
> +	return hw;
> +}
> +
> +#define NPCM8XX_CLKEN1          (0x00)
> +#define NPCM8XX_CLKEN2          (0x28)
> +#define NPCM8XX_CLKEN3          (0x30)
> +#define NPCM8XX_CLKEN4          (0x70)
> +#define NPCM8XX_CLKSEL          (0x04)
> +#define NPCM8XX_CLKDIV1         (0x08)
> +#define NPCM8XX_CLKDIV2         (0x2C)
> +#define NPCM8XX_CLKDIV3         (0x58)
> +#define NPCM8XX_CLKDIV4         (0x7C)
> +#define NPCM8XX_PLLCON0         (0x0C)
> +#define NPCM8XX_PLLCON1         (0x10)
> +#define NPCM8XX_PLLCON2         (0x54)
> +#define NPCM8XX_SWRSTR          (0x14)
> +#define NPCM8XX_IRQWAKECON      (0x18)
> +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> +#define NPCM8XX_IPSRST1         (0x20)
> +#define NPCM8XX_IPSRST2         (0x24)
> +#define NPCM8XX_IPSRST3         (0x34)
> +#define NPCM8XX_WD0RCR          (0x38)
> +#define NPCM8XX_WD1RCR          (0x3C)
> +#define NPCM8XX_WD2RCR          (0x40)
> +#define NPCM8XX_SWRSTC1         (0x44)
> +#define NPCM8XX_SWRSTC2         (0x48)
> +#define NPCM8XX_SWRSTC3         (0x4C)
> +#define NPCM8XX_SWRSTC4         (0x50)
> +#define NPCM8XX_CORSTC          (0x5C)
> +#define NPCM8XX_PLLCONG         (0x60)
> +#define NPCM8XX_AHBCKFI         (0x64)
> +#define NPCM8XX_SECCNT          (0x68)
> +#define NPCM8XX_CNTR25M         (0x6C)
> +#define NPCM8XX_THRTL_CNT       (0xC0)
> +
> +struct npcm8xx_clk_gate_data {
> +	u32 reg;
> +	u8 bit_idx;
> +	const char *name;
> +	const char *parent_name;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_mux_data {
> +	u8 shift;
> +	u8 mask;
> +	u32 *table;
> +	const char *name;
> +	const char * const *parent_names;
> +	u8 num_parents;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +
> +};
> +
> +struct npcm8xx_clk_div_fixed_data {
> +	u8 mult;
> +	u8 div;
> +	const char *name;
> +	const char *parent_name;
> +	u8 clk_divider_flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_div_data {
> +	u32 reg;
> +	u8 shift;
> +	u8 width;
> +	const char *name;
> +	const char *parent_name;
> +	u8 clk_divider_flags;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_pll_data {
> +	u32 reg;
> +	const char *name;
> +	const char *parent_name;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +


> +/*
> + * Single copy of strings used to refer to clocks within this driver indexed by
> + * above enum.
> + */
> +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> +#define NPCM8XX_CLK_S_PLL0        "pll0"
> +#define NPCM8XX_CLK_S_PLL1        "pll1"
> +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> +#define NPCM8XX_CLK_S_PLL2        "pll2"
> +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/

Add spaces around comment.

> +#define NPCM8XX_CLK_S_MC          "mc"
> +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/

Ditto.

> +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> +{
> +	struct clk_hw_onecell_data *npcm8xx_clk_data;
> +	void __iomem *clk_base;
> +	struct resource res;
> +	struct clk_hw *hw;
> +	int ret;
> +	int i;
> +
> +	ret = of_address_to_resource(clk_np, 0, &res);
> +	if (ret) {
> +		pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
> +		return;
> +	}
> +
> +	clk_base = ioremap(res.start, resource_size(&res));
> +	if (!clk_base)
> +		goto npcm8xx_init_error;
> +
> +	npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> +					       NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> +	if (!npcm8xx_clk_data)
> +		goto npcm8xx_init_np_err;
> +
> +	npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> +
> +	for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> +		npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> +
> +	/* Register plls */
> +	for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> +		const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
> +
> +		hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> +					      pll_data->name,
> +					      pll_data->parent_name,
> +					      pll_data->flags);
> +		if (IS_ERR(hw)) {

Who deregisters the already registered plls on error paths?

You might want to consider devm_ variants in npcm8xx_clk_register_pll() to 
make the cleanup simpler.

Please check the other error path rollbacks from this point onward too.

> +			pr_err("npcm8xx_clk: Can't register pll\n");
> +			goto npcm8xx_init_fail;
> +		}
> +
> +		if (pll_data->onecell_idx >= 0)
> +			npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> +	}
> +
> +	/* Register fixed dividers */
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> +					  NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register fixed div\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> +					  NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register pll div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> +					  NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> +					  NPCM8XX_CLK_S_TH, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register axi div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> +					  NPCM8XX_CLK_S_AXI, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register atb div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	/* Register muxes */
> +	for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> +		const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
> +
> +		hw = clk_hw_register_mux_table(NULL, mux_data->name,
> +					       mux_data->parent_names,
> +					       mux_data->num_parents,
> +					       mux_data->flags,
> +					       clk_base + NPCM8XX_CLKSEL,
> +					       mux_data->shift,
> +					       mux_data->mask, 0,
> +					       mux_data->table,
> +					       &npcm8xx_clk_lock);
> +
> +		if (IS_ERR(hw)) {
> +			pr_err("npcm8xx_clk: Can't register mux\n");
> +			goto npcm8xx_init_fail;
> +		}
> +
> +		if (mux_data->onecell_idx >= 0)
> +			npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> +	}
> +
> +	/* Register clock dividers specified in npcm8xx_divs */
> +	for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> +		const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
> +
> +		hw = clk_hw_register_divider(NULL, div_data->name,
> +					     div_data->parent_name,
> +					     div_data->flags,
> +					     clk_base + div_data->reg,
> +					     div_data->shift, div_data->width,
> +					     div_data->clk_divider_flags,
> +					     &npcm8xx_clk_lock);
> +		if (IS_ERR(hw)) {
> +			pr_err("npcm8xx_clk: Can't register div table\n");
> +			goto npcm8xx_init_fail;
> +		}
> +
> +		if (div_data->onecell_idx >= 0)
> +			npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> +	}
> +
> +	ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> +				     npcm8xx_clk_data);
> +	if (ret)
> +		pr_err("failed to add DT provider: %d\n", ret);
> +
> +	of_node_put(clk_np);
> +
> +	return;
> +
> +npcm8xx_init_fail:
> +	kfree(npcm8xx_clk_data->hws);
> +npcm8xx_init_np_err:
> +	iounmap(clk_base);
> +npcm8xx_init_error:
> +	of_node_put(clk_np);
> +}
> +
> +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);
> 

-- 
 i.

Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Ilpo Järvinen]

On Sun, 22 May 2022, Tomer Maimon wrote:

> Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
> generates and supplies clocks to all modules within the BMC.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

> +static struct clk_hw *
> +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> +			 const char *parent_name, unsigned long flags)
> +{
> +	struct npcm8xx_clk_pll *pll;
> +	struct clk_init_data init;
> +	struct clk_hw *hw;
> +	int ret;
> +
> +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +	if (!pll)
> +		return ERR_PTR(-ENOMEM);
> +
> +	pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> +
> +	init.name = name;
> +	init.ops = &npcm8xx_clk_pll_ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.flags = flags;
> +
> +	pll->pllcon = pllcon;
> +	pll->hw.init = &init;
> +
> +	hw = &pll->hw;
> +
> +	ret = clk_hw_register(NULL, hw);
> +	if (ret) {
> +		kfree(pll);
> +		hw = ERR_PTR(ret);
> +	}
> +
> +	return hw;
> +}
> +
> +#define NPCM8XX_CLKEN1          (0x00)
> +#define NPCM8XX_CLKEN2          (0x28)
> +#define NPCM8XX_CLKEN3          (0x30)
> +#define NPCM8XX_CLKEN4          (0x70)
> +#define NPCM8XX_CLKSEL          (0x04)
> +#define NPCM8XX_CLKDIV1         (0x08)
> +#define NPCM8XX_CLKDIV2         (0x2C)
> +#define NPCM8XX_CLKDIV3         (0x58)
> +#define NPCM8XX_CLKDIV4         (0x7C)
> +#define NPCM8XX_PLLCON0         (0x0C)
> +#define NPCM8XX_PLLCON1         (0x10)
> +#define NPCM8XX_PLLCON2         (0x54)
> +#define NPCM8XX_SWRSTR          (0x14)
> +#define NPCM8XX_IRQWAKECON      (0x18)
> +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> +#define NPCM8XX_IPSRST1         (0x20)
> +#define NPCM8XX_IPSRST2         (0x24)
> +#define NPCM8XX_IPSRST3         (0x34)
> +#define NPCM8XX_WD0RCR          (0x38)
> +#define NPCM8XX_WD1RCR          (0x3C)
> +#define NPCM8XX_WD2RCR          (0x40)
> +#define NPCM8XX_SWRSTC1         (0x44)
> +#define NPCM8XX_SWRSTC2         (0x48)
> +#define NPCM8XX_SWRSTC3         (0x4C)
> +#define NPCM8XX_SWRSTC4         (0x50)
> +#define NPCM8XX_CORSTC          (0x5C)
> +#define NPCM8XX_PLLCONG         (0x60)
> +#define NPCM8XX_AHBCKFI         (0x64)
> +#define NPCM8XX_SECCNT          (0x68)
> +#define NPCM8XX_CNTR25M         (0x6C)
> +#define NPCM8XX_THRTL_CNT       (0xC0)
> +
> +struct npcm8xx_clk_gate_data {
> +	u32 reg;
> +	u8 bit_idx;
> +	const char *name;
> +	const char *parent_name;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_mux_data {
> +	u8 shift;
> +	u8 mask;
> +	u32 *table;
> +	const char *name;
> +	const char * const *parent_names;
> +	u8 num_parents;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +
> +};
> +
> +struct npcm8xx_clk_div_fixed_data {
> +	u8 mult;
> +	u8 div;
> +	const char *name;
> +	const char *parent_name;
> +	u8 clk_divider_flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_div_data {
> +	u32 reg;
> +	u8 shift;
> +	u8 width;
> +	const char *name;
> +	const char *parent_name;
> +	u8 clk_divider_flags;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_pll_data {
> +	u32 reg;
> +	const char *name;
> +	const char *parent_name;
> +	unsigned long flags;
> +	/*
> +	 * If this clock is exported via DT, set onecell_idx to constant
> +	 * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +	 * this specific clock.  Otherwise, set to -1.
> +	 */
> +	int onecell_idx;
> +};
> +


> +/*
> + * Single copy of strings used to refer to clocks within this driver indexed by
> + * above enum.
> + */
> +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> +#define NPCM8XX_CLK_S_PLL0        "pll0"
> +#define NPCM8XX_CLK_S_PLL1        "pll1"
> +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> +#define NPCM8XX_CLK_S_PLL2        "pll2"
> +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/

Add spaces around comment.

> +#define NPCM8XX_CLK_S_MC          "mc"
> +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/

Ditto.

> +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> +{
> +	struct clk_hw_onecell_data *npcm8xx_clk_data;
> +	void __iomem *clk_base;
> +	struct resource res;
> +	struct clk_hw *hw;
> +	int ret;
> +	int i;
> +
> +	ret = of_address_to_resource(clk_np, 0, &res);
> +	if (ret) {
> +		pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
> +		return;
> +	}
> +
> +	clk_base = ioremap(res.start, resource_size(&res));
> +	if (!clk_base)
> +		goto npcm8xx_init_error;
> +
> +	npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> +					       NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> +	if (!npcm8xx_clk_data)
> +		goto npcm8xx_init_np_err;
> +
> +	npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> +
> +	for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> +		npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> +
> +	/* Register plls */
> +	for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> +		const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
> +
> +		hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> +					      pll_data->name,
> +					      pll_data->parent_name,
> +					      pll_data->flags);
> +		if (IS_ERR(hw)) {

Who deregisters the already registered plls on error paths?

You might want to consider devm_ variants in npcm8xx_clk_register_pll() to 
make the cleanup simpler.

Please check the other error path rollbacks from this point onward too.

> +			pr_err("npcm8xx_clk: Can't register pll\n");
> +			goto npcm8xx_init_fail;
> +		}
> +
> +		if (pll_data->onecell_idx >= 0)
> +			npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> +	}
> +
> +	/* Register fixed dividers */
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> +					  NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register fixed div\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> +					  NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register pll div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> +					  NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> +					  NPCM8XX_CLK_S_TH, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register axi div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> +					  NPCM8XX_CLK_S_AXI, 0, 1, 2);
> +	if (IS_ERR(hw)) {
> +		pr_err("npcm8xx_clk: Can't register atb div2\n");
> +		goto npcm8xx_init_fail;
> +	}
> +
> +	/* Register muxes */
> +	for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> +		const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
> +
> +		hw = clk_hw_register_mux_table(NULL, mux_data->name,
> +					       mux_data->parent_names,
> +					       mux_data->num_parents,
> +					       mux_data->flags,
> +					       clk_base + NPCM8XX_CLKSEL,
> +					       mux_data->shift,
> +					       mux_data->mask, 0,
> +					       mux_data->table,
> +					       &npcm8xx_clk_lock);
> +
> +		if (IS_ERR(hw)) {
> +			pr_err("npcm8xx_clk: Can't register mux\n");
> +			goto npcm8xx_init_fail;
> +		}
> +
> +		if (mux_data->onecell_idx >= 0)
> +			npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> +	}
> +
> +	/* Register clock dividers specified in npcm8xx_divs */
> +	for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> +		const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
> +
> +		hw = clk_hw_register_divider(NULL, div_data->name,
> +					     div_data->parent_name,
> +					     div_data->flags,
> +					     clk_base + div_data->reg,
> +					     div_data->shift, div_data->width,
> +					     div_data->clk_divider_flags,
> +					     &npcm8xx_clk_lock);
> +		if (IS_ERR(hw)) {
> +			pr_err("npcm8xx_clk: Can't register div table\n");
> +			goto npcm8xx_init_fail;
> +		}
> +
> +		if (div_data->onecell_idx >= 0)
> +			npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> +	}
> +
> +	ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> +				     npcm8xx_clk_data);
> +	if (ret)
> +		pr_err("failed to add DT provider: %d\n", ret);
> +
> +	of_node_put(clk_np);
> +
> +	return;
> +
> +npcm8xx_init_fail:
> +	kfree(npcm8xx_clk_data->hws);
> +npcm8xx_init_np_err:
> +	iounmap(clk_base);
> +npcm8xx_init_error:
> +	of_node_put(clk_np);
> +}
> +
> +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);
> 

-- 
 i.


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Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Tomer Maimon]

[-- Attachment #1: Type: text/plain, Size: 12978 bytes --]

Hi Ilpo,

Thanks for your comments.

the patch will modify according to your comments and will be sent in the
next kernel revision 5.19.rc1

On Mon, 23 May 2022 at 10:07, Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
wrote:

> On Sun, 22 May 2022, Tomer Maimon wrote:
>
> > Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, which
> > generates and supplies clocks to all modules within the BMC.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>
> > +static struct clk_hw *
> > +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> > +                      const char *parent_name, unsigned long flags)
> > +{
> > +     struct npcm8xx_clk_pll *pll;
> > +     struct clk_init_data init;
> > +     struct clk_hw *hw;
> > +     int ret;
> > +
> > +     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > +     if (!pll)
> > +             return ERR_PTR(-ENOMEM);
> > +
> > +     pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> > +
> > +     init.name = name;
> > +     init.ops = &npcm8xx_clk_pll_ops;
> > +     init.parent_names = &parent_name;
> > +     init.num_parents = 1;
> > +     init.flags = flags;
> > +
> > +     pll->pllcon = pllcon;
> > +     pll->hw.init = &init;
> > +
> > +     hw = &pll->hw;
> > +
> > +     ret = clk_hw_register(NULL, hw);
> > +     if (ret) {
> > +             kfree(pll);
> > +             hw = ERR_PTR(ret);
> > +     }
> > +
> > +     return hw;
> > +}
> > +
> > +#define NPCM8XX_CLKEN1          (0x00)
> > +#define NPCM8XX_CLKEN2          (0x28)
> > +#define NPCM8XX_CLKEN3          (0x30)
> > +#define NPCM8XX_CLKEN4          (0x70)
> > +#define NPCM8XX_CLKSEL          (0x04)
> > +#define NPCM8XX_CLKDIV1         (0x08)
> > +#define NPCM8XX_CLKDIV2         (0x2C)
> > +#define NPCM8XX_CLKDIV3         (0x58)
> > +#define NPCM8XX_CLKDIV4         (0x7C)
> > +#define NPCM8XX_PLLCON0         (0x0C)
> > +#define NPCM8XX_PLLCON1         (0x10)
> > +#define NPCM8XX_PLLCON2         (0x54)
> > +#define NPCM8XX_SWRSTR          (0x14)
> > +#define NPCM8XX_IRQWAKECON      (0x18)
> > +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> > +#define NPCM8XX_IPSRST1         (0x20)
> > +#define NPCM8XX_IPSRST2         (0x24)
> > +#define NPCM8XX_IPSRST3         (0x34)
> > +#define NPCM8XX_WD0RCR          (0x38)
> > +#define NPCM8XX_WD1RCR          (0x3C)
> > +#define NPCM8XX_WD2RCR          (0x40)
> > +#define NPCM8XX_SWRSTC1         (0x44)
> > +#define NPCM8XX_SWRSTC2         (0x48)
> > +#define NPCM8XX_SWRSTC3         (0x4C)
> > +#define NPCM8XX_SWRSTC4         (0x50)
> > +#define NPCM8XX_CORSTC          (0x5C)
> > +#define NPCM8XX_PLLCONG         (0x60)
> > +#define NPCM8XX_AHBCKFI         (0x64)
> > +#define NPCM8XX_SECCNT          (0x68)
> > +#define NPCM8XX_CNTR25M         (0x6C)
> > +#define NPCM8XX_THRTL_CNT       (0xC0)
> > +
> > +struct npcm8xx_clk_gate_data {
> > +     u32 reg;
> > +     u8 bit_idx;
> > +     const char *name;
> > +     const char *parent_name;
> > +     unsigned long flags;
> > +     /*
> > +      * If this clock is exported via DT, set onecell_idx to constant
> > +      * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h
> for
> > +      * this specific clock.  Otherwise, set to -1.
> > +      */
> > +     int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_mux_data {
> > +     u8 shift;
> > +     u8 mask;
> > +     u32 *table;
> > +     const char *name;
> > +     const char * const *parent_names;
> > +     u8 num_parents;
> > +     unsigned long flags;
> > +     /*
> > +      * If this clock is exported via DT, set onecell_idx to constant
> > +      * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h
> for
> > +      * this specific clock.  Otherwise, set to -1.
> > +      */
> > +     int onecell_idx;
> > +
> > +};
> > +
> > +struct npcm8xx_clk_div_fixed_data {
> > +     u8 mult;
> > +     u8 div;
> > +     const char *name;
> > +     const char *parent_name;
> > +     u8 clk_divider_flags;
> > +     /*
> > +      * If this clock is exported via DT, set onecell_idx to constant
> > +      * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h
> for
> > +      * this specific clock.  Otherwise, set to -1.
> > +      */
> > +     int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_div_data {
> > +     u32 reg;
> > +     u8 shift;
> > +     u8 width;
> > +     const char *name;
> > +     const char *parent_name;
> > +     u8 clk_divider_flags;
> > +     unsigned long flags;
> > +     /*
> > +      * If this clock is exported via DT, set onecell_idx to constant
> > +      * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h
> for
> > +      * this specific clock.  Otherwise, set to -1.
> > +      */
> > +     int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_pll_data {
> > +     u32 reg;
> > +     const char *name;
> > +     const char *parent_name;
> > +     unsigned long flags;
> > +     /*
> > +      * If this clock is exported via DT, set onecell_idx to constant
> > +      * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h
> for
> > +      * this specific clock.  Otherwise, set to -1.
> > +      */
> > +     int onecell_idx;
> > +};
> > +
>
>
> > +/*
> > + * Single copy of strings used to refer to clocks within this driver
> indexed by
> > + * above enum.
> > + */
> > +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> > +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> > +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> > +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> > +#define NPCM8XX_CLK_S_PLL0        "pll0"
> > +#define NPCM8XX_CLK_S_PLL1        "pll1"
> > +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> > +#define NPCM8XX_CLK_S_PLL2        "pll2"
> > +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> > +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> > +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> > +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> > +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> > +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
>
> Add spaces around comment.
>
> > +#define NPCM8XX_CLK_S_MC          "mc"
> > +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> > +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
>
> Ditto.
>
> > +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> > +{
> > +     struct clk_hw_onecell_data *npcm8xx_clk_data;
> > +     void __iomem *clk_base;
> > +     struct resource res;
> > +     struct clk_hw *hw;
> > +     int ret;
> > +     int i;
> > +
> > +     ret = of_address_to_resource(clk_np, 0, &res);
> > +     if (ret) {
> > +             pr_err("%pOFn: failed to get resource, ret %d\n", clk_np,
> ret);
> > +             return;
> > +     }
> > +
> > +     clk_base = ioremap(res.start, resource_size(&res));
> > +     if (!clk_base)
> > +             goto npcm8xx_init_error;
> > +
> > +     npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> > +                                            NPCM8XX_NUM_CLOCKS),
> GFP_KERNEL);
> > +     if (!npcm8xx_clk_data)
> > +             goto npcm8xx_init_np_err;
> > +
> > +     npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> > +
> > +     for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> > +             npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> > +
> > +     /* Register plls */
> > +     for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> > +             const struct npcm8xx_clk_pll_data *pll_data =
> &npcm8xx_plls[i];
> > +
> > +             hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> > +                                           pll_data->name,
> > +                                           pll_data->parent_name,
> > +                                           pll_data->flags);
> > +             if (IS_ERR(hw)) {
>
> Who deregisters the already registered plls on error paths?
>
> You might want to consider devm_ variants in npcm8xx_clk_register_pll() to
> make the cleanup simpler.
>
> Please check the other error path rollbacks from this point onward too.


> > +                     pr_err("npcm8xx_clk: Can't register pll\n");
> > +                     goto npcm8xx_init_fail;
> > +             }
> > +
> > +             if (pll_data->onecell_idx >= 0)
> > +                     npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> > +     }
> > +
> > +     /* Register fixed dividers */
> > +     hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> > +                                       NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> > +     if (IS_ERR(hw)) {
> > +             pr_err("npcm8xx_clk: Can't register fixed div\n");
> > +             goto npcm8xx_init_fail;
> > +     }
> > +
> > +     hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> > +                                       NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> > +     if (IS_ERR(hw)) {
> > +             pr_err("npcm8xx_clk: Can't register pll div2\n");
> > +             goto npcm8xx_init_fail;
> > +     }
> > +
> > +     hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> > +                                       NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> > +     if (IS_ERR(hw)) {
> > +             pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> > +             goto npcm8xx_init_fail;
> > +     }
> > +
> > +     hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> > +                                       NPCM8XX_CLK_S_TH, 0, 1, 2);
> > +     if (IS_ERR(hw)) {
> > +             pr_err("npcm8xx_clk: Can't register axi div2\n");
> > +             goto npcm8xx_init_fail;
> > +     }
> > +
> > +     hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> > +                                       NPCM8XX_CLK_S_AXI, 0, 1, 2);
> > +     if (IS_ERR(hw)) {
> > +             pr_err("npcm8xx_clk: Can't register atb div2\n");
> > +             goto npcm8xx_init_fail;
> > +     }
> > +
> > +     /* Register muxes */
> > +     for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> > +             const struct npcm8xx_clk_mux_data *mux_data =
> &npcm8xx_muxes[i];
> > +
> > +             hw = clk_hw_register_mux_table(NULL, mux_data->name,
> > +                                            mux_data->parent_names,
> > +                                            mux_data->num_parents,
> > +                                            mux_data->flags,
> > +                                            clk_base + NPCM8XX_CLKSEL,
> > +                                            mux_data->shift,
> > +                                            mux_data->mask, 0,
> > +                                            mux_data->table,
> > +                                            &npcm8xx_clk_lock);
> > +
> > +             if (IS_ERR(hw)) {
> > +                     pr_err("npcm8xx_clk: Can't register mux\n");
> > +                     goto npcm8xx_init_fail;
> > +             }
> > +
> > +             if (mux_data->onecell_idx >= 0)
> > +                     npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> > +     }
> > +
> > +     /* Register clock dividers specified in npcm8xx_divs */
> > +     for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> > +             const struct npcm8xx_clk_div_data *div_data =
> &npcm8xx_divs[i];
> > +
> > +             hw = clk_hw_register_divider(NULL, div_data->name,
> > +                                          div_data->parent_name,
> > +                                          div_data->flags,
> > +                                          clk_base + div_data->reg,
> > +                                          div_data->shift,
> div_data->width,
> > +                                          div_data->clk_divider_flags,
> > +                                          &npcm8xx_clk_lock);
> > +             if (IS_ERR(hw)) {
> > +                     pr_err("npcm8xx_clk: Can't register div table\n");
> > +                     goto npcm8xx_init_fail;
> > +             }
> > +
> > +             if (div_data->onecell_idx >= 0)
> > +                     npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> > +     }
> > +
> > +     ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> > +                                  npcm8xx_clk_data);
> > +     if (ret)
> > +             pr_err("failed to add DT provider: %d\n", ret);
> > +
> > +     of_node_put(clk_np);
> > +
> > +     return;
> > +
> > +npcm8xx_init_fail:
> > +     kfree(npcm8xx_clk_data->hws);
> > +npcm8xx_init_np_err:
> > +     iounmap(clk_base);
> > +npcm8xx_init_error:
> > +     of_node_put(clk_np);
> > +}
> > +
> > +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk",
> npcm8xx_clk_init);
> >
>
> --
>  i.
>
>
Best regards,

Tomer

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Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Stephen Boyd]

Quoting Tomer Maimon (2022-05-22 08:50:35)
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 5d596e778ff4..b9f3202de872 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -414,6 +414,13 @@ config COMMON_CLK_K210
>         help
>           Support for the Canaan Kendryte K210 RISC-V SoC clocks.
>  
> +config COMMON_CLK_NPCM8XX
> +       tristate "Clock driver for the NPCM8XX SoC Family"
> +       depends on ARCH_NPCM || COMPILE_TEST
> +       depends on OF

What depends on OF? Presumably it builds even when OF is disabled.

> +       help
> +          This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family.
> +
>  source "drivers/clk/actions/Kconfig"
>  source "drivers/clk/analogbits/Kconfig"
>  source "drivers/clk/baikal-t1/Kconfig"
> diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> new file mode 100644
> index 000000000000..6d0ab7f97ae6
> --- /dev/null
> +++ b/drivers/clk/clk-npcm8xx.c
> @@ -0,0 +1,767 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Nuvoton NPCM8xx Clock Generator
> + * All the clocks are initialized by the bootloader, so this driver allow only
> + * reading of current settings directly from the hardware.
> + *
> + * Copyright (C) 2020 Nuvoton Technologies tomer.maimon@nuvoton.com
> + */
> +
> +#include <asm/cputype.h>

What is this include for?

> +#include <linux/module.h>

It isn't a module though. Compiling the driver as a module will
(hopefully) fail.

> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/bitfield.h>

Please sort includes alphabetically.

> +
> +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>

This should stay at the end though.

> +
> +struct npcm8xx_clk_pll {
> +       struct clk_hw   hw;
> +       void __iomem    *pllcon;
> +       u8              flags;
> +};
> +
> +#define to_npcm8xx_clk_pll(_hw) container_of(_hw, struct npcm8xx_clk_pll, hw)
> +
> +#define PLLCON_LOKI    BIT(31)
> +#define PLLCON_LOKS    BIT(30)
> +#define PLLCON_FBDV    GENMASK(27, 16)
> +#define PLLCON_OTDV2   GENMASK(15, 13)
> +#define PLLCON_PWDEN   BIT(12)
> +#define PLLCON_OTDV1   GENMASK(10, 8)
> +#define PLLCON_INDV    GENMASK(5, 0)
> +
> +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
> +                                                unsigned long parent_rate)
> +{
> +       struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
> +       unsigned long fbdv, indv, otdv1, otdv2;
> +       unsigned int val;
> +       u64 ret;
> +
> +       if (parent_rate == 0) {
> +               pr_err("%s: parent rate is zero", __func__);

This can happen because of registration logic, so downgrade to
pr_debug() or just remove entirely and return 0.

> +               return 0;
> +       }
> +
> +       val = readl_relaxed(pll->pllcon);
> +
> +       indv = FIELD_GET(PLLCON_INDV, val);
> +       fbdv = FIELD_GET(PLLCON_FBDV, val);
> +       otdv1 = FIELD_GET(PLLCON_OTDV1, val);
> +       otdv2 = FIELD_GET(PLLCON_OTDV2, val);
> +
> +       ret = (u64)parent_rate * fbdv;
> +       do_div(ret, indv * otdv1 * otdv2);

Does that indv * otdv1 * otdv2 ever overflow 32-bits?

> +
> +       return ret;
> +}
> +
> +static const struct clk_ops npcm8xx_clk_pll_ops = {
> +       .recalc_rate = npcm8xx_clk_pll_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> +                        const char *parent_name, unsigned long flags)
> +{
> +       struct npcm8xx_clk_pll *pll;
> +       struct clk_init_data init;
> +       struct clk_hw *hw;
> +       int ret;
> +
> +       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +       if (!pll)
> +               return ERR_PTR(-ENOMEM);
> +
> +       pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> +
> +       init.name = name;
> +       init.ops = &npcm8xx_clk_pll_ops;
> +       init.parent_names = &parent_name;
> +       init.num_parents = 1;
> +       init.flags = flags;
> +
> +       pll->pllcon = pllcon;
> +       pll->hw.init = &init;
> +
> +       hw = &pll->hw;
> +
> +       ret = clk_hw_register(NULL, hw);
> +       if (ret) {
> +               kfree(pll);
> +               hw = ERR_PTR(ret);
> +       }
> +
> +       return hw;
> +}
> +
> +#define NPCM8XX_CLKEN1          (0x00)
> +#define NPCM8XX_CLKEN2          (0x28)
> +#define NPCM8XX_CLKEN3          (0x30)
> +#define NPCM8XX_CLKEN4          (0x70)
> +#define NPCM8XX_CLKSEL          (0x04)
> +#define NPCM8XX_CLKDIV1         (0x08)
> +#define NPCM8XX_CLKDIV2         (0x2C)
> +#define NPCM8XX_CLKDIV3         (0x58)
> +#define NPCM8XX_CLKDIV4         (0x7C)
> +#define NPCM8XX_PLLCON0         (0x0C)
> +#define NPCM8XX_PLLCON1         (0x10)
> +#define NPCM8XX_PLLCON2         (0x54)
> +#define NPCM8XX_SWRSTR          (0x14)
> +#define NPCM8XX_IRQWAKECON      (0x18)
> +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> +#define NPCM8XX_IPSRST1         (0x20)
> +#define NPCM8XX_IPSRST2         (0x24)
> +#define NPCM8XX_IPSRST3         (0x34)
> +#define NPCM8XX_WD0RCR          (0x38)
> +#define NPCM8XX_WD1RCR          (0x3C)
> +#define NPCM8XX_WD2RCR          (0x40)
> +#define NPCM8XX_SWRSTC1         (0x44)
> +#define NPCM8XX_SWRSTC2         (0x48)
> +#define NPCM8XX_SWRSTC3         (0x4C)
> +#define NPCM8XX_SWRSTC4         (0x50)
> +#define NPCM8XX_CORSTC          (0x5C)
> +#define NPCM8XX_PLLCONG         (0x60)
> +#define NPCM8XX_AHBCKFI         (0x64)
> +#define NPCM8XX_SECCNT          (0x68)
> +#define NPCM8XX_CNTR25M         (0x6C)
> +#define NPCM8XX_THRTL_CNT       (0xC0)
> +
> +struct npcm8xx_clk_gate_data {
> +       u32 reg;
> +       u8 bit_idx;
> +       const char *name;
> +       const char *parent_name;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_mux_data {
> +       u8 shift;
> +       u8 mask;
> +       u32 *table;
> +       const char *name;
> +       const char * const *parent_names;
> +       u8 num_parents;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +
> +};
> +
> +struct npcm8xx_clk_div_fixed_data {
> +       u8 mult;
> +       u8 div;
> +       const char *name;
> +       const char *parent_name;
> +       u8 clk_divider_flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_div_data {
> +       u32 reg;
> +       u8 shift;
> +       u8 width;
> +       const char *name;
> +       const char *parent_name;
> +       u8 clk_divider_flags;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_pll_data {
> +       u32 reg;
> +       const char *name;
> +       const char *parent_name;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +/*
> + * Single copy of strings used to refer to clocks within this driver indexed by
> + * above enum.
> + */
> +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> +#define NPCM8XX_CLK_S_PLL0        "pll0"
> +#define NPCM8XX_CLK_S_PLL1        "pll1"
> +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> +#define NPCM8XX_CLK_S_PLL2        "pll2"
> +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
> +#define NPCM8XX_CLK_S_MC          "mc"
> +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
> +#define NPCM8XX_CLK_S_CLKOUT_MUX  "clkout_mux"
> +#define NPCM8XX_CLK_S_UART_MUX    "uart_mux"
> +#define NPCM8XX_CLK_S_UART2_MUX   "uart2_mux"
> +#define NPCM8XX_CLK_S_TIM_MUX     "timer_mux"
> +#define NPCM8XX_CLK_S_PRE_ADC_MUX "pre_adc_mux"
> +#define NPCM8XX_CLK_S_SD_MUX      "sd_mux"
> +#define NPCM8XX_CLK_S_GFXM_MUX    "gfxm_mux"
> +#define NPCM8XX_CLK_S_SU_MUX      "serial_usb_mux"
> +#define NPCM8XX_CLK_S_DVC_MUX     "dvc_mux"
> +#define NPCM8XX_CLK_S_GFX_MUX     "gfx_mux"
> +#define NPCM8XX_CLK_S_ADC_MUX     "adc_mux"
> +#define NPCM8XX_CLK_S_GFX_PIXEL   "gfx_pixel"
> +#define NPCM8XX_CLK_S_SPI0        "spi0"
> +#define NPCM8XX_CLK_S_SPI1        "spi1"
> +#define NPCM8XX_CLK_S_SPI3        "spi3"
> +#define NPCM8XX_CLK_S_SPIX        "spix"
> +#define NPCM8XX_CLK_S_APB1        "apb1"
> +#define NPCM8XX_CLK_S_APB2        "apb2"
> +#define NPCM8XX_CLK_S_APB3        "apb3"
> +#define NPCM8XX_CLK_S_APB4        "apb4"
> +#define NPCM8XX_CLK_S_APB5        "apb5"
> +#define NPCM8XX_CLK_S_APB19       "apb19"
> +#define NPCM8XX_CLK_S_TOCK        "tock"
> +#define NPCM8XX_CLK_S_CLKOUT      "clkout"
> +#define NPCM8XX_CLK_S_PRE_ADC     "pre adc"
> +#define NPCM8XX_CLK_S_UART        "uart"
> +#define NPCM8XX_CLK_S_UART2       "uart2"
> +#define NPCM8XX_CLK_S_TIMER       "timer"
> +#define NPCM8XX_CLK_S_MMC         "mmc"
> +#define NPCM8XX_CLK_S_SDHC        "sdhc"
> +#define NPCM8XX_CLK_S_ADC         "adc"
> +#define NPCM8XX_CLK_S_AMBA        "amba"
> +#define NPCM8XX_CLK_S_GFX         "gfx0_gfx1_mem"
> +#define NPCM8XX_CLK_S_USBIF       "serial_usbif"
> +#define NPCM8XX_CLK_S_USB_HOST    "usb_host"
> +#define NPCM8XX_CLK_S_USB_BRIDGE  "usb_bridge"
> +#define NPCM8XX_CLK_S_PCI         "pci"
> +#define NPCM8XX_CLK_S_TH          "th"
> +#define NPCM8XX_CLK_S_ATB         "atb"
> +#define NPCM8XX_CLK_S_PRE_CLK     "pre_clk"
> +
> +#define NPCM8XX_CLK_S_RG_MUX     "rg_mux"
> +#define NPCM8XX_CLK_S_RCP_MUX    "rcp_mux"
> +#define NPCM8XX_CLK_S_RG         "rg"
> +#define NPCM8XX_CLK_S_RCP        "rcp"

I suspect these defines will largely go away.

> +
> +static u32 pll_mux_table[] = {0, 1, 2, 3};
> +static const char * const pll_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL0,
> +       NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 cpuck_mux_table[] = {0, 1, 2, 3, 7};
> +static const char * const cpuck_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL0,
> +       NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_SYSBYPCK,
> +       NPCM8XX_CLK_S_PLL2,
> +};
> +
> +static u32 pixcksel_mux_table[] = {0, 2};
> +static const char * const pixcksel_mux_parents[] __initconst = {

Please use clk_parent_data instead of this.

> +       NPCM8XX_CLK_S_PLL_GFX,
> +       NPCM8XX_CLK_S_REFCLK,
> +};
> +
> +static u32 sucksel_mux_table[] = {2, 3};
> +static const char * const sucksel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 mccksel_mux_table[] = {0, 2, 3};
> +static const char * const mccksel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL1_DIV2,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_MCBYPCK,
> +};
> +
> +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
> +static const char * const clkoutsel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL0,
> +       NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL_GFX, // divided by 2
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 gfxmsel_mux_table[] = {2, 3};
> +static const char * const gfxmsel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 dvcssel_mux_table[] = {2, 3};

Use checkpatch, add space around { and } for arrays.

> +static const char * const dvcssel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2,
> +};
> +
> +static const struct npcm8xx_clk_pll_data npcm8xx_plls[] __initconst = {
> +       {NPCM8XX_PLLCON0, NPCM8XX_CLK_S_PLL0, NPCM8XX_CLK_S_REFCLK, 0, -1},
> +
> +       {NPCM8XX_PLLCON1, NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> +
> +       {NPCM8XX_PLLCON2, NPCM8XX_CLK_S_PLL2,
> +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> +
> +       {NPCM8XX_PLLCONG, NPCM8XX_CLK_S_PLL_GFX,
> +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> +};
> +
> +static const struct npcm8xx_clk_mux_data npcm8xx_muxes[] __initconst = {
> +       {0, GENMASK(1, 0), cpuck_mux_table, NPCM8XX_CLK_S_CPU_MUX,
> +       cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
> +       NPCM8XX_CLK_CPU},
> +
> +       {4, GENMASK(1, 0), pixcksel_mux_table, NPCM8XX_CLK_S_PIX_MUX,
> +       pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
> +       NPCM8XX_CLK_GFX_PIXEL},
> +
> +       {6, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_SD_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {8, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_UART_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {10, GENMASK(1, 0), sucksel_mux_table, NPCM8XX_CLK_S_SU_MUX,
> +       sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
> +
> +       {12, GENMASK(1, 0), mccksel_mux_table, NPCM8XX_CLK_S_MC_MUX,
> +       mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
> +
> +       {14, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_ADC_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {16, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_GFX_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM8XX_CLK_S_CLKOUT_MUX,
> +       clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
> +
> +       {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM8XX_CLK_S_GFXM_MUX,
> +       gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
> +
> +       {23, GENMASK(1, 0), dvcssel_mux_table, NPCM8XX_CLK_S_DVC_MUX,
> +       dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
> +
> +       {25, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RG_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {27, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RCP_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +};
> +
> +/* fixed ratio dividers (no register): */
> +static const struct npcm8xx_clk_div_fixed_data npcm8xx_divs_fx[] __initconst = {
> +       { 1, 2, NPCM8XX_CLK_S_MC, NPCM8XX_CLK_S_MC_MUX, 0, NPCM8XX_CLK_MC},
> +       { 1, 2, NPCM8XX_CLK_S_AXI, NPCM8XX_CLK_S_TH, 0, NPCM8XX_CLK_AXI},
> +       { 1, 2, NPCM8XX_CLK_S_ATB, NPCM8XX_CLK_S_AXI, 0, NPCM8XX_CLK_ATB},
> +       { 1, 2, NPCM8XX_CLK_S_PRE_CLK, NPCM8XX_CLK_S_CPU_MUX, 0, -1},
> +       { 1, 2, NPCM8XX_CLK_S_PLL1_DIV2, NPCM8XX_CLK_S_PLL1, 0, -1},
> +       { 1, 2, NPCM8XX_CLK_S_PLL2_DIV2, NPCM8XX_CLK_S_PLL2, 0, -1},
> +};
> +
> +/* configurable dividers: */
> +static const struct npcm8xx_clk_div_data npcm8xx_divs[] __initconst = {
> +       {NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, NPCM8XX_CLK_S_PRE_ADC,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_ADC},
> +       /*30-28 ADCCKDIV*/

What are the numbers for? Bits inside the register?

> +       {NPCM8XX_CLKDIV1, 26, 2, NPCM8XX_CLK_S_AHB, NPCM8XX_CLK_S_PRE_CLK,
> +               CLK_DIVIDER_READ_ONLY, CLK_IS_CRITICAL, NPCM8XX_CLK_AHB},
> +       /*28-26 CLK4DIV*/
> +       {NPCM8XX_CLKDIV1, 21, 5, NPCM8XX_CLK_S_PRE_ADC,
> +       NPCM8XX_CLK_S_ADC_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PRE_ADC},
> +       /*25-21 PRE-ADCCKDIV*/
> +       {NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART,
> +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART},
> +       /*20-16 UARTDIV*/
> +       {NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC,
> +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC},
> +       /*15-11 MMCCKDIV*/
> +       {NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3,
> +       NPCM8XX_CLK_S_AHB, 0, 0, NPCM8XX_CLK_SPI3},
> +       /*10-6 AHB3CKDIV*/
> +       {NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI,
> +       NPCM8XX_CLK_S_GFX_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI},
> +       /*5-2 PCICKDIV*/
> +
> +       {NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB4},
> +       /*31-30 APB4CKDIV*/
> +       {NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB3},
> +       /*29-28 APB3CKDIV*/
> +       {NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB2},
> +       /*28-26 APB2CKDIV*/
> +       {NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB1},
> +       /*25-24 APB1CKDIV*/
> +       {NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB5},
> +       /*23-22 APB5CKDIV*/
> +       {NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, NPCM8XX_CLK_S_CLKOUT_MUX,
> +                CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT},
> +       /*20-16 CLKOUTDIV*/
> +       {NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, NPCM8XX_CLK_S_GFX_MUX,
> +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX},
> +       /*15-13 GFXCKDIV*/
> +       {NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, NPCM8XX_CLK_S_SU_MUX,
> +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU},
> +       /*12-8 SUCKDIV*/
> +       {NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, NPCM8XX_CLK_S_SU_MUX,
> +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48},
> +       /*8-4 SU48CKDIV*/
> +       {NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC,
> +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC}
> +       ,/*3-0 SD1CKDIV*/
> +
> +       {NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1,
> +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1},
> +       /*23-16 SPI1CKDV*/
> +       {NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2,
> +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2},
> +       /*15-11 UARTDIV2*/
> +       {NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0,
> +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0},
> +       /*10-6 SPI0CKDV*/
> +       {NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX,
> +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX},
> +
> +       /*5-1 SPIXCKDV*/
> +       {NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, NPCM8XX_CLK_S_RG_MUX,
> +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG},
> +
> +       /*31-28 RGREFDIV*/
> +       {NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, NPCM8XX_CLK_S_RCP_MUX,
> +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP},
> +
> +       /*15-12 RCPREFDIV*/
> +       {NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, NPCM8XX_CLK_S_CPU_MUX,
> +       CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH},
> +       /*1-0 TH_DIV*/
> +};
> +
> +static const struct npcm8xx_clk_gate_data npcm8xx_gates[] __initconst = {
> +       {NPCM8XX_CLKEN1, 31, "smb1-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 30, "smb0-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 29, "smb7-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 28, "smb6-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 27, "adc-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 26, "wdt-gate", NPCM8XX_CLK_S_TIMER, 0},
> +       {NPCM8XX_CLKEN1, 25, "usbdev3-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 24, "usbdev6-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 23, "usbdev5-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 22, "usbdev4-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 21, "gmac4-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 20, "timer5_9-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 19, "timer0_4-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 18, "pwmm0-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN1, 17, "huart-gate", NPCM8XX_CLK_S_UART, 0},
> +       {NPCM8XX_CLKEN1, 16, "smb5-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 15, "smb4-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 14, "smb3-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 13, "smb2-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 12, "mc-gate", NPCM8XX_CLK_S_MC, 0},
> +       {NPCM8XX_CLKEN1, 11, "uart01-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 10, "aes-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 9, "peci-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN1, 8, "usbdev2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 7, "uart23-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 6, "gmac3-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 5, "usbdev1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 4, "shm-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 3, "gdma0-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 2, "kcs-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 1, "spi3-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 0, "spi0-gate", NPCM8XX_CLK_S_AHB, 0},
> +
> +       {NPCM8XX_CLKEN2, 31, "cp-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 30, "tock-gate", NPCM8XX_CLK_S_TOCK, 0},
> +       /* bit 29 is reserved */
> +       {NPCM8XX_CLKEN2, 28, "gmac1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 27, "usbif-gate", NPCM8XX_CLK_S_USBIF, 0},
> +       {NPCM8XX_CLKEN2, 26, "usbhost1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 25, "gmac2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 24, "spi1-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN2, 23, "pspi2-gate", NPCM8XX_CLK_S_APB5, 0},
> +       /* bit 22 is reserved */
> +       {NPCM8XX_CLKEN2, 21, "3des-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 20, "bt-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN2, 19, "siox2-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN2, 18, "siox1-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN2, 17, "viruart2-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN2, 16, "viruart1-gate", NPCM8XX_CLK_S_APB5, 0},
> +       /*  bit 15 is reserved */
> +       {NPCM8XX_CLKEN2, 14, "vcd-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 13, "ece-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 12, "vdma-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 10, "gfxsys-gate", NPCM8XX_CLK_S_APB1, 0},
> +       //{NPCM8XX_CLKEN2, 9, "sdhc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       /*  bit 9 is reserved */
> +       {NPCM8XX_CLKEN2, 8, "mmc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 7, "mft7-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 6, "mft6-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 5, "mft5-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 4, "mft4-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 3, "mft3-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 2, "mft2-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 1, "mft1-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 0, "mft0-gate", NPCM8XX_CLK_S_APB4, 0},
> +
> +       {NPCM8XX_CLKEN3, 31, "gpiom7-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 30, "gpiom6-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 29, "gpiom5-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 28, "gpiom4-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 27, "gpiom3-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 26, "gpiom2-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 25, "gpiom1-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 24, "gpiom0-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 23, "espi-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 22, "smb11-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 21, "smb10-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 20, "smb9-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 19, "smb8-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 18, "smb15-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 17, "rng-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 16, "timer10_14-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 15, "pcirc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 14, "sececc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 13, "sha-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 12, "smb14-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 11, "gdma2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 10, "gdma1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 9, "pcimbx-gate", NPCM8XX_CLK_S_AHB, 0},
> +       /* bit 8 is reserved */
> +       {NPCM8XX_CLKEN3, 7, "usbdev9-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 6, "usbdev8-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 5, "usbdev7-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 4, "usbdev0-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 3, "smb13-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 2, "spix-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 1, "smb12-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 0, "pwmm1-gate", NPCM8XX_CLK_S_APB3, 0},
> +
> +       {NPCM8XX_CLKEN4, 31, "usbhost2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN4, 30, "jtm2-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN4, 29, "jtm1-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN4, 28, "pwmm2-gate", NPCM8XX_CLK_S_APB3, 0},
> +       /* bit 27 is reserved */
> +       /* bit 26 is reserved */
> +       /* bit 25 is reserved */
> +       {NPCM8XX_CLKEN4, 24, "smb26-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 23, "smb25-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 22, "smb24-gate", NPCM8XX_CLK_S_APB19, 0},
> +       /* bit 21 is reserved */
> +       /* bit 20 is reserved */
> +       {NPCM8XX_CLKEN4, 19, "pcimbx2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN4, 18, "uart6-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN4, 17, "uart5-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN4, 16, "uart4-gate", NPCM8XX_CLK_S_APB1, 0},
> +       /* bit 15 is reserved */
> +       /* bit 14 is reserved */
> +       {NPCM8XX_CLKEN4, 13, "i3c5-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 12, "i3c4-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 11, "i3c3-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 10, "i3c2-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 9, "i3c1-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 8, "i3c0-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 7, "smb23-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 6, "smb22-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 5, "smb21-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 4, "smb20-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 3, "smb19-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 2, "smb18-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 1, "smb17-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 0, "smb16-gate", NPCM8XX_CLK_S_APB19, 0},
> +
> +};
> +
> +static DEFINE_SPINLOCK(npcm8xx_clk_lock);

Preferably this lock isn't global.

> +
> +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> +{
> +       struct clk_hw_onecell_data *npcm8xx_clk_data;
> +       void __iomem *clk_base;
> +       struct resource res;
> +       struct clk_hw *hw;
> +       int ret;
> +       int i;
> +
> +       ret = of_address_to_resource(clk_np, 0, &res);
> +       if (ret) {
> +               pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
> +               return;
> +       }
> +
> +       clk_base = ioremap(res.start, resource_size(&res));
> +       if (!clk_base)
> +               goto npcm8xx_init_error;
> +
> +       npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> +                                              NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> +       if (!npcm8xx_clk_data)
> +               goto npcm8xx_init_np_err;
> +
> +       npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> +
> +       for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> +               npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> +
> +       /* Register plls */
> +       for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> +               const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
> +
> +               hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> +                                             pll_data->name,
> +                                             pll_data->parent_name,
> +                                             pll_data->flags);
> +               if (IS_ERR(hw)) {
> +                       pr_err("npcm8xx_clk: Can't register pll\n");
> +                       goto npcm8xx_init_fail;
> +               }
> +
> +               if (pll_data->onecell_idx >= 0)
> +                       npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> +       }
> +
> +       /* Register fixed dividers */
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> +                                         NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register fixed div\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> +                                         NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register pll div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> +                                         NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> +                                         NPCM8XX_CLK_S_TH, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register axi div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> +                                         NPCM8XX_CLK_S_AXI, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register atb div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       /* Register muxes */
> +       for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> +               const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
> +
> +               hw = clk_hw_register_mux_table(NULL, mux_data->name,
> +                                              mux_data->parent_names,
> +                                              mux_data->num_parents,
> +                                              mux_data->flags,
> +                                              clk_base + NPCM8XX_CLKSEL,
> +                                              mux_data->shift,
> +                                              mux_data->mask, 0,
> +                                              mux_data->table,
> +                                              &npcm8xx_clk_lock);
> +
> +               if (IS_ERR(hw)) {
> +                       pr_err("npcm8xx_clk: Can't register mux\n");
> +                       goto npcm8xx_init_fail;
> +               }
> +
> +               if (mux_data->onecell_idx >= 0)
> +                       npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> +       }
> +
> +       /* Register clock dividers specified in npcm8xx_divs */
> +       for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> +               const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
> +
> +               hw = clk_hw_register_divider(NULL, div_data->name,
> +                                            div_data->parent_name,
> +                                            div_data->flags,
> +                                            clk_base + div_data->reg,
> +                                            div_data->shift, div_data->width,
> +                                            div_data->clk_divider_flags,
> +                                            &npcm8xx_clk_lock);
> +               if (IS_ERR(hw)) {
> +                       pr_err("npcm8xx_clk: Can't register div table\n");
> +                       goto npcm8xx_init_fail;
> +               }
> +
> +               if (div_data->onecell_idx >= 0)
> +                       npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> +       }
> +
> +       ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> +                                    npcm8xx_clk_data);
> +       if (ret)
> +               pr_err("failed to add DT provider: %d\n", ret);
> +
> +       of_node_put(clk_np);
> +
> +       return;
> +
> +npcm8xx_init_fail:
> +       kfree(npcm8xx_clk_data->hws);

Why only hws and not the entire npcm8xx_clk_data? Also, this error path
fails to unregister clks on error. Probably devm usage will help make
all of this code go away.

> +npcm8xx_init_np_err:
> +       iounmap(clk_base);
> +npcm8xx_init_error:
> +       of_node_put(clk_np);

What is this of_node_put() associated with in this function?

> +}
> +
> +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);

This should be made into a platform device driver and platform device
APIs should be used throughout.

Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Stephen Boyd]

Quoting Tomer Maimon (2022-05-22 08:50:35)
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 5d596e778ff4..b9f3202de872 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -414,6 +414,13 @@ config COMMON_CLK_K210
>         help
>           Support for the Canaan Kendryte K210 RISC-V SoC clocks.
>  
> +config COMMON_CLK_NPCM8XX
> +       tristate "Clock driver for the NPCM8XX SoC Family"
> +       depends on ARCH_NPCM || COMPILE_TEST
> +       depends on OF

What depends on OF? Presumably it builds even when OF is disabled.

> +       help
> +          This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family.
> +
>  source "drivers/clk/actions/Kconfig"
>  source "drivers/clk/analogbits/Kconfig"
>  source "drivers/clk/baikal-t1/Kconfig"
> diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> new file mode 100644
> index 000000000000..6d0ab7f97ae6
> --- /dev/null
> +++ b/drivers/clk/clk-npcm8xx.c
> @@ -0,0 +1,767 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Nuvoton NPCM8xx Clock Generator
> + * All the clocks are initialized by the bootloader, so this driver allow only
> + * reading of current settings directly from the hardware.
> + *
> + * Copyright (C) 2020 Nuvoton Technologies tomer.maimon@nuvoton.com
> + */
> +
> +#include <asm/cputype.h>

What is this include for?

> +#include <linux/module.h>

It isn't a module though. Compiling the driver as a module will
(hopefully) fail.

> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/bitfield.h>

Please sort includes alphabetically.

> +
> +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>

This should stay at the end though.

> +
> +struct npcm8xx_clk_pll {
> +       struct clk_hw   hw;
> +       void __iomem    *pllcon;
> +       u8              flags;
> +};
> +
> +#define to_npcm8xx_clk_pll(_hw) container_of(_hw, struct npcm8xx_clk_pll, hw)
> +
> +#define PLLCON_LOKI    BIT(31)
> +#define PLLCON_LOKS    BIT(30)
> +#define PLLCON_FBDV    GENMASK(27, 16)
> +#define PLLCON_OTDV2   GENMASK(15, 13)
> +#define PLLCON_PWDEN   BIT(12)
> +#define PLLCON_OTDV1   GENMASK(10, 8)
> +#define PLLCON_INDV    GENMASK(5, 0)
> +
> +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
> +                                                unsigned long parent_rate)
> +{
> +       struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
> +       unsigned long fbdv, indv, otdv1, otdv2;
> +       unsigned int val;
> +       u64 ret;
> +
> +       if (parent_rate == 0) {
> +               pr_err("%s: parent rate is zero", __func__);

This can happen because of registration logic, so downgrade to
pr_debug() or just remove entirely and return 0.

> +               return 0;
> +       }
> +
> +       val = readl_relaxed(pll->pllcon);
> +
> +       indv = FIELD_GET(PLLCON_INDV, val);
> +       fbdv = FIELD_GET(PLLCON_FBDV, val);
> +       otdv1 = FIELD_GET(PLLCON_OTDV1, val);
> +       otdv2 = FIELD_GET(PLLCON_OTDV2, val);
> +
> +       ret = (u64)parent_rate * fbdv;
> +       do_div(ret, indv * otdv1 * otdv2);

Does that indv * otdv1 * otdv2 ever overflow 32-bits?

> +
> +       return ret;
> +}
> +
> +static const struct clk_ops npcm8xx_clk_pll_ops = {
> +       .recalc_rate = npcm8xx_clk_pll_recalc_rate,
> +};
> +
> +static struct clk_hw *
> +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> +                        const char *parent_name, unsigned long flags)
> +{
> +       struct npcm8xx_clk_pll *pll;
> +       struct clk_init_data init;
> +       struct clk_hw *hw;
> +       int ret;
> +
> +       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> +       if (!pll)
> +               return ERR_PTR(-ENOMEM);
> +
> +       pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> +
> +       init.name = name;
> +       init.ops = &npcm8xx_clk_pll_ops;
> +       init.parent_names = &parent_name;
> +       init.num_parents = 1;
> +       init.flags = flags;
> +
> +       pll->pllcon = pllcon;
> +       pll->hw.init = &init;
> +
> +       hw = &pll->hw;
> +
> +       ret = clk_hw_register(NULL, hw);
> +       if (ret) {
> +               kfree(pll);
> +               hw = ERR_PTR(ret);
> +       }
> +
> +       return hw;
> +}
> +
> +#define NPCM8XX_CLKEN1          (0x00)
> +#define NPCM8XX_CLKEN2          (0x28)
> +#define NPCM8XX_CLKEN3          (0x30)
> +#define NPCM8XX_CLKEN4          (0x70)
> +#define NPCM8XX_CLKSEL          (0x04)
> +#define NPCM8XX_CLKDIV1         (0x08)
> +#define NPCM8XX_CLKDIV2         (0x2C)
> +#define NPCM8XX_CLKDIV3         (0x58)
> +#define NPCM8XX_CLKDIV4         (0x7C)
> +#define NPCM8XX_PLLCON0         (0x0C)
> +#define NPCM8XX_PLLCON1         (0x10)
> +#define NPCM8XX_PLLCON2         (0x54)
> +#define NPCM8XX_SWRSTR          (0x14)
> +#define NPCM8XX_IRQWAKECON      (0x18)
> +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> +#define NPCM8XX_IPSRST1         (0x20)
> +#define NPCM8XX_IPSRST2         (0x24)
> +#define NPCM8XX_IPSRST3         (0x34)
> +#define NPCM8XX_WD0RCR          (0x38)
> +#define NPCM8XX_WD1RCR          (0x3C)
> +#define NPCM8XX_WD2RCR          (0x40)
> +#define NPCM8XX_SWRSTC1         (0x44)
> +#define NPCM8XX_SWRSTC2         (0x48)
> +#define NPCM8XX_SWRSTC3         (0x4C)
> +#define NPCM8XX_SWRSTC4         (0x50)
> +#define NPCM8XX_CORSTC          (0x5C)
> +#define NPCM8XX_PLLCONG         (0x60)
> +#define NPCM8XX_AHBCKFI         (0x64)
> +#define NPCM8XX_SECCNT          (0x68)
> +#define NPCM8XX_CNTR25M         (0x6C)
> +#define NPCM8XX_THRTL_CNT       (0xC0)
> +
> +struct npcm8xx_clk_gate_data {
> +       u32 reg;
> +       u8 bit_idx;
> +       const char *name;
> +       const char *parent_name;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_mux_data {
> +       u8 shift;
> +       u8 mask;
> +       u32 *table;
> +       const char *name;
> +       const char * const *parent_names;
> +       u8 num_parents;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +
> +};
> +
> +struct npcm8xx_clk_div_fixed_data {
> +       u8 mult;
> +       u8 div;
> +       const char *name;
> +       const char *parent_name;
> +       u8 clk_divider_flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_div_data {
> +       u32 reg;
> +       u8 shift;
> +       u8 width;
> +       const char *name;
> +       const char *parent_name;
> +       u8 clk_divider_flags;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_pll_data {
> +       u32 reg;
> +       const char *name;
> +       const char *parent_name;
> +       unsigned long flags;
> +       /*
> +        * If this clock is exported via DT, set onecell_idx to constant
> +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> +        * this specific clock.  Otherwise, set to -1.
> +        */
> +       int onecell_idx;
> +};
> +
> +/*
> + * Single copy of strings used to refer to clocks within this driver indexed by
> + * above enum.
> + */
> +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> +#define NPCM8XX_CLK_S_PLL0        "pll0"
> +#define NPCM8XX_CLK_S_PLL1        "pll1"
> +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> +#define NPCM8XX_CLK_S_PLL2        "pll2"
> +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
> +#define NPCM8XX_CLK_S_MC          "mc"
> +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
> +#define NPCM8XX_CLK_S_CLKOUT_MUX  "clkout_mux"
> +#define NPCM8XX_CLK_S_UART_MUX    "uart_mux"
> +#define NPCM8XX_CLK_S_UART2_MUX   "uart2_mux"
> +#define NPCM8XX_CLK_S_TIM_MUX     "timer_mux"
> +#define NPCM8XX_CLK_S_PRE_ADC_MUX "pre_adc_mux"
> +#define NPCM8XX_CLK_S_SD_MUX      "sd_mux"
> +#define NPCM8XX_CLK_S_GFXM_MUX    "gfxm_mux"
> +#define NPCM8XX_CLK_S_SU_MUX      "serial_usb_mux"
> +#define NPCM8XX_CLK_S_DVC_MUX     "dvc_mux"
> +#define NPCM8XX_CLK_S_GFX_MUX     "gfx_mux"
> +#define NPCM8XX_CLK_S_ADC_MUX     "adc_mux"
> +#define NPCM8XX_CLK_S_GFX_PIXEL   "gfx_pixel"
> +#define NPCM8XX_CLK_S_SPI0        "spi0"
> +#define NPCM8XX_CLK_S_SPI1        "spi1"
> +#define NPCM8XX_CLK_S_SPI3        "spi3"
> +#define NPCM8XX_CLK_S_SPIX        "spix"
> +#define NPCM8XX_CLK_S_APB1        "apb1"
> +#define NPCM8XX_CLK_S_APB2        "apb2"
> +#define NPCM8XX_CLK_S_APB3        "apb3"
> +#define NPCM8XX_CLK_S_APB4        "apb4"
> +#define NPCM8XX_CLK_S_APB5        "apb5"
> +#define NPCM8XX_CLK_S_APB19       "apb19"
> +#define NPCM8XX_CLK_S_TOCK        "tock"
> +#define NPCM8XX_CLK_S_CLKOUT      "clkout"
> +#define NPCM8XX_CLK_S_PRE_ADC     "pre adc"
> +#define NPCM8XX_CLK_S_UART        "uart"
> +#define NPCM8XX_CLK_S_UART2       "uart2"
> +#define NPCM8XX_CLK_S_TIMER       "timer"
> +#define NPCM8XX_CLK_S_MMC         "mmc"
> +#define NPCM8XX_CLK_S_SDHC        "sdhc"
> +#define NPCM8XX_CLK_S_ADC         "adc"
> +#define NPCM8XX_CLK_S_AMBA        "amba"
> +#define NPCM8XX_CLK_S_GFX         "gfx0_gfx1_mem"
> +#define NPCM8XX_CLK_S_USBIF       "serial_usbif"
> +#define NPCM8XX_CLK_S_USB_HOST    "usb_host"
> +#define NPCM8XX_CLK_S_USB_BRIDGE  "usb_bridge"
> +#define NPCM8XX_CLK_S_PCI         "pci"
> +#define NPCM8XX_CLK_S_TH          "th"
> +#define NPCM8XX_CLK_S_ATB         "atb"
> +#define NPCM8XX_CLK_S_PRE_CLK     "pre_clk"
> +
> +#define NPCM8XX_CLK_S_RG_MUX     "rg_mux"
> +#define NPCM8XX_CLK_S_RCP_MUX    "rcp_mux"
> +#define NPCM8XX_CLK_S_RG         "rg"
> +#define NPCM8XX_CLK_S_RCP        "rcp"

I suspect these defines will largely go away.

> +
> +static u32 pll_mux_table[] = {0, 1, 2, 3};
> +static const char * const pll_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL0,
> +       NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 cpuck_mux_table[] = {0, 1, 2, 3, 7};
> +static const char * const cpuck_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL0,
> +       NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_SYSBYPCK,
> +       NPCM8XX_CLK_S_PLL2,
> +};
> +
> +static u32 pixcksel_mux_table[] = {0, 2};
> +static const char * const pixcksel_mux_parents[] __initconst = {

Please use clk_parent_data instead of this.

> +       NPCM8XX_CLK_S_PLL_GFX,
> +       NPCM8XX_CLK_S_REFCLK,
> +};
> +
> +static u32 sucksel_mux_table[] = {2, 3};
> +static const char * const sucksel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 mccksel_mux_table[] = {0, 2, 3};
> +static const char * const mccksel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL1_DIV2,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_MCBYPCK,
> +};
> +
> +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
> +static const char * const clkoutsel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_PLL0,
> +       NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL_GFX, // divided by 2
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 gfxmsel_mux_table[] = {2, 3};
> +static const char * const gfxmsel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2_DIV2,
> +};
> +
> +static u32 dvcssel_mux_table[] = {2, 3};

Use checkpatch, add space around { and } for arrays.

> +static const char * const dvcssel_mux_parents[] __initconst = {
> +       NPCM8XX_CLK_S_REFCLK,
> +       NPCM8XX_CLK_S_PLL2,
> +};
> +
> +static const struct npcm8xx_clk_pll_data npcm8xx_plls[] __initconst = {
> +       {NPCM8XX_PLLCON0, NPCM8XX_CLK_S_PLL0, NPCM8XX_CLK_S_REFCLK, 0, -1},
> +
> +       {NPCM8XX_PLLCON1, NPCM8XX_CLK_S_PLL1,
> +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> +
> +       {NPCM8XX_PLLCON2, NPCM8XX_CLK_S_PLL2,
> +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> +
> +       {NPCM8XX_PLLCONG, NPCM8XX_CLK_S_PLL_GFX,
> +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> +};
> +
> +static const struct npcm8xx_clk_mux_data npcm8xx_muxes[] __initconst = {
> +       {0, GENMASK(1, 0), cpuck_mux_table, NPCM8XX_CLK_S_CPU_MUX,
> +       cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
> +       NPCM8XX_CLK_CPU},
> +
> +       {4, GENMASK(1, 0), pixcksel_mux_table, NPCM8XX_CLK_S_PIX_MUX,
> +       pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
> +       NPCM8XX_CLK_GFX_PIXEL},
> +
> +       {6, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_SD_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {8, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_UART_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {10, GENMASK(1, 0), sucksel_mux_table, NPCM8XX_CLK_S_SU_MUX,
> +       sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
> +
> +       {12, GENMASK(1, 0), mccksel_mux_table, NPCM8XX_CLK_S_MC_MUX,
> +       mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
> +
> +       {14, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_ADC_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {16, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_GFX_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM8XX_CLK_S_CLKOUT_MUX,
> +       clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
> +
> +       {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM8XX_CLK_S_GFXM_MUX,
> +       gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
> +
> +       {23, GENMASK(1, 0), dvcssel_mux_table, NPCM8XX_CLK_S_DVC_MUX,
> +       dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
> +
> +       {25, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RG_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +
> +       {27, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RCP_MUX,
> +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> +};
> +
> +/* fixed ratio dividers (no register): */
> +static const struct npcm8xx_clk_div_fixed_data npcm8xx_divs_fx[] __initconst = {
> +       { 1, 2, NPCM8XX_CLK_S_MC, NPCM8XX_CLK_S_MC_MUX, 0, NPCM8XX_CLK_MC},
> +       { 1, 2, NPCM8XX_CLK_S_AXI, NPCM8XX_CLK_S_TH, 0, NPCM8XX_CLK_AXI},
> +       { 1, 2, NPCM8XX_CLK_S_ATB, NPCM8XX_CLK_S_AXI, 0, NPCM8XX_CLK_ATB},
> +       { 1, 2, NPCM8XX_CLK_S_PRE_CLK, NPCM8XX_CLK_S_CPU_MUX, 0, -1},
> +       { 1, 2, NPCM8XX_CLK_S_PLL1_DIV2, NPCM8XX_CLK_S_PLL1, 0, -1},
> +       { 1, 2, NPCM8XX_CLK_S_PLL2_DIV2, NPCM8XX_CLK_S_PLL2, 0, -1},
> +};
> +
> +/* configurable dividers: */
> +static const struct npcm8xx_clk_div_data npcm8xx_divs[] __initconst = {
> +       {NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, NPCM8XX_CLK_S_PRE_ADC,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_ADC},
> +       /*30-28 ADCCKDIV*/

What are the numbers for? Bits inside the register?

> +       {NPCM8XX_CLKDIV1, 26, 2, NPCM8XX_CLK_S_AHB, NPCM8XX_CLK_S_PRE_CLK,
> +               CLK_DIVIDER_READ_ONLY, CLK_IS_CRITICAL, NPCM8XX_CLK_AHB},
> +       /*28-26 CLK4DIV*/
> +       {NPCM8XX_CLKDIV1, 21, 5, NPCM8XX_CLK_S_PRE_ADC,
> +       NPCM8XX_CLK_S_ADC_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PRE_ADC},
> +       /*25-21 PRE-ADCCKDIV*/
> +       {NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART,
> +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART},
> +       /*20-16 UARTDIV*/
> +       {NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC,
> +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC},
> +       /*15-11 MMCCKDIV*/
> +       {NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3,
> +       NPCM8XX_CLK_S_AHB, 0, 0, NPCM8XX_CLK_SPI3},
> +       /*10-6 AHB3CKDIV*/
> +       {NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI,
> +       NPCM8XX_CLK_S_GFX_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI},
> +       /*5-2 PCICKDIV*/
> +
> +       {NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB4},
> +       /*31-30 APB4CKDIV*/
> +       {NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB3},
> +       /*29-28 APB3CKDIV*/
> +       {NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB2},
> +       /*28-26 APB2CKDIV*/
> +       {NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB1},
> +       /*25-24 APB1CKDIV*/
> +       {NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, NPCM8XX_CLK_S_AHB,
> +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> +               NPCM8XX_CLK_APB5},
> +       /*23-22 APB5CKDIV*/
> +       {NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, NPCM8XX_CLK_S_CLKOUT_MUX,
> +                CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT},
> +       /*20-16 CLKOUTDIV*/
> +       {NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, NPCM8XX_CLK_S_GFX_MUX,
> +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX},
> +       /*15-13 GFXCKDIV*/
> +       {NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, NPCM8XX_CLK_S_SU_MUX,
> +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU},
> +       /*12-8 SUCKDIV*/
> +       {NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, NPCM8XX_CLK_S_SU_MUX,
> +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48},
> +       /*8-4 SU48CKDIV*/
> +       {NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC,
> +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC}
> +       ,/*3-0 SD1CKDIV*/
> +
> +       {NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1,
> +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1},
> +       /*23-16 SPI1CKDV*/
> +       {NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2,
> +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2},
> +       /*15-11 UARTDIV2*/
> +       {NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0,
> +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0},
> +       /*10-6 SPI0CKDV*/
> +       {NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX,
> +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX},
> +
> +       /*5-1 SPIXCKDV*/
> +       {NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, NPCM8XX_CLK_S_RG_MUX,
> +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG},
> +
> +       /*31-28 RGREFDIV*/
> +       {NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, NPCM8XX_CLK_S_RCP_MUX,
> +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP},
> +
> +       /*15-12 RCPREFDIV*/
> +       {NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, NPCM8XX_CLK_S_CPU_MUX,
> +       CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH},
> +       /*1-0 TH_DIV*/
> +};
> +
> +static const struct npcm8xx_clk_gate_data npcm8xx_gates[] __initconst = {
> +       {NPCM8XX_CLKEN1, 31, "smb1-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 30, "smb0-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 29, "smb7-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 28, "smb6-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 27, "adc-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 26, "wdt-gate", NPCM8XX_CLK_S_TIMER, 0},
> +       {NPCM8XX_CLKEN1, 25, "usbdev3-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 24, "usbdev6-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 23, "usbdev5-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 22, "usbdev4-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 21, "gmac4-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 20, "timer5_9-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 19, "timer0_4-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 18, "pwmm0-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN1, 17, "huart-gate", NPCM8XX_CLK_S_UART, 0},
> +       {NPCM8XX_CLKEN1, 16, "smb5-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 15, "smb4-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 14, "smb3-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 13, "smb2-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN1, 12, "mc-gate", NPCM8XX_CLK_S_MC, 0},
> +       {NPCM8XX_CLKEN1, 11, "uart01-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 10, "aes-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 9, "peci-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN1, 8, "usbdev2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 7, "uart23-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 6, "gmac3-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 5, "usbdev1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 4, "shm-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 3, "gdma0-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 2, "kcs-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN1, 1, "spi3-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN1, 0, "spi0-gate", NPCM8XX_CLK_S_AHB, 0},
> +
> +       {NPCM8XX_CLKEN2, 31, "cp-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 30, "tock-gate", NPCM8XX_CLK_S_TOCK, 0},
> +       /* bit 29 is reserved */
> +       {NPCM8XX_CLKEN2, 28, "gmac1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 27, "usbif-gate", NPCM8XX_CLK_S_USBIF, 0},
> +       {NPCM8XX_CLKEN2, 26, "usbhost1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 25, "gmac2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 24, "spi1-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN2, 23, "pspi2-gate", NPCM8XX_CLK_S_APB5, 0},
> +       /* bit 22 is reserved */
> +       {NPCM8XX_CLKEN2, 21, "3des-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 20, "bt-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN2, 19, "siox2-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN2, 18, "siox1-gate", NPCM8XX_CLK_S_APB3, 0},
> +       {NPCM8XX_CLKEN2, 17, "viruart2-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN2, 16, "viruart1-gate", NPCM8XX_CLK_S_APB5, 0},
> +       /*  bit 15 is reserved */
> +       {NPCM8XX_CLKEN2, 14, "vcd-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 13, "ece-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 12, "vdma-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 10, "gfxsys-gate", NPCM8XX_CLK_S_APB1, 0},
> +       //{NPCM8XX_CLKEN2, 9, "sdhc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       /*  bit 9 is reserved */
> +       {NPCM8XX_CLKEN2, 8, "mmc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN2, 7, "mft7-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 6, "mft6-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 5, "mft5-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 4, "mft4-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 3, "mft3-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 2, "mft2-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 1, "mft1-gate", NPCM8XX_CLK_S_APB4, 0},
> +       {NPCM8XX_CLKEN2, 0, "mft0-gate", NPCM8XX_CLK_S_APB4, 0},
> +
> +       {NPCM8XX_CLKEN3, 31, "gpiom7-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 30, "gpiom6-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 29, "gpiom5-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 28, "gpiom4-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 27, "gpiom3-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 26, "gpiom2-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 25, "gpiom1-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 24, "gpiom0-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 23, "espi-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 22, "smb11-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 21, "smb10-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 20, "smb9-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 19, "smb8-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 18, "smb15-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 17, "rng-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 16, "timer10_14-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN3, 15, "pcirc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 14, "sececc-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 13, "sha-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 12, "smb14-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 11, "gdma2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 10, "gdma1-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 9, "pcimbx-gate", NPCM8XX_CLK_S_AHB, 0},
> +       /* bit 8 is reserved */
> +       {NPCM8XX_CLKEN3, 7, "usbdev9-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 6, "usbdev8-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 5, "usbdev7-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 4, "usbdev0-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 3, "smb13-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 2, "spix-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN3, 1, "smb12-gate", NPCM8XX_CLK_S_APB2, 0},
> +       {NPCM8XX_CLKEN3, 0, "pwmm1-gate", NPCM8XX_CLK_S_APB3, 0},
> +
> +       {NPCM8XX_CLKEN4, 31, "usbhost2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN4, 30, "jtm2-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN4, 29, "jtm1-gate", NPCM8XX_CLK_S_APB5, 0},
> +       {NPCM8XX_CLKEN4, 28, "pwmm2-gate", NPCM8XX_CLK_S_APB3, 0},
> +       /* bit 27 is reserved */
> +       /* bit 26 is reserved */
> +       /* bit 25 is reserved */
> +       {NPCM8XX_CLKEN4, 24, "smb26-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 23, "smb25-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 22, "smb24-gate", NPCM8XX_CLK_S_APB19, 0},
> +       /* bit 21 is reserved */
> +       /* bit 20 is reserved */
> +       {NPCM8XX_CLKEN4, 19, "pcimbx2-gate", NPCM8XX_CLK_S_AHB, 0},
> +       {NPCM8XX_CLKEN4, 18, "uart6-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN4, 17, "uart5-gate", NPCM8XX_CLK_S_APB1, 0},
> +       {NPCM8XX_CLKEN4, 16, "uart4-gate", NPCM8XX_CLK_S_APB1, 0},
> +       /* bit 15 is reserved */
> +       /* bit 14 is reserved */
> +       {NPCM8XX_CLKEN4, 13, "i3c5-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 12, "i3c4-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 11, "i3c3-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 10, "i3c2-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 9, "i3c1-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 8, "i3c0-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 7, "smb23-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 6, "smb22-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 5, "smb21-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 4, "smb20-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 3, "smb19-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 2, "smb18-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 1, "smb17-gate", NPCM8XX_CLK_S_APB19, 0},
> +       {NPCM8XX_CLKEN4, 0, "smb16-gate", NPCM8XX_CLK_S_APB19, 0},
> +
> +};
> +
> +static DEFINE_SPINLOCK(npcm8xx_clk_lock);

Preferably this lock isn't global.

> +
> +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> +{
> +       struct clk_hw_onecell_data *npcm8xx_clk_data;
> +       void __iomem *clk_base;
> +       struct resource res;
> +       struct clk_hw *hw;
> +       int ret;
> +       int i;
> +
> +       ret = of_address_to_resource(clk_np, 0, &res);
> +       if (ret) {
> +               pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
> +               return;
> +       }
> +
> +       clk_base = ioremap(res.start, resource_size(&res));
> +       if (!clk_base)
> +               goto npcm8xx_init_error;
> +
> +       npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> +                                              NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> +       if (!npcm8xx_clk_data)
> +               goto npcm8xx_init_np_err;
> +
> +       npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> +
> +       for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> +               npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> +
> +       /* Register plls */
> +       for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> +               const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
> +
> +               hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> +                                             pll_data->name,
> +                                             pll_data->parent_name,
> +                                             pll_data->flags);
> +               if (IS_ERR(hw)) {
> +                       pr_err("npcm8xx_clk: Can't register pll\n");
> +                       goto npcm8xx_init_fail;
> +               }
> +
> +               if (pll_data->onecell_idx >= 0)
> +                       npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> +       }
> +
> +       /* Register fixed dividers */
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> +                                         NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register fixed div\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> +                                         NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register pll div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> +                                         NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> +                                         NPCM8XX_CLK_S_TH, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register axi div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> +                                         NPCM8XX_CLK_S_AXI, 0, 1, 2);
> +       if (IS_ERR(hw)) {
> +               pr_err("npcm8xx_clk: Can't register atb div2\n");
> +               goto npcm8xx_init_fail;
> +       }
> +
> +       /* Register muxes */
> +       for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> +               const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
> +
> +               hw = clk_hw_register_mux_table(NULL, mux_data->name,
> +                                              mux_data->parent_names,
> +                                              mux_data->num_parents,
> +                                              mux_data->flags,
> +                                              clk_base + NPCM8XX_CLKSEL,
> +                                              mux_data->shift,
> +                                              mux_data->mask, 0,
> +                                              mux_data->table,
> +                                              &npcm8xx_clk_lock);
> +
> +               if (IS_ERR(hw)) {
> +                       pr_err("npcm8xx_clk: Can't register mux\n");
> +                       goto npcm8xx_init_fail;
> +               }
> +
> +               if (mux_data->onecell_idx >= 0)
> +                       npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> +       }
> +
> +       /* Register clock dividers specified in npcm8xx_divs */
> +       for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> +               const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
> +
> +               hw = clk_hw_register_divider(NULL, div_data->name,
> +                                            div_data->parent_name,
> +                                            div_data->flags,
> +                                            clk_base + div_data->reg,
> +                                            div_data->shift, div_data->width,
> +                                            div_data->clk_divider_flags,
> +                                            &npcm8xx_clk_lock);
> +               if (IS_ERR(hw)) {
> +                       pr_err("npcm8xx_clk: Can't register div table\n");
> +                       goto npcm8xx_init_fail;
> +               }
> +
> +               if (div_data->onecell_idx >= 0)
> +                       npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> +       }
> +
> +       ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> +                                    npcm8xx_clk_data);
> +       if (ret)
> +               pr_err("failed to add DT provider: %d\n", ret);
> +
> +       of_node_put(clk_np);
> +
> +       return;
> +
> +npcm8xx_init_fail:
> +       kfree(npcm8xx_clk_data->hws);

Why only hws and not the entire npcm8xx_clk_data? Also, this error path
fails to unregister clks on error. Probably devm usage will help make
all of this code go away.

> +npcm8xx_init_np_err:
> +       iounmap(clk_base);
> +npcm8xx_init_error:
> +       of_node_put(clk_np);

What is this of_node_put() associated with in this function?

> +}
> +
> +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);

This should be made into a platform device driver and platform device
APIs should be used throughout.

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Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Tomer Maimon]

 Hi Stephen,

Thanks for your comments.

The patch will modify according to your comments and will be sent in
the next kernel revision 5.19.rc1

On Thu, 26 May 2022 at 22:37, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Tomer Maimon (2022-05-22 08:50:35)
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 5d596e778ff4..b9f3202de872 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -414,6 +414,13 @@ config COMMON_CLK_K210
> >         help
> >           Support for the Canaan Kendryte K210 RISC-V SoC clocks.
> >
> > +config COMMON_CLK_NPCM8XX
> > +       tristate "Clock driver for the NPCM8XX SoC Family"
> > +       depends on ARCH_NPCM || COMPILE_TEST
> > +       depends on OF
>
> What depends on OF? Presumably it builds even when OF is disabled.
Will remove.
>
> > +       help
> > +          This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family.
> > +
> >  source "drivers/clk/actions/Kconfig"
> >  source "drivers/clk/analogbits/Kconfig"
> >  source "drivers/clk/baikal-t1/Kconfig"
> > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > new file mode 100644
> > index 000000000000..6d0ab7f97ae6
> > --- /dev/null
> > +++ b/drivers/clk/clk-npcm8xx.c
> > @@ -0,0 +1,767 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Nuvoton NPCM8xx Clock Generator
> > + * All the clocks are initialized by the bootloader, so this driver allow only
> > + * reading of current settings directly from the hardware.
> > + *
> > + * Copyright (C) 2020 Nuvoton Technologies tomer.maimon@nuvoton.com
> > + */
> > +
> > +#include <asm/cputype.h>
>
> What is this include for?
will remove.
>
> > +#include <linux/module.h>
>
> It isn't a module though. Compiling the driver as a module will
> (hopefully) fail.
>
> > +#include <linux/clk-provider.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/slab.h>
> > +#include <linux/err.h>
> > +#include <linux/bitfield.h>
>
> Please sort includes alphabetically.
>
> > +
> > +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
>
> This should stay at the end though.
>
> > +
> > +struct npcm8xx_clk_pll {
> > +       struct clk_hw   hw;
> > +       void __iomem    *pllcon;
> > +       u8              flags;
> > +};
> > +
> > +#define to_npcm8xx_clk_pll(_hw) container_of(_hw, struct npcm8xx_clk_pll, hw)
> > +
> > +#define PLLCON_LOKI    BIT(31)
> > +#define PLLCON_LOKS    BIT(30)
> > +#define PLLCON_FBDV    GENMASK(27, 16)
> > +#define PLLCON_OTDV2   GENMASK(15, 13)
> > +#define PLLCON_PWDEN   BIT(12)
> > +#define PLLCON_OTDV1   GENMASK(10, 8)
> > +#define PLLCON_INDV    GENMASK(5, 0)
> > +
> > +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
> > +                                                unsigned long parent_rate)
> > +{
> > +       struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
> > +       unsigned long fbdv, indv, otdv1, otdv2;
> > +       unsigned int val;
> > +       u64 ret;
> > +
> > +       if (parent_rate == 0) {
> > +               pr_err("%s: parent rate is zero", __func__);
>
> This can happen because of registration logic, so downgrade to
> pr_debug() or just remove entirely and return 0.
>
> > +               return 0;
> > +       }
> > +
> > +       val = readl_relaxed(pll->pllcon);
> > +
> > +       indv = FIELD_GET(PLLCON_INDV, val);
> > +       fbdv = FIELD_GET(PLLCON_FBDV, val);
> > +       otdv1 = FIELD_GET(PLLCON_OTDV1, val);
> > +       otdv2 = FIELD_GET(PLLCON_OTDV2, val);
> > +
> > +       ret = (u64)parent_rate * fbdv;
> > +       do_div(ret, indv * otdv1 * otdv2);
>
> Does that indv * otdv1 * otdv2 ever overflow 32-bits?
No.
>
> > +
> > +       return ret;
> > +}
> > +
> > +static const struct clk_ops npcm8xx_clk_pll_ops = {
> > +       .recalc_rate = npcm8xx_clk_pll_recalc_rate,
> > +};
> > +
> > +static struct clk_hw *
> > +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> > +                        const char *parent_name, unsigned long flags)
> > +{
> > +       struct npcm8xx_clk_pll *pll;
> > +       struct clk_init_data init;
> > +       struct clk_hw *hw;
> > +       int ret;
> > +
> > +       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > +       if (!pll)
> > +               return ERR_PTR(-ENOMEM);
> > +
> > +       pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> > +
> > +       init.name = name;
> > +       init.ops = &npcm8xx_clk_pll_ops;
> > +       init.parent_names = &parent_name;
> > +       init.num_parents = 1;
> > +       init.flags = flags;
> > +
> > +       pll->pllcon = pllcon;
> > +       pll->hw.init = &init;
> > +
> > +       hw = &pll->hw;
> > +
> > +       ret = clk_hw_register(NULL, hw);
> > +       if (ret) {
> > +               kfree(pll);
> > +               hw = ERR_PTR(ret);
> > +       }
> > +
> > +       return hw;
> > +}
> > +
> > +#define NPCM8XX_CLKEN1          (0x00)
> > +#define NPCM8XX_CLKEN2          (0x28)
> > +#define NPCM8XX_CLKEN3          (0x30)
> > +#define NPCM8XX_CLKEN4          (0x70)
> > +#define NPCM8XX_CLKSEL          (0x04)
> > +#define NPCM8XX_CLKDIV1         (0x08)
> > +#define NPCM8XX_CLKDIV2         (0x2C)
> > +#define NPCM8XX_CLKDIV3         (0x58)
> > +#define NPCM8XX_CLKDIV4         (0x7C)
> > +#define NPCM8XX_PLLCON0         (0x0C)
> > +#define NPCM8XX_PLLCON1         (0x10)
> > +#define NPCM8XX_PLLCON2         (0x54)
> > +#define NPCM8XX_SWRSTR          (0x14)
> > +#define NPCM8XX_IRQWAKECON      (0x18)
> > +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> > +#define NPCM8XX_IPSRST1         (0x20)
> > +#define NPCM8XX_IPSRST2         (0x24)
> > +#define NPCM8XX_IPSRST3         (0x34)
> > +#define NPCM8XX_WD0RCR          (0x38)
> > +#define NPCM8XX_WD1RCR          (0x3C)
> > +#define NPCM8XX_WD2RCR          (0x40)
> > +#define NPCM8XX_SWRSTC1         (0x44)
> > +#define NPCM8XX_SWRSTC2         (0x48)
> > +#define NPCM8XX_SWRSTC3         (0x4C)
> > +#define NPCM8XX_SWRSTC4         (0x50)
> > +#define NPCM8XX_CORSTC          (0x5C)
> > +#define NPCM8XX_PLLCONG         (0x60)
> > +#define NPCM8XX_AHBCKFI         (0x64)
> > +#define NPCM8XX_SECCNT          (0x68)
> > +#define NPCM8XX_CNTR25M         (0x6C)
> > +#define NPCM8XX_THRTL_CNT       (0xC0)
> > +
> > +struct npcm8xx_clk_gate_data {
> > +       u32 reg;
> > +       u8 bit_idx;
> > +       const char *name;
> > +       const char *parent_name;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_mux_data {
> > +       u8 shift;
> > +       u8 mask;
> > +       u32 *table;
> > +       const char *name;
> > +       const char * const *parent_names;
> > +       u8 num_parents;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +
> > +};
> > +
> > +struct npcm8xx_clk_div_fixed_data {
> > +       u8 mult;
> > +       u8 div;
> > +       const char *name;
> > +       const char *parent_name;
> > +       u8 clk_divider_flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_div_data {
> > +       u32 reg;
> > +       u8 shift;
> > +       u8 width;
> > +       const char *name;
> > +       const char *parent_name;
> > +       u8 clk_divider_flags;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_pll_data {
> > +       u32 reg;
> > +       const char *name;
> > +       const char *parent_name;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +/*
> > + * Single copy of strings used to refer to clocks within this driver indexed by
> > + * above enum.
> > + */
> > +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> > +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> > +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> > +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> > +#define NPCM8XX_CLK_S_PLL0        "pll0"
> > +#define NPCM8XX_CLK_S_PLL1        "pll1"
> > +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> > +#define NPCM8XX_CLK_S_PLL2        "pll2"
> > +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> > +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> > +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> > +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> > +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> > +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
> > +#define NPCM8XX_CLK_S_MC          "mc"
> > +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> > +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
> > +#define NPCM8XX_CLK_S_CLKOUT_MUX  "clkout_mux"
> > +#define NPCM8XX_CLK_S_UART_MUX    "uart_mux"
> > +#define NPCM8XX_CLK_S_UART2_MUX   "uart2_mux"
> > +#define NPCM8XX_CLK_S_TIM_MUX     "timer_mux"
> > +#define NPCM8XX_CLK_S_PRE_ADC_MUX "pre_adc_mux"
> > +#define NPCM8XX_CLK_S_SD_MUX      "sd_mux"
> > +#define NPCM8XX_CLK_S_GFXM_MUX    "gfxm_mux"
> > +#define NPCM8XX_CLK_S_SU_MUX      "serial_usb_mux"
> > +#define NPCM8XX_CLK_S_DVC_MUX     "dvc_mux"
> > +#define NPCM8XX_CLK_S_GFX_MUX     "gfx_mux"
> > +#define NPCM8XX_CLK_S_ADC_MUX     "adc_mux"
> > +#define NPCM8XX_CLK_S_GFX_PIXEL   "gfx_pixel"
> > +#define NPCM8XX_CLK_S_SPI0        "spi0"
> > +#define NPCM8XX_CLK_S_SPI1        "spi1"
> > +#define NPCM8XX_CLK_S_SPI3        "spi3"
> > +#define NPCM8XX_CLK_S_SPIX        "spix"
> > +#define NPCM8XX_CLK_S_APB1        "apb1"
> > +#define NPCM8XX_CLK_S_APB2        "apb2"
> > +#define NPCM8XX_CLK_S_APB3        "apb3"
> > +#define NPCM8XX_CLK_S_APB4        "apb4"
> > +#define NPCM8XX_CLK_S_APB5        "apb5"
> > +#define NPCM8XX_CLK_S_APB19       "apb19"
> > +#define NPCM8XX_CLK_S_TOCK        "tock"
> > +#define NPCM8XX_CLK_S_CLKOUT      "clkout"
> > +#define NPCM8XX_CLK_S_PRE_ADC     "pre adc"
> > +#define NPCM8XX_CLK_S_UART        "uart"
> > +#define NPCM8XX_CLK_S_UART2       "uart2"
> > +#define NPCM8XX_CLK_S_TIMER       "timer"
> > +#define NPCM8XX_CLK_S_MMC         "mmc"
> > +#define NPCM8XX_CLK_S_SDHC        "sdhc"
> > +#define NPCM8XX_CLK_S_ADC         "adc"
> > +#define NPCM8XX_CLK_S_AMBA        "amba"
> > +#define NPCM8XX_CLK_S_GFX         "gfx0_gfx1_mem"
> > +#define NPCM8XX_CLK_S_USBIF       "serial_usbif"
> > +#define NPCM8XX_CLK_S_USB_HOST    "usb_host"
> > +#define NPCM8XX_CLK_S_USB_BRIDGE  "usb_bridge"
> > +#define NPCM8XX_CLK_S_PCI         "pci"
> > +#define NPCM8XX_CLK_S_TH          "th"
> > +#define NPCM8XX_CLK_S_ATB         "atb"
> > +#define NPCM8XX_CLK_S_PRE_CLK     "pre_clk"
> > +
> > +#define NPCM8XX_CLK_S_RG_MUX     "rg_mux"
> > +#define NPCM8XX_CLK_S_RCP_MUX    "rcp_mux"
> > +#define NPCM8XX_CLK_S_RG         "rg"
> > +#define NPCM8XX_CLK_S_RCP        "rcp"
>
> I suspect these defines will largely go away.
Most of the definitions are used or will be used, I will keep only the
used definitions
>
> > +
> > +static u32 pll_mux_table[] = {0, 1, 2, 3};
> > +static const char * const pll_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL0,
> > +       NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 cpuck_mux_table[] = {0, 1, 2, 3, 7};
> > +static const char * const cpuck_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL0,
> > +       NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_SYSBYPCK,
> > +       NPCM8XX_CLK_S_PLL2,
> > +};
> > +
> > +static u32 pixcksel_mux_table[] = {0, 2};
> > +static const char * const pixcksel_mux_parents[] __initconst = {
>
> Please use clk_parent_data instead of this.
>
> > +       NPCM8XX_CLK_S_PLL_GFX,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +};
> > +
> > +static u32 sucksel_mux_table[] = {2, 3};
> > +static const char * const sucksel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 mccksel_mux_table[] = {0, 2, 3};
> > +static const char * const mccksel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL1_DIV2,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_MCBYPCK,
> > +};
> > +
> > +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
> > +static const char * const clkoutsel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL0,
> > +       NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL_GFX, // divided by 2
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 gfxmsel_mux_table[] = {2, 3};
> > +static const char * const gfxmsel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 dvcssel_mux_table[] = {2, 3};
>
> Use checkpatch, add space around { and } for arrays.
>
> > +static const char * const dvcssel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2,
> > +};
> > +
> > +static const struct npcm8xx_clk_pll_data npcm8xx_plls[] __initconst = {
> > +       {NPCM8XX_PLLCON0, NPCM8XX_CLK_S_PLL0, NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +
> > +       {NPCM8XX_PLLCON1, NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +
> > +       {NPCM8XX_PLLCON2, NPCM8XX_CLK_S_PLL2,
> > +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +
> > +       {NPCM8XX_PLLCONG, NPCM8XX_CLK_S_PLL_GFX,
> > +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +};
> > +
> > +static const struct npcm8xx_clk_mux_data npcm8xx_muxes[] __initconst = {
> > +       {0, GENMASK(1, 0), cpuck_mux_table, NPCM8XX_CLK_S_CPU_MUX,
> > +       cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
> > +       NPCM8XX_CLK_CPU},
> > +
> > +       {4, GENMASK(1, 0), pixcksel_mux_table, NPCM8XX_CLK_S_PIX_MUX,
> > +       pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
> > +       NPCM8XX_CLK_GFX_PIXEL},
> > +
> > +       {6, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_SD_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {8, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_UART_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {10, GENMASK(1, 0), sucksel_mux_table, NPCM8XX_CLK_S_SU_MUX,
> > +       sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
> > +
> > +       {12, GENMASK(1, 0), mccksel_mux_table, NPCM8XX_CLK_S_MC_MUX,
> > +       mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
> > +
> > +       {14, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_ADC_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {16, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_GFX_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM8XX_CLK_S_CLKOUT_MUX,
> > +       clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
> > +
> > +       {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM8XX_CLK_S_GFXM_MUX,
> > +       gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
> > +
> > +       {23, GENMASK(1, 0), dvcssel_mux_table, NPCM8XX_CLK_S_DVC_MUX,
> > +       dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
> > +
> > +       {25, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RG_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {27, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RCP_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +};
> > +
> > +/* fixed ratio dividers (no register): */
> > +static const struct npcm8xx_clk_div_fixed_data npcm8xx_divs_fx[] __initconst = {
> > +       { 1, 2, NPCM8XX_CLK_S_MC, NPCM8XX_CLK_S_MC_MUX, 0, NPCM8XX_CLK_MC},
> > +       { 1, 2, NPCM8XX_CLK_S_AXI, NPCM8XX_CLK_S_TH, 0, NPCM8XX_CLK_AXI},
> > +       { 1, 2, NPCM8XX_CLK_S_ATB, NPCM8XX_CLK_S_AXI, 0, NPCM8XX_CLK_ATB},
> > +       { 1, 2, NPCM8XX_CLK_S_PRE_CLK, NPCM8XX_CLK_S_CPU_MUX, 0, -1},
> > +       { 1, 2, NPCM8XX_CLK_S_PLL1_DIV2, NPCM8XX_CLK_S_PLL1, 0, -1},
> > +       { 1, 2, NPCM8XX_CLK_S_PLL2_DIV2, NPCM8XX_CLK_S_PLL2, 0, -1},
> > +};
> > +
> > +/* configurable dividers: */
> > +static const struct npcm8xx_clk_div_data npcm8xx_divs[] __initconst = {
> > +       {NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, NPCM8XX_CLK_S_PRE_ADC,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_ADC},
> > +       /*30-28 ADCCKDIV*/
>
> What are the numbers for? Bits inside the register?
yes, I will add bits


>
> > +       {NPCM8XX_CLKDIV1, 26, 2, NPCM8XX_CLK_S_AHB, NPCM8XX_CLK_S_PRE_CLK,
> > +               CLK_DIVIDER_READ_ONLY, CLK_IS_CRITICAL, NPCM8XX_CLK_AHB},
> > +       /*28-26 CLK4DIV*/
> > +       {NPCM8XX_CLKDIV1, 21, 5, NPCM8XX_CLK_S_PRE_ADC,
> > +       NPCM8XX_CLK_S_ADC_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PRE_ADC},
> > +       /*25-21 PRE-ADCCKDIV*/
> > +       {NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART,
> > +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART},
> > +       /*20-16 UARTDIV*/
> > +       {NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC,
> > +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC},
> > +       /*15-11 MMCCKDIV*/
> > +       {NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3,
> > +       NPCM8XX_CLK_S_AHB, 0, 0, NPCM8XX_CLK_SPI3},
> > +       /*10-6 AHB3CKDIV*/
> > +       {NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI,
> > +       NPCM8XX_CLK_S_GFX_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI},
> > +       /*5-2 PCICKDIV*/
> > +
> > +       {NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB4},
> > +       /*31-30 APB4CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB3},
> > +       /*29-28 APB3CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB2},
> > +       /*28-26 APB2CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB1},
> > +       /*25-24 APB1CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB5},
> > +       /*23-22 APB5CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, NPCM8XX_CLK_S_CLKOUT_MUX,
> > +                CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT},
> > +       /*20-16 CLKOUTDIV*/
> > +       {NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, NPCM8XX_CLK_S_GFX_MUX,
> > +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX},
> > +       /*15-13 GFXCKDIV*/
> > +       {NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, NPCM8XX_CLK_S_SU_MUX,
> > +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU},
> > +       /*12-8 SUCKDIV*/
> > +       {NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, NPCM8XX_CLK_S_SU_MUX,
> > +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48},
> > +       /*8-4 SU48CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC,
> > +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC}
> > +       ,/*3-0 SD1CKDIV*/
> > +
> > +       {NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1,
> > +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1},
> > +       /*23-16 SPI1CKDV*/
> > +       {NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2,
> > +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2},
> > +       /*15-11 UARTDIV2*/
> > +       {NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0,
> > +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0},
> > +       /*10-6 SPI0CKDV*/
> > +       {NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX,
> > +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX},
> > +
> > +       /*5-1 SPIXCKDV*/
> > +       {NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, NPCM8XX_CLK_S_RG_MUX,
> > +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG},
> > +
> > +       /*31-28 RGREFDIV*/
> > +       {NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, NPCM8XX_CLK_S_RCP_MUX,
> > +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP},
> > +
> > +       /*15-12 RCPREFDIV*/
> > +       {NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, NPCM8XX_CLK_S_CPU_MUX,
> > +       CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH},
> > +       /*1-0 TH_DIV*/
> > +};
> > +
> > +static const struct npcm8xx_clk_gate_data npcm8xx_gates[] __initconst = {
> > +       {NPCM8XX_CLKEN1, 31, "smb1-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 30, "smb0-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 29, "smb7-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 28, "smb6-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 27, "adc-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 26, "wdt-gate", NPCM8XX_CLK_S_TIMER, 0},
> > +       {NPCM8XX_CLKEN1, 25, "usbdev3-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 24, "usbdev6-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 23, "usbdev5-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 22, "usbdev4-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 21, "gmac4-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 20, "timer5_9-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 19, "timer0_4-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 18, "pwmm0-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN1, 17, "huart-gate", NPCM8XX_CLK_S_UART, 0},
> > +       {NPCM8XX_CLKEN1, 16, "smb5-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 15, "smb4-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 14, "smb3-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 13, "smb2-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 12, "mc-gate", NPCM8XX_CLK_S_MC, 0},
> > +       {NPCM8XX_CLKEN1, 11, "uart01-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 10, "aes-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 9, "peci-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN1, 8, "usbdev2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 7, "uart23-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 6, "gmac3-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 5, "usbdev1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 4, "shm-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 3, "gdma0-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 2, "kcs-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 1, "spi3-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 0, "spi0-gate", NPCM8XX_CLK_S_AHB, 0},
> > +
> > +       {NPCM8XX_CLKEN2, 31, "cp-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 30, "tock-gate", NPCM8XX_CLK_S_TOCK, 0},
> > +       /* bit 29 is reserved */
> > +       {NPCM8XX_CLKEN2, 28, "gmac1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 27, "usbif-gate", NPCM8XX_CLK_S_USBIF, 0},
> > +       {NPCM8XX_CLKEN2, 26, "usbhost1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 25, "gmac2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 24, "spi1-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN2, 23, "pspi2-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       /* bit 22 is reserved */
> > +       {NPCM8XX_CLKEN2, 21, "3des-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 20, "bt-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN2, 19, "siox2-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN2, 18, "siox1-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN2, 17, "viruart2-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN2, 16, "viruart1-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       /*  bit 15 is reserved */
> > +       {NPCM8XX_CLKEN2, 14, "vcd-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 13, "ece-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 12, "vdma-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 10, "gfxsys-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       //{NPCM8XX_CLKEN2, 9, "sdhc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       /*  bit 9 is reserved */
> > +       {NPCM8XX_CLKEN2, 8, "mmc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 7, "mft7-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 6, "mft6-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 5, "mft5-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 4, "mft4-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 3, "mft3-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 2, "mft2-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 1, "mft1-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 0, "mft0-gate", NPCM8XX_CLK_S_APB4, 0},
> > +
> > +       {NPCM8XX_CLKEN3, 31, "gpiom7-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 30, "gpiom6-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 29, "gpiom5-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 28, "gpiom4-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 27, "gpiom3-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 26, "gpiom2-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 25, "gpiom1-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 24, "gpiom0-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 23, "espi-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 22, "smb11-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 21, "smb10-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 20, "smb9-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 19, "smb8-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 18, "smb15-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 17, "rng-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 16, "timer10_14-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 15, "pcirc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 14, "sececc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 13, "sha-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 12, "smb14-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 11, "gdma2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 10, "gdma1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 9, "pcimbx-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       /* bit 8 is reserved */
> > +       {NPCM8XX_CLKEN3, 7, "usbdev9-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 6, "usbdev8-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 5, "usbdev7-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 4, "usbdev0-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 3, "smb13-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 2, "spix-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 1, "smb12-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 0, "pwmm1-gate", NPCM8XX_CLK_S_APB3, 0},
> > +
> > +       {NPCM8XX_CLKEN4, 31, "usbhost2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN4, 30, "jtm2-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN4, 29, "jtm1-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN4, 28, "pwmm2-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       /* bit 27 is reserved */
> > +       /* bit 26 is reserved */
> > +       /* bit 25 is reserved */
> > +       {NPCM8XX_CLKEN4, 24, "smb26-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 23, "smb25-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 22, "smb24-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       /* bit 21 is reserved */
> > +       /* bit 20 is reserved */
> > +       {NPCM8XX_CLKEN4, 19, "pcimbx2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN4, 18, "uart6-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN4, 17, "uart5-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN4, 16, "uart4-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       /* bit 15 is reserved */
> > +       /* bit 14 is reserved */
> > +       {NPCM8XX_CLKEN4, 13, "i3c5-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 12, "i3c4-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 11, "i3c3-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 10, "i3c2-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 9, "i3c1-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 8, "i3c0-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 7, "smb23-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 6, "smb22-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 5, "smb21-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 4, "smb20-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 3, "smb19-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 2, "smb18-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 1, "smb17-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 0, "smb16-gate", NPCM8XX_CLK_S_APB19, 0},
> > +
> > +};
> > +
> > +static DEFINE_SPINLOCK(npcm8xx_clk_lock);
>
> Preferably this lock isn't global.
>
> > +
> > +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> > +{
> > +       struct clk_hw_onecell_data *npcm8xx_clk_data;
> > +       void __iomem *clk_base;
> > +       struct resource res;
> > +       struct clk_hw *hw;
> > +       int ret;
> > +       int i;
> > +
> > +       ret = of_address_to_resource(clk_np, 0, &res);
> > +       if (ret) {
> > +               pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
> > +               return;
> > +       }
> > +
> > +       clk_base = ioremap(res.start, resource_size(&res));
> > +       if (!clk_base)
> > +               goto npcm8xx_init_error;
> > +
> > +       npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> > +                                              NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> > +       if (!npcm8xx_clk_data)
> > +               goto npcm8xx_init_np_err;
> > +
> > +       npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> > +
> > +       for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> > +               npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> > +
> > +       /* Register plls */
> > +       for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> > +               const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
> > +
> > +               hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> > +                                             pll_data->name,
> > +                                             pll_data->parent_name,
> > +                                             pll_data->flags);
> > +               if (IS_ERR(hw)) {
> > +                       pr_err("npcm8xx_clk: Can't register pll\n");
> > +                       goto npcm8xx_init_fail;
> > +               }
> > +
> > +               if (pll_data->onecell_idx >= 0)
> > +                       npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> > +       }
> > +
> > +       /* Register fixed dividers */
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> > +                                         NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register fixed div\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> > +                                         NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register pll div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> > +                                         NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> > +                                         NPCM8XX_CLK_S_TH, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register axi div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> > +                                         NPCM8XX_CLK_S_AXI, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register atb div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       /* Register muxes */
> > +       for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> > +               const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
> > +
> > +               hw = clk_hw_register_mux_table(NULL, mux_data->name,
> > +                                              mux_data->parent_names,
> > +                                              mux_data->num_parents,
> > +                                              mux_data->flags,
> > +                                              clk_base + NPCM8XX_CLKSEL,
> > +                                              mux_data->shift,
> > +                                              mux_data->mask, 0,
> > +                                              mux_data->table,
> > +                                              &npcm8xx_clk_lock);
> > +
> > +               if (IS_ERR(hw)) {
> > +                       pr_err("npcm8xx_clk: Can't register mux\n");
> > +                       goto npcm8xx_init_fail;
> > +               }
> > +
> > +               if (mux_data->onecell_idx >= 0)
> > +                       npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> > +       }
> > +
> > +       /* Register clock dividers specified in npcm8xx_divs */
> > +       for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> > +               const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
> > +
> > +               hw = clk_hw_register_divider(NULL, div_data->name,
> > +                                            div_data->parent_name,
> > +                                            div_data->flags,
> > +                                            clk_base + div_data->reg,
> > +                                            div_data->shift, div_data->width,
> > +                                            div_data->clk_divider_flags,
> > +                                            &npcm8xx_clk_lock);
> > +               if (IS_ERR(hw)) {
> > +                       pr_err("npcm8xx_clk: Can't register div table\n");
> > +                       goto npcm8xx_init_fail;
> > +               }
> > +
> > +               if (div_data->onecell_idx >= 0)
> > +                       npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> > +       }
> > +
> > +       ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> > +                                    npcm8xx_clk_data);
> > +       if (ret)
> > +               pr_err("failed to add DT provider: %d\n", ret);
> > +
> > +       of_node_put(clk_np);
> > +
> > +       return;
> > +
> > +npcm8xx_init_fail:
> > +       kfree(npcm8xx_clk_data->hws);
>
> Why only hws and not the entire npcm8xx_clk_data? Also, this error path
> fails to unregister clks on error. Probably devm usage will help make
> all of this code go away.
>
> > +npcm8xx_init_np_err:
> > +       iounmap(clk_base);
> > +npcm8xx_init_error:
> > +       of_node_put(clk_np);
>
> What is this of_node_put() associated with in this function?
>
> > +}
> > +
> > +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);
>
> This should be made into a platform device driver and platform device
> APIs should be used throughout.
Do you mean that I need to use builtin_platform_driver API and not
CLK_OF_DECLARE declaration?

Best regards,

Tomer

Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller

[Tomer Maimon]

 Hi Stephen,

Thanks for your comments.

The patch will modify according to your comments and will be sent in
the next kernel revision 5.19.rc1

On Thu, 26 May 2022 at 22:37, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Tomer Maimon (2022-05-22 08:50:35)
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 5d596e778ff4..b9f3202de872 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -414,6 +414,13 @@ config COMMON_CLK_K210
> >         help
> >           Support for the Canaan Kendryte K210 RISC-V SoC clocks.
> >
> > +config COMMON_CLK_NPCM8XX
> > +       tristate "Clock driver for the NPCM8XX SoC Family"
> > +       depends on ARCH_NPCM || COMPILE_TEST
> > +       depends on OF
>
> What depends on OF? Presumably it builds even when OF is disabled.
Will remove.
>
> > +       help
> > +          This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family.
> > +
> >  source "drivers/clk/actions/Kconfig"
> >  source "drivers/clk/analogbits/Kconfig"
> >  source "drivers/clk/baikal-t1/Kconfig"
> > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > new file mode 100644
> > index 000000000000..6d0ab7f97ae6
> > --- /dev/null
> > +++ b/drivers/clk/clk-npcm8xx.c
> > @@ -0,0 +1,767 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Nuvoton NPCM8xx Clock Generator
> > + * All the clocks are initialized by the bootloader, so this driver allow only
> > + * reading of current settings directly from the hardware.
> > + *
> > + * Copyright (C) 2020 Nuvoton Technologies tomer.maimon@nuvoton.com
> > + */
> > +
> > +#include <asm/cputype.h>
>
> What is this include for?
will remove.
>
> > +#include <linux/module.h>
>
> It isn't a module though. Compiling the driver as a module will
> (hopefully) fail.
>
> > +#include <linux/clk-provider.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/slab.h>
> > +#include <linux/err.h>
> > +#include <linux/bitfield.h>
>
> Please sort includes alphabetically.
>
> > +
> > +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
>
> This should stay at the end though.
>
> > +
> > +struct npcm8xx_clk_pll {
> > +       struct clk_hw   hw;
> > +       void __iomem    *pllcon;
> > +       u8              flags;
> > +};
> > +
> > +#define to_npcm8xx_clk_pll(_hw) container_of(_hw, struct npcm8xx_clk_pll, hw)
> > +
> > +#define PLLCON_LOKI    BIT(31)
> > +#define PLLCON_LOKS    BIT(30)
> > +#define PLLCON_FBDV    GENMASK(27, 16)
> > +#define PLLCON_OTDV2   GENMASK(15, 13)
> > +#define PLLCON_PWDEN   BIT(12)
> > +#define PLLCON_OTDV1   GENMASK(10, 8)
> > +#define PLLCON_INDV    GENMASK(5, 0)
> > +
> > +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
> > +                                                unsigned long parent_rate)
> > +{
> > +       struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
> > +       unsigned long fbdv, indv, otdv1, otdv2;
> > +       unsigned int val;
> > +       u64 ret;
> > +
> > +       if (parent_rate == 0) {
> > +               pr_err("%s: parent rate is zero", __func__);
>
> This can happen because of registration logic, so downgrade to
> pr_debug() or just remove entirely and return 0.
>
> > +               return 0;
> > +       }
> > +
> > +       val = readl_relaxed(pll->pllcon);
> > +
> > +       indv = FIELD_GET(PLLCON_INDV, val);
> > +       fbdv = FIELD_GET(PLLCON_FBDV, val);
> > +       otdv1 = FIELD_GET(PLLCON_OTDV1, val);
> > +       otdv2 = FIELD_GET(PLLCON_OTDV2, val);
> > +
> > +       ret = (u64)parent_rate * fbdv;
> > +       do_div(ret, indv * otdv1 * otdv2);
>
> Does that indv * otdv1 * otdv2 ever overflow 32-bits?
No.
>
> > +
> > +       return ret;
> > +}
> > +
> > +static const struct clk_ops npcm8xx_clk_pll_ops = {
> > +       .recalc_rate = npcm8xx_clk_pll_recalc_rate,
> > +};
> > +
> > +static struct clk_hw *
> > +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> > +                        const char *parent_name, unsigned long flags)
> > +{
> > +       struct npcm8xx_clk_pll *pll;
> > +       struct clk_init_data init;
> > +       struct clk_hw *hw;
> > +       int ret;
> > +
> > +       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > +       if (!pll)
> > +               return ERR_PTR(-ENOMEM);
> > +
> > +       pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
> > +
> > +       init.name = name;
> > +       init.ops = &npcm8xx_clk_pll_ops;
> > +       init.parent_names = &parent_name;
> > +       init.num_parents = 1;
> > +       init.flags = flags;
> > +
> > +       pll->pllcon = pllcon;
> > +       pll->hw.init = &init;
> > +
> > +       hw = &pll->hw;
> > +
> > +       ret = clk_hw_register(NULL, hw);
> > +       if (ret) {
> > +               kfree(pll);
> > +               hw = ERR_PTR(ret);
> > +       }
> > +
> > +       return hw;
> > +}
> > +
> > +#define NPCM8XX_CLKEN1          (0x00)
> > +#define NPCM8XX_CLKEN2          (0x28)
> > +#define NPCM8XX_CLKEN3          (0x30)
> > +#define NPCM8XX_CLKEN4          (0x70)
> > +#define NPCM8XX_CLKSEL          (0x04)
> > +#define NPCM8XX_CLKDIV1         (0x08)
> > +#define NPCM8XX_CLKDIV2         (0x2C)
> > +#define NPCM8XX_CLKDIV3         (0x58)
> > +#define NPCM8XX_CLKDIV4         (0x7C)
> > +#define NPCM8XX_PLLCON0         (0x0C)
> > +#define NPCM8XX_PLLCON1         (0x10)
> > +#define NPCM8XX_PLLCON2         (0x54)
> > +#define NPCM8XX_SWRSTR          (0x14)
> > +#define NPCM8XX_IRQWAKECON      (0x18)
> > +#define NPCM8XX_IRQWAKEFLAG     (0x1C)
> > +#define NPCM8XX_IPSRST1         (0x20)
> > +#define NPCM8XX_IPSRST2         (0x24)
> > +#define NPCM8XX_IPSRST3         (0x34)
> > +#define NPCM8XX_WD0RCR          (0x38)
> > +#define NPCM8XX_WD1RCR          (0x3C)
> > +#define NPCM8XX_WD2RCR          (0x40)
> > +#define NPCM8XX_SWRSTC1         (0x44)
> > +#define NPCM8XX_SWRSTC2         (0x48)
> > +#define NPCM8XX_SWRSTC3         (0x4C)
> > +#define NPCM8XX_SWRSTC4         (0x50)
> > +#define NPCM8XX_CORSTC          (0x5C)
> > +#define NPCM8XX_PLLCONG         (0x60)
> > +#define NPCM8XX_AHBCKFI         (0x64)
> > +#define NPCM8XX_SECCNT          (0x68)
> > +#define NPCM8XX_CNTR25M         (0x6C)
> > +#define NPCM8XX_THRTL_CNT       (0xC0)
> > +
> > +struct npcm8xx_clk_gate_data {
> > +       u32 reg;
> > +       u8 bit_idx;
> > +       const char *name;
> > +       const char *parent_name;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_mux_data {
> > +       u8 shift;
> > +       u8 mask;
> > +       u32 *table;
> > +       const char *name;
> > +       const char * const *parent_names;
> > +       u8 num_parents;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +
> > +};
> > +
> > +struct npcm8xx_clk_div_fixed_data {
> > +       u8 mult;
> > +       u8 div;
> > +       const char *name;
> > +       const char *parent_name;
> > +       u8 clk_divider_flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_div_data {
> > +       u32 reg;
> > +       u8 shift;
> > +       u8 width;
> > +       const char *name;
> > +       const char *parent_name;
> > +       u8 clk_divider_flags;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +struct npcm8xx_clk_pll_data {
> > +       u32 reg;
> > +       const char *name;
> > +       const char *parent_name;
> > +       unsigned long flags;
> > +       /*
> > +        * If this clock is exported via DT, set onecell_idx to constant
> > +        * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
> > +        * this specific clock.  Otherwise, set to -1.
> > +        */
> > +       int onecell_idx;
> > +};
> > +
> > +/*
> > + * Single copy of strings used to refer to clocks within this driver indexed by
> > + * above enum.
> > + */
> > +#define NPCM8XX_CLK_S_REFCLK      "refclk"
> > +#define NPCM8XX_CLK_S_SYSBYPCK    "sysbypck"
> > +#define NPCM8XX_CLK_S_MCBYPCK     "mcbypck"
> > +#define NPCM8XX_CLK_S_GFXBYPCK    "gfxbypck"
> > +#define NPCM8XX_CLK_S_PLL0        "pll0"
> > +#define NPCM8XX_CLK_S_PLL1        "pll1"
> > +#define NPCM8XX_CLK_S_PLL1_DIV2   "pll1_div2"
> > +#define NPCM8XX_CLK_S_PLL2        "pll2"
> > +#define NPCM8XX_CLK_S_PLL_GFX     "pll_gfx"
> > +#define NPCM8XX_CLK_S_PLL2_DIV2   "pll2_div2"
> > +#define NPCM8XX_CLK_S_PIX_MUX     "gfx_pixel"
> > +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> > +#define NPCM8XX_CLK_S_MC_MUX      "mc_phy"
> > +#define NPCM8XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
> > +#define NPCM8XX_CLK_S_MC          "mc"
> > +#define NPCM8XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
> > +#define NPCM8XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
> > +#define NPCM8XX_CLK_S_CLKOUT_MUX  "clkout_mux"
> > +#define NPCM8XX_CLK_S_UART_MUX    "uart_mux"
> > +#define NPCM8XX_CLK_S_UART2_MUX   "uart2_mux"
> > +#define NPCM8XX_CLK_S_TIM_MUX     "timer_mux"
> > +#define NPCM8XX_CLK_S_PRE_ADC_MUX "pre_adc_mux"
> > +#define NPCM8XX_CLK_S_SD_MUX      "sd_mux"
> > +#define NPCM8XX_CLK_S_GFXM_MUX    "gfxm_mux"
> > +#define NPCM8XX_CLK_S_SU_MUX      "serial_usb_mux"
> > +#define NPCM8XX_CLK_S_DVC_MUX     "dvc_mux"
> > +#define NPCM8XX_CLK_S_GFX_MUX     "gfx_mux"
> > +#define NPCM8XX_CLK_S_ADC_MUX     "adc_mux"
> > +#define NPCM8XX_CLK_S_GFX_PIXEL   "gfx_pixel"
> > +#define NPCM8XX_CLK_S_SPI0        "spi0"
> > +#define NPCM8XX_CLK_S_SPI1        "spi1"
> > +#define NPCM8XX_CLK_S_SPI3        "spi3"
> > +#define NPCM8XX_CLK_S_SPIX        "spix"
> > +#define NPCM8XX_CLK_S_APB1        "apb1"
> > +#define NPCM8XX_CLK_S_APB2        "apb2"
> > +#define NPCM8XX_CLK_S_APB3        "apb3"
> > +#define NPCM8XX_CLK_S_APB4        "apb4"
> > +#define NPCM8XX_CLK_S_APB5        "apb5"
> > +#define NPCM8XX_CLK_S_APB19       "apb19"
> > +#define NPCM8XX_CLK_S_TOCK        "tock"
> > +#define NPCM8XX_CLK_S_CLKOUT      "clkout"
> > +#define NPCM8XX_CLK_S_PRE_ADC     "pre adc"
> > +#define NPCM8XX_CLK_S_UART        "uart"
> > +#define NPCM8XX_CLK_S_UART2       "uart2"
> > +#define NPCM8XX_CLK_S_TIMER       "timer"
> > +#define NPCM8XX_CLK_S_MMC         "mmc"
> > +#define NPCM8XX_CLK_S_SDHC        "sdhc"
> > +#define NPCM8XX_CLK_S_ADC         "adc"
> > +#define NPCM8XX_CLK_S_AMBA        "amba"
> > +#define NPCM8XX_CLK_S_GFX         "gfx0_gfx1_mem"
> > +#define NPCM8XX_CLK_S_USBIF       "serial_usbif"
> > +#define NPCM8XX_CLK_S_USB_HOST    "usb_host"
> > +#define NPCM8XX_CLK_S_USB_BRIDGE  "usb_bridge"
> > +#define NPCM8XX_CLK_S_PCI         "pci"
> > +#define NPCM8XX_CLK_S_TH          "th"
> > +#define NPCM8XX_CLK_S_ATB         "atb"
> > +#define NPCM8XX_CLK_S_PRE_CLK     "pre_clk"
> > +
> > +#define NPCM8XX_CLK_S_RG_MUX     "rg_mux"
> > +#define NPCM8XX_CLK_S_RCP_MUX    "rcp_mux"
> > +#define NPCM8XX_CLK_S_RG         "rg"
> > +#define NPCM8XX_CLK_S_RCP        "rcp"
>
> I suspect these defines will largely go away.
Most of the definitions are used or will be used, I will keep only the
used definitions
>
> > +
> > +static u32 pll_mux_table[] = {0, 1, 2, 3};
> > +static const char * const pll_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL0,
> > +       NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 cpuck_mux_table[] = {0, 1, 2, 3, 7};
> > +static const char * const cpuck_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL0,
> > +       NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_SYSBYPCK,
> > +       NPCM8XX_CLK_S_PLL2,
> > +};
> > +
> > +static u32 pixcksel_mux_table[] = {0, 2};
> > +static const char * const pixcksel_mux_parents[] __initconst = {
>
> Please use clk_parent_data instead of this.
>
> > +       NPCM8XX_CLK_S_PLL_GFX,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +};
> > +
> > +static u32 sucksel_mux_table[] = {2, 3};
> > +static const char * const sucksel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 mccksel_mux_table[] = {0, 2, 3};
> > +static const char * const mccksel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL1_DIV2,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_MCBYPCK,
> > +};
> > +
> > +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
> > +static const char * const clkoutsel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_PLL0,
> > +       NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL_GFX, // divided by 2
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 gfxmsel_mux_table[] = {2, 3};
> > +static const char * const gfxmsel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2_DIV2,
> > +};
> > +
> > +static u32 dvcssel_mux_table[] = {2, 3};
>
> Use checkpatch, add space around { and } for arrays.
>
> > +static const char * const dvcssel_mux_parents[] __initconst = {
> > +       NPCM8XX_CLK_S_REFCLK,
> > +       NPCM8XX_CLK_S_PLL2,
> > +};
> > +
> > +static const struct npcm8xx_clk_pll_data npcm8xx_plls[] __initconst = {
> > +       {NPCM8XX_PLLCON0, NPCM8XX_CLK_S_PLL0, NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +
> > +       {NPCM8XX_PLLCON1, NPCM8XX_CLK_S_PLL1,
> > +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +
> > +       {NPCM8XX_PLLCON2, NPCM8XX_CLK_S_PLL2,
> > +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +
> > +       {NPCM8XX_PLLCONG, NPCM8XX_CLK_S_PLL_GFX,
> > +       NPCM8XX_CLK_S_REFCLK, 0, -1},
> > +};
> > +
> > +static const struct npcm8xx_clk_mux_data npcm8xx_muxes[] __initconst = {
> > +       {0, GENMASK(1, 0), cpuck_mux_table, NPCM8XX_CLK_S_CPU_MUX,
> > +       cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
> > +       NPCM8XX_CLK_CPU},
> > +
> > +       {4, GENMASK(1, 0), pixcksel_mux_table, NPCM8XX_CLK_S_PIX_MUX,
> > +       pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
> > +       NPCM8XX_CLK_GFX_PIXEL},
> > +
> > +       {6, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_SD_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {8, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_UART_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {10, GENMASK(1, 0), sucksel_mux_table, NPCM8XX_CLK_S_SU_MUX,
> > +       sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
> > +
> > +       {12, GENMASK(1, 0), mccksel_mux_table, NPCM8XX_CLK_S_MC_MUX,
> > +       mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
> > +
> > +       {14, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_ADC_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {16, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_GFX_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM8XX_CLK_S_CLKOUT_MUX,
> > +       clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
> > +
> > +       {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM8XX_CLK_S_GFXM_MUX,
> > +       gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
> > +
> > +       {23, GENMASK(1, 0), dvcssel_mux_table, NPCM8XX_CLK_S_DVC_MUX,
> > +       dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
> > +
> > +       {25, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RG_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +
> > +       {27, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RCP_MUX,
> > +       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
> > +};
> > +
> > +/* fixed ratio dividers (no register): */
> > +static const struct npcm8xx_clk_div_fixed_data npcm8xx_divs_fx[] __initconst = {
> > +       { 1, 2, NPCM8XX_CLK_S_MC, NPCM8XX_CLK_S_MC_MUX, 0, NPCM8XX_CLK_MC},
> > +       { 1, 2, NPCM8XX_CLK_S_AXI, NPCM8XX_CLK_S_TH, 0, NPCM8XX_CLK_AXI},
> > +       { 1, 2, NPCM8XX_CLK_S_ATB, NPCM8XX_CLK_S_AXI, 0, NPCM8XX_CLK_ATB},
> > +       { 1, 2, NPCM8XX_CLK_S_PRE_CLK, NPCM8XX_CLK_S_CPU_MUX, 0, -1},
> > +       { 1, 2, NPCM8XX_CLK_S_PLL1_DIV2, NPCM8XX_CLK_S_PLL1, 0, -1},
> > +       { 1, 2, NPCM8XX_CLK_S_PLL2_DIV2, NPCM8XX_CLK_S_PLL2, 0, -1},
> > +};
> > +
> > +/* configurable dividers: */
> > +static const struct npcm8xx_clk_div_data npcm8xx_divs[] __initconst = {
> > +       {NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, NPCM8XX_CLK_S_PRE_ADC,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_ADC},
> > +       /*30-28 ADCCKDIV*/
>
> What are the numbers for? Bits inside the register?
yes, I will add bits


>
> > +       {NPCM8XX_CLKDIV1, 26, 2, NPCM8XX_CLK_S_AHB, NPCM8XX_CLK_S_PRE_CLK,
> > +               CLK_DIVIDER_READ_ONLY, CLK_IS_CRITICAL, NPCM8XX_CLK_AHB},
> > +       /*28-26 CLK4DIV*/
> > +       {NPCM8XX_CLKDIV1, 21, 5, NPCM8XX_CLK_S_PRE_ADC,
> > +       NPCM8XX_CLK_S_ADC_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PRE_ADC},
> > +       /*25-21 PRE-ADCCKDIV*/
> > +       {NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART,
> > +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART},
> > +       /*20-16 UARTDIV*/
> > +       {NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC,
> > +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC},
> > +       /*15-11 MMCCKDIV*/
> > +       {NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3,
> > +       NPCM8XX_CLK_S_AHB, 0, 0, NPCM8XX_CLK_SPI3},
> > +       /*10-6 AHB3CKDIV*/
> > +       {NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI,
> > +       NPCM8XX_CLK_S_GFX_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI},
> > +       /*5-2 PCICKDIV*/
> > +
> > +       {NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB4},
> > +       /*31-30 APB4CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB3},
> > +       /*29-28 APB3CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB2},
> > +       /*28-26 APB2CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB1},
> > +       /*25-24 APB1CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, NPCM8XX_CLK_S_AHB,
> > +               CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
> > +               NPCM8XX_CLK_APB5},
> > +       /*23-22 APB5CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, NPCM8XX_CLK_S_CLKOUT_MUX,
> > +                CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT},
> > +       /*20-16 CLKOUTDIV*/
> > +       {NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, NPCM8XX_CLK_S_GFX_MUX,
> > +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX},
> > +       /*15-13 GFXCKDIV*/
> > +       {NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, NPCM8XX_CLK_S_SU_MUX,
> > +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU},
> > +       /*12-8 SUCKDIV*/
> > +       {NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, NPCM8XX_CLK_S_SU_MUX,
> > +               CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48},
> > +       /*8-4 SU48CKDIV*/
> > +       {NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC,
> > +       NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC}
> > +       ,/*3-0 SD1CKDIV*/
> > +
> > +       {NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1,
> > +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1},
> > +       /*23-16 SPI1CKDV*/
> > +       {NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2,
> > +       NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2},
> > +       /*15-11 UARTDIV2*/
> > +       {NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0,
> > +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0},
> > +       /*10-6 SPI0CKDV*/
> > +       {NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX,
> > +       NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX},
> > +
> > +       /*5-1 SPIXCKDV*/
> > +       {NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, NPCM8XX_CLK_S_RG_MUX,
> > +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG},
> > +
> > +       /*31-28 RGREFDIV*/
> > +       {NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, NPCM8XX_CLK_S_RCP_MUX,
> > +       CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP},
> > +
> > +       /*15-12 RCPREFDIV*/
> > +       {NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, NPCM8XX_CLK_S_CPU_MUX,
> > +       CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH},
> > +       /*1-0 TH_DIV*/
> > +};
> > +
> > +static const struct npcm8xx_clk_gate_data npcm8xx_gates[] __initconst = {
> > +       {NPCM8XX_CLKEN1, 31, "smb1-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 30, "smb0-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 29, "smb7-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 28, "smb6-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 27, "adc-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 26, "wdt-gate", NPCM8XX_CLK_S_TIMER, 0},
> > +       {NPCM8XX_CLKEN1, 25, "usbdev3-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 24, "usbdev6-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 23, "usbdev5-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 22, "usbdev4-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 21, "gmac4-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 20, "timer5_9-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 19, "timer0_4-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 18, "pwmm0-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN1, 17, "huart-gate", NPCM8XX_CLK_S_UART, 0},
> > +       {NPCM8XX_CLKEN1, 16, "smb5-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 15, "smb4-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 14, "smb3-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 13, "smb2-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN1, 12, "mc-gate", NPCM8XX_CLK_S_MC, 0},
> > +       {NPCM8XX_CLKEN1, 11, "uart01-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 10, "aes-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 9, "peci-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN1, 8, "usbdev2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 7, "uart23-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 6, "gmac3-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 5, "usbdev1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 4, "shm-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 3, "gdma0-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 2, "kcs-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN1, 1, "spi3-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN1, 0, "spi0-gate", NPCM8XX_CLK_S_AHB, 0},
> > +
> > +       {NPCM8XX_CLKEN2, 31, "cp-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 30, "tock-gate", NPCM8XX_CLK_S_TOCK, 0},
> > +       /* bit 29 is reserved */
> > +       {NPCM8XX_CLKEN2, 28, "gmac1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 27, "usbif-gate", NPCM8XX_CLK_S_USBIF, 0},
> > +       {NPCM8XX_CLKEN2, 26, "usbhost1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 25, "gmac2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 24, "spi1-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN2, 23, "pspi2-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       /* bit 22 is reserved */
> > +       {NPCM8XX_CLKEN2, 21, "3des-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 20, "bt-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN2, 19, "siox2-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN2, 18, "siox1-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       {NPCM8XX_CLKEN2, 17, "viruart2-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN2, 16, "viruart1-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       /*  bit 15 is reserved */
> > +       {NPCM8XX_CLKEN2, 14, "vcd-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 13, "ece-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 12, "vdma-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 10, "gfxsys-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       //{NPCM8XX_CLKEN2, 9, "sdhc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       /*  bit 9 is reserved */
> > +       {NPCM8XX_CLKEN2, 8, "mmc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN2, 7, "mft7-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 6, "mft6-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 5, "mft5-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 4, "mft4-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 3, "mft3-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 2, "mft2-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 1, "mft1-gate", NPCM8XX_CLK_S_APB4, 0},
> > +       {NPCM8XX_CLKEN2, 0, "mft0-gate", NPCM8XX_CLK_S_APB4, 0},
> > +
> > +       {NPCM8XX_CLKEN3, 31, "gpiom7-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 30, "gpiom6-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 29, "gpiom5-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 28, "gpiom4-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 27, "gpiom3-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 26, "gpiom2-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 25, "gpiom1-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 24, "gpiom0-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 23, "espi-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 22, "smb11-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 21, "smb10-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 20, "smb9-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 19, "smb8-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 18, "smb15-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 17, "rng-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 16, "timer10_14-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN3, 15, "pcirc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 14, "sececc-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 13, "sha-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 12, "smb14-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 11, "gdma2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 10, "gdma1-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 9, "pcimbx-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       /* bit 8 is reserved */
> > +       {NPCM8XX_CLKEN3, 7, "usbdev9-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 6, "usbdev8-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 5, "usbdev7-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 4, "usbdev0-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 3, "smb13-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 2, "spix-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN3, 1, "smb12-gate", NPCM8XX_CLK_S_APB2, 0},
> > +       {NPCM8XX_CLKEN3, 0, "pwmm1-gate", NPCM8XX_CLK_S_APB3, 0},
> > +
> > +       {NPCM8XX_CLKEN4, 31, "usbhost2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN4, 30, "jtm2-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN4, 29, "jtm1-gate", NPCM8XX_CLK_S_APB5, 0},
> > +       {NPCM8XX_CLKEN4, 28, "pwmm2-gate", NPCM8XX_CLK_S_APB3, 0},
> > +       /* bit 27 is reserved */
> > +       /* bit 26 is reserved */
> > +       /* bit 25 is reserved */
> > +       {NPCM8XX_CLKEN4, 24, "smb26-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 23, "smb25-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 22, "smb24-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       /* bit 21 is reserved */
> > +       /* bit 20 is reserved */
> > +       {NPCM8XX_CLKEN4, 19, "pcimbx2-gate", NPCM8XX_CLK_S_AHB, 0},
> > +       {NPCM8XX_CLKEN4, 18, "uart6-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN4, 17, "uart5-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       {NPCM8XX_CLKEN4, 16, "uart4-gate", NPCM8XX_CLK_S_APB1, 0},
> > +       /* bit 15 is reserved */
> > +       /* bit 14 is reserved */
> > +       {NPCM8XX_CLKEN4, 13, "i3c5-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 12, "i3c4-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 11, "i3c3-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 10, "i3c2-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 9, "i3c1-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 8, "i3c0-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 7, "smb23-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 6, "smb22-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 5, "smb21-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 4, "smb20-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 3, "smb19-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 2, "smb18-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 1, "smb17-gate", NPCM8XX_CLK_S_APB19, 0},
> > +       {NPCM8XX_CLKEN4, 0, "smb16-gate", NPCM8XX_CLK_S_APB19, 0},
> > +
> > +};
> > +
> > +static DEFINE_SPINLOCK(npcm8xx_clk_lock);
>
> Preferably this lock isn't global.
>
> > +
> > +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> > +{
> > +       struct clk_hw_onecell_data *npcm8xx_clk_data;
> > +       void __iomem *clk_base;
> > +       struct resource res;
> > +       struct clk_hw *hw;
> > +       int ret;
> > +       int i;
> > +
> > +       ret = of_address_to_resource(clk_np, 0, &res);
> > +       if (ret) {
> > +               pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, ret);
> > +               return;
> > +       }
> > +
> > +       clk_base = ioremap(res.start, resource_size(&res));
> > +       if (!clk_base)
> > +               goto npcm8xx_init_error;
> > +
> > +       npcm8xx_clk_data = kzalloc(struct_size(npcm8xx_clk_data, hws,
> > +                                              NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> > +       if (!npcm8xx_clk_data)
> > +               goto npcm8xx_init_np_err;
> > +
> > +       npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> > +
> > +       for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> > +               npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> > +
> > +       /* Register plls */
> > +       for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
> > +               const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
> > +
> > +               hw = npcm8xx_clk_register_pll(clk_base + pll_data->reg,
> > +                                             pll_data->name,
> > +                                             pll_data->parent_name,
> > +                                             pll_data->flags);
> > +               if (IS_ERR(hw)) {
> > +                       pr_err("npcm8xx_clk: Can't register pll\n");
> > +                       goto npcm8xx_init_fail;
> > +               }
> > +
> > +               if (pll_data->onecell_idx >= 0)
> > +                       npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
> > +       }
> > +
> > +       /* Register fixed dividers */
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2,
> > +                                         NPCM8XX_CLK_S_PLL1, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register fixed div\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2,
> > +                                         NPCM8XX_CLK_S_PLL2, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register pll div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK,
> > +                                         NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register ckclk div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI,
> > +                                         NPCM8XX_CLK_S_TH, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register axi div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       hw = clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB,
> > +                                         NPCM8XX_CLK_S_AXI, 0, 1, 2);
> > +       if (IS_ERR(hw)) {
> > +               pr_err("npcm8xx_clk: Can't register atb div2\n");
> > +               goto npcm8xx_init_fail;
> > +       }
> > +
> > +       /* Register muxes */
> > +       for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
> > +               const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
> > +
> > +               hw = clk_hw_register_mux_table(NULL, mux_data->name,
> > +                                              mux_data->parent_names,
> > +                                              mux_data->num_parents,
> > +                                              mux_data->flags,
> > +                                              clk_base + NPCM8XX_CLKSEL,
> > +                                              mux_data->shift,
> > +                                              mux_data->mask, 0,
> > +                                              mux_data->table,
> > +                                              &npcm8xx_clk_lock);
> > +
> > +               if (IS_ERR(hw)) {
> > +                       pr_err("npcm8xx_clk: Can't register mux\n");
> > +                       goto npcm8xx_init_fail;
> > +               }
> > +
> > +               if (mux_data->onecell_idx >= 0)
> > +                       npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
> > +       }
> > +
> > +       /* Register clock dividers specified in npcm8xx_divs */
> > +       for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
> > +               const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
> > +
> > +               hw = clk_hw_register_divider(NULL, div_data->name,
> > +                                            div_data->parent_name,
> > +                                            div_data->flags,
> > +                                            clk_base + div_data->reg,
> > +                                            div_data->shift, div_data->width,
> > +                                            div_data->clk_divider_flags,
> > +                                            &npcm8xx_clk_lock);
> > +               if (IS_ERR(hw)) {
> > +                       pr_err("npcm8xx_clk: Can't register div table\n");
> > +                       goto npcm8xx_init_fail;
> > +               }
> > +
> > +               if (div_data->onecell_idx >= 0)
> > +                       npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
> > +       }
> > +
> > +       ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
> > +                                    npcm8xx_clk_data);
> > +       if (ret)
> > +               pr_err("failed to add DT provider: %d\n", ret);
> > +
> > +       of_node_put(clk_np);
> > +
> > +       return;
> > +
> > +npcm8xx_init_fail:
> > +       kfree(npcm8xx_clk_data->hws);
>
> Why only hws and not the entire npcm8xx_clk_data? Also, this error path
> fails to unregister clks on error. Probably devm usage will help make
> all of this code go away.
>
> > +npcm8xx_init_np_err:
> > +       iounmap(clk_base);
> > +npcm8xx_init_error:
> > +       of_node_put(clk_np);
>
> What is this of_node_put() associated with in this function?
>
> > +}
> > +
> > +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npcm8xx_clk_init);
>
> This should be made into a platform device driver and platform device
> APIs should be used throughout.
Do you mean that I need to use builtin_platform_driver API and not
CLK_OF_DECLARE declaration?

Best regards,

Tomer

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[PATCH v1 09/19] dt-bindings: reset: add syscon property

[Tomer Maimon]

Describe syscon property that handles GCR registers
in Nuvoton BMC NPCM reset driver.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
index 17b7a6a43a29..cb1613092ee7 100644
--- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
+++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
 - reg : specifies physical base address and size of the register.
 - #reset-cells: must be set to 2
+- syscon: a phandle to access GCR registers.
 
 Optional property:
 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
@@ -16,6 +17,7 @@ Example:
 		compatible = "nuvoton,npcm750-reset";
 		reg = <0xf0801000 0x70>;
 		#reset-cells = <2>;
+		syscon = <&gcr>;
 		nuvoton,sw-reset-number = <2>;
 	};
 
-- 
2.33.0

Re: [PATCH v1 09/19] dt-bindings: reset: add syscon property

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Describe syscon property that handles GCR registers
> in Nuvoton BMC NPCM reset driver.

Please wrap according to Linux standards:
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> index 17b7a6a43a29..cb1613092ee7 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> @@ -4,6 +4,7 @@ Required properties:
>  - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
>  - reg : specifies physical base address and size of the register.
>  - #reset-cells: must be set to 2
> +- syscon: a phandle to access GCR registers.

syscon is not a generic property, so vendor prefix and some descriptive
name of property.

>  
>  Optional property:
>  - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
> @@ -16,6 +17,7 @@ Example:
>  		compatible = "nuvoton,npcm750-reset";
>  		reg = <0xf0801000 0x70>;
>  		#reset-cells = <2>;
> +		syscon = <&gcr>;
>  		nuvoton,sw-reset-number = <2>;
>  	};
>  


Best regards,
Krzysztof

Re: [PATCH v1 09/19] dt-bindings: reset: add syscon property

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Describe syscon property that handles GCR registers
> in Nuvoton BMC NPCM reset driver.

Please wrap according to Linux standards:
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> index 17b7a6a43a29..cb1613092ee7 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> @@ -4,6 +4,7 @@ Required properties:
>  - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
>  - reg : specifies physical base address and size of the register.
>  - #reset-cells: must be set to 2
> +- syscon: a phandle to access GCR registers.

syscon is not a generic property, so vendor prefix and some descriptive
name of property.

>  
>  Optional property:
>  - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
> @@ -16,6 +17,7 @@ Example:
>  		compatible = "nuvoton,npcm750-reset";
>  		reg = <0xf0801000 0x70>;
>  		#reset-cells = <2>;
> +		syscon = <&gcr>;
>  		nuvoton,sw-reset-number = <2>;
>  	};
>  


Best regards,
Krzysztof

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Re: [PATCH v1 09/19] dt-bindings: reset: add syscon property

[Tomer Maimon]

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Hi Krzysztof,

Thanks for your comments.

On Mon, 23 May 2022 at 10:39, Krzysztof Kozlowski <
krzysztof.kozlowski@linaro.org> wrote:

> On 22/05/2022 17:50, Tomer Maimon wrote:
> > Describe syscon property that handles GCR registers
> > in Nuvoton BMC NPCM reset driver.
>
> Please wrap according to Linux standards:
>
> https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

Which problem do you see with the commit explanation body?

>
>
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git
> a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> > index 17b7a6a43a29..cb1613092ee7 100644
> > --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> > @@ -4,6 +4,7 @@ Required properties:
> >  - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
> >  - reg : specifies physical base address and size of the register.
> >  - #reset-cells: must be set to 2
> > +- syscon: a phandle to access GCR registers.
>
> syscon is not a generic property, so vendor prefix and some descriptive
> name of property.
>
> Will do.

> >
> >  Optional property:
> >  - nuvoton,sw-reset-number - Contains the software reset number to
> restart the SoC.
> > @@ -16,6 +17,7 @@ Example:
> >               compatible = "nuvoton,npcm750-reset";
> >               reg = <0xf0801000 0x70>;
> >               #reset-cells = <2>;
> > +             syscon = <&gcr>;
> >               nuvoton,sw-reset-number = <2>;
> >       };
> >
>
>
> Best regards,
> Krzysztof
>

Best Regards,

Tomer

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Re: [PATCH v1 09/19] dt-bindings: reset: add syscon property

[Krzysztof Kozlowski]

On 23/05/2022 15:44, Tomer Maimon wrote:
> On Mon, 23 May 2022 at 10:39, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org <mailto:krzysztof.kozlowski@linaro.org>>
> wrote:
> 
>     On 22/05/2022 17:50, Tomer Maimon wrote:
>     > Describe syscon property that handles GCR registers
>     > in Nuvoton BMC NPCM reset driver.
> 
>     Please wrap according to Linux standards:
>     https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586
>     <https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586>
> 
> Which problem do you see with the commit explanation body?

It is wrapped not according to Linux standards.



Best regards,
Krzysztof

Re: [PATCH v1 09/19] dt-bindings: reset: add syscon property

[Krzysztof Kozlowski]

On 23/05/2022 15:44, Tomer Maimon wrote:
> On Mon, 23 May 2022 at 10:39, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org <mailto:krzysztof.kozlowski@linaro.org>>
> wrote:
> 
>     On 22/05/2022 17:50, Tomer Maimon wrote:
>     > Describe syscon property that handles GCR registers
>     > in Nuvoton BMC NPCM reset driver.
> 
>     Please wrap according to Linux standards:
>     https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586
>     <https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586>
> 
> Which problem do you see with the commit explanation body?

It is wrapped not according to Linux standards.



Best regards,
Krzysztof

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[PATCH v1 10/19] reset: npcm: using syscon instead of device data

[Tomer Maimon]

Using syscon device tree property instead of
device data to handle the NPCM GCR registers.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/reset/reset-npcm.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
index 2ea4d3136e15..0c963b21eddc 100644
--- a/drivers/reset/reset-npcm.c
+++ b/drivers/reset/reset-npcm.c
@@ -138,8 +138,7 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
 }
 
 static const struct of_device_id npcm_rc_match[] = {
-	{ .compatible = "nuvoton,npcm750-reset",
-		.data = (void *)"nuvoton,npcm750-gcr" },
+	{ .compatible = "nuvoton,npcm750-reset"},
 	{ }
 };
 
@@ -155,14 +154,10 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
 	u32 ipsrst1_bits = 0;
 	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
 	u32 ipsrst3_bits = 0;
-	const char *gcr_dt;
 
-	gcr_dt = (const char *)
-	of_match_device(dev->driver->of_match_table, dev)->data;
-
-	gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
+	gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
 	if (IS_ERR(gcr_regmap)) {
-		dev_err(&pdev->dev, "Failed to find %s\n", gcr_dt);
+		dev_err(&pdev->dev, "Failed to find gcr syscon");
 		return PTR_ERR(gcr_regmap);
 	}
 
-- 
2.33.0

Re: [PATCH v1 10/19] reset: npcm: using syscon instead of device data

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Using syscon device tree property instead of
> device data to handle the NPCM GCR registers.

https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  drivers/reset/reset-npcm.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
> index 2ea4d3136e15..0c963b21eddc 100644
> --- a/drivers/reset/reset-npcm.c
> +++ b/drivers/reset/reset-npcm.c
> @@ -138,8 +138,7 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
>  }
>  
>  static const struct of_device_id npcm_rc_match[] = {
> -	{ .compatible = "nuvoton,npcm750-reset",
> -		.data = (void *)"nuvoton,npcm750-gcr" },
> +	{ .compatible = "nuvoton,npcm750-reset"},
>  	{ }
>  };
>  
> @@ -155,14 +154,10 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
>  	u32 ipsrst1_bits = 0;
>  	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
>  	u32 ipsrst3_bits = 0;
> -	const char *gcr_dt;
>  
> -	gcr_dt = (const char *)
> -	of_match_device(dev->driver->of_match_table, dev)->data;
> -
> -	gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
> +	gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");

I think this just broke all existing boards...

Best regards,
Krzysztof

Re: [PATCH v1 10/19] reset: npcm: using syscon instead of device data

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Using syscon device tree property instead of
> device data to handle the NPCM GCR registers.

https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  drivers/reset/reset-npcm.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
> index 2ea4d3136e15..0c963b21eddc 100644
> --- a/drivers/reset/reset-npcm.c
> +++ b/drivers/reset/reset-npcm.c
> @@ -138,8 +138,7 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
>  }
>  
>  static const struct of_device_id npcm_rc_match[] = {
> -	{ .compatible = "nuvoton,npcm750-reset",
> -		.data = (void *)"nuvoton,npcm750-gcr" },
> +	{ .compatible = "nuvoton,npcm750-reset"},
>  	{ }
>  };
>  
> @@ -155,14 +154,10 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
>  	u32 ipsrst1_bits = 0;
>  	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
>  	u32 ipsrst3_bits = 0;
> -	const char *gcr_dt;
>  
> -	gcr_dt = (const char *)
> -	of_match_device(dev->driver->of_match_table, dev)->data;
> -
> -	gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
> +	gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");

I think this just broke all existing boards...

Best regards,
Krzysztof

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Re: [PATCH v1 10/19] reset: npcm: using syscon instead of device data

[Tomer Maimon]

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Hi Krzysztof,

Thanks for your comments.

the patch will modify according to your comments and will be sent in the
next kernel revision 5.19.rc1

On Mon, 23 May 2022 at 11:54, Krzysztof Kozlowski <
krzysztof.kozlowski@linaro.org> wrote:

> On 22/05/2022 17:50, Tomer Maimon wrote:
> > Using syscon device tree property instead of
> > device data to handle the NPCM GCR registers.
>
>
> https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586
>
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  drivers/reset/reset-npcm.c | 11 +++--------
> >  1 file changed, 3 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
> > index 2ea4d3136e15..0c963b21eddc 100644
> > --- a/drivers/reset/reset-npcm.c
> > +++ b/drivers/reset/reset-npcm.c
> > @@ -138,8 +138,7 @@ static int npcm_reset_xlate(struct
> reset_controller_dev *rcdev,
> >  }
> >
> >  static const struct of_device_id npcm_rc_match[] = {
> > -     { .compatible = "nuvoton,npcm750-reset",
> > -             .data = (void *)"nuvoton,npcm750-gcr" },
> > +     { .compatible = "nuvoton,npcm750-reset"},
> >       { }
> >  };
> >
> > @@ -155,14 +154,10 @@ static int npcm_usb_reset(struct platform_device
> *pdev, struct npcm_rc_data *rc)
> >       u32 ipsrst1_bits = 0;
> >       u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
> >       u32 ipsrst3_bits = 0;
> > -     const char *gcr_dt;
> >
> > -     gcr_dt = (const char *)
> > -     of_match_device(dev->driver->of_match_table, dev)->data;
> > -
> > -     gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
> > +     gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
> "syscon");
>
> I think this just broke all existing boards...
>
> Best regards,
> Krzysztof
>

Best regards,

Tomer

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[PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Tomer Maimon]

Add binding document and device tree binding
constants for Nuvoton BMC NPCM8XX reset controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../bindings/reset/nuvoton,npcm-reset.txt     |  17 ++-
 .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 ++++++++++++++++++
 2 files changed, 139 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h

diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
index cb1613092ee7..b7eb8615b68b 100644
--- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
+++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
@@ -1,14 +1,15 @@
 Nuvoton NPCM Reset controller
 
 Required properties:
-- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
+- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC.
+               "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC.
 - reg : specifies physical base address and size of the register.
 - #reset-cells: must be set to 2
 - syscon: a phandle to access GCR registers.
 
 Optional property:
 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
-  NPCM7xx contain four software reset that represent numbers 1 to 4.
+  NPCM7xx and NPCM8xx contain four software reset that represent numbers 1 to 4.
 
   If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
 
@@ -32,3 +33,15 @@ example:
         };
 
 The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
+
+Specifying reset lines connected to IP NPCM8XX modules
+======================================================
+example:
+
+        spi0: spi@..... {
+                ...
+                resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI1>;
+                ...
+        };
+
+The index could be found in <dt-bindings/reset/nuvoton,npcm8xx-reset.h>.
diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
new file mode 100644
index 000000000000..4b832a0fd1dd
--- /dev/null
+++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2022 Nuvoton Technology corporation.
+
+#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
+#define _DT_BINDINGS_NPCM8XX_RESET_H
+
+#define NPCM8XX_RESET_IPSRST1		0x20
+#define NPCM8XX_RESET_IPSRST2		0x24
+#define NPCM8XX_RESET_IPSRST3		0x34
+#define NPCM8XX_RESET_IPSRST4		0x74
+
+/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
+#define NPCM8XX_RESET_GDMA0		3
+#define NPCM8XX_RESET_UDC1		5
+#define NPCM8XX_RESET_GMAC3		6
+#define NPCM8XX_RESET_UART_2_3		7
+#define NPCM8XX_RESET_UDC2		8
+#define NPCM8XX_RESET_PECI		9
+#define NPCM8XX_RESET_AES		10
+#define NPCM8XX_RESET_UART_0_1		11
+#define NPCM8XX_RESET_MC		12
+#define NPCM8XX_RESET_SMB2		13
+#define NPCM8XX_RESET_SMB3		14
+#define NPCM8XX_RESET_SMB4		15
+#define NPCM8XX_RESET_SMB5		16
+#define NPCM8XX_RESET_PWM_M0		18
+#define NPCM8XX_RESET_TIMER_0_4		19
+#define NPCM8XX_RESET_TIMER_5_9		20
+#define NPCM8XX_RESET_GMAC4		21
+#define NPCM8XX_RESET_UDC4		22
+#define NPCM8XX_RESET_UDC5		23
+#define NPCM8XX_RESET_UDC6		24
+#define NPCM8XX_RESET_UDC3		25
+#define NPCM8XX_RESET_ADC		27
+#define NPCM8XX_RESET_SMB6		28
+#define NPCM8XX_RESET_SMB7		29
+#define NPCM8XX_RESET_SMB0		30
+#define NPCM8XX_RESET_SMB1		31
+
+/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
+#define NPCM8XX_RESET_MFT0		0
+#define NPCM8XX_RESET_MFT1		1
+#define NPCM8XX_RESET_MFT2		2
+#define NPCM8XX_RESET_MFT3		3
+#define NPCM8XX_RESET_MFT4		4
+#define NPCM8XX_RESET_MFT5		5
+#define NPCM8XX_RESET_MFT6		6
+#define NPCM8XX_RESET_MFT7		7
+#define NPCM8XX_RESET_MMC		8
+#define NPCM8XX_RESET_GFX_SYS		10
+#define NPCM8XX_RESET_AHB_PCIBRG	11
+#define NPCM8XX_RESET_VDMA		12
+#define NPCM8XX_RESET_ECE		13
+#define NPCM8XX_RESET_VCD		14
+#define NPCM8XX_RESET_VIRUART1		16
+#define NPCM8XX_RESET_VIRUART2		17
+#define NPCM8XX_RESET_SIOX1		18
+#define NPCM8XX_RESET_SIOX2		19
+#define NPCM8XX_RESET_BT		20
+#define NPCM8XX_RESET_3DES		21
+#define NPCM8XX_RESET_PSPI2		23
+#define NPCM8XX_RESET_GMAC2		25
+#define NPCM8XX_RESET_USBH1		26
+#define NPCM8XX_RESET_GMAC1		28
+#define NPCM8XX_RESET_CP1		31
+
+/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
+#define NPCM8XX_RESET_PWM_M1		0
+#define NPCM8XX_RESET_SMB12		1
+#define NPCM8XX_RESET_SPIX		2
+#define NPCM8XX_RESET_SMB13		3
+#define NPCM8XX_RESET_UDC0		4
+#define NPCM8XX_RESET_UDC7		5
+#define NPCM8XX_RESET_UDC8		6
+#define NPCM8XX_RESET_UDC9		7
+#define NPCM8XX_RESET_USBHUB		8
+#define NPCM8XX_RESET_PCI_MAILBOX	9
+#define NPCM8XX_RESET_GDMA1		10
+#define NPCM8XX_RESET_GDMA2		11
+#define NPCM8XX_RESET_SMB14		12
+#define NPCM8XX_RESET_SHA		13
+#define NPCM8XX_RESET_SEC_ECC		14
+#define NPCM8XX_RESET_PCIE_RC		15
+#define NPCM8XX_RESET_TIMER_10_14	16
+#define NPCM8XX_RESET_RNG		17
+#define NPCM8XX_RESET_SMB15		18
+#define NPCM8XX_RESET_SMB8		19
+#define NPCM8XX_RESET_SMB9		20
+#define NPCM8XX_RESET_SMB10		21
+#define NPCM8XX_RESET_SMB11		22
+#define NPCM8XX_RESET_ESPI		23
+#define NPCM8XX_RESET_USB_PHY_1		24
+#define NPCM8XX_RESET_USB_PHY_2		25
+
+/* Reset lines on IP4 reset module (NPCM8XX_RESET_IPSRST4) */
+#define NPCM8XX_RESET_SMB16		0
+#define NPCM8XX_RESET_SMB17		1
+#define NPCM8XX_RESET_SMB18		2
+#define NPCM8XX_RESET_SMB19		3
+#define NPCM8XX_RESET_SMB20		4
+#define NPCM8XX_RESET_SMB21		5
+#define NPCM8XX_RESET_SMB22		6
+#define NPCM8XX_RESET_SMB23		7
+#define NPCM8XX_RESET_I3C0		8
+#define NPCM8XX_RESET_I3C1		9
+#define NPCM8XX_RESET_I3C2		10
+#define NPCM8XX_RESET_I3C3		11
+#define NPCM8XX_RESET_I3C4		12
+#define NPCM8XX_RESET_I3C5		13
+#define NPCM8XX_RESET_UART4		16
+#define NPCM8XX_RESET_UART5		17
+#define NPCM8XX_RESET_UART6		18
+#define NPCM8XX_RESET_PCIMBX2		19
+#define NPCM8XX_RESET_SMB24		22
+#define NPCM8XX_RESET_SMB25		23
+#define NPCM8XX_RESET_SMB26		24
+#define NPCM8XX_RESET_USBPHY3		25
+#define NPCM8XX_RESET_PCIRCPHY		27
+#define NPCM8XX_RESET_PWM_M2		28
+#define NPCM8XX_RESET_JTM1		29
+#define NPCM8XX_RESET_JTM2		30
+#define NPCM8XX_RESET_USBH2		31
+
+#endif
-- 
2.33.0

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add binding document and device tree binding
> constants for Nuvoton BMC NPCM8XX reset controller.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../bindings/reset/nuvoton,npcm-reset.txt     |  17 ++-
>  .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 ++++++++++++++++++
>  2 files changed, 139 insertions(+), 2 deletions(-)
>  create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> 
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> index cb1613092ee7..b7eb8615b68b 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> @@ -1,14 +1,15 @@
>  Nuvoton NPCM Reset controller
>  
>  Required properties:
> -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
> +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC.
> +               "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC.
>  - reg : specifies physical base address and size of the register.
>  - #reset-cells: must be set to 2
>  - syscon: a phandle to access GCR registers.
>  
>  Optional property:
>  - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
> -  NPCM7xx contain four software reset that represent numbers 1 to 4.
> +  NPCM7xx and NPCM8xx contain four software reset that represent numbers 1 to 4.
>  
>    If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
>  
> @@ -32,3 +33,15 @@ example:
>          };
>  
>  The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
> +
> +Specifying reset lines connected to IP NPCM8XX modules
> +======================================================

No need to document consumers. Just mention the header.

> +example:
> +
> +        spi0: spi@..... {
> +                ...
> +                resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI1>;
> +                ...
> +        };
> +
> +The index could be found in <dt-bindings/reset/nuvoton,npcm8xx-reset.h>.
> diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> new file mode 100644
> index 000000000000..4b832a0fd1dd
> --- /dev/null
> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> @@ -0,0 +1,124 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license.

> +// Copyright (c) 2022 Nuvoton Technology corporation.
> +
> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> +
> +#define NPCM8XX_RESET_IPSRST1		0x20
> +#define NPCM8XX_RESET_IPSRST2		0x24
> +#define NPCM8XX_RESET_IPSRST3		0x34
> +#define NPCM8XX_RESET_IPSRST4		0x74

What are these? All IDs should be incremental, decimal and start from 0.

> +
> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> +#define NPCM8XX_RESET_GDMA0		3

IDs start from 0 and do not have holes.


> +#define NPCM8XX_RESET_UDC1		5
> +#define NPCM8XX_RESET_GMAC3		6
> +#define NPCM8XX_RESET_UART_2_3		7
> +#define NPCM8XX_RESET_UDC2		8
> +#define NPCM8XX_RESET_PECI		9
> +#define NPCM8XX_RESET_AES		10
> +#define NPCM8XX_RESET_UART_0_1		11
> +#define NPCM8XX_RESET_MC		12
> +#define NPCM8XX_RESET_SMB2		13
> +#define NPCM8XX_RESET_SMB3		14
> +#define NPCM8XX_RESET_SMB4		15
> +#define NPCM8XX_RESET_SMB5		16
> +#define NPCM8XX_RESET_PWM_M0		18
> +#define NPCM8XX_RESET_TIMER_0_4		19
> +#define NPCM8XX_RESET_TIMER_5_9		20
> +#define NPCM8XX_RESET_GMAC4		21
> +#define NPCM8XX_RESET_UDC4		22
> +#define NPCM8XX_RESET_UDC5		23
> +#define NPCM8XX_RESET_UDC6		24
> +#define NPCM8XX_RESET_UDC3		25
> +#define NPCM8XX_RESET_ADC		27
> +#define NPCM8XX_RESET_SMB6		28
> +#define NPCM8XX_RESET_SMB7		29
> +#define NPCM8XX_RESET_SMB0		30
> +#define NPCM8XX_RESET_SMB1		31
> +
> +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
> +#define NPCM8XX_RESET_MFT0		0
> +#define NPCM8XX_RESET_MFT1		1
> +#define NPCM8XX_RESET_MFT2		2
> +#define NPCM8XX_RESET_MFT3		3
> +#define NPCM8XX_RESET_MFT4		4
> +#define NPCM8XX_RESET_MFT5		5
> +#define NPCM8XX_RESET_MFT6		6
> +#define NPCM8XX_RESET_MFT7		7
> +#define NPCM8XX_RESET_MMC		8
> +#define NPCM8XX_RESET_GFX_SYS		10
> +#define NPCM8XX_RESET_AHB_PCIBRG	11
> +#define NPCM8XX_RESET_VDMA		12
> +#define NPCM8XX_RESET_ECE		13
> +#define NPCM8XX_RESET_VCD		14
> +#define NPCM8XX_RESET_VIRUART1		16
> +#define NPCM8XX_RESET_VIRUART2		17
> +#define NPCM8XX_RESET_SIOX1		18
> +#define NPCM8XX_RESET_SIOX2		19
> +#define NPCM8XX_RESET_BT		20
> +#define NPCM8XX_RESET_3DES		21
> +#define NPCM8XX_RESET_PSPI2		23
> +#define NPCM8XX_RESET_GMAC2		25
> +#define NPCM8XX_RESET_USBH1		26
> +#define NPCM8XX_RESET_GMAC1		28
> +#define NPCM8XX_RESET_CP1		31
> +
> +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
> +#define NPCM8XX_RESET_PWM_M1		0
> +#define NPCM8XX_RESET_SMB12		1
> +#define NPCM8XX_RESET_SPIX		2
> +#define NPCM8XX_RESET_SMB13		3
> +#define NPCM8XX_RESET_UDC0		4
> +#define NPCM8XX_RESET_UDC7		5
> +#define NPCM8XX_RESET_UDC8		6
> +#define NPCM8XX_RESET_UDC9		7
> +#define NPCM8XX_RESET_USBHUB		8
> +#define NPCM8XX_RESET_PCI_MAILBOX	9
> +#define NPCM8XX_RESET_GDMA1		10
> +#define NPCM8XX_RESET_GDMA2		11
> +#define NPCM8XX_RESET_SMB14		12
> +#define NPCM8XX_RESET_SHA		13
> +#define NPCM8XX_RESET_SEC_ECC		14
> +#define NPCM8XX_RESET_PCIE_RC		15
> +#define NPCM8XX_RESET_TIMER_10_14	16
> +#define NPCM8XX_RESET_RNG		17
> +#define NPCM8XX_RESET_SMB15		18
> +#define NPCM8XX_RESET_SMB8		19
> +#define NPCM8XX_RESET_SMB9		20
> +#define NPCM8XX_RESET_SMB10		21
> +#define NPCM8XX_RESET_SMB11		22
> +#define NPCM8XX_RESET_ESPI		23
> +#define NPCM8XX_RESET_USB_PHY_1		24
> +#define NPCM8XX_RESET_USB_PHY_2		25
> +


Best regards,
Krzysztof

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add binding document and device tree binding
> constants for Nuvoton BMC NPCM8XX reset controller.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../bindings/reset/nuvoton,npcm-reset.txt     |  17 ++-
>  .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 ++++++++++++++++++
>  2 files changed, 139 insertions(+), 2 deletions(-)
>  create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> 
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> index cb1613092ee7..b7eb8615b68b 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> @@ -1,14 +1,15 @@
>  Nuvoton NPCM Reset controller
>  
>  Required properties:
> -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
> +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC.
> +               "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC.
>  - reg : specifies physical base address and size of the register.
>  - #reset-cells: must be set to 2
>  - syscon: a phandle to access GCR registers.
>  
>  Optional property:
>  - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
> -  NPCM7xx contain four software reset that represent numbers 1 to 4.
> +  NPCM7xx and NPCM8xx contain four software reset that represent numbers 1 to 4.
>  
>    If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
>  
> @@ -32,3 +33,15 @@ example:
>          };
>  
>  The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
> +
> +Specifying reset lines connected to IP NPCM8XX modules
> +======================================================

No need to document consumers. Just mention the header.

> +example:
> +
> +        spi0: spi@..... {
> +                ...
> +                resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI1>;
> +                ...
> +        };
> +
> +The index could be found in <dt-bindings/reset/nuvoton,npcm8xx-reset.h>.
> diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> new file mode 100644
> index 000000000000..4b832a0fd1dd
> --- /dev/null
> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> @@ -0,0 +1,124 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license.

> +// Copyright (c) 2022 Nuvoton Technology corporation.
> +
> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> +
> +#define NPCM8XX_RESET_IPSRST1		0x20
> +#define NPCM8XX_RESET_IPSRST2		0x24
> +#define NPCM8XX_RESET_IPSRST3		0x34
> +#define NPCM8XX_RESET_IPSRST4		0x74

What are these? All IDs should be incremental, decimal and start from 0.

> +
> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> +#define NPCM8XX_RESET_GDMA0		3

IDs start from 0 and do not have holes.


> +#define NPCM8XX_RESET_UDC1		5
> +#define NPCM8XX_RESET_GMAC3		6
> +#define NPCM8XX_RESET_UART_2_3		7
> +#define NPCM8XX_RESET_UDC2		8
> +#define NPCM8XX_RESET_PECI		9
> +#define NPCM8XX_RESET_AES		10
> +#define NPCM8XX_RESET_UART_0_1		11
> +#define NPCM8XX_RESET_MC		12
> +#define NPCM8XX_RESET_SMB2		13
> +#define NPCM8XX_RESET_SMB3		14
> +#define NPCM8XX_RESET_SMB4		15
> +#define NPCM8XX_RESET_SMB5		16
> +#define NPCM8XX_RESET_PWM_M0		18
> +#define NPCM8XX_RESET_TIMER_0_4		19
> +#define NPCM8XX_RESET_TIMER_5_9		20
> +#define NPCM8XX_RESET_GMAC4		21
> +#define NPCM8XX_RESET_UDC4		22
> +#define NPCM8XX_RESET_UDC5		23
> +#define NPCM8XX_RESET_UDC6		24
> +#define NPCM8XX_RESET_UDC3		25
> +#define NPCM8XX_RESET_ADC		27
> +#define NPCM8XX_RESET_SMB6		28
> +#define NPCM8XX_RESET_SMB7		29
> +#define NPCM8XX_RESET_SMB0		30
> +#define NPCM8XX_RESET_SMB1		31
> +
> +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
> +#define NPCM8XX_RESET_MFT0		0
> +#define NPCM8XX_RESET_MFT1		1
> +#define NPCM8XX_RESET_MFT2		2
> +#define NPCM8XX_RESET_MFT3		3
> +#define NPCM8XX_RESET_MFT4		4
> +#define NPCM8XX_RESET_MFT5		5
> +#define NPCM8XX_RESET_MFT6		6
> +#define NPCM8XX_RESET_MFT7		7
> +#define NPCM8XX_RESET_MMC		8
> +#define NPCM8XX_RESET_GFX_SYS		10
> +#define NPCM8XX_RESET_AHB_PCIBRG	11
> +#define NPCM8XX_RESET_VDMA		12
> +#define NPCM8XX_RESET_ECE		13
> +#define NPCM8XX_RESET_VCD		14
> +#define NPCM8XX_RESET_VIRUART1		16
> +#define NPCM8XX_RESET_VIRUART2		17
> +#define NPCM8XX_RESET_SIOX1		18
> +#define NPCM8XX_RESET_SIOX2		19
> +#define NPCM8XX_RESET_BT		20
> +#define NPCM8XX_RESET_3DES		21
> +#define NPCM8XX_RESET_PSPI2		23
> +#define NPCM8XX_RESET_GMAC2		25
> +#define NPCM8XX_RESET_USBH1		26
> +#define NPCM8XX_RESET_GMAC1		28
> +#define NPCM8XX_RESET_CP1		31
> +
> +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
> +#define NPCM8XX_RESET_PWM_M1		0
> +#define NPCM8XX_RESET_SMB12		1
> +#define NPCM8XX_RESET_SPIX		2
> +#define NPCM8XX_RESET_SMB13		3
> +#define NPCM8XX_RESET_UDC0		4
> +#define NPCM8XX_RESET_UDC7		5
> +#define NPCM8XX_RESET_UDC8		6
> +#define NPCM8XX_RESET_UDC9		7
> +#define NPCM8XX_RESET_USBHUB		8
> +#define NPCM8XX_RESET_PCI_MAILBOX	9
> +#define NPCM8XX_RESET_GDMA1		10
> +#define NPCM8XX_RESET_GDMA2		11
> +#define NPCM8XX_RESET_SMB14		12
> +#define NPCM8XX_RESET_SHA		13
> +#define NPCM8XX_RESET_SEC_ECC		14
> +#define NPCM8XX_RESET_PCIE_RC		15
> +#define NPCM8XX_RESET_TIMER_10_14	16
> +#define NPCM8XX_RESET_RNG		17
> +#define NPCM8XX_RESET_SMB15		18
> +#define NPCM8XX_RESET_SMB8		19
> +#define NPCM8XX_RESET_SMB9		20
> +#define NPCM8XX_RESET_SMB10		21
> +#define NPCM8XX_RESET_SMB11		22
> +#define NPCM8XX_RESET_ESPI		23
> +#define NPCM8XX_RESET_USB_PHY_1		24
> +#define NPCM8XX_RESET_USB_PHY_2		25
> +


Best regards,
Krzysztof

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Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Tomer Maimon]

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Hi Krzysztof,

Thanks for your comments.


On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <
krzysztof.kozlowski@linaro.org> wrote:

> On 22/05/2022 17:50, Tomer Maimon wrote:
> > Add binding document and device tree binding
> > constants for Nuvoton BMC NPCM8XX reset controller.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  .../bindings/reset/nuvoton,npcm-reset.txt     |  17 ++-
> >  .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 ++++++++++++++++++
> >  2 files changed, 139 insertions(+), 2 deletions(-)
> >  create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> >
> > diff --git
> a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> > index cb1613092ee7..b7eb8615b68b 100644
> > --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> > @@ -1,14 +1,15 @@
> >  Nuvoton NPCM Reset controller
> >
> >  Required properties:
> > -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
> > +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC.
> > +               "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC.
> >  - reg : specifies physical base address and size of the register.
> >  - #reset-cells: must be set to 2
> >  - syscon: a phandle to access GCR registers.
> >
> >  Optional property:
> >  - nuvoton,sw-reset-number - Contains the software reset number to
> restart the SoC.
> > -  NPCM7xx contain four software reset that represent numbers 1 to 4.
> > +  NPCM7xx and NPCM8xx contain four software reset that represent
> numbers 1 to 4.
> >
> >    If 'nuvoton,sw-reset-number' is not specified software reset is
> disabled.
> >
> > @@ -32,3 +33,15 @@ example:
> >          };
> >
> >  The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
> > +
> > +Specifying reset lines connected to IP NPCM8XX modules
> > +======================================================
>
> we prefer to use the same explanation as the NPCM7XX reset explanation in
the reset binding document.

> No need to document consumers. Just mention the header.
>
> > +example:
> > +
> > +        spi0: spi@..... {
> > +                ...
> > +                resets = <&rstc NPCM8XX_RESET_IPSRST2
> NPCM8XX_RESET_PSPI1>;
> > +                ...
> > +        };
> > +
> > +The index could be found in <dt-bindings/reset/nuvoton,npcm8xx-reset.h>.
> > diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> > new file mode 100644
> > index 000000000000..4b832a0fd1dd
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> > @@ -0,0 +1,124 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> Dual license.
>
O.K.

>
> > +// Copyright (c) 2022 Nuvoton Technology corporation.
> > +
> > +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> > +#define _DT_BINDINGS_NPCM8XX_RESET_H
> > +
> > +#define NPCM8XX_RESET_IPSRST1                0x20
> > +#define NPCM8XX_RESET_IPSRST2                0x24
> > +#define NPCM8XX_RESET_IPSRST3                0x34
> > +#define NPCM8XX_RESET_IPSRST4                0x74
>
> What are these? All IDs should be incremental, decimal and start from 0.
>
Register offset, we use the same method in NPCM7xx. please refer
https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

and the driver asserts the reset according to the reset include definitions

>
> > +
> > +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> > +#define NPCM8XX_RESET_GDMA0          3
>
> IDs start from 0 and do not have holes.
>
This represents the reset BIT in the reset register.

>
>
> > +#define NPCM8XX_RESET_UDC1           5
> > +#define NPCM8XX_RESET_GMAC3          6
> > +#define NPCM8XX_RESET_UART_2_3               7
> > +#define NPCM8XX_RESET_UDC2           8
> > +#define NPCM8XX_RESET_PECI           9
> > +#define NPCM8XX_RESET_AES            10
> > +#define NPCM8XX_RESET_UART_0_1               11
> > +#define NPCM8XX_RESET_MC             12
> > +#define NPCM8XX_RESET_SMB2           13
> > +#define NPCM8XX_RESET_SMB3           14
> > +#define NPCM8XX_RESET_SMB4           15
> > +#define NPCM8XX_RESET_SMB5           16
> > +#define NPCM8XX_RESET_PWM_M0         18
> > +#define NPCM8XX_RESET_TIMER_0_4              19
> > +#define NPCM8XX_RESET_TIMER_5_9              20
> > +#define NPCM8XX_RESET_GMAC4          21
> > +#define NPCM8XX_RESET_UDC4           22
> > +#define NPCM8XX_RESET_UDC5           23
> > +#define NPCM8XX_RESET_UDC6           24
> > +#define NPCM8XX_RESET_UDC3           25
> > +#define NPCM8XX_RESET_ADC            27
> > +#define NPCM8XX_RESET_SMB6           28
> > +#define NPCM8XX_RESET_SMB7           29
> > +#define NPCM8XX_RESET_SMB0           30
> > +#define NPCM8XX_RESET_SMB1           31
> > +
> > +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
> > +#define NPCM8XX_RESET_MFT0           0
> > +#define NPCM8XX_RESET_MFT1           1
> > +#define NPCM8XX_RESET_MFT2           2
> > +#define NPCM8XX_RESET_MFT3           3
> > +#define NPCM8XX_RESET_MFT4           4
> > +#define NPCM8XX_RESET_MFT5           5
> > +#define NPCM8XX_RESET_MFT6           6
> > +#define NPCM8XX_RESET_MFT7           7
> > +#define NPCM8XX_RESET_MMC            8
> > +#define NPCM8XX_RESET_GFX_SYS                10
> > +#define NPCM8XX_RESET_AHB_PCIBRG     11
> > +#define NPCM8XX_RESET_VDMA           12
> > +#define NPCM8XX_RESET_ECE            13
> > +#define NPCM8XX_RESET_VCD            14
> > +#define NPCM8XX_RESET_VIRUART1               16
> > +#define NPCM8XX_RESET_VIRUART2               17
> > +#define NPCM8XX_RESET_SIOX1          18
> > +#define NPCM8XX_RESET_SIOX2          19
> > +#define NPCM8XX_RESET_BT             20
> > +#define NPCM8XX_RESET_3DES           21
> > +#define NPCM8XX_RESET_PSPI2          23
> > +#define NPCM8XX_RESET_GMAC2          25
> > +#define NPCM8XX_RESET_USBH1          26
> > +#define NPCM8XX_RESET_GMAC1          28
> > +#define NPCM8XX_RESET_CP1            31
> > +
> > +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
> > +#define NPCM8XX_RESET_PWM_M1         0
> > +#define NPCM8XX_RESET_SMB12          1
> > +#define NPCM8XX_RESET_SPIX           2
> > +#define NPCM8XX_RESET_SMB13          3
> > +#define NPCM8XX_RESET_UDC0           4
> > +#define NPCM8XX_RESET_UDC7           5
> > +#define NPCM8XX_RESET_UDC8           6
> > +#define NPCM8XX_RESET_UDC9           7
> > +#define NPCM8XX_RESET_USBHUB         8
> > +#define NPCM8XX_RESET_PCI_MAILBOX    9
> > +#define NPCM8XX_RESET_GDMA1          10
> > +#define NPCM8XX_RESET_GDMA2          11
> > +#define NPCM8XX_RESET_SMB14          12
> > +#define NPCM8XX_RESET_SHA            13
> > +#define NPCM8XX_RESET_SEC_ECC                14
> > +#define NPCM8XX_RESET_PCIE_RC                15
> > +#define NPCM8XX_RESET_TIMER_10_14    16
> > +#define NPCM8XX_RESET_RNG            17
> > +#define NPCM8XX_RESET_SMB15          18
> > +#define NPCM8XX_RESET_SMB8           19
> > +#define NPCM8XX_RESET_SMB9           20
> > +#define NPCM8XX_RESET_SMB10          21
> > +#define NPCM8XX_RESET_SMB11          22
> > +#define NPCM8XX_RESET_ESPI           23
> > +#define NPCM8XX_RESET_USB_PHY_1              24
> > +#define NPCM8XX_RESET_USB_PHY_2              25
> > +
>
>
> Best regards,
> Krzysztof
>

Best regards,

Tomer

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Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Geert Uytterhoeven]

Hi Tomer,

On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> On 22/05/2022 17:50, Tomer Maimon wrote:
>> > Add binding document and device tree binding
>> > constants for Nuvoton BMC NPCM8XX reset controller.
>> >
>> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

>> > --- /dev/null
>> > +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>> > @@ -0,0 +1,124 @@
>> > +/* SPDX-License-Identifier: GPL-2.0 */
>> > +// Copyright (c) 2022 Nuvoton Technology corporation.
>> > +
>> > +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>> > +#define _DT_BINDINGS_NPCM8XX_RESET_H
>> > +
>> > +#define NPCM8XX_RESET_IPSRST1                0x20
>> > +#define NPCM8XX_RESET_IPSRST2                0x24
>> > +#define NPCM8XX_RESET_IPSRST3                0x34
>> > +#define NPCM8XX_RESET_IPSRST4                0x74
>>
>> What are these? All IDs should be incremental, decimal and start from 0.
>
> Register offset, we use the same method in NPCM7xx. please refer
> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
>
> and the driver asserts the reset according to the reset include definitions

So if they're easy to look up the values, you could do without the
definitions? Cfr. the interrupts properties in .dtsi files, where we
typically just use the hardcoded numbers.

If you do decide to keep them, a comment explaining their origins
would be useful.

>> > +
>> > +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>> > +#define NPCM8XX_RESET_GDMA0          3
>>
>> IDs start from 0 and do not have holes.
>
> This represents the reset BIT in the reset register.

Likewise, I think it's a good idea to document that in a comment, cfr.
https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Geert Uytterhoeven]

Hi Tomer,

On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>> On 22/05/2022 17:50, Tomer Maimon wrote:
>> > Add binding document and device tree binding
>> > constants for Nuvoton BMC NPCM8XX reset controller.
>> >
>> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

>> > --- /dev/null
>> > +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>> > @@ -0,0 +1,124 @@
>> > +/* SPDX-License-Identifier: GPL-2.0 */
>> > +// Copyright (c) 2022 Nuvoton Technology corporation.
>> > +
>> > +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>> > +#define _DT_BINDINGS_NPCM8XX_RESET_H
>> > +
>> > +#define NPCM8XX_RESET_IPSRST1                0x20
>> > +#define NPCM8XX_RESET_IPSRST2                0x24
>> > +#define NPCM8XX_RESET_IPSRST3                0x34
>> > +#define NPCM8XX_RESET_IPSRST4                0x74
>>
>> What are these? All IDs should be incremental, decimal and start from 0.
>
> Register offset, we use the same method in NPCM7xx. please refer
> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
>
> and the driver asserts the reset according to the reset include definitions

So if they're easy to look up the values, you could do without the
definitions? Cfr. the interrupts properties in .dtsi files, where we
typically just use the hardcoded numbers.

If you do decide to keep them, a comment explaining their origins
would be useful.

>> > +
>> > +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>> > +#define NPCM8XX_RESET_GDMA0          3
>>
>> IDs start from 0 and do not have holes.
>
> This represents the reset BIT in the reset register.

Likewise, I think it's a good idea to document that in a comment, cfr.
https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> Hi Tomer,
> 
> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>>> Add binding document and device tree binding
>>>> constants for Nuvoton BMC NPCM8XX reset controller.
>>>>
>>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> 
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>>>> @@ -0,0 +1,124 @@
>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
>>>> +
>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
>>>> +
>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
>>>
>>> What are these? All IDs should be incremental, decimal and start from 0.
>>
>> Register offset, we use the same method in NPCM7xx. please refer
>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
>>
>> and the driver asserts the reset according to the reset include definitions
> 
> So if they're easy to look up the values, you could do without the
> definitions? Cfr. the interrupts properties in .dtsi files, where we
> typically just use the hardcoded numbers.
> 
> If you do decide to keep them, a comment explaining their origins
> would be useful.
> 
>>>> +
>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>>>> +#define NPCM8XX_RESET_GDMA0          3
>>>
>>> IDs start from 0 and do not have holes.
>>
>> This represents the reset BIT in the reset register.
> 
> Likewise, I think it's a good idea to document that in a comment, cfr.
> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8

Renesas is also doing it not correct (just like many others). The
bindings are not for register bits or offsets. Such data can be DTS but
not part of bindings. Imagine now you made mistake in this register
offset and hardware uses slightly different value. What now? Change
bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.


Best regards,
Krzysztof

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> Hi Tomer,
> 
> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>>> Add binding document and device tree binding
>>>> constants for Nuvoton BMC NPCM8XX reset controller.
>>>>
>>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> 
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>>>> @@ -0,0 +1,124 @@
>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
>>>> +
>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
>>>> +
>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
>>>
>>> What are these? All IDs should be incremental, decimal and start from 0.
>>
>> Register offset, we use the same method in NPCM7xx. please refer
>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
>>
>> and the driver asserts the reset according to the reset include definitions
> 
> So if they're easy to look up the values, you could do without the
> definitions? Cfr. the interrupts properties in .dtsi files, where we
> typically just use the hardcoded numbers.
> 
> If you do decide to keep them, a comment explaining their origins
> would be useful.
> 
>>>> +
>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>>>> +#define NPCM8XX_RESET_GDMA0          3
>>>
>>> IDs start from 0 and do not have holes.
>>
>> This represents the reset BIT in the reset register.
> 
> Likewise, I think it's a good idea to document that in a comment, cfr.
> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8

Renesas is also doing it not correct (just like many others). The
bindings are not for register bits or offsets. Such data can be DTS but
not part of bindings. Imagine now you made mistake in this register
offset and hardware uses slightly different value. What now? Change
bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Geert Uytterhoeven]

Hi Krzysztof,

On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> > On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> >>> On 22/05/2022 17:50, Tomer Maimon wrote:
> >>>> Add binding document and device tree binding
> >>>> constants for Nuvoton BMC NPCM8XX reset controller.
> >>>>
> >>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> >
> >>>> --- /dev/null
> >>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> >>>> @@ -0,0 +1,124 @@
> >>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
> >>>> +
> >>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> >>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> >>>> +
> >>>> +#define NPCM8XX_RESET_IPSRST1                0x20
> >>>> +#define NPCM8XX_RESET_IPSRST2                0x24
> >>>> +#define NPCM8XX_RESET_IPSRST3                0x34
> >>>> +#define NPCM8XX_RESET_IPSRST4                0x74
> >>>
> >>> What are these? All IDs should be incremental, decimal and start from 0.
> >>
> >> Register offset, we use the same method in NPCM7xx. please refer
> >> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> >>
> >> and the driver asserts the reset according to the reset include definitions
> >
> > So if they're easy to look up the values, you could do without the
> > definitions? Cfr. the interrupts properties in .dtsi files, where we
> > typically just use the hardcoded numbers.
> >
> > If you do decide to keep them, a comment explaining their origins
> > would be useful.
> >
> >>>> +
> >>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> >>>> +#define NPCM8XX_RESET_GDMA0          3
> >>>
> >>> IDs start from 0 and do not have holes.
> >>
> >> This represents the reset BIT in the reset register.
> >
> > Likewise, I think it's a good idea to document that in a comment, cfr.
> > https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
>
> Renesas is also doing it not correct (just like many others). The
> bindings are not for register bits or offsets. Such data can be DTS but
> not part of bindings.

I think you are taking a too-extremist standpoint.
The two extremes are:
  1. Numbers correspond to hardware numbers, and are easy to look up
    in the hardware documentation (e.g. GIC SPI interrupt numbers).
     => Use the hardcoded numbers in DTS.
  2. Numbers do not correspond to hardware numbers, so we had to
     invent our own definitions and numbers, usually loosely
     based on some table in the hardware documentation.
     The driver will have to look up the numbers in a data
     structure, to know how to program the hardware.
     The numbers become part of the DT ABI, and cannot be changed
     (header file is append-only).
     => Use the binding definitions in DTS.

We are taking the middle ground: there is a one-to-one relation between
numbers and hardware numbers that can be looked up in or derived from
the hardware documentation, but the conversion is non-trivial (for the
casual human reviewer), or the documentation refers to names instead
of numbers in most sections (e.g. named power domains). Then why not
let the numbers match some feature in the hardware (e.g. register
offset or register bit)?

> Imagine now you made mistake in this register
> offset and hardware uses slightly different value. What now? Change
> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.

I see no difference here with using the wrong interrupt number in an
interrupts property in DTS.  What do we do in that case? Fix the DTS.

BTW, are you aware of any driver that transforms interrupt numbers
obtained from DTS, because the DTS used the wrong number?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Geert Uytterhoeven]

Hi Krzysztof,

On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> > On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> >>> On 22/05/2022 17:50, Tomer Maimon wrote:
> >>>> Add binding document and device tree binding
> >>>> constants for Nuvoton BMC NPCM8XX reset controller.
> >>>>
> >>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> >
> >>>> --- /dev/null
> >>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> >>>> @@ -0,0 +1,124 @@
> >>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
> >>>> +
> >>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> >>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> >>>> +
> >>>> +#define NPCM8XX_RESET_IPSRST1                0x20
> >>>> +#define NPCM8XX_RESET_IPSRST2                0x24
> >>>> +#define NPCM8XX_RESET_IPSRST3                0x34
> >>>> +#define NPCM8XX_RESET_IPSRST4                0x74
> >>>
> >>> What are these? All IDs should be incremental, decimal and start from 0.
> >>
> >> Register offset, we use the same method in NPCM7xx. please refer
> >> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> >>
> >> and the driver asserts the reset according to the reset include definitions
> >
> > So if they're easy to look up the values, you could do without the
> > definitions? Cfr. the interrupts properties in .dtsi files, where we
> > typically just use the hardcoded numbers.
> >
> > If you do decide to keep them, a comment explaining their origins
> > would be useful.
> >
> >>>> +
> >>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> >>>> +#define NPCM8XX_RESET_GDMA0          3
> >>>
> >>> IDs start from 0 and do not have holes.
> >>
> >> This represents the reset BIT in the reset register.
> >
> > Likewise, I think it's a good idea to document that in a comment, cfr.
> > https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
>
> Renesas is also doing it not correct (just like many others). The
> bindings are not for register bits or offsets. Such data can be DTS but
> not part of bindings.

I think you are taking a too-extremist standpoint.
The two extremes are:
  1. Numbers correspond to hardware numbers, and are easy to look up
    in the hardware documentation (e.g. GIC SPI interrupt numbers).
     => Use the hardcoded numbers in DTS.
  2. Numbers do not correspond to hardware numbers, so we had to
     invent our own definitions and numbers, usually loosely
     based on some table in the hardware documentation.
     The driver will have to look up the numbers in a data
     structure, to know how to program the hardware.
     The numbers become part of the DT ABI, and cannot be changed
     (header file is append-only).
     => Use the binding definitions in DTS.

We are taking the middle ground: there is a one-to-one relation between
numbers and hardware numbers that can be looked up in or derived from
the hardware documentation, but the conversion is non-trivial (for the
casual human reviewer), or the documentation refers to names instead
of numbers in most sections (e.g. named power domains). Then why not
let the numbers match some feature in the hardware (e.g. register
offset or register bit)?

> Imagine now you made mistake in this register
> offset and hardware uses slightly different value. What now? Change
> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.

I see no difference here with using the wrong interrupt number in an
interrupts property in DTS.  What do we do in that case? Fix the DTS.

BTW, are you aware of any driver that transforms interrupt numbers
obtained from DTS, because the DTS used the wrong number?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 17:11, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
>>> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>>>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>>>>> Add binding document and device tree binding
>>>>>> constants for Nuvoton BMC NPCM8XX reset controller.
>>>>>>
>>>>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>>>
>>>>>> --- /dev/null
>>>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>>>>>> @@ -0,0 +1,124 @@
>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
>>>>>> +
>>>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>>>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
>>>>>> +
>>>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
>>>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
>>>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
>>>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
>>>>>
>>>>> What are these? All IDs should be incremental, decimal and start from 0.
>>>>
>>>> Register offset, we use the same method in NPCM7xx. please refer
>>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
>>>>
>>>> and the driver asserts the reset according to the reset include definitions
>>>
>>> So if they're easy to look up the values, you could do without the
>>> definitions? Cfr. the interrupts properties in .dtsi files, where we
>>> typically just use the hardcoded numbers.
>>>
>>> If you do decide to keep them, a comment explaining their origins
>>> would be useful.
>>>
>>>>>> +
>>>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>>>>>> +#define NPCM8XX_RESET_GDMA0          3
>>>>>
>>>>> IDs start from 0 and do not have holes.
>>>>
>>>> This represents the reset BIT in the reset register.
>>>
>>> Likewise, I think it's a good idea to document that in a comment, cfr.
>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
>>
>> Renesas is also doing it not correct (just like many others). The
>> bindings are not for register bits or offsets. Such data can be DTS but
>> not part of bindings.
> 
> I think you are taking a too-extremist standpoint.
> The two extremes are:
>   1. Numbers correspond to hardware numbers, and are easy to look up
>     in the hardware documentation (e.g. GIC SPI interrupt numbers).
>      => Use the hardcoded numbers in DTS.

And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
They go to DTS only.

>   2. Numbers do not correspond to hardware numbers, so we had to
>      invent our own definitions and numbers, usually loosely
>      based on some table in the hardware documentation.
>      The driver will have to look up the numbers in a data
>      structure, to know how to program the hardware.
>      The numbers become part of the DT ABI, and cannot be changed
>      (header file is append-only).
>      => Use the binding definitions in DTS.

Correct.

However this patch is some mixture of both approaches.

The same pointed by Arnd:
https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

> We are taking the middle ground: there is a one-to-one relation between
> numbers and hardware numbers that can be looked up in or derived from
> the hardware documentation, but the conversion is non-trivial (for the
> casual human reviewer), or the documentation refers to names instead
> of numbers in most sections (e.g. named power domains). Then why not
> let the numbers match some feature in the hardware (e.g. register
> offset or register bit)?

Because you are embedding the device programming model into the
bindings. It's the same as having properties:
"vendor,value-for-register-xxx"

We do not create bindings to describe programming model but hardware.
Using the values from programming model is fragile and ties the bindings
to that one programming model. Programming model can change, e.g. by
mistake, but bindings should stay independent.

> 
>> Imagine now you made mistake in this register
>> offset and hardware uses slightly different value. What now? Change
>> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.
> 
> I see no difference here with using the wrong interrupt number in an
> interrupts property in DTS.  What do we do in that case? Fix the DTS.

Yes, fix the DTS. DTS are not the bindings. You can fix the DTS. You
cannot fix the bindings because you affect both driver and DTS.

> 
> BTW, are you aware of any driver that transforms interrupt numbers
> obtained from DTS, because the DTS used the wrong number?

Again, what do the DTS has here at all? The interrupt numbers are also
not included in the bindings, so what does it prove?

Best regards,
Krzysztof

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 17:11, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
>>> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>>>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>>>>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>>>>> Add binding document and device tree binding
>>>>>> constants for Nuvoton BMC NPCM8XX reset controller.
>>>>>>
>>>>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
>>>
>>>>>> --- /dev/null
>>>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>>>>>> @@ -0,0 +1,124 @@
>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
>>>>>> +
>>>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>>>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
>>>>>> +
>>>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
>>>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
>>>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
>>>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
>>>>>
>>>>> What are these? All IDs should be incremental, decimal and start from 0.
>>>>
>>>> Register offset, we use the same method in NPCM7xx. please refer
>>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
>>>>
>>>> and the driver asserts the reset according to the reset include definitions
>>>
>>> So if they're easy to look up the values, you could do without the
>>> definitions? Cfr. the interrupts properties in .dtsi files, where we
>>> typically just use the hardcoded numbers.
>>>
>>> If you do decide to keep them, a comment explaining their origins
>>> would be useful.
>>>
>>>>>> +
>>>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>>>>>> +#define NPCM8XX_RESET_GDMA0          3
>>>>>
>>>>> IDs start from 0 and do not have holes.
>>>>
>>>> This represents the reset BIT in the reset register.
>>>
>>> Likewise, I think it's a good idea to document that in a comment, cfr.
>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
>>
>> Renesas is also doing it not correct (just like many others). The
>> bindings are not for register bits or offsets. Such data can be DTS but
>> not part of bindings.
> 
> I think you are taking a too-extremist standpoint.
> The two extremes are:
>   1. Numbers correspond to hardware numbers, and are easy to look up
>     in the hardware documentation (e.g. GIC SPI interrupt numbers).
>      => Use the hardcoded numbers in DTS.

And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
They go to DTS only.

>   2. Numbers do not correspond to hardware numbers, so we had to
>      invent our own definitions and numbers, usually loosely
>      based on some table in the hardware documentation.
>      The driver will have to look up the numbers in a data
>      structure, to know how to program the hardware.
>      The numbers become part of the DT ABI, and cannot be changed
>      (header file is append-only).
>      => Use the binding definitions in DTS.

Correct.

However this patch is some mixture of both approaches.

The same pointed by Arnd:
https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

> We are taking the middle ground: there is a one-to-one relation between
> numbers and hardware numbers that can be looked up in or derived from
> the hardware documentation, but the conversion is non-trivial (for the
> casual human reviewer), or the documentation refers to names instead
> of numbers in most sections (e.g. named power domains). Then why not
> let the numbers match some feature in the hardware (e.g. register
> offset or register bit)?

Because you are embedding the device programming model into the
bindings. It's the same as having properties:
"vendor,value-for-register-xxx"

We do not create bindings to describe programming model but hardware.
Using the values from programming model is fragile and ties the bindings
to that one programming model. Programming model can change, e.g. by
mistake, but bindings should stay independent.

> 
>> Imagine now you made mistake in this register
>> offset and hardware uses slightly different value. What now? Change
>> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.
> 
> I see no difference here with using the wrong interrupt number in an
> interrupts property in DTS.  What do we do in that case? Fix the DTS.

Yes, fix the DTS. DTS are not the bindings. You can fix the DTS. You
cannot fix the bindings because you affect both driver and DTS.

> 
> BTW, are you aware of any driver that transforms interrupt numbers
> obtained from DTS, because the DTS used the wrong number?

Again, what do the DTS has here at all? The interrupt numbers are also
not included in the bindings, so what does it prove?

Best regards,
Krzysztof

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Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 17:22, Krzysztof Kozlowski wrote:
>> I think you are taking a too-extremist standpoint.
>> The two extremes are:
>>   1. Numbers correspond to hardware numbers, and are easy to look up
>>     in the hardware documentation (e.g. GIC SPI interrupt numbers).
>>      => Use the hardcoded numbers in DTS.
> 
> And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
> They go to DTS only.
> 
>>   2. Numbers do not correspond to hardware numbers, so we had to
>>      invent our own definitions and numbers, usually loosely
>>      based on some table in the hardware documentation.
>>      The driver will have to look up the numbers in a data
>>      structure, to know how to program the hardware.
>>      The numbers become part of the DT ABI, and cannot be changed
>>      (header file is append-only).
>>      => Use the binding definitions in DTS.
> 
> Correct.
> 
> However this patch is some mixture of both approaches.
> 
> The same pointed by Arnd:
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

...and one more from Arnd:
https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/



Best regards,
Krzysztof

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 17:22, Krzysztof Kozlowski wrote:
>> I think you are taking a too-extremist standpoint.
>> The two extremes are:
>>   1. Numbers correspond to hardware numbers, and are easy to look up
>>     in the hardware documentation (e.g. GIC SPI interrupt numbers).
>>      => Use the hardcoded numbers in DTS.
> 
> And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
> They go to DTS only.
> 
>>   2. Numbers do not correspond to hardware numbers, so we had to
>>      invent our own definitions and numbers, usually loosely
>>      based on some table in the hardware documentation.
>>      The driver will have to look up the numbers in a data
>>      structure, to know how to program the hardware.
>>      The numbers become part of the DT ABI, and cannot be changed
>>      (header file is append-only).
>>      => Use the binding definitions in DTS.
> 
> Correct.
> 
> However this patch is some mixture of both approaches.
> 
> The same pointed by Arnd:
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/

...and one more from Arnd:
https://lore.kernel.org/linux-devicetree/CAK8P3a1APzs74YTcZ=m43G3zrmwJZKcYSTvV5eDDQX-37UY7Tw@mail.gmail.com/



Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Tomer Maimon]

Hi Krzysztof and Geert,

Appreciate your comments!

We are using the same binding method in the NPCM7XX that it is
upstreamed a few years ago.
https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

In the Reset NPCM driver we check the reset spec arguments that are
using the correct register offset and BIT.
https://github.com/torvalds/linux/blob/master/drivers/reset/reset-npcm.c#L125

One more thing,
Sorry about the mail format, I am using Gmail and now I am moving it
to plain text mode. hope it will help.
Any other suggestion to set the Gmail to work with the Linux community
will help alot

On Mon, 23 May 2022 at 18:23, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 23/05/2022 17:11, Geert Uytterhoeven wrote:
> > Hi Krzysztof,
> >
> > On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> >>> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >>>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> >>>>> On 22/05/2022 17:50, Tomer Maimon wrote:
> >>>>>> Add binding document and device tree binding
> >>>>>> constants for Nuvoton BMC NPCM8XX reset controller.
> >>>>>>
> >>>>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> >>>
> >>>>>> --- /dev/null
> >>>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> >>>>>> @@ -0,0 +1,124 @@
> >>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
> >>>>>> +
> >>>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> >>>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> >>>>>> +
> >>>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
> >>>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
> >>>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
> >>>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
> >>>>>
> >>>>> What are these? All IDs should be incremental, decimal and start from 0.
> >>>>
> >>>> Register offset, we use the same method in NPCM7xx. please refer
> >>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> >>>>
> >>>> and the driver asserts the reset according to the reset include definitions
> >>>
> >>> So if they're easy to look up the values, you could do without the
> >>> definitions? Cfr. the interrupts properties in .dtsi files, where we
> >>> typically just use the hardcoded numbers.
> >>>
> >>> If you do decide to keep them, a comment explaining their origins
> >>> would be useful.
Will do it in the next patch.
> >>>
> >>>>>> +
> >>>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> >>>>>> +#define NPCM8XX_RESET_GDMA0          3
> >>>>>
> >>>>> IDs start from 0 and do not have holes.
> >>>>
> >>>> This represents the reset BIT in the reset register.
> >>>
> >>> Likewise, I think it's a good idea to document that in a comment, cfr.
> >>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
> >>
> >> Renesas is also doing it not correct (just like many others). The
> >> bindings are not for register bits or offsets. Such data can be DTS but
> >> not part of bindings.
> >
> > I think you are taking a too-extremist standpoint.
> > The two extremes are:
> >   1. Numbers correspond to hardware numbers, and are easy to look up
> >     in the hardware documentation (e.g. GIC SPI interrupt numbers).
> >      => Use the hardcoded numbers in DTS.
>
> And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
> They go to DTS only.
>
> >   2. Numbers do not correspond to hardware numbers, so we had to
> >      invent our own definitions and numbers, usually loosely
> >      based on some table in the hardware documentation.
> >      The driver will have to look up the numbers in a data
> >      structure, to know how to program the hardware.
> >      The numbers become part of the DT ABI, and cannot be changed
> >      (header file is append-only).
> >      => Use the binding definitions in DTS.
>
> Correct.
>
> However this patch is some mixture of both approaches.
>
> The same pointed by Arnd:
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>
> > We are taking the middle ground: there is a one-to-one relation between
> > numbers and hardware numbers that can be looked up in or derived from
> > the hardware documentation, but the conversion is non-trivial (for the
> > casual human reviewer), or the documentation refers to names instead
> > of numbers in most sections (e.g. named power domains). Then why not
> > let the numbers match some feature in the hardware (e.g. register
> > offset or register bit)?
>
> Because you are embedding the device programming model into the
> bindings. It's the same as having properties:
> "vendor,value-for-register-xxx"
>
> We do not create bindings to describe programming model but hardware.
> Using the values from programming model is fragile and ties the bindings
> to that one programming model. Programming model can change, e.g. by
> mistake, but bindings should stay independent.
>
> >
> >> Imagine now you made mistake in this register
> >> offset and hardware uses slightly different value. What now? Change
> >> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.
> >
> > I see no difference here with using the wrong interrupt number in an
> > interrupts property in DTS.  What do we do in that case? Fix the DTS.
>
> Yes, fix the DTS. DTS are not the bindings. You can fix the DTS. You
> cannot fix the bindings because you affect both driver and DTS.
>
> >
> > BTW, are you aware of any driver that transforms interrupt numbers
> > obtained from DTS, because the DTS used the wrong number?
>
> Again, what do the DTS has here at all? The interrupt numbers are also
> not included in the bindings, so what does it prove?
>
> Best regards,
> Krzysztof

Best regards,

Tomer

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Tomer Maimon]

Hi Krzysztof and Geert,

Appreciate your comments!

We are using the same binding method in the NPCM7XX that it is
upstreamed a few years ago.
https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

In the Reset NPCM driver we check the reset spec arguments that are
using the correct register offset and BIT.
https://github.com/torvalds/linux/blob/master/drivers/reset/reset-npcm.c#L125

One more thing,
Sorry about the mail format, I am using Gmail and now I am moving it
to plain text mode. hope it will help.
Any other suggestion to set the Gmail to work with the Linux community
will help alot

On Mon, 23 May 2022 at 18:23, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 23/05/2022 17:11, Geert Uytterhoeven wrote:
> > Hi Krzysztof,
> >
> > On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> >>> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >>>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> >>>>> On 22/05/2022 17:50, Tomer Maimon wrote:
> >>>>>> Add binding document and device tree binding
> >>>>>> constants for Nuvoton BMC NPCM8XX reset controller.
> >>>>>>
> >>>>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> >>>
> >>>>>> --- /dev/null
> >>>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> >>>>>> @@ -0,0 +1,124 @@
> >>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
> >>>>>> +
> >>>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> >>>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> >>>>>> +
> >>>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
> >>>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
> >>>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
> >>>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
> >>>>>
> >>>>> What are these? All IDs should be incremental, decimal and start from 0.
> >>>>
> >>>> Register offset, we use the same method in NPCM7xx. please refer
> >>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> >>>>
> >>>> and the driver asserts the reset according to the reset include definitions
> >>>
> >>> So if they're easy to look up the values, you could do without the
> >>> definitions? Cfr. the interrupts properties in .dtsi files, where we
> >>> typically just use the hardcoded numbers.
> >>>
> >>> If you do decide to keep them, a comment explaining their origins
> >>> would be useful.
Will do it in the next patch.
> >>>
> >>>>>> +
> >>>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> >>>>>> +#define NPCM8XX_RESET_GDMA0          3
> >>>>>
> >>>>> IDs start from 0 and do not have holes.
> >>>>
> >>>> This represents the reset BIT in the reset register.
> >>>
> >>> Likewise, I think it's a good idea to document that in a comment, cfr.
> >>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
> >>
> >> Renesas is also doing it not correct (just like many others). The
> >> bindings are not for register bits or offsets. Such data can be DTS but
> >> not part of bindings.
> >
> > I think you are taking a too-extremist standpoint.
> > The two extremes are:
> >   1. Numbers correspond to hardware numbers, and are easy to look up
> >     in the hardware documentation (e.g. GIC SPI interrupt numbers).
> >      => Use the hardcoded numbers in DTS.
>
> And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
> They go to DTS only.
>
> >   2. Numbers do not correspond to hardware numbers, so we had to
> >      invent our own definitions and numbers, usually loosely
> >      based on some table in the hardware documentation.
> >      The driver will have to look up the numbers in a data
> >      structure, to know how to program the hardware.
> >      The numbers become part of the DT ABI, and cannot be changed
> >      (header file is append-only).
> >      => Use the binding definitions in DTS.
>
> Correct.
>
> However this patch is some mixture of both approaches.
>
> The same pointed by Arnd:
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>
> > We are taking the middle ground: there is a one-to-one relation between
> > numbers and hardware numbers that can be looked up in or derived from
> > the hardware documentation, but the conversion is non-trivial (for the
> > casual human reviewer), or the documentation refers to names instead
> > of numbers in most sections (e.g. named power domains). Then why not
> > let the numbers match some feature in the hardware (e.g. register
> > offset or register bit)?
>
> Because you are embedding the device programming model into the
> bindings. It's the same as having properties:
> "vendor,value-for-register-xxx"
>
> We do not create bindings to describe programming model but hardware.
> Using the values from programming model is fragile and ties the bindings
> to that one programming model. Programming model can change, e.g. by
> mistake, but bindings should stay independent.
>
> >
> >> Imagine now you made mistake in this register
> >> offset and hardware uses slightly different value. What now? Change
> >> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.
> >
> > I see no difference here with using the wrong interrupt number in an
> > interrupts property in DTS.  What do we do in that case? Fix the DTS.
>
> Yes, fix the DTS. DTS are not the bindings. You can fix the DTS. You
> cannot fix the bindings because you affect both driver and DTS.
>
> >
> > BTW, are you aware of any driver that transforms interrupt numbers
> > obtained from DTS, because the DTS used the wrong number?
>
> Again, what do the DTS has here at all? The interrupt numbers are also
> not included in the bindings, so what does it prove?
>
> Best regards,
> Krzysztof

Best regards,

Tomer

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 16:03, Tomer Maimon wrote:
> Hi Krzysztof,
> 
> Thanks for your comments.

Please stop replying in HTML. It's not the format of emails used in the
Linux. It makes very difficult to read your replies.

> 
> 
> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org <mailto:krzysztof.kozlowski@linaro.org>>
> wrote:
> 
>     On 22/05/2022 17:50, Tomer Maimon wrote:
>     > Add binding document and device tree binding
>     > constants for Nuvoton BMC NPCM8XX reset controller.
>     >
>     > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com
>     <mailto:tmaimon77@gmail.com>>
>     > ---
>     >  .../bindings/reset/nuvoton,npcm-reset.txt     |  17 ++-
>     >  .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124
>     ++++++++++++++++++
>     >  2 files changed, 139 insertions(+), 2 deletions(-)
>     >  create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     >
>     > diff --git
>     a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     > index cb1613092ee7..b7eb8615b68b 100644
>     > --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     > @@ -1,14 +1,15 @@
>     >  Nuvoton NPCM Reset controller
>     > 
>     >  Required properties:
>     > -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
>     > +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC.
>     > +               "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC.
>     >  - reg : specifies physical base address and size of the register.
>     >  - #reset-cells: must be set to 2
>     >  - syscon: a phandle to access GCR registers.
>     > 
>     >  Optional property:
>     >  - nuvoton,sw-reset-number - Contains the software reset number to
>     restart the SoC.
>     > -  NPCM7xx contain four software reset that represent numbers 1 to 4.
>     > +  NPCM7xx and NPCM8xx contain four software reset that represent
>     numbers 1 to 4.
>     > 
>     >    If 'nuvoton,sw-reset-number' is not specified software reset is
>     disabled.
>     > 
>     > @@ -32,3 +33,15 @@ example:
>     >          };
>     > 
>     >  The index could be found in
>     <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
>     > +
>     > +Specifying reset lines connected to IP NPCM8XX modules
>     > +======================================================
> 
> we prefer to use the same explanation as the NPCM7XX reset explanation
> in the reset binding document.

??

> 
>     No need to document consumers. Just mention the header.

What explanation? Consumers are trivial. Once you convert it to DT
schema there should be no such code at all.

> 
>     > +example:
>     > +
>     > +        spi0: spi@..... {
>     > +                ...
>     > +                resets = <&rstc NPCM8XX_RESET_IPSRST2
>     NPCM8XX_RESET_PSPI1>;
>     > +                ...
>     > +        };
>     > +
>     > +The index could be found in
>     <dt-bindings/reset/nuvoton,npcm8xx-reset.h>.
>     > diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     > new file mode 100644
>     > index 000000000000..4b832a0fd1dd
>     > --- /dev/null
>     > +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     > @@ -0,0 +1,124 @@
>     > +/* SPDX-License-Identifier: GPL-2.0 */
> 
>     Dual license.
> 
> O.K. 
> 
> 
>     > +// Copyright (c) 2022 Nuvoton Technology corporation.
>     > +
>     > +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>     > +#define _DT_BINDINGS_NPCM8XX_RESET_H
>     > +
>     > +#define NPCM8XX_RESET_IPSRST1                0x20
>     > +#define NPCM8XX_RESET_IPSRST2                0x24
>     > +#define NPCM8XX_RESET_IPSRST3                0x34
>     > +#define NPCM8XX_RESET_IPSRST4                0x74
> 
>     What are these? All IDs should be incremental, decimal and start from 0.
> 
> Register offset, we use the same method in NPCM7xx. please refer
> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> <https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h>
> 
> and the driver asserts the reset according to the reset include definitions 

Register offsets, a device programming model, are not part of bindings.
 Bindings should be independent of programming model, so only IDs are
allowed.

Why did you add register offsets to bindings at the first place?

> 
> 
>     > +
>     > +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>     > +#define NPCM8XX_RESET_GDMA0          3
> 
>     IDs start from 0 and do not have holes.
> 
> This represents the reset BIT in the reset register. 

Again, not programming model in the bindings. No bits, not register
values, no register offsets.


Best regards,
Krzysztof

Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

[Krzysztof Kozlowski]

On 23/05/2022 16:03, Tomer Maimon wrote:
> Hi Krzysztof,
> 
> Thanks for your comments.

Please stop replying in HTML. It's not the format of emails used in the
Linux. It makes very difficult to read your replies.

> 
> 
> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org <mailto:krzysztof.kozlowski@linaro.org>>
> wrote:
> 
>     On 22/05/2022 17:50, Tomer Maimon wrote:
>     > Add binding document and device tree binding
>     > constants for Nuvoton BMC NPCM8XX reset controller.
>     >
>     > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com
>     <mailto:tmaimon77@gmail.com>>
>     > ---
>     >  .../bindings/reset/nuvoton,npcm-reset.txt     |  17 ++-
>     >  .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124
>     ++++++++++++++++++
>     >  2 files changed, 139 insertions(+), 2 deletions(-)
>     >  create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     >
>     > diff --git
>     a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     > index cb1613092ee7..b7eb8615b68b 100644
>     > --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>     > @@ -1,14 +1,15 @@
>     >  Nuvoton NPCM Reset controller
>     > 
>     >  Required properties:
>     > -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
>     > +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC.
>     > +               "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC.
>     >  - reg : specifies physical base address and size of the register.
>     >  - #reset-cells: must be set to 2
>     >  - syscon: a phandle to access GCR registers.
>     > 
>     >  Optional property:
>     >  - nuvoton,sw-reset-number - Contains the software reset number to
>     restart the SoC.
>     > -  NPCM7xx contain four software reset that represent numbers 1 to 4.
>     > +  NPCM7xx and NPCM8xx contain four software reset that represent
>     numbers 1 to 4.
>     > 
>     >    If 'nuvoton,sw-reset-number' is not specified software reset is
>     disabled.
>     > 
>     > @@ -32,3 +33,15 @@ example:
>     >          };
>     > 
>     >  The index could be found in
>     <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
>     > +
>     > +Specifying reset lines connected to IP NPCM8XX modules
>     > +======================================================
> 
> we prefer to use the same explanation as the NPCM7XX reset explanation
> in the reset binding document.

??

> 
>     No need to document consumers. Just mention the header.

What explanation? Consumers are trivial. Once you convert it to DT
schema there should be no such code at all.

> 
>     > +example:
>     > +
>     > +        spi0: spi@..... {
>     > +                ...
>     > +                resets = <&rstc NPCM8XX_RESET_IPSRST2
>     NPCM8XX_RESET_PSPI1>;
>     > +                ...
>     > +        };
>     > +
>     > +The index could be found in
>     <dt-bindings/reset/nuvoton,npcm8xx-reset.h>.
>     > diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     > new file mode 100644
>     > index 000000000000..4b832a0fd1dd
>     > --- /dev/null
>     > +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
>     > @@ -0,0 +1,124 @@
>     > +/* SPDX-License-Identifier: GPL-2.0 */
> 
>     Dual license.
> 
> O.K. 
> 
> 
>     > +// Copyright (c) 2022 Nuvoton Technology corporation.
>     > +
>     > +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
>     > +#define _DT_BINDINGS_NPCM8XX_RESET_H
>     > +
>     > +#define NPCM8XX_RESET_IPSRST1                0x20
>     > +#define NPCM8XX_RESET_IPSRST2                0x24
>     > +#define NPCM8XX_RESET_IPSRST3                0x34
>     > +#define NPCM8XX_RESET_IPSRST4                0x74
> 
>     What are these? All IDs should be incremental, decimal and start from 0.
> 
> Register offset, we use the same method in NPCM7xx. please refer
> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> <https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h>
> 
> and the driver asserts the reset according to the reset include definitions 

Register offsets, a device programming model, are not part of bindings.
 Bindings should be independent of programming model, so only IDs are
allowed.

Why did you add register offsets to bindings at the first place?

> 
> 
>     > +
>     > +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
>     > +#define NPCM8XX_RESET_GDMA0          3
> 
>     IDs start from 0 and do not have holes.
> 
> This represents the reset BIT in the reset register. 

Again, not programming model in the bindings. No bits, not register
values, no register offsets.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v1 12/19] reset: npcm: Add NPCM8XX support

[Tomer Maimon]

Updated the NPCM reset driver to add
support for Nuvoton BMC NPCM8XX SoC.
As part of adding NPCM8XX support
- Add NPCM8XX specific compatible string.
- Add NPCM8XX USB reset.
- Some of the Reset Id and number of resets are
  different from NPCM7XX.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/reset/reset-npcm.c | 157 ++++++++++++++++++++++++++++++-------
 1 file changed, 130 insertions(+), 27 deletions(-)

diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
index 0c963b21eddc..8d82a45dd580 100644
--- a/drivers/reset/reset-npcm.c
+++ b/drivers/reset/reset-npcm.c
@@ -17,13 +17,20 @@
 
 /* NPCM7xx GCR registers */
 #define NPCM_MDLR_OFFSET	0x7C
-#define NPCM_MDLR_USBD0		BIT(9)
-#define NPCM_MDLR_USBD1		BIT(8)
-#define NPCM_MDLR_USBD2_4	BIT(21)
-#define NPCM_MDLR_USBD5_9	BIT(22)
+#define NPCM7XX_MDLR_USBD0	BIT(9)
+#define NPCM7XX_MDLR_USBD1	BIT(8)
+#define NPCM7XX_MDLR_USBD2_4	BIT(21)
+#define NPCM7XX_MDLR_USBD5_9	BIT(22)
+
+/* NPCM8xx MDLR bits */
+#define NPCM8XX_MDLR_USBD0_3	BIT(9)
+#define NPCM8XX_MDLR_USBD4_7	BIT(22)
+#define NPCM8XX_MDLR_USBD8	BIT(24)
+#define NPCM8XX_MDLR_USBD9	BIT(21)
 
 #define NPCM_USB1PHYCTL_OFFSET	0x140
 #define NPCM_USB2PHYCTL_OFFSET	0x144
+#define NPCM_USB3PHYCTL_OFFSET	0x148
 #define NPCM_USBXPHYCTL_RS	BIT(28)
 
 /* NPCM7xx Reset registers */
@@ -49,12 +56,17 @@
 #define NPCM_IPSRST3_USBPHY1	BIT(24)
 #define NPCM_IPSRST3_USBPHY2	BIT(25)
 
+#define NPCM_IPSRST4		0x74
+#define NPCM_IPSRST4_USBPHY3	BIT(25)
+#define NPCM_IPSRST4_USB_HOST2	BIT(31)
+
 #define NPCM_RC_RESETS_PER_REG	32
 #define NPCM_MASK_RESETS	GENMASK(4, 0)
 
 struct npcm_rc_data {
 	struct reset_controller_dev rcdev;
 	struct notifier_block restart_nb;
+	struct regmap *gcr_regmap;
 	u32 sw_reset_number;
 	void __iomem *base;
 	spinlock_t lock;
@@ -124,7 +136,7 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
 
 	offset = reset_spec->args[0];
 	if (offset != NPCM_IPSRST1 && offset != NPCM_IPSRST2 &&
-	    offset != NPCM_IPSRST3) {
+	    offset != NPCM_IPSRST3 && offset != NPCM_IPSRST4) {
 		dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
 		return -EINVAL;
 	}
@@ -139,39 +151,28 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
 
 static const struct of_device_id npcm_rc_match[] = {
 	{ .compatible = "nuvoton,npcm750-reset"},
+	{ .compatible = "nuvoton,npcm845-reset"},
 	{ }
 };
 
-/*
- *  The following procedure should be observed in USB PHY, USB device and
- *  USB host initialization at BMC boot
- */
-static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
+static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
 {
 	u32 mdlr, iprst1, iprst2, iprst3;
-	struct device *dev = &pdev->dev;
-	struct regmap *gcr_regmap;
 	u32 ipsrst1_bits = 0;
 	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
 	u32 ipsrst3_bits = 0;
 
-	gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
-	if (IS_ERR(gcr_regmap)) {
-		dev_err(&pdev->dev, "Failed to find gcr syscon");
-		return PTR_ERR(gcr_regmap);
-	}
-
 	/* checking which USB device is enabled */
-	regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
-	if (!(mdlr & NPCM_MDLR_USBD0))
+	regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
+	if (!(mdlr & NPCM7XX_MDLR_USBD0))
 		ipsrst3_bits |= NPCM_IPSRST3_USBD0;
-	if (!(mdlr & NPCM_MDLR_USBD1))
+	if (!(mdlr & NPCM7XX_MDLR_USBD1))
 		ipsrst1_bits |= NPCM_IPSRST1_USBD1;
-	if (!(mdlr & NPCM_MDLR_USBD2_4))
+	if (!(mdlr & NPCM7XX_MDLR_USBD2_4))
 		ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
 				 NPCM_IPSRST1_USBD3 |
 				 NPCM_IPSRST1_USBD4);
-	if (!(mdlr & NPCM_MDLR_USBD0)) {
+	if (!(mdlr & NPCM7XX_MDLR_USBD0)) {
 		ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
 				 NPCM_IPSRST1_USBD6);
 		ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
@@ -194,9 +195,9 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
 	writel(iprst3, rc->base + NPCM_IPSRST3);
 
 	/* clear USB PHY RS bit */
-	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
 			   NPCM_USBXPHYCTL_RS, 0);
-	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
 			   NPCM_USBXPHYCTL_RS, 0);
 
 	/* deassert reset USB PHY */
@@ -206,9 +207,9 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
 	udelay(50);
 
 	/* set USB PHY RS bit */
-	regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
 			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
-	regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
 			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
 
 	/* deassert reset USB devices*/
@@ -219,6 +220,108 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
 	writel(iprst1, rc->base + NPCM_IPSRST1);
 	writel(iprst2, rc->base + NPCM_IPSRST2);
 	writel(iprst3, rc->base + NPCM_IPSRST3);
+}
+
+static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
+{
+	u32 mdlr, iprst1, iprst2, iprst3, iprst4;
+	u32 ipsrst1_bits = 0;
+	u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
+	u32 ipsrst3_bits = 0;
+	u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3;
+
+	/* checking which USB device is enabled */
+	regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
+	if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) {
+		ipsrst3_bits |= NPCM_IPSRST3_USBD0;
+		ipsrst1_bits |= (NPCM_IPSRST1_USBD1 |
+				 NPCM_IPSRST1_USBD2 |
+				 NPCM_IPSRST1_USBD3);
+	}
+	if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) {
+		ipsrst1_bits |= (NPCM_IPSRST1_USBD4 |
+				 NPCM_IPSRST1_USBD5 |
+				 NPCM_IPSRST1_USBD6);
+		ipsrst3_bits |= NPCM_IPSRST3_USBD7;
+	}
+
+	if (!(mdlr & NPCM8XX_MDLR_USBD8))
+		ipsrst3_bits |= NPCM_IPSRST3_USBD8;
+	if (!(mdlr & NPCM8XX_MDLR_USBD9))
+		ipsrst3_bits |= NPCM_IPSRST3_USBD9;
+
+	/* assert reset USB PHY and USB devices */
+	iprst1 = readl(rc->base + NPCM_IPSRST1);
+	iprst2 = readl(rc->base + NPCM_IPSRST2);
+	iprst3 = readl(rc->base + NPCM_IPSRST3);
+	iprst4 = readl(rc->base + NPCM_IPSRST4);
+
+	iprst1 |= ipsrst1_bits;
+	iprst2 |= ipsrst2_bits;
+	iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
+		   NPCM_IPSRST3_USBPHY2);
+	iprst2 |= ipsrst4_bits;
+
+	writel(iprst1, rc->base + NPCM_IPSRST1);
+	writel(iprst2, rc->base + NPCM_IPSRST2);
+	writel(iprst3, rc->base + NPCM_IPSRST3);
+	writel(iprst4, rc->base + NPCM_IPSRST4);
+
+	/* clear USB PHY RS bit */
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, 0);
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, 0);
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, 0);
+
+	/* deassert reset USB PHY */
+	iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
+	writel(iprst3, rc->base + NPCM_IPSRST3);
+	iprst4 &= ~NPCM_IPSRST4_USBPHY3;
+	writel(iprst4, rc->base + NPCM_IPSRST4);
+
+	/* set USB PHY RS bit */
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+	regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
+			   NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+
+	/* deassert reset USB devices*/
+	iprst1 &= ~ipsrst1_bits;
+	iprst2 &= ~ipsrst2_bits;
+	iprst3 &= ~ipsrst3_bits;
+	iprst4 &= ~ipsrst4_bits;
+
+	writel(iprst1, rc->base + NPCM_IPSRST1);
+	writel(iprst2, rc->base + NPCM_IPSRST2);
+	writel(iprst3, rc->base + NPCM_IPSRST3);
+	writel(iprst4, rc->base + NPCM_IPSRST4);
+}
+
+/*
+ *  The following procedure should be observed in USB PHY, USB device and
+ *  USB host initialization at BMC boot
+ */
+static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
+
+	rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
+	if (IS_ERR(rc->gcr_regmap)) {
+		dev_err(&pdev->dev, "Failed to find gcr syscon");
+		return PTR_ERR(rc->gcr_regmap);
+	}
+
+	if (of_device_is_compatible(np, "nuvoton,npcm750-reset"))
+		npcm_usb_reset_npcm7xx(rc);
+	else if (of_device_is_compatible(np, "nuvoton,npcm845-reset"))
+		npcm_usb_reset_npcm8xx(rc);
+	else
+		return -ENODEV;
 
 	return 0;
 }
-- 
2.33.0

Re: [PATCH v1 12/19] reset: npcm: Add NPCM8XX support

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:

>  static const struct of_device_id npcm_rc_match[] = {
>         { .compatible = "nuvoton,npcm750-reset"},
> +       { .compatible = "nuvoton,npcm845-reset"},
>         { }
>  };
> +/*
> + *  The following procedure should be observed in USB PHY, USB device and
> + *  USB host initialization at BMC boot
> + */
> +static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct device *dev = &pdev->dev;
> +
> +       rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
> +       if (IS_ERR(rc->gcr_regmap)) {
> +               dev_err(&pdev->dev, "Failed to find gcr syscon");
> +               return PTR_ERR(rc->gcr_regmap);
> +       }
> +
> +       if (of_device_is_compatible(np, "nuvoton,npcm750-reset"))
> +               npcm_usb_reset_npcm7xx(rc);
> +       else if (of_device_is_compatible(np, "nuvoton,npcm845-reset"))
> +               npcm_usb_reset_npcm8xx(rc);
> +       else
> +               return -ENODEV;
>

In place of the string comparison in of_device_is_compatible(), maybe just use
the .data field of the of_device_id structure to point to the actual
reset function.

Alternatively, register two separate platform_driver instances here and
use separate probe functions that do the soc specific bits and call into
shared functions for the bits that are the same.

       Arnd

Re: [PATCH v1 12/19] reset: npcm: Add NPCM8XX support

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:

>  static const struct of_device_id npcm_rc_match[] = {
>         { .compatible = "nuvoton,npcm750-reset"},
> +       { .compatible = "nuvoton,npcm845-reset"},
>         { }
>  };
> +/*
> + *  The following procedure should be observed in USB PHY, USB device and
> + *  USB host initialization at BMC boot
> + */
> +static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct device *dev = &pdev->dev;
> +
> +       rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
> +       if (IS_ERR(rc->gcr_regmap)) {
> +               dev_err(&pdev->dev, "Failed to find gcr syscon");
> +               return PTR_ERR(rc->gcr_regmap);
> +       }
> +
> +       if (of_device_is_compatible(np, "nuvoton,npcm750-reset"))
> +               npcm_usb_reset_npcm7xx(rc);
> +       else if (of_device_is_compatible(np, "nuvoton,npcm845-reset"))
> +               npcm_usb_reset_npcm8xx(rc);
> +       else
> +               return -ENODEV;
>

In place of the string comparison in of_device_is_compatible(), maybe just use
the .data field of the of_device_id structure to point to the actual
reset function.

Alternatively, register two separate platform_driver instances here and
use separate probe functions that do the soc specific bits and call into
shared functions for the bits that are the same.

       Arnd

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[PATCH v1 13/19] dt-bindings: arm: npcm: Add maintainer

[Tomer Maimon]

Add Tomer Maimon to the maintainers list.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 Documentation/devicetree/bindings/arm/npcm/npcm.yaml        | 1 +
 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
index 95e51378089c..ea9c3103761d 100644
--- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
@@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings
 
 maintainers:
   - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+  - Tomer Maimon <tmaimon77@gmail.com>
 
 properties:
   $nodename:
diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
index fcb211add7d3..aad7c85e787f 100644
--- a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
@@ -8,6 +8,7 @@ title: Global Control Registers block in Nuvoton SoCs
 
 maintainers:
   - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+  - Tomer Maimon <tmaimon77@gmail.com>
 
 description:
   The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
-- 
2.33.0

Re: [PATCH v1 13/19] dt-bindings: arm: npcm: Add maintainer

[Rob Herring]

On Sun, 22 May 2022 18:50:40 +0300, Tomer Maimon wrote:
> Add Tomer Maimon to the maintainers list.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/npcm/npcm.yaml        | 1 +
>  Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml | 1 +
>  2 files changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v1 13/19] dt-bindings: arm: npcm: Add maintainer

[Rob Herring]

On Sun, 22 May 2022 18:50:40 +0300, Tomer Maimon wrote:
> Add Tomer Maimon to the maintainers list.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/npcm/npcm.yaml        | 1 +
>  Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml | 1 +
>  2 files changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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[PATCH v1 14/19] dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string

[Tomer Maimon]

Add a compatible string for Nuvoton BMC NPCM845 SoC and a board
specific device tree for the NPCM845 (Arbel) evaluation board.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 Documentation/devicetree/bindings/arm/npcm/npcm.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
index ea9c3103761d..43409e5721d5 100644
--- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
@@ -27,4 +27,10 @@ properties:
               - nuvoton,npcm750-evb         # NPCM750 evaluation board
           - const: nuvoton,npcm750
 
+      - description: NPCM845 based boards
+        items:
+          - enum:
+              - nuvoton,npcm845-evb         # NPCM845 evaluation board
+          - const: nuvoton,npcm845
+
 additionalProperties: true
-- 
2.33.0

Re: [PATCH v1 14/19] dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 SoC and a board
> specific device tree for the NPCM845 (Arbel) evaluation board.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 14/19] dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845 SoC and a board
> specific device tree for the NPCM845 (Arbel) evaluation board.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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[PATCH v1 15/19] dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string

[Tomer Maimon]

Add a compatible string for Nuvoton BMC NPCM845
global control registers (GCR).

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
index aad7c85e787f..94e72f25b331 100644
--- a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
@@ -21,6 +21,7 @@ properties:
       - enum:
           - nuvoton,wpcm450-gcr
           - nuvoton,npcm750-gcr
+          - nuvoton,npcm845-gcr
       - const: syscon
       - const: simple-mfd
 
-- 
2.33.0

Re: [PATCH v1 15/19] dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845
> global control registers (GCR).
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 15/19] dt-bindings: arm: npcm: Add nuvoton, npcm845 GCR compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845
> global control registers (GCR).
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH v1 15/19] dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845
> global control registers (GCR).
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 15/19] dt-bindings: arm: npcm: Add nuvoton, npcm845 GCR compatible string

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add a compatible string for Nuvoton BMC NPCM845
> global control registers (GCR).
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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[PATCH v1 16/19] arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC

[Tomer Maimon]

This adds support for the Nuvoton NPCM8XX Board Management
controller (BMC) SoC family.

The NPCM8XX based quad-core Cortex-A35 ARMv8 architecture.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 MAINTAINERS                  |  3 +++
 arch/arm64/Kconfig.platforms | 11 +++++++++++
 2 files changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d6d879cb0afd..bb81dda94372 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2431,9 +2431,12 @@ F:	Documentation/devicetree/bindings/*/*npcm*
 F:	Documentation/devicetree/bindings/arm/npcm/*
 F:	arch/arm/boot/dts/nuvoton-npcm*
 F:	arch/arm/mach-npcm/
+F:	arch/arm64/boot/dts/nuvoton/
 F:	drivers/*/*npcm*
 F:	drivers/*/*/*npcm*
 F:	include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
+F:	include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
+F:	include/dt-bindings/clock/nuvoton,npcm8xx-reset.h
 
 ARM/NUVOTON WPCM450 ARCHITECTURE
 M:	Jonathan Neuschäfer <j.neuschaefer@gmx.net>
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 30b123cde02c..1767027ee9e8 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -203,6 +203,17 @@ config ARCH_MXC
 	  This enables support for the ARMv8 based SoCs in the
 	  NXP i.MX family.
 
+config ARCH_NPCM
+	bool "Nuvoton NPCM Architecture"
+	select PINCTRL
+	select GPIOLIB
+	select NPCM7XX_TIMER
+	select RESET_CONTROLLER
+	select MFD_SYSCON
+	help
+	  General support for NPCM8xx BMC (Arbel).
+	  Nuvoton NPCM8xx BMC based on the Cortex A35.
+
 config ARCH_QCOM
 	bool "Qualcomm Platforms"
 	select GPIOLIB
-- 
2.33.0

[PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Tomer Maimon]

This adds initial device tree support for the
Nuvoton NPCM845 Board Management controller (BMC) SoC family.

The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
have various peripheral IPs.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm64/boot/dts/Makefile                  |   1 +
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 197 ++++++++++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  77 +++++++
 3 files changed, 275 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 1ba04e31a438..7b107fa7414b 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ subdir-y += lg
 subdir-y += marvell
 subdir-y += mediatek
 subdir-y += microchip
+subdir-y += nuvoton
 subdir-y += nvidia
 subdir-y += qcom
 subdir-y += realtek
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
new file mode 100644
index 000000000000..19c672ecfee7
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	/* external reference clock */
+	clk_refclk: clk-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "refclk";
+	};
+
+	/* external reference clock for cpu. float in normal operation */
+	clk_sysbypck: clk-sysbypck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+		clock-output-names = "sysbypck";
+	};
+
+	/* external reference clock for MC. float in normal operation */
+	clk_mcbypck: clk-mcbypck {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1050000000>;
+		clock-output-names = "mcbypck";
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		gcr: gcr@f0800000 {
+			compatible = "nuvoton,npcm845-gcr", "syscon",
+				"simple-mfd";
+			reg = <0x0 0xf0800000 0x0 0x1000>;
+		};
+
+		gic: interrupt-controller@dfff9000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xdfff9000 0x0 0x1000>,
+			      <0x0 0xdfffa000 0x0 0x2000>,
+			      <0x0 0xdfffc000 0x0 0x2000>,
+			      <0x0 0xdfffe000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#address-cells = <0>;
+			ppi-partitions {
+				ppi_cluster0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+				};
+			};
+		};
+	};
+
+	ahb {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		rstc: rstc@f0801000 {
+			compatible = "nuvoton,npcm845-reset";
+			reg = <0x0 0xf0801000 0x0 0x78>;
+			#reset-cells = <2>;
+			syscon = <&gcr>;
+		};
+
+		clk: clock-controller@f0801000 {
+			compatible = "nuvoton,npcm845-clk";
+			#clock-cells = <1>;
+			reg = <0x0 0xf0801000 0x0 0x1000>;
+			clock-names = "refclk", "sysbypck", "mcbypck";
+			clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			interrupt-parent = <&gic>;
+			ranges = <0x0 0x0 0xf0000000 0x00300000>,
+				<0xfff00000 0x0 0xfff00000 0x00016000>;
+
+			timer0: timer@8000 {
+				compatible = "nuvoton,npcm845-timer";
+				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x8000 0x1C>;
+				clocks	= <&clk_refclk>;
+				clock-names = "refclk";
+			};
+
+			serial0: serial@0 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x0 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			serial1: serial@1000 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x1000 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			serial2: serial@2000 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x2000 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			serial3: serial@3000 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x3000 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			serial4: serial@4000 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x4000 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			serial5: serial@5000 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x5000 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			serial6: serial@6000 {
+				compatible = "nuvoton,npcm845-uart";
+				reg = <0x6000 0x1000>;
+				clocks = <&clk NPCM8XX_CLK_UART>;
+				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				status = "disabled";
+			};
+
+			watchdog0: watchdog@801c {
+				compatible = "nuvoton,npcm845-wdt";
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x801c 0x4>;
+				status = "disabled";
+				clocks = <&clk_refclk>;
+				syscon = <&gcr>;
+			};
+
+			watchdog1: watchdog@901c {
+				compatible = "nuvoton,npcm845-wdt";
+				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x901c 0x4>;
+				status = "disabled";
+				clocks = <&clk_refclk>;
+				syscon = <&gcr>;
+			};
+
+			watchdog2: watchdog@a01c {
+				compatible = "nuvoton,npcm845-wdt";
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0xa01c 0x4>;
+				status = "disabled";
+				clocks = <&clk_refclk>;
+				syscon = <&gcr>;
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
new file mode 100644
index 000000000000..900cee112251
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+#include "nuvoton-common-npcm8xx.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			clocks = <&clk NPCM8XX_CLK_CPU>;
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			clocks = <&clk NPCM8XX_CLK_CPU>;
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			clocks = <&clk NPCM8XX_CLK_CPU>;
+			reg = <0x0 0x2>;
+			next-level-cache = <&l2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			clocks = <&clk NPCM8XX_CLK_CPU>;
+			reg = <0x0 0x3>;
+			next-level-cache = <&l2>;
+			enable-method = "psci";
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a35-pmu";
+		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible      = "arm,psci-1.0";
+		method          = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.33.0

Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> This adds initial device tree support for the
> Nuvoton NPCM845 Board Management controller (BMC) SoC family.

Thank you for your patch. There is something to discuss/improve.

> 
> The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
> have various peripheral IPs.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 197 ++++++++++++++++++
>  .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  77 +++++++
>  3 files changed, 275 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 1ba04e31a438..7b107fa7414b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -19,6 +19,7 @@ subdir-y += lg
>  subdir-y += marvell
>  subdir-y += mediatek
>  subdir-y += microchip
> +subdir-y += nuvoton
>  subdir-y += nvidia
>  subdir-y += qcom
>  subdir-y += realtek
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> new file mode 100644
> index 000000000000..19c672ecfee7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
> +
> +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;
> +
> +	/* external reference clock */
> +	clk_refclk: clk-refclk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>

This is not a property of a SoC, but board.

> +		clock-output-names = "refclk";
> +	};
> +
> +	/* external reference clock for cpu. float in normal operation */
> +	clk_sysbypck: clk-sysbypck {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1000000000>;

This is not a property of a SoC, but board.


> +		clock-output-names = "sysbypck";
> +	};
> +
> +	/* external reference clock for MC. float in normal operation */
> +	clk_mcbypck: clk-mcbypck {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1050000000>;

This is not a property of a SoC, but board.

> +		clock-output-names = "mcbypck";
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		gcr: gcr@f0800000 {

Generic node names. I guess it is system-controller?

> +			compatible = "nuvoton,npcm845-gcr", "syscon",
> +				"simple-mfd";
> +			reg = <0x0 0xf0800000 0x0 0x1000>;
> +		};
> +
> +		gic: interrupt-controller@dfff9000 {
> +			compatible = "arm,gic-400";
> +			reg = <0x0 0xdfff9000 0x0 0x1000>,
> +			      <0x0 0xdfffa000 0x0 0x2000>,
> +			      <0x0 0xdfffc000 0x0 0x2000>,
> +			      <0x0 0xdfffe000 0x0 0x2000>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			ppi-partitions {
> +				ppi_cluster0: interrupt-partition-0 {
> +					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> +				};
> +			};
> +		};
> +	};
> +
> +	ahb {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		rstc: rstc@f0801000 {

Generic node names.

> +			compatible = "nuvoton,npcm845-reset";
> +			reg = <0x0 0xf0801000 0x0 0x78>;
> +			#reset-cells = <2>;
> +			syscon = <&gcr>;
> +		};
> +
> +		clk: clock-controller@f0801000 {
> +			compatible = "nuvoton,npcm845-clk";
> +			#clock-cells = <1>;
> +			reg = <0x0 0xf0801000 0x0 0x1000>;
> +			clock-names = "refclk", "sysbypck", "mcbypck";
> +			clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
> +		};
> +
> +		apb {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "simple-bus";
> +			interrupt-parent = <&gic>;
> +			ranges = <0x0 0x0 0xf0000000 0x00300000>,
> +				<0xfff00000 0x0 0xfff00000 0x00016000>;
> +
> +			timer0: timer@8000 {
> +				compatible = "nuvoton,npcm845-timer";
> +				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x8000 0x1C>;
> +				clocks	= <&clk_refclk>;
> +				clock-names = "refclk";
> +			};
> +
> +			serial0: serial@0 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x0 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial1: serial@1000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x1000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial2: serial@2000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x2000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial3: serial@3000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x3000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial4: serial@4000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x4000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial5: serial@5000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x5000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial6: serial@6000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x6000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			watchdog0: watchdog@801c {
> +				compatible = "nuvoton,npcm845-wdt";
> +				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x801c 0x4>;
> +				status = "disabled";
> +				clocks = <&clk_refclk>;
> +				syscon = <&gcr>;
> +			};
> +
> +			watchdog1: watchdog@901c {
> +				compatible = "nuvoton,npcm845-wdt";
> +				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x901c 0x4>;
> +				status = "disabled";
> +				clocks = <&clk_refclk>;
> +				syscon = <&gcr>;
> +			};
> +
> +			watchdog2: watchdog@a01c {
> +				compatible = "nuvoton,npcm845-wdt";
> +				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0xa01c 0x4>;
> +				status = "disabled";
> +				clocks = <&clk_refclk>;
> +				syscon = <&gcr>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> new file mode 100644
> index 000000000000..900cee112251
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
> +
> +#include "nuvoton-common-npcm8xx.dtsi"
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;

You do not have gic here, so it's not correct. Do not reference nodes
outsides of the file.

> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x0>;

Why do you have two address cells? A bit more complicated and not
necessary, I think.

> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x1>;
> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x2>;
> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x3>;
> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";

Is this a real compatible? What bindings are you using here?

> +		};
> +	};
> +
> +	arm-pmu {
> +		compatible = "arm,cortex-a35-pmu";
> +		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +
> +	psci {
> +		compatible      = "arm,psci-1.0";
> +		method          = "smc";

Weird indentation.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};


Best regards,
Krzysztof

Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> This adds initial device tree support for the
> Nuvoton NPCM845 Board Management controller (BMC) SoC family.

Thank you for your patch. There is something to discuss/improve.

> 
> The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
> have various peripheral IPs.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 197 ++++++++++++++++++
>  .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  77 +++++++
>  3 files changed, 275 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 1ba04e31a438..7b107fa7414b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -19,6 +19,7 @@ subdir-y += lg
>  subdir-y += marvell
>  subdir-y += mediatek
>  subdir-y += microchip
> +subdir-y += nuvoton
>  subdir-y += nvidia
>  subdir-y += qcom
>  subdir-y += realtek
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> new file mode 100644
> index 000000000000..19c672ecfee7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
> +
> +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;
> +
> +	/* external reference clock */
> +	clk_refclk: clk-refclk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>

This is not a property of a SoC, but board.

> +		clock-output-names = "refclk";
> +	};
> +
> +	/* external reference clock for cpu. float in normal operation */
> +	clk_sysbypck: clk-sysbypck {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1000000000>;

This is not a property of a SoC, but board.


> +		clock-output-names = "sysbypck";
> +	};
> +
> +	/* external reference clock for MC. float in normal operation */
> +	clk_mcbypck: clk-mcbypck {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1050000000>;

This is not a property of a SoC, but board.

> +		clock-output-names = "mcbypck";
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		gcr: gcr@f0800000 {

Generic node names. I guess it is system-controller?

> +			compatible = "nuvoton,npcm845-gcr", "syscon",
> +				"simple-mfd";
> +			reg = <0x0 0xf0800000 0x0 0x1000>;
> +		};
> +
> +		gic: interrupt-controller@dfff9000 {
> +			compatible = "arm,gic-400";
> +			reg = <0x0 0xdfff9000 0x0 0x1000>,
> +			      <0x0 0xdfffa000 0x0 0x2000>,
> +			      <0x0 0xdfffc000 0x0 0x2000>,
> +			      <0x0 0xdfffe000 0x0 0x2000>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			ppi-partitions {
> +				ppi_cluster0: interrupt-partition-0 {
> +					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> +				};
> +			};
> +		};
> +	};
> +
> +	ahb {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		rstc: rstc@f0801000 {

Generic node names.

> +			compatible = "nuvoton,npcm845-reset";
> +			reg = <0x0 0xf0801000 0x0 0x78>;
> +			#reset-cells = <2>;
> +			syscon = <&gcr>;
> +		};
> +
> +		clk: clock-controller@f0801000 {
> +			compatible = "nuvoton,npcm845-clk";
> +			#clock-cells = <1>;
> +			reg = <0x0 0xf0801000 0x0 0x1000>;
> +			clock-names = "refclk", "sysbypck", "mcbypck";
> +			clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
> +		};
> +
> +		apb {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "simple-bus";
> +			interrupt-parent = <&gic>;
> +			ranges = <0x0 0x0 0xf0000000 0x00300000>,
> +				<0xfff00000 0x0 0xfff00000 0x00016000>;
> +
> +			timer0: timer@8000 {
> +				compatible = "nuvoton,npcm845-timer";
> +				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x8000 0x1C>;
> +				clocks	= <&clk_refclk>;
> +				clock-names = "refclk";
> +			};
> +
> +			serial0: serial@0 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x0 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial1: serial@1000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x1000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial2: serial@2000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x2000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial3: serial@3000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x3000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial4: serial@4000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x4000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial5: serial@5000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x5000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			serial6: serial@6000 {
> +				compatible = "nuvoton,npcm845-uart";
> +				reg = <0x6000 0x1000>;
> +				clocks = <&clk NPCM8XX_CLK_UART>;
> +				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-shift = <2>;
> +				status = "disabled";
> +			};
> +
> +			watchdog0: watchdog@801c {
> +				compatible = "nuvoton,npcm845-wdt";
> +				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x801c 0x4>;
> +				status = "disabled";
> +				clocks = <&clk_refclk>;
> +				syscon = <&gcr>;
> +			};
> +
> +			watchdog1: watchdog@901c {
> +				compatible = "nuvoton,npcm845-wdt";
> +				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x901c 0x4>;
> +				status = "disabled";
> +				clocks = <&clk_refclk>;
> +				syscon = <&gcr>;
> +			};
> +
> +			watchdog2: watchdog@a01c {
> +				compatible = "nuvoton,npcm845-wdt";
> +				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0xa01c 0x4>;
> +				status = "disabled";
> +				clocks = <&clk_refclk>;
> +				syscon = <&gcr>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> new file mode 100644
> index 000000000000..900cee112251
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
> +
> +#include "nuvoton-common-npcm8xx.dtsi"
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;

You do not have gic here, so it's not correct. Do not reference nodes
outsides of the file.

> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x0>;

Why do you have two address cells? A bit more complicated and not
necessary, I think.

> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x1>;
> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x2>;
> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			clocks = <&clk NPCM8XX_CLK_CPU>;
> +			reg = <0x0 0x3>;
> +			next-level-cache = <&l2>;
> +			enable-method = "psci";
> +		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";

Is this a real compatible? What bindings are you using here?

> +		};
> +	};
> +
> +	arm-pmu {
> +		compatible = "arm,cortex-a35-pmu";
> +		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +
> +	psci {
> +		compatible      = "arm,psci-1.0";
> +		method          = "smc";

Weird indentation.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};


Best regards,
Krzysztof

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Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Geert Uytterhoeven]

Hi Krzysztof,

On Mon, May 23, 2022 at 11:08 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 22/05/2022 17:50, Tomer Maimon wrote:
> > This adds initial device tree support for the
> > Nuvoton NPCM845 Board Management controller (BMC) SoC family.
>
> Thank you for your patch. There is something to discuss/improve.
>
> > The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
> > have various peripheral IPs.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

> > +             l2: l2-cache {
> > +                     compatible = "cache";
>
> Is this a real compatible? What bindings are you using here?

The compatible value and related properties are defined in the
Devicetree Specification, v0.4-rc1, Section 3.9 ("Multi-level and
Shared Cache Nodes (/cpus/cpu*/l?-cache)").

The properties are handled by
dtschema/schemas/cache-controller.yaml, but the latter seems to lack
any checking on the compatible value?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Geert Uytterhoeven]

Hi Krzysztof,

On Mon, May 23, 2022 at 11:08 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 22/05/2022 17:50, Tomer Maimon wrote:
> > This adds initial device tree support for the
> > Nuvoton NPCM845 Board Management controller (BMC) SoC family.
>
> Thank you for your patch. There is something to discuss/improve.
>
> > The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
> > have various peripheral IPs.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

> > +             l2: l2-cache {
> > +                     compatible = "cache";
>
> Is this a real compatible? What bindings are you using here?

The compatible value and related properties are defined in the
Devicetree Specification, v0.4-rc1, Section 3.9 ("Multi-level and
Shared Cache Nodes (/cpus/cpu*/l?-cache)").

The properties are handled by
dtschema/schemas/cache-controller.yaml, but the latter seems to lack
any checking on the compatible value?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Krzysztof Kozlowski]

On 23/05/2022 15:58, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Mon, May 23, 2022 at 11:08 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>> This adds initial device tree support for the
>>> Nuvoton NPCM845 Board Management controller (BMC) SoC family.
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
>>> have various peripheral IPs.
>>>
>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> 
>>> +             l2: l2-cache {
>>> +                     compatible = "cache";
>>
>> Is this a real compatible? What bindings are you using here?
> 
> The compatible value and related properties are defined in the
> Devicetree Specification, v0.4-rc1, Section 3.9 ("Multi-level and
> Shared Cache Nodes (/cpus/cpu*/l?-cache)").

Indeed, thanks!

> 
> The properties are handled by
> dtschema/schemas/cache-controller.yaml, but the latter seems to lack
> any checking on the compatible value?


Best regards,
Krzysztof

Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree

[Krzysztof Kozlowski]

On 23/05/2022 15:58, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Mon, May 23, 2022 at 11:08 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>> This adds initial device tree support for the
>>> Nuvoton NPCM845 Board Management controller (BMC) SoC family.
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
>>> have various peripheral IPs.
>>>
>>> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> 
>>> +             l2: l2-cache {
>>> +                     compatible = "cache";
>>
>> Is this a real compatible? What bindings are you using here?
> 
> The compatible value and related properties are defined in the
> Devicetree Specification, v0.4-rc1, Section 3.9 ("Multi-level and
> Shared Cache Nodes (/cpus/cpu*/l?-cache)").

Indeed, thanks!

> 
> The properties are handled by
> dtschema/schemas/cache-controller.yaml, but the latter seems to lack
> any checking on the compatible value?


Best regards,
Krzysztof

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[PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Tomer Maimon]

Add initial Nuvoton NPCM845 evaluation board device tree.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm64/boot/dts/nuvoton/Makefile          |  2 +
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 50 +++++++++++++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
 create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts

diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
new file mode 100644
index 000000000000..a99dab90472a
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
new file mode 100644
index 000000000000..d7a9a85f8075
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+/dts-v1/;
+#include "nuvoton-npcm845.dtsi"
+
+/ {
+	model = "Nuvoton npcm845 Development Board (Device Tree)";
+	compatible = "nuvoton,npcm845";
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	ahb {
+
+		apb {
+			serial0: serial@0 {
+				status = "okay";
+			};
+
+			serial1: serial@1000 {
+				status = "disabled";
+			};
+
+			serial2: serial@2000 {
+				status = "disabled";
+			};
+
+			serial3: serial@3000 {
+				status = "disabled";
+			};
+
+			watchdog1: watchdog@901c {
+				status = "okay";
+			};
+		};
+	};
+};
-- 
2.33.0

Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add initial Nuvoton NPCM845 evaluation board device tree.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  arch/arm64/boot/dts/nuvoton/Makefile          |  2 +
>  .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 50 +++++++++++++++++++
>  2 files changed, 52 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> 
> diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
> new file mode 100644
> index 000000000000..a99dab90472a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> new file mode 100644
> index 000000000000..d7a9a85f8075
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
> +
> +/dts-v1/;
> +#include "nuvoton-npcm845.dtsi"
> +
> +/ {
> +	model = "Nuvoton npcm845 Development Board (Device Tree)";

s/ (Device Tree)//

> +	compatible = "nuvoton,npcm845";

This does not match your bindings. Please test your DTS with `make
dtbs_check`.

> +
> +	aliases {
> +		serial0 = &serial0;
> +		serial1 = &serial1;
> +		serial2 = &serial2;
> +		serial3 = &serial3;
> +	};
> +
> +	chosen {
> +		stdout-path = &serial0;
> +	};
> +
> +	memory {
> +		reg = <0x0 0x0 0x0 0x40000000>;
> +	};
> +
> +	ahb {
> +

No need for blank line.

> +		apb {
> +			serial0: serial@0 {
> +				status = "okay";

No, override by labels. Here and in places below.

> +			};
> +
> +			serial1: serial@1000 {
> +				status = "disabled";
> +			};
> +
> +			serial2: serial@2000 {
> +				status = "disabled";
> +			};
> +
> +			serial3: serial@3000 {
> +				status = "disabled";
> +			};
> +
> +			watchdog1: watchdog@901c {
> +				status = "okay";
> +			};
> +		};
> +	};
> +};


Best regards,
Krzysztof

Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Krzysztof Kozlowski]

On 22/05/2022 17:50, Tomer Maimon wrote:
> Add initial Nuvoton NPCM845 evaluation board device tree.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  arch/arm64/boot/dts/nuvoton/Makefile          |  2 +
>  .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 50 +++++++++++++++++++
>  2 files changed, 52 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> 
> diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
> new file mode 100644
> index 000000000000..a99dab90472a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> new file mode 100644
> index 000000000000..d7a9a85f8075
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
> +
> +/dts-v1/;
> +#include "nuvoton-npcm845.dtsi"
> +
> +/ {
> +	model = "Nuvoton npcm845 Development Board (Device Tree)";

s/ (Device Tree)//

> +	compatible = "nuvoton,npcm845";

This does not match your bindings. Please test your DTS with `make
dtbs_check`.

> +
> +	aliases {
> +		serial0 = &serial0;
> +		serial1 = &serial1;
> +		serial2 = &serial2;
> +		serial3 = &serial3;
> +	};
> +
> +	chosen {
> +		stdout-path = &serial0;
> +	};
> +
> +	memory {
> +		reg = <0x0 0x0 0x0 0x40000000>;
> +	};
> +
> +	ahb {
> +

No need for blank line.

> +		apb {
> +			serial0: serial@0 {
> +				status = "okay";

No, override by labels. Here and in places below.

> +			};
> +
> +			serial1: serial@1000 {
> +				status = "disabled";
> +			};
> +
> +			serial2: serial@2000 {
> +				status = "disabled";
> +			};
> +
> +			serial3: serial@3000 {
> +				status = "disabled";
> +			};
> +
> +			watchdog1: watchdog@901c {
> +				status = "okay";
> +			};
> +		};
> +	};
> +};


Best regards,
Krzysztof

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Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> +/ {
> +       model = "Nuvoton npcm845 Development Board (Device Tree)";
> +       compatible = "nuvoton,npcm845";
> +
> +       aliases {
> +               serial0 = &serial0;
> +               serial1 = &serial1;
> +               serial2 = &serial2;
> +               serial3 = &serial3;
> +       };

> +               apb {
> +                       serial0: serial@0 {
> +                               status = "okay";
> +                       };
> +
> +                       serial1: serial@1000 {
> +                               status = "disabled";
> +                       };
> +
> +                       serial2: serial@2000 {
> +                               status = "disabled";
> +                       };
> +
> +                       serial3: serial@3000 {
> +                               status = "disabled";
> +                       };

Please drop the aliases for disabled uarts. It probably also makes
sense to have the status="disabled" properties in the .dtsi file and
only override them when you explicitly want to enable a uart for a
board.

       Arnd

Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> +/ {
> +       model = "Nuvoton npcm845 Development Board (Device Tree)";
> +       compatible = "nuvoton,npcm845";
> +
> +       aliases {
> +               serial0 = &serial0;
> +               serial1 = &serial1;
> +               serial2 = &serial2;
> +               serial3 = &serial3;
> +       };

> +               apb {
> +                       serial0: serial@0 {
> +                               status = "okay";
> +                       };
> +
> +                       serial1: serial@1000 {
> +                               status = "disabled";
> +                       };
> +
> +                       serial2: serial@2000 {
> +                               status = "disabled";
> +                       };
> +
> +                       serial3: serial@3000 {
> +                               status = "disabled";
> +                       };

Please drop the aliases for disabled uarts. It probably also makes
sense to have the status="disabled" properties in the .dtsi file and
only override them when you explicitly want to enable a uart for a
board.

       Arnd

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Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Tomer Maimon]

[-- Attachment #1: Type: text/plain, Size: 1462 bytes --]

Hi,

Thanks for your comments.

the patch will modify according to your comments and will be sent in the
next kernel revision 5.19.rc1

On Mon, 23 May 2022 at 12:40, Arnd Bergmann <arnd@arndb.de> wrote:

> On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> > +/ {
> > +       model = "Nuvoton npcm845 Development Board (Device Tree)";
> > +       compatible = "nuvoton,npcm845";
> > +
> > +       aliases {
> > +               serial0 = &serial0;
> > +               serial1 = &serial1;
> > +               serial2 = &serial2;
> > +               serial3 = &serial3;
> > +       };
>
> > +               apb {
> > +                       serial0: serial@0 {
> > +                               status = "okay";
> > +                       };
> > +
> > +                       serial1: serial@1000 {
> > +                               status = "disabled";
> > +                       };
> > +
> > +                       serial2: serial@2000 {
> > +                               status = "disabled";
> > +                       };
> > +
> > +                       serial3: serial@3000 {
> > +                               status = "disabled";
> > +                       };
>
> Please drop the aliases for disabled uarts. It probably also makes
> sense to have the status="disabled" properties in the .dtsi file and
> only override them when you explicitly want to enable a uart for a
> board.
>
>        Arnd
>

Best regards,

Tomer

[-- Attachment #2: Type: text/html, Size: 2464 bytes --]

Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Krzysztof Kozlowski]

On 23/05/2022 16:17, Tomer Maimon wrote:
> Hi,
> 
> Thanks for your comments.
> 
> the patch will modify according to your comments and will be sent in the
> next kernel revision 5.19.rc1
> 

None of your emails reach lists because of using HTML. Please use
appropriate messaging format.

Best regards,
Krzysztof

Re: [PATCH v1 18/19] arm64: dts: nuvoton: Add initial NPCM845 EVB device tree

[Krzysztof Kozlowski]

On 23/05/2022 16:17, Tomer Maimon wrote:
> Hi,
> 
> Thanks for your comments.
> 
> the patch will modify according to your comments and will be sent in the
> next kernel revision 5.19.rc1
> 

None of your emails reach lists because of using HTML. Please use
appropriate messaging format.

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v1 19/19] arm64: defconfig: Add Nuvoton NPCM family support

[Tomer Maimon]

Enable basic drivers for NPCM8XX booting up support:
Architecture, Clock, and WD.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm64/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 50aa3d75ab4f..42ad8ac85b99 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -49,6 +49,7 @@ CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_MESON=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NPCM=y
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_ROCKCHIP=y
@@ -617,6 +618,7 @@ CONFIG_RENESAS_WDT=y
 CONFIG_RENESAS_RZG2LWDT=y
 CONFIG_UNIPHIER_WATCHDOG=y
 CONFIG_BCM2835_WDT=y
+CONFIG_NPCM7XX_WATCHDOG=y
 CONFIG_MFD_ALTERA_SYSMGR=y
 CONFIG_MFD_BD9571MWV=y
 CONFIG_MFD_AXP20X_I2C=y
@@ -997,6 +999,7 @@ CONFIG_COMMON_CLK_FSL_SAI=y
 CONFIG_COMMON_CLK_S2MPS11=y
 CONFIG_COMMON_CLK_PWM=y
 CONFIG_COMMON_CLK_VC5=y
+CONFIG_COMMON_CLK_NPCM8XX=y
 CONFIG_COMMON_CLK_BD718XX=m
 CONFIG_CLK_RASPBERRYPI=m
 CONFIG_CLK_IMX8MM=y
-- 
2.33.0

Re: [PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> This patchset  adds initial support for the Nuvoton
> Arbel NPCM8XX Board Management controller (BMC) SoC family.
>
> The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
> The NPCM8XX computing subsystem comprises a quadcore ARM
> Cortex A35 ARM-V8 architecture.
>
> This patchset adds minimal architecture and drivers such as:
> Clocksource, Clock, Reset, and WD.
>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.

Thanks for your submission. Please note a few things about the process here:

- The merge window is currently open, which means a lo

Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

This patchset was tested on the Arbel NPCM8XX evaluation board.

Tomer Maimon (19):
  dt-bindings: timer: npcm: Add npcm845 compatible string
  clocksource: timer-npcm7xx: Add NPCM845 timer support
  dt-bindings: serial: 8250: Add npcm845 compatible string
  tty: serial: 8250: Add NPCM845 UART support
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  watchdog: npcm_wdt: Add NPCM845 watchdog support
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  clk: npcm8xx: add clock controller
  dt-bindings: reset: add syscon property
  reset: npcm: using syscon instead of device data
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: Add NPCM8XX support
  dt-bindings: arm: npcm: Add maintainer
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers
  won't be reviewing your patches at the moment. It may be better to wait
  for the -rc1 to be out before sending out v2

- don't send your patches to soc@kernel.org unless you want me to pick
  them up into the soc tree and they have been reviewed already. The series
  is clearly still under review at the moment, and I expect it to go through
  a few revisions first.

- gmail marked your emails as possible spam for me. I don't know what
  happened here, but you may want to look into this to ensure that
  everybody receives it.

Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

This patchset was tested on the Arbel NPCM8XX evaluation board.

Tomer Maimon (19):
  dt-bindings: timer: npcm: Add npcm845 compatible string
  clocksource: timer-npcm7xx: Add NPCM845 timer support
  dt-bindings: serial: 8250: Add npcm845 compatible string
  tty: serial: 8250: Add NPCM845 UART support
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  watchdog: npcm_wdt: Add NPCM845 watchdog support
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  clk: npcm8xx: add clock controller
  dt-bindings: reset: add syscon property
  reset: npcm: using syscon instead of device data
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: Add NPCM8XX support
  dt-bindings: arm: npcm: Add maintainer
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: defconfig: Add Nuvoton NPCM family support

- For an initial platform submission, I can merge the
  clk/clocksource/serial/reset drivers along with the platform if they
  have an Ack from the subsystem maintainers. I would normally
  not include the watchdog patch in this as it's not essential, but
  I suppose that it's fine if you only do a oneline change and it
  has an Ack. If you have other nonessential drivers that need changes,
  best submit them separately though.

         Arnd

Re: [PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[Arnd Bergmann]

On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> This patchset  adds initial support for the Nuvoton
> Arbel NPCM8XX Board Management controller (BMC) SoC family.
>
> The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
> The NPCM8XX computing subsystem comprises a quadcore ARM
> Cortex A35 ARM-V8 architecture.
>
> This patchset adds minimal architecture and drivers such as:
> Clocksource, Clock, Reset, and WD.
>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.

Thanks for your submission. Please note a few things about the process here:

- The merge window is currently open, which means a lo

Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

This patchset was tested on the Arbel NPCM8XX evaluation board.

Tomer Maimon (19):
  dt-bindings: timer: npcm: Add npcm845 compatible string
  clocksource: timer-npcm7xx: Add NPCM845 timer support
  dt-bindings: serial: 8250: Add npcm845 compatible string
  tty: serial: 8250: Add NPCM845 UART support
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  watchdog: npcm_wdt: Add NPCM845 watchdog support
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  clk: npcm8xx: add clock controller
  dt-bindings: reset: add syscon property
  reset: npcm: using syscon instead of device data
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: Add NPCM8XX support
  dt-bindings: arm: npcm: Add maintainer
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers
  won't be reviewing your patches at the moment. It may be better to wait
  for the -rc1 to be out before sending out v2

- don't send your patches to soc@kernel.org unless you want me to pick
  them up into the soc tree and they have been reviewed already. The series
  is clearly still under review at the moment, and I expect it to go through
  a few revisions first.

- gmail marked your emails as possible spam for me. I don't know what
  happened here, but you may want to look into this to ensure that
  everybody receives it.

Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.

This patchset was tested on the Arbel NPCM8XX evaluation board.

Tomer Maimon (19):
  dt-bindings: timer: npcm: Add npcm845 compatible string
  clocksource: timer-npcm7xx: Add NPCM845 timer support
  dt-bindings: serial: 8250: Add npcm845 compatible string
  tty: serial: 8250: Add NPCM845 UART support
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  watchdog: npcm_wdt: Add NPCM845 watchdog support
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  clk: npcm8xx: add clock controller
  dt-bindings: reset: add syscon property
  reset: npcm: using syscon instead of device data
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: Add NPCM8XX support
  dt-bindings: arm: npcm: Add maintainer
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: defconfig: Add Nuvoton NPCM family support

- For an initial platform submission, I can merge the
  clk/clocksource/serial/reset drivers along with the platform if they
  have an Ack from the subsystem maintainers. I would normally
  not include the watchdog patch in this as it's not essential, but
  I suppose that it's fine if you only do a oneline change and it
  has an Ack. If you have other nonessential drivers that need changes,
  best submit them separately though.

         Arnd

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[Tomer Maimon]

[-- Attachment #1: Type: text/plain, Size: 4577 bytes --]

Hi Arnd,

Appreciate your comments

On Mon, 23 May 2022 at 14:46, Arnd Bergmann <arnd@arndb.de> wrote:

> On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >
> > This patchset  adds initial support for the Nuvoton
> > Arbel NPCM8XX Board Management controller (BMC) SoC family.
> >
> > The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
> > The NPCM8XX computing subsystem comprises a quadcore ARM
> > Cortex A35 ARM-V8 architecture.
> >
> > This patchset adds minimal architecture and drivers such as:
> > Clocksource, Clock, Reset, and WD.
> >
> > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
> >
> > This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Thanks for your submission. Please note a few things about the process
> here:
>
> - The merge window is currently open, which means a lo
>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
>   dt-bindings: timer: npcm: Add npcm845 compatible string
>   clocksource: timer-npcm7xx: Add NPCM845 timer support
>   dt-bindings: serial: 8250: Add npcm845 compatible string
>   tty: serial: 8250: Add NPCM845 UART support
>   dt-bindings: watchdog: npcm: Add npcm845 compatible string
>   watchdog: npcm_wdt: Add NPCM845 watchdog support
>   dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
>   clk: npcm8xx: add clock controller
>   dt-bindings: reset: add syscon property
>   reset: npcm: using syscon instead of device data
>   dt-bindings: reset: npcm: Add support for NPCM8XX
>   reset: npcm: Add NPCM8XX support
>   dt-bindings: arm: npcm: Add maintainer
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
>   arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
>   arm64: dts: nuvoton: Add initial NPCM8XX device tree
>   arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
>   arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers
>   won't be reviewing your patches at the moment. It may be better to wait
>   for the -rc1 to be out before sending out v2
>
 Will do.

>
> - don't send your patches to soc@kernel.org unless you want me to pick
>   them up into the soc tree and they have been reviewed already. The series
>   is clearly still under review at the moment, and I expect it to go
> through
>   a few revisions first.
>
I will remove soc@kernel.org in the next patchset revision.


> - gmail marked your emails as possible spam for me. I don't know what
>   happened here, but you may want to look into this to ensure that
>   everybody receives it.

Unfortunately, this is happen because of the way we send the mail from our
mail server.
I double-check it our IT guys if there is a way to overcome it.

>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
>   dt-bindings: timer: npcm: Add npcm845 compatible string
>   clocksource: timer-npcm7xx: Add NPCM845 timer support
>   dt-bindings: serial: 8250: Add npcm845 compatible string
>   tty: serial: 8250: Add NPCM845 UART support
>   dt-bindings: watchdog: npcm: Add npcm845 compatible string
>   watchdog: npcm_wdt: Add NPCM845 watchdog support
>   dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
>   clk: npcm8xx: add clock controller
>   dt-bindings: reset: add syscon property
>   reset: npcm: using syscon instead of device data
>   dt-bindings: reset: npcm: Add support for NPCM8XX
>   reset: npcm: Add NPCM8XX support
>   dt-bindings: arm: npcm: Add maintainer
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
>   arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
>   arm64: dts: nuvoton: Add initial NPCM8XX device tree
>   arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
>   arm64: defconfig: Add Nuvoton NPCM family support
>
> - For an initial platform submission, I can merge the
>   clk/clocksource/serial/reset drivers along with the platform if they
>   have an Ack from the subsystem maintainers. I would normally
>   not include the watchdog patch in this as it's not essential, but
>   I suppose that it's fine if you only do a oneline change and it
>   has an Ack. If you have other nonessential drivers that need changes,
>   best submit them separately though.
>
Sure.

>
>          Arnd
>

Best regards,

Tomer

[-- Attachment #2: Type: text/html, Size: 6106 bytes --]

Re: [PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[Andy Shevchenko]

On Mon, May 23, 2022 at 1:59 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >
> > This patchset  adds initial support for the Nuvoton
> > Arbel NPCM8XX Board Management controller (BMC) SoC family.
> >
> > The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
> > The NPCM8XX computing subsystem comprises a quadcore ARM
> > Cortex A35 ARM-V8 architecture.
> >
> > This patchset adds minimal architecture and drivers such as:
> > Clocksource, Clock, Reset, and WD.
> >
> > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
> >
> > This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Thanks for your submission. Please note a few things about the process here:
>
> - The merge window is currently open, which means a lo

Something wrong with the script?

> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
>   dt-bindings: timer: npcm: Add npcm845 compatible string
>   clocksource: timer-npcm7xx: Add NPCM845 timer support
>   dt-bindings: serial: 8250: Add npcm845 compatible string
>   tty: serial: 8250: Add NPCM845 UART support
>   dt-bindings: watchdog: npcm: Add npcm845 compatible string
>   watchdog: npcm_wdt: Add NPCM845 watchdog support
>   dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
>   clk: npcm8xx: add clock controller
>   dt-bindings: reset: add syscon property
>   reset: npcm: using syscon instead of device data
>   dt-bindings: reset: npcm: Add support for NPCM8XX
>   reset: npcm: Add NPCM8XX support
>   dt-bindings: arm: npcm: Add maintainer
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
>   arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
>   arm64: dts: nuvoton: Add initial NPCM8XX device tree
>   arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
>   arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers
>   won't be reviewing your patches at the moment. It may be better to wait
>   for the -rc1 to be out before sending out v2
>
> - don't send your patches to soc@kernel.org unless you want me to pick
>   them up into the soc tree and they have been reviewed already. The series
>   is clearly still under review at the moment, and I expect it to go through
>   a few revisions first.
>
> - gmail marked your emails as possible spam for me. I don't know what
>   happened here, but you may want to look into this to ensure that
>   everybody receives it.
>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
>   dt-bindings: timer: npcm: Add npcm845 compatible string
>   clocksource: timer-npcm7xx: Add NPCM845 timer support
>   dt-bindings: serial: 8250: Add npcm845 compatible string
>   tty: serial: 8250: Add NPCM845 UART support
>   dt-bindings: watchdog: npcm: Add npcm845 compatible string
>   watchdog: npcm_wdt: Add NPCM845 watchdog support
>   dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
>   clk: npcm8xx: add clock controller
>   dt-bindings: reset: add syscon property
>   reset: npcm: using syscon instead of device data
>   dt-bindings: reset: npcm: Add support for NPCM8XX
>   reset: npcm: Add NPCM8XX support
>   dt-bindings: arm: npcm: Add maintainer
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
>   arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
>   arm64: dts: nuvoton: Add initial NPCM8XX device tree
>   arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
>   arm64: defconfig: Add Nuvoton NPCM family support
>
> - For an initial platform submission, I can merge the
>   clk/clocksource/serial/reset drivers along with the platform if they
>   have an Ack from the subsystem maintainers. I would normally
>   not include the watchdog patch in this as it's not essential, but
>   I suppose that it's fine if you only do a oneline change and it
>   has an Ack. If you have other nonessential drivers that need changes,
>   best submit them separately though.
>
>          Arnd



-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC

[Andy Shevchenko]

On Mon, May 23, 2022 at 1:59 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >
> > This patchset  adds initial support for the Nuvoton
> > Arbel NPCM8XX Board Management controller (BMC) SoC family.
> >
> > The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
> > The NPCM8XX computing subsystem comprises a quadcore ARM
> > Cortex A35 ARM-V8 architecture.
> >
> > This patchset adds minimal architecture and drivers such as:
> > Clocksource, Clock, Reset, and WD.
> >
> > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
> >
> > This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Thanks for your submission. Please note a few things about the process here:
>
> - The merge window is currently open, which means a lo

Something wrong with the script?

> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
>   dt-bindings: timer: npcm: Add npcm845 compatible string
>   clocksource: timer-npcm7xx: Add NPCM845 timer support
>   dt-bindings: serial: 8250: Add npcm845 compatible string
>   tty: serial: 8250: Add NPCM845 UART support
>   dt-bindings: watchdog: npcm: Add npcm845 compatible string
>   watchdog: npcm_wdt: Add NPCM845 watchdog support
>   dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
>   clk: npcm8xx: add clock controller
>   dt-bindings: reset: add syscon property
>   reset: npcm: using syscon instead of device data
>   dt-bindings: reset: npcm: Add support for NPCM8XX
>   reset: npcm: Add NPCM8XX support
>   dt-bindings: arm: npcm: Add maintainer
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
>   arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
>   arm64: dts: nuvoton: Add initial NPCM8XX device tree
>   arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
>   arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers
>   won't be reviewing your patches at the moment. It may be better to wait
>   for the -rc1 to be out before sending out v2
>
> - don't send your patches to soc@kernel.org unless you want me to pick
>   them up into the soc tree and they have been reviewed already. The series
>   is clearly still under review at the moment, and I expect it to go through
>   a few revisions first.
>
> - gmail marked your emails as possible spam for me. I don't know what
>   happened here, but you may want to look into this to ensure that
>   everybody receives it.
>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
>   dt-bindings: timer: npcm: Add npcm845 compatible string
>   clocksource: timer-npcm7xx: Add NPCM845 timer support
>   dt-bindings: serial: 8250: Add npcm845 compatible string
>   tty: serial: 8250: Add NPCM845 UART support
>   dt-bindings: watchdog: npcm: Add npcm845 compatible string
>   watchdog: npcm_wdt: Add NPCM845 watchdog support
>   dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
>   clk: npcm8xx: add clock controller
>   dt-bindings: reset: add syscon property
>   reset: npcm: using syscon instead of device data
>   dt-bindings: reset: npcm: Add support for NPCM8XX
>   reset: npcm: Add NPCM8XX support
>   dt-bindings: arm: npcm: Add maintainer
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
>   dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
>   arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
>   arm64: dts: nuvoton: Add initial NPCM8XX device tree
>   arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
>   arm64: defconfig: Add Nuvoton NPCM family support
>
> - For an initial platform submission, I can merge the
>   clk/clocksource/serial/reset drivers along with the platform if they
>   have an Ack from the subsystem maintainers. I would normally
>   not include the watchdog patch in this as it's not essential, but
>   I suppose that it's fine if you only do a oneline change and it
>   has an Ack. If you have other nonessential drivers that need changes,
>   best submit them separately though.
>
>          Arnd



-- 
With Best Regards,
Andy Shevchenko

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