* [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
@ 2016-03-14 16:56 Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
` (17 more replies)
0 siblings, 18 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, Cédric Le Goater, qemu-ppc, qemu-devel
Hello,
This is a first mini-serie of patches adding support for new ppc SPRs.
They were taken from Ben's larger patchset adding the ppc powernv
platform and they should already be useful for the pseries guest
migration.
Initial patches come from :
https://github.com/ozbenh/qemu/commits/powernv
The changes are mostly due to the rebase on Dave's 2.6 branch:
https://github.com/dgibson/qemu/commits/ppc-for-2.6
A couple more are bisect and checkpatch fixes and finally some patches
were merge to reduce the noise.
The patchset is also available here:
https://github.com/legoater/qemu/commits/for-2.6
It was quickly tested with a pseries guest using KVM and TCG.
Thanks,
C.
Benjamin Herrenschmidt (17):
ppc: Update SPR definitions
ppc: Add macros to register hypervisor mode SPRs
ppc: Add a bunch of hypervisor SPRs to Book3s
ppc: Add number of threads per core to the processor definition
ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
ppc: Create cpu_ppc_set_papr() helper
ppc: Better figure out if processor has HV mode
ppc: Add placeholder SPRs for DPDES and DHDES on P8
ppc: SPURR & PURR are HV writeable and privileged
ppc: Add dummy SPR_IC for POWER8
ppc: Initialize AMOR in PAPR mode
ppc: Fix writing to AMR/UAMOR
ppc: Add POWER8 IAMR register
ppc: Add dummy write to VTB
ppc: Add dummy POWER8 MPPR register
ppc: Add dummy CIABR SPR
ppc: A couple more dummy POWER8 Book4 regs
hw/ppc/spapr.c | 11 +-
target-ppc/cpu-qom.h | 1 +
target-ppc/cpu.h | 68 ++++++-
target-ppc/excp_helper.c | 8 +-
target-ppc/helper_regs.h | 4 +-
target-ppc/translate.c | 30 +--
target-ppc/translate_init.c | 461 ++++++++++++++++++++++++++++++++++++++++----
7 files changed, 510 insertions(+), 73 deletions(-)
--
2.1.4
^ permalink raw reply [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 18:34 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Cédric Le Goater
` (16 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Add definitions for additional SPR numbers and SPR bit definitions
that will be relevant for subsequent improvements to POWER8 emulation
Also fix the definition of LPIDR which was incorrect (and is different
for server and embedded).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/cpu.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 47 insertions(+), 7 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8d90d862de17..9ce301f18922 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -474,9 +474,17 @@ struct ppc_slb_t {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
-#define LPCR_ILE (1 << (63-38))
-#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
-#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
+/* LPCR bits */
+#define LPCR_VPM0 (1ull << (63 - 0))
+#define LPCR_VPM1 (1ull << (63 - 1))
+#define LPCR_ISL (1ull << (63 - 2))
+#define LPCR_KBV (1ull << (63 - 3))
+#define LPCR_ILE (1ull << (63 - 38))
+#define LPCR_MER (1ull << (63 - 52))
+#define LPCR_LPES0 (1ull << (63 - 60))
+#define LPCR_LPES1 (1ull << (63 - 61))
+#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
+#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
@@ -1381,6 +1389,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_MPC_ICTRL (0x09E)
#define SPR_MPC_BAR (0x09F)
#define SPR_PSPB (0x09F)
+#define SPR_DAWR (0x0B4)
+#define SPR_RPR (0x0BA)
+#define SPR_DAWRX (0x0BC)
+#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)
#define SPR_USPRG0 (0x100)
#define SPR_USPRG1 (0x101)
@@ -1435,19 +1447,25 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_HSRR1 (0x13B)
#define SPR_BOOKE_IAC4 (0x13B)
#define SPR_BOOKE_DAC1 (0x13C)
-#define SPR_LPIDR (0x13D)
+#define SPR_MMCRH (0x13C)
#define SPR_DABR2 (0x13D)
#define SPR_BOOKE_DAC2 (0x13D)
+#define SPR_TFMR (0x13D)
#define SPR_BOOKE_DVC1 (0x13E)
#define SPR_LPCR (0x13E)
#define SPR_BOOKE_DVC2 (0x13F)
+#define SPR_LPIDR (0x13F)
#define SPR_BOOKE_TSR (0x150)
+#define SPR_HMER (0x150)
+#define SPR_HMEER (0x151)
#define SPR_PCR (0x152)
+#define SPR_BOOKE_LPIDR (0x152)
#define SPR_BOOKE_TCR (0x154)
#define SPR_BOOKE_TLB0PS (0x158)
#define SPR_BOOKE_TLB1PS (0x159)
#define SPR_BOOKE_TLB2PS (0x15A)
#define SPR_BOOKE_TLB3PS (0x15B)
+#define SPR_AMOR (0x15D)
#define SPR_BOOKE_MAS7_MAS3 (0x174)
#define SPR_BOOKE_IVOR0 (0x190)
#define SPR_BOOKE_IVOR1 (0x191)
@@ -1667,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_TAR (0x32F)
#define SPR_VTB (0x351)
+#define SPR_MMCRC (0x353)
#define SPR_440_INV0 (0x370)
#define SPR_440_INV1 (0x371)
#define SPR_440_INV2 (0x372)
@@ -1705,6 +1724,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_440_DVLIM (0x398)
#define SPR_750_WPAR (0x399)
#define SPR_440_IVLIM (0x399)
+#define SPR_TSCR (0x399)
#define SPR_750_DMAU (0x39A)
#define SPR_750_DMAL (0x39B)
#define SPR_440_RSTCFG (0x39B)
@@ -1879,9 +1899,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
/* HID0 bits */
-#define HID0_DEEPNAP (1 << 24)
-#define HID0_DOZE (1 << 23)
-#define HID0_NAP (1 << 22)
+#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
+#define HID0_DOZE (1 << 23) /* pre-2.06 */
+#define HID0_NAP (1 << 22) /* pre-2.06 */
+#define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
/*****************************************************************************/
/* PowerPC Instructions types definitions */
@@ -2230,6 +2251,25 @@ enum {
PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
};
+/* HMER/HMEER */
+enum {
+ HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
+ HMER_PROC_RECV_DONE = 1ull << (63 - 2),
+ HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
+ HMER_TFAC_ERROR = 1ull << (63 - 4),
+ HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
+ HMER_XSCOM_FAIL = 1ull << (63 - 8),
+ HMER_XSCOM_DONE = 1ull << (63 - 9),
+ HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
+ HMER_WARN_RISE = 1ull << (63 - 14),
+ HMER_WARN_FALL = 1ull << (63 - 15),
+ HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
+ HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
+ HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
+ HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
+ HMER_XSCOM_STATUS_LSH = (63 - 23),
+};
+
/*****************************************************************************/
static inline target_ulong cpu_read_xer(CPUPPCState *env)
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 18:50 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
` (15 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The current set of spr_register_* macros only take the user and
supervisor function pointers. To make the transition easy, we
don't change that but we add "_hv" variants that can be used to
register all 3 sets.
To simplify the transition, users of the "old" macro will set the
hypervisor callback to be the same as the supervisor one. The new
registration function only needs to be used for registers that are
either hypervisor only or behave differently in HV mode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate.c | 26 ++++++++++++++++----------
target-ppc/translate_init.c | 35 +++++++++++++++++++++++++++++++----
2 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e402ff920314..327f3259b4be 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4282,14 +4282,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
uint32_t sprn = SPR(ctx->opcode);
-#if !defined(CONFIG_USER_ONLY)
- if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+ read_cb = ctx->spr_cb[sprn].uea_read;
+#else
+ if (ctx->pr) {
+ read_cb = ctx->spr_cb[sprn].uea_read;
+ } else if (ctx->hv) {
read_cb = ctx->spr_cb[sprn].hea_read;
- else if (!ctx->pr)
+ } else if (!ctx->pr) {
read_cb = ctx->spr_cb[sprn].oea_read;
- else
+ }
#endif
- read_cb = ctx->spr_cb[sprn].uea_read;
if (likely(read_cb != NULL)) {
if (likely(read_cb != SPR_NOACCESS)) {
(*read_cb)(ctx, rD(ctx->opcode), sprn);
@@ -4437,14 +4440,17 @@ static void gen_mtspr(DisasContext *ctx)
void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
uint32_t sprn = SPR(ctx->opcode);
-#if !defined(CONFIG_USER_ONLY)
- if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+ write_cb = ctx->spr_cb[sprn].uea_write;
+#else
+ if (ctx->pr) {
+ write_cb = ctx->spr_cb[sprn].uea_write;
+ } else if (ctx->hv) {
write_cb = ctx->spr_cb[sprn].hea_write;
- else if (!ctx->pr)
+ } else {
write_cb = ctx->spr_cb[sprn].oea_write;
- else
+ }
#endif
- write_cb = ctx->spr_cb[sprn].uea_write;
if (likely(write_cb != NULL)) {
if (likely(write_cb != SPR_NOACCESS)) {
(*write_cb)(ctx, sprn, rS(ctx->opcode));
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index fb206aff29ad..6a11b41206e5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -579,17 +579,33 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, initial_value)
#else
#if !defined(CONFIG_KVM)
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, oea_read, oea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, initial_value)
+ oea_read, oea_write, hea_read, hea_write, initial_value)
#else
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, oea_read, oea_write, \
+ one_reg_id, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value)
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value)
#endif
#endif
@@ -598,6 +614,13 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, 0, initial_value)
+#define spr_register_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ initial_value) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ 0, initial_value)
+
static inline void _spr_register(CPUPPCState *env, int num,
const char *name,
void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
@@ -606,6 +629,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
+ void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
+ void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
#endif
#if defined(CONFIG_KVM)
uint64_t one_reg_id,
@@ -633,6 +658,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
#if !defined(CONFIG_USER_ONLY)
spr->oea_read = oea_read;
spr->oea_write = oea_write;
+ spr->hea_read = hea_read;
+ spr->hea_write = hea_write;
#endif
#if defined(CONFIG_KVM)
spr->one_reg_id = one_reg_id,
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 19:14 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
` (14 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, Cédric Le Goater, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We don't give them a KVM reg number to most of the registers yet as no
current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
number is needed since this register can be set by the guest via the
H_SET_MODE hypercall.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
changed the commit log with a proposal of Thomas Huth ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 137 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6a11b41206e5..43c6e524a6bc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_UAMOR, 0);
+ spr_register_hv(env, SPR_AMOR, "AMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
#endif /* !CONFIG_USER_ONLY */
}
#endif /* TARGET_PPC64 */
@@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
KVM_REG_PPC_DABRX, 0x00000000);
}
+static void gen_spr_book3s_207_dbg(CPUPPCState *env)
+{
+ spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAWR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAWRX, 0x00000000);
+}
+
static void gen_spr_970_dbg(CPUPPCState *env)
{
/* Breakpoints */
@@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
spr_register_kvm(env, SPR_LPCR, "LPCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
+ KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
}
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv hmer = tcg_temp_new();
+
+ gen_load_spr(hmer, sprn);
+ tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
+ gen_store_spr(sprn, hmer);
+ spr_store_dump_spr(sprn);
+ tcg_temp_free(hmer);
+}
+#endif
+
static void gen_spr_book3s_ids(CPUPPCState *env)
{
+ /* FIXME: Will need to deal with thread vs core only SPRs */
+
/* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
+ spr_register_hv(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, NULL,
+ 0x00000000);
+ spr_register_hv(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TSCR, "TSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMER, "HMER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_hmer,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMEER, "HMEER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TFMR, "TFMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_LPIDR, "LPIDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HFSCR, "HFSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_MMCRC, "MMCRC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_MMCRH, "MMCRH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSRR0, "HSRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HSRR1, "HSRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HDAR, "HDAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HDSISR, "HDSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_RMOR, "RMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_HRMOR, "HRMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
0x00000000);
}
@@ -7905,6 +8025,17 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
KVM_REG_PPC_PSPB, 0);
}
+static void gen_spr_power8_rpr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_RPR, "RPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000103070F1F3F);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7957,9 +8088,12 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_tm(env);
gen_spr_power8_pspb(env);
gen_spr_vtb(env);
+ gen_spr_power8_rpr(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
+ } else {
+ gen_spr_book3s_207_dbg(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (2 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 19:20 ` Thomas Huth
2016-03-15 9:45 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
` (13 subsequent siblings)
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
are offset by that value in order to preserve consistency with the
HW implementations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/cpu-qom.h | 1 +
target-ppc/translate_init.c | 11 ++++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 7d5e2b36a997..735981309c5b 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
+ uint32_t threads_per_core;
#if defined(TARGET_PPC64)
const struct ppc_segment_page_sizes *sps;
#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 43c6e524a6bc..46dabe58783a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x10000;
+ pcc->threads_per_core = 2;
}
static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
@@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->threads_per_core = 4;
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->threads_per_core = 8;
}
#endif /* defined (TARGET_PPC64) */
@@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
#if !defined(CONFIG_USER_ONLY)
+ if (pcc->threads_per_core == 0) {
+ pcc->threads_per_core = 1;
+ }
+ if (max_smt > pcc->threads_per_core) {
+ max_smt = pcc->threads_per_core;
+ }
if (smp_threads > max_smt) {
error_setg(errp, "Cannot support more than %d threads on PPC with %s",
max_smt, kvm_enabled() ? "KVM" : "TCG");
@@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
}
#if !defined(CONFIG_USER_ONLY)
- cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
+ cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core
+ (cs->cpu_index % smp_threads);
#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (3 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 19:29 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
` (12 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This helper is only used by the various instructions that can alter
MSR and not interrupts. Add a comment to that effect to the interrupt
code as well in case somebody wants to change this
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/excp_helper.c | 8 ++++++--
target-ppc/helper_regs.h | 4 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index c890853d861b..37d4721db63b 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -666,8 +666,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
}
#endif
- /* XXX: we don't use hreg_store_msr here as already have treated
- * any special case that could occur. Just store MSR and update hflags
+ /* We don't use hreg_store_msr here as already have treated
+ * any special case that could occur. Just store MSR and update hflags
+ *
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
+ * will prevent setting of the HV bit which some exceptions might need
+ * to do.
*/
env->msr = new_msr & env->msr_mask;
hreg_compute_hflags(env);
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 271fddf17f0a..844240d1a755 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -75,8 +75,8 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
excp = 0;
value &= env->msr_mask;
#if !defined(CONFIG_USER_ONLY)
- if (!alter_hv) {
- /* mtmsr cannot alter the hypervisor state */
+ /* Neither mtmsr nor guest state can alter HV */
+ if (!alter_hv || !(env->msr & MSR_HVB)) {
value &= ~MSR_HVB;
value |= env->msr & MSR_HVB;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (4 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-17 2:34 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
` (11 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 11 ++---------
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++-
3 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 43708a2a9086..9c01872ce4d3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1612,15 +1612,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ);
- /* PAPR always has exception vectors in RAM not ROM. To ensure this,
- * MSR[IP] should never be set.
- */
- env->msr_mask &= ~(1 << 6);
-
- /* Tell KVM that we're in PAPR mode */
- if (kvm_enabled()) {
- kvmppc_set_papr(cpu);
- }
+ /* Enable PAPR mode in TCG or KVM */
+ cpu_ppc_set_papr(cpu);
if (cpu->max_compat) {
Error *local_err = NULL;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9ce301f18922..a7da0d3e95a9 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
+void cpu_ppc_set_papr(PowerPCCPU *cpu);
#endif
#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 46dabe58783a..093ef036320d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8496,8 +8496,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
pcc->threads_per_core = 8;
}
-#endif /* defined (TARGET_PPC64) */
+#if !defined(CONFIG_USER_ONLY)
+
+void cpu_ppc_set_papr(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
+
+ /* PAPR always has exception vectors in RAM not ROM. To ensure this,
+ * MSR[IP] should never be set.
+ *
+ * We also disallow setting of MSR_HV
+ */
+ env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+
+ /* Set emulated LPCR to not send interrupts to hypervisor. Note that
+ * under KVM, the actual HW LPCR will be set differently by KVM itself,
+ * the settings below ensure proper operations with TCG in absence of
+ * a real hypervisor
+ */
+ lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
+ lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
+
+ /* We should be followed by a CPU reset but update the active value
+ * just in case...
+ */
+ env->spr[SPR_LPCR] = lpcr->default_value;
+
+ /* Tell KVM that we're in PAPR mode */
+ if (kvm_enabled()) {
+ kvmppc_set_papr(cpu);
+ }
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+#endif /* defined (TARGET_PPC64) */
/*****************************************************************************/
/* Generic CPU instantiation routine */
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (5 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-16 1:05 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
` (10 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We use an env. flag which is set to the initial value of MSR_HVB in
the msr_mask. We also adjust the POWER8 mask to set SHV.
Also use this to adjust ctx.hv so that it is *set* when the processor
doesn't have an HV mode (970 with Apple mode for example), thus enabling
hypervisor instructions/SPRs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/cpu.h | 4 ++++
target-ppc/translate.c | 4 +++-
target-ppc/translate_init.c | 19 +++++++++++++++----
3 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a7da0d3e95a9..02aed6427ade 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1153,6 +1153,10 @@ struct CPUPPCState {
hwaddr mpic_iack;
/* true when the external proxy facility mode is enabled */
bool mpic_proxy;
+ /* set when the processor has an HV mode, thus HV priv
+ * instructions and SPRs are diallowed if MSR:HV is 0
+ */
+ bool has_hv_mode;
#endif
/* Those resources are used only during code translation */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 327f3259b4be..11801ded62d2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11456,8 +11456,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.exception = POWERPC_EXCP_NONE;
ctx.spr_cb = env->spr_cb;
ctx.pr = msr_pr;
- ctx.hv = !msr_pr && msr_hv;
ctx.mem_idx = env->mmu_idx;
+#if !defined(CONFIG_USER_ONLY)
+ ctx.hv = msr_hv || !env->has_hv_mode;
+#endif
ctx.insns_flags = env->insns_flags;
ctx.insns_flags2 = env->insns_flags2;
ctx.access_type = -1;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 093ef036320d..59a68de0bce8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8463,6 +8463,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM;
pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_SHV) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -9876,10 +9877,7 @@ static void ppc_cpu_reset(CPUState *s)
pcc->parent_reset(s);
msr = (target_ulong)0;
- if (0) {
- /* XXX: find a suitable condition to enable the hypervisor mode */
- msr |= (target_ulong)MSR_HVB;
- }
+ msr |= (target_ulong)MSR_HVB;
msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
msr |= (target_ulong)1 << MSR_EP;
@@ -9980,6 +9978,19 @@ static void ppc_cpu_initfn(Object *obj)
env->bfd_mach = pcc->bfd_mach;
env->check_pow = pcc->check_pow;
+ /* Mark HV mode as supported if the CPU has an MSR_HV bit
+ * in the msr_mask. The mask can later be cleared by PAPR
+ * mode but the hv mode support will remain, thus enforcing
+ * that we cannot use priv. instructions in guest in PAPR
+ * mode. For 970 we currently simply don't set HV in msr_mask
+ * thus simulating an "Apple mode" 970. If we ever want to
+ * support 970 HV mode, we'll have to add a processor attribute
+ * of some sort.
+ */
+#if !defined(CONFIG_USER_ONLY)
+ env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
+#endif
+
#if defined(TARGET_PPC64)
if (pcc->sps) {
env->sps = *pcc->sps;
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (6 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 19:32 ` Thomas Huth
2016-03-16 1:06 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
` (9 subsequent siblings)
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We still need to eventually implement doorbells but at least this
makes us not crash when the SPRs are accessed.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/cpu.h | 2 ++
target-ppc/translate_init.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 02aed6427ade..779cb57bd700 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1394,6 +1394,8 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_MPC_ICTRL (0x09E)
#define SPR_MPC_BAR (0x09F)
#define SPR_PSPB (0x09F)
+#define SPR_DHDES (0x0B1)
+#define SPR_DPDES (0x0B0)
#define SPR_DAWR (0x0B4)
#define SPR_RPR (0x0BA)
#define SPR_DAWRX (0x0BC)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 59a68de0bce8..7a399b97bc6f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8036,6 +8036,22 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
#endif
}
+static void gen_spr_power8_dbell(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_DPDES, "DPDES",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+ spr_register_hv(env, SPR_DHDES, "DHDES",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -8089,6 +8105,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_pspb(env);
gen_spr_vtb(env);
gen_spr_power8_rpr(env);
+ gen_spr_power8_dbell(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (7 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 19:37 ` Thomas Huth
2016-03-16 1:07 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
` (8 subsequent siblings)
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Those are HV writeable, so we provide a dummy write. We eventually need
to provide a better emulation but for now this will get us going.
We also make them non-user readable as per the architecture.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/translate_init.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7a399b97bc6f..10f67136b609 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -293,6 +293,13 @@ static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
}
+
+__attribute__ ((unused))
+static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
+{
+ /* Temporary placeholder */
+}
+
#endif
#endif
@@ -7828,14 +7835,16 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
- spr_register_kvm(env, SPR_PURR, "PURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_PURR, 0x00000000);
- spr_register_kvm(env, SPR_SPURR, "SPURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_SPURR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_PURR, "PURR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, &spr_write_purr,
+ KVM_REG_PPC_PURR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, &spr_write_purr,
+ KVM_REG_PPC_SPURR, 0x00000000);
#endif
}
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (8 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 19:40 ` Thomas Huth
2016-03-16 1:08 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
` (7 subsequent siblings)
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
It's supposed to be an instruction counter. For now make us not
crash when accessing it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 779cb57bd700..6952d789e518 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1691,6 +1691,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_MPC_MD_DBRAM1 (0x32A)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_TAR (0x32F)
+#define SPR_IC (0x350)
#define SPR_VTB (0x351)
#define SPR_MMCRC (0x353)
#define SPR_440_INV0 (0x370)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 10f67136b609..68abd847a251 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8061,6 +8061,17 @@ static void gen_spr_power8_dbell(CPUPPCState *env)
#endif
}
+static void gen_spr_power8_ic(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_IC, "IC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -8115,6 +8126,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_vtb(env);
gen_spr_power8_rpr(env);
gen_spr_power8_dbell(env);
+ gen_spr_power8_ic(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (9 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 20:13 ` Thomas Huth
` (2 more replies)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
` (6 subsequent siblings)
17 siblings, 3 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Make sure we give the guest full authorization
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/translate_init.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 68abd847a251..c921d9f53984 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8542,6 +8542,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
+ ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
/* PAPR always has exception vectors in RAM not ROM. To ensure this,
* MSR[IP] should never be set.
@@ -8563,6 +8564,9 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
*/
env->spr[SPR_LPCR] = lpcr->default_value;
+ /* Set a full AMOR so guest can use the AMR as it sees fit */
+ env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
+
/* Tell KVM that we're in PAPR mode */
if (kvm_enabled()) {
kvmppc_set_papr(cpu);
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (10 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 20:26 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
` (5 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, Cédric Le Goater, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The masks weren't chosen nor applied properly. The architecture specifies
that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0.
The writes to UAMOR are masked by AMOR for HV=0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: fixed gen_spr_amr() call in init_proc_book3s_64()]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
target-ppc/translate_init.c | 78 +++++++++++++++++++++++++++++++++++----------
1 file changed, 61 insertions(+), 17 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c921d9f53984..f2eb5f041ecd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1070,30 +1070,72 @@ static void gen_spr_7xx (CPUPPCState *env)
#ifdef TARGET_PPC64
#ifndef CONFIG_USER_ONLY
-static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn)
+static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
{
- gen_load_spr(cpu_gpr[gprn], SPR_AMR);
- spr_load_dump_spr(SPR_AMR);
-}
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
-static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
+ /* Note, the HV=1 PR=0 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ if (ctx->pr) {
+ gen_load_spr(t1, SPR_UAMOR);
+ } else {
+ gen_load_spr(t1, SPR_AMOR);
+ }
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_AMR, t0);
spr_store_dump_spr(SPR_AMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
-static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn)
+static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /* Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
gen_load_spr(t0, SPR_UAMOR);
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- gen_store_spr(SPR_AMR, t0);
- spr_store_dump_spr(SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_UAMOR, t0);
+ spr_store_dump_spr(SPR_UAMOR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
#endif /* CONFIG_USER_ONLY */
-static void gen_spr_amr (CPUPPCState *env)
+static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
{
#ifndef CONFIG_USER_ONLY
/* Virtual Page Class Key protection */
@@ -1101,15 +1143,17 @@ static void gen_spr_amr (CPUPPCState *env)
* userspace accessible, 29 is privileged. So we only need to set
* the kvm ONE_REG id on one of them, we use 29 */
spr_register(env, SPR_UAMR, "UAMR",
- &spr_read_uamr, &spr_write_uamr_pr,
- &spr_read_uamr, &spr_write_uamr,
+ &spr_read_generic, &spr_write_amr,
+ &spr_read_generic, &spr_write_amr,
0);
- spr_register_kvm(env, SPR_AMR, "AMR",
+ spr_register_kvm_hv(env, SPR_AMR, "AMR",
SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_amr,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_AMR, 0);
- spr_register_kvm(env, SPR_UAMOR, "UAMOR",
+ spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_uamor,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_UAMOR, 0);
spr_register_hv(env, SPR_AMOR, "AMOR",
@@ -8093,7 +8137,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
case BOOK3S_CPU_POWER7:
case BOOK3S_CPU_POWER8:
gen_spr_book3s_ids(env);
- gen_spr_amr(env);
+ gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
gen_spr_book3s_purr(env);
env->ci_large_pages = true;
break;
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (11 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 20:36 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
` (4 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, Cédric Le Goater, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
With appropriate AMR-like masks. Not actually used by the translation
logic at that point
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: add the use of spr_register_kvm_hv()]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 6952d789e518..81a3e6b5ed29 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1364,6 +1364,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_BOOKE_CSRR0 (0x03A)
#define SPR_BOOKE_CSRR1 (0x03B)
#define SPR_BOOKE_DEAR (0x03D)
+#define SPR_IAMR (0x03D)
#define SPR_BOOKE_ESR (0x03E)
#define SPR_BOOKE_IVPR (0x03F)
#define SPR_MPC_EIE (0x050)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f2eb5f041ecd..2fac6ea58698 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1133,6 +1133,36 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t1);
tcg_temp_free(t2);
}
+
+static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /* Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_IAMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_IAMR, t0);
+ spr_store_dump_spr(SPR_IAMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
#endif /* CONFIG_USER_ONLY */
static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
@@ -1161,6 +1191,14 @@ static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0);
+ if (!has_iamr) {
+ return;
+ }
+ spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_iamr,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_IAMR, 0);
#endif /* !CONFIG_USER_ONLY */
}
#endif /* TARGET_PPC64 */
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (12 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 20:54 ` Thomas Huth
2016-03-16 1:12 ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
` (3 subsequent siblings)
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The Hypervisor can write it. We don't handle that properly yet but
at least let's not blow up when it is written.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/translate_init.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 2fac6ea58698..28a9c2e73156 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -300,6 +300,12 @@ static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
/* Temporary placeholder */
}
+__attribute__ ((unused))
+static void spr_write_vtb(DisasContext *ctx, int gprn, int sprn)
+{
+ /* Temporary placeholder */
+}
+
#endif
#endif
@@ -8089,10 +8095,11 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
/* Virtual Time Base */
static void gen_spr_vtb(CPUPPCState *env)
{
- spr_register(env, SPR_VTB, "VTB",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
+ spr_register_hv(env, SPR_VTB, "VTB",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, spr_write_vtb,
+ 0x00000000);
}
static void gen_spr_power8_fscr(CPUPPCState *env)
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (13 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-16 1:14 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
` (2 subsequent siblings)
17 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Controls the micropartition prefetch, this is pretty much meaningless
in full emulation (used for priming the caches on real HW).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 81a3e6b5ed29..5203cc6a3bfb 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1398,6 +1398,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_DHDES (0x0B1)
#define SPR_DPDES (0x0B0)
#define SPR_DAWR (0x0B4)
+#define SPR_MPPR (0x0B8)
#define SPR_RPR (0x0BA)
#define SPR_DAWRX (0x0BC)
#define SPR_HFSCR (0x0BE)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 28a9c2e73156..cfb1bc088950 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8161,6 +8161,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
#endif
}
+static void gen_spr_power8_book4(CPUPPCState *env)
+{
+ /* Add a number of P8 book4 registers */
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_MPPR, "MPPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -8216,6 +8228,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_rpr(env);
gen_spr_power8_dbell(env);
gen_spr_power8_ic(env);
+ gen_spr_power8_book4(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (14 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 20:00 ` Thomas Huth
2016-03-16 1:14 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
2016-03-15 0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
We should implement HW breakpoint/watchpoint, qemu supports them...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5203cc6a3bfb..9e1ef10b7dc6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_DAWR (0x0B4)
#define SPR_MPPR (0x0B8)
#define SPR_RPR (0x0BA)
+#define SPR_CIABR (0x0BB)
#define SPR_DAWRX (0x0BC)
#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index cfb1bc088950..f88bdf7b3cd1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DAWRX, 0x00000000);
+ spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_CIABR, 0x00000000);
}
static void gen_spr_970_dbg(CPUPPCState *env)
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (15 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
@ 2016-03-14 16:56 ` Cédric Le Goater
2016-03-14 20:08 ` Thomas Huth
2016-03-16 1:15 ` David Gibson
2016-03-15 0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
17 siblings, 2 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-14 16:56 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, Cédric Le Goater, qemu-ppc, qemu-devel
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
target-ppc/cpu.h | 3 +++
target-ppc/translate_init.c | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9e1ef10b7dc6..9ed406cf111b 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1359,7 +1359,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_SRR1 (0x01B)
#define SPR_CFAR (0x01C)
#define SPR_AMR (0x01D)
+#define SPR_ACOP (0x01F)
#define SPR_BOOKE_PID (0x030)
+#define SPR_BOOKS_PID (0x030)
#define SPR_BOOKE_DECAR (0x036)
#define SPR_BOOKE_CSRR0 (0x03A)
#define SPR_BOOKE_CSRR1 (0x03B)
@@ -1713,6 +1715,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_POWER_SPMC1 (0x37C)
#define SPR_POWER_SPMC2 (0x37D)
#define SPR_POWER_MMCRS (0x37E)
+#define SPR_WORT (0x37F)
#define SPR_PPR (0x380)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f88bdf7b3cd1..22afeef2731a 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8175,6 +8175,18 @@ static void gen_spr_power8_book4(CPUPPCState *env)
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0);
+ spr_register_kvm(env, SPR_ACOP, "ACOP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_ACOP, 0);
+ spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PID, 0);
+ spr_register_kvm(env, SPR_WORT, "WORT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_WORT, 0);
#endif
}
--
2.1.4
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
@ 2016-03-14 18:34 ` Thomas Huth
0 siblings, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 18:34 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Add definitions for additional SPR numbers and SPR bit definitions
> that will be relevant for subsequent improvements to POWER8 emulation
>
> Also fix the definition of LPIDR which was incorrect (and is different
> for server and embedded).
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/cpu.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 47 insertions(+), 7 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 8d90d862de17..9ce301f18922 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -474,9 +474,17 @@ struct ppc_slb_t {
> #define MSR_RI 1 /* Recoverable interrupt 1 */
> #define MSR_LE 0 /* Little-endian mode 1 hflags */
>
> -#define LPCR_ILE (1 << (63-38))
> -#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
> -#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
> +/* LPCR bits */
> +#define LPCR_VPM0 (1ull << (63 - 0))
> +#define LPCR_VPM1 (1ull << (63 - 1))
> +#define LPCR_ISL (1ull << (63 - 2))
> +#define LPCR_KBV (1ull << (63 - 3))
> +#define LPCR_ILE (1ull << (63 - 38))
> +#define LPCR_MER (1ull << (63 - 52))
> +#define LPCR_LPES0 (1ull << (63 - 60))
> +#define LPCR_LPES1 (1ull << (63 - 61))
> +#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
> +#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
>
> #define msr_sf ((env->msr >> MSR_SF) & 1)
> #define msr_isf ((env->msr >> MSR_ISF) & 1)
> @@ -1381,6 +1389,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_MPC_ICTRL (0x09E)
> #define SPR_MPC_BAR (0x09F)
> #define SPR_PSPB (0x09F)
> +#define SPR_DAWR (0x0B4)
> +#define SPR_RPR (0x0BA)
> +#define SPR_DAWRX (0x0BC)
> +#define SPR_HFSCR (0x0BE)
> #define SPR_VRSAVE (0x100)
> #define SPR_USPRG0 (0x100)
> #define SPR_USPRG1 (0x101)
> @@ -1435,19 +1447,25 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_HSRR1 (0x13B)
> #define SPR_BOOKE_IAC4 (0x13B)
> #define SPR_BOOKE_DAC1 (0x13C)
> -#define SPR_LPIDR (0x13D)
> +#define SPR_MMCRH (0x13C)
> #define SPR_DABR2 (0x13D)
> #define SPR_BOOKE_DAC2 (0x13D)
> +#define SPR_TFMR (0x13D)
> #define SPR_BOOKE_DVC1 (0x13E)
> #define SPR_LPCR (0x13E)
> #define SPR_BOOKE_DVC2 (0x13F)
> +#define SPR_LPIDR (0x13F)
> #define SPR_BOOKE_TSR (0x150)
> +#define SPR_HMER (0x150)
> +#define SPR_HMEER (0x151)
> #define SPR_PCR (0x152)
> +#define SPR_BOOKE_LPIDR (0x152)
> #define SPR_BOOKE_TCR (0x154)
> #define SPR_BOOKE_TLB0PS (0x158)
> #define SPR_BOOKE_TLB1PS (0x159)
> #define SPR_BOOKE_TLB2PS (0x15A)
> #define SPR_BOOKE_TLB3PS (0x15B)
> +#define SPR_AMOR (0x15D)
> #define SPR_BOOKE_MAS7_MAS3 (0x174)
> #define SPR_BOOKE_IVOR0 (0x190)
> #define SPR_BOOKE_IVOR1 (0x191)
> @@ -1667,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_RCPU_L2U_RA3 (0x32B)
> #define SPR_TAR (0x32F)
> #define SPR_VTB (0x351)
> +#define SPR_MMCRC (0x353)
> #define SPR_440_INV0 (0x370)
> #define SPR_440_INV1 (0x371)
> #define SPR_440_INV2 (0x372)
> @@ -1705,6 +1724,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_440_DVLIM (0x398)
> #define SPR_750_WPAR (0x399)
> #define SPR_440_IVLIM (0x399)
> +#define SPR_TSCR (0x399)
> #define SPR_750_DMAU (0x39A)
> #define SPR_750_DMAL (0x39B)
> #define SPR_440_RSTCFG (0x39B)
> @@ -1879,9 +1899,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
>
> /* HID0 bits */
> -#define HID0_DEEPNAP (1 << 24)
> -#define HID0_DOZE (1 << 23)
> -#define HID0_NAP (1 << 22)
> +#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
> +#define HID0_DOZE (1 << 23) /* pre-2.06 */
> +#define HID0_NAP (1 << 22) /* pre-2.06 */
> +#define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
>
> /*****************************************************************************/
> /* PowerPC Instructions types definitions */
> @@ -2230,6 +2251,25 @@ enum {
> PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
> };
>
> +/* HMER/HMEER */
> +enum {
> + HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
> + HMER_PROC_RECV_DONE = 1ull << (63 - 2),
> + HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
> + HMER_TFAC_ERROR = 1ull << (63 - 4),
> + HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
> + HMER_XSCOM_FAIL = 1ull << (63 - 8),
> + HMER_XSCOM_DONE = 1ull << (63 - 9),
> + HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
> + HMER_WARN_RISE = 1ull << (63 - 14),
> + HMER_WARN_FALL = 1ull << (63 - 15),
> + HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
> + HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
> + HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
> + HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
> + HMER_XSCOM_STATUS_LSH = (63 - 23),
> +};
> +
> /*****************************************************************************/
>
> static inline target_ulong cpu_read_xer(CPUPPCState *env)
>
Some of the definitions (MMCRH, MMCRC, TFMR, TSCR, HID0_HILE and most of
the HMER bits) are unfortunately not listed in the PowerISA spec, but
the definitions here match the definitions from the Linux kernel and/or
skiboot, so I assume they are OK. So:
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs
2016-03-14 16:56 ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Cédric Le Goater
@ 2016-03-14 18:50 ` Thomas Huth
0 siblings, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 18:50 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The current set of spr_register_* macros only take the user and
> supervisor function pointers. To make the transition easy, we
> don't change that but we add "_hv" variants that can be used to
> register all 3 sets.
>
> To simplify the transition, users of the "old" macro will set the
> hypervisor callback to be the same as the supervisor one. The new
> registration function only needs to be used for registers that are
> either hypervisor only or behave differently in HV mode.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target-ppc/translate.c | 26 ++++++++++++++++----------
> target-ppc/translate_init.c | 35 +++++++++++++++++++++++++++++++----
> 2 files changed, 47 insertions(+), 14 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index e402ff920314..327f3259b4be 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -4282,14 +4282,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
> void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
> uint32_t sprn = SPR(ctx->opcode);
>
> -#if !defined(CONFIG_USER_ONLY)
> - if (ctx->hv)
> +#if defined(CONFIG_USER_ONLY)
> + read_cb = ctx->spr_cb[sprn].uea_read;
> +#else
> + if (ctx->pr) {
> + read_cb = ctx->spr_cb[sprn].uea_read;
> + } else if (ctx->hv) {
> read_cb = ctx->spr_cb[sprn].hea_read;
> - else if (!ctx->pr)
> + } else if (!ctx->pr) {
That check for !ctx->pr is now superfluous, isn't it? ... because it has
already been checked 4 lines earlier.
> read_cb = ctx->spr_cb[sprn].oea_read;
> - else
> + }
> #endif
> - read_cb = ctx->spr_cb[sprn].uea_read;
> if (likely(read_cb != NULL)) {
> if (likely(read_cb != SPR_NOACCESS)) {
> (*read_cb)(ctx, rD(ctx->opcode), sprn);
> @@ -4437,14 +4440,17 @@ static void gen_mtspr(DisasContext *ctx)
> void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
> uint32_t sprn = SPR(ctx->opcode);
>
> -#if !defined(CONFIG_USER_ONLY)
> - if (ctx->hv)
> +#if defined(CONFIG_USER_ONLY)
> + write_cb = ctx->spr_cb[sprn].uea_write;
> +#else
> + if (ctx->pr) {
> + write_cb = ctx->spr_cb[sprn].uea_write;
> + } else if (ctx->hv) {
> write_cb = ctx->spr_cb[sprn].hea_write;
> - else if (!ctx->pr)
> + } else {
Here it is right already :-)
> write_cb = ctx->spr_cb[sprn].oea_write;
> - else
> + }
> #endif
> - write_cb = ctx->spr_cb[sprn].uea_write;
> if (likely(write_cb != NULL)) {
> if (likely(write_cb != SPR_NOACCESS)) {
> (*write_cb)(ctx, sprn, rS(ctx->opcode));
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index fb206aff29ad..6a11b41206e5 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -579,17 +579,33 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
> #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, one_reg_id, initial_value) \
> _spr_register(env, num, name, uea_read, uea_write, initial_value)
> +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, hea_read, hea_write, \
> + one_reg_id, initial_value) \
> + _spr_register(env, num, name, uea_read, uea_write, initial_value)
> #else
> #if !defined(CONFIG_KVM)
> #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> - oea_read, oea_write, one_reg_id, initial_value) \
> + oea_read, oea_write, one_reg_id, initial_value) \
> + _spr_register(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, oea_read, oea_write, initial_value)
> +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, hea_read, hea_write, \
> + one_reg_id, initial_value) \
> _spr_register(env, num, name, uea_read, uea_write, \
> - oea_read, oea_write, initial_value)
> + oea_read, oea_write, hea_read, hea_write, initial_value)
> #else
> #define spr_register_kvm(env, num, name, uea_read, uea_write, \
> - oea_read, oea_write, one_reg_id, initial_value) \
> + oea_read, oea_write, one_reg_id, initial_value) \
> + _spr_register(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, oea_read, oea_write, \
> + one_reg_id, initial_value)
> +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, hea_read, hea_write, \
> + one_reg_id, initial_value) \
> _spr_register(env, num, name, uea_read, uea_write, \
> - oea_read, oea_write, one_reg_id, initial_value)
> + oea_read, oea_write, hea_read, hea_write, \
> + one_reg_id, initial_value)
> #endif
> #endif
>
> @@ -598,6 +614,13 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
> spr_register_kvm(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, 0, initial_value)
>
> +#define spr_register_hv(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, hea_read, hea_write, \
> + initial_value) \
> + spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
> + oea_read, oea_write, hea_read, hea_write, \
> + 0, initial_value)
> +
> static inline void _spr_register(CPUPPCState *env, int num,
> const char *name,
> void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
> @@ -606,6 +629,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
>
> void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
> void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
> + void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
> + void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
> #endif
> #if defined(CONFIG_KVM)
> uint64_t one_reg_id,
> @@ -633,6 +658,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
> #if !defined(CONFIG_USER_ONLY)
> spr->oea_read = oea_read;
> spr->oea_write = oea_write;
> + spr->hea_read = hea_read;
> + spr->hea_write = hea_write;
> #endif
> #if defined(CONFIG_KVM)
> spr->one_reg_id = one_reg_id,
Apart from the one superfluous if-statement, the patch looks fine to me.
Thomas
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
@ 2016-03-14 19:14 ` Thomas Huth
2016-03-15 9:43 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 19:14 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We don't give them a KVM reg number to most of the registers yet as no
> current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
> number is needed since this register can be set by the guest via the
> H_SET_MODE hypercall.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
> changed the commit log with a proposal of Thomas Huth ]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> ---
> target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 137 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 6a11b41206e5..43c6e524a6bc 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_UAMOR, 0);
> + spr_register_hv(env, SPR_AMOR, "AMOR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> #endif /* !CONFIG_USER_ONLY */
> }
> #endif /* TARGET_PPC64 */
> @@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> KVM_REG_PPC_DABRX, 0x00000000);
> }
>
> +static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> +{
> + spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_DAWR, 0x00000000);
> + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_DAWRX, 0x00000000);
> +}
> +
> static void gen_spr_970_dbg(CPUPPCState *env)
> {
> /* Breakpoints */
> @@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> spr_register_kvm(env, SPR_LPCR, "LPCR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_LPCR, 0x00000000);
> + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
Could we please postpone that hunk to a later, separate patch (after
QEMU 2.6 has been released)? It looks like it could maybe cause some
trouble with some emulated boards (e.g. there is some code in
target-ppc/excp_helper.c for example - which is currently disabled, but
I'm not sure whether there are other spots like this somewhere else).
> }
>
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv hmer = tcg_temp_new();
> +
> + gen_load_spr(hmer, sprn);
> + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
> + gen_store_spr(sprn, hmer);
> + spr_store_dump_spr(sprn);
> + tcg_temp_free(hmer);
> +}
> +#endif
> +
> static void gen_spr_book3s_ids(CPUPPCState *env)
> {
> + /* FIXME: Will need to deal with thread vs core only SPRs */
> +
> /* Processor identification */
> - spr_register(env, SPR_PIR, "PIR",
> + spr_register_hv(env, SPR_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_pir,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, NULL,
> + 0x00000000);
What does the NULL mean here? I haven't seen any other spr_register*()
calls yet that pass NULL as parameter for a handler. Should that maybe
rather be a SPR_NOACCESS instead?
Thomas
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
@ 2016-03-14 19:20 ` Thomas Huth
2016-03-15 8:06 ` Cédric Le Goater
2016-03-15 8:21 ` Bharata B Rao
2016-03-15 9:45 ` David Gibson
1 sibling, 2 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 19:20 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel, Bharata B Rao
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
> are offset by that value in order to preserve consistency with the
> HW implementations.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/cpu-qom.h | 1 +
> target-ppc/translate_init.c | 11 ++++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
> index 7d5e2b36a997..735981309c5b 100644
> --- a/target-ppc/cpu-qom.h
> +++ b/target-ppc/cpu-qom.h
> @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
> uint32_t flags;
> int bfd_mach;
> uint32_t l1_dcache_size, l1_icache_size;
> + uint32_t threads_per_core;
> #if defined(TARGET_PPC64)
> const struct ppc_segment_page_sizes *sps;
> #endif
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 43c6e524a6bc..46dabe58783a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> POWERPC_FLAG_BUS_CLK;
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x10000;
> + pcc->threads_per_core = 2;
> }
>
> static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
> @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> + pcc->threads_per_core = 4;
> }
>
> static void init_proc_POWER8(CPUPPCState *env)
> @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> + pcc->threads_per_core = 8;
> }
> #endif /* defined (TARGET_PPC64) */
>
> @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> #endif
>
> #if !defined(CONFIG_USER_ONLY)
> + if (pcc->threads_per_core == 0) {
> + pcc->threads_per_core = 1;
> + }
> + if (max_smt > pcc->threads_per_core) {
> + max_smt = pcc->threads_per_core;
> + }
> if (smp_threads > max_smt) {
> error_setg(errp, "Cannot support more than %d threads on PPC with %s",
> max_smt, kvm_enabled() ? "KVM" : "TCG");
> @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> }
>
> #if !defined(CONFIG_USER_ONLY)
> - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
> + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core
> + (cs->cpu_index % smp_threads);
> #endif
That looks like it could collide with Bharata's CPU hotplug series ...
Bharata,
what do you think?
Anyway, I don't see where this is really required for the SPR
definitions ... Cédric, could you also do it without this patch
for now?
Thomas
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
@ 2016-03-14 19:29 ` Thomas Huth
2016-03-15 9:47 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 19:29 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This helper is only used by the various instructions that can alter
> MSR and not interrupts. Add a comment to that effect to the interrupt
> code as well in case somebody wants to change this
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target-ppc/excp_helper.c | 8 ++++++--
> target-ppc/helper_regs.h | 4 ++--
> 2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index c890853d861b..37d4721db63b 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -666,8 +666,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> }
> }
> #endif
> - /* XXX: we don't use hreg_store_msr here as already have treated
> - * any special case that could occur. Just store MSR and update hflags
> + /* We don't use hreg_store_msr here as already have treated
> + * any special case that could occur. Just store MSR and update hflags
> + *
> + * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
> + * will prevent setting of the HV bit which some exceptions might need
> + * to do.
> */
> env->msr = new_msr & env->msr_mask;
> hreg_compute_hflags(env);
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index 271fddf17f0a..844240d1a755 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -75,8 +75,8 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> excp = 0;
> value &= env->msr_mask;
> #if !defined(CONFIG_USER_ONLY)
> - if (!alter_hv) {
> - /* mtmsr cannot alter the hypervisor state */
> + /* Neither mtmsr nor guest state can alter HV */
> + if (!alter_hv || !(env->msr & MSR_HVB)) {
> value &= ~MSR_HVB;
> value |= env->msr & MSR_HVB;
> }
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
@ 2016-03-14 19:32 ` Thomas Huth
2016-03-16 1:06 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 19:32 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We still need to eventually implement doorbells but at least this
> makes us not crash when the SPRs are accessed.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/cpu.h | 2 ++
> target-ppc/translate_init.c | 17 +++++++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 02aed6427ade..779cb57bd700 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1394,6 +1394,8 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_MPC_ICTRL (0x09E)
> #define SPR_MPC_BAR (0x09F)
> #define SPR_PSPB (0x09F)
> +#define SPR_DHDES (0x0B1)
> +#define SPR_DPDES (0x0B0)
> #define SPR_DAWR (0x0B4)
> #define SPR_RPR (0x0BA)
> #define SPR_DAWRX (0x0BC)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 59a68de0bce8..7a399b97bc6f 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8036,6 +8036,22 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_dbell(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_hv(env, SPR_DPDES, "DPDES",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> + spr_register_hv(env, SPR_DHDES, "DHDES",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> +#endif
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -8089,6 +8105,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_power8_pspb(env);
> gen_spr_vtb(env);
> gen_spr_power8_rpr(env);
> + gen_spr_power8_dbell(env);
> }
> if (version < BOOK3S_CPU_POWER8) {
> gen_spr_book3s_dbg(env);
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
@ 2016-03-14 19:37 ` Thomas Huth
2016-03-16 1:07 ` David Gibson
2016-03-16 1:07 ` David Gibson
1 sibling, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 19:37 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Those are HV writeable, so we provide a dummy write. We eventually need
> to provide a better emulation but for now this will get us going.
>
> We also make them non-user readable as per the architecture.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/translate_init.c | 25 +++++++++++++++++--------
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 7a399b97bc6f..10f67136b609 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -293,6 +293,13 @@ static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
> {
> gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> }
> +
> +__attribute__ ((unused))
> +static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
> +{
> + /* Temporary placeholder */
> +}
What's the "__attribute__ ((unused))" needed here for? The function is
referenced below, so it should be "used"?
Or is this simply about handling the CONFIG_USER_ONLY case? Then I think
it would be nicer to change the #ifdef in front of it to include
"!defined(CONFIG_USER_ONLY)", too.
Thomas
> #endif
> #endif
>
> @@ -7828,14 +7835,16 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> - spr_register_kvm(env, SPR_PURR, "PURR",
> - &spr_read_purr, SPR_NOACCESS,
> - &spr_read_purr, SPR_NOACCESS,
> - KVM_REG_PPC_PURR, 0x00000000);
> - spr_register_kvm(env, SPR_SPURR, "SPURR",
> - &spr_read_purr, SPR_NOACCESS,
> - &spr_read_purr, SPR_NOACCESS,
> - KVM_REG_PPC_SPURR, 0x00000000);
> + spr_register_kvm_hv(env, SPR_PURR, "PURR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_purr, SPR_NOACCESS,
> + &spr_read_purr, &spr_write_purr,
> + KVM_REG_PPC_PURR, 0x00000000);
> + spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_purr, SPR_NOACCESS,
> + &spr_read_purr, &spr_write_purr,
> + KVM_REG_PPC_SPURR, 0x00000000);
> #endif
> }
>
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
@ 2016-03-14 19:40 ` Thomas Huth
2016-03-16 1:08 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 19:40 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> It's supposed to be an instruction counter. For now make us not
> crash when accessing it.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 12 ++++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 779cb57bd700..6952d789e518 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1691,6 +1691,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_MPC_MD_DBRAM1 (0x32A)
> #define SPR_RCPU_L2U_RA3 (0x32B)
> #define SPR_TAR (0x32F)
> +#define SPR_IC (0x350)
> #define SPR_VTB (0x351)
> #define SPR_MMCRC (0x353)
> #define SPR_440_INV0 (0x370)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 10f67136b609..68abd847a251 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8061,6 +8061,17 @@ static void gen_spr_power8_dbell(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_ic(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_hv(env, SPR_IC, "IC",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> +#endif
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -8115,6 +8126,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_vtb(env);
> gen_spr_power8_rpr(env);
> gen_spr_power8_dbell(env);
> + gen_spr_power8_ic(env);
> }
> if (version < BOOK3S_CPU_POWER8) {
> gen_spr_book3s_dbg(env);
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
@ 2016-03-14 20:00 ` Thomas Huth
2016-03-16 1:14 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 20:00 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We should implement HW breakpoint/watchpoint, qemu supports them...
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 5203cc6a3bfb..9e1ef10b7dc6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_DAWR (0x0B4)
> #define SPR_MPPR (0x0B8)
> #define SPR_RPR (0x0BA)
> +#define SPR_CIABR (0x0BB)
> #define SPR_DAWRX (0x0BC)
> #define SPR_HFSCR (0x0BE)
> #define SPR_VRSAVE (0x100)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index cfb1bc088950..f88bdf7b3cd1 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_DAWRX, 0x00000000);
> + spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_CIABR, 0x00000000);
> }
>
> static void gen_spr_970_dbg(CPUPPCState *env)
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
@ 2016-03-14 20:08 ` Thomas Huth
2016-03-16 1:15 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 20:08 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> ---
> target-ppc/cpu.h | 3 +++
> target-ppc/translate_init.c | 12 ++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 9e1ef10b7dc6..9ed406cf111b 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1359,7 +1359,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_SRR1 (0x01B)
> #define SPR_CFAR (0x01C)
> #define SPR_AMR (0x01D)
> +#define SPR_ACOP (0x01F)
> #define SPR_BOOKE_PID (0x030)
> +#define SPR_BOOKS_PID (0x030)
> #define SPR_BOOKE_DECAR (0x036)
> #define SPR_BOOKE_CSRR0 (0x03A)
> #define SPR_BOOKE_CSRR1 (0x03B)
> @@ -1713,6 +1715,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_POWER_SPMC1 (0x37C)
> #define SPR_POWER_SPMC2 (0x37D)
> #define SPR_POWER_MMCRS (0x37E)
> +#define SPR_WORT (0x37F)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f88bdf7b3cd1..22afeef2731a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8175,6 +8175,18 @@ static void gen_spr_power8_book4(CPUPPCState *env)
> &spr_read_generic, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0);
> + spr_register_kvm(env, SPR_ACOP, "ACOP",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_ACOP, 0);
> + spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PID, 0);
> + spr_register_kvm(env, SPR_WORT, "WORT",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_WORT, 0);
> #endif
> }
Register numbers match the ones from the header
arch/powerpc/include/asm/reg.h in the linux kernel sources, so I assume
the SPR numbers are correct. So:
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
@ 2016-03-14 20:13 ` Thomas Huth
2016-03-16 1:09 ` David Gibson
2016-03-17 2:36 ` David Gibson
2 siblings, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 20:13 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Make sure we give the guest full authorization
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/translate_init.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 68abd847a251..c921d9f53984 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8542,6 +8542,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
> + ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
>
> /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> * MSR[IP] should never be set.
> @@ -8563,6 +8564,9 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
> */
> env->spr[SPR_LPCR] = lpcr->default_value;
>
> + /* Set a full AMOR so guest can use the AMR as it sees fit */
> + env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
> +
> /* Tell KVM that we're in PAPR mode */
> if (kvm_enabled()) {
> kvmppc_set_papr(cpu);
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
@ 2016-03-14 20:26 ` Thomas Huth
2016-03-15 8:05 ` Cédric Le Goater
0 siblings, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 20:26 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The masks weren't chosen nor applied properly. The architecture specifies
> that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0.
>
> The writes to UAMOR are masked by AMOR for HV=0
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: fixed gen_spr_amr() call in init_proc_book3s_64()]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> ---
> target-ppc/translate_init.c | 78 +++++++++++++++++++++++++++++++++++----------
> 1 file changed, 61 insertions(+), 17 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index c921d9f53984..f2eb5f041ecd 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -1070,30 +1070,72 @@ static void gen_spr_7xx (CPUPPCState *env)
>
> #ifdef TARGET_PPC64
> #ifndef CONFIG_USER_ONLY
> -static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn)
> +static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
> {
> - gen_load_spr(cpu_gpr[gprn], SPR_AMR);
> - spr_load_dump_spr(SPR_AMR);
> -}
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
>
> -static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
> + /* Note, the HV=1 PR=0 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + if (ctx->pr) {
> + gen_load_spr(t1, SPR_UAMOR);
> + } else {
> + gen_load_spr(t1, SPR_AMOR);
> + }
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_AMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_AMR, t0);
> spr_store_dump_spr(SPR_AMR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> }
>
> -static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn)
> +static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
> {
> TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /* Note, the HV=1 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
>
> + /* Build insertion mask into t1 based on context */
> + gen_load_spr(t1, SPR_AMOR);
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> gen_load_spr(t0, SPR_UAMOR);
> - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> - gen_store_spr(SPR_AMR, t0);
> - spr_store_dump_spr(SPR_AMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_UAMOR, t0);
> + spr_store_dump_spr(SPR_UAMOR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> }
> #endif /* CONFIG_USER_ONLY */
>
> -static void gen_spr_amr (CPUPPCState *env)
> +static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
> {
> #ifndef CONFIG_USER_ONLY
> /* Virtual Page Class Key protection */
> @@ -1101,15 +1143,17 @@ static void gen_spr_amr (CPUPPCState *env)
> * userspace accessible, 29 is privileged. So we only need to set
> * the kvm ONE_REG id on one of them, we use 29 */
> spr_register(env, SPR_UAMR, "UAMR",
> - &spr_read_uamr, &spr_write_uamr_pr,
> - &spr_read_uamr, &spr_write_uamr,
> + &spr_read_generic, &spr_write_amr,
> + &spr_read_generic, &spr_write_amr,
> 0);
> - spr_register_kvm(env, SPR_AMR, "AMR",
> + spr_register_kvm_hv(env, SPR_AMR, "AMR",
> SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_amr,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_AMR, 0);
> - spr_register_kvm(env, SPR_UAMOR, "UAMOR",
> + spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
> SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_uamor,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_UAMOR, 0);
> spr_register_hv(env, SPR_AMOR, "AMOR",
> @@ -8093,7 +8137,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> case BOOK3S_CPU_POWER7:
> case BOOK3S_CPU_POWER8:
> gen_spr_book3s_ids(env);
> - gen_spr_amr(env);
> + gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
> gen_spr_book3s_purr(env);
> env->ci_large_pages = true;
> break;
I think this last hunk (and thus the "has_iamr" parameter of that
function) rather belong to the next patch, since it is not used here yet.
Apart from that, the patch looks fine to me.
Thomas
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
@ 2016-03-14 20:36 ` Thomas Huth
0 siblings, 0 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 20:36 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> With appropriate AMR-like masks. Not actually used by the translation
> logic at that point
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: add the use of spr_register_kvm_hv()]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 38 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 39 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 6952d789e518..81a3e6b5ed29 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1364,6 +1364,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_BOOKE_CSRR0 (0x03A)
> #define SPR_BOOKE_CSRR1 (0x03B)
> #define SPR_BOOKE_DEAR (0x03D)
> +#define SPR_IAMR (0x03D)
> #define SPR_BOOKE_ESR (0x03E)
> #define SPR_BOOKE_IVPR (0x03F)
> #define SPR_MPC_EIE (0x050)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f2eb5f041ecd..2fac6ea58698 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -1133,6 +1133,36 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
> tcg_temp_free(t1);
> tcg_temp_free(t2);
> }
> +
> +static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /* Note, the HV=1 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + gen_load_spr(t1, SPR_AMOR);
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_IAMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_IAMR, t0);
> + spr_store_dump_spr(SPR_IAMR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> #endif /* CONFIG_USER_ONLY */
>
> static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
> @@ -1161,6 +1191,14 @@ static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0);
> + if (!has_iamr) {
> + return;
> + }
> + spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_iamr,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_IAMR, 0);
In case you rework this patch (e.g. by putting the has_iamr parameter
from the last patch in here), I think I'd also rather write this as:
if (has_iamr) {
spr_register_kvm_hv(...
}
That would be slightly easier to read.
Apart from that, the patch looks fine to me.
Thomas
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
@ 2016-03-14 20:54 ` Thomas Huth
2016-03-14 21:07 ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-03-16 1:12 ` [Qemu-devel] " David Gibson
1 sibling, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-14 20:54 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The Hypervisor can write it. We don't handle that properly yet but
> at least let's not blow up when it is written.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/translate_init.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 2fac6ea58698..28a9c2e73156 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -300,6 +300,12 @@ static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
> /* Temporary placeholder */
> }
>
> +__attribute__ ((unused))
> +static void spr_write_vtb(DisasContext *ctx, int gprn, int sprn)
> +{
> + /* Temporary placeholder */
> +}
Why "__attribute__ ((unused))" here (again)?
> #endif
> #endif
>
> @@ -8089,10 +8095,11 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
> /* Virtual Time Base */
> static void gen_spr_vtb(CPUPPCState *env)
> {
> - spr_register(env, SPR_VTB, "VTB",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_tbl, SPR_NOACCESS,
> - 0x00000000);
> + spr_register_hv(env, SPR_VTB, "VTB",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_tbl, SPR_NOACCESS,
> + &spr_read_tbl, spr_write_vtb,
> + 0x00000000);
> }
I think it would also be possible to use spr_access_nop() for now
instead of introducing more dummy functions like spr_write_vtb.
Thomas
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 14/17] ppc: Add dummy write to VTB
2016-03-14 20:54 ` Thomas Huth
@ 2016-03-14 21:07 ` Benjamin Herrenschmidt
0 siblings, 0 replies; 69+ messages in thread
From: Benjamin Herrenschmidt @ 2016-03-14 21:07 UTC (permalink / raw)
To: Thomas Huth, Cédric Le Goater, David Gibson; +Cc: qemu-ppc, qemu-devel
On Mon, 2016-03-14 at 21:54 +0100, Thomas Huth wrote:
> I think it would also be possible to use spr_access_nop() for now
> instead of introducing more dummy functions like spr_write_vtb.
Well, the goal was to eventually put some real code in there...
Cheers,
Ben.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
` (16 preceding siblings ...)
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
@ 2016-03-15 0:39 ` David Gibson
2016-03-15 8:11 ` Cédric Le Goater
17 siblings, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-15 0:39 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2551 bytes --]
On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
> Hello,
>
> This is a first mini-serie of patches adding support for new ppc SPRs.
> They were taken from Ben's larger patchset adding the ppc powernv
> platform and they should already be useful for the pseries guest
> migration.
>
> Initial patches come from :
>
> https://github.com/ozbenh/qemu/commits/powernv
>
> The changes are mostly due to the rebase on Dave's 2.6 branch:
>
> https://github.com/dgibson/qemu/commits/ppc-for-2.6
>
> A couple more are bisect and checkpatch fixes and finally some patches
> were merge to reduce the noise.
>
>
>
> The patchset is also available here:
>
> https://github.com/legoater/qemu/commits/for-2.6
>
> It was quickly tested with a pseries guest using KVM and TCG.
Hmm.. do these all fix bugs with migration, or only some of them?
The relevance is that things to fix migration should go into 2.6, but
preparation work for powernv that doesn't fix bug shouldn't really be
going in now, after the soft freeze and will need to wait for 2.7.
>
> Thanks,
>
> C.
>
>
> Benjamin Herrenschmidt (17):
> ppc: Update SPR definitions
> ppc: Add macros to register hypervisor mode SPRs
> ppc: Add a bunch of hypervisor SPRs to Book3s
> ppc: Add number of threads per core to the processor definition
> ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
> ppc: Create cpu_ppc_set_papr() helper
> ppc: Better figure out if processor has HV mode
> ppc: Add placeholder SPRs for DPDES and DHDES on P8
> ppc: SPURR & PURR are HV writeable and privileged
> ppc: Add dummy SPR_IC for POWER8
> ppc: Initialize AMOR in PAPR mode
> ppc: Fix writing to AMR/UAMOR
> ppc: Add POWER8 IAMR register
> ppc: Add dummy write to VTB
> ppc: Add dummy POWER8 MPPR register
> ppc: Add dummy CIABR SPR
> ppc: A couple more dummy POWER8 Book4 regs
>
> hw/ppc/spapr.c | 11 +-
> target-ppc/cpu-qom.h | 1 +
> target-ppc/cpu.h | 68 ++++++-
> target-ppc/excp_helper.c | 8 +-
> target-ppc/helper_regs.h | 4 +-
> target-ppc/translate.c | 30 +--
> target-ppc/translate_init.c | 461 ++++++++++++++++++++++++++++++++++++++++----
> 7 files changed, 510 insertions(+), 73 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR
2016-03-14 20:26 ` Thomas Huth
@ 2016-03-15 8:05 ` Cédric Le Goater
0 siblings, 0 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-15 8:05 UTC (permalink / raw)
To: Thomas Huth, David Gibson; +Cc: qemu-ppc, qemu-devel
On 03/14/2016 09:26 PM, Thomas Huth wrote:
>> > @@ -8093,7 +8137,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> > case BOOK3S_CPU_POWER7:
>> > case BOOK3S_CPU_POWER8:
>> > gen_spr_book3s_ids(env);
>> > - gen_spr_amr(env);
>> > + gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
>> > gen_spr_book3s_purr(env);
>> > env->ci_large_pages = true;
>> > break;
> I think this last hunk (and thus the "has_iamr" parameter of that
> function) rather belong to the next patch, since it is not used here yet.
Yes. I fixed a compile break but I moved the hunk in the wrong patch.
Thanks,
C.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-14 19:20 ` Thomas Huth
@ 2016-03-15 8:06 ` Cédric Le Goater
2016-03-15 8:21 ` Bharata B Rao
1 sibling, 0 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-15 8:06 UTC (permalink / raw)
To: Thomas Huth, David Gibson; +Cc: qemu-ppc, qemu-devel, Bharata B Rao
On 03/14/2016 08:20 PM, Thomas Huth wrote:
> On 14.03.2016 17:56, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
>> are offset by that value in order to preserve consistency with the
>> HW implementations.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> ---
>> target-ppc/cpu-qom.h | 1 +
>> target-ppc/translate_init.c | 11 ++++++++++-
>> 2 files changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
>> index 7d5e2b36a997..735981309c5b 100644
>> --- a/target-ppc/cpu-qom.h
>> +++ b/target-ppc/cpu-qom.h
>> @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
>> uint32_t flags;
>> int bfd_mach;
>> uint32_t l1_dcache_size, l1_icache_size;
>> + uint32_t threads_per_core;
>> #if defined(TARGET_PPC64)
>> const struct ppc_segment_page_sizes *sps;
>> #endif
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 43c6e524a6bc..46dabe58783a 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
>> POWERPC_FLAG_BUS_CLK;
>> pcc->l1_dcache_size = 0x8000;
>> pcc->l1_icache_size = 0x10000;
>> + pcc->threads_per_core = 2;
>> }
>>
>> static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
>> @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>> pcc->l1_dcache_size = 0x8000;
>> pcc->l1_icache_size = 0x8000;
>> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>> + pcc->threads_per_core = 4;
>> }
>>
>> static void init_proc_POWER8(CPUPPCState *env)
>> @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>> pcc->l1_dcache_size = 0x8000;
>> pcc->l1_icache_size = 0x8000;
>> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>> + pcc->threads_per_core = 8;
>> }
>> #endif /* defined (TARGET_PPC64) */
>>
>> @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
>> #endif
>>
>> #if !defined(CONFIG_USER_ONLY)
>> + if (pcc->threads_per_core == 0) {
>> + pcc->threads_per_core = 1;
>> + }
>> + if (max_smt > pcc->threads_per_core) {
>> + max_smt = pcc->threads_per_core;
>> + }
>> if (smp_threads > max_smt) {
>> error_setg(errp, "Cannot support more than %d threads on PPC with %s",
>> max_smt, kvm_enabled() ? "KVM" : "TCG");
>> @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
>> }
>>
>> #if !defined(CONFIG_USER_ONLY)
>> - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
>> + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core
>> + (cs->cpu_index % smp_threads);
>> #endif
>
> That looks like it could collide with Bharata's CPU hotplug series ...
> Bharata,
> what do you think?
>
> Anyway, I don't see where this is really required for the SPR
> definitions ... Cédric, could you also do it without this patch
> for now?
Yes. Will remove.
Thanks
C.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-15 0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
@ 2016-03-15 8:11 ` Cédric Le Goater
2016-03-16 1:19 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-15 8:11 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
On 03/15/2016 01:39 AM, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
>> Hello,
>>
>> This is a first mini-serie of patches adding support for new ppc SPRs.
>> They were taken from Ben's larger patchset adding the ppc powernv
>> platform and they should already be useful for the pseries guest
>> migration.
>>
>> Initial patches come from :
>>
>> https://github.com/ozbenh/qemu/commits/powernv
>>
>> The changes are mostly due to the rebase on Dave's 2.6 branch:
>>
>> https://github.com/dgibson/qemu/commits/ppc-for-2.6
>>
>> A couple more are bisect and checkpatch fixes and finally some patches
>> were merge to reduce the noise.
>>
>>
>>
>> The patchset is also available here:
>>
>> https://github.com/legoater/qemu/commits/for-2.6
>>
>> It was quickly tested with a pseries guest using KVM and TCG.
>
> Hmm.. do these all fix bugs with migration, or only some of them?
Probably only some.
Initially, Thomas gave a shorter list which I expanded to a larger one
because of dependencies between patches and I didn't want to change too
much what Ben had sent. You had also reviewed a few.
> The relevance is that things to fix migration should go into 2.6, but
> preparation work for powernv that doesn't fix bug shouldn't really be
> going in now, after the soft freeze and will need to wait for 2.7.
OK. I will rework and keep the rest for 2.7.
Thomas, thanks for the review. I have identified a few things I need
to work on but may be, the patchset is still too large for 2.6 ?
Full list is below.
Thanks,
C.
>> Benjamin Herrenschmidt (17):
>> ppc: Update SPR definitions
>> ppc: Add macros to register hypervisor mode SPRs
>> ppc: Add a bunch of hypervisor SPRs to Book3s
>> ppc: Add number of threads per core to the processor definition
>> ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
>> ppc: Create cpu_ppc_set_papr() helper
>> ppc: Better figure out if processor has HV mode
>> ppc: Add placeholder SPRs for DPDES and DHDES on P8
>> ppc: SPURR & PURR are HV writeable and privileged
>> ppc: Add dummy SPR_IC for POWER8
>> ppc: Initialize AMOR in PAPR mode
>> ppc: Fix writing to AMR/UAMOR
>> ppc: Add POWER8 IAMR register
>> ppc: Add dummy write to VTB
>> ppc: Add dummy POWER8 MPPR register
>> ppc: Add dummy CIABR SPR
>> ppc: A couple more dummy POWER8 Book4 regs
>>
>> hw/ppc/spapr.c | 11 +-
>> target-ppc/cpu-qom.h | 1 +
>> target-ppc/cpu.h | 68 ++++++-
>> target-ppc/excp_helper.c | 8 +-
>> target-ppc/helper_regs.h | 4 +-
>> target-ppc/translate.c | 30 +--
>> target-ppc/translate_init.c | 461 ++++++++++++++++++++++++++++++++++++++++----
>> 7 files changed, 510 insertions(+), 73 deletions(-)
>>
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-14 19:20 ` Thomas Huth
2016-03-15 8:06 ` Cédric Le Goater
@ 2016-03-15 8:21 ` Bharata B Rao
1 sibling, 0 replies; 69+ messages in thread
From: Bharata B Rao @ 2016-03-15 8:21 UTC (permalink / raw)
To: Thomas Huth; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel, David Gibson
On Mon, Mar 14, 2016 at 08:20:52PM +0100, Thomas Huth wrote:
> On 14.03.2016 17:56, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
> > are offset by that value in order to preserve consistency with the
> > HW implementations.
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> > target-ppc/cpu-qom.h | 1 +
> > target-ppc/translate_init.c | 11 ++++++++++-
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
> > index 7d5e2b36a997..735981309c5b 100644
> > --- a/target-ppc/cpu-qom.h
> > +++ b/target-ppc/cpu-qom.h
> > @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
> > uint32_t flags;
> > int bfd_mach;
> > uint32_t l1_dcache_size, l1_icache_size;
> > + uint32_t threads_per_core;
> > #if defined(TARGET_PPC64)
> > const struct ppc_segment_page_sizes *sps;
> > #endif
> > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> > index 43c6e524a6bc..46dabe58783a 100644
> > --- a/target-ppc/translate_init.c
> > +++ b/target-ppc/translate_init.c
> > @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> > POWERPC_FLAG_BUS_CLK;
> > pcc->l1_dcache_size = 0x8000;
> > pcc->l1_icache_size = 0x10000;
> > + pcc->threads_per_core = 2;
> > }
> >
> > static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
> > @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> > pcc->l1_dcache_size = 0x8000;
> > pcc->l1_icache_size = 0x8000;
> > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> > + pcc->threads_per_core = 4;
> > }
> >
> > static void init_proc_POWER8(CPUPPCState *env)
> > @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> > pcc->l1_dcache_size = 0x8000;
> > pcc->l1_icache_size = 0x8000;
> > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> > + pcc->threads_per_core = 8;
> > }
> > #endif /* defined (TARGET_PPC64) */
> >
> > @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> > #endif
> >
> > #if !defined(CONFIG_USER_ONLY)
> > + if (pcc->threads_per_core == 0) {
> > + pcc->threads_per_core = 1;
> > + }
> > + if (max_smt > pcc->threads_per_core) {
I wonder when can the above condition be true. max_smt is kvmppc_smt_threads()
which returns threads_per_subcore via KVM_CAP_PPC_SMT capability call.
> > + max_smt = pcc->threads_per_core;
> > + }
> > if (smp_threads > max_smt) {
> > error_setg(errp, "Cannot support more than %d threads on PPC with %s",
> > max_smt, kvm_enabled() ? "KVM" : "TCG");
> > @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> > }
> >
> > #if !defined(CONFIG_USER_ONLY)
> > - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
> > + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core
> > + (cs->cpu_index % smp_threads);
> > #endif
>
> That looks like it could collide with Bharata's CPU hotplug series ...
> Bharata,
> what do you think?
In my last patchset, I was following the existing logic of DT id generation
to assign DT ids for spapr-cpu-core devices. Guess I will have to change
that when this patch is accepted.
Regards,
Bharata.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
2016-03-14 19:14 ` Thomas Huth
@ 2016-03-15 9:43 ` David Gibson
2016-03-15 10:49 ` Thomas Huth
0 siblings, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-15 9:43 UTC (permalink / raw)
To: Thomas Huth; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4744 bytes --]
On Mon, Mar 14, 2016 at 08:14:59PM +0100, Thomas Huth wrote:
> On 14.03.2016 17:56, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > We don't give them a KVM reg number to most of the registers yet as no
> > current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
> > number is needed since this register can be set by the guest via the
> > H_SET_MODE hypercall.
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
> > changed the commit log with a proposal of Thomas Huth ]
> > Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> > ---
> > target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 137 insertions(+), 3 deletions(-)
> >
> > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> > index 6a11b41206e5..43c6e524a6bc 100644
> > --- a/target-ppc/translate_init.c
> > +++ b/target-ppc/translate_init.c
> > @@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
> > SPR_NOACCESS, SPR_NOACCESS,
> > &spr_read_generic, &spr_write_generic,
> > KVM_REG_PPC_UAMOR, 0);
> > + spr_register_hv(env, SPR_AMOR, "AMOR",
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_generic, &spr_write_generic,
> > + 0);
> > #endif /* !CONFIG_USER_ONLY */
> > }
> > #endif /* TARGET_PPC64 */
> > @@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> > KVM_REG_PPC_DABRX, 0x00000000);
> > }
> >
> > +static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> > +{
> > + spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_generic, &spr_write_generic,
> > + KVM_REG_PPC_DAWR, 0x00000000);
> > + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_generic, &spr_write_generic,
> > + KVM_REG_PPC_DAWRX, 0x00000000);
> > +}
> > +
> > static void gen_spr_970_dbg(CPUPPCState *env)
> > {
> > /* Breakpoints */
> > @@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> > spr_register_kvm(env, SPR_LPCR, "LPCR",
> > SPR_NOACCESS, SPR_NOACCESS,
> > &spr_read_generic, &spr_write_generic,
> > - KVM_REG_PPC_LPCR, 0x00000000);
> > + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
>
> Could we please postpone that hunk to a later, separate patch (after
> QEMU 2.6 has been released)? It looks like it could maybe cause some
> trouble with some emulated boards (e.g. there is some code in
> target-ppc/excp_helper.c for example - which is currently disabled, but
> I'm not sure whether there are other spots like this somewhere else).
I think this whole patch needs to wait until after 2.6, I'm not seeing
a good rationale for squeezing it into 2.6 at this stage.
> > }
> >
> > +#if !defined(CONFIG_USER_ONLY)
> > +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
> > +{
> > + TCGv hmer = tcg_temp_new();
> > +
> > + gen_load_spr(hmer, sprn);
> > + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
> > + gen_store_spr(sprn, hmer);
> > + spr_store_dump_spr(sprn);
> > + tcg_temp_free(hmer);
> > +}
> > +#endif
> > +
> > static void gen_spr_book3s_ids(CPUPPCState *env)
> > {
> > + /* FIXME: Will need to deal with thread vs core only SPRs */
> > +
> > /* Processor identification */
> > - spr_register(env, SPR_PIR, "PIR",
> > + spr_register_hv(env, SPR_PIR, "PIR",
> > SPR_NOACCESS, SPR_NOACCESS,
> > - &spr_read_generic, &spr_write_pir,
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_generic, NULL,
> > + 0x00000000);
>
> What does the NULL mean here? I haven't seen any other spr_register*()
> calls yet that pass NULL as parameter for a handler. Should that maybe
> rather be a SPR_NOACCESS instead?
>
> Thomas
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
2016-03-14 19:20 ` Thomas Huth
@ 2016-03-15 9:45 ` David Gibson
2016-03-15 21:11 ` Benjamin Herrenschmidt
1 sibling, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-15 9:45 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3354 bytes --]
On Mon, Mar 14, 2016 at 05:56:27PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
> are offset by that value in order to preserve consistency with the
> HW implementations.
I think this can change change CPU ids, and therefore break migration
on some existing setups. So it will need some rework to apply at all,
and will certainly want to wait until after 2.6
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/cpu-qom.h | 1 +
> target-ppc/translate_init.c | 11 ++++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
> index 7d5e2b36a997..735981309c5b 100644
> --- a/target-ppc/cpu-qom.h
> +++ b/target-ppc/cpu-qom.h
> @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
> uint32_t flags;
> int bfd_mach;
> uint32_t l1_dcache_size, l1_icache_size;
> + uint32_t threads_per_core;
> #if defined(TARGET_PPC64)
> const struct ppc_segment_page_sizes *sps;
> #endif
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 43c6e524a6bc..46dabe58783a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> POWERPC_FLAG_BUS_CLK;
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x10000;
> + pcc->threads_per_core = 2;
> }
>
> static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
> @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> + pcc->threads_per_core = 4;
> }
>
> static void init_proc_POWER8(CPUPPCState *env)
> @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->l1_dcache_size = 0x8000;
> pcc->l1_icache_size = 0x8000;
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> + pcc->threads_per_core = 8;
> }
> #endif /* defined (TARGET_PPC64) */
>
> @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> #endif
>
> #if !defined(CONFIG_USER_ONLY)
> + if (pcc->threads_per_core == 0) {
> + pcc->threads_per_core = 1;
> + }
> + if (max_smt > pcc->threads_per_core) {
> + max_smt = pcc->threads_per_core;
> + }
> if (smp_threads > max_smt) {
> error_setg(errp, "Cannot support more than %d threads on PPC with %s",
> max_smt, kvm_enabled() ? "KVM" : "TCG");
> @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
> }
>
> #if !defined(CONFIG_USER_ONLY)
> - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
> + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core
> + (cs->cpu_index % smp_threads);
> #endif
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
2016-03-14 19:29 ` Thomas Huth
@ 2016-03-15 9:47 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-15 9:47 UTC (permalink / raw)
To: Thomas Huth; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2592 bytes --]
On Mon, Mar 14, 2016 at 08:29:10PM +0100, Thomas Huth wrote:
> On 14.03.2016 17:56, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > This helper is only used by the various instructions that can alter
> > MSR and not interrupts. Add a comment to that effect to the interrupt
> > code as well in case somebody wants to change this
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > target-ppc/excp_helper.c | 8 ++++++--
> > target-ppc/helper_regs.h | 4 ++--
> > 2 files changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> > index c890853d861b..37d4721db63b 100644
> > --- a/target-ppc/excp_helper.c
> > +++ b/target-ppc/excp_helper.c
> > @@ -666,8 +666,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> > }
> > }
> > #endif
> > - /* XXX: we don't use hreg_store_msr here as already have treated
> > - * any special case that could occur. Just store MSR and update hflags
> > + /* We don't use hreg_store_msr here as already have treated
> > + * any special case that could occur. Just store MSR and update hflags
> > + *
> > + * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
> > + * will prevent setting of the HV bit which some exceptions might need
> > + * to do.
> > */
> > env->msr = new_msr & env->msr_mask;
> > hreg_compute_hflags(env);
> > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> > index 271fddf17f0a..844240d1a755 100644
> > --- a/target-ppc/helper_regs.h
> > +++ b/target-ppc/helper_regs.h
> > @@ -75,8 +75,8 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> > excp = 0;
> > value &= env->msr_mask;
> > #if !defined(CONFIG_USER_ONLY)
> > - if (!alter_hv) {
> > - /* mtmsr cannot alter the hypervisor state */
> > + /* Neither mtmsr nor guest state can alter HV */
> > + if (!alter_hv || !(env->msr & MSR_HVB)) {
> > value &= ~MSR_HVB;
> > value |= env->msr & MSR_HVB;
> > }
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
This looks correct, but I'm not seeing a strong case for including it
before 2.6.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
2016-03-15 9:43 ` David Gibson
@ 2016-03-15 10:49 ` Thomas Huth
2016-03-15 17:04 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-03-16 1:04 ` [Qemu-devel] " David Gibson
0 siblings, 2 replies; 69+ messages in thread
From: Thomas Huth @ 2016-03-15 10:49 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3991 bytes --]
On 15.03.2016 10:43, David Gibson wrote:
>
> On Mon, Mar 14, 2016 at 08:14:59PM +0100, Thomas Huth wrote:
>> On 14.03.2016 17:56, Cédric Le Goater wrote:
>>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>
>>> We don't give them a KVM reg number to most of the registers yet as no
>>> current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
>>> number is needed since this register can be set by the guest via the
>>> H_SET_MODE hypercall.
>>>
>>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>> [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
>>> changed the commit log with a proposal of Thomas Huth ]
>>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
>>> ---
>>> target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 137 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>> index 6a11b41206e5..43c6e524a6bc 100644
>>> --- a/target-ppc/translate_init.c
>>> +++ b/target-ppc/translate_init.c
>>> @@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
>>> SPR_NOACCESS, SPR_NOACCESS,
>>> &spr_read_generic, &spr_write_generic,
>>> KVM_REG_PPC_UAMOR, 0);
>>> + spr_register_hv(env, SPR_AMOR, "AMOR",
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + &spr_read_generic, &spr_write_generic,
>>> + 0);
>>> #endif /* !CONFIG_USER_ONLY */
>>> }
>>> #endif /* TARGET_PPC64 */
>>> @@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
>>> KVM_REG_PPC_DABRX, 0x00000000);
>>> }
>>>
>>> +static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>>> +{
>>> + spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + &spr_read_generic, &spr_write_generic,
>>> + KVM_REG_PPC_DAWR, 0x00000000);
>>> + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + &spr_read_generic, &spr_write_generic,
>>> + KVM_REG_PPC_DAWRX, 0x00000000);
>>> +}
>>> +
>>> static void gen_spr_970_dbg(CPUPPCState *env)
>>> {
>>> /* Breakpoints */
>>> @@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
>>> spr_register_kvm(env, SPR_LPCR, "LPCR",
>>> SPR_NOACCESS, SPR_NOACCESS,
>>> &spr_read_generic, &spr_write_generic,
>>> - KVM_REG_PPC_LPCR, 0x00000000);
>>> + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
>>
>> Could we please postpone that hunk to a later, separate patch (after
>> QEMU 2.6 has been released)? It looks like it could maybe cause some
>> trouble with some emulated boards (e.g. there is some code in
>> target-ppc/excp_helper.c for example - which is currently disabled, but
>> I'm not sure whether there are other spots like this somewhere else).
>
> I think this whole patch needs to wait until after 2.6, I'm not seeing
> a good rationale for squeezing it into 2.6 at this stage.
Well, this patch registers DAWR and DAWRX registers with KVM - so
without this patch, the hardware breakpoints will be lost during
migration. I haven't tested it, but I think that when somebody uses
hardware breakpoints in gdb in a KVM guest, and migrates it, then the
breakpoints won't be triggered anymore after migration without this patch.
Cédric, maybe you could send a patch that adds at least the DAWR and
DAWRX registers if David does not want to have the full patch for 2.6?
Thomas
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
2016-03-15 10:49 ` Thomas Huth
@ 2016-03-15 17:04 ` Cédric Le Goater
2016-03-16 1:04 ` [Qemu-devel] " David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-15 17:04 UTC (permalink / raw)
To: Thomas Huth, David Gibson; +Cc: qemu-ppc, qemu-devel
On 03/15/2016 11:49 AM, Thomas Huth wrote:
> On 15.03.2016 10:43, David Gibson wrote:
>>
>> On Mon, Mar 14, 2016 at 08:14:59PM +0100, Thomas Huth wrote:
>>> On 14.03.2016 17:56, Cédric Le Goater wrote:
>>>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>>
>>>> We don't give them a KVM reg number to most of the registers yet as no
>>>> current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
>>>> number is needed since this register can be set by the guest via the
>>>> H_SET_MODE hypercall.
>>>>
>>>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>> [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
>>>> changed the commit log with a proposal of Thomas Huth ]
>>>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
>>>> ---
>>>> target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 137 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>>> index 6a11b41206e5..43c6e524a6bc 100644
>>>> --- a/target-ppc/translate_init.c
>>>> +++ b/target-ppc/translate_init.c
>>>> @@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
>>>> SPR_NOACCESS, SPR_NOACCESS,
>>>> &spr_read_generic, &spr_write_generic,
>>>> KVM_REG_PPC_UAMOR, 0);
>>>> + spr_register_hv(env, SPR_AMOR, "AMOR",
>>>> + SPR_NOACCESS, SPR_NOACCESS,
>>>> + SPR_NOACCESS, SPR_NOACCESS,
>>>> + &spr_read_generic, &spr_write_generic,
>>>> + 0);
>>>> #endif /* !CONFIG_USER_ONLY */
>>>> }
>>>> #endif /* TARGET_PPC64 */
>>>> @@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
>>>> KVM_REG_PPC_DABRX, 0x00000000);
>>>> }
>>>>
>>>> +static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>>>> +{
>>>> + spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
>>>> + SPR_NOACCESS, SPR_NOACCESS,
>>>> + SPR_NOACCESS, SPR_NOACCESS,
>>>> + &spr_read_generic, &spr_write_generic,
>>>> + KVM_REG_PPC_DAWR, 0x00000000);
>>>> + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
>>>> + SPR_NOACCESS, SPR_NOACCESS,
>>>> + SPR_NOACCESS, SPR_NOACCESS,
>>>> + &spr_read_generic, &spr_write_generic,
>>>> + KVM_REG_PPC_DAWRX, 0x00000000);
>>>> +}
>>>> +
>>>> static void gen_spr_970_dbg(CPUPPCState *env)
>>>> {
>>>> /* Breakpoints */
>>>> @@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
>>>> spr_register_kvm(env, SPR_LPCR, "LPCR",
>>>> SPR_NOACCESS, SPR_NOACCESS,
>>>> &spr_read_generic, &spr_write_generic,
>>>> - KVM_REG_PPC_LPCR, 0x00000000);
>>>> + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
>>>
>>> Could we please postpone that hunk to a later, separate patch (after
>>> QEMU 2.6 has been released)? It looks like it could maybe cause some
>>> trouble with some emulated boards (e.g. there is some code in
>>> target-ppc/excp_helper.c for example - which is currently disabled, but
>>> I'm not sure whether there are other spots like this somewhere else).
>>
>> I think this whole patch needs to wait until after 2.6, I'm not seeing
>> a good rationale for squeezing it into 2.6 at this stage.
>
> Well, this patch registers DAWR and DAWRX registers with KVM - so
> without this patch, the hardware breakpoints will be lost during
> migration. I haven't tested it, but I think that when somebody uses
> hardware breakpoints in gdb in a KVM guest, and migrates it, then the
> breakpoints won't be triggered anymore after migration without this patch.
>
> Cédric, maybe you could send a patch that adds at least the DAWR and
> DAWRX registers if David does not want to have the full patch for 2.6?
yes. Here is my plan for the next patchset :
01/17 - ppc: Update SPR definitions (take)
02/17 - ppc: Add macros to register hypervisor mode SPRs (needs a fix)
03/17 - ppc: Add a bunch of hypervisor SPRs to Book3s (extract DAWR*)
04/17 - ppc: Add number of threads per core to the processor definition (drop for 2.6)
05/17 - ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV (drop for 2.6)
06/17 - ppc: Create cpu_ppc_set_papr() helper (take. needed by 11/17)
07/17 - ppc: Better figure out if processor has HV mode (take)
08/17 - ppc: Add placeholder SPRs for DPDES and DHDES on P8 (take)
09/17 - ppc: SPURR & PURR are HV writeable and privileged (drop for 2.6)
10/17 - ppc: Add dummy SPR_IC for POWER8 (take)
11/17 - ppc: Initialize AMOR in PAPR mode (take)
12/17 - ppc: Fix writing to AMR/UAMOR (move hunk to 13)
13/17 - ppc: Add POWER8 IAMR register (rework with above)
14/17 - ppc: Add dummy write to VTB (drop for 2.6)
15/17 - ppc: Add dummy POWER8 MPPR register (drop for 2.6)
16/17 - ppc: Add dummy CIABR SPR (take)
17/17 - ppc: A couple more dummy POWER8 Book4 regs (take)
C.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-15 9:45 ` David Gibson
@ 2016-03-15 21:11 ` Benjamin Herrenschmidt
2016-03-16 0:41 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Benjamin Herrenschmidt @ 2016-03-15 21:11 UTC (permalink / raw)
To: David Gibson, Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
On Tue, 2016-03-15 at 20:45 +1100, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:27PM +0100, Cédric Le Goater wrote:
> >
> > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
> > are offset by that value in order to preserve consistency with the
> > HW implementations.
> I think this can change change CPU ids, and therefore break migration
> on some existing setups. So it will need some rework to apply at
> all, and will certainly want to wait until after 2.6
Our migration is so bloody damn fragile ... grrr.
We will need it for powernv though, there are many things especially in
OPAL that rely on the consistent numbering.
In fact, it will have to go further and number the cores based on their
equivalent HW numbers at some point for SCOMs to work, which means a
slightly discontiguous numbering scheme (no core 0 for example). At
least if we want to model some of the EX XSCOMs.
Cheers,
Ben.
> >
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> > target-ppc/cpu-qom.h | 1 +
> > target-ppc/translate_init.c | 11 ++++++++++-
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
> > index 7d5e2b36a997..735981309c5b 100644
> > --- a/target-ppc/cpu-qom.h
> > +++ b/target-ppc/cpu-qom.h
> > @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
> > uint32_t flags;
> > int bfd_mach;
> > uint32_t l1_dcache_size, l1_icache_size;
> > + uint32_t threads_per_core;
> > #if defined(TARGET_PPC64)
> > const struct ppc_segment_page_sizes *sps;
> > #endif
> > diff --git a/target-ppc/translate_init.c b/target-
> > ppc/translate_init.c
> > index 43c6e524a6bc..46dabe58783a 100644
> > --- a/target-ppc/translate_init.c
> > +++ b/target-ppc/translate_init.c
> > @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void
> > *data)
> > POWERPC_FLAG_BUS_CLK;
> > pcc->l1_dcache_size = 0x8000;
> > pcc->l1_icache_size = 0x10000;
> > + pcc->threads_per_core = 2;
> > }
> >
> > static void powerpc_get_compat(Object *obj, Visitor *v, const char
> > *name,
> > @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void
> > *data)
> > pcc->l1_dcache_size = 0x8000;
> > pcc->l1_icache_size = 0x8000;
> > pcc->interrupts_big_endian =
> > ppc_cpu_interrupts_big_endian_lpcr;
> > + pcc->threads_per_core = 4;
> > }
> >
> > static void init_proc_POWER8(CPUPPCState *env)
> > @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void
> > *data)
> > pcc->l1_dcache_size = 0x8000;
> > pcc->l1_icache_size = 0x8000;
> > pcc->interrupts_big_endian =
> > ppc_cpu_interrupts_big_endian_lpcr;
> > + pcc->threads_per_core = 8;
> > }
> > #endif /* defined (TARGET_PPC64) */
> >
> > @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState
> > *dev, Error **errp)
> > #endif
> >
> > #if !defined(CONFIG_USER_ONLY)
> > + if (pcc->threads_per_core == 0) {
> > + pcc->threads_per_core = 1;
> > + }
> > + if (max_smt > pcc->threads_per_core) {
> > + max_smt = pcc->threads_per_core;
> > + }
> > if (smp_threads > max_smt) {
> > error_setg(errp, "Cannot support more than %d threads on
> > PPC with %s",
> > max_smt, kvm_enabled() ? "KVM" : "TCG");
> > @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState
> > *dev, Error **errp)
> > }
> >
> > #if !defined(CONFIG_USER_ONLY)
> > - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
> > + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc-
> > >threads_per_core
> > + (cs->cpu_index % smp_threads);
> > #endif
> >
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition
2016-03-15 21:11 ` Benjamin Herrenschmidt
@ 2016-03-16 0:41 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 0:41 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Thomas Huth, Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1843 bytes --]
On Wed, Mar 16, 2016 at 08:11:48AM +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2016-03-15 at 20:45 +1100, David Gibson wrote:
> > On Mon, Mar 14, 2016 at 05:56:27PM +0100, Cédric Le Goater wrote:
> > >
> > > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > >
> > > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
> > > are offset by that value in order to preserve consistency with the
> > > HW implementations.
>
> > I think this can change change CPU ids, and therefore break migration
> > on some existing setups. So it will need some rework to apply at
> > all, and will certainly want to wait until after 2.6
>
> Our migration is so bloody damn fragile ... grrr.
Well, yes, but that can't really be blamed for this one: you're
changing a guest visible detail.
> We will need it for powernv though, there are many things especially in
> OPAL that rely on the consistent numbering.
Right. Really it doesn't make sense to allocate the dt_id here - that
should be done in the machine type code which actually controls the
DT. That way we can change to fixed numbering for powernv (and
possibly future spapr) machine types, while leaving it the same for
existing machine types for compatibility.
> In fact, it will have to go further and number the cores based on their
> equivalent HW numbers at some point for SCOMs to work, which means a
> slightly discontiguous numbering scheme (no core 0 for example). At
> least if we want to model some of the EX XSCOMs.
Right, another argument that the machine setup code needs to be in
charge of the guest visible CPU ids.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s
2016-03-15 10:49 ` Thomas Huth
2016-03-15 17:04 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
@ 2016-03-16 1:04 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:04 UTC (permalink / raw)
To: Thomas Huth; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4596 bytes --]
On Tue, Mar 15, 2016 at 11:49:31AM +0100, Thomas Huth wrote:
> On 15.03.2016 10:43, David Gibson wrote:
> >
> > On Mon, Mar 14, 2016 at 08:14:59PM +0100, Thomas Huth wrote:
> >> On 14.03.2016 17:56, Cédric Le Goater wrote:
> >>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>>
> >>> We don't give them a KVM reg number to most of the registers yet as no
> >>> current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
> >>> number is needed since this register can be set by the guest via the
> >>> H_SET_MODE hypercall.
> >>>
> >>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>> [clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs' and
> >>> changed the commit log with a proposal of Thomas Huth ]
> >>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> >>> ---
> >>> target-ppc/translate_init.c | 140 +++++++++++++++++++++++++++++++++++++++++++-
> >>> 1 file changed, 137 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >>> index 6a11b41206e5..43c6e524a6bc 100644
> >>> --- a/target-ppc/translate_init.c
> >>> +++ b/target-ppc/translate_init.c
> >>> @@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
> >>> SPR_NOACCESS, SPR_NOACCESS,
> >>> &spr_read_generic, &spr_write_generic,
> >>> KVM_REG_PPC_UAMOR, 0);
> >>> + spr_register_hv(env, SPR_AMOR, "AMOR",
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + &spr_read_generic, &spr_write_generic,
> >>> + 0);
> >>> #endif /* !CONFIG_USER_ONLY */
> >>> }
> >>> #endif /* TARGET_PPC64 */
> >>> @@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> >>> KVM_REG_PPC_DABRX, 0x00000000);
> >>> }
> >>>
> >>> +static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> >>> +{
> >>> + spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + &spr_read_generic, &spr_write_generic,
> >>> + KVM_REG_PPC_DAWR, 0x00000000);
> >>> + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + SPR_NOACCESS, SPR_NOACCESS,
> >>> + &spr_read_generic, &spr_write_generic,
> >>> + KVM_REG_PPC_DAWRX, 0x00000000);
> >>> +}
> >>> +
> >>> static void gen_spr_970_dbg(CPUPPCState *env)
> >>> {
> >>> /* Breakpoints */
> >>> @@ -7683,15 +7702,116 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> >>> spr_register_kvm(env, SPR_LPCR, "LPCR",
> >>> SPR_NOACCESS, SPR_NOACCESS,
> >>> &spr_read_generic, &spr_write_generic,
> >>> - KVM_REG_PPC_LPCR, 0x00000000);
> >>> + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
> >>
> >> Could we please postpone that hunk to a later, separate patch (after
> >> QEMU 2.6 has been released)? It looks like it could maybe cause some
> >> trouble with some emulated boards (e.g. there is some code in
> >> target-ppc/excp_helper.c for example - which is currently disabled, but
> >> I'm not sure whether there are other spots like this somewhere else).
> >
> > I think this whole patch needs to wait until after 2.6, I'm not seeing
> > a good rationale for squeezing it into 2.6 at this stage.
>
> Well, this patch registers DAWR and DAWRX registers with KVM - so
> without this patch, the hardware breakpoints will be lost during
> migration. I haven't tested it, but I think that when somebody uses
> hardware breakpoints in gdb in a KVM guest, and migrates it, then the
> breakpoints won't be triggered anymore after migration without this patch.
Ah.. good point. So the question becomes, which is lower risk:
adjusting the patches to just add DAWR without the HV SPR stuff, or
just incorporating the HV SPR stuff as is.
> Cédric, maybe you could send a patch that adds at least the DAWR and
> DAWRX registers if David does not want to have the full patch for 2.6?
>
> Thomas
>
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
@ 2016-03-16 1:05 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:05 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4261 bytes --]
On Mon, Mar 14, 2016 at 05:56:30PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We use an env. flag which is set to the initial value of MSR_HVB in
> the msr_mask. We also adjust the POWER8 mask to set SHV.
>
> Also use this to adjust ctx.hv so that it is *set* when the processor
> doesn't have an HV mode (970 with Apple mode for example), thus enabling
> hypervisor instructions/SPRs.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Since this seems to apply purely to improving HV mode support, I'm not
yet seeing the case for including this in 2.6.
> ---
> target-ppc/cpu.h | 4 ++++
> target-ppc/translate.c | 4 +++-
> target-ppc/translate_init.c | 19 +++++++++++++++----
> 3 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index a7da0d3e95a9..02aed6427ade 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1153,6 +1153,10 @@ struct CPUPPCState {
> hwaddr mpic_iack;
> /* true when the external proxy facility mode is enabled */
> bool mpic_proxy;
> + /* set when the processor has an HV mode, thus HV priv
> + * instructions and SPRs are diallowed if MSR:HV is 0
> + */
> + bool has_hv_mode;
> #endif
>
> /* Those resources are used only during code translation */
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 327f3259b4be..11801ded62d2 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -11456,8 +11456,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
> ctx.exception = POWERPC_EXCP_NONE;
> ctx.spr_cb = env->spr_cb;
> ctx.pr = msr_pr;
> - ctx.hv = !msr_pr && msr_hv;
> ctx.mem_idx = env->mmu_idx;
> +#if !defined(CONFIG_USER_ONLY)
> + ctx.hv = msr_hv || !env->has_hv_mode;
> +#endif
> ctx.insns_flags = env->insns_flags;
> ctx.insns_flags2 = env->insns_flags2;
> ctx.access_type = -1;
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 093ef036320d..59a68de0bce8 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8463,6 +8463,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> PPC2_TM;
> pcc->msr_mask = (1ull << MSR_SF) |
> + (1ull << MSR_SHV) |
> (1ull << MSR_TM) |
> (1ull << MSR_VR) |
> (1ull << MSR_VSX) |
> @@ -9876,10 +9877,7 @@ static void ppc_cpu_reset(CPUState *s)
> pcc->parent_reset(s);
>
> msr = (target_ulong)0;
> - if (0) {
> - /* XXX: find a suitable condition to enable the hypervisor mode */
> - msr |= (target_ulong)MSR_HVB;
> - }
> + msr |= (target_ulong)MSR_HVB;
> msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
> msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
> msr |= (target_ulong)1 << MSR_EP;
> @@ -9980,6 +9978,19 @@ static void ppc_cpu_initfn(Object *obj)
> env->bfd_mach = pcc->bfd_mach;
> env->check_pow = pcc->check_pow;
>
> + /* Mark HV mode as supported if the CPU has an MSR_HV bit
> + * in the msr_mask. The mask can later be cleared by PAPR
> + * mode but the hv mode support will remain, thus enforcing
> + * that we cannot use priv. instructions in guest in PAPR
> + * mode. For 970 we currently simply don't set HV in msr_mask
> + * thus simulating an "Apple mode" 970. If we ever want to
> + * support 970 HV mode, we'll have to add a processor attribute
> + * of some sort.
> + */
> +#if !defined(CONFIG_USER_ONLY)
> + env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
> +#endif
> +
> #if defined(TARGET_PPC64)
> if (pcc->sps) {
> env->sps = *pcc->sps;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
2016-03-14 19:32 ` Thomas Huth
@ 2016-03-16 1:06 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:06 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2665 bytes --]
On Mon, Mar 14, 2016 at 05:56:31PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We still need to eventually implement doorbells but at least this
> makes us not crash when the SPRs are accessed.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
But expecting this will be for 2.7, not 2.6.
> ---
> target-ppc/cpu.h | 2 ++
> target-ppc/translate_init.c | 17 +++++++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 02aed6427ade..779cb57bd700 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1394,6 +1394,8 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_MPC_ICTRL (0x09E)
> #define SPR_MPC_BAR (0x09F)
> #define SPR_PSPB (0x09F)
> +#define SPR_DHDES (0x0B1)
> +#define SPR_DPDES (0x0B0)
> #define SPR_DAWR (0x0B4)
> #define SPR_RPR (0x0BA)
> #define SPR_DAWRX (0x0BC)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 59a68de0bce8..7a399b97bc6f 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8036,6 +8036,22 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_dbell(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_hv(env, SPR_DPDES, "DPDES",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> + spr_register_hv(env, SPR_DHDES, "DHDES",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> +#endif
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -8089,6 +8105,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_power8_pspb(env);
> gen_spr_vtb(env);
> gen_spr_power8_rpr(env);
> + gen_spr_power8_dbell(env);
> }
> if (version < BOOK3S_CPU_POWER8) {
> gen_spr_book3s_dbg(env);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
2016-03-14 19:37 ` Thomas Huth
@ 2016-03-16 1:07 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:07 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2596 bytes --]
On Mon, Mar 14, 2016 at 05:56:32PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Those are HV writeable, so we provide a dummy write. We eventually need
> to provide a better emulation but for now this will get us going.
>
> We also make them non-user readable as per the architecture.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
But expecting it for 2.7, not 2.6.
> ---
> target-ppc/translate_init.c | 25 +++++++++++++++++--------
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 7a399b97bc6f..10f67136b609 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -293,6 +293,13 @@ static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
> {
> gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> }
> +
> +__attribute__ ((unused))
> +static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
> +{
> + /* Temporary placeholder */
> +}
> +
> #endif
> #endif
>
> @@ -7828,14 +7835,16 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> - spr_register_kvm(env, SPR_PURR, "PURR",
> - &spr_read_purr, SPR_NOACCESS,
> - &spr_read_purr, SPR_NOACCESS,
> - KVM_REG_PPC_PURR, 0x00000000);
> - spr_register_kvm(env, SPR_SPURR, "SPURR",
> - &spr_read_purr, SPR_NOACCESS,
> - &spr_read_purr, SPR_NOACCESS,
> - KVM_REG_PPC_SPURR, 0x00000000);
> + spr_register_kvm_hv(env, SPR_PURR, "PURR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_purr, SPR_NOACCESS,
> + &spr_read_purr, &spr_write_purr,
> + KVM_REG_PPC_PURR, 0x00000000);
> + spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_purr, SPR_NOACCESS,
> + &spr_read_purr, &spr_write_purr,
> + KVM_REG_PPC_SPURR, 0x00000000);
> #endif
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged
2016-03-14 19:37 ` Thomas Huth
@ 2016-03-16 1:07 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:07 UTC (permalink / raw)
To: Thomas Huth; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3018 bytes --]
On Mon, Mar 14, 2016 at 08:37:59PM +0100, Thomas Huth wrote:
> On 14.03.2016 17:56, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > Those are HV writeable, so we provide a dummy write. We eventually need
> > to provide a better emulation but for now this will get us going.
> >
> > We also make them non-user readable as per the architecture.
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> > target-ppc/translate_init.c | 25 +++++++++++++++++--------
> > 1 file changed, 17 insertions(+), 8 deletions(-)
> >
> > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> > index 7a399b97bc6f..10f67136b609 100644
> > --- a/target-ppc/translate_init.c
> > +++ b/target-ppc/translate_init.c
> > @@ -293,6 +293,13 @@ static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
> > {
> > gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> > }
> > +
> > +__attribute__ ((unused))
> > +static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
> > +{
> > + /* Temporary placeholder */
> > +}
>
> What's the "__attribute__ ((unused))" needed here for? The function is
> referenced below, so it should be "used"?
> Or is this simply about handling the CONFIG_USER_ONLY case? Then I think
> it would be nicer to change the #ifdef in front of it to include
> "!defined(CONFIG_USER_ONLY)", too.
Ah, yes. I second Thomas' comment.
>
> Thomas
>
> > #endif
> > #endif
> >
> > @@ -7828,14 +7835,16 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> > {
> > #if !defined(CONFIG_USER_ONLY)
> > /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> > - spr_register_kvm(env, SPR_PURR, "PURR",
> > - &spr_read_purr, SPR_NOACCESS,
> > - &spr_read_purr, SPR_NOACCESS,
> > - KVM_REG_PPC_PURR, 0x00000000);
> > - spr_register_kvm(env, SPR_SPURR, "SPURR",
> > - &spr_read_purr, SPR_NOACCESS,
> > - &spr_read_purr, SPR_NOACCESS,
> > - KVM_REG_PPC_SPURR, 0x00000000);
> > + spr_register_kvm_hv(env, SPR_PURR, "PURR",
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_purr, SPR_NOACCESS,
> > + &spr_read_purr, &spr_write_purr,
> > + KVM_REG_PPC_PURR, 0x00000000);
> > + spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_purr, SPR_NOACCESS,
> > + &spr_read_purr, &spr_write_purr,
> > + KVM_REG_PPC_SPURR, 0x00000000);
> > #endif
> > }
> >
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
2016-03-14 19:40 ` Thomas Huth
@ 2016-03-16 1:08 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:08 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2335 bytes --]
On Mon, Mar 14, 2016 at 05:56:33PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> It's supposed to be an instruction counter. For now make us not
> crash when accessing it.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
But expecting this is for 2.7, not 2.6.
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 12 ++++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 779cb57bd700..6952d789e518 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1691,6 +1691,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_MPC_MD_DBRAM1 (0x32A)
> #define SPR_RCPU_L2U_RA3 (0x32B)
> #define SPR_TAR (0x32F)
> +#define SPR_IC (0x350)
> #define SPR_VTB (0x351)
> #define SPR_MMCRC (0x353)
> #define SPR_440_INV0 (0x370)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 10f67136b609..68abd847a251 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8061,6 +8061,17 @@ static void gen_spr_power8_dbell(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_ic(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_hv(env, SPR_IC, "IC",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> +#endif
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -8115,6 +8126,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_vtb(env);
> gen_spr_power8_rpr(env);
> gen_spr_power8_dbell(env);
> + gen_spr_power8_ic(env);
> }
> if (version < BOOK3S_CPU_POWER8) {
> gen_spr_book3s_dbg(env);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
2016-03-14 20:13 ` Thomas Huth
@ 2016-03-16 1:09 ` David Gibson
2016-03-17 2:36 ` David Gibson
2 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:09 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1594 bytes --]
On Mon, Mar 14, 2016 at 05:56:34PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Make sure we give the guest full authorization
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
I'm guessing this one is a fix that belongs in 2.6, but I'm not
entirely certain.
> ---
> target-ppc/translate_init.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 68abd847a251..c921d9f53984 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8542,6 +8542,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
> + ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
>
> /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> * MSR[IP] should never be set.
> @@ -8563,6 +8564,9 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
> */
> env->spr[SPR_LPCR] = lpcr->default_value;
>
> + /* Set a full AMOR so guest can use the AMR as it sees fit */
> + env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
> +
> /* Tell KVM that we're in PAPR mode */
> if (kvm_enabled()) {
> kvmppc_set_papr(cpu);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
2016-03-14 20:54 ` Thomas Huth
@ 2016-03-16 1:12 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:12 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1819 bytes --]
On Mon, Mar 14, 2016 at 05:56:37PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The Hypervisor can write it. We don't handle that properly yet but
> at least let's not blow up when it is written.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
AFAICT this should be for 2.7, not 2.6?
> ---
> target-ppc/translate_init.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 2fac6ea58698..28a9c2e73156 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -300,6 +300,12 @@ static void spr_write_purr(DisasContext *ctx, int gprn, int sprn)
> /* Temporary placeholder */
> }
>
> +__attribute__ ((unused))
> +static void spr_write_vtb(DisasContext *ctx, int gprn, int sprn)
> +{
> + /* Temporary placeholder */
> +}
> +
> #endif
> #endif
>
> @@ -8089,10 +8095,11 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
> /* Virtual Time Base */
> static void gen_spr_vtb(CPUPPCState *env)
> {
> - spr_register(env, SPR_VTB, "VTB",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_tbl, SPR_NOACCESS,
> - 0x00000000);
> + spr_register_hv(env, SPR_VTB, "VTB",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_tbl, SPR_NOACCESS,
> + &spr_read_tbl, spr_write_vtb,
> + 0x00000000);
> }
>
> static void gen_spr_power8_fscr(CPUPPCState *env)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
@ 2016-03-16 1:14 ` David Gibson
2016-03-16 6:17 ` Thomas Huth
0 siblings, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:14 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2537 bytes --]
On Mon, Mar 14, 2016 at 05:56:38PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Controls the micropartition prefetch, this is pretty much meaningless
> in full emulation (used for priming the caches on real HW).
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
So, this is readable with HV=0, so technically a fix even for non-HV
machines. I'm guessing it's not actually read in practice outside the
HV, though. Not sure if this should go in 2.6 or 2.7.
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 81a3e6b5ed29..5203cc6a3bfb 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1398,6 +1398,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_DHDES (0x0B1)
> #define SPR_DPDES (0x0B0)
> #define SPR_DAWR (0x0B4)
> +#define SPR_MPPR (0x0B8)
> #define SPR_RPR (0x0BA)
> #define SPR_DAWRX (0x0BC)
> #define SPR_HFSCR (0x0BE)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 28a9c2e73156..cfb1bc088950 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8161,6 +8161,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_book4(CPUPPCState *env)
> +{
> + /* Add a number of P8 book4 registers */
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_hv(env, SPR_MPPR, "MPPR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0);
> +#endif
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -8216,6 +8228,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_power8_rpr(env);
> gen_spr_power8_dbell(env);
> gen_spr_power8_ic(env);
> + gen_spr_power8_book4(env);
> }
> if (version < BOOK3S_CPU_POWER8) {
> gen_spr_book3s_dbg(env);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
2016-03-14 20:00 ` Thomas Huth
@ 2016-03-16 1:14 ` David Gibson
2016-03-16 6:24 ` Thomas Huth
1 sibling, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:14 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2028 bytes --]
On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> We should implement HW breakpoint/watchpoint, qemu supports them...
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
But I'm assuming 2.7, not 2.6.
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 5203cc6a3bfb..9e1ef10b7dc6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_DAWR (0x0B4)
> #define SPR_MPPR (0x0B8)
> #define SPR_RPR (0x0BA)
> +#define SPR_CIABR (0x0BB)
> #define SPR_DAWRX (0x0BC)
> #define SPR_HFSCR (0x0BE)
> #define SPR_VRSAVE (0x100)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index cfb1bc088950..f88bdf7b3cd1 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_DAWRX, 0x00000000);
> + spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_CIABR, 0x00000000);
> }
>
> static void gen_spr_970_dbg(CPUPPCState *env)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
2016-03-14 20:08 ` Thomas Huth
@ 2016-03-16 1:15 ` David Gibson
1 sibling, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:15 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2820 bytes --]
On Mon, Mar 14, 2016 at 05:56:40PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
And this looks like a fix for 2.6 to me.
> ---
> target-ppc/cpu.h | 3 +++
> target-ppc/translate_init.c | 12 ++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 9e1ef10b7dc6..9ed406cf111b 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1359,7 +1359,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_SRR1 (0x01B)
> #define SPR_CFAR (0x01C)
> #define SPR_AMR (0x01D)
> +#define SPR_ACOP (0x01F)
> #define SPR_BOOKE_PID (0x030)
> +#define SPR_BOOKS_PID (0x030)
> #define SPR_BOOKE_DECAR (0x036)
> #define SPR_BOOKE_CSRR0 (0x03A)
> #define SPR_BOOKE_CSRR1 (0x03B)
> @@ -1713,6 +1715,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> #define SPR_POWER_SPMC1 (0x37C)
> #define SPR_POWER_SPMC2 (0x37D)
> #define SPR_POWER_MMCRS (0x37E)
> +#define SPR_WORT (0x37F)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f88bdf7b3cd1..22afeef2731a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8175,6 +8175,18 @@ static void gen_spr_power8_book4(CPUPPCState *env)
> &spr_read_generic, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0);
> + spr_register_kvm(env, SPR_ACOP, "ACOP",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_ACOP, 0);
> + spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PID, 0);
> + spr_register_kvm(env, SPR_WORT, "WORT",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_WORT, 0);
> #endif
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-15 8:11 ` Cédric Le Goater
@ 2016-03-16 1:19 ` David Gibson
2016-03-16 9:08 ` Cédric Le Goater
0 siblings, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-16 1:19 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2469 bytes --]
On Tue, Mar 15, 2016 at 09:11:31AM +0100, Cédric Le Goater wrote:
> On 03/15/2016 01:39 AM, David Gibson wrote:
> > On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
> >> Hello,
> >>
> >> This is a first mini-serie of patches adding support for new ppc SPRs.
> >> They were taken from Ben's larger patchset adding the ppc powernv
> >> platform and they should already be useful for the pseries guest
> >> migration.
> >>
> >> Initial patches come from :
> >>
> >> https://github.com/ozbenh/qemu/commits/powernv
> >>
> >> The changes are mostly due to the rebase on Dave's 2.6 branch:
> >>
> >> https://github.com/dgibson/qemu/commits/ppc-for-2.6
> >>
> >> A couple more are bisect and checkpatch fixes and finally some patches
> >> were merge to reduce the noise.
> >>
> >>
> >>
> >> The patchset is also available here:
> >>
> >> https://github.com/legoater/qemu/commits/for-2.6
> >>
> >> It was quickly tested with a pseries guest using KVM and TCG.
> >
> > Hmm.. do these all fix bugs with migration, or only some of them?
>
> Probably only some.
>
> Initially, Thomas gave a shorter list which I expanded to a larger one
> because of dependencies between patches and I didn't want to change too
> much what Ben had sent. You had also reviewed a few.
>
> > The relevance is that things to fix migration should go into 2.6, but
> > preparation work for powernv that doesn't fix bug shouldn't really be
> > going in now, after the soft freeze and will need to wait for 2.7.
>
> OK. I will rework and keep the rest for 2.7.
So, I'm ok with including (low risk) patches that aren't directly
relevant to 2.6 if they're prereqs for patches that are relevant to
2.6. After all, reworking the patches isn't risk free either. Please
mention why these patches are being included in the commit messages
though.
> Thomas, thanks for the review. I have identified a few things I need
> to work on but may be, the patchset is still too large for 2.6 ?
It's not really a question of being too large, it's that I'm nervous
about applying patches which touch the core translation code
(e.g. fixes to HV mode tests) during soft freeze if they're not
addressing a bug that's relevant to 2.6.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register
2016-03-16 1:14 ` David Gibson
@ 2016-03-16 6:17 ` Thomas Huth
2016-03-16 9:24 ` Cédric Le Goater
0 siblings, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-16 6:17 UTC (permalink / raw)
To: David Gibson, Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2745 bytes --]
On 16.03.2016 02:14, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:38PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> Controls the micropartition prefetch, this is pretty much meaningless
>> in full emulation (used for priming the caches on real HW).
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> So, this is readable with HV=0, so technically a fix even for non-HV
> machines. I'm guessing it's not actually read in practice outside the
> HV, though. Not sure if this should go in 2.6 or 2.7.
Patch looks simple (i.e. without risk) enough to be fine for 2.6, I think.
But looking at this again, I wonder why there is no KVM_REG_PPC_*
definition for this register, so that it could be sync'ed with the
kernel, too? Is that on purpose or is it just missing by accident?
Thomas
>> ---
>> target-ppc/cpu.h | 1 +
>> target-ppc/translate_init.c | 13 +++++++++++++
>> 2 files changed, 14 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 81a3e6b5ed29..5203cc6a3bfb 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1398,6 +1398,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>> #define SPR_DHDES (0x0B1)
>> #define SPR_DPDES (0x0B0)
>> #define SPR_DAWR (0x0B4)
>> +#define SPR_MPPR (0x0B8)
>> #define SPR_RPR (0x0BA)
>> #define SPR_DAWRX (0x0BC)
>> #define SPR_HFSCR (0x0BE)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 28a9c2e73156..cfb1bc088950 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8161,6 +8161,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
>> #endif
>> }
>>
>> +static void gen_spr_power8_book4(CPUPPCState *env)
>> +{
>> + /* Add a number of P8 book4 registers */
>> +#if !defined(CONFIG_USER_ONLY)
>> + spr_register_hv(env, SPR_MPPR, "MPPR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + 0);
>> +#endif
>> +}
>> +
>> static void init_proc_book3s_64(CPUPPCState *env, int version)
>> {
>> gen_spr_ne_601(env);
>> @@ -8216,6 +8228,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> gen_spr_power8_rpr(env);
>> gen_spr_power8_dbell(env);
>> gen_spr_power8_ic(env);
>> + gen_spr_power8_book4(env);
>> }
>> if (version < BOOK3S_CPU_POWER8) {
>> gen_spr_book3s_dbg(env);
>
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
2016-03-16 1:14 ` David Gibson
@ 2016-03-16 6:24 ` Thomas Huth
2016-03-16 22:28 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Thomas Huth @ 2016-03-16 6:24 UTC (permalink / raw)
To: David Gibson, Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2332 bytes --]
On 16.03.2016 02:14, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> We should implement HW breakpoint/watchpoint, qemu supports them...
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>
> But I'm assuming 2.7, not 2.6.
Looks like this register can be set by the guest using the H_SET_MODE
hypercall, too (search for H_SET_MODE_RESOURCE_SET_CIABR in the KVM
kernel sources), similar to the DAWR register.
And this patch is using KVM_REG_PPC_CIABR to link this register with the
KVM code in the kernel ... so I think this patch should still go into
2.6 to make sure that the register is migrated properly.
Thomas
>> ---
>> target-ppc/cpu.h | 1 +
>> target-ppc/translate_init.c | 5 +++++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 5203cc6a3bfb..9e1ef10b7dc6 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>> #define SPR_DAWR (0x0B4)
>> #define SPR_MPPR (0x0B8)
>> #define SPR_RPR (0x0BA)
>> +#define SPR_CIABR (0x0BB)
>> #define SPR_DAWRX (0x0BC)
>> #define SPR_HFSCR (0x0BE)
>> #define SPR_VRSAVE (0x100)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index cfb1bc088950..f88bdf7b3cd1 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_generic, &spr_write_generic,
>> KVM_REG_PPC_DAWRX, 0x00000000);
>> + spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + KVM_REG_PPC_CIABR, 0x00000000);
>> }
>>
>> static void gen_spr_970_dbg(CPUPPCState *env)
>
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-16 1:19 ` David Gibson
@ 2016-03-16 9:08 ` Cédric Le Goater
2016-03-17 2:45 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-16 9:08 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
On 03/16/2016 02:19 AM, David Gibson wrote:
> On Tue, Mar 15, 2016 at 09:11:31AM +0100, Cédric Le Goater wrote:
>> On 03/15/2016 01:39 AM, David Gibson wrote:
>>> On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
>>>> Hello,
>>>>
>>>> This is a first mini-serie of patches adding support for new ppc SPRs.
>>>> They were taken from Ben's larger patchset adding the ppc powernv
>>>> platform and they should already be useful for the pseries guest
>>>> migration.
>>>>
>>>> Initial patches come from :
>>>>
>>>> https://github.com/ozbenh/qemu/commits/powernv
>>>>
>>>> The changes are mostly due to the rebase on Dave's 2.6 branch:
>>>>
>>>> https://github.com/dgibson/qemu/commits/ppc-for-2.6
>>>>
>>>> A couple more are bisect and checkpatch fixes and finally some patches
>>>> were merge to reduce the noise.
>>>>
>>>>
>>>>
>>>> The patchset is also available here:
>>>>
>>>> https://github.com/legoater/qemu/commits/for-2.6
>>>>
>>>> It was quickly tested with a pseries guest using KVM and TCG.
>>>
>>> Hmm.. do these all fix bugs with migration, or only some of them?
>>
>> Probably only some.
>>
>> Initially, Thomas gave a shorter list which I expanded to a larger one
>> because of dependencies between patches and I didn't want to change too
>> much what Ben had sent. You had also reviewed a few.
>>
>>> The relevance is that things to fix migration should go into 2.6, but
>>> preparation work for powernv that doesn't fix bug shouldn't really be
>>> going in now, after the soft freeze and will need to wait for 2.7.
>>
>> OK. I will rework and keep the rest for 2.7.
>
> So, I'm ok with including (low risk) patches that aren't directly
> relevant to 2.6 if they're prereqs for patches that are relevant to
> 2.6. After all, reworking the patches isn't risk free either. Please
> mention why these patches are being included in the commit messages
> though.
Sure.
>> Thomas, thanks for the review. I have identified a few things I need
>> to work on but may be, the patchset is still too large for 2.6 ?
>
> It's not really a question of being too large, it's that I'm nervous
> about applying patches which touch the core translation code
> (e.g. fixes to HV mode tests) during soft freeze if they're not
> addressing a bug that's relevant to 2.6.
Could you please take a look at these two patches to see if they are
relevant for 2.6 ? From my readings, they seem to be the only ones on
the edge.
06/17 ppc: Create cpu_ppc_set_papr() helper
11/17 ppc: Initialize AMOR in PAPR mode
but it makes sense to take them if we take :
12/17 ppc: Fix writing to AMR/UAMOR (move hunk to 13)
13/17 ppc: Add POWER8 IAMR register (rework hunk)
Thanks for the review,
C.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register
2016-03-16 6:17 ` Thomas Huth
@ 2016-03-16 9:24 ` Cédric Le Goater
0 siblings, 0 replies; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-16 9:24 UTC (permalink / raw)
To: Thomas Huth, David Gibson; +Cc: qemu-ppc, qemu-devel
On 03/16/2016 07:17 AM, Thomas Huth wrote:
> On 16.03.2016 02:14, David Gibson wrote:
>> On Mon, Mar 14, 2016 at 05:56:38PM +0100, Cédric Le Goater wrote:
>>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>
>>> Controls the micropartition prefetch, this is pretty much meaningless
>>> in full emulation (used for priming the caches on real HW).
>>>
>>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> So, this is readable with HV=0, so technically a fix even for non-HV
>> machines. I'm guessing it's not actually read in practice outside the
>> HV, though. Not sure if this should go in 2.6 or 2.7.
>
> Patch looks simple (i.e. without risk) enough to be fine for 2.6, I think.
> But looking at this again, I wonder why there is no KVM_REG_PPC_*
> definition for this register, so that it could be sync'ed with the
> kernel, too? Is that on purpose or is it just missing by accident?
The spr was reverted :
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=23316316c1af
I should have checked that. I guess we don't want to keep the patch for
2.6 then.
C.
> Thomas
>
>>> ---
>>> target-ppc/cpu.h | 1 +
>>> target-ppc/translate_init.c | 13 +++++++++++++
>>> 2 files changed, 14 insertions(+)
>>>
>>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>>> index 81a3e6b5ed29..5203cc6a3bfb 100644
>>> --- a/target-ppc/cpu.h
>>> +++ b/target-ppc/cpu.h
>>> @@ -1398,6 +1398,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>>> #define SPR_DHDES (0x0B1)
>>> #define SPR_DPDES (0x0B0)
>>> #define SPR_DAWR (0x0B4)
>>> +#define SPR_MPPR (0x0B8)
>>> #define SPR_RPR (0x0BA)
>>> #define SPR_DAWRX (0x0BC)
>>> #define SPR_HFSCR (0x0BE)
>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>> index 28a9c2e73156..cfb1bc088950 100644
>>> --- a/target-ppc/translate_init.c
>>> +++ b/target-ppc/translate_init.c
>>> @@ -8161,6 +8161,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
>>> #endif
>>> }
>>>
>>> +static void gen_spr_power8_book4(CPUPPCState *env)
>>> +{
>>> + /* Add a number of P8 book4 registers */
>>> +#if !defined(CONFIG_USER_ONLY)
>>> + spr_register_hv(env, SPR_MPPR, "MPPR",
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + &spr_read_generic, SPR_NOACCESS,
>>> + &spr_read_generic, &spr_write_generic,
>>> + 0);
>>> +#endif
>>> +}
>>> +
>>> static void init_proc_book3s_64(CPUPPCState *env, int version)
>>> {
>>> gen_spr_ne_601(env);
>>> @@ -8216,6 +8228,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>>> gen_spr_power8_rpr(env);
>>> gen_spr_power8_dbell(env);
>>> gen_spr_power8_ic(env);
>>> + gen_spr_power8_book4(env);
>>> }
>>> if (version < BOOK3S_CPU_POWER8) {
>>> gen_spr_book3s_dbg(env);
>>
>
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
2016-03-16 6:24 ` Thomas Huth
@ 2016-03-16 22:28 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-16 22:28 UTC (permalink / raw)
To: Thomas Huth; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2752 bytes --]
On Wed, Mar 16, 2016 at 07:24:01AM +0100, Thomas Huth wrote:
> On 16.03.2016 02:14, David Gibson wrote:
> > On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>
> >> We should implement HW breakpoint/watchpoint, qemu supports them...
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> >
> > But I'm assuming 2.7, not 2.6.
>
> Looks like this register can be set by the guest using the H_SET_MODE
> hypercall, too (search for H_SET_MODE_RESOURCE_SET_CIABR in the KVM
> kernel sources), similar to the DAWR register.
> And this patch is using KVM_REG_PPC_CIABR to link this register with the
> KVM code in the kernel ... so I think this patch should still go into
> 2.6 to make sure that the register is migrated properly.
Good point, not sure how I missed that.
>
> Thomas
>
> >> ---
> >> target-ppc/cpu.h | 1 +
> >> target-ppc/translate_init.c | 5 +++++
> >> 2 files changed, 6 insertions(+)
> >>
> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> >> index 5203cc6a3bfb..9e1ef10b7dc6 100644
> >> --- a/target-ppc/cpu.h
> >> +++ b/target-ppc/cpu.h
> >> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
> >> #define SPR_DAWR (0x0B4)
> >> #define SPR_MPPR (0x0B8)
> >> #define SPR_RPR (0x0BA)
> >> +#define SPR_CIABR (0x0BB)
> >> #define SPR_DAWRX (0x0BC)
> >> #define SPR_HFSCR (0x0BE)
> >> #define SPR_VRSAVE (0x100)
> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >> index cfb1bc088950..f88bdf7b3cd1 100644
> >> --- a/target-ppc/translate_init.c
> >> +++ b/target-ppc/translate_init.c
> >> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> >> SPR_NOACCESS, SPR_NOACCESS,
> >> &spr_read_generic, &spr_write_generic,
> >> KVM_REG_PPC_DAWRX, 0x00000000);
> >> + spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
> >> + SPR_NOACCESS, SPR_NOACCESS,
> >> + SPR_NOACCESS, SPR_NOACCESS,
> >> + &spr_read_generic, &spr_write_generic,
> >> + KVM_REG_PPC_CIABR, 0x00000000);
> >> }
> >>
> >> static void gen_spr_970_dbg(CPUPPCState *env)
> >
>
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
@ 2016-03-17 2:34 ` David Gibson
2016-03-17 12:33 ` Cédric Le Goater
0 siblings, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-17 2:34 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4467 bytes --]
On Mon, Mar 14, 2016 at 05:56:29PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
> to it. This allows us to add a few more things such as disabling setting
> of MSR:HV and appropriate LPCR bits which will be used when fixing
> the exception model.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
I'm a little nervous about applying this before 2.6. This affects the
value of the LPCR which is used to control exception behaviour in some
cases. I'm pretty sure the current behaviour is wrong, but we do know
it doesn't break horribly for existing machines, which we'd have to
retest with the new behaviour.
I'm certainly willing to hear a case for this if it makes other
patches in the series significantly easier though.
> ---
> hw/ppc/spapr.c | 11 ++---------
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++-
> 3 files changed, 39 insertions(+), 10 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 43708a2a9086..9c01872ce4d3 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1612,15 +1612,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
> /* Set time-base frequency to 512 MHz */
> cpu_ppc_tb_init(env, TIMEBASE_FREQ);
>
> - /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> - * MSR[IP] should never be set.
> - */
> - env->msr_mask &= ~(1 << 6);
> -
> - /* Tell KVM that we're in PAPR mode */
> - if (kvm_enabled()) {
> - kvmppc_set_papr(cpu);
> - }
> + /* Enable PAPR mode in TCG or KVM */
> + cpu_ppc_set_papr(cpu);
>
> if (cpu->max_compat) {
> Error *local_err = NULL;
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 9ce301f18922..a7da0d3e95a9 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
> void store_booke_tsr (CPUPPCState *env, target_ulong val);
> void ppc_tlb_invalidate_all (CPUPPCState *env);
> void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
> +void cpu_ppc_set_papr(PowerPCCPU *cpu);
> #endif
> #endif
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 46dabe58783a..093ef036320d 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8496,8 +8496,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> pcc->threads_per_core = 8;
> }
> -#endif /* defined (TARGET_PPC64) */
>
> +#if !defined(CONFIG_USER_ONLY)
> +
> +void cpu_ppc_set_papr(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
> +
> + /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> + * MSR[IP] should never be set.
> + *
> + * We also disallow setting of MSR_HV
> + */
> + env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
> +
> + /* Set emulated LPCR to not send interrupts to hypervisor. Note that
> + * under KVM, the actual HW LPCR will be set differently by KVM itself,
> + * the settings below ensure proper operations with TCG in absence of
> + * a real hypervisor
> + */
> + lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
> + lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
> +
> + /* We should be followed by a CPU reset but update the active value
> + * just in case...
> + */
> + env->spr[SPR_LPCR] = lpcr->default_value;
> +
> + /* Tell KVM that we're in PAPR mode */
> + if (kvm_enabled()) {
> + kvmppc_set_papr(cpu);
> + }
> +}
> +
> +#endif /* !defined(CONFIG_USER_ONLY) */
> +
> +#endif /* defined (TARGET_PPC64) */
>
> /*****************************************************************************/
> /* Generic CPU instantiation routine */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
2016-03-14 20:13 ` Thomas Huth
2016-03-16 1:09 ` David Gibson
@ 2016-03-17 2:36 ` David Gibson
2 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-17 2:36 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1583 bytes --]
On Mon, Mar 14, 2016 at 05:56:34PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Make sure we give the guest full authorization
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
So my guess is that this is essential for 2.6 if the other patches
affecting AMOR/AMR go in, but not otherwise. Is that correct?
> ---
> target-ppc/translate_init.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 68abd847a251..c921d9f53984 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8542,6 +8542,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
> + ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
>
> /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> * MSR[IP] should never be set.
> @@ -8563,6 +8564,9 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
> */
> env->spr[SPR_LPCR] = lpcr->default_value;
>
> + /* Set a full AMOR so guest can use the AMR as it sees fit */
> + env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
> +
> /* Tell KVM that we're in PAPR mode */
> if (kvm_enabled()) {
> kvmppc_set_papr(cpu);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-16 9:08 ` Cédric Le Goater
@ 2016-03-17 2:45 ` David Gibson
2016-03-17 14:28 ` Cédric Le Goater
0 siblings, 1 reply; 69+ messages in thread
From: David Gibson @ 2016-03-17 2:45 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3550 bytes --]
On Wed, Mar 16, 2016 at 10:08:19AM +0100, Cédric Le Goater wrote:
> On 03/16/2016 02:19 AM, David Gibson wrote:
> > On Tue, Mar 15, 2016 at 09:11:31AM +0100, Cédric Le Goater wrote:
> >> On 03/15/2016 01:39 AM, David Gibson wrote:
> >>> On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
> >>>> Hello,
> >>>>
> >>>> This is a first mini-serie of patches adding support for new ppc SPRs.
> >>>> They were taken from Ben's larger patchset adding the ppc powernv
> >>>> platform and they should already be useful for the pseries guest
> >>>> migration.
> >>>>
> >>>> Initial patches come from :
> >>>>
> >>>> https://github.com/ozbenh/qemu/commits/powernv
> >>>>
> >>>> The changes are mostly due to the rebase on Dave's 2.6 branch:
> >>>>
> >>>> https://github.com/dgibson/qemu/commits/ppc-for-2.6
> >>>>
> >>>> A couple more are bisect and checkpatch fixes and finally some patches
> >>>> were merge to reduce the noise.
> >>>>
> >>>>
> >>>>
> >>>> The patchset is also available here:
> >>>>
> >>>> https://github.com/legoater/qemu/commits/for-2.6
> >>>>
> >>>> It was quickly tested with a pseries guest using KVM and TCG.
> >>>
> >>> Hmm.. do these all fix bugs with migration, or only some of them?
> >>
> >> Probably only some.
> >>
> >> Initially, Thomas gave a shorter list which I expanded to a larger one
> >> because of dependencies between patches and I didn't want to change too
> >> much what Ben had sent. You had also reviewed a few.
> >>
> >>> The relevance is that things to fix migration should go into 2.6, but
> >>> preparation work for powernv that doesn't fix bug shouldn't really be
> >>> going in now, after the soft freeze and will need to wait for 2.7.
> >>
> >> OK. I will rework and keep the rest for 2.7.
> >
> > So, I'm ok with including (low risk) patches that aren't directly
> > relevant to 2.6 if they're prereqs for patches that are relevant to
> > 2.6. After all, reworking the patches isn't risk free either. Please
> > mention why these patches are being included in the commit messages
> > though.
>
> Sure.
>
> >> Thomas, thanks for the review. I have identified a few things I need
> >> to work on but may be, the patchset is still too large for 2.6 ?
> >
> > It's not really a question of being too large, it's that I'm nervous
> > about applying patches which touch the core translation code
> > (e.g. fixes to HV mode tests) during soft freeze if they're not
> > addressing a bug that's relevant to 2.6.
>
> Could you please take a look at these two patches to see if they are
> relevant for 2.6 ? From my readings, they seem to be the only ones on
> the edge.
>
> 06/17 ppc: Create cpu_ppc_set_papr() helper
> 11/17 ppc: Initialize AMOR in PAPR mode
Ok, I've replied to each of those.
> but it makes sense to take them if we take :
>
> 12/17 ppc: Fix writing to AMR/UAMOR (move hunk to 13)
I'm not seeing a lot of cause to put this in for 2.6. The registers
in question are already linked up to KVM, so migration should be ok,
and I don't believe we have real use cases which are hitting the bugs
this patch fixes. Except...
> 13/17 ppc: Add POWER8 IAMR register (rework hunk)
..that I guess it's kind of a pre-req for this one, which could fix real
migration bugs.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper
2016-03-17 2:34 ` David Gibson
@ 2016-03-17 12:33 ` Cédric Le Goater
2016-03-17 22:03 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-17 12:33 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
On 03/17/2016 03:34 AM, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:29PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
>> to it. This allows us to add a few more things such as disabling setting
>> of MSR:HV and appropriate LPCR bits which will be used when fixing
>> the exception model.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
>
> I'm a little nervous about applying this before 2.6. This affects the
> value of the LPCR which is used to control exception behaviour in some
> cases. I'm pretty sure the current behaviour is wrong, but we do know
> it doesn't break horribly for existing machines, which we'd have to
> retest with the new behaviour.
Yes. I agree.
> I'm certainly willing to hear a case for this if it makes other
> patches in the series significantly easier though.
I think we should split this patch in two. Put the cpu_ppc_set_papr() helper
and the MSR change in the first one and keep the LPCR changes for the second.
The latter belong to another set of fixes related the exception models.
C.
>> ---
>> hw/ppc/spapr.c | 11 ++---------
>> target-ppc/cpu.h | 1 +
>> target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++-
>> 3 files changed, 39 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>> index 43708a2a9086..9c01872ce4d3 100644
>> --- a/hw/ppc/spapr.c
>> +++ b/hw/ppc/spapr.c
>> @@ -1612,15 +1612,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
>> /* Set time-base frequency to 512 MHz */
>> cpu_ppc_tb_init(env, TIMEBASE_FREQ);
>>
>> - /* PAPR always has exception vectors in RAM not ROM. To ensure this,
>> - * MSR[IP] should never be set.
>> - */
>> - env->msr_mask &= ~(1 << 6);
>> -
>> - /* Tell KVM that we're in PAPR mode */
>> - if (kvm_enabled()) {
>> - kvmppc_set_papr(cpu);
>> - }
>> + /* Enable PAPR mode in TCG or KVM */
>> + cpu_ppc_set_papr(cpu);
>>
>> if (cpu->max_compat) {
>> Error *local_err = NULL;
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 9ce301f18922..a7da0d3e95a9 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
>> void store_booke_tsr (CPUPPCState *env, target_ulong val);
>> void ppc_tlb_invalidate_all (CPUPPCState *env);
>> void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
>> +void cpu_ppc_set_papr(PowerPCCPU *cpu);
>> #endif
>> #endif
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 46dabe58783a..093ef036320d 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8496,8 +8496,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>> pcc->threads_per_core = 8;
>> }
>> -#endif /* defined (TARGET_PPC64) */
>>
>> +#if !defined(CONFIG_USER_ONLY)
>> +
>> +void cpu_ppc_set_papr(PowerPCCPU *cpu)
>> +{
>> + CPUPPCState *env = &cpu->env;
>> + ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
>> +
>> + /* PAPR always has exception vectors in RAM not ROM. To ensure this,
>> + * MSR[IP] should never be set.
>> + *
>> + * We also disallow setting of MSR_HV
>> + */
>> + env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
>> +
>> + /* Set emulated LPCR to not send interrupts to hypervisor. Note that
>> + * under KVM, the actual HW LPCR will be set differently by KVM itself,
>> + * the settings below ensure proper operations with TCG in absence of
>> + * a real hypervisor
>> + */
>> + lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
>> + lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
>> +
>> + /* We should be followed by a CPU reset but update the active value
>> + * just in case...
>> + */
>> + env->spr[SPR_LPCR] = lpcr->default_value;
>> +
>> + /* Tell KVM that we're in PAPR mode */
>> + if (kvm_enabled()) {
>> + kvmppc_set_papr(cpu);
>> + }
>> +}
>> +
>> +#endif /* !defined(CONFIG_USER_ONLY) */
>> +
>> +#endif /* defined (TARGET_PPC64) */
>>
>> /*****************************************************************************/
>> /* Generic CPU instantiation routine */
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-17 2:45 ` David Gibson
@ 2016-03-17 14:28 ` Cédric Le Goater
2016-03-21 0:59 ` David Gibson
0 siblings, 1 reply; 69+ messages in thread
From: Cédric Le Goater @ 2016-03-17 14:28 UTC (permalink / raw)
To: David Gibson; +Cc: Thomas Huth, qemu-ppc, qemu-devel
On 03/17/2016 03:45 AM, David Gibson wrote:
> On Wed, Mar 16, 2016 at 10:08:19AM +0100, Cédric Le Goater wrote:
>> On 03/16/2016 02:19 AM, David Gibson wrote:
>>> On Tue, Mar 15, 2016 at 09:11:31AM +0100, Cédric Le Goater wrote:
>>>> On 03/15/2016 01:39 AM, David Gibson wrote:
>>>>> On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
>>>>>> Hello,
>>>>>>
>>>>>> This is a first mini-serie of patches adding support for new ppc SPRs.
>>>>>> They were taken from Ben's larger patchset adding the ppc powernv
>>>>>> platform and they should already be useful for the pseries guest
>>>>>> migration.
>>>>>>
>>>>>> Initial patches come from :
>>>>>>
>>>>>> https://github.com/ozbenh/qemu/commits/powernv
>>>>>>
>>>>>> The changes are mostly due to the rebase on Dave's 2.6 branch:
>>>>>>
>>>>>> https://github.com/dgibson/qemu/commits/ppc-for-2.6
>>>>>>
>>>>>> A couple more are bisect and checkpatch fixes and finally some patches
>>>>>> were merge to reduce the noise.
>>>>>>
>>>>>>
>>>>>>
>>>>>> The patchset is also available here:
>>>>>>
>>>>>> https://github.com/legoater/qemu/commits/for-2.6
>>>>>>
>>>>>> It was quickly tested with a pseries guest using KVM and TCG.
>>>>>
>>>>> Hmm.. do these all fix bugs with migration, or only some of them?
>>>>
>>>> Probably only some.
>>>>
>>>> Initially, Thomas gave a shorter list which I expanded to a larger one
>>>> because of dependencies between patches and I didn't want to change too
>>>> much what Ben had sent. You had also reviewed a few.
>>>>
>>>>> The relevance is that things to fix migration should go into 2.6, but
>>>>> preparation work for powernv that doesn't fix bug shouldn't really be
>>>>> going in now, after the soft freeze and will need to wait for 2.7.
>>>>
>>>> OK. I will rework and keep the rest for 2.7.
>>>
>>> So, I'm ok with including (low risk) patches that aren't directly
>>> relevant to 2.6 if they're prereqs for patches that are relevant to
>>> 2.6. After all, reworking the patches isn't risk free either. Please
>>> mention why these patches are being included in the commit messages
>>> though.
>>
>> Sure.
>>
>>>> Thomas, thanks for the review. I have identified a few things I need
>>>> to work on but may be, the patchset is still too large for 2.6 ?
>>>
>>> It's not really a question of being too large, it's that I'm nervous
>>> about applying patches which touch the core translation code
>>> (e.g. fixes to HV mode tests) during soft freeze if they're not
>>> addressing a bug that's relevant to 2.6.
>>
>> Could you please take a look at these two patches to see if they are
>> relevant for 2.6 ? From my readings, they seem to be the only ones on
>> the edge.
>>
>> 06/17 ppc: Create cpu_ppc_set_papr() helper
>> 11/17 ppc: Initialize AMOR in PAPR mode
>
> Ok, I've replied to each of those.
>
>> but it makes sense to take them if we take :
>>
>> 12/17 ppc: Fix writing to AMR/UAMOR (move hunk to 13)
>
> I'm not seeing a lot of cause to put this in for 2.6. The registers
> in question are already linked up to KVM, so migration should be ok,
> and I don't believe we have real use cases which are hitting the bugs
> this patch fixes. Except...
>
>> 13/17 ppc: Add POWER8 IAMR register (rework hunk)
>
> ..that I guess it's kind of a pre-req for this one, which could fix real
> migration bugs.
Yes. So, I will send a v3 removing the LPCR changes in the cpu_ppc_set_papr()
helper. How does that sound ?
Thanks,
C.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper
2016-03-17 12:33 ` Cédric Le Goater
@ 2016-03-17 22:03 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-17 22:03 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 5234 bytes --]
On Thu, Mar 17, 2016 at 01:33:31PM +0100, Cédric Le Goater wrote:
> On 03/17/2016 03:34 AM, David Gibson wrote:
> > On Mon, Mar 14, 2016 at 05:56:29PM +0100, Cédric Le Goater wrote:
> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>
> >> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
> >> to it. This allows us to add a few more things such as disabling setting
> >> of MSR:HV and appropriate LPCR bits which will be used when fixing
> >> the exception model.
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> >
> > I'm a little nervous about applying this before 2.6. This affects the
> > value of the LPCR which is used to control exception behaviour in some
> > cases. I'm pretty sure the current behaviour is wrong, but we do know
> > it doesn't break horribly for existing machines, which we'd have to
> > retest with the new behaviour.
>
> Yes. I agree.
>
> > I'm certainly willing to hear a case for this if it makes other
> > patches in the series significantly easier though.
>
> I think we should split this patch in two. Put the cpu_ppc_set_papr() helper
> and the MSR change in the first one and keep the LPCR changes for the second.
> The latter belong to another set of fixes related the exception
> models.
Yes, I think that makes sense.
>
> C.
>
> >> ---
> >> hw/ppc/spapr.c | 11 ++---------
> >> target-ppc/cpu.h | 1 +
> >> target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++-
> >> 3 files changed, 39 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> >> index 43708a2a9086..9c01872ce4d3 100644
> >> --- a/hw/ppc/spapr.c
> >> +++ b/hw/ppc/spapr.c
> >> @@ -1612,15 +1612,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
> >> /* Set time-base frequency to 512 MHz */
> >> cpu_ppc_tb_init(env, TIMEBASE_FREQ);
> >>
> >> - /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> >> - * MSR[IP] should never be set.
> >> - */
> >> - env->msr_mask &= ~(1 << 6);
> >> -
> >> - /* Tell KVM that we're in PAPR mode */
> >> - if (kvm_enabled()) {
> >> - kvmppc_set_papr(cpu);
> >> - }
> >> + /* Enable PAPR mode in TCG or KVM */
> >> + cpu_ppc_set_papr(cpu);
> >>
> >> if (cpu->max_compat) {
> >> Error *local_err = NULL;
> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> >> index 9ce301f18922..a7da0d3e95a9 100644
> >> --- a/target-ppc/cpu.h
> >> +++ b/target-ppc/cpu.h
> >> @@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
> >> void store_booke_tsr (CPUPPCState *env, target_ulong val);
> >> void ppc_tlb_invalidate_all (CPUPPCState *env);
> >> void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
> >> +void cpu_ppc_set_papr(PowerPCCPU *cpu);
> >> #endif
> >> #endif
> >>
> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >> index 46dabe58783a..093ef036320d 100644
> >> --- a/target-ppc/translate_init.c
> >> +++ b/target-ppc/translate_init.c
> >> @@ -8496,8 +8496,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> >> pcc->threads_per_core = 8;
> >> }
> >> -#endif /* defined (TARGET_PPC64) */
> >>
> >> +#if !defined(CONFIG_USER_ONLY)
> >> +
> >> +void cpu_ppc_set_papr(PowerPCCPU *cpu)
> >> +{
> >> + CPUPPCState *env = &cpu->env;
> >> + ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
> >> +
> >> + /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> >> + * MSR[IP] should never be set.
> >> + *
> >> + * We also disallow setting of MSR_HV
> >> + */
> >> + env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
> >> +
> >> + /* Set emulated LPCR to not send interrupts to hypervisor. Note that
> >> + * under KVM, the actual HW LPCR will be set differently by KVM itself,
> >> + * the settings below ensure proper operations with TCG in absence of
> >> + * a real hypervisor
> >> + */
> >> + lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
> >> + lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
> >> +
> >> + /* We should be followed by a CPU reset but update the active value
> >> + * just in case...
> >> + */
> >> + env->spr[SPR_LPCR] = lpcr->default_value;
> >> +
> >> + /* Tell KVM that we're in PAPR mode */
> >> + if (kvm_enabled()) {
> >> + kvmppc_set_papr(cpu);
> >> + }
> >> +}
> >> +
> >> +#endif /* !defined(CONFIG_USER_ONLY) */
> >> +
> >> +#endif /* defined (TARGET_PPC64) */
> >>
> >> /*****************************************************************************/
> >> /* Generic CPU instantiation routine */
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
2016-03-17 14:28 ` Cédric Le Goater
@ 2016-03-21 0:59 ` David Gibson
0 siblings, 0 replies; 69+ messages in thread
From: David Gibson @ 2016-03-21 0:59 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4003 bytes --]
On Thu, Mar 17, 2016 at 03:28:46PM +0100, Cédric Le Goater wrote:
> On 03/17/2016 03:45 AM, David Gibson wrote:
> > On Wed, Mar 16, 2016 at 10:08:19AM +0100, Cédric Le Goater wrote:
> >> On 03/16/2016 02:19 AM, David Gibson wrote:
> >>> On Tue, Mar 15, 2016 at 09:11:31AM +0100, Cédric Le Goater wrote:
> >>>> On 03/15/2016 01:39 AM, David Gibson wrote:
> >>>>> On Mon, Mar 14, 2016 at 05:56:23PM +0100, Cédric Le Goater wrote:
> >>>>>> Hello,
> >>>>>>
> >>>>>> This is a first mini-serie of patches adding support for new ppc SPRs.
> >>>>>> They were taken from Ben's larger patchset adding the ppc powernv
> >>>>>> platform and they should already be useful for the pseries guest
> >>>>>> migration.
> >>>>>>
> >>>>>> Initial patches come from :
> >>>>>>
> >>>>>> https://github.com/ozbenh/qemu/commits/powernv
> >>>>>>
> >>>>>> The changes are mostly due to the rebase on Dave's 2.6 branch:
> >>>>>>
> >>>>>> https://github.com/dgibson/qemu/commits/ppc-for-2.6
> >>>>>>
> >>>>>> A couple more are bisect and checkpatch fixes and finally some patches
> >>>>>> were merge to reduce the noise.
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> The patchset is also available here:
> >>>>>>
> >>>>>> https://github.com/legoater/qemu/commits/for-2.6
> >>>>>>
> >>>>>> It was quickly tested with a pseries guest using KVM and TCG.
> >>>>>
> >>>>> Hmm.. do these all fix bugs with migration, or only some of them?
> >>>>
> >>>> Probably only some.
> >>>>
> >>>> Initially, Thomas gave a shorter list which I expanded to a larger one
> >>>> because of dependencies between patches and I didn't want to change too
> >>>> much what Ben had sent. You had also reviewed a few.
> >>>>
> >>>>> The relevance is that things to fix migration should go into 2.6, but
> >>>>> preparation work for powernv that doesn't fix bug shouldn't really be
> >>>>> going in now, after the soft freeze and will need to wait for 2.7.
> >>>>
> >>>> OK. I will rework and keep the rest for 2.7.
> >>>
> >>> So, I'm ok with including (low risk) patches that aren't directly
> >>> relevant to 2.6 if they're prereqs for patches that are relevant to
> >>> 2.6. After all, reworking the patches isn't risk free either. Please
> >>> mention why these patches are being included in the commit messages
> >>> though.
> >>
> >> Sure.
> >>
> >>>> Thomas, thanks for the review. I have identified a few things I need
> >>>> to work on but may be, the patchset is still too large for 2.6 ?
> >>>
> >>> It's not really a question of being too large, it's that I'm nervous
> >>> about applying patches which touch the core translation code
> >>> (e.g. fixes to HV mode tests) during soft freeze if they're not
> >>> addressing a bug that's relevant to 2.6.
> >>
> >> Could you please take a look at these two patches to see if they are
> >> relevant for 2.6 ? From my readings, they seem to be the only ones on
> >> the edge.
> >>
> >> 06/17 ppc: Create cpu_ppc_set_papr() helper
> >> 11/17 ppc: Initialize AMOR in PAPR mode
> >
> > Ok, I've replied to each of those.
> >
> >> but it makes sense to take them if we take :
> >>
> >> 12/17 ppc: Fix writing to AMR/UAMOR (move hunk to 13)
> >
> > I'm not seeing a lot of cause to put this in for 2.6. The registers
> > in question are already linked up to KVM, so migration should be ok,
> > and I don't believe we have real use cases which are hitting the bugs
> > this patch fixes. Except...
> >
> >> 13/17 ppc: Add POWER8 IAMR register (rework hunk)
> >
> > ..that I guess it's kind of a pre-req for this one, which could fix real
> > migration bugs.
>
> Yes. So, I will send a v3 removing the LPCR changes in the cpu_ppc_set_papr()
> helper. How does that sound ?
Ok, sounds good.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
end of thread, other threads:[~2016-03-21 1:10 UTC | newest]
Thread overview: 69+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
2016-03-14 18:34 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Cédric Le Goater
2016-03-14 18:50 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
2016-03-14 19:14 ` Thomas Huth
2016-03-15 9:43 ` David Gibson
2016-03-15 10:49 ` Thomas Huth
2016-03-15 17:04 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-03-16 1:04 ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
2016-03-14 19:20 ` Thomas Huth
2016-03-15 8:06 ` Cédric Le Goater
2016-03-15 8:21 ` Bharata B Rao
2016-03-15 9:45 ` David Gibson
2016-03-15 21:11 ` Benjamin Herrenschmidt
2016-03-16 0:41 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
2016-03-14 19:29 ` Thomas Huth
2016-03-15 9:47 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
2016-03-17 2:34 ` David Gibson
2016-03-17 12:33 ` Cédric Le Goater
2016-03-17 22:03 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
2016-03-16 1:05 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
2016-03-14 19:32 ` Thomas Huth
2016-03-16 1:06 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
2016-03-14 19:37 ` Thomas Huth
2016-03-16 1:07 ` David Gibson
2016-03-16 1:07 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
2016-03-14 19:40 ` Thomas Huth
2016-03-16 1:08 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
2016-03-14 20:13 ` Thomas Huth
2016-03-16 1:09 ` David Gibson
2016-03-17 2:36 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
2016-03-14 20:26 ` Thomas Huth
2016-03-15 8:05 ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
2016-03-14 20:36 ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
2016-03-14 20:54 ` Thomas Huth
2016-03-14 21:07 ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-03-16 1:12 ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
2016-03-16 1:14 ` David Gibson
2016-03-16 6:17 ` Thomas Huth
2016-03-16 9:24 ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
2016-03-14 20:00 ` Thomas Huth
2016-03-16 1:14 ` David Gibson
2016-03-16 6:24 ` Thomas Huth
2016-03-16 22:28 ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
2016-03-14 20:08 ` Thomas Huth
2016-03-16 1:15 ` David Gibson
2016-03-15 0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
2016-03-15 8:11 ` Cédric Le Goater
2016-03-16 1:19 ` David Gibson
2016-03-16 9:08 ` Cédric Le Goater
2016-03-17 2:45 ` David Gibson
2016-03-17 14:28 ` Cédric Le Goater
2016-03-21 0:59 ` David Gibson
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