* [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU
@ 2012-03-04 20:32 Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
` (8 more replies)
0 siblings, 9 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-04 20:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Avi Kivity, Andreas Färber, anthony, lcapitulino
Hello Anthony,
This series prepares for QOM'ification of CPUs and machines by rearranging
constructor calls and Makefile dependency rules. I've separated it out due
to complaints about patch series length for conversion of all targets.
Patch 1 is a RESEND that avoids an abort after patch 2.
Patch 2 rearranges module init for QOM in the system emulators, so that
objects can really be used beyond devices.
Patch 3 adds QOM support to the user emulators. As required by Anthony,
they are now only built once.
Available at:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-user.v4
Regards,
Andreas
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Avi Kivity <avi@redhat.com>
v3 -> v4:
* Fix kvmclock abort due to too early kvm_enabled() check.
* Introduce $(universal-obj-y) to build some objects only once.
* Fix GPLv2 license link.
v2 -> v3:
* Rebased against qom-upstream.14 branch (and that against master).
* Build common dependencies for user emulators in libuser/.
* New dependencies needed after moving properties into object.c.
* Add a qemu-user.c with stubs needed for successful linking.
v1 -> v2:
* Don't introduce extra early_init(), just relocate former MODULE_INIT_DEVICE.
* Provide new type_init() macro to be used instead of device_init().
Andreas Färber (3):
kvmclock: Always register type
qom: Register QOM infrastructure early
qom: Add QOM support to user emulators
Makefile | 6 +++---
Makefile.objs | 23 ++++++++++++++++++-----
Makefile.target | 4 ++++
Makefile.user | 1 +
bsd-user/main.c | 2 ++
darwin-user/main.c | 3 +++
hw/kvm/clock.c | 2 --
linux-user/main.c | 2 ++
qemu-user.c | 37 +++++++++++++++++++++++++++++++++++++
vl.c | 4 ++--
10 files changed, 72 insertions(+), 12 deletions(-)
create mode 100644 qemu-user.c
--
1.7.7
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
@ 2012-03-04 20:32 ` Andreas Färber
2012-03-05 9:23 ` Avi Kivity
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early Andreas Färber
` (7 subsequent siblings)
8 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-04 20:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Marcelo Tosatti, Andreas Färber, anthony, lcapitulino
Currently, the "kvmclock" type is only registered when kvm_enabled().
This breaks when moving type registration to before command line
parsing (so that QOM types can be used for CPU and machine).
Since the QOM classes are lazy-initialized anyway and kvmclock_create()
has another kvm_enabled() check, simply drop the KVM check in
kvmclock_register_types().
kvm-i8259, kvm-apic and kvm-ioapic do not suffer from such a check.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
---
hw/kvm/clock.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/kvm/clock.c b/hw/kvm/clock.c
index 2157340..446bd62 100644
--- a/hw/kvm/clock.c
+++ b/hw/kvm/clock.c
@@ -121,9 +121,7 @@ void kvmclock_create(void)
static void kvmclock_register_types(void)
{
- if (kvm_enabled()) {
type_register_static(&kvmclock_info);
- }
}
type_init(kvmclock_register_types)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
@ 2012-03-04 20:32 ` Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
` (6 subsequent siblings)
8 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-04 20:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, anthony, lcapitulino
The constructors for QOM TYPE_INTERFACE were executed rather late in
vl.c's main(). Call them very early so that QOM can safely be used for
machines and CPUs.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
vl.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/vl.c b/vl.c
index 97ab2b9..3fb9182 100644
--- a/vl.c
+++ b/vl.c
@@ -2299,6 +2299,8 @@ int main(int argc, char **argv, char **envp)
#endif
}
+ module_call_init(MODULE_INIT_QOM);
+
runstate_init();
init_clocks();
@@ -3460,8 +3462,6 @@ int main(int argc, char **argv, char **envp)
if (foreach_device_config(DEV_DEBUGCON, debugcon_parse) < 0)
exit(1);
- module_call_init(MODULE_INIT_QOM);
-
/* must be after qdev registration but before machine init */
if (vga_model) {
select_vgahw(vga_model);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early Andreas Färber
@ 2012-03-04 20:32 ` Andreas Färber
2012-03-07 14:11 ` Luiz Capitulino
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (5 subsequent siblings)
8 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-04 20:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, anthony, lcapitulino
Link the Object base class and the module infrastructure for class
registration. Introduce $(universal-obj-y) for objects that are more
common than $(common-obj-y), so that those only get built once.
Call QOM module init for type registration.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
Makefile | 6 +++---
Makefile.objs | 23 ++++++++++++++++++-----
Makefile.target | 4 ++++
Makefile.user | 1 +
bsd-user/main.c | 2 ++
darwin-user/main.c | 3 +++
linux-user/main.c | 2 ++
qemu-user.c | 37 +++++++++++++++++++++++++++++++++++++
8 files changed, 70 insertions(+), 8 deletions(-)
create mode 100644 qemu-user.c
diff --git a/Makefile b/Makefile
index 49c775b..cc24fea 100644
--- a/Makefile
+++ b/Makefile
@@ -97,12 +97,12 @@ ifneq ($(wildcard config-host.mak),)
include $(SRC_PATH)/Makefile.objs
endif
-$(common-obj-y): $(GENERATED_HEADERS)
+$(universal-obj-y) $(common-obj-y): $(GENERATED_HEADERS)
subdir-libcacard: $(oslib-obj-y) $(trace-obj-y) qemu-timer-common.o
-$(filter %-softmmu,$(SUBDIR_RULES)): $(trace-obj-y) $(common-obj-y) subdir-libdis
+$(filter %-softmmu,$(SUBDIR_RULES)): $(universal-obj-y) $(trace-obj-y) $(common-obj-y) subdir-libdis
-$(filter %-user,$(SUBDIR_RULES)): $(GENERATED_HEADERS) $(trace-obj-y) subdir-libdis-user subdir-libuser
+$(filter %-user,$(SUBDIR_RULES)): $(GENERATED_HEADERS) $(universal-obj-y) $(trace-obj-y) subdir-libdis-user subdir-libuser
ROMSUBDIR_RULES=$(patsubst %,romsubdir-%, $(ROMS))
romsubdir-%:
diff --git a/Makefile.objs b/Makefile.objs
index 808de6a..f912fbb 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -1,9 +1,22 @@
#######################################################################
+# Target-independent parts used in system and user emulation
+universal-obj-y =
+
+#######################################################################
# QObject
qobject-obj-y = qint.o qstring.o qdict.o qlist.o qfloat.o qbool.o
qobject-obj-y += qjson.o json-lexer.o json-streamer.o json-parser.o
qobject-obj-y += qerror.o error.o qemu-error.o
+universal-obj-y += $(qobject-obj-y)
+
+#######################################################################
+# QOM
+include $(SRC_PATH)/qom/Makefile
+qom-obj-y = $(addprefix qom/, $(qom-y))
+
+universal-obj-y += $(qom-obj-y)
+
#######################################################################
# oslib-obj-y is code depending on the OS (win32 vs posix)
oslib-obj-y = osdep.o
@@ -76,7 +89,6 @@ fsdev-obj-$(CONFIG_VIRTFS) += $(addprefix fsdev/, $(fsdev-nested-y))
common-obj-y = $(block-obj-y) blockdev.o
common-obj-y += $(net-obj-y)
-common-obj-y += $(qobject-obj-y)
common-obj-$(CONFIG_LINUX) += $(fsdev-obj-$(CONFIG_LINUX))
common-obj-y += readline.o console.o cursor.o
common-obj-y += $(oslib-obj-y)
@@ -124,9 +136,6 @@ common-obj-$(CONFIG_WIN32) += version.o
common-obj-$(CONFIG_SPICE) += ui/spice-core.o ui/spice-input.o ui/spice-display.o spice-qemu-char.o
-include $(SRC_PATH)/qom/Makefile
-common-obj-y += $(addprefix qom/, $(qom-y))
-
audio-obj-y = audio.o noaudio.o wavaudio.o mixeng.o
audio-obj-$(CONFIG_SDL) += sdlaudio.o
audio-obj-$(CONFIG_OSS) += ossaudio.o
@@ -182,6 +191,8 @@ user-obj-y =
user-obj-y += envlist.o path.o
user-obj-y += tcg-runtime.o host-utils.o
user-obj-y += cutils.o cache-utils.o
+user-obj-y += module.o
+user-obj-y += qemu-user.o
user-obj-y += $(trace-obj-y)
######################################################################
@@ -418,9 +429,11 @@ qapi-nested-y += qmp-output-visitor.o qmp-registry.o qmp-dispatch.o
qapi-nested-y += string-input-visitor.o string-output-visitor.o
qapi-obj-y = $(addprefix qapi/, $(qapi-nested-y))
-common-obj-y += qmp-marshal.o qapi-visit.o qapi-types.o $(qapi-obj-y)
+common-obj-y += qmp-marshal.o qapi-visit.o qapi-types.o
common-obj-y += qmp.o hmp.o
+universal-obj-y += $(qapi-obj-y)
+
######################################################################
# guest agent
diff --git a/Makefile.target b/Makefile.target
index 343eb78..ac4ebfe 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -136,6 +136,7 @@ obj-m68k-y += m68k-sim.o m68k-semi.o
$(obj-y) $(obj-$(TARGET_BASE_ARCH)-y): $(GENERATED_HEADERS)
+obj-y += $(addprefix ../, $(universal-obj-y))
obj-y += $(addprefix ../libuser/, $(user-obj-y))
obj-y += $(addprefix ../libdis-user/, $(libdis-y))
obj-y += $(libobj-y)
@@ -163,6 +164,7 @@ obj-i386-y += ioport-user.o
$(obj-y) $(obj-$(TARGET_BASE_ARCH)-y): $(GENERATED_HEADERS)
+obj-y += $(addprefix ../, $(universal-obj-y))
obj-y += $(addprefix ../libuser/, $(user-obj-y))
obj-y += $(addprefix ../libdis-user/, $(libdis-y))
obj-y += $(libobj-y)
@@ -185,6 +187,7 @@ obj-i386-y += ioport-user.o
$(obj-y) $(obj-$(TARGET_BASE_ARCH)-y): $(GENERATED_HEADERS)
+obj-y += $(addprefix ../, $(universal-obj-y))
obj-y += $(addprefix ../libuser/, $(user-obj-y))
obj-y += $(addprefix ../libdis-user/, $(libdis-y))
obj-y += $(libobj-y)
@@ -401,6 +404,7 @@ monitor.o: hmp-commands.h qmp-commands-old.h
$(obj-y) $(obj-$(TARGET_BASE_ARCH)-y): $(GENERATED_HEADERS)
+obj-y += $(addprefix ../, $(universal-obj-y))
obj-y += $(addprefix ../, $(common-obj-y))
obj-y += $(addprefix ../libdis/, $(libdis-y))
obj-y += $(libobj-y)
diff --git a/Makefile.user b/Makefile.user
index 2b1e4d1..b717820 100644
--- a/Makefile.user
+++ b/Makefile.user
@@ -9,6 +9,7 @@ include $(SRC_PATH)/rules.mak
$(call set-vpath, $(SRC_PATH))
QEMU_CFLAGS+=-I..
+QEMU_CFLAGS += -I$(SRC_PATH)/include
include $(SRC_PATH)/Makefile.objs
diff --git a/bsd-user/main.c b/bsd-user/main.c
index cc7d4a3..cdb0d0a 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -748,6 +748,8 @@ int main(int argc, char **argv)
if (argc <= 1)
usage();
+ module_call_init(MODULE_INIT_QOM);
+
if ((envlist = envlist_create()) == NULL) {
(void) fprintf(stderr, "Unable to allocate envlist\n");
exit(1);
diff --git a/darwin-user/main.c b/darwin-user/main.c
index 9b57c20..e1519c7 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -28,6 +28,7 @@
#include <sys/mman.h>
#include "qemu.h"
+#include "qemu-common.h"
#define DEBUG_LOGFILE "/tmp/qemu.log"
@@ -749,6 +750,8 @@ int main(int argc, char **argv)
if (argc <= 1)
usage();
+ module_call_init(MODULE_INIT_QOM);
+
optind = 1;
for(;;) {
if (optind >= argc)
diff --git a/linux-user/main.c b/linux-user/main.c
index 14bf5f0..bd47489 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3285,6 +3285,8 @@ int main(int argc, char **argv, char **envp)
int i;
int ret;
+ module_call_init(MODULE_INIT_QOM);
+
qemu_cache_utils_init(envp);
if ((envlist = envlist_create()) == NULL) {
diff --git a/qemu-user.c b/qemu-user.c
new file mode 100644
index 0000000..08ccb0f
--- /dev/null
+++ b/qemu-user.c
@@ -0,0 +1,37 @@
+/*
+ * Stubs for QEMU user emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu-common.h"
+#include "monitor.h"
+
+Monitor *cur_mon;
+
+int monitor_cur_is_qmp(void)
+{
+ return 0;
+}
+
+void monitor_vprintf(Monitor *mon, const char *fmt, va_list ap)
+{
+}
+
+void monitor_set_error(Monitor *mon, QError *qerror)
+{
+}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
@ 2012-03-05 9:23 ` Avi Kivity
2012-03-10 1:35 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Avi Kivity @ 2012-03-05 9:23 UTC (permalink / raw)
To: Andreas Färber; +Cc: Marcelo Tosatti, qemu-devel, anthony, lcapitulino
On 03/04/2012 10:32 PM, Andreas Färber wrote:
> Currently, the "kvmclock" type is only registered when kvm_enabled().
>
> This breaks when moving type registration to before command line
> parsing (so that QOM types can be used for CPU and machine).
>
> Since the QOM classes are lazy-initialized anyway and kvmclock_create()
> has another kvm_enabled() check, simply drop the KVM check in
> kvmclock_register_types().
>
> kvm-i8259, kvm-apic and kvm-ioapic do not suffer from such a check.
Patch looks good.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
@ 2012-03-07 14:11 ` Luiz Capitulino
0 siblings, 0 replies; 175+ messages in thread
From: Luiz Capitulino @ 2012-03-07 14:11 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, anthony
On Sun, 4 Mar 2012 21:32:36 +0100
Andreas Färber <afaerber@suse.de> wrote:
> Link the Object base class and the module infrastructure for class
> registration. Introduce $(universal-obj-y) for objects that are more
> common than $(common-obj-y), so that those only get built once.
>
> Call QOM module init for type registration.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Cc: Anthony Liguori <anthony@codemonkey.ws>
Never looked how user emulators work in detail, but looks good to me.
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type
2012-03-05 9:23 ` Avi Kivity
@ 2012-03-10 1:35 ` Andreas Färber
2012-03-12 10:36 ` Avi Kivity
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 1:35 UTC (permalink / raw)
To: Avi Kivity, qemu-devel; +Cc: Marcelo Tosatti, anthony, lcapitulino
Am 05.03.2012 10:23, schrieb Avi Kivity:
> On 03/04/2012 10:32 PM, Andreas Färber wrote:
>> Currently, the "kvmclock" type is only registered when kvm_enabled().
>>
>> This breaks when moving type registration to before command line
>> parsing (so that QOM types can be used for CPU and machine).
>>
>> Since the QOM classes are lazy-initialized anyway and kvmclock_create()
>> has another kvm_enabled() check, simply drop the KVM check in
>> kvmclock_register_types().
>>
>> kvm-i8259, kvm-apic and kvm-ioapic do not suffer from such a check.
>
> Patch looks good.
Ping for series.
Avi, do you want to sign this patch off through uq/master? Or should I
make the above a Reviewed-by (and remove the Cc:) within this series?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
` (2 preceding siblings ...)
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
` (43 more replies)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (4 subsequent siblings)
8 siblings, 44 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jan Kiszka, Andreas Färber, Anthony Liguori
Hello,
This is a heavily rebased and redone series introducing a QOM CPU base class.
It now avoids the name conflict between typedef struct CPU CPU and CPU(obj)
by freeing the identifier CPUState.
Patch 1 is a patch by Alex that removes some unused occurrences of cpu_reset().
Patch 2 renames cpu_reset() to avoid workarounds such as previous cpu_do_reset().
These two have no dependency on the CPUState/CPU() issue under discussion and
could be applied independently.
Patches 3-12 are hand-crafted patches converting CPUState uses to the appropriate
CPU*State and prepare for mass conversion from CPUState to CPU*State.
Patches 13-43 are scripted conversions, separated by architecture, cf. below.
Patch 44 introduces CPUClass, CPU() and reintroduces a new CPUState.
Available at:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu.v4
Regards,
Andreas
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jan Kiszka <jan.kiszka@web.de>
v3 -> v4:
* Rebased on top of type_init() v2, qom-user v4 and ppc405 cleanup.
* Rename cpu_reset() to cpu_state_reset(), so that cpu_reset() can be used
for CPU class in place of cpu_do_reset() (suggested by Anthony).
* Use container_of() for CPUState -> CPU macros (suggested by Anthony).
* Resolve name conflict between struct CPU and CPU(obj) by renaming CPUState
to CPUArchState and by restricting its use to places that must be replaced
with new CPUState after all targets are converted.
v2 -> v3:
* Rebased against qom-upstream.14 branch (and that against master).
* Move cpu.c from hw/ to qom/ (built only once).
* Use proper GPL headers.
v1 -> v2:
* Drop processor_init() and MODULE_INIT_CPU in favor of MODULE_INIT_DEVICE.
* Prepare cast macros for CPU.
* Add documentation.
* Prepare reset callback.
---8<---
#!/bin/sh
for arch in `find . -maxdepth 1 -name "target-*" | cut -d- -f2 | sort`; do
case $arch in
"alpha") dest=CPUAlphaState ;;
"arm") dest=CPUARMState ;;
"cris") dest=CPUCRISState ;;
"i386") dest=CPUX86State ;;
"lm32") dest=CPULM32State ;;
"m68k") dest=CPUM68KState ;;
"microblaze") dest=CPUMBState ;;
"mips") dest=CPUMIPSState ;;
"ppc") dest=CPUPPCState ;;
"s390x") dest=CPUS390XState ;;
"sh4") dest=CPUSH4State ;;
"sparc") dest=CPUSPARCState ;;
"unicore32") dest=CPUUniCore32State ;;
"xtensa") dest=CPUXtensaState ;;
esac
sed --in-place "s/CPUState/$dest/g" target-$arch/*.[hc]
sed --in-place "s/#define $dest/#define CPUState/" target-$arch/cpu.h
git commit --all --signoff --no-verify --file=- <<EOM
target-$arch: Don't overuse CPUState
Scripted conversion:
sed -i "s/CPUState/$dest/g" target-$arch/*.[hc]
sed -i "s/#define $dest/#define CPUState/" target-$arch/cpu.h
EOM
done
for arch in arm m68k xtensa; do
case $arch in
"arm") dest=CPUARMState ;;
"m68k") dest=CPUM68KState ;;
"xtensa") dest=CPUXtensaState ;;
esac
sed --in-place "s/CPUState/$dest/g" $arch-semi.c
git commit --all --signoff --no-verify --file=- <<EOM
$arch-semi: Don't use CPUState
Scripted conversion:
sed -i "s/CPUState/$dest/g" $arch-semi.c
EOM
done
INPUTS="hw/alpha_*.[hc]"
sed --in-place "s/CPUState/CPUAlphaState/g" $INPUTS
git commit --all --signoff --no-verify --file=- <<EOM
alpha hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUAlphaState/g" \$file
done
EOM
INPUTS="hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c"
INPUTS="$INPUTS hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c"
INPUTS="$INPUTS hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c"
INPUTS="$INPUTS hw/strongarm.h hw/versatilepb.c hw/vexpress.c "
INPUTS="$INPUTS hw/xilinx_zynq.c "
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUARMState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
arm hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUARMState/g" \$file
done
EOM
INPUTS="hw/cris-boot.[hc] hw/cris_pic_cpu.c hw/axis_dev88.c hw/etraxfs.h hw/etraxfs_ser.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUCRISState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
cris hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUCRISState/g" \$file
done
EOM
INPUTS="hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c hw/xen_machine_pv.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUX86State/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
i386 hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUX86State/g" \$file
done
EOM
INPUTS="hw/lm32_boards.c hw/milkymist.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPULM32State/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
lm32 hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPULM32State/g" \$file
done
EOM
INPUTS="hw/an5206.c hw/dummy_m68k.c hw/mcf.h hw/mcf5206.c hw/mcf5208.c hw/mcf_intc.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUM68KState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
m68k hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUM68KState/g" \$file
done
EOM
INPUTS="hw/microblaze_*.[hc]"
INPUTS="$INPUTS hw/petalogix_ml605_mmu.c hw/petalogix_s3adsp1800_mmu.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUMBState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
microblaze hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUMBState/g" \$file
done
EOM
INPUTS="hw/mips_*.[hc]"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUMIPSState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
mips hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUMIPSState/g" \$file
done
EOM
INPUTS="hw/ppc*.[hc] hw/mpc8544_guts.c hw/spapr*.[hc] hw/virtex_ml507.c hw/xics.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUPPCState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
ppc hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUPPCState/g" \$file
done
EOM
INPUTS="hw/s390-*.[hc]"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUS390XState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
s390x hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUS390XState/g" \$file
done
EOM
INPUTS="hw/sh.h hw/shix.c hw/r2d.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUSH4State/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
sh4 hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUSH4State/g" \$file
done
EOM
INPUTS="hw/sun4m.c hw/sun4u.c hw/grlib.h hw/leon3.c"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUSPARCState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
sparc hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUSPARCState/g" \$file
done
EOM
INPUTS="hw/xtensa_*.[hc]"
for file in $INPUTS; do
sed --in-place "s/CPUState/CPUXtensaState/g" $file
done
git commit --all --signoff --no-verify --file=- <<EOM
xtensa hw/: Don't use CPUState
Scripted conversion:
for file in $INPUTS; do
sed -i "s/CPUState/CPUXtensaState/g" \$file
done
EOM
#exit
INPUTS="*.[hc] hw/*.[hc] hw/kvm/*.[hc]"
INPUTS="$INPUTS linux-user/*.[hc] linux-user/m68k/*.[hc]"
INPUTS="$INPUTS bsd-user/*.[hc]"
INPUTS="$INPUTS darwin-user/*.[hc]"
INPUTS="$INPUTS tcg/*/*.[hc]"
INPUTS="$INPUTS target-*/cpu.h"
for input in $INPUTS; do
sed --in-place "s/CPUState/CPUArchState/g" $input
done
git commit --all --no-verify --signoff --file=- <<EOM
Rename CPUState -> CPUArchState
EOM
---8<---
Alexander Graf (1):
PPC: 405: Use proper CPU reset
Andreas Färber (43):
Rename cpu_reset() to cpu_state_reset()
monitor: Don't access registers through CPUState
monitor: Avoid CPUState in read/write functions
target-lm32: Typedef struct CPULM32State
target-microblaze: Typedef struct CPUMBState
target-sparc: Typedef struct CPUSPARCState early
target-unicore32: Rename to CPUUniCore32State
hw/mc146818: Drop unneeded #includes
linux-user: Don't overuse CPUState
darwin-user: Don't overuse CPUState
bsd-user: Don't overuse CPUState
target-alpha: Don't overuse CPUState
target-arm: Don't overuse CPUState
target-cris: Don't overuse CPUState
target-i386: Don't overuse CPUState
target-lm32: Don't overuse CPUState
target-m68k: Don't overuse CPUState
target-microblaze: Don't overuse CPUState
target-mips: Don't overuse CPUState
target-ppc: Don't overuse CPUState
target-s390x: Don't overuse CPUState
target-sh4: Don't overuse CPUState
target-sparc: Don't overuse CPUState
target-unicore32: Don't overuse CPUState
target-xtensa: Don't overuse CPUState
arm-semi: Don't use CPUState
m68k-semi: Don't use CPUState
xtensa-semi: Don't use CPUState
alpha hw/: Don't use CPUState
arm hw/: Don't use CPUState
cris hw/: Don't use CPUState
i386 hw/: Don't use CPUState
lm32 hw/: Don't use CPUState
m68k hw/: Don't use CPUState
microblaze hw/: Don't use CPUState
mips hw/: Don't use CPUState
ppc hw/: Don't use CPUState
s390x hw/: Don't use CPUState
sh4 hw/: Don't use CPUState
sparc hw/: Don't use CPUState
xtensa hw/: Don't use CPUState
Rename CPUState -> CPUArchState
qom: Introduce CPU class
Makefile.objs | 3 +
arm-semi.c | 10 +-
bsd-user/main.c | 14 +-
bsd-user/qemu.h | 12 +-
bsd-user/signal.c | 2 +-
configure | 1 +
cpu-all.h | 56 ++--
cpu-defs.h | 2 +-
cpu-exec.c | 20 +-
cpus.c | 76 +++---
darwin-user/main.c | 22 +-
darwin-user/qemu.h | 6 +-
darwin-user/signal.c | 8 +-
def-helper.h | 2 +-
disas.c | 4 +-
disas.h | 2 +-
dyngen-exec.h | 4 +-
exec-all.h | 38 ++--
exec.c | 114 +++++-----
gdbstub.c | 100 ++++----
gdbstub.h | 16 +-
gen-icount.h | 8 +-
hw/alpha_dp264.c | 2 +-
hw/alpha_sys.h | 2 +-
hw/alpha_typhoon.c | 14 +-
hw/an5206.c | 2 +-
hw/apic.h | 2 +-
hw/arm-misc.h | 8 +-
hw/arm_boot.c | 10 +-
hw/arm_pic.c | 4 +-
hw/armv7m.c | 4 +-
hw/axis_dev88.c | 2 +-
hw/cris-boot.c | 6 +-
hw/cris-boot.h | 2 +-
hw/cris_pic_cpu.c | 4 +-
hw/dummy_m68k.c | 2 +-
hw/etraxfs.h | 2 +-
hw/etraxfs_ser.c | 4 +-
hw/exynos4210.h | 2 +-
hw/grlib.h | 2 +-
hw/highbank.c | 8 +-
hw/integratorcp.c | 2 +-
hw/kvm/apic.c | 2 +-
hw/kvmvapic.c | 22 +-
hw/leon3.c | 10 +-
hw/lm32_boards.c | 12 +-
hw/mc146818rtc.c | 2 -
hw/mcf.h | 4 +-
hw/mcf5206.c | 4 +-
hw/mcf5208.c | 2 +-
hw/mcf_intc.c | 4 +-
hw/microblaze_boot.c | 10 +-
hw/microblaze_boot.h | 4 +-
hw/microblaze_pic_cpu.c | 4 +-
hw/microblaze_pic_cpu.h | 2 +-
hw/milkymist.c | 10 +-
hw/mips_cpudevs.h | 4 +-
hw/mips_fulong2e.c | 12 +-
hw/mips_int.c | 6 +-
hw/mips_jazz.c | 8 +-
hw/mips_malta.c | 12 +-
hw/mips_mipssim.c | 8 +-
hw/mips_r4k.c | 8 +-
hw/mips_timer.c | 20 +-
hw/mpc8544_guts.c | 2 +-
hw/musicpal.c | 2 +-
hw/omap.h | 2 +-
hw/omap1.c | 2 +-
hw/omap2.c | 2 +-
hw/pc.c | 22 +-
hw/petalogix_ml605_mmu.c | 4 +-
hw/petalogix_s3adsp1800_mmu.c | 4 +-
hw/ppc.c | 123 +++++-----
hw/ppc.h | 28 +-
hw/ppc405.h | 8 +-
hw/ppc405_uc.c | 50 ++---
hw/ppc440_bamboo.c | 8 +-
hw/ppc4xx.h | 8 +-
hw/ppc4xx_devs.c | 17 +-
hw/ppc_booke.c | 20 +-
hw/ppc_newworld.c | 11 +-
hw/ppc_oldworld.c | 11 +-
hw/ppc_prep.c | 13 +-
hw/ppce500_mpc8544ds.c | 16 +-
hw/ppce500_spin.c | 8 +-
hw/pxa.h | 6 +-
hw/pxa2xx.c | 2 +-
hw/pxa2xx_gpio.c | 4 +-
hw/pxa2xx_pic.c | 4 +-
hw/r2d.c | 8 +-
hw/realview.c | 2 +-
hw/s390-virtio-bus.c | 6 +-
hw/s390-virtio.c | 16 +-
hw/sh.h | 2 +-
hw/shix.c | 2 +-
hw/spapr.c | 17 +-
hw/spapr.h | 4 +-
hw/spapr_hcall.c | 42 ++--
hw/spapr_llan.c | 10 +-
hw/spapr_rtas.c | 4 +-
hw/spapr_vio.c | 12 +-
hw/spapr_vty.c | 4 +-
hw/strongarm.h | 2 +-
hw/sun4m.c | 16 +-
hw/sun4u.c | 26 +-
hw/versatilepb.c | 2 +-
hw/vexpress.c | 4 +-
hw/virtex_ml507.c | 12 +-
hw/vmport.c | 12 +-
hw/xen_machine_pv.c | 2 +-
hw/xics.c | 10 +-
hw/xilinx_zynq.c | 2 +-
hw/xtensa_lx60.c | 10 +-
hw/xtensa_pic.c | 16 +-
hw/xtensa_sim.c | 4 +-
include/qemu/cpu.h | 75 ++++++
kvm-all.c | 54 ++--
kvm-stub.c | 22 +-
kvm.h | 60 +++---
linux-user/elfload.c | 40 ++--
linux-user/m68k/syscall.h | 2 +-
linux-user/main.c | 44 ++--
linux-user/qemu.h | 14 +-
linux-user/signal.c | 217 +++++++++--------
linux-user/syscall.c | 30 ++--
m68k-semi.c | 4 +-
monitor.c | 544 ++++++++++++++++++++--------------------
poison.h | 2 +-
qom/Makefile | 1 +
qom/cpu.c | 58 +++++
softmmu-semi.h | 12 +-
target-alpha/cpu.h | 26 +-
target-alpha/helper.c | 18 +-
target-alpha/machine.c | 44 ++--
target-alpha/op_helper.c | 6 +-
target-alpha/translate.c | 56 ++--
target-arm/cpu.h | 12 +-
target-arm/helper.c | 120 +++++-----
target-arm/iwmmxt_helper.c | 66 +++---
target-arm/neon_helper.c | 88 ++++----
target-arm/op_helper.c | 6 +-
target-arm/translate.c | 104 ++++----
target-cris/cpu.h | 14 +-
target-cris/helper.c | 14 +-
target-cris/mmu.c | 14 +-
target-cris/mmu.h | 6 +-
target-cris/op_helper.c | 6 +-
target-cris/translate.c | 50 ++--
target-cris/translate_v10.c | 26 +-
target-i386/cpu.h | 36 ++--
target-i386/helper.c | 40 ++--
target-i386/kvm.c | 76 +++---
target-i386/machine.c | 172 +++++++-------
target-i386/op_helper.c | 34 ++--
target-i386/translate.c | 82 +++---
target-lm32/cpu.h | 31 ++--
target-lm32/helper.c | 18 +-
target-lm32/machine.c | 22 +-
target-lm32/op_helper.c | 4 +-
target-lm32/translate.c | 38 ++--
target-m68k/cpu.h | 18 +-
target-m68k/helper.c | 82 +++---
target-m68k/op_helper.c | 20 +-
target-m68k/translate.c | 16 +-
target-microblaze/cpu.h | 33 ++--
target-microblaze/helper.c | 10 +-
target-microblaze/mmu.c | 8 +-
target-microblaze/mmu.h | 6 +-
target-microblaze/op_helper.c | 8 +-
target-microblaze/translate.c | 54 ++--
target-mips/cpu.h | 42 ++--
target-mips/helper.c | 26 +-
target-mips/machine.c | 4 +-
target-mips/op_helper.c | 124 +++++-----
target-mips/translate.c | 360 ++++++++++++++--------------
target-ppc/cpu.h | 43 ++--
target-ppc/helper.c | 82 +++---
target-ppc/kvm.c | 38 ++--
target-ppc/kvm_ppc.h | 12 +-
target-ppc/machine.c | 4 +-
target-ppc/op_helper.c | 12 +-
target-ppc/translate.c | 78 +++---
target-ppc/translate_init.c | 42 ++--
target-s390x/cpu.h | 48 ++--
target-s390x/helper.c | 42 ++--
target-s390x/kvm.c | 56 ++--
target-s390x/op_helper.c | 70 +++---
target-s390x/translate.c | 56 ++--
target-sh4/cpu.h | 12 +-
target-sh4/helper.c | 28 +-
target-sh4/op_helper.c | 4 +-
target-sh4/translate.c | 50 ++--
target-sparc/cc_helper.c | 66 +++---
target-sparc/cpu.h | 64 +++---
target-sparc/cpu_init.c | 4 +-
target-sparc/fop_helper.c | 68 +++---
target-sparc/helper.c | 16 +-
target-sparc/int32_helper.c | 6 +-
target-sparc/int64_helper.c | 12 +-
target-sparc/ldst_helper.c | 16 +-
target-sparc/machine.c | 4 +-
target-sparc/mmu_helper.c | 28 +-
target-sparc/op_helper.c | 4 +-
target-sparc/translate.c | 80 +++---
target-sparc/win_helper.c | 58 +++---
target-unicore32/cpu.h | 32 ++--
target-unicore32/helper.c | 62 +++---
target-unicore32/op_helper.c | 8 +-
target-unicore32/translate.c | 60 +++---
target-xtensa/cpu.h | 46 ++--
target-xtensa/helper.c | 42 ++--
target-xtensa/op_helper.c | 30 ++--
target-xtensa/translate.c | 22 +-
tcg/arm/tcg-target.c | 22 +-
tcg/hppa/tcg-target.c | 8 +-
tcg/i386/tcg-target.c | 2 +-
tcg/ia64/tcg-target.c | 10 +-
tcg/mips/tcg-target.c | 14 +-
tcg/ppc/tcg-target.c | 4 +-
tcg/ppc64/tcg-target.c | 4 +-
tcg/s390/tcg-target.c | 8 +-
tcg/sparc/tcg-target.c | 4 +-
tcg/tci/tcg-target.c | 2 +-
tcg/tci/tcg-target.h | 2 +-
tci.c | 4 +-
translate-all.c | 4 +-
user-exec.c | 4 +-
xen-all.c | 4 +-
xtensa-semi.c | 2 +-
229 files changed, 3142 insertions(+), 2978 deletions(-)
create mode 100644 include/qemu/cpu.h
create mode 100644 qom/cpu.c
--
1.7.7
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
` (42 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf, Andreas Färber
From: Alexander Graf <agraf@suse.de>
On ppc405ep there is a register that allows for software to reset the
core, but not the whole system. Implement this reset using a reset
interrupt.
This gets rid of a bunch of #if 0'ed code.
Reported-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 2 --
hw/ppc.c | 13 ++-----------
hw/ppc405_uc.c | 16 ++--------------
target-ppc/cpu.h | 3 +++
4 files changed, 7 insertions(+), 27 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 2c2d24e..3d28053 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -339,11 +339,9 @@ int cpu_exec(CPUState *env)
}
}
#elif defined(TARGET_PPC)
-#if 0
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
cpu_reset(env);
}
-#endif
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
if (env->pending_interrupts == 0)
diff --git a/hw/ppc.c b/hw/ppc.c
index 59882e2..a9516f1 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -131,13 +131,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: reset the CPU\n", __func__);
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC6xx_INPUT_SRESET:
@@ -214,10 +208,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
case PPC970_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
-#if 0 // XXX: TOFIX
- LOG_IRQ("%s: reset the CPU\n", __func__);
- cpu_reset(env);
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC970_INPUT_SRESET:
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 98079fa..951b389 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -1769,13 +1769,7 @@ void ppc40x_core_reset (CPUState *env)
target_ulong dbsr;
printf("Reset PowerPC core\n");
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
@@ -1787,13 +1781,7 @@ void ppc40x_chip_reset (CPUState *env)
target_ulong dbsr;
printf("Reset PowerPC chip\n");
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fbcf488..ac753f3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2051,6 +2051,9 @@ enum {
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
};
+/* CPU should be reset next, restart from scratch afterwards */
+#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
+
/*****************************************************************************/
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset()
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:02 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
` (41 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
bsd-user/main.c | 2 +-
cpu-all.h | 2 +-
cpu-exec.c | 2 +-
darwin-user/main.c | 2 +-
hw/arm_boot.c | 2 +-
hw/armv7m.c | 2 +-
hw/cris-boot.c | 2 +-
hw/leon3.c | 2 +-
hw/lm32_boards.c | 2 +-
hw/microblaze_boot.c | 2 +-
hw/milkymist.c | 2 +-
hw/mips_fulong2e.c | 2 +-
hw/mips_jazz.c | 2 +-
hw/mips_malta.c | 2 +-
hw/mips_mipssim.c | 2 +-
hw/mips_r4k.c | 2 +-
hw/omap1.c | 2 +-
hw/omap2.c | 2 +-
hw/pc.c | 2 +-
hw/ppc440_bamboo.c | 2 +-
hw/ppc4xx_devs.c | 9 ++++++++-
hw/ppc_newworld.c | 9 ++++++++-
hw/ppc_oldworld.c | 9 ++++++++-
hw/ppc_prep.c | 9 ++++++++-
hw/ppce500_mpc8544ds.c | 4 ++--
hw/pxa2xx.c | 2 +-
hw/r2d.c | 2 +-
hw/spapr.c | 9 ++++++++-
hw/sun4m.c | 4 ++--
hw/sun4u.c | 2 +-
hw/virtex_ml507.c | 2 +-
hw/xtensa_lx60.c | 8 +++++---
hw/xtensa_sim.c | 2 +-
linux-user/main.c | 2 +-
linux-user/syscall.c | 2 +-
target-arm/helper.c | 4 ++--
target-cris/translate.c | 4 ++--
target-i386/helper.c | 4 ++--
target-lm32/helper.c | 4 ++--
target-m68k/helper.c | 4 ++--
target-microblaze/translate.c | 4 ++--
target-mips/helper.c | 2 +-
target-mips/translate.c | 4 ++--
target-ppc/helper.c | 2 +-
target-s390x/helper.c | 4 ++--
target-sh4/translate.c | 4 ++--
target-sparc/cpu_init.c | 2 +-
target-xtensa/helper.c | 2 +-
48 files changed, 98 insertions(+), 61 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index cdb0d0a..c3af395 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -917,7 +917,7 @@ int main(int argc, char **argv)
exit(1);
}
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
- cpu_reset(env);
+ cpu_state_reset(env);
#endif
thread_env = env;
diff --git a/cpu-all.h b/cpu-all.h
index 80e6d42..7586c0d 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -433,7 +433,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask);
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
void cpu_single_step(CPUState *env, int enabled);
-void cpu_reset(CPUState *s);
+void cpu_state_reset(CPUState *s);
int cpu_is_stopped(CPUState *env);
void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
diff --git a/cpu-exec.c b/cpu-exec.c
index 3d28053..2bf1735 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -340,7 +340,7 @@ int cpu_exec(CPUState *env)
}
#elif defined(TARGET_PPC)
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
- cpu_reset(env);
+ cpu_state_reset(env);
}
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
diff --git a/darwin-user/main.c b/darwin-user/main.c
index e1519c7..13c1f05 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -858,7 +858,7 @@ int main(int argc, char **argv)
/* NOTE: we need to init the CPU at this stage to get
qemu_host_page_size */
env = cpu_init(cpu_model);
- cpu_reset(env);
+ cpu_state_reset(env);
printf("Starting %s with qemu\n----------------\n", filename);
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index fc66910..23b3f0a 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -277,7 +277,7 @@ static void do_cpu_reset(void *opaque)
CPUState *env = opaque;
const struct arm_boot_info *info = env->boot_info;
- cpu_reset(env);
+ cpu_state_reset(env);
if (info) {
if (!info->is_linux) {
/* Jump to the entry point. */
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 6b80579..9cf96f4 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque)
{
- cpu_reset((CPUState *)opaque);
+ cpu_state_reset((CPUState *)opaque);
}
/* Init CPU and memory for a v7-M based board.
diff --git a/hw/cris-boot.c b/hw/cris-boot.c
index 37894f8..ade517d 100644
--- a/hw/cris-boot.c
+++ b/hw/cris-boot.c
@@ -34,7 +34,7 @@ static void main_cpu_reset(void *opaque)
li = env->load_info;
- cpu_reset(env);
+ cpu_state_reset(env);
if (!li) {
/* nothing more to do. */
diff --git a/hw/leon3.c b/hw/leon3.c
index 71d79a6..1dc5a02 100644
--- a/hw/leon3.c
+++ b/hw/leon3.c
@@ -51,7 +51,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
- cpu_reset(env);
+ cpu_state_reset(env);
env->halted = 0;
env->pc = s->entry;
diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index 3cdf120..51c8a0f 100644
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -56,7 +56,7 @@ static void main_cpu_reset(void *opaque)
ResetInfo *reset_info = opaque;
CPUState *env = reset_info->env;
- cpu_reset(env);
+ cpu_state_reset(env);
/* init defaults */
env->pc = (uint32_t)reset_info->bootstrap_pc;
diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c
index b2f96df..7ce04dc 100644
--- a/hw/microblaze_boot.c
+++ b/hw/microblaze_boot.c
@@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
env->regs[5] = boot_info.cmdline;
env->regs[7] = boot_info.fdt;
env->sregs[SR_PC] = boot_info.bootstrap_pc;
diff --git a/hw/milkymist.c b/hw/milkymist.c
index eaef0c2..7ec6554 100644
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -61,7 +61,7 @@ static void main_cpu_reset(void *opaque)
ResetInfo *reset_info = opaque;
CPUState *env = reset_info->env;
- cpu_reset(env);
+ cpu_state_reset(env);
/* init defaults */
env->pc = reset_info->bootstrap_pc;
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index e3ba9dd..2db8ba0 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
/* TODO: 2E reset stuff */
if (loaderparams.kernel_filename) {
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 2b4678e..d5f1b34 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -51,7 +51,7 @@ enum jazz_model_e
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
}
static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index b1563ed..887faea 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -746,7 +746,7 @@ static void malta_mips_config(CPUState *env)
static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
/* The bootloader does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index 76c95b2..1fe4ac5 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -107,7 +107,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
- cpu_reset(env);
+ cpu_state_reset(env);
env->active_tc.PC = s->vector & ~(target_ulong)1;
if (s->vector & 1) {
env->hflags |= MIPS_HFLAG_M16;
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 83401f0..96ad808 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -145,7 +145,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
- cpu_reset(env);
+ cpu_state_reset(env);
env->active_tc.PC = s->vector;
}
diff --git a/hw/omap1.c b/hw/omap1.c
index 1aa5f23..5317b9b 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque)
omap_lpg_reset(mpu->led[0]);
omap_lpg_reset(mpu->led[1]);
omap_clkm_reset(mpu);
- cpu_reset(mpu->env);
+ cpu_state_reset(mpu->env);
}
static const struct omap_map_s {
diff --git a/hw/omap2.c b/hw/omap2.c
index a6851b0..157defb 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque)
omap_mcspi_reset(mpu->mcspi[1]);
omap_i2c_reset(mpu->i2c[0]);
omap_i2c_reset(mpu->i2c[1]);
- cpu_reset(mpu->env);
+ cpu_state_reset(mpu->env);
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
diff --git a/hw/pc.c b/hw/pc.c
index bb9867b..aca4460 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -928,7 +928,7 @@ static void pc_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
env->halted = !cpu_is_bsp(env);
}
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index f86b168..835e36d 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
env->gpr[1] = (16<<20) - 8;
env->gpr[3] = FDT_ADDR;
env->nip = entry;
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 26040ac..2311162 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -38,6 +38,13 @@
# define LOG_UIC(...) do { } while (0)
#endif
+static void ppc4xx_reset(void *opaque)
+{
+ CPUState *env = opaque;
+
+ cpu_state_reset(env);
+}
+
/*****************************************************************************/
/* Generic PowerPC 4xx processor instantiation */
CPUState *ppc4xx_init (const char *cpu_model,
@@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
- qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+ qemu_register_reset(ppc4xx_reset, env);
return env;
}
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 506187b..fd8e21d 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -122,6 +122,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
+static void ppc_core99_reset(void *opaque)
+{
+ CPUState *env = opaque;
+
+ cpu_state_reset(env);
+}
+
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size,
const char *boot_device,
@@ -167,7 +174,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
}
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
- qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+ qemu_register_reset(ppc_core99_reset, env);
}
/* allocate RAM */
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 9295a34..085b825 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -66,6 +66,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
+static void ppc_heathrow_reset(void *opaque)
+{
+ CPUState *env = opaque;
+
+ cpu_state_reset(env);
+}
+
static void ppc_heathrow_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
@@ -105,7 +112,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
}
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
- qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+ qemu_register_reset(ppc_heathrow_reset, env);
}
/* allocate RAM */
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index eb43fb5..c5f2542 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -471,6 +471,13 @@ static void cpu_request_exit(void *opaque, int irq, int level)
}
}
+static void ppc_prep_reset(void *opaque)
+{
+ CPUState *env = opaque;
+
+ cpu_state_reset(env);
+}
+
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (ram_addr_t ram_size,
const char *boot_device,
@@ -525,7 +532,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
- qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
+ qemu_register_reset(ppc_prep_reset, env);
}
/* allocate RAM */
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index d69f78c..752aed9 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -198,7 +198,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
/* Secondary CPU starts in halted state for now. Needs to change when
implementing non-kernel boot. */
@@ -211,7 +211,7 @@ static void mpc8544ds_cpu_reset(void *opaque)
CPUState *env = opaque;
struct boot_info *bi = env->load_info;
- cpu_reset(env);
+ cpu_state_reset(env);
/* Set initial guest state. */
env->halted = 0;
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 1ab2701..f552877 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level)
PXA2xxState *s = (PXA2xxState *) opaque;
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
- cpu_reset(s->env);
+ cpu_state_reset(s->env);
/* TODO: reset peripherals */
}
}
diff --git a/hw/r2d.c b/hw/r2d.c
index c80f9e3..ae327a7 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque;
CPUState *env = s->env;
- cpu_reset(env);
+ cpu_state_reset(env);
env->pc = s->vector;
}
diff --git a/hw/spapr.c b/hw/spapr.c
index dffb6a2..3f9d87c 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -502,6 +502,13 @@ static void spapr_reset(void *opaque)
}
+static void spapr_cpu_reset(void *opaque)
+{
+ CPUState *env = opaque;
+
+ cpu_state_reset(env);
+}
+
/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size,
const char *boot_device,
@@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
}
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ);
- qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
+ qemu_register_reset(spapr_cpu_reset, env);
env->hreset_vector = 0x60;
env->hreset_excp_prefix = 0;
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 99fb219..4045740 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -283,7 +283,7 @@ static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
env->halted = 0;
}
@@ -291,7 +291,7 @@ static void secondary_cpu_reset(void *opaque)
{
CPUState *env = opaque;
- cpu_reset(env);
+ cpu_state_reset(env);
env->halted = 1;
}
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 423108f..8b043f2 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -376,7 +376,7 @@ static void main_cpu_reset(void *opaque)
CPUState *env = s->env;
static unsigned int nr_resets;
- cpu_reset(env);
+ cpu_state_reset(env);
cpu_timer_reset(env->tick);
cpu_timer_reset(env->stick);
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index f8d2b1b..e672490 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -109,7 +109,7 @@ static void main_cpu_reset(void *opaque)
CPUState *env = opaque;
struct boot_info *bi = env->load_info;
- cpu_reset(env);
+ cpu_state_reset(env);
/* Linux Kernel Parameters (passing device tree):
* r3: pointer to the fdt
* r4: 0
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 26112c3..80ba4d7 100644
--- a/hw/xtensa_lx60.c
+++ b/hw/xtensa_lx60.c
@@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
return cpu_get_phys_page_debug(env, addr);
}
-static void lx60_reset(void *env)
+static void lx60_reset(void *opaque)
{
- cpu_reset(env);
+ CPUState *env = opaque;
+
+ cpu_state_reset(env);
}
static void lx_init(const LxBoardDesc *board,
@@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board,
/* Need MMU initialized prior to ELF loading,
* so that ELF gets loaded into virtual addresses
*/
- cpu_reset(env);
+ cpu_state_reset(env);
}
ram = g_malloc(sizeof(*ram));
diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
index 104e5dc..445cfde 100644
--- a/hw/xtensa_sim.c
+++ b/hw/xtensa_sim.c
@@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
static void sim_reset(void *env)
{
- cpu_reset(env);
+ cpu_state_reset(env);
}
static void sim_init(ram_addr_t ram_size,
diff --git a/linux-user/main.c b/linux-user/main.c
index bd47489..01129f2 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3375,7 +3375,7 @@ int main(int argc, char **argv, char **envp)
exit(1);
}
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
- cpu_reset(env);
+ cpu_state_reset(env);
#endif
thread_env = env;
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 8a11213..29888bd 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4036,7 +4036,7 @@ static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp,
/* we create a new CPU instance. */
new_env = cpu_copy(env);
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
- cpu_reset(new_env);
+ cpu_state_reset(new_env);
#endif
/* Init regs that differ from the parent. */
cpu_clone_regs(new_env, newsp);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index abe1c30..13ff474 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -278,7 +278,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
}
}
-void cpu_reset(CPUARMState *env)
+void cpu_state_reset(CPUARMState *env)
{
uint32_t id;
uint32_t tmp = 0;
@@ -416,7 +416,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
env->cpu_model_str = cpu_model;
env->cp15.c0_cpuid = id;
- cpu_reset(env);
+ cpu_state_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index cbdc72c..f360c31 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3513,7 +3513,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
env->pregs[PR_VR] = vr_by_name(cpu_model);
cpu_exec_init(env);
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
if (tcg_initialized)
@@ -3573,7 +3573,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
return env;
}
-void cpu_reset (CPUCRISState *env)
+void cpu_state_reset(CPUCRISState *env)
{
uint32_t vr;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index af6bba2..0d84c27 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -27,7 +27,7 @@
//#define DEBUG_MMU
/* NOTE: must be called outside the CPU execute loop */
-void cpu_reset(CPUX86State *env)
+void cpu_state_reset(CPUState *env)
{
int i;
@@ -1281,7 +1281,7 @@ void do_cpu_init(CPUState *env)
int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
uint64_t pat = env->pat;
- cpu_reset(env);
+ cpu_state_reset(env);
env->interrupt_request = sipi;
env->pat = pat;
apic_init_reset(env->apic_state);
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 2637c03..6834401 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -212,7 +212,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
env->flags = 0;
cpu_exec_init(env);
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
if (!tcg_initialized) {
@@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
}
}
-void cpu_reset(CPUState *env)
+void cpu_state_reset(CPUState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index fa675bf..3647366 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -143,7 +143,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
return 0;
}
-void cpu_reset(CPUM68KState *env)
+void cpu_state_reset(CPUM68KState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -181,7 +181,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
return NULL;
}
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
return env;
}
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 725c2dd..e34e88d 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1897,7 +1897,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
env = g_malloc0(sizeof(CPUState));
cpu_exec_init(env);
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
@@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
return env;
}
-void cpu_reset (CPUState *env)
+void cpu_state_reset(CPUState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 7225616..4d1cf98 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -452,7 +452,7 @@ void do_interrupt (CPUState *env)
set_hflags_for_handler(env);
break;
case EXCP_RESET:
- cpu_reset(env);
+ cpu_state_reset(env);
break;
case EXCP_SRESET:
env->CP0_Status |= (1 << CP0St_SR);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8361d88..5061e78 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12708,12 +12708,12 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
fpu_init(env, def);
mvp_init(env, def);
mips_tcg_init();
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
return env;
}
-void cpu_reset (CPUMIPSState *env)
+void cpu_state_reset(CPUMIPSState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index bb76a8b..f4552e8 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3136,7 +3136,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
TARGET_FMT_lx "\n", RA, msr);
}
-void cpu_reset(CPUPPCState *env)
+void cpu_state_reset(CPUPPCState *env)
{
target_ulong msr;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index c0ec890..1a1cc0eb 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -95,7 +95,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
env->cpu_model_str = cpu_model;
env->cpu_num = cpu_num++;
env->ext_index = -1;
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
return env;
}
@@ -119,7 +119,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
#endif /* CONFIG_USER_ONLY */
-void cpu_reset(CPUS390XState *env)
+void cpu_state_reset(CPUS390XState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index dd0ee4b..c385de8 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -178,7 +178,7 @@ void cpu_dump_state(CPUState * env, FILE * f,
}
}
-void cpu_reset(CPUSH4State * env)
+void cpu_state_reset(CPUSH4State *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -279,7 +279,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
env->movcal_backup_tail = &(env->movcal_backup);
sh4_translate_init();
env->cpu_model_str = cpu_model;
- cpu_reset(env);
+ cpu_state_reset(env);
cpu_register(env, def);
qemu_init_vcpu(env);
return env;
diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
index c7269b5..bb8b761 100644
--- a/target-sparc/cpu_init.c
+++ b/target-sparc/cpu_init.c
@@ -23,7 +23,7 @@
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
-void cpu_reset(CPUSPARCState *env)
+void cpu_state_reset(CPUSPARCState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 42a559f..077c20a 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -35,7 +35,7 @@
static void reset_mmu(CPUState *env);
-void cpu_reset(CPUXtensaState *env)
+void cpu_state_reset(CPUXtensaState *env)
{
env->exception_taken = 0;
env->pc = env->config->exception_vector[EXC_RESET];
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:02 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
` (40 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Use CPUX86State etc. instead (hand-converted).
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
monitor.c | 488 ++++++++++++++++++++++++++++++------------------------------
1 files changed, 244 insertions(+), 244 deletions(-)
diff --git a/monitor.c b/monitor.c
index cbdfbad..e3b72ff 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2696,30 +2696,30 @@ static const MonitorDef monitor_defs[] = {
#ifdef TARGET_I386
#define SEG(name, seg) \
- { name, offsetof(CPUState, segs[seg].selector), NULL, MD_I32 },\
- { name ".base", offsetof(CPUState, segs[seg].base) },\
- { name ".limit", offsetof(CPUState, segs[seg].limit), NULL, MD_I32 },
+ { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
+ { name ".base", offsetof(CPUX86State, segs[seg].base) },\
+ { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
- { "eax", offsetof(CPUState, regs[0]) },
- { "ecx", offsetof(CPUState, regs[1]) },
- { "edx", offsetof(CPUState, regs[2]) },
- { "ebx", offsetof(CPUState, regs[3]) },
- { "esp|sp", offsetof(CPUState, regs[4]) },
- { "ebp|fp", offsetof(CPUState, regs[5]) },
- { "esi", offsetof(CPUState, regs[6]) },
- { "edi", offsetof(CPUState, regs[7]) },
+ { "eax", offsetof(CPUX86State, regs[0]) },
+ { "ecx", offsetof(CPUX86State, regs[1]) },
+ { "edx", offsetof(CPUX86State, regs[2]) },
+ { "ebx", offsetof(CPUX86State, regs[3]) },
+ { "esp|sp", offsetof(CPUX86State, regs[4]) },
+ { "ebp|fp", offsetof(CPUX86State, regs[5]) },
+ { "esi", offsetof(CPUX86State, regs[6]) },
+ { "edi", offsetof(CPUX86State, regs[7]) },
#ifdef TARGET_X86_64
- { "r8", offsetof(CPUState, regs[8]) },
- { "r9", offsetof(CPUState, regs[9]) },
- { "r10", offsetof(CPUState, regs[10]) },
- { "r11", offsetof(CPUState, regs[11]) },
- { "r12", offsetof(CPUState, regs[12]) },
- { "r13", offsetof(CPUState, regs[13]) },
- { "r14", offsetof(CPUState, regs[14]) },
- { "r15", offsetof(CPUState, regs[15]) },
+ { "r8", offsetof(CPUX86State, regs[8]) },
+ { "r9", offsetof(CPUX86State, regs[9]) },
+ { "r10", offsetof(CPUX86State, regs[10]) },
+ { "r11", offsetof(CPUX86State, regs[11]) },
+ { "r12", offsetof(CPUX86State, regs[12]) },
+ { "r13", offsetof(CPUX86State, regs[13]) },
+ { "r14", offsetof(CPUX86State, regs[14]) },
+ { "r15", offsetof(CPUX86State, regs[15]) },
#endif
- { "eflags", offsetof(CPUState, eflags) },
- { "eip", offsetof(CPUState, eip) },
+ { "eflags", offsetof(CPUX86State, eflags) },
+ { "eip", offsetof(CPUX86State, eip) },
SEG("cs", R_CS)
SEG("ds", R_DS)
SEG("es", R_ES)
@@ -2729,76 +2729,76 @@ static const MonitorDef monitor_defs[] = {
{ "pc", 0, monitor_get_pc, },
#elif defined(TARGET_PPC)
/* General purpose registers */
- { "r0", offsetof(CPUState, gpr[0]) },
- { "r1", offsetof(CPUState, gpr[1]) },
- { "r2", offsetof(CPUState, gpr[2]) },
- { "r3", offsetof(CPUState, gpr[3]) },
- { "r4", offsetof(CPUState, gpr[4]) },
- { "r5", offsetof(CPUState, gpr[5]) },
- { "r6", offsetof(CPUState, gpr[6]) },
- { "r7", offsetof(CPUState, gpr[7]) },
- { "r8", offsetof(CPUState, gpr[8]) },
- { "r9", offsetof(CPUState, gpr[9]) },
- { "r10", offsetof(CPUState, gpr[10]) },
- { "r11", offsetof(CPUState, gpr[11]) },
- { "r12", offsetof(CPUState, gpr[12]) },
- { "r13", offsetof(CPUState, gpr[13]) },
- { "r14", offsetof(CPUState, gpr[14]) },
- { "r15", offsetof(CPUState, gpr[15]) },
- { "r16", offsetof(CPUState, gpr[16]) },
- { "r17", offsetof(CPUState, gpr[17]) },
- { "r18", offsetof(CPUState, gpr[18]) },
- { "r19", offsetof(CPUState, gpr[19]) },
- { "r20", offsetof(CPUState, gpr[20]) },
- { "r21", offsetof(CPUState, gpr[21]) },
- { "r22", offsetof(CPUState, gpr[22]) },
- { "r23", offsetof(CPUState, gpr[23]) },
- { "r24", offsetof(CPUState, gpr[24]) },
- { "r25", offsetof(CPUState, gpr[25]) },
- { "r26", offsetof(CPUState, gpr[26]) },
- { "r27", offsetof(CPUState, gpr[27]) },
- { "r28", offsetof(CPUState, gpr[28]) },
- { "r29", offsetof(CPUState, gpr[29]) },
- { "r30", offsetof(CPUState, gpr[30]) },
- { "r31", offsetof(CPUState, gpr[31]) },
+ { "r0", offsetof(CPUPPCState, gpr[0]) },
+ { "r1", offsetof(CPUPPCState, gpr[1]) },
+ { "r2", offsetof(CPUPPCState, gpr[2]) },
+ { "r3", offsetof(CPUPPCState, gpr[3]) },
+ { "r4", offsetof(CPUPPCState, gpr[4]) },
+ { "r5", offsetof(CPUPPCState, gpr[5]) },
+ { "r6", offsetof(CPUPPCState, gpr[6]) },
+ { "r7", offsetof(CPUPPCState, gpr[7]) },
+ { "r8", offsetof(CPUPPCState, gpr[8]) },
+ { "r9", offsetof(CPUPPCState, gpr[9]) },
+ { "r10", offsetof(CPUPPCState, gpr[10]) },
+ { "r11", offsetof(CPUPPCState, gpr[11]) },
+ { "r12", offsetof(CPUPPCState, gpr[12]) },
+ { "r13", offsetof(CPUPPCState, gpr[13]) },
+ { "r14", offsetof(CPUPPCState, gpr[14]) },
+ { "r15", offsetof(CPUPPCState, gpr[15]) },
+ { "r16", offsetof(CPUPPCState, gpr[16]) },
+ { "r17", offsetof(CPUPPCState, gpr[17]) },
+ { "r18", offsetof(CPUPPCState, gpr[18]) },
+ { "r19", offsetof(CPUPPCState, gpr[19]) },
+ { "r20", offsetof(CPUPPCState, gpr[20]) },
+ { "r21", offsetof(CPUPPCState, gpr[21]) },
+ { "r22", offsetof(CPUPPCState, gpr[22]) },
+ { "r23", offsetof(CPUPPCState, gpr[23]) },
+ { "r24", offsetof(CPUPPCState, gpr[24]) },
+ { "r25", offsetof(CPUPPCState, gpr[25]) },
+ { "r26", offsetof(CPUPPCState, gpr[26]) },
+ { "r27", offsetof(CPUPPCState, gpr[27]) },
+ { "r28", offsetof(CPUPPCState, gpr[28]) },
+ { "r29", offsetof(CPUPPCState, gpr[29]) },
+ { "r30", offsetof(CPUPPCState, gpr[30]) },
+ { "r31", offsetof(CPUPPCState, gpr[31]) },
/* Floating point registers */
- { "f0", offsetof(CPUState, fpr[0]) },
- { "f1", offsetof(CPUState, fpr[1]) },
- { "f2", offsetof(CPUState, fpr[2]) },
- { "f3", offsetof(CPUState, fpr[3]) },
- { "f4", offsetof(CPUState, fpr[4]) },
- { "f5", offsetof(CPUState, fpr[5]) },
- { "f6", offsetof(CPUState, fpr[6]) },
- { "f7", offsetof(CPUState, fpr[7]) },
- { "f8", offsetof(CPUState, fpr[8]) },
- { "f9", offsetof(CPUState, fpr[9]) },
- { "f10", offsetof(CPUState, fpr[10]) },
- { "f11", offsetof(CPUState, fpr[11]) },
- { "f12", offsetof(CPUState, fpr[12]) },
- { "f13", offsetof(CPUState, fpr[13]) },
- { "f14", offsetof(CPUState, fpr[14]) },
- { "f15", offsetof(CPUState, fpr[15]) },
- { "f16", offsetof(CPUState, fpr[16]) },
- { "f17", offsetof(CPUState, fpr[17]) },
- { "f18", offsetof(CPUState, fpr[18]) },
- { "f19", offsetof(CPUState, fpr[19]) },
- { "f20", offsetof(CPUState, fpr[20]) },
- { "f21", offsetof(CPUState, fpr[21]) },
- { "f22", offsetof(CPUState, fpr[22]) },
- { "f23", offsetof(CPUState, fpr[23]) },
- { "f24", offsetof(CPUState, fpr[24]) },
- { "f25", offsetof(CPUState, fpr[25]) },
- { "f26", offsetof(CPUState, fpr[26]) },
- { "f27", offsetof(CPUState, fpr[27]) },
- { "f28", offsetof(CPUState, fpr[28]) },
- { "f29", offsetof(CPUState, fpr[29]) },
- { "f30", offsetof(CPUState, fpr[30]) },
- { "f31", offsetof(CPUState, fpr[31]) },
- { "fpscr", offsetof(CPUState, fpscr) },
+ { "f0", offsetof(CPUPPCState, fpr[0]) },
+ { "f1", offsetof(CPUPPCState, fpr[1]) },
+ { "f2", offsetof(CPUPPCState, fpr[2]) },
+ { "f3", offsetof(CPUPPCState, fpr[3]) },
+ { "f4", offsetof(CPUPPCState, fpr[4]) },
+ { "f5", offsetof(CPUPPCState, fpr[5]) },
+ { "f6", offsetof(CPUPPCState, fpr[6]) },
+ { "f7", offsetof(CPUPPCState, fpr[7]) },
+ { "f8", offsetof(CPUPPCState, fpr[8]) },
+ { "f9", offsetof(CPUPPCState, fpr[9]) },
+ { "f10", offsetof(CPUPPCState, fpr[10]) },
+ { "f11", offsetof(CPUPPCState, fpr[11]) },
+ { "f12", offsetof(CPUPPCState, fpr[12]) },
+ { "f13", offsetof(CPUPPCState, fpr[13]) },
+ { "f14", offsetof(CPUPPCState, fpr[14]) },
+ { "f15", offsetof(CPUPPCState, fpr[15]) },
+ { "f16", offsetof(CPUPPCState, fpr[16]) },
+ { "f17", offsetof(CPUPPCState, fpr[17]) },
+ { "f18", offsetof(CPUPPCState, fpr[18]) },
+ { "f19", offsetof(CPUPPCState, fpr[19]) },
+ { "f20", offsetof(CPUPPCState, fpr[20]) },
+ { "f21", offsetof(CPUPPCState, fpr[21]) },
+ { "f22", offsetof(CPUPPCState, fpr[22]) },
+ { "f23", offsetof(CPUPPCState, fpr[23]) },
+ { "f24", offsetof(CPUPPCState, fpr[24]) },
+ { "f25", offsetof(CPUPPCState, fpr[25]) },
+ { "f26", offsetof(CPUPPCState, fpr[26]) },
+ { "f27", offsetof(CPUPPCState, fpr[27]) },
+ { "f28", offsetof(CPUPPCState, fpr[28]) },
+ { "f29", offsetof(CPUPPCState, fpr[29]) },
+ { "f30", offsetof(CPUPPCState, fpr[30]) },
+ { "f31", offsetof(CPUPPCState, fpr[31]) },
+ { "fpscr", offsetof(CPUPPCState, fpscr) },
/* Next instruction pointer */
- { "nip|pc", offsetof(CPUState, nip) },
- { "lr", offsetof(CPUState, lr) },
- { "ctr", offsetof(CPUState, ctr) },
+ { "nip|pc", offsetof(CPUPPCState, nip) },
+ { "lr", offsetof(CPUPPCState, lr) },
+ { "ctr", offsetof(CPUPPCState, ctr) },
{ "decr", 0, &monitor_get_decr, },
{ "ccr", 0, &monitor_get_ccr, },
/* Machine state register */
@@ -2808,105 +2808,105 @@ static const MonitorDef monitor_defs[] = {
{ "tbl", 0, &monitor_get_tbl, },
#if defined(TARGET_PPC64)
/* Address space register */
- { "asr", offsetof(CPUState, asr) },
+ { "asr", offsetof(CPUPPCState, asr) },
#endif
/* Segment registers */
- { "sdr1", offsetof(CPUState, spr[SPR_SDR1]) },
- { "sr0", offsetof(CPUState, sr[0]) },
- { "sr1", offsetof(CPUState, sr[1]) },
- { "sr2", offsetof(CPUState, sr[2]) },
- { "sr3", offsetof(CPUState, sr[3]) },
- { "sr4", offsetof(CPUState, sr[4]) },
- { "sr5", offsetof(CPUState, sr[5]) },
- { "sr6", offsetof(CPUState, sr[6]) },
- { "sr7", offsetof(CPUState, sr[7]) },
- { "sr8", offsetof(CPUState, sr[8]) },
- { "sr9", offsetof(CPUState, sr[9]) },
- { "sr10", offsetof(CPUState, sr[10]) },
- { "sr11", offsetof(CPUState, sr[11]) },
- { "sr12", offsetof(CPUState, sr[12]) },
- { "sr13", offsetof(CPUState, sr[13]) },
- { "sr14", offsetof(CPUState, sr[14]) },
- { "sr15", offsetof(CPUState, sr[15]) },
+ { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
+ { "sr0", offsetof(CPUPPCState, sr[0]) },
+ { "sr1", offsetof(CPUPPCState, sr[1]) },
+ { "sr2", offsetof(CPUPPCState, sr[2]) },
+ { "sr3", offsetof(CPUPPCState, sr[3]) },
+ { "sr4", offsetof(CPUPPCState, sr[4]) },
+ { "sr5", offsetof(CPUPPCState, sr[5]) },
+ { "sr6", offsetof(CPUPPCState, sr[6]) },
+ { "sr7", offsetof(CPUPPCState, sr[7]) },
+ { "sr8", offsetof(CPUPPCState, sr[8]) },
+ { "sr9", offsetof(CPUPPCState, sr[9]) },
+ { "sr10", offsetof(CPUPPCState, sr[10]) },
+ { "sr11", offsetof(CPUPPCState, sr[11]) },
+ { "sr12", offsetof(CPUPPCState, sr[12]) },
+ { "sr13", offsetof(CPUPPCState, sr[13]) },
+ { "sr14", offsetof(CPUPPCState, sr[14]) },
+ { "sr15", offsetof(CPUPPCState, sr[15]) },
/* Too lazy to put BATs... */
- { "pvr", offsetof(CPUState, spr[SPR_PVR]) },
+ { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
- { "srr0", offsetof(CPUState, spr[SPR_SRR0]) },
- { "srr1", offsetof(CPUState, spr[SPR_SRR1]) },
- { "sprg0", offsetof(CPUState, spr[SPR_SPRG0]) },
- { "sprg1", offsetof(CPUState, spr[SPR_SPRG1]) },
- { "sprg2", offsetof(CPUState, spr[SPR_SPRG2]) },
- { "sprg3", offsetof(CPUState, spr[SPR_SPRG3]) },
- { "sprg4", offsetof(CPUState, spr[SPR_SPRG4]) },
- { "sprg5", offsetof(CPUState, spr[SPR_SPRG5]) },
- { "sprg6", offsetof(CPUState, spr[SPR_SPRG6]) },
- { "sprg7", offsetof(CPUState, spr[SPR_SPRG7]) },
- { "pid", offsetof(CPUState, spr[SPR_BOOKE_PID]) },
- { "csrr0", offsetof(CPUState, spr[SPR_BOOKE_CSRR0]) },
- { "csrr1", offsetof(CPUState, spr[SPR_BOOKE_CSRR1]) },
- { "esr", offsetof(CPUState, spr[SPR_BOOKE_ESR]) },
- { "dear", offsetof(CPUState, spr[SPR_BOOKE_DEAR]) },
- { "mcsr", offsetof(CPUState, spr[SPR_BOOKE_MCSR]) },
- { "tsr", offsetof(CPUState, spr[SPR_BOOKE_TSR]) },
- { "tcr", offsetof(CPUState, spr[SPR_BOOKE_TCR]) },
- { "vrsave", offsetof(CPUState, spr[SPR_VRSAVE]) },
- { "pir", offsetof(CPUState, spr[SPR_BOOKE_PIR]) },
- { "mcsrr0", offsetof(CPUState, spr[SPR_BOOKE_MCSRR0]) },
- { "mcsrr1", offsetof(CPUState, spr[SPR_BOOKE_MCSRR1]) },
- { "decar", offsetof(CPUState, spr[SPR_BOOKE_DECAR]) },
- { "ivpr", offsetof(CPUState, spr[SPR_BOOKE_IVPR]) },
- { "epcr", offsetof(CPUState, spr[SPR_BOOKE_EPCR]) },
- { "sprg8", offsetof(CPUState, spr[SPR_BOOKE_SPRG8]) },
- { "ivor0", offsetof(CPUState, spr[SPR_BOOKE_IVOR0]) },
- { "ivor1", offsetof(CPUState, spr[SPR_BOOKE_IVOR1]) },
- { "ivor2", offsetof(CPUState, spr[SPR_BOOKE_IVOR2]) },
- { "ivor3", offsetof(CPUState, spr[SPR_BOOKE_IVOR3]) },
- { "ivor4", offsetof(CPUState, spr[SPR_BOOKE_IVOR4]) },
- { "ivor5", offsetof(CPUState, spr[SPR_BOOKE_IVOR5]) },
- { "ivor6", offsetof(CPUState, spr[SPR_BOOKE_IVOR6]) },
- { "ivor7", offsetof(CPUState, spr[SPR_BOOKE_IVOR7]) },
- { "ivor8", offsetof(CPUState, spr[SPR_BOOKE_IVOR8]) },
- { "ivor9", offsetof(CPUState, spr[SPR_BOOKE_IVOR9]) },
- { "ivor10", offsetof(CPUState, spr[SPR_BOOKE_IVOR10]) },
- { "ivor11", offsetof(CPUState, spr[SPR_BOOKE_IVOR11]) },
- { "ivor12", offsetof(CPUState, spr[SPR_BOOKE_IVOR12]) },
- { "ivor13", offsetof(CPUState, spr[SPR_BOOKE_IVOR13]) },
- { "ivor14", offsetof(CPUState, spr[SPR_BOOKE_IVOR14]) },
- { "ivor15", offsetof(CPUState, spr[SPR_BOOKE_IVOR15]) },
- { "ivor32", offsetof(CPUState, spr[SPR_BOOKE_IVOR32]) },
- { "ivor33", offsetof(CPUState, spr[SPR_BOOKE_IVOR33]) },
- { "ivor34", offsetof(CPUState, spr[SPR_BOOKE_IVOR34]) },
- { "ivor35", offsetof(CPUState, spr[SPR_BOOKE_IVOR35]) },
- { "ivor36", offsetof(CPUState, spr[SPR_BOOKE_IVOR36]) },
- { "ivor37", offsetof(CPUState, spr[SPR_BOOKE_IVOR37]) },
- { "mas0", offsetof(CPUState, spr[SPR_BOOKE_MAS0]) },
- { "mas1", offsetof(CPUState, spr[SPR_BOOKE_MAS1]) },
- { "mas2", offsetof(CPUState, spr[SPR_BOOKE_MAS2]) },
- { "mas3", offsetof(CPUState, spr[SPR_BOOKE_MAS3]) },
- { "mas4", offsetof(CPUState, spr[SPR_BOOKE_MAS4]) },
- { "mas6", offsetof(CPUState, spr[SPR_BOOKE_MAS6]) },
- { "mas7", offsetof(CPUState, spr[SPR_BOOKE_MAS7]) },
- { "mmucfg", offsetof(CPUState, spr[SPR_MMUCFG]) },
- { "tlb0cfg", offsetof(CPUState, spr[SPR_BOOKE_TLB0CFG]) },
- { "tlb1cfg", offsetof(CPUState, spr[SPR_BOOKE_TLB1CFG]) },
- { "epr", offsetof(CPUState, spr[SPR_BOOKE_EPR]) },
- { "eplc", offsetof(CPUState, spr[SPR_BOOKE_EPLC]) },
- { "epsc", offsetof(CPUState, spr[SPR_BOOKE_EPSC]) },
- { "svr", offsetof(CPUState, spr[SPR_E500_SVR]) },
- { "mcar", offsetof(CPUState, spr[SPR_Exxx_MCAR]) },
- { "pid1", offsetof(CPUState, spr[SPR_BOOKE_PID1]) },
- { "pid2", offsetof(CPUState, spr[SPR_BOOKE_PID2]) },
- { "hid0", offsetof(CPUState, spr[SPR_HID0]) },
+ { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
+ { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
+ { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
+ { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
+ { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
+ { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
+ { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
+ { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
+ { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
+ { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
+ { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
+ { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
+ { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
+ { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
+ { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
+ { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
+ { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
+ { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
+ { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
+ { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
+ { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
+ { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
+ { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
+ { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
+ { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
+ { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
+ { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
+ { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
+ { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
+ { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
+ { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
+ { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
+ { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
+ { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
+ { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
+ { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
+ { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
+ { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
+ { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
+ { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
+ { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
+ { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
+ { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
+ { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
+ { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
+ { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
+ { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
+ { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
+ { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
+ { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
+ { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
+ { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
+ { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
+ { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
+ { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
+ { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
+ { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
+ { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
+ { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
+ { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
+ { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
+ { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
+ { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
+ { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
+ { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
+ { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
#elif defined(TARGET_SPARC)
- { "g0", offsetof(CPUState, gregs[0]) },
- { "g1", offsetof(CPUState, gregs[1]) },
- { "g2", offsetof(CPUState, gregs[2]) },
- { "g3", offsetof(CPUState, gregs[3]) },
- { "g4", offsetof(CPUState, gregs[4]) },
- { "g5", offsetof(CPUState, gregs[5]) },
- { "g6", offsetof(CPUState, gregs[6]) },
- { "g7", offsetof(CPUState, gregs[7]) },
+ { "g0", offsetof(CPUSPARCState, gregs[0]) },
+ { "g1", offsetof(CPUSPARCState, gregs[1]) },
+ { "g2", offsetof(CPUSPARCState, gregs[2]) },
+ { "g3", offsetof(CPUSPARCState, gregs[3]) },
+ { "g4", offsetof(CPUSPARCState, gregs[4]) },
+ { "g5", offsetof(CPUSPARCState, gregs[5]) },
+ { "g6", offsetof(CPUSPARCState, gregs[6]) },
+ { "g7", offsetof(CPUSPARCState, gregs[7]) },
{ "o0", 0, monitor_get_reg },
{ "o1", 1, monitor_get_reg },
{ "o2", 2, monitor_get_reg },
@@ -2931,72 +2931,72 @@ static const MonitorDef monitor_defs[] = {
{ "i5", 21, monitor_get_reg },
{ "i6", 22, monitor_get_reg },
{ "i7", 23, monitor_get_reg },
- { "pc", offsetof(CPUState, pc) },
- { "npc", offsetof(CPUState, npc) },
- { "y", offsetof(CPUState, y) },
+ { "pc", offsetof(CPUSPARCState, pc) },
+ { "npc", offsetof(CPUSPARCState, npc) },
+ { "y", offsetof(CPUSPARCState, y) },
#ifndef TARGET_SPARC64
{ "psr", 0, &monitor_get_psr, },
- { "wim", offsetof(CPUState, wim) },
+ { "wim", offsetof(CPUSPARCState, wim) },
#endif
- { "tbr", offsetof(CPUState, tbr) },
- { "fsr", offsetof(CPUState, fsr) },
- { "f0", offsetof(CPUState, fpr[0].l.upper) },
- { "f1", offsetof(CPUState, fpr[0].l.lower) },
- { "f2", offsetof(CPUState, fpr[1].l.upper) },
- { "f3", offsetof(CPUState, fpr[1].l.lower) },
- { "f4", offsetof(CPUState, fpr[2].l.upper) },
- { "f5", offsetof(CPUState, fpr[2].l.lower) },
- { "f6", offsetof(CPUState, fpr[3].l.upper) },
- { "f7", offsetof(CPUState, fpr[3].l.lower) },
- { "f8", offsetof(CPUState, fpr[4].l.upper) },
- { "f9", offsetof(CPUState, fpr[4].l.lower) },
- { "f10", offsetof(CPUState, fpr[5].l.upper) },
- { "f11", offsetof(CPUState, fpr[5].l.lower) },
- { "f12", offsetof(CPUState, fpr[6].l.upper) },
- { "f13", offsetof(CPUState, fpr[6].l.lower) },
- { "f14", offsetof(CPUState, fpr[7].l.upper) },
- { "f15", offsetof(CPUState, fpr[7].l.lower) },
- { "f16", offsetof(CPUState, fpr[8].l.upper) },
- { "f17", offsetof(CPUState, fpr[8].l.lower) },
- { "f18", offsetof(CPUState, fpr[9].l.upper) },
- { "f19", offsetof(CPUState, fpr[9].l.lower) },
- { "f20", offsetof(CPUState, fpr[10].l.upper) },
- { "f21", offsetof(CPUState, fpr[10].l.lower) },
- { "f22", offsetof(CPUState, fpr[11].l.upper) },
- { "f23", offsetof(CPUState, fpr[11].l.lower) },
- { "f24", offsetof(CPUState, fpr[12].l.upper) },
- { "f25", offsetof(CPUState, fpr[12].l.lower) },
- { "f26", offsetof(CPUState, fpr[13].l.upper) },
- { "f27", offsetof(CPUState, fpr[13].l.lower) },
- { "f28", offsetof(CPUState, fpr[14].l.upper) },
- { "f29", offsetof(CPUState, fpr[14].l.lower) },
- { "f30", offsetof(CPUState, fpr[15].l.upper) },
- { "f31", offsetof(CPUState, fpr[15].l.lower) },
+ { "tbr", offsetof(CPUSPARCState, tbr) },
+ { "fsr", offsetof(CPUSPARCState, fsr) },
+ { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
+ { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
+ { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
+ { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
+ { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
+ { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
+ { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
+ { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
+ { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
+ { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
+ { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
+ { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
+ { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
+ { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
+ { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
+ { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
+ { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
+ { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
+ { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
+ { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
+ { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
+ { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
+ { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
+ { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
+ { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
+ { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
+ { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
+ { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
+ { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
+ { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
+ { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
+ { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
#ifdef TARGET_SPARC64
- { "f32", offsetof(CPUState, fpr[16]) },
- { "f34", offsetof(CPUState, fpr[17]) },
- { "f36", offsetof(CPUState, fpr[18]) },
- { "f38", offsetof(CPUState, fpr[19]) },
- { "f40", offsetof(CPUState, fpr[20]) },
- { "f42", offsetof(CPUState, fpr[21]) },
- { "f44", offsetof(CPUState, fpr[22]) },
- { "f46", offsetof(CPUState, fpr[23]) },
- { "f48", offsetof(CPUState, fpr[24]) },
- { "f50", offsetof(CPUState, fpr[25]) },
- { "f52", offsetof(CPUState, fpr[26]) },
- { "f54", offsetof(CPUState, fpr[27]) },
- { "f56", offsetof(CPUState, fpr[28]) },
- { "f58", offsetof(CPUState, fpr[29]) },
- { "f60", offsetof(CPUState, fpr[30]) },
- { "f62", offsetof(CPUState, fpr[31]) },
- { "asi", offsetof(CPUState, asi) },
- { "pstate", offsetof(CPUState, pstate) },
- { "cansave", offsetof(CPUState, cansave) },
- { "canrestore", offsetof(CPUState, canrestore) },
- { "otherwin", offsetof(CPUState, otherwin) },
- { "wstate", offsetof(CPUState, wstate) },
- { "cleanwin", offsetof(CPUState, cleanwin) },
- { "fprs", offsetof(CPUState, fprs) },
+ { "f32", offsetof(CPUSPARCState, fpr[16]) },
+ { "f34", offsetof(CPUSPARCState, fpr[17]) },
+ { "f36", offsetof(CPUSPARCState, fpr[18]) },
+ { "f38", offsetof(CPUSPARCState, fpr[19]) },
+ { "f40", offsetof(CPUSPARCState, fpr[20]) },
+ { "f42", offsetof(CPUSPARCState, fpr[21]) },
+ { "f44", offsetof(CPUSPARCState, fpr[22]) },
+ { "f46", offsetof(CPUSPARCState, fpr[23]) },
+ { "f48", offsetof(CPUSPARCState, fpr[24]) },
+ { "f50", offsetof(CPUSPARCState, fpr[25]) },
+ { "f52", offsetof(CPUSPARCState, fpr[26]) },
+ { "f54", offsetof(CPUSPARCState, fpr[27]) },
+ { "f56", offsetof(CPUSPARCState, fpr[28]) },
+ { "f58", offsetof(CPUSPARCState, fpr[29]) },
+ { "f60", offsetof(CPUSPARCState, fpr[30]) },
+ { "f62", offsetof(CPUSPARCState, fpr[31]) },
+ { "asi", offsetof(CPUSPARCState, asi) },
+ { "pstate", offsetof(CPUSPARCState, pstate) },
+ { "cansave", offsetof(CPUSPARCState, cansave) },
+ { "canrestore", offsetof(CPUSPARCState, canrestore) },
+ { "otherwin", offsetof(CPUSPARCState, otherwin) },
+ { "wstate", offsetof(CPUSPARCState, wstate) },
+ { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
+ { "fprs", offsetof(CPUSPARCState, fprs) },
#endif
#endif
{ NULL },
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (2 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:03 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
` (39 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
gdbstub.c | 56 ++++++++++++++++++++++++++++----------------------------
1 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 7d470b6..054e16c 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -533,7 +533,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define IDX_XMM_REGS (IDX_FP_REGS + 16)
#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
@@ -590,7 +590,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
+static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
{
uint16_t selector = ldl_p(mem_buf);
@@ -615,7 +615,7 @@ static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
return 4;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -703,7 +703,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GDB_CORE_XML "power-core.xml"
#endif
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
@@ -740,7 +740,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
@@ -801,7 +801,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GET_REGA(val) GET_REGL(val)
#endif
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* g0..g7 */
@@ -860,7 +860,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
#if defined(TARGET_ABI32)
abi_ulong tmp;
@@ -944,7 +944,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 26
#define GDB_CORE_XML "arm-core.xml"
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
if (n < 16) {
/* Core integer register. */
@@ -971,7 +971,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1014,7 +1014,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GDB_CORE_XML "cf-core.xml"
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* D0-D7 */
@@ -1033,7 +1033,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1058,7 +1058,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 73
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REGL(env->active_tc.gpr[n]);
@@ -1104,7 +1104,7 @@ static unsigned int ieee_rm[] =
#define RESTORE_ROUNDING_MODE \
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
target_ulong tmp;
@@ -1163,7 +1163,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 59
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
@@ -1197,7 +1197,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1244,7 +1244,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS (32 + 5)
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
@@ -1254,7 +1254,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1275,7 +1275,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 49
static int
-read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
+read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
{
if (n < 15) {
GET_REG32(env->regs[n]);
@@ -1307,7 +1307,7 @@ read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint8_t srs;
@@ -1337,7 +1337,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1370,7 +1370,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 67
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
uint64_t val;
CPU_DoubleU d;
@@ -1404,7 +1404,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
GET_REGL(val);
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
target_ulong tmp = ldtul_p(mem_buf);
CPU_DoubleU d;
@@ -1440,7 +1440,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS S390_NUM_TOTAL_REGS
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
switch (n) {
case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
@@ -1464,7 +1464,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
target_ulong tmpl;
uint32_t tmp32;
@@ -1494,7 +1494,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#include "hw/lm32_pic.h"
#define NUM_CORE_REGS (32 + 7)
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
@@ -1527,7 +1527,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1573,7 +1573,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
#define num_g_regs NUM_CORE_REGS
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
@@ -1610,7 +1610,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
}
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (3 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:04 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState Andreas Färber
` (38 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-lm32/cpu.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index b6b6b4c..cc9b53b 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -28,6 +28,7 @@
#include "qemu-common.h"
#include "cpu-defs.h"
struct CPULM32State;
+typedef struct CPULM32State CPULM32State;
#define TARGET_HAS_ICE 1
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (4 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
` (37 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-microblaze/cpu.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 4092506..94ec43b 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -29,6 +29,7 @@
#include "cpu-defs.h"
#include "softfloat.h"
struct CPUMBState;
+typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (5 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
` (36 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Will be needed for qemu_irq_ack callback.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sparc/cpu.h | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 38a7074..8098669 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -378,7 +378,9 @@ struct QEMUFile;
void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
-typedef struct CPUSPARCState {
+typedef struct CPUSPARCState CPUSPARCState;
+
+struct CPUSPARCState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
target_ulong pc; /* program counter */
@@ -503,7 +505,7 @@ typedef struct CPUSPARCState {
/* Leon3 cache control */
uint32_t cache_control;
-} CPUSPARCState;
+};
#ifndef NO_CPU_IO_DEFS
/* cpu_init.c */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (6 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:05 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
` (35 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
This aids in refactoring CPUState by adopting the common naming scheme.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu.h | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index f725634..923db05 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -18,7 +18,7 @@
#define ELF_MACHINE EM_UNICORE32
-#define CPUState struct CPUState_UniCore32
+#define CPUState struct CPUUniCore32State
#include "config.h"
#include "qemu-common.h"
@@ -27,7 +27,7 @@
#define NB_MMU_MODES 2
-typedef struct CPUState_UniCore32 {
+typedef struct CPUUniCore32State {
/* Regs for current mode. */
uint32_t regs[32];
/* Frequently accessed ASR bits are stored separately for efficiently.
@@ -71,7 +71,7 @@ typedef struct CPUState_UniCore32 {
/* Internal CPU feature flags. */
uint32_t features;
-} CPUState_UniCore32;
+} CPUUniCore32State;
#define ASR_M (0x1f)
#define ASR_MODE_USER (0x10)
@@ -179,7 +179,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
void uc32_translate_init(void);
void do_interrupt(CPUState *);
-void switch_mode(CPUState_UniCore32 *, int);
+void switch_mode(CPUUniCore32State *, int);
static inline bool cpu_has_work(CPUState *env)
{
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (7 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:07 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
` (34 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
pc.h and apic.h are not needed; apic.h would drag in x86 CPUState and
is now included directly for TARGET_I386.
isa.h is already #included from mc146818rtc.h.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/mc146818rtc.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index 8b5cf8c..2b59c36 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -24,8 +24,6 @@
#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
-#include "pc.h"
-#include "isa.h"
#include "mc146818rtc.h"
#ifdef TARGET_I386
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (8 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:08 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: " Andreas Färber
` (33 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
In target-specific code use CPU*State.
While at it, fix indentation on those lines.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
linux-user/elfload.c | 24 +++---
linux-user/m68k/syscall.h | 2 +-
linux-user/main.c | 28 +++---
linux-user/signal.c | 201 +++++++++++++++++++++++----------------------
4 files changed, 131 insertions(+), 124 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 2fd4a93..48e3232 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -157,7 +157,7 @@ typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
*
* See linux kernel: arch/x86/include/asm/elf.h
*/
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *env)
{
(*regs)[0] = env->regs[15];
(*regs)[1] = env->regs[14];
@@ -229,7 +229,7 @@ typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
*
* See linux kernel: arch/x86/include/asm/elf.h
*/
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *env)
{
(*regs)[0] = env->regs[R_EBX];
(*regs)[1] = env->regs[R_ECX];
@@ -288,7 +288,7 @@ static inline void init_thread(struct target_pt_regs *regs,
#define ELF_NREG 18
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUARMState *env)
{
(*regs)[0] = tswapl(env->regs[0]);
(*regs)[1] = tswapl(env->regs[1]);
@@ -307,7 +307,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
(*regs)[14] = tswapl(env->regs[14]);
(*regs)[15] = tswapl(env->regs[15]);
- (*regs)[16] = tswapl(cpsr_read((CPUState *)env));
+ (*regs)[16] = tswapl(cpsr_read((CPUARMState *)env));
(*regs)[17] = tswapl(env->regs[0]); /* XXX */
}
@@ -410,7 +410,7 @@ static inline void init_thread(struct target_pt_regs *regs,
#define ELF_NREG 34
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUUniCore32State *env)
{
(*regs)[0] = env->regs[0];
(*regs)[1] = env->regs[1];
@@ -445,7 +445,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
(*regs)[30] = env->regs[30];
(*regs)[31] = env->regs[31];
- (*regs)[32] = cpu_asr_read((CPUState *)env);
+ (*regs)[32] = cpu_asr_read((CPUUniCore32State *)env);
(*regs)[33] = env->regs[0]; /* XXX */
}
@@ -572,7 +572,7 @@ enum {
static uint32_t get_elf_hwcap(void)
{
- CPUState *e = thread_env;
+ CPUPPCState *e = thread_env;
uint32_t features = 0;
/* We don't have to be terribly complete here; the high points are
@@ -628,7 +628,7 @@ static inline void init_thread(struct target_pt_regs *_regs, struct image_info *
#define ELF_NREG 48
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *env)
{
int i;
target_ulong ccr = 0;
@@ -697,7 +697,7 @@ enum {
};
/* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *env)
{
int i;
@@ -749,7 +749,7 @@ static inline void init_thread(struct target_pt_regs *regs,
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
/* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env)
{
int i, pos = 0;
@@ -797,7 +797,7 @@ enum {
};
static inline void elf_core_copy_regs(target_elf_gregset_t *regs,
- const CPUState *env)
+ const CPUSH4State *env)
{
int i;
@@ -862,7 +862,7 @@ static inline void init_thread(struct target_pt_regs *regs,
#define ELF_NREG 20
typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
-static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
+static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUM68KState *env)
{
(*regs)[0] = tswapl(env->dregs[1]);
(*regs)[1] = tswapl(env->dregs[2]);
diff --git a/linux-user/m68k/syscall.h b/linux-user/m68k/syscall.h
index 2fd85dd..2618793 100644
--- a/linux-user/m68k/syscall.h
+++ b/linux-user/m68k/syscall.h
@@ -18,4 +18,4 @@ struct target_pt_regs {
#define UNAME_MACHINE "m68k"
-void do_m68k_simcall(CPUState *, int);
+void do_m68k_simcall(CPUM68KState *, int);
diff --git a/linux-user/main.c b/linux-user/main.c
index 01129f2..3b48882 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -71,7 +71,7 @@ void gemu_log(const char *fmt, ...)
}
#if defined(TARGET_I386)
-int cpu_get_pic_interrupt(CPUState *env)
+int cpu_get_pic_interrupt(CPUX86State *env)
{
return -1;
}
@@ -247,7 +247,7 @@ void cpu_list_unlock(void)
/***********************************************************/
/* CPUX86 core interface */
-void cpu_smm_update(CPUState *env)
+void cpu_smm_update(CPUX86State *env)
{
}
@@ -889,7 +889,7 @@ void cpu_loop(CPUARMState *env)
#ifdef TARGET_UNICORE32
-void cpu_loop(CPUState *env)
+void cpu_loop(CPUUniCore32State *env)
{
int trapnr;
unsigned int n, insn;
@@ -1226,36 +1226,36 @@ void cpu_loop (CPUSPARCState *env)
#endif
#ifdef TARGET_PPC
-static inline uint64_t cpu_ppc_get_tb (CPUState *env)
+static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
{
/* TO FIX */
return 0;
}
-uint64_t cpu_ppc_load_tbl (CPUState *env)
+uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
{
return cpu_ppc_get_tb(env);
}
-uint32_t cpu_ppc_load_tbu (CPUState *env)
+uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
{
return cpu_ppc_get_tb(env) >> 32;
}
-uint64_t cpu_ppc_load_atbl (CPUState *env)
+uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
{
return cpu_ppc_get_tb(env);
}
-uint32_t cpu_ppc_load_atbu (CPUState *env)
+uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
{
return cpu_ppc_get_tb(env) >> 32;
}
-uint32_t cpu_ppc601_load_rtcu (CPUState *env)
+uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
-uint32_t cpu_ppc601_load_rtcl (CPUState *env)
+uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
{
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
@@ -2276,7 +2276,7 @@ done_syscall:
#endif
#ifdef TARGET_SH4
-void cpu_loop (CPUState *env)
+void cpu_loop(CPUSH4State *env)
{
int trapnr, ret;
target_siginfo_t info;
@@ -2335,7 +2335,7 @@ void cpu_loop (CPUState *env)
#endif
#ifdef TARGET_CRIS
-void cpu_loop (CPUState *env)
+void cpu_loop(CPUCRISState *env)
{
int trapnr, ret;
target_siginfo_t info;
@@ -2393,7 +2393,7 @@ void cpu_loop (CPUState *env)
#endif
#ifdef TARGET_MICROBLAZE
-void cpu_loop (CPUState *env)
+void cpu_loop(CPUMBState *env)
{
int trapnr, ret;
target_siginfo_t info;
@@ -2630,7 +2630,7 @@ static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
queue_signal(env, TARGET_SIGSEGV, &info);
}
-void cpu_loop (CPUState *env)
+void cpu_loop(CPUAlphaState *env)
{
int trapnr;
target_siginfo_t info;
diff --git a/linux-user/signal.c b/linux-user/signal.c
index cefd2ff..f44f78e 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1205,14 +1205,14 @@ static const abi_ulong retcodes[4] = {
#define __get_user_error(x,p,e) __get_user(x, p)
-static inline int valid_user_regs(CPUState *regs)
+static inline int valid_user_regs(CPUARMState *regs)
{
return 1;
}
static void
setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
- CPUState *env, abi_ulong mask)
+ CPUARMState *env, abi_ulong mask)
{
__put_user(env->regs[0], &sc->arm_r0);
__put_user(env->regs[1], &sc->arm_r1);
@@ -1241,7 +1241,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
}
static inline abi_ulong
-get_sigframe(struct target_sigaction *ka, CPUState *regs, int framesize)
+get_sigframe(struct target_sigaction *ka, CPUARMState *regs, int framesize)
{
unsigned long sp = regs->regs[13];
@@ -1257,7 +1257,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, int framesize)
}
static int
-setup_return(CPUState *env, struct target_sigaction *ka,
+setup_return(CPUARMState *env, struct target_sigaction *ka,
abi_ulong *rc, abi_ulong frame_addr, int usig, abi_ulong rc_addr)
{
abi_ulong handler = ka->_sa_handler;
@@ -1295,7 +1295,7 @@ setup_return(CPUState *env, struct target_sigaction *ka,
return 0;
}
-static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUState *env)
+static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUARMState *env)
{
int i;
struct target_vfp_sigframe *vfpframe;
@@ -1312,7 +1312,8 @@ static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUState *env)
return (abi_ulong*)(vfpframe+1);
}
-static abi_ulong *setup_sigframe_v2_iwmmxt(abi_ulong *regspace, CPUState *env)
+static abi_ulong *setup_sigframe_v2_iwmmxt(abi_ulong *regspace,
+ CPUARMState *env)
{
int i;
struct target_iwmmxt_sigframe *iwmmxtframe;
@@ -1332,7 +1333,7 @@ static abi_ulong *setup_sigframe_v2_iwmmxt(abi_ulong *regspace, CPUState *env)
}
static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUARMState *env)
{
struct target_sigaltstack stack;
int i;
@@ -1367,7 +1368,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
/* compare linux/arch/arm/kernel/signal.c:setup_frame() */
static void setup_frame_v1(int usig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *regs)
+ target_sigset_t *set, CPUARMState *regs)
{
struct sigframe_v1 *frame;
abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame));
@@ -1391,7 +1392,7 @@ end:
}
static void setup_frame_v2(int usig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *regs)
+ target_sigset_t *set, CPUARMState *regs)
{
struct sigframe_v2 *frame;
abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame));
@@ -1408,7 +1409,7 @@ static void setup_frame_v2(int usig, struct target_sigaction *ka,
}
static void setup_frame(int usig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *regs)
+ target_sigset_t *set, CPUARMState *regs)
{
if (get_osversion() >= 0x020612) {
setup_frame_v2(usig, ka, set, regs);
@@ -1420,7 +1421,7 @@ static void setup_frame(int usig, struct target_sigaction *ka,
/* compare linux/arch/arm/kernel/signal.c:setup_rt_frame() */
static void setup_rt_frame_v1(int usig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUARMState *env)
{
struct rt_sigframe_v1 *frame;
abi_ulong frame_addr = get_sigframe(ka, env, sizeof(*frame));
@@ -1464,7 +1465,7 @@ end:
static void setup_rt_frame_v2(int usig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUARMState *env)
{
struct rt_sigframe_v2 *frame;
abi_ulong frame_addr = get_sigframe(ka, env, sizeof(*frame));
@@ -1490,7 +1491,7 @@ static void setup_rt_frame_v2(int usig, struct target_sigaction *ka,
static void setup_rt_frame(int usig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUARMState *env)
{
if (get_osversion() >= 0x020612) {
setup_rt_frame_v2(usig, ka, info, set, env);
@@ -1500,7 +1501,7 @@ static void setup_rt_frame(int usig, struct target_sigaction *ka,
}
static int
-restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
+restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
{
int err = 0;
uint32_t cpsr;
@@ -1531,7 +1532,7 @@ restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
return err;
}
-static long do_sigreturn_v1(CPUState *env)
+static long do_sigreturn_v1(CPUARMState *env)
{
abi_ulong frame_addr;
struct sigframe_v1 *frame;
@@ -1578,7 +1579,7 @@ badframe:
return 0;
}
-static abi_ulong *restore_sigframe_v2_vfp(CPUState *env, abi_ulong *regspace)
+static abi_ulong *restore_sigframe_v2_vfp(CPUARMState *env, abi_ulong *regspace)
{
int i;
abi_ulong magic, sz;
@@ -1608,7 +1609,8 @@ static abi_ulong *restore_sigframe_v2_vfp(CPUState *env, abi_ulong *regspace)
return (abi_ulong*)(vfpframe + 1);
}
-static abi_ulong *restore_sigframe_v2_iwmmxt(CPUState *env, abi_ulong *regspace)
+static abi_ulong *restore_sigframe_v2_iwmmxt(CPUARMState *env,
+ abi_ulong *regspace)
{
int i;
abi_ulong magic, sz;
@@ -1632,7 +1634,7 @@ static abi_ulong *restore_sigframe_v2_iwmmxt(CPUState *env, abi_ulong *regspace)
return (abi_ulong*)(iwmmxtframe + 1);
}
-static int do_sigframe_return_v2(CPUState *env, target_ulong frame_addr,
+static int do_sigframe_return_v2(CPUARMState *env, target_ulong frame_addr,
struct target_ucontext_v2 *uc)
{
sigset_t host_set;
@@ -1671,7 +1673,7 @@ static int do_sigframe_return_v2(CPUState *env, target_ulong frame_addr,
return 0;
}
-static long do_sigreturn_v2(CPUState *env)
+static long do_sigreturn_v2(CPUARMState *env)
{
abi_ulong frame_addr;
struct sigframe_v2 *frame;
@@ -1700,7 +1702,7 @@ badframe:
return 0;
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUARMState *env)
{
if (get_osversion() >= 0x020612) {
return do_sigreturn_v2(env);
@@ -1709,7 +1711,7 @@ long do_sigreturn(CPUState *env)
}
}
-static long do_rt_sigreturn_v1(CPUState *env)
+static long do_rt_sigreturn_v1(CPUARMState *env)
{
abi_ulong frame_addr;
struct rt_sigframe_v1 *frame;
@@ -1750,7 +1752,7 @@ badframe:
return 0;
}
-static long do_rt_sigreturn_v2(CPUState *env)
+static long do_rt_sigreturn_v2(CPUARMState *env)
{
abi_ulong frame_addr;
struct rt_sigframe_v2 *frame;
@@ -1779,7 +1781,7 @@ badframe:
return 0;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUARMState *env)
{
if (get_osversion() >= 0x020612) {
return do_rt_sigreturn_v2(env);
@@ -1888,7 +1890,8 @@ struct target_rt_signal_frame {
#define UREG_SP UREG_O6
static inline abi_ulong get_sigframe(struct target_sigaction *sa,
- CPUState *env, unsigned long framesize)
+ CPUSPARCState *env,
+ unsigned long framesize)
{
abi_ulong sp;
@@ -1904,7 +1907,7 @@ static inline abi_ulong get_sigframe(struct target_sigaction *sa,
}
static int
-setup___siginfo(__siginfo_t *si, CPUState *env, abi_ulong mask)
+setup___siginfo(__siginfo_t *si, CPUSPARCState *env, abi_ulong mask)
{
int err = 0, i;
@@ -1925,7 +1928,7 @@ setup___siginfo(__siginfo_t *si, CPUState *env, abi_ulong mask)
#if 0
static int
setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
- CPUState *env, unsigned long mask)
+ CPUSPARCState *env, unsigned long mask)
{
int err = 0;
@@ -1943,7 +1946,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
#define NF_ALIGNEDSZ (((sizeof(struct target_signal_frame) + 7) & (~7)))
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUSPARCState *env)
{
abi_ulong sf_addr;
struct target_signal_frame *sf;
@@ -2032,7 +2035,7 @@ sigsegv:
force_sig(TARGET_SIGSEGV);
}
static inline int
-restore_fpu_state(CPUState *env, qemu_siginfo_fpu_t *fpu)
+restore_fpu_state(CPUSPARCState *env, qemu_siginfo_fpu_t *fpu)
{
int err;
#if 0
@@ -2073,12 +2076,12 @@ restore_fpu_state(CPUState *env, qemu_siginfo_fpu_t *fpu)
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUSPARCState *env)
{
fprintf(stderr, "setup_rt_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUSPARCState *env)
{
abi_ulong sf_addr;
struct target_signal_frame *sf;
@@ -2151,7 +2154,7 @@ segv_and_exit:
force_sig(TARGET_SIGSEGV);
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUSPARCState *env)
{
fprintf(stderr, "do_rt_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
@@ -2427,25 +2430,25 @@ void sparc64_get_context(CPUSPARCState *env)
# warning signal handling not implemented
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMIPSState *env)
{
fprintf(stderr, "setup_frame: not implemented\n");
}
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMIPSState *env)
{
fprintf(stderr, "setup_rt_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUMIPSState *env)
{
fprintf(stderr, "do_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUMIPSState *env)
{
fprintf(stderr, "do_rt_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
@@ -2456,25 +2459,25 @@ long do_rt_sigreturn(CPUState *env)
# warning signal handling not implemented
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMIPSState *env)
{
fprintf(stderr, "setup_frame: not implemented\n");
}
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMIPSState *env)
{
fprintf(stderr, "setup_rt_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUMIPSState *env)
{
fprintf(stderr, "do_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUMIPSState *env)
{
fprintf(stderr, "do_rt_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
@@ -2546,7 +2549,7 @@ static inline int install_sigtramp(unsigned int *tramp, unsigned int syscall)
}
static inline int
-setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
+setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
{
int err = 0;
@@ -2621,7 +2624,7 @@ setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
}
static inline int
-restore_sigcontext(CPUState *regs, struct target_sigcontext *sc)
+restore_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
{
int err = 0;
@@ -2692,7 +2695,7 @@ restore_sigcontext(CPUState *regs, struct target_sigcontext *sc)
* Determine which stack to use..
*/
static inline abi_ulong
-get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
+get_sigframe(struct target_sigaction *ka, CPUMIPSState *regs, size_t frame_size)
{
unsigned long sp;
@@ -2716,7 +2719,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
/* compare linux/arch/mips/kernel/signal.c:setup_frame() */
static void setup_frame(int sig, struct target_sigaction * ka,
- target_sigset_t *set, CPUState *regs)
+ target_sigset_t *set, CPUMIPSState *regs)
{
struct sigframe *frame;
abi_ulong frame_addr;
@@ -2764,7 +2767,7 @@ give_sigsegv:
return;
}
-long do_sigreturn(CPUState *regs)
+long do_sigreturn(CPUMIPSState *regs)
{
struct sigframe *frame;
abi_ulong frame_addr;
@@ -2815,7 +2818,7 @@ badframe:
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMIPSState *env)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr;
@@ -2873,7 +2876,7 @@ give_sigsegv:
return;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUMIPSState *env)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr;
@@ -2974,7 +2977,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
}
static int setup_sigcontext(struct target_sigcontext *sc,
- CPUState *regs, unsigned long mask)
+ CPUSH4State *regs, unsigned long mask)
{
int err = 0;
int i;
@@ -3005,7 +3008,7 @@ static int setup_sigcontext(struct target_sigcontext *sc,
return err;
}
-static int restore_sigcontext(CPUState *regs, struct target_sigcontext *sc,
+static int restore_sigcontext(CPUSH4State *regs, struct target_sigcontext *sc,
target_ulong *r0_p)
{
unsigned int err = 0;
@@ -3037,7 +3040,7 @@ static int restore_sigcontext(CPUState *regs, struct target_sigcontext *sc,
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *regs)
+ target_sigset_t *set, CPUSH4State *regs)
{
struct target_sigframe *frame;
abi_ulong frame_addr;
@@ -3089,7 +3092,7 @@ give_sigsegv:
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *regs)
+ target_sigset_t *set, CPUSH4State *regs)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr;
@@ -3150,7 +3153,7 @@ give_sigsegv:
force_sig(TARGET_SIGSEGV);
}
-long do_sigreturn(CPUState *regs)
+long do_sigreturn(CPUSH4State *regs)
{
struct target_sigframe *frame;
abi_ulong frame_addr;
@@ -3190,7 +3193,7 @@ badframe:
return 0;
}
-long do_rt_sigreturn(CPUState *regs)
+long do_rt_sigreturn(CPUSH4State *regs)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr;
@@ -3257,7 +3260,7 @@ struct rt_signal_frame {
uint32_t tramp[2];
};
-static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
+static void setup_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
{
__put_user(env->regs[0], &sc->regs.r0);
__put_user(env->regs[1], &sc->regs.r1);
@@ -3294,7 +3297,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
__put_user(env->sregs[SR_PC], &sc->regs.pc);
}
-static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
+static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
{
__get_user(env->regs[0], &sc->regs.r0);
__get_user(env->regs[1], &sc->regs.r1);
@@ -3332,7 +3335,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
}
static abi_ulong get_sigframe(struct target_sigaction *ka,
- CPUState *env, int frame_size)
+ CPUMBState *env, int frame_size)
{
abi_ulong sp = env->regs[1];
@@ -3343,7 +3346,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMBState *env)
{
struct target_signal_frame *frame;
abi_ulong frame_addr;
@@ -3409,12 +3412,12 @@ static void setup_frame(int sig, struct target_sigaction *ka,
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUMBState *env)
{
fprintf(stderr, "Microblaze setup_rt_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUMBState *env)
{
struct target_signal_frame *frame;
abi_ulong frame_addr;
@@ -3449,7 +3452,7 @@ long do_sigreturn(CPUState *env)
force_sig(TARGET_SIGSEGV);
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUMBState *env)
{
fprintf(stderr, "Microblaze do_rt_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
@@ -3478,7 +3481,7 @@ struct rt_signal_frame {
uint8_t retcode[8]; /* Trampoline code. */
};
-static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
+static void setup_sigcontext(struct target_sigcontext *sc, CPUCRISState *env)
{
__put_user(env->regs[0], &sc->regs.r0);
__put_user(env->regs[1], &sc->regs.r1);
@@ -3501,7 +3504,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
__put_user(env->pc, &sc->regs.erp);
}
-static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
+static void restore_sigcontext(struct target_sigcontext *sc, CPUCRISState *env)
{
__get_user(env->regs[0], &sc->regs.r0);
__get_user(env->regs[1], &sc->regs.r1);
@@ -3524,7 +3527,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
__get_user(env->pc, &sc->regs.erp);
}
-static abi_ulong get_sigframe(CPUState *env, int framesize)
+static abi_ulong get_sigframe(CPUCRISState *env, int framesize)
{
abi_ulong sp;
/* Align the stack downwards to 4. */
@@ -3533,7 +3536,7 @@ static abi_ulong get_sigframe(CPUState *env, int framesize)
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUCRISState *env)
{
struct target_signal_frame *frame;
abi_ulong frame_addr;
@@ -3584,12 +3587,12 @@ static void setup_frame(int sig, struct target_sigaction *ka,
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUCRISState *env)
{
fprintf(stderr, "CRIS setup_rt_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUCRISState *env)
{
struct target_signal_frame *frame;
abi_ulong frame_addr;
@@ -3620,7 +3623,7 @@ long do_sigreturn(CPUState *env)
force_sig(TARGET_SIGSEGV);
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUCRISState *env)
{
fprintf(stderr, "CRIS do_rt_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
@@ -3687,7 +3690,7 @@ typedef struct {
} rt_sigframe;
static inline abi_ulong
-get_sigframe(struct target_sigaction *ka, CPUState *env, size_t frame_size)
+get_sigframe(struct target_sigaction *ka, CPUS390XState *env, size_t frame_size)
{
abi_ulong sp;
@@ -3712,7 +3715,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *env, size_t frame_size)
return (sp - frame_size) & -8ul;
}
-static void save_sigregs(CPUState *env, target_sigregs *sregs)
+static void save_sigregs(CPUS390XState *env, target_sigregs *sregs)
{
int i;
//save_access_regs(current->thread.acrs); FIXME
@@ -3738,7 +3741,7 @@ static void save_sigregs(CPUState *env, target_sigregs *sregs)
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUS390XState *env)
{
sigframe *frame;
abi_ulong frame_addr;
@@ -3805,7 +3808,7 @@ give_sigsegv:
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUS390XState *env)
{
int i;
rt_sigframe *frame;
@@ -3869,7 +3872,7 @@ give_sigsegv:
}
static int
-restore_sigregs(CPUState *env, target_sigregs *sc)
+restore_sigregs(CPUS390XState *env, target_sigregs *sc)
{
int err = 0;
int i;
@@ -3895,7 +3898,7 @@ restore_sigregs(CPUState *env, target_sigregs *sc)
return err;
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUS390XState *env)
{
sigframe *frame;
abi_ulong frame_addr = env->regs[15];
@@ -3927,7 +3930,7 @@ badframe:
return 0;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUS390XState *env)
{
rt_sigframe *frame;
abi_ulong frame_addr = env->regs[15];
@@ -4107,7 +4110,7 @@ struct target_rt_sigframe {
/* See arch/powerpc/kernel/signal.c. */
static target_ulong get_sigframe(struct target_sigaction *ka,
- CPUState *env,
+ CPUPPCState *env,
int frame_size)
{
target_ulong oldsp, newsp;
@@ -4125,7 +4128,7 @@ static target_ulong get_sigframe(struct target_sigaction *ka,
return newsp;
}
-static int save_user_regs(CPUState *env, struct target_mcontext *frame,
+static int save_user_regs(CPUPPCState *env, struct target_mcontext *frame,
int sigret)
{
target_ulong msr = env->msr;
@@ -4221,7 +4224,7 @@ static int save_user_regs(CPUState *env, struct target_mcontext *frame,
return 0;
}
-static int restore_user_regs(CPUState *env,
+static int restore_user_regs(CPUPPCState *env,
struct target_mcontext *frame, int sig)
{
target_ulong save_r2 = 0;
@@ -4320,7 +4323,7 @@ static int restore_user_regs(CPUState *env,
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUPPCState *env)
{
struct target_sigframe *frame;
struct target_sigcontext *sc;
@@ -4382,7 +4385,7 @@ sigsegv:
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUPPCState *env)
{
struct target_rt_sigframe *rt_sf;
struct target_mcontext *frame;
@@ -4450,7 +4453,7 @@ sigsegv:
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUPPCState *env)
{
struct target_sigcontext *sc = NULL;
struct target_mcontext *sr = NULL;
@@ -4493,7 +4496,7 @@ sigsegv:
}
/* See arch/powerpc/kernel/signal_32.c. */
-static int do_setcontext(struct target_ucontext *ucp, CPUState *env, int sig)
+static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
{
struct target_mcontext *mcp;
target_ulong mcp_addr;
@@ -4528,7 +4531,7 @@ sigsegv:
#endif
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUPPCState *env)
{
struct target_rt_sigframe *rt_sf = NULL;
target_ulong rt_sf_addr;
@@ -4617,7 +4620,8 @@ struct target_rt_sigframe
};
static int
-setup_sigcontext(struct target_sigcontext *sc, CPUState *env, abi_ulong mask)
+setup_sigcontext(struct target_sigcontext *sc, CPUM68KState *env,
+ abi_ulong mask)
{
int err = 0;
@@ -4634,7 +4638,7 @@ setup_sigcontext(struct target_sigcontext *sc, CPUState *env, abi_ulong mask)
}
static int
-restore_sigcontext(CPUState *env, struct target_sigcontext *sc, int *pd0)
+restore_sigcontext(CPUM68KState *env, struct target_sigcontext *sc, int *pd0)
{
int err = 0;
int temp;
@@ -4656,7 +4660,8 @@ restore_sigcontext(CPUState *env, struct target_sigcontext *sc, int *pd0)
* Determine which stack to use..
*/
static inline abi_ulong
-get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
+get_sigframe(struct target_sigaction *ka, CPUM68KState *regs,
+ size_t frame_size)
{
unsigned long sp;
@@ -4671,7 +4676,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUM68KState *env)
{
struct target_sigframe *frame;
abi_ulong frame_addr;
@@ -4725,7 +4730,7 @@ give_sigsegv:
}
static inline int target_rt_setup_ucontext(struct target_ucontext *uc,
- CPUState *env)
+ CPUM68KState *env)
{
target_greg_t *gregs = uc->tuc_mcontext.gregs;
int err;
@@ -4753,7 +4758,7 @@ static inline int target_rt_setup_ucontext(struct target_ucontext *uc,
return err;
}
-static inline int target_rt_restore_ucontext(CPUState *env,
+static inline int target_rt_restore_ucontext(CPUM68KState *env,
struct target_ucontext *uc,
int *pd0)
{
@@ -4795,7 +4800,7 @@ badframe:
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUM68KState *env)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr;
@@ -4866,7 +4871,7 @@ give_sigsegv:
force_sig(TARGET_SIGSEGV);
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUM68KState *env)
{
struct target_sigframe *frame;
abi_ulong frame_addr = env->aregs[7] - 4;
@@ -4904,7 +4909,7 @@ badframe:
return 0;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUM68KState *env)
{
struct target_rt_sigframe *frame;
abi_ulong frame_addr = env->aregs[7] - 4;
@@ -4985,7 +4990,7 @@ struct target_rt_sigframe {
#define INSN_LDI_R0 0x201f0000
#define INSN_CALLSYS 0x00000083
-static int setup_sigcontext(struct target_sigcontext *sc, CPUState *env,
+static int setup_sigcontext(struct target_sigcontext *sc, CPUAlphaState *env,
abi_ulong frame_addr, target_sigset_t *set)
{
int i, err = 0;
@@ -5013,7 +5018,8 @@ static int setup_sigcontext(struct target_sigcontext *sc, CPUState *env,
return err;
}
-static int restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
+static int restore_sigcontext(CPUAlphaState *env,
+ struct target_sigcontext *sc)
{
uint64_t fpcr;
int i, err = 0;
@@ -5034,7 +5040,8 @@ static int restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
}
static inline abi_ulong get_sigframe(struct target_sigaction *sa,
- CPUState *env, unsigned long framesize)
+ CPUAlphaState *env,
+ unsigned long framesize)
{
abi_ulong sp = env->ir[IR_SP];
@@ -5046,7 +5053,7 @@ static inline abi_ulong get_sigframe(struct target_sigaction *sa,
}
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUAlphaState *env)
{
abi_ulong frame_addr, r26;
struct target_sigframe *frame;
@@ -5090,7 +5097,7 @@ static void setup_frame(int sig, struct target_sigaction *ka,
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUAlphaState *env)
{
abi_ulong frame_addr, r26;
struct target_rt_sigframe *frame;
@@ -5144,7 +5151,7 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
env->ir[IR_SP] = frame_addr;
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUAlphaState *env)
{
struct target_sigcontext *sc;
abi_ulong sc_addr = env->ir[IR_A0];
@@ -5174,7 +5181,7 @@ long do_sigreturn(CPUState *env)
force_sig(TARGET_SIGSEGV);
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUAlphaState *env)
{
abi_ulong frame_addr = env->ir[IR_A0];
struct target_rt_sigframe *frame;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (9 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: " Andreas Färber
` (32 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Use CPU*State where applicable.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
darwin-user/main.c | 14 +++++++-------
darwin-user/signal.c | 4 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/darwin-user/main.c b/darwin-user/main.c
index 13c1f05..f5cadc7 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -77,38 +77,38 @@ int cpu_get_pic_interrupt(CPUState *env)
}
#ifdef TARGET_PPC
-static inline uint64_t cpu_ppc_get_tb (CPUState *env)
+static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
{
/* TO FIX */
return 0;
}
-uint64_t cpu_ppc_load_tbl (CPUState *env)
+uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
{
return cpu_ppc_get_tb(env);
}
-uint32_t cpu_ppc_load_tbu (CPUState *env)
+uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
{
return cpu_ppc_get_tb(env) >> 32;
}
-uint64_t cpu_ppc_load_atbl (CPUState *env)
+uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
{
return cpu_ppc_get_tb(env);
}
-uint32_t cpu_ppc_load_atbu (CPUState *env)
+uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
{
return cpu_ppc_get_tb(env) >> 32;
}
-uint32_t cpu_ppc601_load_rtcu (CPUState *env)
+uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
{
cpu_ppc_load_tbu(env);
}
-uint32_t cpu_ppc601_load_rtcl (CPUState *env)
+uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
{
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
diff --git a/darwin-user/signal.c b/darwin-user/signal.c
index 317ef92..8f9705d 100644
--- a/darwin-user/signal.c
+++ b/darwin-user/signal.c
@@ -315,7 +315,7 @@ get_sigframe(struct emulated_sigaction *ka, CPUX86State *env, size_t frame_size)
}
static void setup_frame(int sig, struct emulated_sigaction *ka,
- void *set, CPUState *env)
+ void *set, CPUX86State *env)
{
void *frame;
@@ -336,7 +336,7 @@ give_sigsegv:
force_sig(SIGSEGV /* , current */);
}
-long do_sigreturn(CPUState *env, int num)
+long do_sigreturn(CPUX86State *env, int num)
{
int i = 0;
struct target_sigcontext *scp = get_int_arg(&i, env);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (10 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
` (31 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Use CPU*State where applicable.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
bsd-user/main.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index c3af395..78533d5 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -63,7 +63,7 @@ void gemu_log(const char *fmt, ...)
}
#if defined(TARGET_I386)
-int cpu_get_pic_interrupt(CPUState *env)
+int cpu_get_pic_interrupt(CPUX86State *env)
{
return -1;
}
@@ -109,7 +109,7 @@ void cpu_list_unlock(void)
/***********************************************************/
/* CPUX86 core interface */
-void cpu_smm_update(CPUState *env)
+void cpu_smm_update(CPUX86State *env)
{
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (11 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-13 18:10 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
` (30 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUAlphaState/g" target-alpha/*.[hc]
sed -i "s/#define CPUAlphaState/#define CPUState/" target-alpha/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-alpha/cpu.h | 24 ++++++++++----------
target-alpha/helper.c | 18 +++++++-------
target-alpha/machine.c | 44 ++++++++++++++++++------------------
target-alpha/op_helper.c | 6 ++--
target-alpha/translate.c | 56 +++++++++++++++++++++++-----------------------
5 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 5cd6fd8..ecc2a35 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -375,7 +375,7 @@ enum {
PS_USER_MODE = 8
};
-static inline int cpu_mmu_index(CPUState *env)
+static inline int cpu_mmu_index(CPUAlphaState *env)
{
if (env->pal_mode) {
return MMU_KERNEL_IDX;
@@ -430,16 +430,16 @@ int cpu_alpha_exec(CPUAlphaState *s);
is returned if the signal was handled by the virtual CPU. */
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
void *puc);
-int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
+int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
-void do_interrupt (CPUState *env);
+void do_interrupt (CPUAlphaState *env);
-uint64_t cpu_alpha_load_fpcr (CPUState *env);
-void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
+uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
+void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
#ifndef CONFIG_USER_ONLY
-void swap_shadow_regs(CPUState *env);
-QEMU_NORETURN void cpu_unassigned_access(CPUState *env1,
+void swap_shadow_regs(CPUAlphaState *env);
+QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
target_phys_addr_t addr, int is_write,
int is_exec, int unused, int size);
#endif
@@ -459,7 +459,7 @@ enum {
TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
};
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
target_ulong *cs_base, int *pflags)
{
int flags = 0;
@@ -481,7 +481,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
{
if (newsp) {
env->ir[IR_SP] = newsp;
@@ -490,13 +490,13 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->ir[IR_A3] = 0;
}
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
{
env->unique = newtls;
}
#endif
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUAlphaState *env)
{
/* Here we are checking to see if the CPU should wake up from HALT.
We will have gotten into this state only for WTINT from PALmode. */
@@ -513,7 +513,7 @@ static inline bool cpu_has_work(CPUState *env)
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 06d2565..3f2e7c3 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -24,7 +24,7 @@
#include "cpu.h"
#include "softfloat.h"
-uint64_t cpu_alpha_load_fpcr (CPUState *env)
+uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
{
uint64_t r = 0;
uint8_t t;
@@ -94,7 +94,7 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env)
return r;
}
-void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
+void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
{
uint8_t t;
@@ -159,7 +159,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
}
#if defined(CONFIG_USER_ONLY)
-int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, target_ulong address, int rw,
int mmu_idx)
{
env->exception_index = EXCP_MMFAULT;
@@ -167,7 +167,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
return 1;
}
#else
-void swap_shadow_regs(CPUState *env)
+void swap_shadow_regs(CPUAlphaState *env)
{
uint64_t i0, i1, i2, i3, i4, i5, i6, i7;
@@ -200,7 +200,7 @@ void swap_shadow_regs(CPUState *env)
}
/* Returns the OSF/1 entMM failure indication, or -1 on success. */
-static int get_physical_address(CPUState *env, target_ulong addr,
+static int get_physical_address(CPUAlphaState *env, target_ulong addr,
int prot_need, int mmu_idx,
target_ulong *pphys, int *pprot)
{
@@ -306,7 +306,7 @@ static int get_physical_address(CPUState *env, target_ulong addr,
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr)
{
target_ulong phys;
int prot, fail;
@@ -315,7 +315,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return (fail >= 0 ? -1 : phys);
}
-int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
+int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw,
int mmu_idx)
{
target_ulong phys;
@@ -336,7 +336,7 @@ int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
}
#endif /* USER_ONLY */
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUAlphaState *env)
{
int i = env->exception_index;
@@ -453,7 +453,7 @@ void do_interrupt (CPUState *env)
#endif /* !USER_ONLY */
}
-void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state (CPUAlphaState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
static const char *linux_reg_names[] = {
diff --git a/target-alpha/machine.c b/target-alpha/machine.c
index 76d70d9..1c9edd1 100644
--- a/target-alpha/machine.c
+++ b/target-alpha/machine.c
@@ -21,8 +21,8 @@ static const VMStateInfo vmstate_fpcr = {
};
static VMStateField vmstate_cpu_fields[] = {
- VMSTATE_UINTTL_ARRAY(ir, CPUState, 31),
- VMSTATE_UINTTL_ARRAY(fir, CPUState, 31),
+ VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
+ VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
/* Save the architecture value of the fpcr, not the internally
expanded version. Since this architecture value does not
exist in memory to be stored, this requires a but of hoop
@@ -37,33 +37,33 @@ static VMStateField vmstate_cpu_fields[] = {
.flags = VMS_SINGLE,
.offset = 0
},
- VMSTATE_UINTTL(pc, CPUState),
- VMSTATE_UINTTL(unique, CPUState),
- VMSTATE_UINTTL(lock_addr, CPUState),
- VMSTATE_UINTTL(lock_value, CPUState),
+ VMSTATE_UINTTL(pc, CPUAlphaState),
+ VMSTATE_UINTTL(unique, CPUAlphaState),
+ VMSTATE_UINTTL(lock_addr, CPUAlphaState),
+ VMSTATE_UINTTL(lock_value, CPUAlphaState),
/* Note that lock_st_addr is not saved; it is a temporary
used during the execution of the st[lq]_c insns. */
- VMSTATE_UINT8(ps, CPUState),
- VMSTATE_UINT8(intr_flag, CPUState),
- VMSTATE_UINT8(pal_mode, CPUState),
- VMSTATE_UINT8(fen, CPUState),
+ VMSTATE_UINT8(ps, CPUAlphaState),
+ VMSTATE_UINT8(intr_flag, CPUAlphaState),
+ VMSTATE_UINT8(pal_mode, CPUAlphaState),
+ VMSTATE_UINT8(fen, CPUAlphaState),
- VMSTATE_UINT32(pcc_ofs, CPUState),
+ VMSTATE_UINT32(pcc_ofs, CPUAlphaState),
- VMSTATE_UINTTL(trap_arg0, CPUState),
- VMSTATE_UINTTL(trap_arg1, CPUState),
- VMSTATE_UINTTL(trap_arg2, CPUState),
+ VMSTATE_UINTTL(trap_arg0, CPUAlphaState),
+ VMSTATE_UINTTL(trap_arg1, CPUAlphaState),
+ VMSTATE_UINTTL(trap_arg2, CPUAlphaState),
- VMSTATE_UINTTL(exc_addr, CPUState),
- VMSTATE_UINTTL(palbr, CPUState),
- VMSTATE_UINTTL(ptbr, CPUState),
- VMSTATE_UINTTL(vptptr, CPUState),
- VMSTATE_UINTTL(sysval, CPUState),
- VMSTATE_UINTTL(usp, CPUState),
+ VMSTATE_UINTTL(exc_addr, CPUAlphaState),
+ VMSTATE_UINTTL(palbr, CPUAlphaState),
+ VMSTATE_UINTTL(ptbr, CPUAlphaState),
+ VMSTATE_UINTTL(vptptr, CPUAlphaState),
+ VMSTATE_UINTTL(sysval, CPUAlphaState),
+ VMSTATE_UINTTL(usp, CPUAlphaState),
- VMSTATE_UINTTL_ARRAY(shadow, CPUState, 8),
- VMSTATE_UINTTL_ARRAY(scratch, CPUState, 24),
+ VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8),
+ VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24),
VMSTATE_END_OF_LIST()
};
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index cc102db..c77f009 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1329,7 +1329,7 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
helper_excp(EXCP_UNALIGN, 0);
}
-void QEMU_NORETURN cpu_unassigned_access(CPUState *env1,
+void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1,
target_phys_addr_t addr, int is_write,
int is_exec, int unused, int size)
{
@@ -1360,10 +1360,10 @@ void QEMU_NORETURN cpu_unassigned_access(CPUState *env1,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUAlphaState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
- CPUState *saved_env;
+ CPUAlphaState *saved_env;
int ret;
saved_env = env;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1d2142b..b51fe5c 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -105,35 +105,35 @@ static void alpha_translate_init(void)
for (i = 0; i < 31; i++) {
sprintf(p, "ir%d", i);
cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, ir[i]), p);
+ offsetof(CPUAlphaState, ir[i]), p);
p += (i < 10) ? 4 : 5;
sprintf(p, "fir%d", i);
cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, fir[i]), p);
+ offsetof(CPUAlphaState, fir[i]), p);
p += (i < 10) ? 5 : 6;
}
cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, pc), "pc");
+ offsetof(CPUAlphaState, pc), "pc");
cpu_lock_addr = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, lock_addr),
+ offsetof(CPUAlphaState, lock_addr),
"lock_addr");
cpu_lock_st_addr = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, lock_st_addr),
+ offsetof(CPUAlphaState, lock_st_addr),
"lock_st_addr");
cpu_lock_value = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, lock_value),
+ offsetof(CPUAlphaState, lock_value),
"lock_value");
cpu_unique = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, unique), "unique");
+ offsetof(CPUAlphaState, unique), "unique");
#ifndef CONFIG_USER_ONLY
cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, sysval), "sysval");
+ offsetof(CPUAlphaState, sysval), "sysval");
cpu_usp = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, usp), "usp");
+ offsetof(CPUAlphaState, usp), "usp");
#endif
/* register helpers */
@@ -611,7 +611,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
tcg_gen_movi_i32(tmp, float_round_down);
break;
case QUAL_RM_D:
- tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round));
+ tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_dyn_round));
break;
}
@@ -620,7 +620,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
sets the one field. */
tcg_gen_st8_i32(tmp, cpu_env,
- offsetof(CPUState, fp_status.float_rounding_mode));
+ offsetof(CPUAlphaState, fp_status.float_rounding_mode));
#else
gen_helper_setroundmode(tmp);
#endif
@@ -641,7 +641,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
tmp = tcg_temp_new_i32();
if (fn11) {
/* Underflow is enabled, use the FPCR setting. */
- tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_zero));
+ tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_flush_to_zero));
} else {
/* Underflow is disabled, force flush-to-zero. */
tcg_gen_movi_i32(tmp, 1);
@@ -649,7 +649,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
#if defined(CONFIG_SOFTFLOAT_INLINE)
tcg_gen_st8_i32(tmp, cpu_env,
- offsetof(CPUState, fp_status.flush_to_zero));
+ offsetof(CPUAlphaState, fp_status.flush_to_zero));
#else
gen_helper_setflushzero(tmp);
#endif
@@ -677,7 +677,7 @@ static void gen_fp_exc_clear(void)
#if defined(CONFIG_SOFTFLOAT_INLINE)
TCGv_i32 zero = tcg_const_i32(0);
tcg_gen_st8_i32(zero, cpu_env,
- offsetof(CPUState, fp_status.float_exception_flags));
+ offsetof(CPUAlphaState, fp_status.float_exception_flags));
tcg_temp_free_i32(zero);
#else
gen_helper_fp_exc_clear();
@@ -696,7 +696,7 @@ static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore)
#if defined(CONFIG_SOFTFLOAT_INLINE)
tcg_gen_ld8u_i32(exc, cpu_env,
- offsetof(CPUState, fp_status.float_exception_flags));
+ offsetof(CPUAlphaState, fp_status.float_exception_flags));
#else
gen_helper_fp_exc_get(exc);
#endif
@@ -1456,11 +1456,11 @@ static void gen_rx(int ra, int set)
TCGv_i32 tmp;
if (ra != 31) {
- tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_flag));
+ tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUAlphaState, intr_flag));
}
tmp = tcg_const_i32(set);
- tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag));
+ tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag));
tcg_temp_free_i32(tmp);
}
@@ -1504,7 +1504,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
break;
case 0x2D:
/* WRVPTPTR */
- tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vptptr));
+ tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUAlphaState, vptptr));
break;
case 0x31:
/* WRVAL */
@@ -1521,19 +1521,19 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
/* Note that we already know we're in kernel mode, so we know
that PS only contains the 3 IPL bits. */
- tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
+ tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps));
/* But make sure and store only the 3 IPL bits from the user. */
tmp = tcg_temp_new();
tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK);
- tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps));
+ tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps));
tcg_temp_free(tmp);
break;
}
case 0x36:
/* RDPS */
- tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
+ tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps));
break;
case 0x38:
/* WRUSP */
@@ -1546,7 +1546,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
case 0x3C:
/* WHAMI */
tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env,
- offsetof(CPUState, cpu_index));
+ offsetof(CPUAlphaState, cpu_index));
break;
default:
@@ -1654,7 +1654,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
case 253:
/* WAIT */
tmp = tcg_const_i64(1);
- tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted));
+ tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted));
return gen_excp(ctx, EXCP_HLT, 0);
case 252:
@@ -3107,7 +3107,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */
TCGv tmp = tcg_temp_new();
- tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, exc_addr));
+ tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
gen_helper_hw_ret(tmp);
tcg_temp_free(tmp);
} else {
@@ -3325,7 +3325,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
-static inline void gen_intermediate_code_internal(CPUState *env,
+static inline void gen_intermediate_code_internal(CPUAlphaState *env,
TranslationBlock *tb,
int search_pc)
{
@@ -3450,12 +3450,12 @@ static inline void gen_intermediate_code_internal(CPUState *env,
#endif
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUAlphaState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
@@ -3522,7 +3522,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
return env;
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 14/44] target-arm: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (12 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-14 14:39 ` Peter Maydell
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 15/44] target-cris: " Andreas Färber
` (29 subsequent siblings)
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc]
sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-arm/cpu.h | 10 ++--
target-arm/helper.c | 116 ++++++++++++++++++++++----------------------
target-arm/iwmmxt_helper.c | 66 ++++++++++++------------
target-arm/neon_helper.c | 88 +++++++++++++++++-----------------
target-arm/op_helper.c | 6 +-
target-arm/translate.c | 104 ++++++++++++++++++++--------------------
6 files changed, 195 insertions(+), 195 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 0d9b39c..2bbb5d1 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -461,13 +461,13 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUARMState *env)
{
return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
{
if (newsp)
env->regs[13] = newsp;
@@ -506,7 +506,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#define ARM_TBFLAG_CONDEXEC(F) \
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
int privmode;
@@ -529,7 +529,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
}
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUARMState *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
@@ -537,7 +537,7 @@ static inline bool cpu_has_work(CPUState *env)
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
{
env->regs[15] = tb->pc;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 13ff474..8a08db8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -339,14 +339,14 @@ void cpu_state_reset(CPUARMState *env)
set_float_detect_tininess(float_tininess_before_rounding,
&env->vfp.standard_fp_status);
tlb_flush(env, 1);
- /* Reset is a state change for some CPUState fields which we
+ /* Reset is a state change for some CPUARMState fields which we
* bake assumptions about into translated code, so we need to
* tb_flush().
*/
tb_flush(env);
}
-static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
+static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
{
int nregs;
@@ -373,7 +373,7 @@ static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
return 0;
}
-static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
+static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
{
int nregs;
@@ -498,7 +498,7 @@ void cpu_arm_close(CPUARMState *env)
g_free(env);
}
-static int bad_mode_switch(CPUState *env, int mode)
+static int bad_mode_switch(CPUARMState *env, int mode)
{
/* Return true if it is not valid for us to switch to
* this CPU mode (ie all the UNPREDICTABLE cases in
@@ -628,12 +628,12 @@ uint32_t HELPER(abs)(uint32_t x)
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUARMState *env)
{
env->exception_index = -1;
}
-int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
int mmu_idx)
{
if (rw == 2) {
@@ -647,54 +647,54 @@ int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
}
/* These should probably raise undefined insn exceptions. */
-void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
+void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val)
{
int op1 = (insn >> 8) & 0xf;
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
return;
}
-uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
+uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn)
{
int op1 = (insn >> 8) & 0xf;
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
return 0;
}
-void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
+void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
{
cpu_abort(env, "cp15 insn %08x\n", insn);
}
-uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
+uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
{
cpu_abort(env, "cp15 insn %08x\n", insn);
}
/* These should probably raise undefined insn exceptions. */
-void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
cpu_abort(env, "v7m_mrs %d\n", reg);
}
-uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
cpu_abort(env, "v7m_mrs %d\n", reg);
return 0;
}
-void switch_mode(CPUState *env, int mode)
+void switch_mode(CPUARMState *env, int mode)
{
if (mode != ARM_CPU_MODE_USR)
cpu_abort(env, "Tried to switch out of user mode\n");
}
-void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
+void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
cpu_abort(env, "banked r13 write\n");
}
-uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
+uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
{
cpu_abort(env, "banked r13 read\n");
return 0;
@@ -703,7 +703,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
#else
/* Map CPU modes onto saved register banks. */
-static inline int bank_number(CPUState *env, int mode)
+static inline int bank_number(CPUARMState *env, int mode)
{
switch (mode) {
case ARM_CPU_MODE_USR:
@@ -724,7 +724,7 @@ static inline int bank_number(CPUState *env, int mode)
return -1;
}
-void switch_mode(CPUState *env, int mode)
+void switch_mode(CPUARMState *env, int mode)
{
int old_mode;
int i;
@@ -997,7 +997,7 @@ void do_interrupt(CPUARMState *env)
/* Check section/page access permissions.
Returns the page protection flags, or zero if the access is not
permitted. */
-static inline int check_ap(CPUState *env, int ap, int domain_prot,
+static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
int access_type, int is_user)
{
int prot_ro;
@@ -1047,7 +1047,7 @@ static inline int check_ap(CPUState *env, int ap, int domain_prot,
}
}
-static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
+static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
{
uint32_t table;
@@ -1060,7 +1060,7 @@ static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
return table;
}
-static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
+static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
int is_user, uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
{
@@ -1155,7 +1155,7 @@ do_fault:
return code | (domain << 4);
}
-static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
+static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
int is_user, uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
{
@@ -1259,7 +1259,7 @@ do_fault:
return code | (domain << 4);
}
-static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
+static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
int is_user, uint32_t *phys_ptr, int *prot)
{
int n;
@@ -1319,7 +1319,7 @@ static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
return 0;
}
-static inline int get_phys_addr(CPUState *env, uint32_t address,
+static inline int get_phys_addr(CPUARMState *env, uint32_t address,
int access_type, int is_user,
uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
@@ -1347,7 +1347,7 @@ static inline int get_phys_addr(CPUState *env, uint32_t address,
}
}
-int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
+int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
int access_type, int mmu_idx)
{
uint32_t phys_addr;
@@ -1380,7 +1380,7 @@ int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
{
uint32_t phys_addr;
target_ulong page_size;
@@ -1395,7 +1395,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return phys_addr;
}
-void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
+void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val)
{
int cp_num = (insn >> 8) & 0xf;
int cp_info = (insn >> 5) & 7;
@@ -1407,7 +1407,7 @@ void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
cp_info, src, operand, val);
}
-uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
+uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn)
{
int cp_num = (insn >> 8) & 0xf;
int cp_info = (insn >> 5) & 7;
@@ -1450,7 +1450,7 @@ static uint32_t extended_mpu_ap_bits(uint32_t val)
return ret;
}
-void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
+void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
{
int op1;
int op2;
@@ -1860,7 +1860,7 @@ bad_reg:
(insn >> 16) & 0xf, crm, op1, op2);
}
-uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
+uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
{
int op1;
int op2;
@@ -2261,7 +2261,7 @@ bad_reg:
return 0;
}
-void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
+void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {
env->regs[13] = val;
@@ -2270,7 +2270,7 @@ void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
}
}
-uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
+uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {
return env->regs[13];
@@ -2279,7 +2279,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
}
}
-uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
switch (reg) {
case 0: /* APSR */
@@ -2316,7 +2316,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
}
}
-void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
switch (reg) {
case 0: /* APSR */
@@ -2672,7 +2672,7 @@ static inline int vfp_exceptbits_from_host(int host_bits)
return target_bits;
}
-uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
+uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
{
int i;
uint32_t fpscr;
@@ -2686,7 +2686,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
return fpscr;
}
-uint32_t vfp_get_fpscr(CPUState *env)
+uint32_t vfp_get_fpscr(CPUARMState *env)
{
return HELPER(vfp_get_fpscr)(env);
}
@@ -2711,7 +2711,7 @@ static inline int vfp_exceptbits_to_host(int target_bits)
return host_bits;
}
-void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
+void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
int i;
uint32_t changed;
@@ -2752,7 +2752,7 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
set_float_exception_flags(0, &env->vfp.standard_fp_status);
}
-void vfp_set_fpscr(CPUState *env, uint32_t val)
+void vfp_set_fpscr(CPUARMState *env, uint32_t val)
{
HELPER(vfp_set_fpscr)(env, val);
}
@@ -2796,19 +2796,19 @@ float64 VFP_HELPER(abs, d)(float64 a)
return float64_abs(a);
}
-float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
+float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
{
return float32_sqrt(a, &env->vfp.fp_status);
}
-float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
+float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
{
return float64_sqrt(a, &env->vfp.fp_status);
}
/* XXX: check quiet/signaling case */
#define DO_VFP_cmp(p, type) \
-void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
+void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
{ \
uint32_t flags; \
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
@@ -2820,7 +2820,7 @@ void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
} \
-void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
+void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
{ \
uint32_t flags; \
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
@@ -2871,7 +2871,7 @@ FLOAT_CONVS(ui, d, 64, u)
#undef FLOAT_CONVS
/* floating point conversion */
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
+float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
{
float64 r = float32_to_float64(x, &env->vfp.fp_status);
/* ARM requires that S<->D conversion of any kind of NaN generates
@@ -2880,7 +2880,7 @@ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
return float64_maybe_silence_nan(r);
}
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
+float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
{
float32 r = float64_to_float32(x, &env->vfp.fp_status);
/* ARM requires that S<->D conversion of any kind of NaN generates
@@ -2923,7 +2923,7 @@ VFP_CONV_FIX(ul, s, 32, uint32, u)
#undef VFP_CONV_FIX
/* Half precision conversions. */
-static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
+static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
{
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float32 r = float16_to_float32(make_float16(a), ieee, s);
@@ -2933,7 +2933,7 @@ static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
return r;
}
-static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
+static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
{
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float16 r = float32_to_float16(a, ieee, s);
@@ -2943,22 +2943,22 @@ static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
return float16_val(r);
}
-float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
+float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
{
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
}
-uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
+uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
{
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
}
-float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
{
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
}
-uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
{
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
}
@@ -2967,7 +2967,7 @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
#define float32_three make_float32(0x40400000)
#define float32_one_point_five make_float32(0x3fc00000)
-float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
+float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
{
float_status *s = &env->vfp.standard_fp_status;
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
@@ -2980,7 +2980,7 @@ float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
return float32_sub(float32_two, float32_mul(a, b, s), s);
}
-float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
+float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
{
float_status *s = &env->vfp.standard_fp_status;
float32 product;
@@ -3005,7 +3005,7 @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
/* The algorithm that must be used to calculate the estimate
* is specified by the ARM ARM.
*/
-static float64 recip_estimate(float64 a, CPUState *env)
+static float64 recip_estimate(float64 a, CPUARMState *env)
{
/* These calculations mustn't set any fp exception flags,
* so we use a local copy of the fp_status.
@@ -3031,7 +3031,7 @@ static float64 recip_estimate(float64 a, CPUState *env)
return float64_div(int64_to_float64(q_int, s), float64_256, s);
}
-float32 HELPER(recpe_f32)(float32 a, CPUState *env)
+float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
{
float_status *s = &env->vfp.standard_fp_status;
float64 f64;
@@ -3075,7 +3075,7 @@ float32 HELPER(recpe_f32)(float32 a, CPUState *env)
/* The algorithm that must be used to calculate the estimate
* is specified by the ARM ARM.
*/
-static float64 recip_sqrt_estimate(float64 a, CPUState *env)
+static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
{
/* These calculations mustn't set any fp exception flags,
* so we use a local copy of the fp_status.
@@ -3127,7 +3127,7 @@ static float64 recip_sqrt_estimate(float64 a, CPUState *env)
return float64_div(int64_to_float64(q_int, s), float64_256, s);
}
-float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
+float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
{
float_status *s = &env->vfp.standard_fp_status;
int result_exp;
@@ -3178,7 +3178,7 @@ float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
return make_float32(val);
}
-uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
+uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
{
float64 f64;
@@ -3194,7 +3194,7 @@ uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
}
-uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
+uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
{
float64 f64;
@@ -3228,7 +3228,7 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
return float64_muladd(a, b, c, 0, fpst);
}
-void HELPER(set_teecr)(CPUState *env, uint32_t val)
+void HELPER(set_teecr)(CPUARMState *env, uint32_t val)
{
val &= 1;
if (env->teecr != val) {
diff --git a/target-arm/iwmmxt_helper.c b/target-arm/iwmmxt_helper.c
index 843994d..1dd8d1a 100644
--- a/target-arm/iwmmxt_helper.c
+++ b/target-arm/iwmmxt_helper.c
@@ -162,7 +162,7 @@ uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b)
SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUARMState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
@@ -177,7 +177,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
return a; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUARMState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
@@ -190,7 +190,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
NZBIT8(a >> 32, 2) | NZBIT8(a >> 48, 3); \
return a; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUARMState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
@@ -200,7 +200,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \
return a; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUARMState *env, \
uint64_t x) \
{ \
x = \
@@ -213,7 +213,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
return x; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUARMState *env, \
uint64_t x) \
{ \
x = \
@@ -223,14 +223,14 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
return x; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUARMState *env, \
uint64_t x) \
{ \
x = (((x >> SH0) & 0xffffffff) << 0); \
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0); \
return x; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUARMState *env, \
uint64_t x) \
{ \
x = \
@@ -243,7 +243,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
return x; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUARMState *env, \
uint64_t x) \
{ \
x = \
@@ -253,7 +253,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
return x; \
} \
-uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUARMState *env, \
uint64_t x) \
{ \
x = EXTEND32((x >> SH0) & 0xffffffff); \
@@ -264,7 +264,7 @@ IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
-uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUARMState *env, \
uint64_t a, uint64_t b) \
{ \
a = \
@@ -279,7 +279,7 @@ uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env, \
NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
return a; \
} \
-uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUARMState *env, \
uint64_t a, uint64_t b) \
{ \
a = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \
@@ -289,7 +289,7 @@ uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env, \
NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); \
return a; \
} \
-uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUState *env, \
+uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUARMState *env, \
uint64_t a, uint64_t b) \
{ \
a = CMP(0, Tl, O, 0xffffffff) | \
@@ -329,7 +329,7 @@ IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
#define AVGB(SHR) ((( \
((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR)
#define IWMMXT_OP_AVGB(r) \
-uint64_t HELPER(iwmmxt_avgb##r)(CPUState *env, uint64_t a, uint64_t b) \
+uint64_t HELPER(iwmmxt_avgb##r)(CPUARMState *env, uint64_t a, uint64_t b) \
{ \
const int round = r; \
a = AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | \
@@ -353,7 +353,7 @@ IWMMXT_OP_AVGB(1)
#define AVGW(SHR) ((( \
((a >> SHR) & 0xffff) + ((b >> SHR) & 0xffff) + round) >> 1) << SHR)
#define IWMMXT_OP_AVGW(r) \
-uint64_t HELPER(iwmmxt_avgw##r)(CPUState *env, uint64_t a, uint64_t b) \
+uint64_t HELPER(iwmmxt_avgw##r)(CPUARMState *env, uint64_t a, uint64_t b) \
{ \
const int round = r; \
a = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); \
@@ -464,7 +464,7 @@ uint32_t HELPER(iwmmxt_msbl)(uint64_t x)
}
/* FIXME: Split wCASF setting into a separate op to avoid env use. */
-uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_srlw)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = (((x & (0xffffll << 0)) >> n) & (0xffffll << 0)) |
(((x & (0xffffll << 16)) >> n) & (0xffffll << 16)) |
@@ -476,7 +476,7 @@ uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_srll)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = ((x & (0xffffffffll << 0)) >> n) |
((x >> n) & (0xffffffffll << 32));
@@ -485,14 +485,14 @@ uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_srlq)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_srlq)(CPUARMState *env, uint64_t x, uint32_t n)
{
x >>= n;
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
-uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_sllw)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = (((x & (0xffffll << 0)) << n) & (0xffffll << 0)) |
(((x & (0xffffll << 16)) << n) & (0xffffll << 16)) |
@@ -504,7 +504,7 @@ uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_slll)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = ((x << n) & (0xffffffffll << 0)) |
((x & (0xffffffffll << 32)) << n);
@@ -513,14 +513,14 @@ uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_sllq)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_sllq)(CPUARMState *env, uint64_t x, uint32_t n)
{
x <<= n;
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
-uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_sraw)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = ((uint64_t) ((EXTEND16(x >> 0) >> n) & 0xffff) << 0) |
((uint64_t) ((EXTEND16(x >> 16) >> n) & 0xffff) << 16) |
@@ -532,7 +532,7 @@ uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_sral)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) |
(((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32);
@@ -541,14 +541,14 @@ uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_sraq)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_sraq)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = (int64_t) x >> n;
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
-uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_rorw)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = ((((x & (0xffffll << 0)) >> n) |
((x & (0xffffll << 0)) << (16 - n))) & (0xffffll << 0)) |
@@ -564,7 +564,7 @@ uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_rorl)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = ((x & (0xffffffffll << 0)) >> n) |
((x >> n) & (0xffffffffll << 32)) |
@@ -575,14 +575,14 @@ uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
return x;
}
-uint64_t HELPER(iwmmxt_rorq)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = (x >> n) | (x << (64 - n));
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x;
}
-uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
+uint64_t HELPER(iwmmxt_shufh)(CPUARMState *env, uint64_t x, uint32_t n)
{
x = (((x >> ((n << 4) & 0x30)) & 0xffff) << 0) |
(((x >> ((n << 2) & 0x30)) & 0xffff) << 16) |
@@ -595,7 +595,7 @@ uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
}
/* TODO: Unsigned-Saturation */
-uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(iwmmxt_packuw)(CPUARMState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
(((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
@@ -609,7 +609,7 @@ uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
return a;
}
-uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(iwmmxt_packul)(CPUARMState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
(((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
@@ -619,7 +619,7 @@ uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
return a;
}
-uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(iwmmxt_packuq)(CPUARMState *env, uint64_t a, uint64_t b)
{
a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
@@ -628,7 +628,7 @@ uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
}
/* TODO: Signed-Saturation */
-uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(iwmmxt_packsw)(CPUARMState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
(((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
@@ -642,7 +642,7 @@ uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
return a;
}
-uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(iwmmxt_packsl)(CPUARMState *env, uint64_t a, uint64_t b)
{
a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
(((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
@@ -652,7 +652,7 @@ uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
return a;
}
-uint64_t HELPER(iwmmxt_packsq)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(iwmmxt_packsq)(CPUARMState *env, uint64_t a, uint64_t b)
{
a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c
index b51e35a..1e02d61 100644
--- a/target-arm/neon_helper.c
+++ b/target-arm/neon_helper.c
@@ -114,7 +114,7 @@ uint32_t HELPER(glue(neon_,name))(uint32_t arg1, uint32_t arg2) \
NEON_VOP_BODY(vtype, n)
#define NEON_VOP_ENV(name, vtype, n) \
-uint32_t HELPER(glue(neon_,name))(CPUState *env, uint32_t arg1, uint32_t arg2) \
+uint32_t HELPER(glue(neon_,name))(CPUARMState *env, uint32_t arg1, uint32_t arg2) \
NEON_VOP_BODY(vtype, n)
/* Pairwise operations. */
@@ -172,7 +172,7 @@ NEON_VOP_ENV(qadd_u16, neon_u16, 2)
#undef NEON_FN
#undef NEON_USAT
-uint32_t HELPER(neon_qadd_u32)(CPUState *env, uint32_t a, uint32_t b)
+uint32_t HELPER(neon_qadd_u32)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
if (res < a) {
@@ -182,7 +182,7 @@ uint32_t HELPER(neon_qadd_u32)(CPUState *env, uint32_t a, uint32_t b)
return res;
}
-uint64_t HELPER(neon_qadd_u64)(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t HELPER(neon_qadd_u64)(CPUARMState *env, uint64_t src1, uint64_t src2)
{
uint64_t res;
@@ -214,7 +214,7 @@ NEON_VOP_ENV(qadd_s16, neon_s16, 2)
#undef NEON_FN
#undef NEON_SSAT
-uint32_t HELPER(neon_qadd_s32)(CPUState *env, uint32_t a, uint32_t b)
+uint32_t HELPER(neon_qadd_s32)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a + b;
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
@@ -224,7 +224,7 @@ uint32_t HELPER(neon_qadd_s32)(CPUState *env, uint32_t a, uint32_t b)
return res;
}
-uint64_t HELPER(neon_qadd_s64)(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t HELPER(neon_qadd_s64)(CPUARMState *env, uint64_t src1, uint64_t src2)
{
uint64_t res;
@@ -252,7 +252,7 @@ NEON_VOP_ENV(qsub_u16, neon_u16, 2)
#undef NEON_FN
#undef NEON_USAT
-uint32_t HELPER(neon_qsub_u32)(CPUState *env, uint32_t a, uint32_t b)
+uint32_t HELPER(neon_qsub_u32)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a - b;
if (res > a) {
@@ -262,7 +262,7 @@ uint32_t HELPER(neon_qsub_u32)(CPUState *env, uint32_t a, uint32_t b)
return res;
}
-uint64_t HELPER(neon_qsub_u64)(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t HELPER(neon_qsub_u64)(CPUARMState *env, uint64_t src1, uint64_t src2)
{
uint64_t res;
@@ -295,7 +295,7 @@ NEON_VOP_ENV(qsub_s16, neon_s16, 2)
#undef NEON_FN
#undef NEON_SSAT
-uint32_t HELPER(neon_qsub_s32)(CPUState *env, uint32_t a, uint32_t b)
+uint32_t HELPER(neon_qsub_s32)(CPUARMState *env, uint32_t a, uint32_t b)
{
uint32_t res = a - b;
if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
@@ -305,7 +305,7 @@ uint32_t HELPER(neon_qsub_s32)(CPUState *env, uint32_t a, uint32_t b)
return res;
}
-uint64_t HELPER(neon_qsub_s64)(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t HELPER(neon_qsub_s64)(CPUARMState *env, uint64_t src1, uint64_t src2)
{
uint64_t res;
@@ -661,7 +661,7 @@ NEON_VOP_ENV(qshl_u16, neon_u16, 2)
NEON_VOP_ENV(qshl_u32, neon_u32, 1)
#undef NEON_FN
-uint64_t HELPER(neon_qshl_u64)(CPUState *env, uint64_t val, uint64_t shiftop)
+uint64_t HELPER(neon_qshl_u64)(CPUARMState *env, uint64_t val, uint64_t shiftop)
{
int8_t shift = (int8_t)shiftop;
if (shift >= 64) {
@@ -716,7 +716,7 @@ NEON_VOP_ENV(qshl_s16, neon_s16, 2)
NEON_VOP_ENV(qshl_s32, neon_s32, 1)
#undef NEON_FN
-uint64_t HELPER(neon_qshl_s64)(CPUState *env, uint64_t valop, uint64_t shiftop)
+uint64_t HELPER(neon_qshl_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)
{
int8_t shift = (uint8_t)shiftop;
int64_t val = valop;
@@ -770,7 +770,7 @@ NEON_VOP_ENV(qshlu_s8, neon_u8, 4)
NEON_VOP_ENV(qshlu_s16, neon_u16, 2)
#undef NEON_FN
-uint32_t HELPER(neon_qshlu_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
+uint32_t HELPER(neon_qshlu_s32)(CPUARMState *env, uint32_t valop, uint32_t shiftop)
{
if ((int32_t)valop < 0) {
SET_QC();
@@ -779,7 +779,7 @@ uint32_t HELPER(neon_qshlu_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
return helper_neon_qshl_u32(env, valop, shiftop);
}
-uint64_t HELPER(neon_qshlu_s64)(CPUState *env, uint64_t valop, uint64_t shiftop)
+uint64_t HELPER(neon_qshlu_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)
{
if ((int64_t)valop < 0) {
SET_QC();
@@ -818,7 +818,7 @@ NEON_VOP_ENV(qrshl_u16, neon_u16, 2)
/* The addition of the rounding constant may overflow, so we use an
* intermediate 64 bits accumulator. */
-uint32_t HELPER(neon_qrshl_u32)(CPUState *env, uint32_t val, uint32_t shiftop)
+uint32_t HELPER(neon_qrshl_u32)(CPUARMState *env, uint32_t val, uint32_t shiftop)
{
uint32_t dest;
int8_t shift = (int8_t)shiftop;
@@ -848,7 +848,7 @@ uint32_t HELPER(neon_qrshl_u32)(CPUState *env, uint32_t val, uint32_t shiftop)
/* Handling addition overflow with 64 bits inputs values is more
* tricky than with 32 bits values. */
-uint64_t HELPER(neon_qrshl_u64)(CPUState *env, uint64_t val, uint64_t shiftop)
+uint64_t HELPER(neon_qrshl_u64)(CPUARMState *env, uint64_t val, uint64_t shiftop)
{
int8_t shift = (int8_t)shiftop;
if (shift >= 64) {
@@ -915,7 +915,7 @@ NEON_VOP_ENV(qrshl_s16, neon_s16, 2)
/* The addition of the rounding constant may overflow, so we use an
* intermediate 64 bits accumulator. */
-uint32_t HELPER(neon_qrshl_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
+uint32_t HELPER(neon_qrshl_s32)(CPUARMState *env, uint32_t valop, uint32_t shiftop)
{
int32_t dest;
int32_t val = (int32_t)valop;
@@ -944,7 +944,7 @@ uint32_t HELPER(neon_qrshl_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
/* Handling addition overflow with 64 bits inputs values is more
* tricky than with 32 bits values. */
-uint64_t HELPER(neon_qrshl_s64)(CPUState *env, uint64_t valop, uint64_t shiftop)
+uint64_t HELPER(neon_qrshl_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)
{
int8_t shift = (uint8_t)shiftop;
int64_t val = valop;
@@ -1223,7 +1223,7 @@ uint32_t HELPER(neon_narrow_round_high_u16)(uint64_t x)
return ((x >> 16) & 0xffff) | ((x >> 32) & 0xffff0000);
}
-uint32_t HELPER(neon_unarrow_sat8)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_unarrow_sat8)(CPUARMState *env, uint64_t x)
{
uint16_t s;
uint8_t d;
@@ -1250,7 +1250,7 @@ uint32_t HELPER(neon_unarrow_sat8)(CPUState *env, uint64_t x)
return res;
}
-uint32_t HELPER(neon_narrow_sat_u8)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_narrow_sat_u8)(CPUARMState *env, uint64_t x)
{
uint16_t s;
uint8_t d;
@@ -1273,7 +1273,7 @@ uint32_t HELPER(neon_narrow_sat_u8)(CPUState *env, uint64_t x)
return res;
}
-uint32_t HELPER(neon_narrow_sat_s8)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_narrow_sat_s8)(CPUARMState *env, uint64_t x)
{
int16_t s;
uint8_t d;
@@ -1296,7 +1296,7 @@ uint32_t HELPER(neon_narrow_sat_s8)(CPUState *env, uint64_t x)
return res;
}
-uint32_t HELPER(neon_unarrow_sat16)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_unarrow_sat16)(CPUARMState *env, uint64_t x)
{
uint32_t high;
uint32_t low;
@@ -1319,7 +1319,7 @@ uint32_t HELPER(neon_unarrow_sat16)(CPUState *env, uint64_t x)
return low | (high << 16);
}
-uint32_t HELPER(neon_narrow_sat_u16)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_narrow_sat_u16)(CPUARMState *env, uint64_t x)
{
uint32_t high;
uint32_t low;
@@ -1336,7 +1336,7 @@ uint32_t HELPER(neon_narrow_sat_u16)(CPUState *env, uint64_t x)
return low | (high << 16);
}
-uint32_t HELPER(neon_narrow_sat_s16)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_narrow_sat_s16)(CPUARMState *env, uint64_t x)
{
int32_t low;
int32_t high;
@@ -1353,7 +1353,7 @@ uint32_t HELPER(neon_narrow_sat_s16)(CPUState *env, uint64_t x)
return (uint16_t)low | (high << 16);
}
-uint32_t HELPER(neon_unarrow_sat32)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_unarrow_sat32)(CPUARMState *env, uint64_t x)
{
if (x & 0x8000000000000000ull) {
SET_QC();
@@ -1366,7 +1366,7 @@ uint32_t HELPER(neon_unarrow_sat32)(CPUState *env, uint64_t x)
return x;
}
-uint32_t HELPER(neon_narrow_sat_u32)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_narrow_sat_u32)(CPUARMState *env, uint64_t x)
{
if (x > 0xffffffffu) {
SET_QC();
@@ -1375,7 +1375,7 @@ uint32_t HELPER(neon_narrow_sat_u32)(CPUState *env, uint64_t x)
return x;
}
-uint32_t HELPER(neon_narrow_sat_s32)(CPUState *env, uint64_t x)
+uint32_t HELPER(neon_narrow_sat_s32)(CPUARMState *env, uint64_t x)
{
if ((int64_t)x != (int32_t)x) {
SET_QC();
@@ -1482,7 +1482,7 @@ uint64_t HELPER(neon_subl_u32)(uint64_t a, uint64_t b)
return (a - b) ^ mask;
}
-uint64_t HELPER(neon_addl_saturate_s32)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(neon_addl_saturate_s32)(CPUARMState *env, uint64_t a, uint64_t b)
{
uint32_t x, y;
uint32_t low, high;
@@ -1504,7 +1504,7 @@ uint64_t HELPER(neon_addl_saturate_s32)(CPUState *env, uint64_t a, uint64_t b)
return low | ((uint64_t)high << 32);
}
-uint64_t HELPER(neon_addl_saturate_s64)(CPUState *env, uint64_t a, uint64_t b)
+uint64_t HELPER(neon_addl_saturate_s64)(CPUARMState *env, uint64_t a, uint64_t b)
{
uint64_t result;
@@ -1680,7 +1680,7 @@ uint64_t HELPER(neon_negl_u64)(uint64_t x)
} else if (x < 0) { \
x = -x; \
}} while (0)
-uint32_t HELPER(neon_qabs_s8)(CPUState *env, uint32_t x)
+uint32_t HELPER(neon_qabs_s8)(CPUARMState *env, uint32_t x)
{
neon_s8 vec;
NEON_UNPACK(neon_s8, vec, x);
@@ -1700,7 +1700,7 @@ uint32_t HELPER(neon_qabs_s8)(CPUState *env, uint32_t x)
} else { \
x = -x; \
}} while (0)
-uint32_t HELPER(neon_qneg_s8)(CPUState *env, uint32_t x)
+uint32_t HELPER(neon_qneg_s8)(CPUARMState *env, uint32_t x)
{
neon_s8 vec;
NEON_UNPACK(neon_s8, vec, x);
@@ -1720,7 +1720,7 @@ uint32_t HELPER(neon_qneg_s8)(CPUState *env, uint32_t x)
} else if (x < 0) { \
x = -x; \
}} while (0)
-uint32_t HELPER(neon_qabs_s16)(CPUState *env, uint32_t x)
+uint32_t HELPER(neon_qabs_s16)(CPUARMState *env, uint32_t x)
{
neon_s16 vec;
NEON_UNPACK(neon_s16, vec, x);
@@ -1738,7 +1738,7 @@ uint32_t HELPER(neon_qabs_s16)(CPUState *env, uint32_t x)
} else { \
x = -x; \
}} while (0)
-uint32_t HELPER(neon_qneg_s16)(CPUState *env, uint32_t x)
+uint32_t HELPER(neon_qneg_s16)(CPUARMState *env, uint32_t x)
{
neon_s16 vec;
NEON_UNPACK(neon_s16, vec, x);
@@ -1749,7 +1749,7 @@ uint32_t HELPER(neon_qneg_s16)(CPUState *env, uint32_t x)
}
#undef DO_QNEG16
-uint32_t HELPER(neon_qabs_s32)(CPUState *env, uint32_t x)
+uint32_t HELPER(neon_qabs_s32)(CPUARMState *env, uint32_t x)
{
if (x == SIGNBIT) {
SET_QC();
@@ -1760,7 +1760,7 @@ uint32_t HELPER(neon_qabs_s32)(CPUState *env, uint32_t x)
return x;
}
-uint32_t HELPER(neon_qneg_s32)(CPUState *env, uint32_t x)
+uint32_t HELPER(neon_qneg_s32)(CPUARMState *env, uint32_t x)
{
if (x == SIGNBIT) {
SET_QC();
@@ -1832,7 +1832,7 @@ uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, void *fpstp)
#define ELEM(V, N, SIZE) (((V) >> ((N) * (SIZE))) & ((1ull << (SIZE)) - 1))
-void HELPER(neon_qunzip8)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
@@ -1860,7 +1860,7 @@ void HELPER(neon_qunzip8)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd + 1] = make_float64(d1);
}
-void HELPER(neon_qunzip16)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_qunzip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
@@ -1880,7 +1880,7 @@ void HELPER(neon_qunzip16)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd + 1] = make_float64(d1);
}
-void HELPER(neon_qunzip32)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_qunzip32)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
@@ -1896,7 +1896,7 @@ void HELPER(neon_qunzip32)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd + 1] = make_float64(d1);
}
-void HELPER(neon_unzip8)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_unzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm = float64_val(env->vfp.regs[rm]);
uint64_t zd = float64_val(env->vfp.regs[rd]);
@@ -1912,7 +1912,7 @@ void HELPER(neon_unzip8)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd] = make_float64(d0);
}
-void HELPER(neon_unzip16)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_unzip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm = float64_val(env->vfp.regs[rm]);
uint64_t zd = float64_val(env->vfp.regs[rd]);
@@ -1924,7 +1924,7 @@ void HELPER(neon_unzip16)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd] = make_float64(d0);
}
-void HELPER(neon_qzip8)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_qzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
@@ -1952,7 +1952,7 @@ void HELPER(neon_qzip8)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd + 1] = make_float64(d1);
}
-void HELPER(neon_qzip16)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_qzip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
@@ -1972,7 +1972,7 @@ void HELPER(neon_qzip16)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd + 1] = make_float64(d1);
}
-void HELPER(neon_qzip32)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_qzip32)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
@@ -1988,7 +1988,7 @@ void HELPER(neon_qzip32)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd + 1] = make_float64(d1);
}
-void HELPER(neon_zip8)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_zip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm = float64_val(env->vfp.regs[rm]);
uint64_t zd = float64_val(env->vfp.regs[rd]);
@@ -2004,7 +2004,7 @@ void HELPER(neon_zip8)(CPUState *env, uint32_t rd, uint32_t rm)
env->vfp.regs[rd] = make_float64(d0);
}
-void HELPER(neon_zip16)(CPUState *env, uint32_t rd, uint32_t rm)
+void HELPER(neon_zip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
uint64_t zm = float64_val(env->vfp.regs[rm]);
uint64_t zd = float64_val(env->vfp.regs[rd]);
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 1892b35..c728432 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -75,11 +75,11 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUARMState *saved_env;
unsigned long pc;
int ret;
@@ -103,7 +103,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
}
#endif
-/* FIXME: Pass an axplicit pointer to QF to CPUState, and move saturating
+/* FIXME: Pass an axplicit pointer to QF to CPUARMState, and move saturating
instructions into helper.c */
uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
{
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 280bfca..2709010 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -111,20 +111,20 @@ void arm_translate_init(void)
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPUARMState, regs[i]),
regnames[i]);
}
cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, exclusive_addr), "exclusive_addr");
+ offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, exclusive_val), "exclusive_val");
+ offsetof(CPUARMState, exclusive_val), "exclusive_val");
cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, exclusive_high), "exclusive_high");
+ offsetof(CPUARMState, exclusive_high), "exclusive_high");
#ifdef CONFIG_USER_ONLY
cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, exclusive_test), "exclusive_test");
+ offsetof(CPUARMState, exclusive_test), "exclusive_test");
cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, exclusive_info), "exclusive_info");
+ offsetof(CPUARMState, exclusive_info), "exclusive_info");
#endif
#define GEN_HELPER 2
@@ -138,7 +138,7 @@ static inline TCGv load_cpu_offset(int offset)
return tmp;
}
-#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
+#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
static inline void store_cpu_offset(TCGv var, int offset)
{
@@ -147,7 +147,7 @@ static inline void store_cpu_offset(TCGv var, int offset)
}
#define store_cpu_field(var, name) \
- store_cpu_offset(var, offsetof(CPUState, name))
+ store_cpu_offset(var, offsetof(CPUARMState, name))
/* Set a variable to the value of a CPU register. */
static void load_reg_var(DisasContext *s, TCGv var, int reg)
@@ -368,7 +368,7 @@ static void gen_add16(TCGv t0, TCGv t1)
tcg_temp_free_i32(t1);
}
-#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
+#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, CF))
/* Set CF to the top bit of var. */
static void gen_set_CF_bit31(TCGv var)
@@ -382,8 +382,8 @@ static void gen_set_CF_bit31(TCGv var)
/* Set N and Z flags from var. */
static inline void gen_logic_CC(TCGv var)
{
- tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
- tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
+ tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, NF));
+ tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, ZF));
}
/* T0 += T1 + CF. */
@@ -523,13 +523,13 @@ static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
case 1:
tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
+ tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
PAS_OP(s)
tcg_temp_free_ptr(tmp);
break;
case 5:
tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
+ tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
PAS_OP(u)
tcg_temp_free_ptr(tmp);
break;
@@ -570,13 +570,13 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
case 0:
tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
+ tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
PAS_OP(s)
tcg_temp_free_ptr(tmp);
break;
case 4:
tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
+ tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
PAS_OP(u)
tcg_temp_free_ptr(tmp);
break;
@@ -725,7 +725,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr)
if (s->thumb != (addr & 1)) {
tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, addr & 1);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
tcg_temp_free_i32(tmp);
}
tcg_gen_movi_i32(cpu_R[15], addr & ~1);
@@ -743,7 +743,7 @@ static inline void gen_bx(DisasContext *s, TCGv var)
/* Variant of store_reg which uses branch&exchange logic when storing
to r15 in ARM architecture v7 and above. The source must be a temporary
and will be marked as dead. */
-static inline void store_reg_bx(CPUState *env, DisasContext *s,
+static inline void store_reg_bx(CPUARMState *env, DisasContext *s,
int reg, TCGv var)
{
if (reg == 15 && ENABLE_ARCH_7) {
@@ -757,7 +757,7 @@ static inline void store_reg_bx(CPUState *env, DisasContext *s,
* to r15 in ARM architecture v5T and above. This is used for storing
* the results of a LDR/LDM/POP into r15, and corresponds to the cases
* in the ARM ARM which use the LoadWritePC() pseudocode function. */
-static inline void store_reg_from_load(CPUState *env, DisasContext *s,
+static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
int reg, TCGv var)
{
if (reg == 15 && ENABLE_ARCH_5) {
@@ -897,9 +897,9 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
TCGv_ptr statusptr = tcg_temp_new_ptr();
int offset;
if (neon) {
- offset = offsetof(CPUState, vfp.standard_fp_status);
+ offset = offsetof(CPUARMState, vfp.standard_fp_status);
} else {
- offset = offsetof(CPUState, vfp.fp_status);
+ offset = offsetof(CPUARMState, vfp.fp_status);
}
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
return statusptr;
@@ -1147,24 +1147,24 @@ static inline void gen_mov_vreg_F0(int dp, int reg)
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{
- tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
+ tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
}
static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
{
- tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
+ tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
}
static inline TCGv iwmmxt_load_creg(int reg)
{
TCGv var = tcg_temp_new_i32();
- tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
+ tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
return var;
}
static inline void iwmmxt_store_creg(int reg, TCGv var)
{
- tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
+ tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
tcg_temp_free_i32(var);
}
@@ -1366,7 +1366,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
-static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
+static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
{
int rd, wrd;
int rdhi, rdlo, rd0, rd1, i;
@@ -2370,7 +2370,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
-static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
+static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
{
int acc, rd0, rd1, rdhi, rdlo;
TCGv tmp, tmp2;
@@ -2440,7 +2440,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
/* Disassemble system coprocessor instruction. Return nonzero if
instruction is not defined. */
-static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
+static int disas_cp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
{
TCGv tmp, tmp2;
uint32_t rd = (insn >> 12) & 0xf;
@@ -2471,7 +2471,7 @@ static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
return 0;
}
-static int cp15_user_ok(CPUState *env, uint32_t insn)
+static int cp15_user_ok(CPUARMState *env, uint32_t insn)
{
int cpn = (insn >> 16) & 0xf;
int cpm = insn & 0xf;
@@ -2501,7 +2501,7 @@ static int cp15_user_ok(CPUState *env, uint32_t insn)
return 0;
}
-static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
+static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd)
{
TCGv tmp;
int cpn = (insn >> 16) & 0xf;
@@ -2552,7 +2552,7 @@ static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, ui
/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
instruction is not defined. */
-static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
+static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
{
uint32_t rd;
TCGv tmp, tmp2;
@@ -2747,7 +2747,7 @@ static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
/* Disassemble a VFP instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
-static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
+static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
{
uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
int dp, veclen;
@@ -3586,7 +3586,7 @@ static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
}
/* Return the mask of PSR bits set by a MSR instruction. */
-static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
+static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr) {
uint32_t mask;
mask = 0;
@@ -3946,7 +3946,7 @@ static struct {
/* Translate a NEON load/store element instruction. Return nonzero if the
instruction is invalid. */
-static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
+static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
{
int rd, rn, rm;
int op;
@@ -4622,7 +4622,7 @@ static const uint8_t neon_2rm_sizes[] = {
We process data in a mixture of 32-bit and 64-bit chunks.
Mostly we use 32-bit chunks so we can use normal scalar instructions. */
-static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
+static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
{
int op;
int q;
@@ -6387,7 +6387,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
return 0;
}
-static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
+static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn)
{
int crn = (insn >> 16) & 0xf;
int crm = insn & 0xf;
@@ -6445,7 +6445,7 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
return 1;
}
-static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
+static int disas_cp14_write(CPUARMState * env, DisasContext *s, uint32_t insn)
{
int crn = (insn >> 16) & 0xf;
int crm = insn & 0xf;
@@ -6476,7 +6476,7 @@ static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
return 1;
}
-static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
+static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
{
int cpnum;
@@ -6696,7 +6696,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
}
#endif
-static void disas_arm_insn(CPUState * env, DisasContext *s)
+static void disas_arm_insn(CPUARMState * env, DisasContext *s)
{
unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
TCGv tmp;
@@ -7587,7 +7587,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
tmp3 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
+ tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
tcg_temp_free_i32(tmp3);
tcg_temp_free_i32(tmp2);
@@ -8077,7 +8077,7 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG
/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
is not legal. */
-static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
+static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
{
uint32_t insn, imm, shift, offset;
uint32_t rd, rn, rm, rs;
@@ -8488,7 +8488,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
case 0x10: /* sel */
tmp2 = load_reg(s, rm);
tmp3 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
+ tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
tcg_temp_free_i32(tmp3);
tcg_temp_free_i32(tmp2);
@@ -9145,7 +9145,7 @@ illegal_op:
return 1;
}
-static void disas_thumb_insn(CPUState *env, DisasContext *s)
+static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
{
uint32_t val, insn, op, rm, rn, rd, shift, cond;
int32_t offset;
@@ -9830,7 +9830,7 @@ undef:
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline void gen_intermediate_code_internal(CPUState *env,
+static inline void gen_intermediate_code_internal(CPUARMState *env,
TranslationBlock *tb,
int search_pc)
{
@@ -9885,22 +9885,22 @@ static inline void gen_intermediate_code_internal(CPUState *env,
/* A note on handling of the condexec (IT) bits:
*
* We want to avoid the overhead of having to write the updated condexec
- * bits back to the CPUState for every instruction in an IT block. So:
+ * bits back to the CPUARMState for every instruction in an IT block. So:
* (1) if the condexec bits are not already zero then we write
- * zero back into the CPUState now. This avoids complications trying
+ * zero back into the CPUARMState now. This avoids complications trying
* to do it at the end of the block. (For example if we don't do this
* it's hard to identify whether we can safely skip writing condexec
* at the end of the TB, which we definitely want to do for the case
* where a TB doesn't do anything with the IT state at all.)
* (2) if we are going to leave the TB then we call gen_set_condexec()
- * which will write the correct value into CPUState if zero is wrong.
+ * which will write the correct value into CPUARMState if zero is wrong.
* This is done both for leaving the TB at the end, and for leaving
* it because of an exception we know will happen, which is done in
* gen_exception_insn(). The latter is necessary because we need to
* leave the TB with the PC/IT state just prior to execution of the
* instruction which caused the exception.
* (3) if we leave the TB unexpectedly (eg a data abort on a load)
- * then the CPUState will be wrong and we need to reset it.
+ * then the CPUARMState will be wrong and we need to reset it.
* This is handled in the same way as restoration of the
* PC in these situations: we will be called again with search_pc=1
* and generate a mapping of the condexec bits for each PC in
@@ -9909,7 +9909,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
*
* Note that there are no instructions which can read the condexec
* bits, and none which can write non-static values to them, so
- * we don't need to care about whether CPUState is correct in the
+ * we don't need to care about whether CPUARMState is correct in the
* middle of a TB.
*/
@@ -10103,12 +10103,12 @@ done_generating:
}
}
-void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
@@ -10118,7 +10118,7 @@ static const char *cpu_mode_names[16] = {
"???", "???", "???", "und", "???", "???", "???", "sys"
};
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -10170,7 +10170,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
#endif
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)
{
env->regs[15] = gen_opc_pc[pc_pos];
env->condexec_bits = gen_opc_condexec_bits[pc_pos];
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 15/44] target-cris: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (13 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 16/44] target-i386: " Andreas Färber
` (28 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc]
sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-cris/cpu.h | 12 +++++-----
target-cris/helper.c | 14 ++++++------
target-cris/mmu.c | 14 ++++++------
target-cris/mmu.h | 6 ++--
target-cris/op_helper.c | 6 ++--
target-cris/translate.c | 46 +++++++++++++++++++++---------------------
target-cris/translate_v10.c | 26 ++++++++++++------------
7 files changed, 62 insertions(+), 62 deletions(-)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 222a062..f38393a 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -225,17 +225,17 @@ enum {
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUCRISState *env)
{
return !!(env->pregs[PR_CCS] & U_FLAG);
}
-int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
{
if (newsp)
env->regs[14] = newsp;
@@ -260,7 +260,7 @@ static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
#include "cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -273,14 +273,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
#define cpu_list cris_cpu_list
void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUCRISState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index dd7f18e..8680f43 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -36,13 +36,13 @@
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUCRISState *env)
{
env->exception_index = -1;
env->pregs[PR_ERP] = env->pc;
}
-int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
+int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
int mmu_idx)
{
env->exception_index = 0xaa;
@@ -54,7 +54,7 @@ int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
#else /* !CONFIG_USER_ONLY */
-static void cris_shift_ccs(CPUState *env)
+static void cris_shift_ccs(CPUCRISState *env)
{
uint32_t ccs;
/* Apply the ccs shift. */
@@ -63,7 +63,7 @@ static void cris_shift_ccs(CPUState *env)
env->pregs[PR_CCS] = ccs;
}
-int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw,
int mmu_idx)
{
struct cris_mmu_result res;
@@ -106,7 +106,7 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
return r;
}
-static void do_interruptv10(CPUState *env)
+static void do_interruptv10(CPUCRISState *env)
{
int ex_vec = -1;
@@ -162,7 +162,7 @@ static void do_interruptv10(CPUState *env)
env->pregs[PR_ERP]);
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUCRISState *env)
{
int ex_vec = -1;
@@ -246,7 +246,7 @@ void do_interrupt(CPUState *env)
env->pregs[PR_ERP]);
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
{
uint32_t phy = addr;
struct cris_mmu_result res;
diff --git a/target-cris/mmu.c b/target-cris/mmu.c
index 5cd8f27..512e28b 100644
--- a/target-cris/mmu.c
+++ b/target-cris/mmu.c
@@ -31,7 +31,7 @@
#define D_LOG(...) do { } while (0)
#endif
-void cris_mmu_init(CPUState *env)
+void cris_mmu_init(CPUCRISState *env)
{
env->mmu_rand_lfsr = 0xcccc;
}
@@ -49,7 +49,7 @@ static inline unsigned int compute_polynom(unsigned int sr)
return f;
}
-static void cris_mmu_update_rand_lfsr(CPUState *env)
+static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
{
unsigned int f;
@@ -70,7 +70,7 @@ static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
return (1 << seg) & rw_mm_cfg;
}
-static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
+static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
{
uint32_t base;
int i;
@@ -106,7 +106,7 @@ static inline void set_field(uint32_t *dst, unsigned int val,
}
#ifdef DEBUG
-static void dump_tlb(CPUState *env, int mmu)
+static void dump_tlb(CPUCRISState *env, int mmu)
{
int set;
int idx;
@@ -128,7 +128,7 @@ static void dump_tlb(CPUState *env, int mmu)
/* rw 0 = read, 1 = write, 2 = exec. */
static int cris_mmu_translate_page(struct cris_mmu_result *res,
- CPUState *env, uint32_t vaddr,
+ CPUCRISState *env, uint32_t vaddr,
int rw, int usermode, int debug)
{
unsigned int vpage;
@@ -288,7 +288,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
return !match;
}
-void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
+void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
target_ulong vaddr;
unsigned int idx;
@@ -323,7 +323,7 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
}
int cris_mmu_translate(struct cris_mmu_result *res,
- CPUState *env, uint32_t vaddr,
+ CPUCRISState *env, uint32_t vaddr,
int rw, int mmu_idx, int debug)
{
int seg;
diff --git a/target-cris/mmu.h b/target-cris/mmu.h
index 459d809..8e249e8 100644
--- a/target-cris/mmu.h
+++ b/target-cris/mmu.h
@@ -10,8 +10,8 @@ struct cris_mmu_result
int bf_vec;
};
-void cris_mmu_init(CPUState *env);
-void cris_mmu_flush_pid(CPUState *env, uint32_t pid);
+void cris_mmu_init(CPUCRISState *env);
+void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid);
int cris_mmu_translate(struct cris_mmu_result *res,
- CPUState *env, uint32_t vaddr,
+ CPUCRISState *env, uint32_t vaddr,
int rw, int mmu_idx, int debug);
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 1eacc5f..c568e2b 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -56,11 +56,11 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUCRISState *saved_env;
unsigned long pc;
int ret;
@@ -201,7 +201,7 @@ void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
env->regs[reg] = env->sregs[srs][sreg];
}
-static void cris_ccs_rshift(CPUState *env)
+static void cris_ccs_rshift(CPUCRISState *env)
{
uint32_t ccs;
diff --git a/target-cris/translate.c b/target-cris/translate.c
index f360c31..7224f46 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -74,7 +74,7 @@ static TCGv env_pc;
/* This is the state at translation time. */
typedef struct DisasContext {
- CPUState *env;
+ CPUCRISState *env;
target_ulong pc, ppc;
/* Decoder. */
@@ -160,9 +160,9 @@ static int preg_sizes[] = {
};
#define t_gen_mov_TN_env(tn, member) \
- _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
+ _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member))
#define t_gen_mov_env_TN(member, tn) \
- _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
+ _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))
static inline void t_gen_mov_TN_reg(TCGv tn, int r)
{
@@ -179,13 +179,13 @@ static inline void t_gen_mov_reg_TN(int r, TCGv tn)
static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
{
- if (offset > sizeof (CPUState))
+ if (offset > sizeof (CPUCRISState))
fprintf(stderr, "wrong load from env from off=%d\n", offset);
tcg_gen_ld_tl(tn, cpu_env, offset);
}
static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
{
- if (offset > sizeof (CPUState))
+ if (offset > sizeof (CPUCRISState))
fprintf(stderr, "wrong store to env at off=%d\n", offset);
tcg_gen_st_tl(tn, cpu_env, offset);
}
@@ -3114,7 +3114,7 @@ static unsigned int crisv32_decoder(DisasContext *dc)
return insn_len;
}
-static void check_breakpoint(CPUState *env, DisasContext *dc)
+static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
{
CPUBreakpoint *bp;
@@ -3168,7 +3168,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
/* generate intermediate code for basic block 'tb'. */
static void
-gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
+gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb,
int search_pc)
{
uint16_t *gen_opc_end;
@@ -3419,17 +3419,17 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
#endif
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state (CPUCRISState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -3532,41 +3532,41 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cc_x = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_x), "cc_x");
+ offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_src), "cc_src");
+ offsetof(CPUCRISState, cc_src), "cc_src");
cc_dest = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_dest),
+ offsetof(CPUCRISState, cc_dest),
"cc_dest");
cc_result = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_result),
+ offsetof(CPUCRISState, cc_result),
"cc_result");
cc_op = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_op), "cc_op");
+ offsetof(CPUCRISState, cc_op), "cc_op");
cc_size = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_size),
+ offsetof(CPUCRISState, cc_size),
"cc_size");
cc_mask = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_mask),
+ offsetof(CPUCRISState, cc_mask),
"cc_mask");
env_pc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, pc),
+ offsetof(CPUCRISState, pc),
"pc");
env_btarget = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btarget),
+ offsetof(CPUCRISState, btarget),
"btarget");
env_btaken = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btaken),
+ offsetof(CPUCRISState, btaken),
"btaken");
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPUCRISState, regs[i]),
regnames[i]);
}
for (i = 0; i < 16; i++) {
cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, pregs[i]),
+ offsetof(CPUCRISState, pregs[i]),
pregnames[i]);
}
@@ -3596,7 +3596,7 @@ void cpu_state_reset(CPUCRISState *env)
#endif
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 95053b6..4ada3ed 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1253,47 +1253,47 @@ static unsigned int crisv10_decoder(DisasContext *dc)
return insn_len;
}
-static CPUCRISState *cpu_crisv10_init (CPUState *env)
+static CPUCRISState *cpu_crisv10_init (CPUCRISState *env)
{
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cc_x = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_x), "cc_x");
+ offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_src), "cc_src");
+ offsetof(CPUCRISState, cc_src), "cc_src");
cc_dest = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_dest),
+ offsetof(CPUCRISState, cc_dest),
"cc_dest");
cc_result = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_result),
+ offsetof(CPUCRISState, cc_result),
"cc_result");
cc_op = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_op), "cc_op");
+ offsetof(CPUCRISState, cc_op), "cc_op");
cc_size = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_size),
+ offsetof(CPUCRISState, cc_size),
"cc_size");
cc_mask = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_mask),
+ offsetof(CPUCRISState, cc_mask),
"cc_mask");
env_pc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, pc),
+ offsetof(CPUCRISState, pc),
"pc");
env_btarget = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btarget),
+ offsetof(CPUCRISState, btarget),
"btarget");
env_btaken = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btaken),
+ offsetof(CPUCRISState, btaken),
"btaken");
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPUCRISState, regs[i]),
regnames_v10[i]);
}
for (i = 0; i < 16; i++) {
cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, pregs[i]),
+ offsetof(CPUCRISState, pregs[i]),
pregnames_v10[i]);
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 16/44] target-i386: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (14 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 15/44] target-cris: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: " Andreas Färber
` (27 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc]
sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-i386/cpu.h | 34 +++++-----
target-i386/helper.c | 38 +++++-----
target-i386/kvm.c | 76 ++++++++++----------
target-i386/machine.c | 172 +++++++++++++++++++++++-----------------------
target-i386/op_helper.c | 34 +++++-----
target-i386/translate.c | 82 +++++++++++-----------
6 files changed, 218 insertions(+), 218 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 196b0c5..f337dd0 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -787,7 +787,7 @@ int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg);
void x86_cpudef_setup(void);
-int cpu_x86_support_mca_broadcast(CPUState *env);
+int cpu_x86_support_mca_broadcast(CPUX86State *env);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
@@ -969,7 +969,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUX86State *env)
{
return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
}
@@ -1008,7 +1008,7 @@ static inline int cpu_mmu_index (CPUState *env)
void optimize_flags_init(void);
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp)
{
if (newsp)
env->regs[R_ESP] = newsp;
@@ -1023,7 +1023,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#include "hw/apic.h"
#endif
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUX86State *env)
{
return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
@@ -1035,12 +1035,12 @@ static inline bool cpu_has_work(CPUState *env)
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb)
{
env->eip = tb->pc - tb->cs_base;
}
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*cs_base = env->segs[R_CS].base;
@@ -1049,29 +1049,29 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
(env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
}
-void do_cpu_init(CPUState *env);
-void do_cpu_sipi(CPUState *env);
+void do_cpu_init(CPUX86State *env);
+void do_cpu_sipi(CPUX86State *env);
#define MCE_INJECT_BROADCAST 1
#define MCE_INJECT_UNCOND_AO 2
-void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
+void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank,
uint64_t status, uint64_t mcg_status, uint64_t addr,
uint64_t misc, int flags);
/* op_helper.c */
-void do_interrupt(CPUState *env);
-void do_interrupt_x86_hardirq(CPUState *env, int intno, int is_hw);
-void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv);
-void QEMU_NORETURN raise_exception_err_env(CPUState *nenv, int exception_index,
+void do_interrupt(CPUX86State *env);
+void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
+void QEMU_NORETURN raise_exception_env(int exception_index, CPUX86State *nenv);
+void QEMU_NORETURN raise_exception_err_env(CPUX86State *nenv, int exception_index,
int error_code);
-void do_smm_enter(CPUState *env1);
+void do_smm_enter(CPUX86State *env1);
-void svm_check_intercept(CPUState *env1, uint32_t type);
+void svm_check_intercept(CPUX86State *env1, uint32_t type);
-uint32_t cpu_cc_compute_all(CPUState *env1, int op);
+uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
-void cpu_report_tpr_access(CPUState *env, TPRAccess access);
+void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
#endif /* CPU_I386_H */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 0d84c27..c702bd6 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -27,7 +27,7 @@
//#define DEBUG_MMU
/* NOTE: must be called outside the CPU execute loop */
-void cpu_state_reset(CPUState *env)
+void cpu_state_reset(CPUX86State *env)
{
int i;
@@ -106,7 +106,7 @@ void cpu_x86_close(CPUX86State *env)
g_free(env);
}
-static void cpu_x86_version(CPUState *env, int *family, int *model)
+static void cpu_x86_version(CPUX86State *env, int *family, int *model)
{
int cpuver = env->cpuid_version;
@@ -119,7 +119,7 @@ static void cpu_x86_version(CPUState *env, int *family, int *model)
}
/* Broadcast MCA signal for processor version 06H_EH and above */
-int cpu_x86_support_mca_broadcast(CPUState *env)
+int cpu_x86_support_mca_broadcast(CPUX86State *env)
{
int family = 0;
int model = 0;
@@ -191,7 +191,7 @@ static const char *cc_op_str[] = {
};
static void
-cpu_x86_dump_seg_cache(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, fprintf_function cpu_fprintf,
const char *name, struct SegmentCache *sc)
{
#ifdef TARGET_X86_64
@@ -248,7 +248,7 @@ done:
#define DUMP_CODE_BYTES_TOTAL 50
#define DUMP_CODE_BYTES_BACKWARD 20
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUX86State *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int eflags, i, nb;
@@ -857,7 +857,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUX86State *env, target_ulong addr)
{
target_ulong pde_addr, pte_addr;
uint64_t pte;
@@ -951,7 +951,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return paddr;
}
-void hw_breakpoint_insert(CPUState *env, int index)
+void hw_breakpoint_insert(CPUX86State *env, int index)
{
int type, err = 0;
@@ -979,7 +979,7 @@ void hw_breakpoint_insert(CPUState *env, int index)
env->cpu_breakpoint[index] = NULL;
}
-void hw_breakpoint_remove(CPUState *env, int index)
+void hw_breakpoint_remove(CPUX86State *env, int index)
{
if (!env->cpu_breakpoint[index])
return;
@@ -998,7 +998,7 @@ void hw_breakpoint_remove(CPUState *env, int index)
}
}
-int check_hw_breakpoints(CPUState *env, int force_dr6_update)
+int check_hw_breakpoints(CPUX86State *env, int force_dr6_update)
{
target_ulong dr6;
int reg, type;
@@ -1022,7 +1022,7 @@ int check_hw_breakpoints(CPUState *env, int force_dr6_update)
static CPUDebugExcpHandler *prev_debug_excp_handler;
-static void breakpoint_handler(CPUState *env)
+static void breakpoint_handler(CPUX86State *env)
{
CPUBreakpoint *bp;
@@ -1050,7 +1050,7 @@ static void breakpoint_handler(CPUState *env)
typedef struct MCEInjectionParams {
Monitor *mon;
- CPUState *env;
+ CPUX86State *env;
int bank;
uint64_t status;
uint64_t mcg_status;
@@ -1062,7 +1062,7 @@ typedef struct MCEInjectionParams {
static void do_inject_x86_mce(void *data)
{
MCEInjectionParams *params = data;
- CPUState *cenv = params->env;
+ CPUX86State *cenv = params->env;
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
cpu_synchronize_state(cenv);
@@ -1132,7 +1132,7 @@ static void do_inject_x86_mce(void *data)
}
}
-void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
+void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank,
uint64_t status, uint64_t mcg_status, uint64_t addr,
uint64_t misc, int flags)
{
@@ -1147,7 +1147,7 @@ void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
.flags = flags,
};
unsigned bank_num = cenv->mcg_cap & 0xff;
- CPUState *env;
+ CPUX86State *env;
if (!cenv->mcg_cap) {
monitor_printf(mon, "MCE injection not supported\n");
@@ -1184,7 +1184,7 @@ void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
}
}
-void cpu_report_tpr_access(CPUState *env, TPRAccess access)
+void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
{
TranslationBlock *tb;
@@ -1276,7 +1276,7 @@ CPUX86State *cpu_x86_init(const char *cpu_model)
}
#if !defined(CONFIG_USER_ONLY)
-void do_cpu_init(CPUState *env)
+void do_cpu_init(CPUX86State *env)
{
int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
uint64_t pat = env->pat;
@@ -1288,15 +1288,15 @@ void do_cpu_init(CPUState *env)
env->halted = !cpu_is_bsp(env);
}
-void do_cpu_sipi(CPUState *env)
+void do_cpu_sipi(CPUX86State *env)
{
apic_sipi(env->apic_state);
}
#else
-void do_cpu_init(CPUState *env)
+void do_cpu_init(CPUX86State *env)
{
}
-void do_cpu_sipi(CPUState *env)
+void do_cpu_sipi(CPUX86State *env)
{
}
#endif
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 619d773..e74a9e4 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -221,7 +221,7 @@ static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
return -ENOSYS;
}
-static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
+static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, int code)
{
uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
@@ -246,7 +246,7 @@ static void hardware_memory_error(void)
exit(1);
}
-int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
{
ram_addr_t ram_addr;
target_phys_addr_t paddr;
@@ -306,7 +306,7 @@ int kvm_arch_on_sigbus(int code, void *addr)
return 0;
}
-static int kvm_inject_mce_oldstyle(CPUState *env)
+static int kvm_inject_mce_oldstyle(CPUX86State *env)
{
if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
unsigned int bank, bank_num = env->mcg_cap & 0xff;
@@ -338,14 +338,14 @@ static int kvm_inject_mce_oldstyle(CPUState *env)
static void cpu_update_state(void *opaque, int running, RunState state)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
if (running) {
env->tsc_valid = false;
}
}
-int kvm_arch_init_vcpu(CPUState *env)
+int kvm_arch_init_vcpu(CPUX86State *env)
{
struct {
struct kvm_cpuid2 cpuid;
@@ -577,7 +577,7 @@ int kvm_arch_init_vcpu(CPUState *env)
return 0;
}
-void kvm_arch_reset_vcpu(CPUState *env)
+void kvm_arch_reset_vcpu(CPUX86State *env)
{
env->exception_injected = -1;
env->interrupt_injected = -1;
@@ -768,7 +768,7 @@ static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
}
}
-static int kvm_getput_regs(CPUState *env, int set)
+static int kvm_getput_regs(CPUX86State *env, int set)
{
struct kvm_regs regs;
int ret = 0;
@@ -809,7 +809,7 @@ static int kvm_getput_regs(CPUState *env, int set)
return ret;
}
-static int kvm_put_fpu(CPUState *env)
+static int kvm_put_fpu(CPUX86State *env)
{
struct kvm_fpu fpu;
int i;
@@ -841,7 +841,7 @@ static int kvm_put_fpu(CPUState *env)
#define XSAVE_XSTATE_BV 128
#define XSAVE_YMMH_SPACE 144
-static int kvm_put_xsave(CPUState *env)
+static int kvm_put_xsave(CPUX86State *env)
{
struct kvm_xsave* xsave = env->kvm_xsave_buf;
uint16_t cwd, swd, twd;
@@ -875,7 +875,7 @@ static int kvm_put_xsave(CPUState *env)
return r;
}
-static int kvm_put_xcrs(CPUState *env)
+static int kvm_put_xcrs(CPUX86State *env)
{
struct kvm_xcrs xcrs;
@@ -890,7 +890,7 @@ static int kvm_put_xcrs(CPUState *env)
return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
}
-static int kvm_put_sregs(CPUState *env)
+static int kvm_put_sregs(CPUX86State *env)
{
struct kvm_sregs sregs;
@@ -946,7 +946,7 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
entry->data = value;
}
-static int kvm_put_msrs(CPUState *env, int level)
+static int kvm_put_msrs(CPUX86State *env, int level)
{
struct {
struct kvm_msrs info;
@@ -1029,7 +1029,7 @@ static int kvm_put_msrs(CPUState *env, int level)
}
-static int kvm_get_fpu(CPUState *env)
+static int kvm_get_fpu(CPUX86State *env)
{
struct kvm_fpu fpu;
int i, ret;
@@ -1055,7 +1055,7 @@ static int kvm_get_fpu(CPUState *env)
return 0;
}
-static int kvm_get_xsave(CPUState *env)
+static int kvm_get_xsave(CPUX86State *env)
{
struct kvm_xsave* xsave = env->kvm_xsave_buf;
int ret, i;
@@ -1093,7 +1093,7 @@ static int kvm_get_xsave(CPUState *env)
return 0;
}
-static int kvm_get_xcrs(CPUState *env)
+static int kvm_get_xcrs(CPUX86State *env)
{
int i, ret;
struct kvm_xcrs xcrs;
@@ -1117,7 +1117,7 @@ static int kvm_get_xcrs(CPUState *env)
return 0;
}
-static int kvm_get_sregs(CPUState *env)
+static int kvm_get_sregs(CPUX86State *env)
{
struct kvm_sregs sregs;
uint32_t hflags;
@@ -1201,7 +1201,7 @@ static int kvm_get_sregs(CPUState *env)
return 0;
}
-static int kvm_get_msrs(CPUState *env)
+static int kvm_get_msrs(CPUX86State *env)
{
struct {
struct kvm_msrs info;
@@ -1331,14 +1331,14 @@ static int kvm_get_msrs(CPUState *env)
return 0;
}
-static int kvm_put_mp_state(CPUState *env)
+static int kvm_put_mp_state(CPUX86State *env)
{
struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
}
-static int kvm_get_mp_state(CPUState *env)
+static int kvm_get_mp_state(CPUX86State *env)
{
struct kvm_mp_state mp_state;
int ret;
@@ -1354,7 +1354,7 @@ static int kvm_get_mp_state(CPUState *env)
return 0;
}
-static int kvm_get_apic(CPUState *env)
+static int kvm_get_apic(CPUX86State *env)
{
DeviceState *apic = env->apic_state;
struct kvm_lapic_state kapic;
@@ -1371,7 +1371,7 @@ static int kvm_get_apic(CPUState *env)
return 0;
}
-static int kvm_put_apic(CPUState *env)
+static int kvm_put_apic(CPUX86State *env)
{
DeviceState *apic = env->apic_state;
struct kvm_lapic_state kapic;
@@ -1384,7 +1384,7 @@ static int kvm_put_apic(CPUState *env)
return 0;
}
-static int kvm_put_vcpu_events(CPUState *env, int level)
+static int kvm_put_vcpu_events(CPUX86State *env, int level)
{
struct kvm_vcpu_events events;
@@ -1418,7 +1418,7 @@ static int kvm_put_vcpu_events(CPUState *env, int level)
return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
}
-static int kvm_get_vcpu_events(CPUState *env)
+static int kvm_get_vcpu_events(CPUX86State *env)
{
struct kvm_vcpu_events events;
int ret;
@@ -1453,7 +1453,7 @@ static int kvm_get_vcpu_events(CPUState *env)
return 0;
}
-static int kvm_guest_debug_workarounds(CPUState *env)
+static int kvm_guest_debug_workarounds(CPUX86State *env)
{
int ret = 0;
unsigned long reinject_trap = 0;
@@ -1482,7 +1482,7 @@ static int kvm_guest_debug_workarounds(CPUState *env)
return ret;
}
-static int kvm_put_debugregs(CPUState *env)
+static int kvm_put_debugregs(CPUX86State *env)
{
struct kvm_debugregs dbgregs;
int i;
@@ -1501,7 +1501,7 @@ static int kvm_put_debugregs(CPUState *env)
return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
}
-static int kvm_get_debugregs(CPUState *env)
+static int kvm_get_debugregs(CPUX86State *env)
{
struct kvm_debugregs dbgregs;
int i, ret;
@@ -1523,7 +1523,7 @@ static int kvm_get_debugregs(CPUState *env)
return 0;
}
-int kvm_arch_put_registers(CPUState *env, int level)
+int kvm_arch_put_registers(CPUX86State *env, int level)
{
int ret;
@@ -1580,7 +1580,7 @@ int kvm_arch_put_registers(CPUState *env, int level)
return 0;
}
-int kvm_arch_get_registers(CPUState *env)
+int kvm_arch_get_registers(CPUX86State *env)
{
int ret;
@@ -1625,7 +1625,7 @@ int kvm_arch_get_registers(CPUState *env)
return 0;
}
-void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
+void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
{
int ret;
@@ -1685,7 +1685,7 @@ void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
}
}
-void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
+void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
{
if (run->if_flag) {
env->eflags |= IF_MASK;
@@ -1696,7 +1696,7 @@ void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
cpu_set_apic_base(env->apic_state, run->apic_base);
}
-int kvm_arch_process_async_events(CPUState *env)
+int kvm_arch_process_async_events(CPUX86State *env)
{
if (env->interrupt_request & CPU_INTERRUPT_MCE) {
/* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
@@ -1748,7 +1748,7 @@ int kvm_arch_process_async_events(CPUState *env)
return env->halted;
}
-static int kvm_handle_halt(CPUState *env)
+static int kvm_handle_halt(CPUX86State *env)
{
if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) &&
@@ -1760,7 +1760,7 @@ static int kvm_handle_halt(CPUState *env)
return 0;
}
-static int kvm_handle_tpr_access(CPUState *env)
+static int kvm_handle_tpr_access(CPUX86State *env)
{
struct kvm_run *run = env->kvm_run;
@@ -1770,7 +1770,7 @@ static int kvm_handle_tpr_access(CPUState *env)
return 1;
}
-int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
{
static const uint8_t int3 = 0xcc;
@@ -1781,7 +1781,7 @@ int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
return 0;
}
-int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
{
uint8_t int3;
@@ -1924,7 +1924,7 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
return ret;
}
-void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
+void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
{
const uint8_t type_code[] = {
[GDB_BREAKPOINT_HW] = 0x0,
@@ -1961,7 +1961,7 @@ static bool host_supports_vmx(void)
#define VMX_INVALID_GUEST_STATE 0x80000021
-int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
+int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
{
uint64_t code;
int ret;
@@ -2012,7 +2012,7 @@ int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
return ret;
}
-bool kvm_arch_stop_on_emulation_error(CPUState *env)
+bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
{
kvm_cpu_synchronize_state(env);
return !(env->cr[0] & CR0_PE_MASK) ||
diff --git a/target-i386/machine.c b/target-i386/machine.c
index d6e98ff..a8be058 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -171,14 +171,14 @@ static const VMStateInfo vmstate_fpreg_1_no_mmx = {
static bool fpregs_is_0(void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
return (env->fpregs_format_vmstate == 0);
}
static bool fpregs_is_1_mmx(void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
int guess_mmx;
guess_mmx = ((env->fptag_vmstate == 0xff) &&
@@ -188,7 +188,7 @@ static bool fpregs_is_1_mmx(void *opaque, int version_id)
static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
int guess_mmx;
guess_mmx = ((env->fptag_vmstate == 0xff) &&
@@ -237,7 +237,7 @@ static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
static void cpu_pre_save(void *opaque)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
int i;
/* FPU */
@@ -252,7 +252,7 @@ static void cpu_pre_save(void *opaque)
static int cpu_post_load(void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
int i;
/* XXX: restore FPU round state */
@@ -274,7 +274,7 @@ static int cpu_post_load(void *opaque, int version_id)
static bool async_pf_msr_needed(void *opaque)
{
- CPUState *cpu = opaque;
+ CPUX86State *cpu = opaque;
return cpu->async_pf_en_msr != 0;
}
@@ -285,14 +285,14 @@ static const VMStateDescription vmstate_async_pf_msr = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(async_pf_en_msr, CPUState),
+ VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
VMSTATE_END_OF_LIST()
}
};
static bool fpop_ip_dp_needed(void *opaque)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
}
@@ -303,16 +303,16 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT16(fpop, CPUState),
- VMSTATE_UINT64(fpip, CPUState),
- VMSTATE_UINT64(fpdp, CPUState),
+ VMSTATE_UINT16(fpop, CPUX86State),
+ VMSTATE_UINT64(fpip, CPUX86State),
+ VMSTATE_UINT64(fpdp, CPUX86State),
VMSTATE_END_OF_LIST()
}
};
static bool tscdeadline_needed(void *opaque)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
return env->tsc_deadline != 0;
}
@@ -323,14 +323,14 @@ static const VMStateDescription vmstate_msr_tscdeadline = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(tsc_deadline, CPUState),
+ VMSTATE_UINT64(tsc_deadline, CPUX86State),
VMSTATE_END_OF_LIST()
}
};
static bool misc_enable_needed(void *opaque)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
}
@@ -341,7 +341,7 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(msr_ia32_misc_enable, CPUState),
+ VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),
VMSTATE_END_OF_LIST()
}
};
@@ -354,98 +354,98 @@ static const VMStateDescription vmstate_cpu = {
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField []) {
- VMSTATE_UINTTL_ARRAY(regs, CPUState, CPU_NB_REGS),
- VMSTATE_UINTTL(eip, CPUState),
- VMSTATE_UINTTL(eflags, CPUState),
- VMSTATE_UINT32(hflags, CPUState),
+ VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
+ VMSTATE_UINTTL(eip, CPUX86State),
+ VMSTATE_UINTTL(eflags, CPUX86State),
+ VMSTATE_UINT32(hflags, CPUX86State),
/* FPU */
- VMSTATE_UINT16(fpuc, CPUState),
- VMSTATE_UINT16(fpus_vmstate, CPUState),
- VMSTATE_UINT16(fptag_vmstate, CPUState),
- VMSTATE_UINT16(fpregs_format_vmstate, CPUState),
- VMSTATE_FP_REGS(fpregs, CPUState, 8),
+ VMSTATE_UINT16(fpuc, CPUX86State),
+ VMSTATE_UINT16(fpus_vmstate, CPUX86State),
+ VMSTATE_UINT16(fptag_vmstate, CPUX86State),
+ VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),
+ VMSTATE_FP_REGS(fpregs, CPUX86State, 8),
- VMSTATE_SEGMENT_ARRAY(segs, CPUState, 6),
- VMSTATE_SEGMENT(ldt, CPUState),
- VMSTATE_SEGMENT(tr, CPUState),
- VMSTATE_SEGMENT(gdt, CPUState),
- VMSTATE_SEGMENT(idt, CPUState),
+ VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),
+ VMSTATE_SEGMENT(ldt, CPUX86State),
+ VMSTATE_SEGMENT(tr, CPUX86State),
+ VMSTATE_SEGMENT(gdt, CPUX86State),
+ VMSTATE_SEGMENT(idt, CPUX86State),
- VMSTATE_UINT32(sysenter_cs, CPUState),
+ VMSTATE_UINT32(sysenter_cs, CPUX86State),
#ifdef TARGET_X86_64
/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
- VMSTATE_HACK_UINT32(sysenter_esp, CPUState, less_than_7),
- VMSTATE_HACK_UINT32(sysenter_eip, CPUState, less_than_7),
- VMSTATE_UINTTL_V(sysenter_esp, CPUState, 7),
- VMSTATE_UINTTL_V(sysenter_eip, CPUState, 7),
+ VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),
+ VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),
+ VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),
+ VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),
#else
- VMSTATE_UINTTL(sysenter_esp, CPUState),
- VMSTATE_UINTTL(sysenter_eip, CPUState),
+ VMSTATE_UINTTL(sysenter_esp, CPUX86State),
+ VMSTATE_UINTTL(sysenter_eip, CPUX86State),
#endif
- VMSTATE_UINTTL(cr[0], CPUState),
- VMSTATE_UINTTL(cr[2], CPUState),
- VMSTATE_UINTTL(cr[3], CPUState),
- VMSTATE_UINTTL(cr[4], CPUState),
- VMSTATE_UINTTL_ARRAY(dr, CPUState, 8),
+ VMSTATE_UINTTL(cr[0], CPUX86State),
+ VMSTATE_UINTTL(cr[2], CPUX86State),
+ VMSTATE_UINTTL(cr[3], CPUX86State),
+ VMSTATE_UINTTL(cr[4], CPUX86State),
+ VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),
/* MMU */
- VMSTATE_INT32(a20_mask, CPUState),
+ VMSTATE_INT32(a20_mask, CPUX86State),
/* XMM */
- VMSTATE_UINT32(mxcsr, CPUState),
- VMSTATE_XMM_REGS(xmm_regs, CPUState, CPU_NB_REGS),
+ VMSTATE_UINT32(mxcsr, CPUX86State),
+ VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),
#ifdef TARGET_X86_64
- VMSTATE_UINT64(efer, CPUState),
- VMSTATE_UINT64(star, CPUState),
- VMSTATE_UINT64(lstar, CPUState),
- VMSTATE_UINT64(cstar, CPUState),
- VMSTATE_UINT64(fmask, CPUState),
- VMSTATE_UINT64(kernelgsbase, CPUState),
+ VMSTATE_UINT64(efer, CPUX86State),
+ VMSTATE_UINT64(star, CPUX86State),
+ VMSTATE_UINT64(lstar, CPUX86State),
+ VMSTATE_UINT64(cstar, CPUX86State),
+ VMSTATE_UINT64(fmask, CPUX86State),
+ VMSTATE_UINT64(kernelgsbase, CPUX86State),
#endif
- VMSTATE_UINT32_V(smbase, CPUState, 4),
+ VMSTATE_UINT32_V(smbase, CPUX86State, 4),
- VMSTATE_UINT64_V(pat, CPUState, 5),
- VMSTATE_UINT32_V(hflags2, CPUState, 5),
+ VMSTATE_UINT64_V(pat, CPUX86State, 5),
+ VMSTATE_UINT32_V(hflags2, CPUX86State, 5),
- VMSTATE_UINT32_TEST(halted, CPUState, version_is_5),
- VMSTATE_UINT64_V(vm_hsave, CPUState, 5),
- VMSTATE_UINT64_V(vm_vmcb, CPUState, 5),
- VMSTATE_UINT64_V(tsc_offset, CPUState, 5),
- VMSTATE_UINT64_V(intercept, CPUState, 5),
- VMSTATE_UINT16_V(intercept_cr_read, CPUState, 5),
- VMSTATE_UINT16_V(intercept_cr_write, CPUState, 5),
- VMSTATE_UINT16_V(intercept_dr_read, CPUState, 5),
- VMSTATE_UINT16_V(intercept_dr_write, CPUState, 5),
- VMSTATE_UINT32_V(intercept_exceptions, CPUState, 5),
- VMSTATE_UINT8_V(v_tpr, CPUState, 5),
+ VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),
+ VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),
+ VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),
+ VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),
+ VMSTATE_UINT64_V(intercept, CPUX86State, 5),
+ VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),
+ VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),
+ VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),
+ VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),
+ VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),
+ VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),
/* MTRRs */
- VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUState, 11, 8),
- VMSTATE_UINT64_V(mtrr_deftype, CPUState, 8),
- VMSTATE_MTRR_VARS(mtrr_var, CPUState, 8, 8),
+ VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),
+ VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),
+ VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),
/* KVM-related states */
- VMSTATE_INT32_V(interrupt_injected, CPUState, 9),
- VMSTATE_UINT32_V(mp_state, CPUState, 9),
- VMSTATE_UINT64_V(tsc, CPUState, 9),
- VMSTATE_INT32_V(exception_injected, CPUState, 11),
- VMSTATE_UINT8_V(soft_interrupt, CPUState, 11),
- VMSTATE_UINT8_V(nmi_injected, CPUState, 11),
- VMSTATE_UINT8_V(nmi_pending, CPUState, 11),
- VMSTATE_UINT8_V(has_error_code, CPUState, 11),
- VMSTATE_UINT32_V(sipi_vector, CPUState, 11),
+ VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),
+ VMSTATE_UINT32_V(mp_state, CPUX86State, 9),
+ VMSTATE_UINT64_V(tsc, CPUX86State, 9),
+ VMSTATE_INT32_V(exception_injected, CPUX86State, 11),
+ VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),
+ VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),
+ VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),
+ VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),
+ VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),
/* MCE */
- VMSTATE_UINT64_V(mcg_cap, CPUState, 10),
- VMSTATE_UINT64_V(mcg_status, CPUState, 10),
- VMSTATE_UINT64_V(mcg_ctl, CPUState, 10),
- VMSTATE_UINT64_ARRAY_V(mce_banks, CPUState, MCE_BANKS_DEF *4, 10),
+ VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),
+ VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),
+ VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),
+ VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),
/* rdtscp */
- VMSTATE_UINT64_V(tsc_aux, CPUState, 11),
+ VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),
/* KVM pvclock msr */
- VMSTATE_UINT64_V(system_time_msr, CPUState, 11),
- VMSTATE_UINT64_V(wall_clock_msr, CPUState, 11),
+ VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),
+ VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),
/* XSAVE related fields */
- VMSTATE_UINT64_V(xcr0, CPUState, 12),
- VMSTATE_UINT64_V(xstate_bv, CPUState, 12),
- VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12),
+ VMSTATE_UINT64_V(xcr0, CPUX86State, 12),
+ VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),
+ VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),
VMSTATE_END_OF_LIST()
/* The above list is not sorted /wrt version numbers, watch out! */
},
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 63a08d6..c04ae44 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -125,7 +125,7 @@ static inline void load_eflags(int eflags, int update_mask)
/* load efer and update the corresponding hflags. XXX: do consistency
checks with cpuid bits ? */
-static inline void cpu_load_efer(CPUState *env, uint64_t val)
+static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
{
env->efer = val;
env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
@@ -1376,9 +1376,9 @@ static void do_interrupt_all(int intno, int is_int, int error_code,
#endif
}
-void do_interrupt(CPUState *env1)
+void do_interrupt(CPUX86State *env1)
{
- CPUState *saved_env;
+ CPUX86State *saved_env;
saved_env = env;
env = env1;
@@ -1406,9 +1406,9 @@ void do_interrupt(CPUState *env1)
env = saved_env;
}
-void do_interrupt_x86_hardirq(CPUState *env1, int intno, int is_hw)
+void do_interrupt_x86_hardirq(CPUX86State *env1, int intno, int is_hw)
{
- CPUState *saved_env;
+ CPUX86State *saved_env;
saved_env = env;
env = env1;
@@ -1492,7 +1492,7 @@ static void QEMU_NORETURN raise_exception_err(int exception_index,
raise_interrupt(exception_index, 0, error_code, 0);
}
-void raise_exception_err_env(CPUState *nenv, int exception_index,
+void raise_exception_err_env(CPUX86State *nenv, int exception_index,
int error_code)
{
env = nenv;
@@ -1504,7 +1504,7 @@ static void QEMU_NORETURN raise_exception(int exception_index)
raise_interrupt(exception_index, 0, 0, 0);
}
-void raise_exception_env(int exception_index, CPUState *nenv)
+void raise_exception_env(int exception_index, CPUX86State *nenv)
{
env = nenv;
raise_exception(exception_index);
@@ -1513,7 +1513,7 @@ void raise_exception_env(int exception_index, CPUState *nenv)
#if defined(CONFIG_USER_ONLY)
-void do_smm_enter(CPUState *env1)
+void do_smm_enter(CPUX86State *env1)
{
}
@@ -1529,12 +1529,12 @@ void helper_rsm(void)
#define SMM_REVISION_ID 0x00020000
#endif
-void do_smm_enter(CPUState *env1)
+void do_smm_enter(CPUX86State *env1)
{
target_ulong sm_state;
SegmentCache *dt;
int i, offset;
- CPUState *saved_env;
+ CPUX86State *saved_env;
saved_env = env;
env = env1;
@@ -5002,7 +5002,7 @@ void helper_boundl(target_ulong a0, int v)
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUX86State *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
@@ -5066,7 +5066,7 @@ void helper_svm_check_intercept_param(uint32_t type, uint64_t param)
{
}
-void svm_check_intercept(CPUState *env1, uint32_t type)
+void svm_check_intercept(CPUX86State *env1, uint32_t type)
{
}
@@ -5101,7 +5101,7 @@ static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc)
}
static inline void svm_load_seg_cache(target_phys_addr_t addr,
- CPUState *env, int seg_reg)
+ CPUX86State *env, int seg_reg)
{
SegmentCache sc1, *sc = &sc1;
svm_load_seg(addr, sc);
@@ -5460,9 +5460,9 @@ void helper_svm_check_intercept_param(uint32_t type, uint64_t param)
}
}
-void svm_check_intercept(CPUState *env1, uint32_t type)
+void svm_check_intercept(CPUX86State *env1, uint32_t type)
{
- CPUState *saved_env;
+ CPUX86State *saved_env;
saved_env = env;
env = env1;
@@ -5840,9 +5840,9 @@ uint32_t helper_cc_compute_all(int op)
}
}
-uint32_t cpu_cc_compute_all(CPUState *env1, int op)
+uint32_t cpu_cc_compute_all(CPUX86State *env1, int op)
{
- CPUState *saved_env;
+ CPUX86State *saved_env;
uint32_t ret;
saved_env = env;
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 860b4a3..c1ede1a 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -388,7 +388,7 @@ static inline void gen_op_addl_T0_T1(void)
static inline void gen_op_jmp_T0(void)
{
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
+ tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
}
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
@@ -453,12 +453,12 @@ static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
static inline void gen_op_movl_A0_seg(int reg)
{
- tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
+ tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
}
static inline void gen_op_addl_A0_seg(int reg)
{
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
+ tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
#ifdef TARGET_X86_64
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
@@ -468,12 +468,12 @@ static inline void gen_op_addl_A0_seg(int reg)
#ifdef TARGET_X86_64
static inline void gen_op_movq_A0_seg(int reg)
{
- tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
+ tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
}
static inline void gen_op_addq_A0_seg(int reg)
{
- tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
+ tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
@@ -583,7 +583,7 @@ static inline void gen_op_st_T1_A0(int idx)
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
+ tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
}
static inline void gen_string_movl_A0_ESI(DisasContext *s)
@@ -644,7 +644,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)
static inline void gen_op_movl_T0_Dshift(int ot)
{
- tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
+ tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
};
@@ -6466,11 +6466,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
break;
case 0xfc: /* cld */
tcg_gen_movi_i32(cpu_tmp2_i32, 1);
- tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
+ tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
break;
case 0xfd: /* std */
tcg_gen_movi_i32(cpu_tmp2_i32, -1);
- tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
+ tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
break;
/************************/
@@ -7645,64 +7645,64 @@ void optimize_flags_init(void)
{
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, cc_op), "cc_op");
- cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
+ offsetof(CPUX86State, cc_op), "cc_op");
+ cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
"cc_src");
- cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
+ cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
"cc_dst");
- cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
+ cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_tmp),
"cc_tmp");
#ifdef TARGET_X86_64
cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_EAX]), "rax");
+ offsetof(CPUX86State, regs[R_EAX]), "rax");
cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_ECX]), "rcx");
+ offsetof(CPUX86State, regs[R_ECX]), "rcx");
cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_EDX]), "rdx");
+ offsetof(CPUX86State, regs[R_EDX]), "rdx");
cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_EBX]), "rbx");
+ offsetof(CPUX86State, regs[R_EBX]), "rbx");
cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_ESP]), "rsp");
+ offsetof(CPUX86State, regs[R_ESP]), "rsp");
cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_EBP]), "rbp");
+ offsetof(CPUX86State, regs[R_EBP]), "rbp");
cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_ESI]), "rsi");
+ offsetof(CPUX86State, regs[R_ESI]), "rsi");
cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[R_EDI]), "rdi");
+ offsetof(CPUX86State, regs[R_EDI]), "rdi");
cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[8]), "r8");
+ offsetof(CPUX86State, regs[8]), "r8");
cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[9]), "r9");
+ offsetof(CPUX86State, regs[9]), "r9");
cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[10]), "r10");
+ offsetof(CPUX86State, regs[10]), "r10");
cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[11]), "r11");
+ offsetof(CPUX86State, regs[11]), "r11");
cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[12]), "r12");
+ offsetof(CPUX86State, regs[12]), "r12");
cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[13]), "r13");
+ offsetof(CPUX86State, regs[13]), "r13");
cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[14]), "r14");
+ offsetof(CPUX86State, regs[14]), "r14");
cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, regs[15]), "r15");
+ offsetof(CPUX86State, regs[15]), "r15");
#else
cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_EAX]), "eax");
+ offsetof(CPUX86State, regs[R_EAX]), "eax");
cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_ECX]), "ecx");
+ offsetof(CPUX86State, regs[R_ECX]), "ecx");
cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_EDX]), "edx");
+ offsetof(CPUX86State, regs[R_EDX]), "edx");
cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_EBX]), "ebx");
+ offsetof(CPUX86State, regs[R_EBX]), "ebx");
cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_ESP]), "esp");
+ offsetof(CPUX86State, regs[R_ESP]), "esp");
cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_EBP]), "ebp");
+ offsetof(CPUX86State, regs[R_EBP]), "ebp");
cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_ESI]), "esi");
+ offsetof(CPUX86State, regs[R_ESI]), "esi");
cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[R_EDI]), "edi");
+ offsetof(CPUX86State, regs[R_EDI]), "edi");
#endif
/* register helpers */
@@ -7713,7 +7713,7 @@ void optimize_flags_init(void)
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline void gen_intermediate_code_internal(CPUState *env,
+static inline void gen_intermediate_code_internal(CPUX86State *env,
TranslationBlock *tb,
int search_pc)
{
@@ -7890,17 +7890,17 @@ static inline void gen_intermediate_code_internal(CPUState *env,
}
}
-void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
{
int cc_op;
#ifdef DEBUG_DISAS
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (15 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 16/44] target-i386: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: " Andreas Färber
` (26 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPULM32State/g" target-lm32/*.[hc]
sed -i "s/#define CPULM32State/#define CPUState/" target-lm32/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-lm32/cpu.h | 28 ++++++++++++++--------------
target-lm32/helper.c | 16 ++++++++--------
target-lm32/machine.c | 22 +++++++++++-----------
target-lm32/op_helper.c | 4 ++--
target-lm32/translate.c | 38 +++++++++++++++++++-------------------
5 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index cc9b53b..684b2fa 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -36,7 +36,7 @@ typedef struct CPULM32State CPULM32State;
#define NB_MMU_MODES 1
#define TARGET_PAGE_BITS 12
-static inline int cpu_mmu_index(CPUState *env)
+static inline int cpu_mmu_index(CPULM32State *env)
{
return 0;
}
@@ -185,18 +185,18 @@ typedef struct CPULM32State {
} CPULM32State;
-CPUState *cpu_lm32_init(const char *cpu_model);
+CPULM32State *cpu_lm32_init(const char *cpu_model);
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
-int cpu_lm32_exec(CPUState *s);
-void cpu_lm32_close(CPUState *s);
-void do_interrupt(CPUState *env);
+int cpu_lm32_exec(CPULM32State *s);
+void cpu_lm32_close(CPULM32State *s);
+void do_interrupt(CPULM32State *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
int cpu_lm32_signal_handler(int host_signum, void *pinfo,
void *puc);
void lm32_translate_init(void);
-void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
+void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
#define cpu_list cpu_lm32_list
#define cpu_init cpu_lm32_init
@@ -206,12 +206,12 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
#define CPU_SAVE_VERSION 1
-int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPULM32State *env, target_ulong newsp)
{
if (newsp) {
env->regs[R_SP] = newsp;
@@ -220,23 +220,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
}
#endif
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPULM32State *env, target_ulong newtls)
{
}
-static inline int cpu_interrupts_enabled(CPUState *env)
+static inline int cpu_interrupts_enabled(CPULM32State *env)
{
return env->ie & IE_IE;
}
#include "cpu-all.h"
-static inline target_ulong cpu_get_pc(CPUState *env)
+static inline target_ulong cpu_get_pc(CPULM32State *env)
{
return env->pc;
}
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -244,14 +244,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*flags = 0;
}
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPULM32State *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPULM32State *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 6834401..5db8f8d 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -20,7 +20,7 @@
#include "cpu.h"
#include "host-utils.h"
-int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx)
{
int prot;
@@ -37,12 +37,12 @@ int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
{
return addr & TARGET_PAGE_MASK;
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPULM32State *env)
{
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%x type=%x\n", env->pc, env->exception_index);
@@ -192,9 +192,9 @@ static uint32_t cfg_by_def(const LM32Def *def)
return cfg;
}
-CPUState *cpu_lm32_init(const char *cpu_model)
+CPULM32State *cpu_lm32_init(const char *cpu_model)
{
- CPUState *env;
+ CPULM32State *env;
const LM32Def *def;
static int tcg_initialized;
@@ -203,7 +203,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
return NULL;
}
- env = g_malloc0(sizeof(CPUState));
+ env = g_malloc0(sizeof(CPULM32State));
env->features = def->features;
env->num_bps = def->num_breakpoints;
@@ -226,7 +226,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
* 0x80000000-0xffffffff is not cached and used to access IO devices. */
-void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
+void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
{
if (value) {
env->flags |= LM32_FLAG_IGNORE_MSB;
@@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
}
}
-void cpu_state_reset(CPUState *env)
+void cpu_state_reset(CPULM32State *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index 70ca52a..6802e81 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -7,17 +7,17 @@ static const VMStateDescription vmstate_cpu = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, CPUState, 32),
- VMSTATE_UINT32(pc, CPUState),
- VMSTATE_UINT32(ie, CPUState),
- VMSTATE_UINT32(icc, CPUState),
- VMSTATE_UINT32(dcc, CPUState),
- VMSTATE_UINT32(cc, CPUState),
- VMSTATE_UINT32(eba, CPUState),
- VMSTATE_UINT32(dc, CPUState),
- VMSTATE_UINT32(deba, CPUState),
- VMSTATE_UINT32_ARRAY(bp, CPUState, 4),
- VMSTATE_UINT32_ARRAY(wp, CPUState, 4),
+ VMSTATE_UINT32_ARRAY(regs, CPULM32State, 32),
+ VMSTATE_UINT32(pc, CPULM32State),
+ VMSTATE_UINT32(ie, CPULM32State),
+ VMSTATE_UINT32(icc, CPULM32State),
+ VMSTATE_UINT32(dcc, CPULM32State),
+ VMSTATE_UINT32(cc, CPULM32State),
+ VMSTATE_UINT32(eba, CPULM32State),
+ VMSTATE_UINT32(dc, CPULM32State),
+ VMSTATE_UINT32(deba, CPULM32State),
+ VMSTATE_UINT32_ARRAY(bp, CPULM32State, 4),
+ VMSTATE_UINT32_ARRAY(wp, CPULM32State, 4),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 02be134..e9c9638 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -75,11 +75,11 @@ uint32_t helper_rcsr_jrx(void)
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPULM32State *saved_env;
unsigned long pc;
int ret;
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index c80e48b..872a2ba 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -64,7 +64,7 @@ enum {
/* This is the state at translation time. */
typedef struct DisasContext {
- CPUState *env;
+ CPULM32State *env;
target_ulong pc;
/* Decoder. */
@@ -987,7 +987,7 @@ static inline void decode(DisasContext *dc)
decinfo[dc->opcode](dc);
}
-static void check_breakpoint(CPUState *env, DisasContext *dc)
+static void check_breakpoint(CPULM32State *env, DisasContext *dc)
{
CPUBreakpoint *bp;
@@ -1003,7 +1003,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
}
/* generate intermediate code for basic block 'tb'. */
-static void gen_intermediate_code_internal(CPUState *env,
+static void gen_intermediate_code_internal(CPULM32State *env,
TranslationBlock *tb, int search_pc)
{
struct DisasContext ctx, *dc = &ctx;
@@ -1129,17 +1129,17 @@ static void gen_intermediate_code_internal(CPUState *env,
#endif
}
-void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -1171,7 +1171,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n\n");
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
@@ -1184,48 +1184,48 @@ void lm32_translate_init(void)
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPULM32State, regs[i]),
regnames[i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, bp[i]),
+ offsetof(CPULM32State, bp[i]),
regnames[32+i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, wp[i]),
+ offsetof(CPULM32State, wp[i]),
regnames[36+i]);
}
cpu_pc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, pc),
+ offsetof(CPULM32State, pc),
"pc");
cpu_ie = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, ie),
+ offsetof(CPULM32State, ie),
"ie");
cpu_icc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, icc),
+ offsetof(CPULM32State, icc),
"icc");
cpu_dcc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, dcc),
+ offsetof(CPULM32State, dcc),
"dcc");
cpu_cc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc),
+ offsetof(CPULM32State, cc),
"cc");
cpu_cfg = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cfg),
+ offsetof(CPULM32State, cfg),
"cfg");
cpu_eba = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, eba),
+ offsetof(CPULM32State, eba),
"eba");
cpu_dc = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, dc),
+ offsetof(CPULM32State, dc),
"dc");
cpu_deba = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, deba),
+ offsetof(CPULM32State, deba),
"deba");
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (16 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: " Andreas Färber
` (25 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUM68KState/g" target-m68k/*.[hc]
sed -i "s/#define CPUM68KState/#define CPUState/" target-m68k/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-m68k/cpu.h | 16 +++++-----
target-m68k/helper.c | 78 +++++++++++++++++++++++-----------------------
target-m68k/op_helper.c | 20 ++++++------
target-m68k/translate.c | 16 +++++-----
4 files changed, 65 insertions(+), 65 deletions(-)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 4cc3a35..2c83b89 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -120,8 +120,8 @@ void m68k_tcg_init(void);
CPUM68KState *cpu_m68k_init(const char *cpu_model);
int cpu_m68k_exec(CPUM68KState *s);
void cpu_m68k_close(CPUM68KState *s);
-void do_interrupt(CPUState *env1);
-void do_interrupt_m68k_hardirq(CPUState *env1);
+void do_interrupt(CPUM68KState *env1);
+void do_interrupt_m68k_hardirq(CPUM68KState *env1);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -226,17 +226,17 @@ void register_m68k_insns (CPUM68KState *env);
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUM68KState *env)
{
return (env->sr & SR_S) == 0 ? 1 : 0;
}
-int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp)
{
if (newsp)
env->aregs[7] = newsp;
@@ -246,7 +246,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#include "cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -256,14 +256,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
}
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUM68KState *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUM68KState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 3647366..1feed9b 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -56,7 +56,7 @@ void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf)
}
}
-static int fpu_gdb_get_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
stfq_p(mem_buf, env->fregs[n]);
@@ -70,7 +70,7 @@ static int fpu_gdb_get_reg(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int fpu_gdb_set_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
env->fregs[n] = ldfq_p(mem_buf);
@@ -338,7 +338,7 @@ void m68k_switch_sp(CPUM68KState *env)
#if defined(CONFIG_USER_ONLY)
-int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
int mmu_idx)
{
env->exception_index = EXCP_ACCESS;
@@ -351,12 +351,12 @@ int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
/* MMU */
/* TODO: This will need fixing once the MMU is implemented. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUM68KState *env, target_ulong addr)
{
return addr;
}
-int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
int mmu_idx)
{
int prot;
@@ -407,7 +407,7 @@ uint32_t HELPER(sats)(uint32_t val, uint32_t ccr)
return val;
}
-uint32_t HELPER(subx_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+uint32_t HELPER(subx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2)
{
uint32_t res;
uint32_t old_flags;
@@ -430,7 +430,7 @@ uint32_t HELPER(subx_cc)(CPUState *env, uint32_t op1, uint32_t op2)
return res;
}
-uint32_t HELPER(addx_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+uint32_t HELPER(addx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2)
{
uint32_t res;
uint32_t old_flags;
@@ -458,13 +458,13 @@ uint32_t HELPER(xflag_lt)(uint32_t a, uint32_t b)
return a < b;
}
-void HELPER(set_sr)(CPUState *env, uint32_t val)
+void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
{
env->sr = val & 0xffff;
m68k_switch_sp(env);
}
-uint32_t HELPER(shl_cc)(CPUState *env, uint32_t val, uint32_t shift)
+uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
{
uint32_t result;
uint32_t cf;
@@ -489,7 +489,7 @@ uint32_t HELPER(shl_cc)(CPUState *env, uint32_t val, uint32_t shift)
return result;
}
-uint32_t HELPER(shr_cc)(CPUState *env, uint32_t val, uint32_t shift)
+uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
{
uint32_t result;
uint32_t cf;
@@ -514,7 +514,7 @@ uint32_t HELPER(shr_cc)(CPUState *env, uint32_t val, uint32_t shift)
return result;
}
-uint32_t HELPER(sar_cc)(CPUState *env, uint32_t val, uint32_t shift)
+uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
{
uint32_t result;
uint32_t cf;
@@ -537,37 +537,37 @@ uint32_t HELPER(sar_cc)(CPUState *env, uint32_t val, uint32_t shift)
}
/* FPU helpers. */
-uint32_t HELPER(f64_to_i32)(CPUState *env, float64 val)
+uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
{
return float64_to_int32(val, &env->fp_status);
}
-float32 HELPER(f64_to_f32)(CPUState *env, float64 val)
+float32 HELPER(f64_to_f32)(CPUM68KState *env, float64 val)
{
return float64_to_float32(val, &env->fp_status);
}
-float64 HELPER(i32_to_f64)(CPUState *env, uint32_t val)
+float64 HELPER(i32_to_f64)(CPUM68KState *env, uint32_t val)
{
return int32_to_float64(val, &env->fp_status);
}
-float64 HELPER(f32_to_f64)(CPUState *env, float32 val)
+float64 HELPER(f32_to_f64)(CPUM68KState *env, float32 val)
{
return float32_to_float64(val, &env->fp_status);
}
-float64 HELPER(iround_f64)(CPUState *env, float64 val)
+float64 HELPER(iround_f64)(CPUM68KState *env, float64 val)
{
return float64_round_to_int(val, &env->fp_status);
}
-float64 HELPER(itrunc_f64)(CPUState *env, float64 val)
+float64 HELPER(itrunc_f64)(CPUM68KState *env, float64 val)
{
return float64_trunc_to_int(val, &env->fp_status);
}
-float64 HELPER(sqrt_f64)(CPUState *env, float64 val)
+float64 HELPER(sqrt_f64)(CPUM68KState *env, float64 val)
{
return float64_sqrt(val, &env->fp_status);
}
@@ -582,27 +582,27 @@ float64 HELPER(chs_f64)(float64 val)
return float64_chs(val);
}
-float64 HELPER(add_f64)(CPUState *env, float64 a, float64 b)
+float64 HELPER(add_f64)(CPUM68KState *env, float64 a, float64 b)
{
return float64_add(a, b, &env->fp_status);
}
-float64 HELPER(sub_f64)(CPUState *env, float64 a, float64 b)
+float64 HELPER(sub_f64)(CPUM68KState *env, float64 a, float64 b)
{
return float64_sub(a, b, &env->fp_status);
}
-float64 HELPER(mul_f64)(CPUState *env, float64 a, float64 b)
+float64 HELPER(mul_f64)(CPUM68KState *env, float64 a, float64 b)
{
return float64_mul(a, b, &env->fp_status);
}
-float64 HELPER(div_f64)(CPUState *env, float64 a, float64 b)
+float64 HELPER(div_f64)(CPUM68KState *env, float64 a, float64 b)
{
return float64_div(a, b, &env->fp_status);
}
-float64 HELPER(sub_cmp_f64)(CPUState *env, float64 a, float64 b)
+float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
{
/* ??? This may incorrectly raise exceptions. */
/* ??? Should flush denormals to zero. */
@@ -620,7 +620,7 @@ float64 HELPER(sub_cmp_f64)(CPUState *env, float64 a, float64 b)
return res;
}
-uint32_t HELPER(compare_f64)(CPUState *env, float64 val)
+uint32_t HELPER(compare_f64)(CPUM68KState *env, float64 val)
{
return float64_compare_quiet(val, float64_zero, &env->fp_status);
}
@@ -629,7 +629,7 @@ uint32_t HELPER(compare_f64)(CPUState *env, float64 val)
/* FIXME: The MAC unit implementation is a bit of a mess. Some helpers
take values, others take register numbers and manipulate the contents
in-place. */
-void HELPER(mac_move)(CPUState *env, uint32_t dest, uint32_t src)
+void HELPER(mac_move)(CPUM68KState *env, uint32_t dest, uint32_t src)
{
uint32_t mask;
env->macc[dest] = env->macc[src];
@@ -640,7 +640,7 @@ void HELPER(mac_move)(CPUState *env, uint32_t dest, uint32_t src)
env->macsr &= ~mask;
}
-uint64_t HELPER(macmuls)(CPUState *env, uint32_t op1, uint32_t op2)
+uint64_t HELPER(macmuls)(CPUM68KState *env, uint32_t op1, uint32_t op2)
{
int64_t product;
int64_t res;
@@ -660,7 +660,7 @@ uint64_t HELPER(macmuls)(CPUState *env, uint32_t op1, uint32_t op2)
return res;
}
-uint64_t HELPER(macmulu)(CPUState *env, uint32_t op1, uint32_t op2)
+uint64_t HELPER(macmulu)(CPUM68KState *env, uint32_t op1, uint32_t op2)
{
uint64_t product;
@@ -677,7 +677,7 @@ uint64_t HELPER(macmulu)(CPUState *env, uint32_t op1, uint32_t op2)
return product;
}
-uint64_t HELPER(macmulf)(CPUState *env, uint32_t op1, uint32_t op2)
+uint64_t HELPER(macmulf)(CPUM68KState *env, uint32_t op1, uint32_t op2)
{
uint64_t product;
uint32_t remainder;
@@ -696,7 +696,7 @@ uint64_t HELPER(macmulf)(CPUState *env, uint32_t op1, uint32_t op2)
return product;
}
-void HELPER(macsats)(CPUState *env, uint32_t acc)
+void HELPER(macsats)(CPUM68KState *env, uint32_t acc)
{
int64_t tmp;
int64_t result;
@@ -717,7 +717,7 @@ void HELPER(macsats)(CPUState *env, uint32_t acc)
env->macc[acc] = result;
}
-void HELPER(macsatu)(CPUState *env, uint32_t acc)
+void HELPER(macsatu)(CPUM68KState *env, uint32_t acc)
{
uint64_t val;
@@ -739,7 +739,7 @@ void HELPER(macsatu)(CPUState *env, uint32_t acc)
env->macc[acc] = val;
}
-void HELPER(macsatf)(CPUState *env, uint32_t acc)
+void HELPER(macsatf)(CPUM68KState *env, uint32_t acc)
{
int64_t sum;
int64_t result;
@@ -758,7 +758,7 @@ void HELPER(macsatf)(CPUState *env, uint32_t acc)
env->macc[acc] = result;
}
-void HELPER(mac_set_flags)(CPUState *env, uint32_t acc)
+void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc)
{
uint64_t val;
val = env->macc[acc];
@@ -784,12 +784,12 @@ void HELPER(mac_set_flags)(CPUState *env, uint32_t acc)
}
}
-void HELPER(flush_flags)(CPUState *env, uint32_t cc_op)
+void HELPER(flush_flags)(CPUM68KState *env, uint32_t cc_op)
{
cpu_m68k_flush_flags(env, cc_op);
}
-uint32_t HELPER(get_macf)(CPUState *env, uint64_t val)
+uint32_t HELPER(get_macf)(CPUM68KState *env, uint64_t val)
{
int rem;
uint32_t result;
@@ -858,7 +858,7 @@ uint32_t HELPER(get_macu)(uint64_t val)
}
}
-uint32_t HELPER(get_mac_extf)(CPUState *env, uint32_t acc)
+uint32_t HELPER(get_mac_extf)(CPUM68KState *env, uint32_t acc)
{
uint32_t val;
val = env->macc[acc] & 0x00ff;
@@ -868,7 +868,7 @@ uint32_t HELPER(get_mac_extf)(CPUState *env, uint32_t acc)
return val;
}
-uint32_t HELPER(get_mac_exti)(CPUState *env, uint32_t acc)
+uint32_t HELPER(get_mac_exti)(CPUM68KState *env, uint32_t acc)
{
uint32_t val;
val = (env->macc[acc] >> 32) & 0xffff;
@@ -876,7 +876,7 @@ uint32_t HELPER(get_mac_exti)(CPUState *env, uint32_t acc)
return val;
}
-void HELPER(set_mac_extf)(CPUState *env, uint32_t val, uint32_t acc)
+void HELPER(set_mac_extf)(CPUM68KState *env, uint32_t val, uint32_t acc)
{
int64_t res;
int32_t tmp;
@@ -892,7 +892,7 @@ void HELPER(set_mac_extf)(CPUState *env, uint32_t val, uint32_t acc)
env->macc[acc + 1] = res;
}
-void HELPER(set_mac_exts)(CPUState *env, uint32_t val, uint32_t acc)
+void HELPER(set_mac_exts)(CPUM68KState *env, uint32_t val, uint32_t acc)
{
int64_t res;
int32_t tmp;
@@ -906,7 +906,7 @@ void HELPER(set_mac_exts)(CPUState *env, uint32_t val, uint32_t acc)
env->macc[acc + 1] = res;
}
-void HELPER(set_mac_extu)(CPUState *env, uint32_t val, uint32_t acc)
+void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc)
{
uint64_t res;
res = (uint32_t)env->macc[acc];
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 2f7fe6b..bc8c1f0 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -22,12 +22,12 @@
#if defined(CONFIG_USER_ONLY)
-void do_interrupt(CPUState *env1)
+void do_interrupt(CPUM68KState *env1)
{
env1->exception_index = -1;
}
-void do_interrupt_m68k_hardirq(CPUState *env1)
+void do_interrupt_m68k_hardirq(CPUM68KState *env1)
{
}
@@ -55,11 +55,11 @@ extern int semihosting_enabled;
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUM68KState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUM68KState *saved_env;
unsigned long pc;
int ret;
@@ -161,9 +161,9 @@ static void do_interrupt_all(int is_hw)
env->pc = ldl_kernel(env->vbr + vector);
}
-void do_interrupt(CPUState *env1)
+void do_interrupt(CPUM68KState *env1)
{
- CPUState *saved_env;
+ CPUM68KState *saved_env;
saved_env = env;
env = env1;
@@ -171,9 +171,9 @@ void do_interrupt(CPUState *env1)
env = saved_env;
}
-void do_interrupt_m68k_hardirq(CPUState *env1)
+void do_interrupt_m68k_hardirq(CPUM68KState *env1)
{
- CPUState *saved_env;
+ CPUM68KState *saved_env;
saved_env = env;
env = env1;
@@ -193,7 +193,7 @@ void HELPER(raise_exception)(uint32_t tt)
raise_exception(tt);
}
-void HELPER(divu)(CPUState *env, uint32_t word)
+void HELPER(divu)(CPUM68KState *env, uint32_t word)
{
uint32_t num;
uint32_t den;
@@ -223,7 +223,7 @@ void HELPER(divu)(CPUState *env, uint32_t word)
env->cc_dest = flags;
}
-void HELPER(divs)(CPUState *env, uint32_t word)
+void HELPER(divs)(CPUM68KState *env, uint32_t word)
{
int32_t num;
int32_t den;
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 2bdd9dd..9fc1e31 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -68,8 +68,8 @@ void m68k_tcg_init(void)
char *p;
int i;
-#define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, offset), #name);
-#define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, offset), #name);
+#define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
+#define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
#define DEFF64(name, offset) DEFO64(name, offset)
#include "qregs.def"
#undef DEFO32
@@ -2937,7 +2937,7 @@ void register_m68k_insns (CPUM68KState *env)
/* ??? Some of this implementation is not exception safe. We should always
write back the result to memory before setting the condition codes. */
-static void disas_m68k_insn(CPUState * env, DisasContext *s)
+static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
{
uint16_t insn;
@@ -2949,7 +2949,7 @@ static void disas_m68k_insn(CPUState * env, DisasContext *s)
/* generate intermediate code for basic block 'tb'. */
static inline void
-gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
+gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb,
int search_pc)
{
DisasContext dc1, *dc = &dc1;
@@ -3072,17 +3072,17 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
//expand_target_qops();
}
-void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUM68KState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -3103,7 +3103,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (17 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 20/44] target-mips: " Andreas Färber
` (24 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUMBState/g" target-microblaze/*.[hc]
sed -i "s/#define CPUMBState/#define CPUState/" target-microblaze/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-microblaze/cpu.h | 30 +++++++++++-----------
target-microblaze/helper.c | 10 ++++----
target-microblaze/mmu.c | 8 +++---
target-microblaze/mmu.h | 6 ++--
target-microblaze/op_helper.c | 8 +++---
target-microblaze/translate.c | 52 ++++++++++++++++++++--------------------
6 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 94ec43b..6ae5649 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -250,7 +250,7 @@ typedef struct CPUMBState {
#define DRTE_FLAG (1 << 17)
#define DRTB_FLAG (1 << 18)
#define D_FLAG (1 << 19) /* Bit in ESR. */
-/* TB dependent CPUState. */
+/* TB dependent CPUMBState. */
#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
uint32_t iflags;
@@ -266,10 +266,10 @@ typedef struct CPUMBState {
CPU_COMMON
} CPUMBState;
-CPUState *cpu_mb_init(const char *cpu_model);
-int cpu_mb_exec(CPUState *s);
-void cpu_mb_close(CPUState *s);
-void do_interrupt(CPUState *env);
+CPUMBState *cpu_mb_init(const char *cpu_model);
+int cpu_mb_exec(CPUMBState *s);
+void cpu_mb_close(CPUMBState *s);
+void do_interrupt(CPUMBState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -305,7 +305,7 @@ enum {
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUMBState *env)
{
/* Are we in nommu mode?. */
if (!(env->sregs[SR_MSR] & MSR_VM))
@@ -316,12 +316,12 @@ static inline int cpu_mmu_index (CPUState *env)
return MMU_KERNEL_IDX;
}
-int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUMBState *env, target_ulong newsp)
{
if (newsp)
env->regs[R_SP] = newsp;
@@ -329,23 +329,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
}
#endif
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls)
{
}
-static inline int cpu_interrupts_enabled(CPUState *env)
+static inline int cpu_interrupts_enabled(CPUMBState *env)
{
return env->sregs[SR_MSR] & MSR_IE;
}
#include "cpu-all.h"
-static inline target_ulong cpu_get_pc(CPUState *env)
+static inline target_ulong cpu_get_pc(CPUMBState *env)
{
return env->sregs[SR_PC];
}
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->sregs[SR_PC];
@@ -355,18 +355,18 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size);
#endif
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUMBState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb)
{
env->sregs[SR_PC] = tb->pc;
}
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index e1355ff..6e0e411 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -25,13 +25,13 @@
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUMBState *env)
{
env->exception_index = -1;
env->regs[14] = env->sregs[SR_PC];
}
-int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
+int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
int mmu_idx)
{
env->exception_index = 0xaa;
@@ -41,7 +41,7 @@ int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
#else /* !CONFIG_USER_ONLY */
-int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
int mmu_idx)
{
unsigned int hit;
@@ -107,7 +107,7 @@ int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
return r;
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUMBState *env)
{
uint32_t t;
@@ -255,7 +255,7 @@ void do_interrupt(CPUState *env)
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
{
target_ulong vaddr, paddr = 0;
struct microblaze_mmu_lookup lu;
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index 7c34ac0..43092e5 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -31,7 +31,7 @@ static unsigned int tlb_decode_size(unsigned int f)
return sizes[f];
}
-static void mmu_flush_idx(CPUState *env, unsigned int idx)
+static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
@@ -51,7 +51,7 @@ static void mmu_flush_idx(CPUState *env, unsigned int idx)
}
}
-static void mmu_change_pid(CPUState *env, unsigned int newpid)
+static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
{
struct microblaze_mmu *mmu = &env->mmu;
unsigned int i;
@@ -175,7 +175,7 @@ done:
}
/* Writes/reads to the MMU's special regs end up here. */
-uint32_t mmu_read(CPUState *env, uint32_t rn)
+uint32_t mmu_read(CPUMBState *env, uint32_t rn)
{
unsigned int i;
uint32_t r;
@@ -215,7 +215,7 @@ uint32_t mmu_read(CPUState *env, uint32_t rn)
return r;
}
-void mmu_write(CPUState *env, uint32_t rn, uint32_t v)
+void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
unsigned int i;
D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
diff --git a/target-microblaze/mmu.h b/target-microblaze/mmu.h
index 56149a5..3f74dda 100644
--- a/target-microblaze/mmu.h
+++ b/target-microblaze/mmu.h
@@ -82,10 +82,10 @@ struct microblaze_mmu_lookup
} err;
};
-void mmu_flip_um(CPUState *env, unsigned int um);
+void mmu_flip_um(CPUMBState *env, unsigned int um);
unsigned int mmu_translate(struct microblaze_mmu *mmu,
struct microblaze_mmu_lookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
-uint32_t mmu_read(CPUState *env, uint32_t rn);
-void mmu_write(CPUState *env, uint32_t rn, uint32_t v);
+uint32_t mmu_read(CPUMBState *env, uint32_t rn);
+void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v);
void mmu_init(struct microblaze_mmu *mmu);
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 7232c71..76cc0e0 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -42,11 +42,11 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUMBState *saved_env;
unsigned long pc;
int ret;
@@ -506,10 +506,10 @@ void helper_mmu_write(uint32_t rn, uint32_t v)
mmu_write(env, rn, v);
}
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
- CPUState *saved_env;
+ CPUMBState *saved_env;
saved_env = env;
env = env1;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index e34e88d..64cbfb8 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -53,7 +53,7 @@ static TCGv env_iflags;
/* This is the state at translation time. */
typedef struct DisasContext {
- CPUState *env;
+ CPUMBState *env;
target_ulong pc;
/* Decoder. */
@@ -519,10 +519,10 @@ static void dec_msr(DisasContext *dc)
tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
break;
case 0x800:
- tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, slr));
+ tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
break;
case 0x802:
- tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, shr));
+ tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
break;
default:
cpu_abort(dc->env, "unknown mts reg %x\n", sr);
@@ -551,10 +551,10 @@ static void dec_msr(DisasContext *dc)
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
break;
case 0x800:
- tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, slr));
+ tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
break;
case 0x802:
- tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, shr));
+ tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
break;
case 0x2000:
case 0x2001:
@@ -571,7 +571,7 @@ static void dec_msr(DisasContext *dc)
case 0x200c:
rn = sr & 0xf;
tcg_gen_ld_tl(cpu_R[dc->rd],
- cpu_env, offsetof(CPUState, pvr.regs[rn]));
+ cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
break;
default:
cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
@@ -1222,7 +1222,7 @@ static void dec_bcc(DisasContext *dc)
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
- cpu_env, offsetof(CPUState, bimm));
+ cpu_env, offsetof(CPUMBState, bimm));
}
if (dec_alu_op_b_is_small_imm(dc)) {
@@ -1267,7 +1267,7 @@ static void dec_br(DisasContext *dc)
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
- cpu_env, offsetof(CPUState, bimm));
+ cpu_env, offsetof(CPUMBState, bimm));
}
if (link && dc->rd)
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
@@ -1366,7 +1366,7 @@ static void dec_rts(DisasContext *dc)
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
- cpu_env, offsetof(CPUState, bimm));
+ cpu_env, offsetof(CPUMBState, bimm));
if (i_bit) {
LOG_DIS("rtid ir=%x\n", dc->ir);
@@ -1632,7 +1632,7 @@ static inline void decode(DisasContext *dc)
}
}
-static void check_breakpoint(CPUState *env, DisasContext *dc)
+static void check_breakpoint(CPUMBState *env, DisasContext *dc)
{
CPUBreakpoint *bp;
@@ -1648,7 +1648,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
/* generate intermediate code for basic block 'tb'. */
static void
-gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
+gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
int search_pc)
{
uint16_t *gen_opc_end;
@@ -1850,17 +1850,17 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
assert(!dc->abort_at_next_insn);
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -1888,13 +1888,13 @@ void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n\n");
}
-CPUState *cpu_mb_init (const char *cpu_model)
+CPUMBState *cpu_mb_init (const char *cpu_model)
{
- CPUState *env;
+ CPUMBState *env;
static int tcg_initialized = 0;
int i;
- env = g_malloc0(sizeof(CPUState));
+ env = g_malloc0(sizeof(CPUMBState));
cpu_exec_init(env);
cpu_state_reset(env);
@@ -1909,28 +1909,28 @@ CPUState *cpu_mb_init (const char *cpu_model)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
env_debug = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, debug),
+ offsetof(CPUMBState, debug),
"debug0");
env_iflags = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, iflags),
+ offsetof(CPUMBState, iflags),
"iflags");
env_imm = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, imm),
+ offsetof(CPUMBState, imm),
"imm");
env_btarget = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btarget),
+ offsetof(CPUMBState, btarget),
"btarget");
env_btaken = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btaken),
+ offsetof(CPUMBState, btaken),
"btaken");
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPUMBState, regs[i]),
regnames[i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, sregs[i]),
+ offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
}
#define GEN_HELPER 2
@@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
return env;
}
-void cpu_state_reset(CPUState *env)
+void cpu_state_reset(CPUMBState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -1991,7 +1991,7 @@ void cpu_state_reset(CPUState *env)
#endif
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
{
env->sregs[SR_PC] = gen_opc_pc[pc_pos];
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 20/44] target-mips: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (18 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: " Andreas Färber
` (23 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc]
sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-mips/cpu.h | 40 +++---
target-mips/helper.c | 24 ++--
target-mips/machine.c | 4 +-
target-mips/op_helper.c | 124 ++++++++--------
target-mips/translate.c | 356 +++++++++++++++++++++++-----------------------
5 files changed, 274 insertions(+), 274 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 71cb4e8..94381ec 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -495,7 +495,7 @@ void r4k_helper_tlbwr (void);
void r4k_helper_tlbp (void);
void r4k_helper_tlbr (void);
-void cpu_unassigned_access(CPUState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
int is_write, int is_exec, int unused, int size);
#endif
@@ -515,12 +515,12 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUMIPSState *env)
{
return env->hflags & MIPS_HFLAG_KSU;
}
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
{
if (newsp)
env->active_tc.gpr[29] = newsp;
@@ -528,7 +528,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->active_tc.gpr[2] = 0;
}
-static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
+static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
int32_t pending;
int32_t status;
@@ -636,28 +636,28 @@ CPUMIPSState *cpu_mips_init(const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
/* mips_timer.c */
-uint32_t cpu_mips_get_random (CPUState *env);
-uint32_t cpu_mips_get_count (CPUState *env);
-void cpu_mips_store_count (CPUState *env, uint32_t value);
-void cpu_mips_store_compare (CPUState *env, uint32_t value);
-void cpu_mips_start_count(CPUState *env);
-void cpu_mips_stop_count(CPUState *env);
+uint32_t cpu_mips_get_random (CPUMIPSState *env);
+uint32_t cpu_mips_get_count (CPUMIPSState *env);
+void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
+void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
+void cpu_mips_start_count(CPUMIPSState *env);
+void cpu_mips_stop_count(CPUMIPSState *env);
/* mips_int.c */
-void cpu_mips_soft_irq(CPUState *env, int irq, int level);
+void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* helper.c */
-int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
-void do_interrupt (CPUState *env);
+void do_interrupt (CPUMIPSState *env);
#if !defined(CONFIG_USER_ONLY)
-void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
-target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
+void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
+target_phys_addr_t cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
int rw);
#endif
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->active_tc.PC;
@@ -665,12 +665,12 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
}
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
{
env->tls_value = newtls;
}
-static inline int mips_vpe_active(CPUState *env)
+static inline int mips_vpe_active(CPUMIPSState *env)
{
int active = 1;
@@ -701,7 +701,7 @@ static inline int mips_vpe_active(CPUState *env)
return active;
}
-static inline int cpu_has_work(CPUState *env)
+static inline int cpu_has_work(CPUMIPSState *env)
{
int has_work = 0;
@@ -730,7 +730,7 @@ static inline int cpu_has_work(CPUState *env)
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
{
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 4d1cf98..ddf9cb7 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -36,7 +36,7 @@ enum {
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
-int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
@@ -45,7 +45,7 @@ int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
@@ -63,7 +63,7 @@ int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *pro
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint8_t ASID = env->CP0_EntryHi & 0xFF;
@@ -99,7 +99,7 @@ int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
return TLBRET_NOMATCH;
}
-static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@@ -201,7 +201,7 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
}
#endif
-static void raise_mmu_exception(CPUState *env, target_ulong address,
+static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
int exception = 0, error_code = 0;
@@ -254,7 +254,7 @@ static void raise_mmu_exception(CPUState *env, target_ulong address,
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
{
target_phys_addr_t phys_addr;
int prot;
@@ -265,7 +265,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
}
#endif
-int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int mmu_idx)
{
#if !defined(CONFIG_USER_ONLY)
@@ -308,7 +308,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
+target_phys_addr_t cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
{
target_phys_addr_t physical;
int prot;
@@ -367,7 +367,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
};
#if !defined(CONFIG_USER_ONLY)
-static target_ulong exception_resume_pc (CPUState *env)
+static target_ulong exception_resume_pc (CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@@ -383,7 +383,7 @@ static target_ulong exception_resume_pc (CPUState *env)
return bad_pc;
}
-static void set_hflags_for_handler (CPUState *env)
+static void set_hflags_for_handler (CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
env->hflags &= ~(MIPS_HFLAG_M16);
@@ -396,7 +396,7 @@ static void set_hflags_for_handler (CPUState *env)
}
#endif
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUMIPSState *env)
{
#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
@@ -637,7 +637,7 @@ void do_interrupt (CPUState *env)
}
#if !defined(CONFIG_USER_ONLY)
-void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
+void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
{
r4k_tlb_t *tlb;
target_ulong addr;
diff --git a/target-mips/machine.c b/target-mips/machine.c
index a506ee0..23504ba 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -42,7 +42,7 @@ static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
void cpu_save(QEMUFile *f, void *opaque)
{
- CPUState *env = opaque;
+ CPUMIPSState *env = opaque;
int i;
/* Save active TC */
@@ -190,7 +190,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUMIPSState *env = opaque;
int i;
if (version_id != 3)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 87e9799..3a20731 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -29,10 +29,10 @@
#endif /* !defined(CONFIG_USER_ONLY) */
#ifndef CONFIG_USER_ONLY
-static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global);
+static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
#endif
-static inline void compute_hflags(CPUState *env)
+static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
@@ -750,14 +750,14 @@ void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
#ifndef CONFIG_USER_ONLY
/* SMP helpers. */
-static int mips_vpe_is_wfi(CPUState *c)
+static int mips_vpe_is_wfi(CPUMIPSState *c)
{
/* If the VPE is halted but otherwise active, it means it's waiting for
an interrupt. */
return c->halted && mips_vpe_active(c);
}
-static inline void mips_vpe_wake(CPUState *c)
+static inline void mips_vpe_wake(CPUMIPSState *c)
{
/* Dont set ->halted = 0 directly, let it be done via cpu_has_work
because there might be other conditions that state that c should
@@ -765,7 +765,7 @@ static inline void mips_vpe_wake(CPUState *c)
cpu_interrupt(c, CPU_INTERRUPT_WAKE);
}
-static inline void mips_vpe_sleep(CPUState *c)
+static inline void mips_vpe_sleep(CPUMIPSState *c)
{
/* The VPE was shut off, really go to bed.
Reset any old _WAKE requests. */
@@ -773,7 +773,7 @@ static inline void mips_vpe_sleep(CPUState *c)
cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
}
-static inline void mips_tc_wake(CPUState *c, int tc)
+static inline void mips_tc_wake(CPUMIPSState *c, int tc)
{
/* FIXME: TC reschedule. */
if (mips_vpe_active(c) && !mips_vpe_is_wfi(c)) {
@@ -781,7 +781,7 @@ static inline void mips_tc_wake(CPUState *c, int tc)
}
}
-static inline void mips_tc_sleep(CPUState *c, int tc)
+static inline void mips_tc_sleep(CPUMIPSState *c, int tc)
{
/* FIXME: TC reschedule. */
if (!mips_vpe_active(c)) {
@@ -791,14 +791,14 @@ static inline void mips_tc_sleep(CPUState *c, int tc)
/* tc should point to an int with the value of the global TC index.
This function will transform it into a local index within the
- returned CPUState.
+ returned CPUMIPSState.
FIXME: This code assumes that all VPEs have the same number of TCs,
which depends on runtime setup. Can probably be fixed by
- walking the list of CPUStates. */
-static CPUState *mips_cpu_map_tc(int *tc)
+ walking the list of CPUMIPSStates. */
+static CPUMIPSState *mips_cpu_map_tc(int *tc)
{
- CPUState *other;
+ CPUMIPSState *other;
int vpe_idx, nr_threads = env->nr_threads;
int tc_idx = *tc;
@@ -823,7 +823,7 @@ static CPUState *mips_cpu_map_tc(int *tc)
These helper call synchronizes the regs for a given cpu. */
/* Called for updates to CP0_Status. */
-static void sync_c0_status(CPUState *cpu, int tc)
+static void sync_c0_status(CPUMIPSState *cpu, int tc)
{
int32_t tcstatus, *tcst;
uint32_t v = cpu->CP0_Status;
@@ -858,7 +858,7 @@ static void sync_c0_status(CPUState *cpu, int tc)
}
/* Called for updates to CP0_TCStatus. */
-static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
+static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, target_ulong v)
{
uint32_t status;
uint32_t tcu, tmx, tasid, tksu;
@@ -889,7 +889,7 @@ static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
}
/* Called for updates to CP0_EntryHi. */
-static void sync_c0_entryhi(CPUState *cpu, int tc)
+static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
{
int32_t *tcst;
uint32_t asid, v = cpu->CP0_EntryHi;
@@ -935,7 +935,7 @@ target_ulong helper_mfc0_tcstatus (void)
target_ulong helper_mftc0_tcstatus(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCStatus;
@@ -951,7 +951,7 @@ target_ulong helper_mfc0_tcbind (void)
target_ulong helper_mftc0_tcbind(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCBind;
@@ -967,7 +967,7 @@ target_ulong helper_mfc0_tcrestart (void)
target_ulong helper_mftc0_tcrestart(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.PC;
@@ -983,7 +983,7 @@ target_ulong helper_mfc0_tchalt (void)
target_ulong helper_mftc0_tchalt(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCHalt;
@@ -999,7 +999,7 @@ target_ulong helper_mfc0_tccontext (void)
target_ulong helper_mftc0_tccontext(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCContext;
@@ -1015,7 +1015,7 @@ target_ulong helper_mfc0_tcschedule (void)
target_ulong helper_mftc0_tcschedule(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCSchedule;
@@ -1031,7 +1031,7 @@ target_ulong helper_mfc0_tcschefback (void)
target_ulong helper_mftc0_tcschefback(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCScheFBack;
@@ -1047,7 +1047,7 @@ target_ulong helper_mfc0_count (void)
target_ulong helper_mftc0_entryhi(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_EntryHi;
}
@@ -1056,7 +1056,7 @@ target_ulong helper_mftc0_cause(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
int32_t tccause;
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc) {
tccause = other->CP0_Cause;
@@ -1070,7 +1070,7 @@ target_ulong helper_mftc0_cause(void)
target_ulong helper_mftc0_status(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_Status;
}
@@ -1103,7 +1103,7 @@ target_ulong helper_mftc0_debug(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
int32_t tcstatus;
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
tcstatus = other->active_tc.CP0_Debug_tcstatus;
@@ -1201,7 +1201,7 @@ void helper_mtc0_vpecontrol (target_ulong arg1)
void helper_mttc0_vpecontrol(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
uint32_t mask;
uint32_t newval;
@@ -1217,7 +1217,7 @@ void helper_mttc0_vpecontrol(target_ulong arg1)
target_ulong helper_mftc0_vpecontrol(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
/* FIXME: Mask away return zero on read bits. */
return other->CP0_VPEControl;
}
@@ -1225,7 +1225,7 @@ target_ulong helper_mftc0_vpecontrol(void)
target_ulong helper_mftc0_vpeconf0(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_VPEConf0;
}
@@ -1250,7 +1250,7 @@ void helper_mtc0_vpeconf0 (target_ulong arg1)
void helper_mttc0_vpeconf0(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
uint32_t mask = 0;
uint32_t newval;
@@ -1311,7 +1311,7 @@ void helper_mtc0_tcstatus (target_ulong arg1)
void helper_mttc0_tcstatus (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCStatus = arg1;
@@ -1336,7 +1336,7 @@ void helper_mttc0_tcbind (target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
mask |= (1 << CP0TCBd_CurVPE);
@@ -1360,7 +1360,7 @@ void helper_mtc0_tcrestart (target_ulong arg1)
void helper_mttc0_tcrestart (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc) {
other->active_tc.PC = arg1;
@@ -1390,7 +1390,7 @@ void helper_mtc0_tchalt (target_ulong arg1)
void helper_mttc0_tchalt (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
// TODO: Halt TC / Restart (if allocated+active) TC.
@@ -1414,7 +1414,7 @@ void helper_mtc0_tccontext (target_ulong arg1)
void helper_mttc0_tccontext (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCContext = arg1;
@@ -1430,7 +1430,7 @@ void helper_mtc0_tcschedule (target_ulong arg1)
void helper_mttc0_tcschedule (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCSchedule = arg1;
@@ -1446,7 +1446,7 @@ void helper_mtc0_tcschefback (target_ulong arg1)
void helper_mttc0_tcschefback (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCScheFBack = arg1;
@@ -1542,7 +1542,7 @@ void helper_mtc0_entryhi (target_ulong arg1)
void helper_mttc0_entryhi(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
other->CP0_EntryHi = arg1;
sync_c0_entryhi(other, other_tc);
@@ -1584,7 +1584,7 @@ void helper_mtc0_status (target_ulong arg1)
void helper_mttc0_status(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
other->CP0_Status = arg1 & ~0xf1000018;
sync_c0_status(other, other_tc);
@@ -1602,7 +1602,7 @@ void helper_mtc0_srsctl (target_ulong arg1)
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
}
-static void mtc0_cause(CPUState *cpu, target_ulong arg1)
+static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
{
uint32_t mask = 0x00C00300;
uint32_t old = cpu->CP0_Cause;
@@ -1638,7 +1638,7 @@ void helper_mtc0_cause(target_ulong arg1)
void helper_mttc0_cause(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
mtc0_cause(other, arg1);
}
@@ -1646,7 +1646,7 @@ void helper_mttc0_cause(target_ulong arg1)
target_ulong helper_mftc0_epc(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_EPC;
}
@@ -1654,7 +1654,7 @@ target_ulong helper_mftc0_epc(void)
target_ulong helper_mftc0_ebase(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_EBase;
}
@@ -1668,14 +1668,14 @@ void helper_mtc0_ebase (target_ulong arg1)
void helper_mttc0_ebase(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
}
target_ulong helper_mftc0_configx(target_ulong idx)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
switch (idx) {
case 0: return other->CP0_Config0;
@@ -1746,7 +1746,7 @@ void helper_mttc0_debug(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
/* XXX: Might be wrong, check with EJTAG spec. */
if (other_tc == other->current_tc)
@@ -1787,7 +1787,7 @@ void helper_mtc0_datahi (target_ulong arg1)
target_ulong helper_mftgpr(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.gpr[sel];
@@ -1798,7 +1798,7 @@ target_ulong helper_mftgpr(uint32_t sel)
target_ulong helper_mftlo(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.LO[sel];
@@ -1809,7 +1809,7 @@ target_ulong helper_mftlo(uint32_t sel)
target_ulong helper_mfthi(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.HI[sel];
@@ -1820,7 +1820,7 @@ target_ulong helper_mfthi(uint32_t sel)
target_ulong helper_mftacx(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.ACX[sel];
@@ -1831,7 +1831,7 @@ target_ulong helper_mftacx(uint32_t sel)
target_ulong helper_mftdsp(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.DSPControl;
@@ -1842,7 +1842,7 @@ target_ulong helper_mftdsp(void)
void helper_mttgpr(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.gpr[sel] = arg1;
@@ -1853,7 +1853,7 @@ void helper_mttgpr(target_ulong arg1, uint32_t sel)
void helper_mttlo(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.LO[sel] = arg1;
@@ -1864,7 +1864,7 @@ void helper_mttlo(target_ulong arg1, uint32_t sel)
void helper_mtthi(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.HI[sel] = arg1;
@@ -1875,7 +1875,7 @@ void helper_mtthi(target_ulong arg1, uint32_t sel)
void helper_mttacx(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.ACX[sel] = arg1;
@@ -1886,7 +1886,7 @@ void helper_mttacx(target_ulong arg1, uint32_t sel)
void helper_mttdsp(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
- CPUState *other = mips_cpu_map_tc(&other_tc);
+ CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.DSPControl = arg1;
@@ -1909,7 +1909,7 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(void)
{
- CPUState *other_cpu = first_cpu;
+ CPUMIPSState *other_cpu = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
do {
@@ -1925,7 +1925,7 @@ target_ulong helper_dvpe(void)
target_ulong helper_evpe(void)
{
- CPUState *other_cpu = first_cpu;
+ CPUMIPSState *other_cpu = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
do {
@@ -1981,14 +1981,14 @@ target_ulong helper_yield(target_ulong arg)
#ifndef CONFIG_USER_ONLY
/* TLB management */
-static void cpu_mips_tlb_flush (CPUState *env, int flush_global)
+static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
{
/* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush (env, flush_global);
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
-static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
+static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
while (env->tlb->tlb_in_use > first) {
@@ -2316,11 +2316,11 @@ static void do_unaligned_access (target_ulong addr, int is_write, int is_user, v
helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
}
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUMIPSState *saved_env;
unsigned long pc;
int ret;
@@ -2343,7 +2343,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
env = saved_env;
}
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUMIPSState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int unused, int size)
{
env = env1;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 5061e78..a663b74 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -602,7 +602,7 @@ static inline void gen_load_srsgpr (int from, int to)
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
@@ -625,7 +625,7 @@ static inline void gen_store_srsgpr (int from, int to)
TCGv_ptr addr = tcg_temp_new_ptr();
gen_load_gpr(t0, from);
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
@@ -642,28 +642,28 @@ static inline void gen_store_srsgpr (int from, int to)
/* Floating point register moves. */
static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
{
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
}
static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
{
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
}
static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
{
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
}
static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
{
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
}
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
- tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
+ tcg_gen_ld_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d));
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -678,7 +678,7 @@ static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
- tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
+ tcg_gen_st_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d));
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -728,7 +728,7 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
}
}
-static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
+static inline void restore_cpu_state (CPUMIPSState *env, DisasContext *ctx)
{
ctx->saved_hflags = ctx->hflags;
switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
@@ -826,7 +826,7 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs)
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
-static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
+static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags)
{
if (unlikely(!(env->insn_flags & flags)))
generate_exception(ctx, EXCP_RI);
@@ -940,8 +940,8 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
- tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
+ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
tcg_temp_free(t0); \
}
#else
@@ -967,14 +967,14 @@ static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx)
\
tcg_gen_andi_tl(t0, arg2, almask); \
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
- tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
+ tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \
generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
- tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
+ tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
gen_helper_0i(raise_exception, EXCP_SC); \
gen_set_label(l2); \
tcg_gen_movi_tl(t0, 0); \
@@ -1025,7 +1025,7 @@ static target_ulong pc_relative_pc (DisasContext *ctx)
}
/* Load */
-static void gen_ld (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rt, int base, int16_t offset)
{
const char *opn = "ld";
@@ -1313,7 +1313,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
tcg_temp_free(t0);
}
-static void gen_cop1_ldst(CPUState *env, DisasContext *ctx,
+static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx,
uint32_t op, int rt, int rs, int16_t imm)
{
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
@@ -1325,7 +1325,7 @@ static void gen_cop1_ldst(CPUState *env, DisasContext *ctx,
}
/* Arithmetic with immediate operand */
-static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_arith_imm (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rt, int rs, int16_t imm)
{
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
@@ -1413,7 +1413,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
}
/* Logic with immediate operand */
-static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
+static void gen_logic_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm)
{
target_ulong uimm;
const char *opn = "imm logic";
@@ -1456,7 +1456,7 @@ static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t
}
/* Set on less than with immediate operand */
-static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
+static void gen_slt_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm)
{
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
const char *opn = "imm arith";
@@ -1485,7 +1485,7 @@ static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t im
}
/* Shifts with immediate operand */
-static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_shift_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rt, int rs, int16_t imm)
{
target_ulong uimm = ((uint16_t)imm) & 0x1f;
@@ -1577,7 +1577,7 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
}
/* Arithmetic */
-static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_arith (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "arith";
@@ -1757,7 +1757,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
}
/* Conditional move */
-static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_cond_move (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
{
const char *opn = "cond move";
int l1;
@@ -1795,7 +1795,7 @@ static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
}
/* Logic */
-static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_logic (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
{
const char *opn = "logic";
@@ -1856,7 +1856,7 @@ static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
}
/* Set on lower than */
-static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_slt (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
{
const char *opn = "slt";
TCGv t0, t1;
@@ -1888,7 +1888,7 @@ static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
}
/* Shifts */
-static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_shift (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "shifts";
@@ -3171,7 +3171,7 @@ static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
tcg_gen_st_tl(arg, cpu_env, off);
}
-static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -3182,7 +3182,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 0:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
rn = "Index";
break;
case 1:
@@ -3212,37 +3212,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
+ gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
+ gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
+ gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
rn = "VPEOpt";
break;
default:
@@ -3252,7 +3252,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 2:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
tcg_gen_ext32s_tl(arg, arg);
rn = "EntryLo0";
break;
@@ -3298,7 +3298,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 3:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
tcg_gen_ext32s_tl(arg, arg);
rn = "EntryLo1";
break;
@@ -3309,7 +3309,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
rn = "Context";
break;
@@ -3324,12 +3324,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 5:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
rn = "PageGrain";
break;
default:
@@ -3339,32 +3339,32 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 6:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
default:
@@ -3375,7 +3375,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
rn = "HWREna";
break;
default:
@@ -3385,7 +3385,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
rn = "BadVAddr";
break;
@@ -3416,7 +3416,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
rn = "EntryHi";
break;
@@ -3427,7 +3427,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 11:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -3438,22 +3438,22 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 12:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
rn = "SRSMap";
break;
default:
@@ -3463,7 +3463,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 13:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
rn = "Cause";
break;
default:
@@ -3473,7 +3473,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
rn = "EPC";
break;
@@ -3484,12 +3484,12 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 15:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
rn = "EBase";
break;
default:
@@ -3499,29 +3499,29 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 16:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
rn = "Config";
break;
case 1:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
rn = "Config1";
break;
case 2:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
rn = "Config2";
break;
case 3:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
/* 4,5 are reserved */
/* 6,7 are implementation dependent */
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
rn = "Config6";
break;
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
rn = "Config7";
break;
default:
@@ -3563,7 +3563,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
tcg_gen_ext32s_tl(arg, arg);
rn = "XContext";
break;
@@ -3576,7 +3576,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
rn = "Framemask";
break;
default:
@@ -3617,7 +3617,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
rn = "DEPC";
break;
@@ -3628,7 +3628,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 25:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
rn = "Performance0";
break;
case 1:
@@ -3683,14 +3683,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
rn = "DataLo";
break;
default:
@@ -3703,14 +3703,14 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
rn = "DataHi";
break;
default:
@@ -3720,7 +3720,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
rn = "ErrorEPC";
break;
@@ -3732,7 +3732,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
switch (sel) {
case 0:
/* EJTAG support */
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -3751,7 +3751,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -3815,12 +3815,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -4024,7 +4024,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
@@ -4047,7 +4047,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 14:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -4207,7 +4207,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -4310,7 +4310,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
case 30:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -4321,7 +4321,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -4348,7 +4348,7 @@ die:
}
#if defined(TARGET_MIPS64)
-static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -4359,7 +4359,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 0:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
rn = "Index";
break;
case 1:
@@ -4389,37 +4389,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
rn = "VPEOpt";
break;
default:
@@ -4429,7 +4429,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 2:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
case 1:
@@ -4474,7 +4474,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 3:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
default:
@@ -4484,7 +4484,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
rn = "Context";
break;
case 1:
@@ -4498,12 +4498,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 5:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
rn = "PageGrain";
break;
default:
@@ -4513,32 +4513,32 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 6:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
default:
@@ -4549,7 +4549,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
rn = "HWREna";
break;
default:
@@ -4559,7 +4559,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
rn = "BadVAddr";
break;
default:
@@ -4589,7 +4589,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
rn = "EntryHi";
break;
default:
@@ -4599,7 +4599,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 11:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -4610,22 +4610,22 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 12:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
rn = "SRSMap";
break;
default:
@@ -4635,7 +4635,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 13:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
rn = "Cause";
break;
default:
@@ -4645,7 +4645,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -4655,12 +4655,12 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 15:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
rn = "EBase";
break;
default:
@@ -4670,28 +4670,28 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 16:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
rn = "Config";
break;
case 1:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
rn = "Config1";
break;
case 2:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
rn = "Config2";
break;
case 3:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
/* 6,7 are implementation dependent */
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
rn = "Config6";
break;
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
rn = "Config7";
break;
default:
@@ -4732,7 +4732,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
rn = "XContext";
break;
default:
@@ -4743,7 +4743,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
rn = "Framemask";
break;
default:
@@ -4784,7 +4784,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -4794,7 +4794,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 25:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
rn = "Performance0";
break;
case 1:
@@ -4850,14 +4850,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
rn = "DataLo";
break;
default:
@@ -4870,14 +4870,14 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
rn = "DataHi";
break;
default:
@@ -4887,7 +4887,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -4898,7 +4898,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
switch (sel) {
case 0:
/* EJTAG support */
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -4917,7 +4917,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -4981,12 +4981,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -5194,7 +5194,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
@@ -5227,7 +5227,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 14:
switch (sel) {
case 0:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -5374,7 +5374,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -5477,7 +5477,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
case 30:
switch (sel) {
case 0:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -5488,7 +5488,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -5515,7 +5515,7 @@ die:
}
#endif /* TARGET_MIPS64 */
-static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
+static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -5732,7 +5732,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
+static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -5929,7 +5929,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
+static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
{
const char *opn = "ldst";
@@ -6053,7 +6053,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
#endif /* !CONFIG_USER_ONLY */
/* CP1 Branches (before delay slot) */
-static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
+static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t op,
int32_t cc, int32_t offset)
{
target_ulong btarget;
@@ -8108,7 +8108,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
}
static void
-gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd)
+gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
{
TCGv t0;
@@ -8138,7 +8138,7 @@ gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd)
break;
case 29:
#if defined(CONFIG_USER_ONLY)
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, tls_value));
gen_store_gpr(t0, rt);
break;
#else
@@ -8153,7 +8153,7 @@ gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd)
tcg_temp_free(t0);
}
-static void handle_delay_slot (CPUState *env, DisasContext *ctx,
+static void handle_delay_slot (CPUMIPSState *env, DisasContext *ctx,
int insn_bytes)
{
if (ctx->hflags & MIPS_HFLAG_BMASK) {
@@ -8619,7 +8619,7 @@ static void gen_addiupc (DisasContext *ctx, int rx, int imm,
}
#if defined(TARGET_MIPS64)
-static void decode_i64_mips16 (CPUState *env, DisasContext *ctx,
+static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx,
int ry, int funct, int16_t offset,
int extended)
{
@@ -8671,7 +8671,7 @@ static void decode_i64_mips16 (CPUState *env, DisasContext *ctx,
}
#endif
-static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx,
+static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
int *is_branch)
{
int extend = lduw_code(ctx->pc + 2);
@@ -8863,7 +8863,7 @@ static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx,
return 4;
}
-static int decode_mips16_opc (CPUState *env, DisasContext *ctx,
+static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
int *is_branch)
{
int rx, ry;
@@ -9777,14 +9777,14 @@ static int mmreg2 (int r)
/* Zero-extended immediate */
#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
-static void gen_addiur1sp (CPUState *env, DisasContext *ctx)
+static void gen_addiur1sp (CPUMIPSState *env, DisasContext *ctx)
{
int rd = mmreg(uMIPS_RD(ctx->opcode));
gen_arith_imm(env, ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2);
}
-static void gen_addiur2 (CPUState *env, DisasContext *ctx)
+static void gen_addiur2 (CPUMIPSState *env, DisasContext *ctx)
{
static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
int rd = mmreg(uMIPS_RD(ctx->opcode));
@@ -9793,7 +9793,7 @@ static void gen_addiur2 (CPUState *env, DisasContext *ctx)
gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]);
}
-static void gen_addiusp (CPUState *env, DisasContext *ctx)
+static void gen_addiusp (CPUMIPSState *env, DisasContext *ctx)
{
int encoded = ZIMM(ctx->opcode, 1, 9);
int decoded;
@@ -9811,7 +9811,7 @@ static void gen_addiusp (CPUState *env, DisasContext *ctx)
gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, decoded << 2);
}
-static void gen_addius5 (CPUState *env, DisasContext *ctx)
+static void gen_addius5 (CPUMIPSState *env, DisasContext *ctx)
{
int imm = SIMM(ctx->opcode, 1, 4);
int rd = (ctx->opcode >> 5) & 0x1f;
@@ -9819,7 +9819,7 @@ static void gen_addius5 (CPUState *env, DisasContext *ctx)
gen_arith_imm(env, ctx, OPC_ADDIU, rd, rd, imm);
}
-static void gen_andi16 (CPUState *env, DisasContext *ctx)
+static void gen_andi16 (CPUMIPSState *env, DisasContext *ctx)
{
static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
31, 32, 63, 64, 255, 32768, 65535 };
@@ -9872,7 +9872,7 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
}
-static void gen_pool16c_insn (CPUState *env, DisasContext *ctx, int *is_branch)
+static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
{
int rd = mmreg((ctx->opcode >> 3) & 0x7);
int rs = mmreg(ctx->opcode & 0x7);
@@ -10087,7 +10087,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(t1);
}
-static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs,
+static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs,
int *is_branch)
{
int extension = (ctx->opcode >> 6) & 0x3f;
@@ -10361,7 +10361,7 @@ enum {
FMT_DWL_L = 2
};
-static void gen_pool32fxf (CPUState *env, DisasContext *ctx, int rt, int rs)
+static void gen_pool32fxf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
{
int extension = (ctx->opcode >> 6) & 0x3ff;
uint32_t mips32_op;
@@ -10607,7 +10607,7 @@ static void gen_pool32fxf (CPUState *env, DisasContext *ctx, int rt, int rs)
}
}
-static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,
+static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
uint16_t insn_hw1, int *is_branch)
{
int32_t offset;
@@ -11365,7 +11365,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,
}
}
-static int decode_micromips_opc (CPUState *env, DisasContext *ctx, int *is_branch)
+static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
{
uint32_t op;
@@ -11682,7 +11682,7 @@ static int decode_micromips_opc (CPUState *env, DisasContext *ctx, int *is_branc
#endif
-static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
+static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
{
int32_t offset;
int rs, rt, rd, sa;
@@ -12369,7 +12369,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
}
static inline void
-gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
+gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb,
int search_pc)
{
DisasContext ctx;
@@ -12522,17 +12522,17 @@ done_generating:
#endif
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUMIPSState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUMIPSState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-static void fpu_dump_state(CPUState *env, FILE *f, fprintf_function fpu_fprintf,
+static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
int flags)
{
int i;
@@ -12579,7 +12579,7 @@ static void fpu_dump_state(CPUState *env, FILE *f, fprintf_function fpu_fprintf,
#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
static void
-cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
+cpu_mips_check_sign_extensions (CPUMIPSState *env, FILE *f,
fprintf_function cpu_fprintf,
int flags)
{
@@ -12606,7 +12606,7 @@ cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
}
#endif
-void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state (CPUMIPSState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -12648,36 +12648,36 @@ static void mips_tcg_init(void)
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.gpr[i]),
+ offsetof(CPUMIPSState, active_tc.gpr[i]),
regnames[i]);
cpu_PC = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.PC), "PC");
+ offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.HI[i]),
+ offsetof(CPUMIPSState, active_tc.HI[i]),
regnames_HI[i]);
cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.LO[i]),
+ offsetof(CPUMIPSState, active_tc.LO[i]),
regnames_LO[i]);
cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.ACX[i]),
+ offsetof(CPUMIPSState, active_tc.ACX[i]),
regnames_ACX[i]);
}
cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.DSPControl),
+ offsetof(CPUMIPSState, active_tc.DSPControl),
"DSPControl");
bcond = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, bcond), "bcond");
+ offsetof(CPUMIPSState, bcond), "bcond");
btarget = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btarget), "btarget");
+ offsetof(CPUMIPSState, btarget), "btarget");
hflags = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, hflags), "hflags");
+ offsetof(CPUMIPSState, hflags), "hflags");
fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, active_fpu.fcr0),
+ offsetof(CPUMIPSState, active_fpu.fcr0),
"fcr0");
fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, active_fpu.fcr31),
+ offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
/* register helpers */
@@ -12841,7 +12841,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->exception_index = EXCP_NONE;
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)
{
env->active_tc.PC = gen_opc_pc[pc_pos];
env->hflags &= ~MIPS_HFLAG_BMASK;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (19 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 20/44] target-mips: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: " Andreas Färber
` (22 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc]
sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-ppc/cpu.h | 38 ++++++++++----------
target-ppc/helper.c | 80 +++++++++++++++++++++---------------------
target-ppc/kvm.c | 38 ++++++++++----------
target-ppc/kvm_ppc.h | 12 +++---
target-ppc/machine.c | 4 +-
target-ppc/op_helper.c | 12 +++---
target-ppc/translate.c | 78 +++++++++++++++++++++---------------------
target-ppc/translate_init.c | 42 +++++++++++-----------
8 files changed, 152 insertions(+), 152 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ac753f3..3508d8a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1173,12 +1173,12 @@ void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
void store_40x_sler (CPUPPCState *env, uint32_t val);
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
-void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
-target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb);
-int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
+void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot);
+target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
+int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
target_phys_addr_t *raddrp, target_ulong address,
uint32_t pid, int ext, int i);
-int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
+int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
target_phys_addr_t *raddrp, target_ulong address,
uint32_t pid);
void ppc_tlb_invalidate_all (CPUPPCState *env);
@@ -1226,13 +1226,13 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _hypv
#define MMU_USER_IDX 0
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUPPCState *env)
{
return env->mmu_idx;
}
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
{
if (newsp)
env->gpr[1] = newsp;
@@ -2056,7 +2056,7 @@ enum {
/*****************************************************************************/
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->nip;
@@ -2064,7 +2064,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*flags = env->hflags;
}
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
{
#if defined(TARGET_PPC64)
/* The kernel checks TIF_32BIT here; we don't support loading 32-bit
@@ -2076,7 +2076,7 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
}
#if !defined(CONFIG_USER_ONLY)
-static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm)
+static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
{
uintptr_t tlbml = (uintptr_t)tlbm;
uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
@@ -2084,21 +2084,21 @@ static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm)
return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
}
-static inline int booke206_tlb_size(CPUState *env, int tlbn)
+static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
{
uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
int r = tlbncfg & TLBnCFG_N_ENTRY;
return r;
}
-static inline int booke206_tlb_ways(CPUState *env, int tlbn)
+static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
{
uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
return r;
}
-static inline int booke206_tlbm_to_tlbn(CPUState *env, ppcmas_tlb_t *tlbm)
+static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
{
int id = booke206_tlbm_id(env, tlbm);
int end = 0;
@@ -2115,14 +2115,14 @@ static inline int booke206_tlbm_to_tlbn(CPUState *env, ppcmas_tlb_t *tlbm)
return 0;
}
-static inline int booke206_tlbm_to_way(CPUState *env, ppcmas_tlb_t *tlb)
+static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
{
int tlbn = booke206_tlbm_to_tlbn(env, tlb);
int tlbid = booke206_tlbm_id(env, tlb);
return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
}
-static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
+static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
target_ulong ea, int way)
{
int r;
@@ -2149,7 +2149,7 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
}
/* returns bitmap of supported page sizes for a given TLB */
-static inline uint32_t booke206_tlbnps(CPUState *env, const int tlbn)
+static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
{
bool mav2 = false;
uint32_t ret = 0;
@@ -2171,20 +2171,20 @@ static inline uint32_t booke206_tlbnps(CPUState *env, const int tlbn)
#endif
-extern void (*cpu_ppc_hypercall)(CPUState *);
+extern void (*cpu_ppc_hypercall)(CPUPPCState *);
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUPPCState *env)
{
return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
{
env->nip = tb->pc;
}
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
#endif /* !defined (__CPU_PPC_H__) */
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index f4552e8..bd711b6 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -67,13 +67,13 @@
/*****************************************************************************/
/* PowerPC Hypercall emulation */
-void (*cpu_ppc_hypercall)(CPUState *);
+void (*cpu_ppc_hypercall)(CPUPPCState *);
/*****************************************************************************/
/* PowerPC MMU emulation */
#if defined(CONFIG_USER_ONLY)
-int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
int mmu_idx)
{
int exception, error_code;
@@ -291,7 +291,7 @@ static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
}
/* Software driven TLB helpers */
-static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
+static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, int way,
int is_code)
{
int nr;
@@ -307,7 +307,7 @@ static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
return nr;
}
-static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
+static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
{
ppc6xx_tlb_t *tlb;
int nr, max;
@@ -324,7 +324,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
tlb_flush(env, 1);
}
-static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
+static inline void __ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
target_ulong eaddr,
int is_code, int match_epn)
{
@@ -349,13 +349,13 @@ static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
#endif
}
-static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
+static inline void ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
target_ulong eaddr, int is_code)
{
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
}
-void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
+void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
target_ulong pte0, target_ulong pte1)
{
ppc6xx_tlb_t *tlb;
@@ -374,7 +374,7 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
env->last_way = way;
}
-static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
+static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int access_type)
{
ppc6xx_tlb_t *tlb;
@@ -436,7 +436,7 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
}
/* Perform BAT hit & translation */
-static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
+static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp, int *validp,
int *protp, target_ulong *BATu,
target_ulong *BATl)
{
@@ -461,7 +461,7 @@ static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
*protp = prot;
}
-static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
+static inline void bat_601_size_prot(CPUPPCState *env, target_ulong *blp,
int *validp, int *protp,
target_ulong *BATu, target_ulong *BATl)
{
@@ -486,7 +486,7 @@ static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
*protp = prot;
}
-static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
+static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong virtual,
int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
@@ -561,7 +561,7 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
return ret;
}
-static inline target_phys_addr_t get_pteg_offset(CPUState *env,
+static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
target_phys_addr_t hash,
int pte_size)
{
@@ -569,7 +569,7 @@ static inline target_phys_addr_t get_pteg_offset(CPUState *env,
}
/* PTE table lookup */
-static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
+static inline int _find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
int rw, int type, int target_page_bits)
{
target_phys_addr_t pteg_off;
@@ -675,7 +675,7 @@ static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
return ret;
}
-static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
+static inline int find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int h, int rw,
int type, int target_page_bits)
{
#if defined(TARGET_PPC64)
@@ -812,7 +812,7 @@ int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt)
#endif /* defined(TARGET_PPC64) */
/* Perform segment based translation */
-static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
+static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
{
target_phys_addr_t hash;
@@ -1002,7 +1002,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
}
/* Generic TLB check function for embedded PowerPC implementations */
-int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
+int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
target_phys_addr_t *raddrp,
target_ulong address, uint32_t pid, int ext,
int i)
@@ -1055,7 +1055,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
}
/* Helpers specific to PowerPC 40x implementations */
-static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
+static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
{
ppcemb_tlb_t *tlb;
int i;
@@ -1067,7 +1067,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
tlb_flush(env, 1);
}
-static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
+static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
target_ulong eaddr, uint32_t pid)
{
#if !defined(FLUSH_ALL_TLBS)
@@ -1091,7 +1091,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
#endif
}
-static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
+static int mmu40x_get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong address, int rw, int access_type)
{
ppcemb_tlb_t *tlb;
@@ -1162,7 +1162,7 @@ void store_40x_sler (CPUPPCState *env, uint32_t val)
env->spr[SPR_405_SLER] = val;
}
-static inline int mmubooke_check_tlb (CPUState *env, ppcemb_tlb_t *tlb,
+static inline int mmubooke_check_tlb (CPUPPCState *env, ppcemb_tlb_t *tlb,
target_phys_addr_t *raddr, int *prot,
target_ulong address, int rw,
int access_type, int i)
@@ -1232,7 +1232,7 @@ found_tlb:
return ret;
}
-static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
+static int mmubooke_get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong address, int rw,
int access_type)
{
@@ -1264,7 +1264,7 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
return ret;
}
-void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot)
+void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot)
{
int tlb_size;
int i, j;
@@ -1285,7 +1285,7 @@ void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot)
tlb_flush(env, 1);
}
-target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
+target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb)
{
int tlbm_size;
@@ -1295,7 +1295,7 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
}
/* TLB check function for MAS based SoftTLBs */
-int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
+int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
target_phys_addr_t *raddrp,
target_ulong address, uint32_t pid)
{
@@ -1331,7 +1331,7 @@ int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
return 0;
}
-static int mmubooke206_check_tlb(CPUState *env, ppcmas_tlb_t *tlb,
+static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
target_phys_addr_t *raddr, int *prot,
target_ulong address, int rw,
int access_type)
@@ -1417,7 +1417,7 @@ found_tlb:
return ret;
}
-static int mmubooke206_get_physical_address(CPUState *env, mmu_ctx_t *ctx,
+static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong address, int rw,
int access_type)
{
@@ -1467,7 +1467,7 @@ static const char *book3e_tsize_to_str[32] = {
};
static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
- CPUState *env, int tlbn, int offset,
+ CPUPPCState *env, int tlbn, int offset,
int tlbsize)
{
ppcmas_tlb_t *entry;
@@ -1514,7 +1514,7 @@ static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
}
static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
- CPUState *env)
+ CPUPPCState *env)
{
int offset = 0;
int i;
@@ -1538,7 +1538,7 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
#if defined(TARGET_PPC64)
static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
- CPUState *env)
+ CPUPPCState *env)
{
int i;
uint64_t slbe, slbv;
@@ -1558,7 +1558,7 @@ static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
}
#endif
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
{
switch (env->mmu_model) {
case POWERPC_MMU_BOOKE206:
@@ -1575,7 +1575,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
}
}
-static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
+static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw)
{
int in_plb, ret;
@@ -1641,7 +1641,7 @@ static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
return ret;
}
-int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
+int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
int rw, int access_type)
{
int ret;
@@ -1716,7 +1716,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug (CPUPPCState *env, target_ulong addr)
{
mmu_ctx_t ctx;
@@ -1726,7 +1726,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
return ctx.raddr & TARGET_PAGE_MASK;
}
-static void booke206_update_mas_tlb_miss(CPUState *env, target_ulong address,
+static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
int rw)
{
env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
@@ -1767,7 +1767,7 @@ static void booke206_update_mas_tlb_miss(CPUState *env, target_ulong address,
}
/* Perform address translation */
-int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
int mmu_idx)
{
mmu_ctx_t ctx;
@@ -2434,19 +2434,19 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value)
/*****************************************************************************/
/* Exception processing */
#if defined (CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUPPCState *env)
{
env->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
-void ppc_hw_interrupt (CPUState *env)
+void ppc_hw_interrupt (CPUPPCState *env)
{
env->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
#else /* defined (CONFIG_USER_ONLY) */
-static inline void dump_syscall(CPUState *env)
+static inline void dump_syscall(CPUPPCState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
" r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
@@ -2459,7 +2459,7 @@ static inline void dump_syscall(CPUState *env)
/* Note that this function should be greatly optimized
* when called with a constant excp, from ppc_hw_interrupt
*/
-static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
+static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
@@ -3008,7 +3008,7 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
}
}
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUPPCState *env)
{
powerpc_excp(env, env->excp_model, env->exception_index);
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 50cfa02..aeb3de9 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -93,7 +93,7 @@ int kvm_arch_init(KVMState *s)
return 0;
}
-static int kvm_arch_sync_sregs(CPUState *cenv)
+static int kvm_arch_sync_sregs(CPUPPCState *cenv)
{
struct kvm_sregs sregs;
int ret;
@@ -121,7 +121,7 @@ static int kvm_arch_sync_sregs(CPUState *cenv)
}
/* Set up a shared TLB array with KVM */
-static int kvm_booke206_tlb_init(CPUState *env)
+static int kvm_booke206_tlb_init(CPUPPCState *env)
{
struct kvm_book3e_206_tlb_params params = {};
struct kvm_config_tlb cfg = {};
@@ -166,7 +166,7 @@ static int kvm_booke206_tlb_init(CPUState *env)
return 0;
}
-int kvm_arch_init_vcpu(CPUState *cenv)
+int kvm_arch_init_vcpu(CPUPPCState *cenv)
{
int ret;
@@ -189,11 +189,11 @@ int kvm_arch_init_vcpu(CPUState *cenv)
return ret;
}
-void kvm_arch_reset_vcpu(CPUState *env)
+void kvm_arch_reset_vcpu(CPUPPCState *env)
{
}
-static void kvm_sw_tlb_put(CPUState *env)
+static void kvm_sw_tlb_put(CPUPPCState *env)
{
struct kvm_dirty_tlb dirty_tlb;
unsigned char *bitmap;
@@ -218,7 +218,7 @@ static void kvm_sw_tlb_put(CPUState *env)
g_free(bitmap);
}
-int kvm_arch_put_registers(CPUState *env, int level)
+int kvm_arch_put_registers(CPUPPCState *env, int level)
{
struct kvm_regs regs;
int ret;
@@ -263,7 +263,7 @@ int kvm_arch_put_registers(CPUState *env, int level)
return ret;
}
-int kvm_arch_get_registers(CPUState *env)
+int kvm_arch_get_registers(CPUPPCState *env)
{
struct kvm_regs regs;
struct kvm_sregs sregs;
@@ -440,7 +440,7 @@ int kvm_arch_get_registers(CPUState *env)
return 0;
}
-int kvmppc_set_interrupt(CPUState *env, int irq, int level)
+int kvmppc_set_interrupt(CPUPPCState *env, int irq, int level)
{
unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
@@ -465,7 +465,7 @@ int kvmppc_set_interrupt(CPUState *env, int irq, int level)
#define PPC_INPUT_INT PPC6xx_INPUT_INT
#endif
-void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
+void kvm_arch_pre_run(CPUPPCState *env, struct kvm_run *run)
{
int r;
unsigned irq;
@@ -498,16 +498,16 @@ void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
* anyways, so we will get a chance to deliver the rest. */
}
-void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
+void kvm_arch_post_run(CPUPPCState *env, struct kvm_run *run)
{
}
-int kvm_arch_process_async_events(CPUState *env)
+int kvm_arch_process_async_events(CPUPPCState *env)
{
return env->halted;
}
-static int kvmppc_handle_halt(CPUState *env)
+static int kvmppc_handle_halt(CPUPPCState *env)
{
if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
env->halted = 1;
@@ -518,7 +518,7 @@ static int kvmppc_handle_halt(CPUState *env)
}
/* map dcr access to existing qemu dcr emulation */
-static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data)
+static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data)
{
if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
@@ -526,7 +526,7 @@ static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data)
return 0;
}
-static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data)
+static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data)
{
if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
@@ -534,7 +534,7 @@ static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data)
return 0;
}
-int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
+int kvm_arch_handle_exit(CPUPPCState *env, struct kvm_run *run)
{
int ret;
@@ -704,7 +704,7 @@ uint32_t kvmppc_get_dfp(void)
return kvmppc_read_int_cpu_dt("ibm,dfp");
}
-int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
+int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
{
uint32_t *hc = (uint32_t*)buf;
@@ -734,7 +734,7 @@ int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
return 0;
}
-void kvmppc_set_papr(CPUState *env)
+void kvmppc_set_papr(CPUPPCState *env)
{
struct kvm_enable_cap cap = {};
struct kvm_one_reg reg = {};
@@ -930,12 +930,12 @@ const ppc_def_t *kvmppc_host_cpu_def(void)
return spec;
}
-bool kvm_arch_stop_on_emulation_error(CPUState *env)
+bool kvm_arch_stop_on_emulation_error(CPUPPCState *env)
{
return true;
}
-int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+int kvm_arch_on_sigbus_vcpu(CPUPPCState *env, int code, void *addr)
{
return 1;
}
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index f9c0198..8f1267c 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -19,9 +19,9 @@ uint32_t kvmppc_get_tbfreq(void);
uint64_t kvmppc_get_clockfreq(void);
uint32_t kvmppc_get_vmx(void);
uint32_t kvmppc_get_dfp(void);
-int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len);
-int kvmppc_set_interrupt(CPUState *env, int irq, int level);
-void kvmppc_set_papr(CPUState *env);
+int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len);
+int kvmppc_set_interrupt(CPUPPCState *env, int irq, int level);
+void kvmppc_set_papr(CPUPPCState *env);
int kvmppc_smt_threads(void);
#ifndef CONFIG_USER_ONLY
off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem);
@@ -52,17 +52,17 @@ static inline uint32_t kvmppc_get_dfp(void)
return 0;
}
-static inline int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
+static inline int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
{
return -1;
}
-static inline int kvmppc_set_interrupt(CPUState *env, int irq, int level)
+static inline int kvmppc_set_interrupt(CPUPPCState *env, int irq, int level)
{
return -1;
}
-static inline void kvmppc_set_papr(CPUState *env)
+static inline void kvmppc_set_papr(CPUPPCState *env)
{
}
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 1c40d43..70e2582 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -4,7 +4,7 @@
void cpu_save(QEMUFile *f, void *opaque)
{
- CPUState *env = (CPUState *)opaque;
+ CPUPPCState *env = (CPUPPCState *)opaque;
unsigned int i, j;
for (i = 0; i < 32; i++)
@@ -91,7 +91,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
- CPUState *env = (CPUState *)opaque;
+ CPUPPCState *env = (CPUPPCState *)opaque;
unsigned int i, j;
target_ulong sdr1;
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 3f4e067..40927b6 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -3714,11 +3714,11 @@ uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUPPCState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUPPCState *saved_env;
unsigned long pc;
int ret;
@@ -4200,7 +4200,7 @@ target_ulong helper_440_tlbsx (target_ulong address)
/* PowerPC BookE 2.06 TLB management */
-static ppcmas_tlb_t *booke206_cur_tlb(CPUState *env)
+static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
{
uint32_t tlbncfg = 0;
int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT;
@@ -4306,7 +4306,7 @@ void helper_booke206_tlbwe(void)
}
}
-static inline void booke206_tlb_to_mas(CPUState *env, ppcmas_tlb_t *tlb)
+static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb)
{
int tlbn = booke206_tlbm_to_tlbn(env, tlb);
int way = booke206_tlbm_to_way(env, tlb);
@@ -4387,7 +4387,7 @@ void helper_booke206_tlbsx(target_ulong address)
env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
}
-static inline void booke206_invalidate_ea_tlb(CPUState *env, int tlbn,
+static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn,
uint32_t ea)
{
int i;
@@ -4553,7 +4553,7 @@ void helper_msgsnd(target_ulong rb)
{
int irq = dbell2irq(rb);
int pir = rb & DBELL_PIRTAG_MASK;
- CPUState *cenv;
+ CPUPPCState *cenv;
if (irq < 0) {
return;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8573e1f..3ec59a7 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -91,7 +91,7 @@ void ppc_translate_init(void)
for (i = 0; i < 8; i++) {
snprintf(p, cpu_reg_names_size, "crf%d", i);
cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, crf[i]), p);
+ offsetof(CPUPPCState, crf[i]), p);
p += 5;
cpu_reg_names_size -= 5;
}
@@ -99,30 +99,30 @@ void ppc_translate_init(void)
for (i = 0; i < 32; i++) {
snprintf(p, cpu_reg_names_size, "r%d", i);
cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, gpr[i]), p);
+ offsetof(CPUPPCState, gpr[i]), p);
p += (i < 10) ? 3 : 4;
cpu_reg_names_size -= (i < 10) ? 3 : 4;
#if !defined(TARGET_PPC64)
snprintf(p, cpu_reg_names_size, "r%dH", i);
cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, gprh[i]), p);
+ offsetof(CPUPPCState, gprh[i]), p);
p += (i < 10) ? 4 : 5;
cpu_reg_names_size -= (i < 10) ? 4 : 5;
#endif
snprintf(p, cpu_reg_names_size, "fp%d", i);
cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, fpr[i]), p);
+ offsetof(CPUPPCState, fpr[i]), p);
p += (i < 10) ? 4 : 5;
cpu_reg_names_size -= (i < 10) ? 4 : 5;
snprintf(p, cpu_reg_names_size, "avr%dH", i);
#ifdef HOST_WORDS_BIGENDIAN
cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, avr[i].u64[0]), p);
+ offsetof(CPUPPCState, avr[i].u64[0]), p);
#else
cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, avr[i].u64[1]), p);
+ offsetof(CPUPPCState, avr[i].u64[1]), p);
#endif
p += (i < 10) ? 6 : 7;
cpu_reg_names_size -= (i < 10) ? 6 : 7;
@@ -130,44 +130,44 @@ void ppc_translate_init(void)
snprintf(p, cpu_reg_names_size, "avr%dL", i);
#ifdef HOST_WORDS_BIGENDIAN
cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, avr[i].u64[1]), p);
+ offsetof(CPUPPCState, avr[i].u64[1]), p);
#else
cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, avr[i].u64[0]), p);
+ offsetof(CPUPPCState, avr[i].u64[0]), p);
#endif
p += (i < 10) ? 6 : 7;
cpu_reg_names_size -= (i < 10) ? 6 : 7;
}
cpu_nip = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, nip), "nip");
+ offsetof(CPUPPCState, nip), "nip");
cpu_msr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, msr), "msr");
+ offsetof(CPUPPCState, msr), "msr");
cpu_ctr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, ctr), "ctr");
+ offsetof(CPUPPCState, ctr), "ctr");
cpu_lr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, lr), "lr");
+ offsetof(CPUPPCState, lr), "lr");
#if defined(TARGET_PPC64)
cpu_cfar = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cfar), "cfar");
+ offsetof(CPUPPCState, cfar), "cfar");
#endif
cpu_xer = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, xer), "xer");
+ offsetof(CPUPPCState, xer), "xer");
cpu_reserve = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, reserve_addr),
+ offsetof(CPUPPCState, reserve_addr),
"reserve_addr");
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, fpscr), "fpscr");
+ offsetof(CPUPPCState, fpscr), "fpscr");
cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, access_type), "access_type");
+ offsetof(CPUPPCState, access_type), "access_type");
/* register helpers */
#define GEN_HELPER 2
@@ -564,12 +564,12 @@ static inline target_ulong MASK(uint32_t start, uint32_t end)
/* SPR load/store helpers */
static inline void gen_load_spr(TCGv t, int reg)
{
- tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
+ tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
}
static inline void gen_store_spr(int reg, TCGv t)
{
- tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
+ tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
}
/* Invalid instruction */
@@ -3078,7 +3078,7 @@ static void gen_lwarx(DisasContext *ctx)
gen_check_align(ctx, t0, 0x03);
gen_qemu_ld32u(ctx, gpr, t0);
tcg_gen_mov_tl(cpu_reserve, t0);
- tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
+ tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
tcg_temp_free(t0);
}
@@ -3089,9 +3089,9 @@ static void gen_conditional_store (DisasContext *ctx, TCGv EA,
TCGv t0 = tcg_temp_new();
uint32_t save_exception = ctx->exception;
- tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
+ tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
tcg_gen_movi_tl(t0, (size << 5) | reg);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
tcg_temp_free(t0);
gen_update_nip(ctx, ctx->nip-4);
ctx->exception = POWERPC_EXCP_BRANCH;
@@ -3140,7 +3140,7 @@ static void gen_ldarx(DisasContext *ctx)
gen_check_align(ctx, t0, 0x07);
gen_qemu_ld64(ctx, gpr, t0);
tcg_gen_mov_tl(cpu_reserve, t0);
- tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
+ tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
tcg_temp_free(t0);
}
@@ -3181,7 +3181,7 @@ static void gen_sync(DisasContext *ctx)
static void gen_wait(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
tcg_temp_free_i32(t0);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_err(ctx, EXCP_HLT, 1);
@@ -6395,7 +6395,7 @@ static void gen_mfvscr(DisasContext *ctx)
}
tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
t = tcg_temp_new_i32();
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
tcg_temp_free_i32(t);
}
@@ -6748,7 +6748,7 @@ static inline void gen_evmra(DisasContext *ctx)
/* spe_acc := rA */
tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
cpu_env,
- offsetof(CPUState, spe_acc));
+ offsetof(CPUPPCState, spe_acc));
#else
TCGv_i64 tmp = tcg_temp_new_i64();
@@ -6756,7 +6756,7 @@ static inline void gen_evmra(DisasContext *ctx)
tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
/* spe_acc := tmp */
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
tcg_temp_free_i64(tmp);
/* rD := rA */
@@ -7399,7 +7399,7 @@ static inline void gen_evmwumia(DisasContext *ctx)
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
tcg_temp_free_i64(tmp);
}
@@ -7422,13 +7422,13 @@ static inline void gen_evmwumiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);
@@ -7476,7 +7476,7 @@ static inline void gen_evmwsmia(DisasContext *ctx)
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
tcg_temp_free_i64(tmp);
}
@@ -7495,13 +7495,13 @@ static inline void gen_evmwsmiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
+ tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);
@@ -9277,7 +9277,7 @@ GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
/*****************************************************************************/
/* Misc PowerPC helpers */
-void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
#define RGPL 4
@@ -9425,7 +9425,7 @@ void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
#undef RFPL
}
-void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
+void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
int flags)
{
#if defined(DO_PPC_STATISTICS)
@@ -9473,7 +9473,7 @@ void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
}
/*****************************************************************************/
-static inline void gen_intermediate_code_internal(CPUState *env,
+static inline void gen_intermediate_code_internal(CPUPPCState *env,
TranslationBlock *tb,
int search_pc)
{
@@ -9658,17 +9658,17 @@ static inline void gen_intermediate_code_internal(CPUState *env,
#endif
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
{
env->nip = gen_opc_pc[pc_pos];
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6253076..1ec6f42 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -268,12 +268,12 @@ static void spr_read_purr (void *opaque, int gprn, int sprn)
/* IBAT0L...IBAT7L */
static void spr_read_ibat (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
}
static void spr_write_ibatu (void *opaque, int sprn, int gprn)
@@ -308,12 +308,12 @@ static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
/* DBAT0L...DBAT7L */
static void spr_read_dbat (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
}
static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
}
static void spr_write_dbatu (void *opaque, int sprn, int gprn)
@@ -355,20 +355,20 @@ static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
#if defined(TARGET_PPC64)
static void spr_read_hior (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
}
static void spr_write_hior (void *opaque, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
tcg_temp_free(t0);
}
static void spr_read_asr (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
}
static void spr_write_asr (void *opaque, int sprn, int gprn)
@@ -415,7 +415,7 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
@@ -475,7 +475,7 @@ static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
}
static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
@@ -498,7 +498,7 @@ static void spr_write_pir (void *opaque, int sprn, int gprn)
static void spr_read_spefscr (void *opaque, int gprn, int sprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
+ tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
tcg_temp_free_i32(t0);
}
@@ -507,7 +507,7 @@ static void spr_write_spefscr (void *opaque, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
tcg_temp_free_i32(t0);
}
@@ -516,9 +516,9 @@ static void spr_write_spefscr (void *opaque, int sprn, int gprn)
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
gen_store_spr(sprn, t0);
tcg_temp_free(t0);
}
@@ -542,9 +542,9 @@ static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
}
TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn_offs]));
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
gen_store_spr(sprn, t0);
tcg_temp_free(t0);
}
@@ -9768,7 +9768,7 @@ static void dump_ppc_insns (CPUPPCState *env)
}
#endif
-static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
stfq_p(mem_buf, env->fpr[n]);
@@ -9781,7 +9781,7 @@ static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
env->fpr[n] = ldfq_p(mem_buf);
@@ -9794,7 +9794,7 @@ static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
#ifdef HOST_WORDS_BIGENDIAN
@@ -9817,7 +9817,7 @@ static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
#ifdef HOST_WORDS_BIGENDIAN
@@ -9840,7 +9840,7 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
#if defined(TARGET_PPC64)
@@ -9861,7 +9861,7 @@ static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
+static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
#if defined(TARGET_PPC64)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (20 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: " Andreas Färber
` (21 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUS390XState/g" target-s390x/*.[hc]
sed -i "s/#define CPUS390XState/#define CPUState/" target-s390x/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-s390x/cpu.h | 46 +++++++++++++++---------------
target-s390x/helper.c | 38 ++++++++++++------------
target-s390x/kvm.c | 56 ++++++++++++++++++------------------
target-s390x/op_helper.c | 70 +++++++++++++++++++++++-----------------------
target-s390x/translate.c | 56 ++++++++++++++++++------------------
5 files changed, 133 insertions(+), 133 deletions(-)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index e892bec..af6cc4e 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -106,7 +106,7 @@ typedef struct CPUS390XState {
} CPUS390XState;
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
{
if (newsp) {
env->regs[15] = newsp;
@@ -233,7 +233,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
#define FLAG_MASK_32 0x00001000
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUS390XState *env)
{
if (env->psw.mask & PSW_MASK_PSTATE) {
return 1;
@@ -242,7 +242,7 @@ static inline int cpu_mmu_index (CPUState *env)
return 0;
}
-static inline void cpu_get_tb_cpu_state(CPUState* env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->psw.addr;
@@ -275,7 +275,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model);
void s390x_translate_init(void);
int cpu_s390x_exec(CPUS390XState *s);
void cpu_s390x_close(CPUS390XState *s);
-void do_interrupt (CPUState *env);
+void do_interrupt (CPUS390XState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
@@ -288,42 +288,42 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw
#ifndef CONFIG_USER_ONLY
-int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall);
+int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall);
#ifdef CONFIG_KVM
-void kvm_s390_interrupt(CPUState *env, int type, uint32_t code);
-void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token);
-void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm,
+void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code);
+void kvm_s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token);
+void kvm_s390_interrupt_internal(CPUS390XState *env, int type, uint32_t parm,
uint64_t parm64, int vm);
#else
-static inline void kvm_s390_interrupt(CPUState *env, int type, uint32_t code)
+static inline void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code)
{
}
-static inline void kvm_s390_virtio_irq(CPUState *env, int config_change,
+static inline void kvm_s390_virtio_irq(CPUS390XState *env, int config_change,
uint64_t token)
{
}
-static inline void kvm_s390_interrupt_internal(CPUState *env, int type,
+static inline void kvm_s390_interrupt_internal(CPUS390XState *env, int type,
uint32_t parm, uint64_t parm64,
int vm)
{
}
#endif
-CPUState *s390_cpu_addr2state(uint16_t cpu_addr);
-void s390_add_running_cpu(CPUState *env);
-unsigned s390_del_running_cpu(CPUState *env);
+CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr);
+void s390_add_running_cpu(CPUS390XState *env);
+unsigned s390_del_running_cpu(CPUS390XState *env);
/* from s390-virtio-bus */
extern const target_phys_addr_t virtio_size;
#else
-static inline void s390_add_running_cpu(CPUState *env)
+static inline void s390_add_running_cpu(CPUS390XState *env)
{
}
-static inline unsigned s390_del_running_cpu(CPUState *env)
+static inline unsigned s390_del_running_cpu(CPUS390XState *env)
{
return 0;
}
@@ -944,11 +944,11 @@ static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
#define SIGP_STAT_INVALID_ORDER 0x00000002UL
#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
-void load_psw(CPUState *env, uint64_t mask, uint64_t addr);
-int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc,
+void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
+int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags);
-int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code);
-uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
+int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code);
+uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
uint64_t vr);
#define TARGET_HAS_ICE 1
@@ -961,7 +961,7 @@ static inline uint64_t time2tod(uint64_t ns) {
return (ns << 9) / 125;
}
-static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
+static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
uint64_t param64)
{
if (env->ext_index == MAX_EXT_QUEUE - 1) {
@@ -980,13 +980,13 @@ static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUS390XState *env)
{
return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->psw.mask & PSW_MASK_EXT);
}
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
+static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
{
env->psw.addr = tb->pc;
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 1a1cc0eb..44d5048 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -53,7 +53,7 @@
#ifndef CONFIG_USER_ONLY
static void s390x_tod_timer(void *opaque)
{
- CPUState *env = opaque;
+ CPUS390XState *env = opaque;
env->pending_int |= INTERRUPT_TOD;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@@ -61,7 +61,7 @@ static void s390x_tod_timer(void *opaque)
static void s390x_cpu_timer(void *opaque)
{
- CPUState *env = opaque;
+ CPUS390XState *env = opaque;
env->pending_int |= INTERRUPT_CPUTIMER;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@@ -102,12 +102,12 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUS390XState *env)
{
env->exception_index = -1;
}
-int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
int mmu_idx)
{
/* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
@@ -135,14 +135,14 @@ void cpu_state_reset(CPUS390XState *env)
#ifndef CONFIG_USER_ONLY
/* Ensure to exit the TB after this call! */
-static void trigger_pgm_exception(CPUState *env, uint32_t code, uint32_t ilc)
+static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc)
{
env->exception_index = EXCP_PGM;
env->int_pgm_code = code;
env->int_pgm_ilc = ilc;
}
-static int trans_bits(CPUState *env, uint64_t mode)
+static int trans_bits(CPUS390XState *env, uint64_t mode)
{
int bits = 0;
@@ -164,7 +164,7 @@ static int trans_bits(CPUState *env, uint64_t mode)
return bits;
}
-static void trigger_prot_fault(CPUState *env, target_ulong vaddr, uint64_t mode)
+static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, uint64_t mode)
{
int ilc = ILC_LATER_INC_2;
int bits = trans_bits(env, mode) | 4;
@@ -175,7 +175,7 @@ static void trigger_prot_fault(CPUState *env, target_ulong vaddr, uint64_t mode)
trigger_pgm_exception(env, PGM_PROTECTION, ilc);
}
-static void trigger_page_fault(CPUState *env, target_ulong vaddr, uint32_t type,
+static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, uint32_t type,
uint64_t asc, int rw)
{
int ilc = ILC_LATER;
@@ -192,7 +192,7 @@ static void trigger_page_fault(CPUState *env, target_ulong vaddr, uint32_t type,
trigger_pgm_exception(env, type, ilc);
}
-static int mmu_translate_asce(CPUState *env, target_ulong vaddr, uint64_t asc,
+static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
uint64_t asce, int level, target_ulong *raddr,
int *flags, int rw)
{
@@ -274,7 +274,7 @@ static int mmu_translate_asce(CPUState *env, target_ulong vaddr, uint64_t asc,
return 0;
}
-static int mmu_translate_asc(CPUState *env, target_ulong vaddr, uint64_t asc,
+static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr, uint64_t asc,
target_ulong *raddr, int *flags, int rw)
{
uint64_t asce = 0;
@@ -343,7 +343,7 @@ static int mmu_translate_asc(CPUState *env, target_ulong vaddr, uint64_t asc,
return r;
}
-int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc,
+int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags)
{
int r = -1;
@@ -404,7 +404,7 @@ out:
return r;
}
-int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw,
+int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong _vaddr, int rw,
int mmu_idx)
{
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
@@ -444,7 +444,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUS390XState *env, target_ulong vaddr)
{
target_ulong raddr;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -462,7 +462,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr)
return raddr;
}
-void load_psw(CPUState *env, uint64_t mask, uint64_t addr)
+void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
if (mask & PSW_MASK_WAIT) {
if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
@@ -481,7 +481,7 @@ void load_psw(CPUState *env, uint64_t mask, uint64_t addr)
env->cc_op = (mask >> 13) & 3;
}
-static uint64_t get_psw_mask(CPUState *env)
+static uint64_t get_psw_mask(CPUS390XState *env)
{
uint64_t r = env->psw.mask;
@@ -494,7 +494,7 @@ static uint64_t get_psw_mask(CPUState *env)
return r;
}
-static void do_svc_interrupt(CPUState *env)
+static void do_svc_interrupt(CPUS390XState *env)
{
uint64_t mask, addr;
LowCore *lowcore;
@@ -514,7 +514,7 @@ static void do_svc_interrupt(CPUState *env)
load_psw(env, mask, addr);
}
-static void do_program_interrupt(CPUState *env)
+static void do_program_interrupt(CPUS390XState *env)
{
uint64_t mask, addr;
LowCore *lowcore;
@@ -557,7 +557,7 @@ static void do_program_interrupt(CPUState *env)
#define VIRTIO_SUBCODE_64 0x0D00
-static void do_ext_interrupt(CPUState *env)
+static void do_ext_interrupt(CPUS390XState *env)
{
uint64_t mask, addr;
LowCore *lowcore;
@@ -597,7 +597,7 @@ static void do_ext_interrupt(CPUState *env)
load_psw(env, mask, addr);
}
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUS390XState *env)
{
qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
env->psw.addr);
diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c
index b1404bf..2b67231 100644
--- a/target-s390x/kvm.c
+++ b/target-s390x/kvm.c
@@ -72,7 +72,7 @@ int kvm_arch_init(KVMState *s)
return 0;
}
-int kvm_arch_init_vcpu(CPUState *env)
+int kvm_arch_init_vcpu(CPUS390XState *env)
{
int ret = 0;
@@ -83,12 +83,12 @@ int kvm_arch_init_vcpu(CPUState *env)
return ret;
}
-void kvm_arch_reset_vcpu(CPUState *env)
+void kvm_arch_reset_vcpu(CPUS390XState *env)
{
/* FIXME: add code to reset vcpu. */
}
-int kvm_arch_put_registers(CPUState *env, int level)
+int kvm_arch_put_registers(CPUS390XState *env, int level)
{
struct kvm_regs regs;
int ret;
@@ -114,7 +114,7 @@ int kvm_arch_put_registers(CPUState *env, int level)
return ret;
}
-int kvm_arch_get_registers(CPUState *env)
+int kvm_arch_get_registers(CPUS390XState *env)
{
int ret;
struct kvm_regs regs;
@@ -135,7 +135,7 @@ int kvm_arch_get_registers(CPUState *env)
return 0;
}
-int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+int kvm_arch_insert_sw_breakpoint(CPUS390XState *env, struct kvm_sw_breakpoint *bp)
{
static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01};
@@ -146,7 +146,7 @@ int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
return 0;
}
-int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
+int kvm_arch_remove_sw_breakpoint(CPUS390XState *env, struct kvm_sw_breakpoint *bp)
{
uint8_t t[4];
static const uint8_t diag_501[] = {0x83, 0x24, 0x05, 0x01};
@@ -162,20 +162,20 @@ int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
return 0;
}
-void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
+void kvm_arch_pre_run(CPUS390XState *env, struct kvm_run *run)
{
}
-void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
+void kvm_arch_post_run(CPUS390XState *env, struct kvm_run *run)
{
}
-int kvm_arch_process_async_events(CPUState *env)
+int kvm_arch_process_async_events(CPUS390XState *env)
{
return env->halted;
}
-void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm,
+void kvm_s390_interrupt_internal(CPUS390XState *env, int type, uint32_t parm,
uint64_t parm64, int vm)
{
struct kvm_s390_interrupt kvmint;
@@ -201,23 +201,23 @@ void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm,
}
}
-void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token)
+void kvm_s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token)
{
kvm_s390_interrupt_internal(env, KVM_S390_INT_VIRTIO, config_change,
token, 1);
}
-void kvm_s390_interrupt(CPUState *env, int type, uint32_t code)
+void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code)
{
kvm_s390_interrupt_internal(env, type, code, 0, 0);
}
-static void enter_pgmcheck(CPUState *env, uint16_t code)
+static void enter_pgmcheck(CPUS390XState *env, uint16_t code)
{
kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
}
-static inline void setcc(CPUState *env, uint64_t cc)
+static inline void setcc(CPUS390XState *env, uint64_t cc)
{
env->kvm_run->psw_mask &= ~(3ull << 44);
env->kvm_run->psw_mask |= (cc & 3) << 44;
@@ -226,7 +226,7 @@ static inline void setcc(CPUState *env, uint64_t cc)
env->psw.mask |= (cc & 3) << 44;
}
-static int kvm_sclp_service_call(CPUState *env, struct kvm_run *run,
+static int kvm_sclp_service_call(CPUS390XState *env, struct kvm_run *run,
uint16_t ipbh0)
{
uint32_t sccb;
@@ -245,7 +245,7 @@ static int kvm_sclp_service_call(CPUState *env, struct kvm_run *run,
return 0;
}
-static int handle_priv(CPUState *env, struct kvm_run *run, uint8_t ipa1)
+static int handle_priv(CPUS390XState *env, struct kvm_run *run, uint8_t ipa1)
{
int r = 0;
uint16_t ipbh0 = (run->s390_sieic.ipb & 0xffff0000) >> 16;
@@ -264,7 +264,7 @@ static int handle_priv(CPUState *env, struct kvm_run *run, uint8_t ipa1)
return r;
}
-static int handle_hypercall(CPUState *env, struct kvm_run *run)
+static int handle_hypercall(CPUS390XState *env, struct kvm_run *run)
{
cpu_synchronize_state(env);
env->regs[2] = s390_virtio_hypercall(env, env->regs[2], env->regs[1]);
@@ -272,7 +272,7 @@ static int handle_hypercall(CPUState *env, struct kvm_run *run)
return 0;
}
-static int handle_diag(CPUState *env, struct kvm_run *run, int ipb_code)
+static int handle_diag(CPUS390XState *env, struct kvm_run *run, int ipb_code)
{
int r = 0;
@@ -292,7 +292,7 @@ static int handle_diag(CPUState *env, struct kvm_run *run, int ipb_code)
return r;
}
-static int s390_cpu_restart(CPUState *env)
+static int s390_cpu_restart(CPUS390XState *env)
{
kvm_s390_interrupt(env, KVM_S390_RESTART, 0);
s390_add_running_cpu(env);
@@ -301,14 +301,14 @@ static int s390_cpu_restart(CPUState *env)
return 0;
}
-static int s390_store_status(CPUState *env, uint32_t parameter)
+static int s390_store_status(CPUS390XState *env, uint32_t parameter)
{
/* XXX */
fprintf(stderr, "XXX SIGP store status\n");
return -1;
}
-static int s390_cpu_initial_reset(CPUState *env)
+static int s390_cpu_initial_reset(CPUS390XState *env)
{
int i;
@@ -326,14 +326,14 @@ static int s390_cpu_initial_reset(CPUState *env)
return 0;
}
-static int handle_sigp(CPUState *env, struct kvm_run *run, uint8_t ipa1)
+static int handle_sigp(CPUS390XState *env, struct kvm_run *run, uint8_t ipa1)
{
uint8_t order_code;
uint32_t parameter;
uint16_t cpu_addr;
uint8_t t;
int r = -1;
- CPUState *target_env;
+ CPUS390XState *target_env;
cpu_synchronize_state(env);
@@ -381,7 +381,7 @@ out:
return 0;
}
-static int handle_instruction(CPUState *env, struct kvm_run *run)
+static int handle_instruction(CPUS390XState *env, struct kvm_run *run)
{
unsigned int ipa0 = (run->s390_sieic.ipa & 0xff00);
uint8_t ipa1 = run->s390_sieic.ipa & 0x00ff;
@@ -407,7 +407,7 @@ static int handle_instruction(CPUState *env, struct kvm_run *run)
return 0;
}
-static int handle_intercept(CPUState *env)
+static int handle_intercept(CPUS390XState *env)
{
struct kvm_run *run = env->kvm_run;
int icpt_code = run->s390_sieic.icptcode;
@@ -443,7 +443,7 @@ static int handle_intercept(CPUState *env)
return r;
}
-int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
+int kvm_arch_handle_exit(CPUS390XState *env, struct kvm_run *run)
{
int ret = 0;
@@ -466,12 +466,12 @@ int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
return ret;
}
-bool kvm_arch_stop_on_emulation_error(CPUState *env)
+bool kvm_arch_stop_on_emulation_error(CPUS390XState *env)
{
return true;
}
-int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+int kvm_arch_on_sigbus_vcpu(CPUS390XState *env, int code, void *addr)
{
return 1;
}
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index 70d98a8..18fdbb2 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -56,11 +56,11 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUS390XState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
- CPUState *saved_env;
+ CPUS390XState *saved_env;
unsigned long pc;
int ret;
@@ -101,7 +101,7 @@ void HELPER(exception)(uint32_t excp)
}
#ifndef CONFIG_USER_ONLY
-static void mvc_fast_memset(CPUState *env, uint32_t l, uint64_t dest,
+static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
uint8_t byte)
{
target_phys_addr_t dest_phys;
@@ -123,7 +123,7 @@ static void mvc_fast_memset(CPUState *env, uint32_t l, uint64_t dest,
cpu_physical_memory_unmap(dest_p, 1, len, len);
}
-static void mvc_fast_memmove(CPUState *env, uint32_t l, uint64_t dest,
+static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
uint64_t src)
{
target_phys_addr_t dest_phys;
@@ -1790,7 +1790,7 @@ void HELPER(cksm)(uint32_t r1, uint32_t r2)
((uint32_t)cksm + (cksm >> 32));
}
-static inline uint32_t cc_calc_ltgt_32(CPUState *env, int32_t src,
+static inline uint32_t cc_calc_ltgt_32(CPUS390XState *env, int32_t src,
int32_t dst)
{
if (src == dst) {
@@ -1802,12 +1802,12 @@ static inline uint32_t cc_calc_ltgt_32(CPUState *env, int32_t src,
}
}
-static inline uint32_t cc_calc_ltgt0_32(CPUState *env, int32_t dst)
+static inline uint32_t cc_calc_ltgt0_32(CPUS390XState *env, int32_t dst)
{
return cc_calc_ltgt_32(env, dst, 0);
}
-static inline uint32_t cc_calc_ltgt_64(CPUState *env, int64_t src,
+static inline uint32_t cc_calc_ltgt_64(CPUS390XState *env, int64_t src,
int64_t dst)
{
if (src == dst) {
@@ -1819,12 +1819,12 @@ static inline uint32_t cc_calc_ltgt_64(CPUState *env, int64_t src,
}
}
-static inline uint32_t cc_calc_ltgt0_64(CPUState *env, int64_t dst)
+static inline uint32_t cc_calc_ltgt0_64(CPUS390XState *env, int64_t dst)
{
return cc_calc_ltgt_64(env, dst, 0);
}
-static inline uint32_t cc_calc_ltugtu_32(CPUState *env, uint32_t src,
+static inline uint32_t cc_calc_ltugtu_32(CPUS390XState *env, uint32_t src,
uint32_t dst)
{
if (src == dst) {
@@ -1836,7 +1836,7 @@ static inline uint32_t cc_calc_ltugtu_32(CPUState *env, uint32_t src,
}
}
-static inline uint32_t cc_calc_ltugtu_64(CPUState *env, uint64_t src,
+static inline uint32_t cc_calc_ltugtu_64(CPUS390XState *env, uint64_t src,
uint64_t dst)
{
if (src == dst) {
@@ -1848,7 +1848,7 @@ static inline uint32_t cc_calc_ltugtu_64(CPUState *env, uint64_t src,
}
}
-static inline uint32_t cc_calc_tm_32(CPUState *env, uint32_t val, uint32_t mask)
+static inline uint32_t cc_calc_tm_32(CPUS390XState *env, uint32_t val, uint32_t mask)
{
HELPER_LOG("%s: val 0x%x mask 0x%x\n", __FUNCTION__, val, mask);
uint16_t r = val & mask;
@@ -1862,7 +1862,7 @@ static inline uint32_t cc_calc_tm_32(CPUState *env, uint32_t val, uint32_t mask)
}
/* set condition code for test under mask */
-static inline uint32_t cc_calc_tm_64(CPUState *env, uint64_t val, uint32_t mask)
+static inline uint32_t cc_calc_tm_64(CPUS390XState *env, uint64_t val, uint32_t mask)
{
uint16_t r = val & mask;
HELPER_LOG("%s: val 0x%lx mask 0x%x r 0x%x\n", __FUNCTION__, val, mask, r);
@@ -1883,12 +1883,12 @@ static inline uint32_t cc_calc_tm_64(CPUState *env, uint64_t val, uint32_t mask)
}
}
-static inline uint32_t cc_calc_nz(CPUState *env, uint64_t dst)
+static inline uint32_t cc_calc_nz(CPUS390XState *env, uint64_t dst)
{
return !!dst;
}
-static inline uint32_t cc_calc_add_64(CPUState *env, int64_t a1, int64_t a2,
+static inline uint32_t cc_calc_add_64(CPUS390XState *env, int64_t a1, int64_t a2,
int64_t ar)
{
if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
@@ -1904,7 +1904,7 @@ static inline uint32_t cc_calc_add_64(CPUState *env, int64_t a1, int64_t a2,
}
}
-static inline uint32_t cc_calc_addu_64(CPUState *env, uint64_t a1, uint64_t a2,
+static inline uint32_t cc_calc_addu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
uint64_t ar)
{
if (ar == 0) {
@@ -1922,7 +1922,7 @@ static inline uint32_t cc_calc_addu_64(CPUState *env, uint64_t a1, uint64_t a2,
}
}
-static inline uint32_t cc_calc_sub_64(CPUState *env, int64_t a1, int64_t a2,
+static inline uint32_t cc_calc_sub_64(CPUS390XState *env, int64_t a1, int64_t a2,
int64_t ar)
{
if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
@@ -1938,7 +1938,7 @@ static inline uint32_t cc_calc_sub_64(CPUState *env, int64_t a1, int64_t a2,
}
}
-static inline uint32_t cc_calc_subu_64(CPUState *env, uint64_t a1, uint64_t a2,
+static inline uint32_t cc_calc_subu_64(CPUS390XState *env, uint64_t a1, uint64_t a2,
uint64_t ar)
{
if (ar == 0) {
@@ -1952,7 +1952,7 @@ static inline uint32_t cc_calc_subu_64(CPUState *env, uint64_t a1, uint64_t a2,
}
}
-static inline uint32_t cc_calc_abs_64(CPUState *env, int64_t dst)
+static inline uint32_t cc_calc_abs_64(CPUS390XState *env, int64_t dst)
{
if ((uint64_t)dst == 0x8000000000000000ULL) {
return 3;
@@ -1963,12 +1963,12 @@ static inline uint32_t cc_calc_abs_64(CPUState *env, int64_t dst)
}
}
-static inline uint32_t cc_calc_nabs_64(CPUState *env, int64_t dst)
+static inline uint32_t cc_calc_nabs_64(CPUS390XState *env, int64_t dst)
{
return !!dst;
}
-static inline uint32_t cc_calc_comp_64(CPUState *env, int64_t dst)
+static inline uint32_t cc_calc_comp_64(CPUS390XState *env, int64_t dst)
{
if ((uint64_t)dst == 0x8000000000000000ULL) {
return 3;
@@ -1982,7 +1982,7 @@ static inline uint32_t cc_calc_comp_64(CPUState *env, int64_t dst)
}
-static inline uint32_t cc_calc_add_32(CPUState *env, int32_t a1, int32_t a2,
+static inline uint32_t cc_calc_add_32(CPUS390XState *env, int32_t a1, int32_t a2,
int32_t ar)
{
if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
@@ -1998,7 +1998,7 @@ static inline uint32_t cc_calc_add_32(CPUState *env, int32_t a1, int32_t a2,
}
}
-static inline uint32_t cc_calc_addu_32(CPUState *env, uint32_t a1, uint32_t a2,
+static inline uint32_t cc_calc_addu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
uint32_t ar)
{
if (ar == 0) {
@@ -2016,7 +2016,7 @@ static inline uint32_t cc_calc_addu_32(CPUState *env, uint32_t a1, uint32_t a2,
}
}
-static inline uint32_t cc_calc_sub_32(CPUState *env, int32_t a1, int32_t a2,
+static inline uint32_t cc_calc_sub_32(CPUS390XState *env, int32_t a1, int32_t a2,
int32_t ar)
{
if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
@@ -2032,7 +2032,7 @@ static inline uint32_t cc_calc_sub_32(CPUState *env, int32_t a1, int32_t a2,
}
}
-static inline uint32_t cc_calc_subu_32(CPUState *env, uint32_t a1, uint32_t a2,
+static inline uint32_t cc_calc_subu_32(CPUS390XState *env, uint32_t a1, uint32_t a2,
uint32_t ar)
{
if (ar == 0) {
@@ -2046,7 +2046,7 @@ static inline uint32_t cc_calc_subu_32(CPUState *env, uint32_t a1, uint32_t a2,
}
}
-static inline uint32_t cc_calc_abs_32(CPUState *env, int32_t dst)
+static inline uint32_t cc_calc_abs_32(CPUS390XState *env, int32_t dst)
{
if ((uint32_t)dst == 0x80000000UL) {
return 3;
@@ -2057,12 +2057,12 @@ static inline uint32_t cc_calc_abs_32(CPUState *env, int32_t dst)
}
}
-static inline uint32_t cc_calc_nabs_32(CPUState *env, int32_t dst)
+static inline uint32_t cc_calc_nabs_32(CPUS390XState *env, int32_t dst)
{
return !!dst;
}
-static inline uint32_t cc_calc_comp_32(CPUState *env, int32_t dst)
+static inline uint32_t cc_calc_comp_32(CPUS390XState *env, int32_t dst)
{
if ((uint32_t)dst == 0x80000000UL) {
return 3;
@@ -2076,7 +2076,7 @@ static inline uint32_t cc_calc_comp_32(CPUState *env, int32_t dst)
}
/* calculate condition code for insert character under mask insn */
-static inline uint32_t cc_calc_icm_32(CPUState *env, uint32_t mask, uint32_t val)
+static inline uint32_t cc_calc_icm_32(CPUS390XState *env, uint32_t mask, uint32_t val)
{
HELPER_LOG("%s: mask 0x%x val %d\n", __FUNCTION__, mask, val);
uint32_t cc;
@@ -2107,7 +2107,7 @@ static inline uint32_t cc_calc_icm_32(CPUState *env, uint32_t mask, uint32_t val
return cc;
}
-static inline uint32_t cc_calc_slag(CPUState *env, uint64_t src, uint64_t shift)
+static inline uint32_t cc_calc_slag(CPUS390XState *env, uint64_t src, uint64_t shift)
{
uint64_t mask = ((1ULL << shift) - 1ULL) << (64 - shift);
uint64_t match, r;
@@ -2136,7 +2136,7 @@ static inline uint32_t cc_calc_slag(CPUState *env, uint64_t src, uint64_t shift)
}
-static inline uint32_t do_calc_cc(CPUState *env, uint32_t cc_op, uint64_t src,
+static inline uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src,
uint64_t dst, uint64_t vr)
{
uint32_t r = 0;
@@ -2249,7 +2249,7 @@ static inline uint32_t do_calc_cc(CPUState *env, uint32_t cc_op, uint64_t src,
return r;
}
-uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
+uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
uint64_t vr)
{
return do_calc_cc(env, cc_op, src, dst, vr);
@@ -2346,7 +2346,7 @@ void HELPER(load_psw)(uint64_t mask, uint64_t addr)
cpu_loop_exit(env);
}
-static void program_interrupt(CPUState *env, uint32_t code, int ilc)
+static void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
@@ -2362,13 +2362,13 @@ static void program_interrupt(CPUState *env, uint32_t code, int ilc)
}
}
-static void ext_interrupt(CPUState *env, int type, uint32_t param,
+static void ext_interrupt(CPUS390XState *env, int type, uint32_t param,
uint64_t param64)
{
cpu_inject_ext(env, type, param, param64);
}
-int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code)
+int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
{
int r = 0;
int shift = 0;
@@ -2481,7 +2481,7 @@ uint32_t HELPER(sck)(uint64_t a1)
return 0;
}
-static inline uint64_t clock_value(CPUState *env)
+static inline uint64_t clock_value(CPUS390XState *env)
{
uint64_t time;
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 8fab38c..9bf8c38 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -74,7 +74,7 @@ static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
return pc;
}
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -148,25 +148,25 @@ void s390x_translate_init(void)
char *p;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr),
+ psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.addr),
"psw_addr");
- psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask),
+ psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.mask),
"psw_mask");
- cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
+ cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
"cc_op");
- cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src),
+ cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
"cc_src");
- cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst),
+ cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
"cc_dst");
- cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr),
+ cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
"cc_vr");
p = cpu_reg_names;
for (i = 0; i < 16; i++) {
snprintf(p, cpu_reg_names_size, "r%d", i);
regs[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, regs[i]), p);
+ offsetof(CPUS390XState, regs[i]), p);
p += (i < 10) ? 3 : 4;
cpu_reg_names_size -= (i < 10) ? 3 : 4;
}
@@ -182,14 +182,14 @@ static inline TCGv_i64 load_reg(int reg)
static inline TCGv_i64 load_freg(int reg)
{
TCGv_i64 r = tcg_temp_new_i64();
- tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d));
+ tcg_gen_ld_i64(r, cpu_env, offsetof(CPUS390XState, fregs[reg].d));
return r;
}
static inline TCGv_i32 load_freg32(int reg)
{
TCGv_i32 r = tcg_temp_new_i32();
- tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
+ tcg_gen_ld_i32(r, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper));
return r;
}
@@ -214,7 +214,7 @@ static inline void store_reg(int reg, TCGv_i64 v)
static inline void store_freg(int reg, TCGv_i64 v)
{
- tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d));
+ tcg_gen_st_i64(v, cpu_env, offsetof(CPUS390XState, fregs[reg].d));
}
static inline void store_reg32(int reg, TCGv_i32 v)
@@ -257,7 +257,7 @@ static inline void store_reg8(int reg, TCGv_i64 v)
static inline void store_freg32(int reg, TCGv_i32 v)
{
- tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
+ tcg_gen_st_i32(v, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper));
}
static inline void update_psw_addr(DisasContext *s)
@@ -361,11 +361,11 @@ static void gen_program_exception(DisasContext *s, int ilc, int code)
/* remember what pgm exeption this was */
tmp = tcg_const_i32(code);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code));
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
tcg_temp_free_i32(tmp);
tmp = tcg_const_i32(ilc);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc));
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilc));
tcg_temp_free_i32(tmp);
/* advance past instruction */
@@ -2647,12 +2647,12 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
break;
case 0x4e: /* SAR R1,R2 [RRE] */
tmp32_1 = load_reg32(r2);
- tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r1]));
+ tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r1]));
tcg_temp_free_i32(tmp32_1);
break;
case 0x4f: /* EAR R1,R2 [RRE] */
tmp32_1 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r2]));
+ tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, aregs[r2]));
store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
@@ -2807,7 +2807,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUState, psa));
+ tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUS390XState, psa));
tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
@@ -2819,7 +2819,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, cpu_num));
+ tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num));
tcg_gen_extu_i32_i64(tmp2, tmp32_1);
tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp);
@@ -2948,7 +2948,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)
tmp32_1 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
- tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
+ tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
@@ -3158,12 +3158,12 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
break;
case 0x84: /* SFPC R1 [RRE] */
tmp32_1 = load_reg32(r1);
- tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
+ tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
tcg_temp_free_i32(tmp32_1);
break;
case 0x8c: /* EFPC R1 [RRE] */
tmp32_1 = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
+ tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
store_reg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
@@ -3929,8 +3929,8 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_const_i32(i);
tmp32_2 = tcg_const_i32(ilc * 2);
tmp32_3 = tcg_const_i32(EXCP_SVC);
- tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, int_svc_code));
- tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUState, int_svc_ilc));
+ tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, int_svc_code));
+ tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUS390XState, int_svc_ilc));
gen_helper_exception(tmp32_3);
s->is_jmp = DISAS_EXCP;
tcg_temp_free_i32(tmp32_1);
@@ -4810,7 +4810,7 @@ static void disas_s390_insn(DisasContext *s)
tmp32_1 = tcg_temp_new_i32();
tmp = tcg_temp_new_i64();
tmp2 = get_address(s, 0, b2, d2);
- tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
+ tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc));
tcg_gen_extu_i32_i64(tmp, tmp32_1);
tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s));
tcg_temp_free_i32(tmp32_1);
@@ -5107,7 +5107,7 @@ static void disas_s390_insn(DisasContext *s)
s->pc += (ilc * 2);
}
-static inline void gen_intermediate_code_internal(CPUState *env,
+static inline void gen_intermediate_code_internal(CPUS390XState *env,
TranslationBlock *tb,
int search_pc)
{
@@ -5223,17 +5223,17 @@ static inline void gen_intermediate_code_internal(CPUState *env,
#endif
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
{
int cc_op;
env->psw.addr = gen_opc_pc[pc_pos];
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (21 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: " Andreas Färber
` (20 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUSH4State/g" target-sh4/*.[hc]
sed -i "s/#define CPUSH4State/#define CPUState/" target-sh4/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/cpu.h | 10 +++++-----
target-sh4/helper.c | 28 ++++++++++++++--------------
target-sh4/op_helper.c | 4 ++--
target-sh4/translate.c | 46 +++++++++++++++++++++++-----------------------
4 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 7d7fdde..b45e54f 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -240,13 +240,13 @@ void cpu_load_tlb(CPUSH4State * env);
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUSH4State *env)
{
return (env->sr & SR_MD) == 0 ? 1 : 0;
}
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
{
if (newsp)
env->gregs[15] = newsp;
@@ -348,7 +348,7 @@ static inline int cpu_ptel_pr (uint32_t ptel)
#define TB_FLAG_PENDING_MOVCA (1 << 4)
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -361,14 +361,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
}
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUSH4State *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb)
{
env->pc = tb->pc;
env->flags = tb->flags;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 006d1a9..5c57380 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -31,12 +31,12 @@
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUSH4State *env)
{
env->exception_index = -1;
}
-int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
+int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int mmu_idx)
{
env->tea = address;
@@ -78,7 +78,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
#define MMU_DADDR_ERROR_READ (-12)
#define MMU_DADDR_ERROR_WRITE (-13)
-void do_interrupt(CPUState * env)
+void do_interrupt(CPUSH4State * env)
{
int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
int do_exp, irq_vector = env->exception_index;
@@ -202,7 +202,7 @@ void do_interrupt(CPUState * env)
}
}
-static void update_itlb_use(CPUState * env, int itlbnb)
+static void update_itlb_use(CPUSH4State * env, int itlbnb)
{
uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
@@ -227,7 +227,7 @@ static void update_itlb_use(CPUState * env, int itlbnb)
env->mmucr |= (or_mask << 24);
}
-static int itlb_replacement(CPUState * env)
+static int itlb_replacement(CPUSH4State * env)
{
if ((env->mmucr & 0xe0000000) == 0xe0000000)
return 0;
@@ -243,7 +243,7 @@ static int itlb_replacement(CPUState * env)
/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
-static int find_tlb_entry(CPUState * env, target_ulong address,
+static int find_tlb_entry(CPUSH4State * env, target_ulong address,
tlb_t * entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
@@ -269,7 +269,7 @@ static int find_tlb_entry(CPUState * env, target_ulong address,
return match;
}
-static void increment_urc(CPUState * env)
+static void increment_urc(CPUSH4State * env)
{
uint8_t urb, urc;
@@ -285,7 +285,7 @@ static void increment_urc(CPUState * env)
/* Copy and utlb entry into itlb
Return entry
*/
-static int copy_utlb_entry_itlb(CPUState *env, int utlb)
+static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
{
int itlb;
@@ -303,7 +303,7 @@ static int copy_utlb_entry_itlb(CPUState *env, int utlb)
/* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/
-static int find_itlb_entry(CPUState * env, target_ulong address,
+static int find_itlb_entry(CPUSH4State * env, target_ulong address,
int use_asid)
{
int e;
@@ -321,7 +321,7 @@ static int find_itlb_entry(CPUState * env, target_ulong address,
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
{
/* per utlb access */
increment_urc(env);
@@ -337,7 +337,7 @@ static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
-static int get_mmu_address(CPUState * env, target_ulong * physical,
+static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@@ -403,7 +403,7 @@ static int get_mmu_address(CPUState * env, target_ulong * physical,
return n;
}
-static int get_physical_address(CPUState * env, target_ulong * physical,
+static int get_physical_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@@ -442,7 +442,7 @@ static int get_physical_address(CPUState * env, target_ulong * physical,
return get_mmu_address(env, physical, prot, address, rw, access_type);
}
-int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
+int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int mmu_idx)
{
target_ulong physical;
@@ -503,7 +503,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
{
target_ulong physical;
int prot;
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index b299576..30f762f 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -55,10 +55,10 @@ static void cpu_restore_state_from_retaddr(void *retaddr)
#define SHIFT 3
#include "softmmu_template.h"
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
- CPUState *saved_env;
+ CPUSH4State *saved_env;
int ret;
saved_env = env;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c385de8..a337beb 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -103,47 +103,47 @@ static void sh4_translate_init(void)
for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, gregs[i]),
+ offsetof(CPUSH4State, gregs[i]),
gregnames[i]);
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, pc), "PC");
+ offsetof(CPUSH4State, pc), "PC");
cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, sr), "SR");
+ offsetof(CPUSH4State, sr), "SR");
cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, ssr), "SSR");
+ offsetof(CPUSH4State, ssr), "SSR");
cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, spc), "SPC");
+ offsetof(CPUSH4State, spc), "SPC");
cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, gbr), "GBR");
+ offsetof(CPUSH4State, gbr), "GBR");
cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, vbr), "VBR");
+ offsetof(CPUSH4State, vbr), "VBR");
cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, sgr), "SGR");
+ offsetof(CPUSH4State, sgr), "SGR");
cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, dbr), "DBR");
+ offsetof(CPUSH4State, dbr), "DBR");
cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, mach), "MACH");
+ offsetof(CPUSH4State, mach), "MACH");
cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, macl), "MACL");
+ offsetof(CPUSH4State, macl), "MACL");
cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, pr), "PR");
+ offsetof(CPUSH4State, pr), "PR");
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, fpscr), "FPSCR");
+ offsetof(CPUSH4State, fpscr), "FPSCR");
cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, fpul), "FPUL");
+ offsetof(CPUSH4State, fpul), "FPUL");
cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, flags), "_flags_");
+ offsetof(CPUSH4State, flags), "_flags_");
cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, delayed_pc),
+ offsetof(CPUSH4State, delayed_pc),
"_delayed_pc_");
cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, ldst), "_ldst_");
+ offsetof(CPUSH4State, ldst), "_ldst_");
for (i = 0; i < 32; i++)
cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, fregs[i]),
+ offsetof(CPUSH4State, fregs[i]),
fregnames[i]);
/* register helpers */
@@ -153,7 +153,7 @@ static void sh4_translate_init(void)
done_init = 1;
}
-void cpu_dump_state(CPUState * env, FILE * f,
+void cpu_dump_state(CPUSH4State * env, FILE * f,
int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
int flags)
{
@@ -1918,7 +1918,7 @@ static void decode_opc(DisasContext * ctx)
}
static inline void
-gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
+gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
int search_pc)
{
DisasContext ctx;
@@ -2044,17 +2044,17 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
#endif
}
-void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
env->flags = gen_opc_hflags[pc_pos];
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (22 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: " Andreas Färber
` (19 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc]
sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sparc/cc_helper.c | 66 ++++++++++++++++++------------------
target-sparc/cpu.h | 56 +++++++++++++++---------------
target-sparc/cpu_init.c | 2 +-
target-sparc/fop_helper.c | 68 ++++++++++++++++++------------------
target-sparc/helper.c | 16 ++++----
target-sparc/int32_helper.c | 6 ++--
target-sparc/int64_helper.c | 12 +++---
target-sparc/ldst_helper.c | 16 ++++----
target-sparc/machine.c | 4 +-
target-sparc/mmu_helper.c | 28 +++++++-------
target-sparc/op_helper.c | 4 +-
target-sparc/translate.c | 80 +++++++++++++++++++++---------------------
target-sparc/win_helper.c | 58 +++++++++++++++---------------
13 files changed, 208 insertions(+), 208 deletions(-)
diff --git a/target-sparc/cc_helper.c b/target-sparc/cc_helper.c
index 04bd2cf..63bab07 100644
--- a/target-sparc/cc_helper.c
+++ b/target-sparc/cc_helper.c
@@ -20,12 +20,12 @@
#include "cpu.h"
#include "helper.h"
-static uint32_t compute_all_flags(CPUState *env)
+static uint32_t compute_all_flags(CPUSPARCState *env)
{
return env->psr & PSR_ICC;
}
-static uint32_t compute_C_flags(CPUState *env)
+static uint32_t compute_C_flags(CPUSPARCState *env)
{
return env->psr & PSR_CARRY;
}
@@ -43,12 +43,12 @@ static inline uint32_t get_NZ_icc(int32_t dst)
}
#ifdef TARGET_SPARC64
-static uint32_t compute_all_flags_xcc(CPUState *env)
+static uint32_t compute_all_flags_xcc(CPUSPARCState *env)
{
return env->xcc & PSR_ICC;
}
-static uint32_t compute_C_flags_xcc(CPUState *env)
+static uint32_t compute_C_flags_xcc(CPUSPARCState *env)
{
return env->xcc & PSR_CARRY;
}
@@ -76,7 +76,7 @@ static inline uint32_t get_V_div_icc(target_ulong src2)
return ret;
}
-static uint32_t compute_all_div(CPUState *env)
+static uint32_t compute_all_div(CPUSPARCState *env)
{
uint32_t ret;
@@ -85,7 +85,7 @@ static uint32_t compute_all_div(CPUState *env)
return ret;
}
-static uint32_t compute_C_div(CPUState *env)
+static uint32_t compute_C_div(CPUSPARCState *env)
{
return 0;
}
@@ -155,7 +155,7 @@ static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
return ret;
}
-static uint32_t compute_all_add_xcc(CPUState *env)
+static uint32_t compute_all_add_xcc(CPUSPARCState *env)
{
uint32_t ret;
@@ -165,13 +165,13 @@ static uint32_t compute_all_add_xcc(CPUState *env)
return ret;
}
-static uint32_t compute_C_add_xcc(CPUState *env)
+static uint32_t compute_C_add_xcc(CPUSPARCState *env)
{
return get_C_add_xcc(CC_DST, CC_SRC);
}
#endif
-static uint32_t compute_all_add(CPUState *env)
+static uint32_t compute_all_add(CPUSPARCState *env)
{
uint32_t ret;
@@ -181,13 +181,13 @@ static uint32_t compute_all_add(CPUState *env)
return ret;
}
-static uint32_t compute_C_add(CPUState *env)
+static uint32_t compute_C_add(CPUSPARCState *env)
{
return get_C_add_icc(CC_DST, CC_SRC);
}
#ifdef TARGET_SPARC64
-static uint32_t compute_all_addx_xcc(CPUState *env)
+static uint32_t compute_all_addx_xcc(CPUSPARCState *env)
{
uint32_t ret;
@@ -197,7 +197,7 @@ static uint32_t compute_all_addx_xcc(CPUState *env)
return ret;
}
-static uint32_t compute_C_addx_xcc(CPUState *env)
+static uint32_t compute_C_addx_xcc(CPUSPARCState *env)
{
uint32_t ret;
@@ -206,7 +206,7 @@ static uint32_t compute_C_addx_xcc(CPUState *env)
}
#endif
-static uint32_t compute_all_addx(CPUState *env)
+static uint32_t compute_all_addx(CPUSPARCState *env)
{
uint32_t ret;
@@ -216,7 +216,7 @@ static uint32_t compute_all_addx(CPUState *env)
return ret;
}
-static uint32_t compute_C_addx(CPUState *env)
+static uint32_t compute_C_addx(CPUSPARCState *env)
{
uint32_t ret;
@@ -234,7 +234,7 @@ static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2)
return ret;
}
-static uint32_t compute_all_tadd(CPUState *env)
+static uint32_t compute_all_tadd(CPUSPARCState *env)
{
uint32_t ret;
@@ -245,7 +245,7 @@ static uint32_t compute_all_tadd(CPUState *env)
return ret;
}
-static uint32_t compute_all_taddtv(CPUState *env)
+static uint32_t compute_all_taddtv(CPUSPARCState *env)
{
uint32_t ret;
@@ -320,7 +320,7 @@ static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
return ret;
}
-static uint32_t compute_all_sub_xcc(CPUState *env)
+static uint32_t compute_all_sub_xcc(CPUSPARCState *env)
{
uint32_t ret;
@@ -330,13 +330,13 @@ static uint32_t compute_all_sub_xcc(CPUState *env)
return ret;
}
-static uint32_t compute_C_sub_xcc(CPUState *env)
+static uint32_t compute_C_sub_xcc(CPUSPARCState *env)
{
return get_C_sub_xcc(CC_SRC, CC_SRC2);
}
#endif
-static uint32_t compute_all_sub(CPUState *env)
+static uint32_t compute_all_sub(CPUSPARCState *env)
{
uint32_t ret;
@@ -346,13 +346,13 @@ static uint32_t compute_all_sub(CPUState *env)
return ret;
}
-static uint32_t compute_C_sub(CPUState *env)
+static uint32_t compute_C_sub(CPUSPARCState *env)
{
return get_C_sub_icc(CC_SRC, CC_SRC2);
}
#ifdef TARGET_SPARC64
-static uint32_t compute_all_subx_xcc(CPUState *env)
+static uint32_t compute_all_subx_xcc(CPUSPARCState *env)
{
uint32_t ret;
@@ -362,7 +362,7 @@ static uint32_t compute_all_subx_xcc(CPUState *env)
return ret;
}
-static uint32_t compute_C_subx_xcc(CPUState *env)
+static uint32_t compute_C_subx_xcc(CPUSPARCState *env)
{
uint32_t ret;
@@ -371,7 +371,7 @@ static uint32_t compute_C_subx_xcc(CPUState *env)
}
#endif
-static uint32_t compute_all_subx(CPUState *env)
+static uint32_t compute_all_subx(CPUSPARCState *env)
{
uint32_t ret;
@@ -381,7 +381,7 @@ static uint32_t compute_all_subx(CPUState *env)
return ret;
}
-static uint32_t compute_C_subx(CPUState *env)
+static uint32_t compute_C_subx(CPUSPARCState *env)
{
uint32_t ret;
@@ -389,7 +389,7 @@ static uint32_t compute_C_subx(CPUState *env)
return ret;
}
-static uint32_t compute_all_tsub(CPUState *env)
+static uint32_t compute_all_tsub(CPUSPARCState *env)
{
uint32_t ret;
@@ -400,7 +400,7 @@ static uint32_t compute_all_tsub(CPUState *env)
return ret;
}
-static uint32_t compute_all_tsubtv(CPUState *env)
+static uint32_t compute_all_tsubtv(CPUSPARCState *env)
{
uint32_t ret;
@@ -409,26 +409,26 @@ static uint32_t compute_all_tsubtv(CPUState *env)
return ret;
}
-static uint32_t compute_all_logic(CPUState *env)
+static uint32_t compute_all_logic(CPUSPARCState *env)
{
return get_NZ_icc(CC_DST);
}
-static uint32_t compute_C_logic(CPUState *env)
+static uint32_t compute_C_logic(CPUSPARCState *env)
{
return 0;
}
#ifdef TARGET_SPARC64
-static uint32_t compute_all_logic_xcc(CPUState *env)
+static uint32_t compute_all_logic_xcc(CPUSPARCState *env)
{
return get_NZ_xcc(CC_DST);
}
#endif
typedef struct CCTable {
- uint32_t (*compute_all)(CPUState *env); /* return all the flags */
- uint32_t (*compute_c)(CPUState *env); /* return the C flag */
+ uint32_t (*compute_all)(CPUSPARCState *env); /* return all the flags */
+ uint32_t (*compute_c)(CPUSPARCState *env); /* return the C flag */
} CCTable;
static const CCTable icc_table[CC_OP_NB] = {
@@ -463,7 +463,7 @@ static const CCTable xcc_table[CC_OP_NB] = {
};
#endif
-void helper_compute_psr(CPUState *env)
+void helper_compute_psr(CPUSPARCState *env)
{
uint32_t new_psr;
@@ -476,7 +476,7 @@ void helper_compute_psr(CPUState *env)
CC_OP = CC_OP_FLAGS;
}
-uint32_t helper_compute_C_icc(CPUState *env)
+uint32_t helper_compute_C_icc(CPUSPARCState *env)
{
uint32_t ret;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 8098669..2c2cea7 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -501,7 +501,7 @@ struct CPUSPARCState {
sparc_def_t *def;
void *irq_manager;
- void (*qemu_irq_ack)(CPUState *env, void *irq_manager, int intno);
+ void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
/* Leon3 cache control */
uint32_t cache_control;
@@ -517,10 +517,10 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw
int mmu_idx);
#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
-int target_memory_rw_debug(CPUState *env, target_ulong addr,
+int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
uint8_t *buf, int len, int is_write);
#define TARGET_CPU_MEMORY_RW_DEBUG
#endif
@@ -533,22 +533,22 @@ void gen_intermediate_code_init(CPUSPARCState *env);
int cpu_sparc_exec(CPUSPARCState *s);
/* win_helper.c */
-target_ulong cpu_get_psr(CPUState *env1);
-void cpu_put_psr(CPUState *env1, target_ulong val);
+target_ulong cpu_get_psr(CPUSPARCState *env1);
+void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
#ifdef TARGET_SPARC64
-target_ulong cpu_get_ccr(CPUState *env1);
-void cpu_put_ccr(CPUState *env1, target_ulong val);
-target_ulong cpu_get_cwp64(CPUState *env1);
-void cpu_put_cwp64(CPUState *env1, int cwp);
-void cpu_change_pstate(CPUState *env1, uint32_t new_pstate);
+target_ulong cpu_get_ccr(CPUSPARCState *env1);
+void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
+target_ulong cpu_get_cwp64(CPUSPARCState *env1);
+void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
+void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
#endif
-int cpu_cwp_inc(CPUState *env1, int cwp);
-int cpu_cwp_dec(CPUState *env1, int cwp);
-void cpu_set_cwp(CPUState *env1, int new_cwp);
+int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
+int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
+void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
/* int_helper.c */
-void do_interrupt(CPUState *env);
-void leon3_irq_manager(CPUState *env, void *irq_manager, int intno);
+void do_interrupt(CPUSPARCState *env);
+void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
/* sun4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
@@ -577,10 +577,10 @@ static inline int tlb_compare_context(const SparcTLBEntry *tlb,
/* cpu-exec.c */
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUSPARCState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size);
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
+target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx);
#endif
@@ -617,23 +617,23 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#endif
#if defined (TARGET_SPARC64)
-static inline int cpu_has_hypervisor(CPUState *env1)
+static inline int cpu_has_hypervisor(CPUSPARCState *env1)
{
return env1->def->features & CPU_FEATURE_HYPV;
}
-static inline int cpu_hypervisor_mode(CPUState *env1)
+static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
{
return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
}
-static inline int cpu_supervisor_mode(CPUState *env1)
+static inline int cpu_supervisor_mode(CPUSPARCState *env1)
{
return env1->pstate & PS_PRIV;
}
#endif
-static inline int cpu_mmu_index(CPUState *env1)
+static inline int cpu_mmu_index(CPUSPARCState *env1)
{
#if defined(CONFIG_USER_ONLY)
return MMU_USER_IDX;
@@ -652,7 +652,7 @@ static inline int cpu_mmu_index(CPUState *env1)
#endif
}
-static inline int cpu_interrupts_enabled(CPUState *env1)
+static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
if (env1->psret != 0)
@@ -665,7 +665,7 @@ static inline int cpu_interrupts_enabled(CPUState *env1)
return 0;
}
-static inline int cpu_pil_allowed(CPUState *env1, int pil)
+static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
{
#if !defined(TARGET_SPARC64)
/* level 15 is non-maskable on sparc v8 */
@@ -676,7 +676,7 @@ static inline int cpu_pil_allowed(CPUState *env1, int pil)
}
#if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp)
{
if (newsp)
env->regwptr[22] = newsp;
@@ -694,13 +694,13 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
uint64_t cpu_tick_get_count(CPUTimer *timer);
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
-trap_state* cpu_tsptr(CPUState* env);
+trap_state* cpu_tsptr(CPUSPARCState* env);
#endif
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -745,7 +745,7 @@ static inline bool tb_am_enabled(int tb_flags)
#endif
}
-static inline bool cpu_has_work(CPUState *env1)
+static inline bool cpu_has_work(CPUSPARCState *env1)
{
return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_interrupts_enabled(env1);
@@ -753,7 +753,7 @@ static inline bool cpu_has_work(CPUState *env1)
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUSPARCState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
env->npc = tb->cs_base;
diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
index bb8b761..29132fb 100644
--- a/target-sparc/cpu_init.c
+++ b/target-sparc/cpu_init.c
@@ -780,7 +780,7 @@ static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
#define REGS_PER_LINE 8
#endif
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i, x;
diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c
index c7a2512..9c64ef8 100644
--- a/target-sparc/fop_helper.c
+++ b/target-sparc/fop_helper.c
@@ -23,7 +23,7 @@
#define QT0 (env->qt0)
#define QT1 (env->qt1)
-static void check_ieee_exceptions(CPUState *env)
+static void check_ieee_exceptions(CPUSPARCState *env)
{
target_ulong status;
@@ -57,15 +57,15 @@ static void check_ieee_exceptions(CPUState *env)
}
}
-static inline void clear_float_exceptions(CPUState *env)
+static inline void clear_float_exceptions(CPUSPARCState *env)
{
set_float_exception_flags(0, &env->fp_status);
}
-#define F_HELPER(name, p) void helper_f##name##p(CPUState *env)
+#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
#define F_BINOP(name) \
- float32 helper_f ## name ## s (CPUState *env, float32 src1, \
+ float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
float32 src2) \
{ \
float32 ret; \
@@ -74,7 +74,7 @@ static inline void clear_float_exceptions(CPUState *env)
check_ieee_exceptions(env); \
return ret; \
} \
- float64 helper_f ## name ## d (CPUState * env, float64 src1,\
+ float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
float64 src2) \
{ \
float64 ret; \
@@ -96,7 +96,7 @@ F_BINOP(mul);
F_BINOP(div);
#undef F_BINOP
-float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2)
+float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
{
float64 ret;
clear_float_exceptions(env);
@@ -107,7 +107,7 @@ float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2)
return ret;
}
-void helper_fdmulq(CPUState *env, float64 src1, float64 src2)
+void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
{
clear_float_exceptions(env);
QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
@@ -134,7 +134,7 @@ F_HELPER(neg, q)
#endif
/* Integer to float conversion. */
-float32 helper_fitos(CPUState *env, int32_t src)
+float32 helper_fitos(CPUSPARCState *env, int32_t src)
{
/* Inexact error possible converting int to float. */
float32 ret;
@@ -144,20 +144,20 @@ float32 helper_fitos(CPUState *env, int32_t src)
return ret;
}
-float64 helper_fitod(CPUState *env, int32_t src)
+float64 helper_fitod(CPUSPARCState *env, int32_t src)
{
/* No possible exceptions converting int to double. */
return int32_to_float64(src, &env->fp_status);
}
-void helper_fitoq(CPUState *env, int32_t src)
+void helper_fitoq(CPUSPARCState *env, int32_t src)
{
/* No possible exceptions converting int to long double. */
QT0 = int32_to_float128(src, &env->fp_status);
}
#ifdef TARGET_SPARC64
-float32 helper_fxtos(CPUState *env, int64_t src)
+float32 helper_fxtos(CPUSPARCState *env, int64_t src)
{
float32 ret;
clear_float_exceptions(env);
@@ -166,7 +166,7 @@ float32 helper_fxtos(CPUState *env, int64_t src)
return ret;
}
-float64 helper_fxtod(CPUState *env, int64_t src)
+float64 helper_fxtod(CPUSPARCState *env, int64_t src)
{
float64 ret;
clear_float_exceptions(env);
@@ -175,7 +175,7 @@ float64 helper_fxtod(CPUState *env, int64_t src)
return ret;
}
-void helper_fxtoq(CPUState *env, int64_t src)
+void helper_fxtoq(CPUSPARCState *env, int64_t src)
{
/* No possible exceptions converting long long to long double. */
QT0 = int64_to_float128(src, &env->fp_status);
@@ -184,7 +184,7 @@ void helper_fxtoq(CPUState *env, int64_t src)
#undef F_HELPER
/* floating point conversion */
-float32 helper_fdtos(CPUState *env, float64 src)
+float32 helper_fdtos(CPUSPARCState *env, float64 src)
{
float32 ret;
clear_float_exceptions(env);
@@ -193,7 +193,7 @@ float32 helper_fdtos(CPUState *env, float64 src)
return ret;
}
-float64 helper_fstod(CPUState *env, float32 src)
+float64 helper_fstod(CPUSPARCState *env, float32 src)
{
float64 ret;
clear_float_exceptions(env);
@@ -202,7 +202,7 @@ float64 helper_fstod(CPUState *env, float32 src)
return ret;
}
-float32 helper_fqtos(CPUState *env)
+float32 helper_fqtos(CPUSPARCState *env)
{
float32 ret;
clear_float_exceptions(env);
@@ -211,14 +211,14 @@ float32 helper_fqtos(CPUState *env)
return ret;
}
-void helper_fstoq(CPUState *env, float32 src)
+void helper_fstoq(CPUSPARCState *env, float32 src)
{
clear_float_exceptions(env);
QT0 = float32_to_float128(src, &env->fp_status);
check_ieee_exceptions(env);
}
-float64 helper_fqtod(CPUState *env)
+float64 helper_fqtod(CPUSPARCState *env)
{
float64 ret;
clear_float_exceptions(env);
@@ -227,7 +227,7 @@ float64 helper_fqtod(CPUState *env)
return ret;
}
-void helper_fdtoq(CPUState *env, float64 src)
+void helper_fdtoq(CPUSPARCState *env, float64 src)
{
clear_float_exceptions(env);
QT0 = float64_to_float128(src, &env->fp_status);
@@ -235,7 +235,7 @@ void helper_fdtoq(CPUState *env, float64 src)
}
/* Float to integer conversion. */
-int32_t helper_fstoi(CPUState *env, float32 src)
+int32_t helper_fstoi(CPUSPARCState *env, float32 src)
{
int32_t ret;
clear_float_exceptions(env);
@@ -244,7 +244,7 @@ int32_t helper_fstoi(CPUState *env, float32 src)
return ret;
}
-int32_t helper_fdtoi(CPUState *env, float64 src)
+int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
{
int32_t ret;
clear_float_exceptions(env);
@@ -253,7 +253,7 @@ int32_t helper_fdtoi(CPUState *env, float64 src)
return ret;
}
-int32_t helper_fqtoi(CPUState *env)
+int32_t helper_fqtoi(CPUSPARCState *env)
{
int32_t ret;
clear_float_exceptions(env);
@@ -263,7 +263,7 @@ int32_t helper_fqtoi(CPUState *env)
}
#ifdef TARGET_SPARC64
-int64_t helper_fstox(CPUState *env, float32 src)
+int64_t helper_fstox(CPUSPARCState *env, float32 src)
{
int64_t ret;
clear_float_exceptions(env);
@@ -272,7 +272,7 @@ int64_t helper_fstox(CPUState *env, float32 src)
return ret;
}
-int64_t helper_fdtox(CPUState *env, float64 src)
+int64_t helper_fdtox(CPUSPARCState *env, float64 src)
{
int64_t ret;
clear_float_exceptions(env);
@@ -281,7 +281,7 @@ int64_t helper_fdtox(CPUState *env, float64 src)
return ret;
}
-int64_t helper_fqtox(CPUState *env)
+int64_t helper_fqtox(CPUSPARCState *env)
{
int64_t ret;
clear_float_exceptions(env);
@@ -302,13 +302,13 @@ float64 helper_fabsd(float64 src)
return float64_abs(src);
}
-void helper_fabsq(CPUState *env)
+void helper_fabsq(CPUSPARCState *env)
{
QT0 = float128_abs(QT1);
}
#endif
-float32 helper_fsqrts(CPUState *env, float32 src)
+float32 helper_fsqrts(CPUSPARCState *env, float32 src)
{
float32 ret;
clear_float_exceptions(env);
@@ -317,7 +317,7 @@ float32 helper_fsqrts(CPUState *env, float32 src)
return ret;
}
-float64 helper_fsqrtd(CPUState *env, float64 src)
+float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
{
float64 ret;
clear_float_exceptions(env);
@@ -326,7 +326,7 @@ float64 helper_fsqrtd(CPUState *env, float64 src)
return ret;
}
-void helper_fsqrtq(CPUState *env)
+void helper_fsqrtq(CPUSPARCState *env)
{
clear_float_exceptions(env);
QT0 = float128_sqrt(QT1, &env->fp_status);
@@ -334,7 +334,7 @@ void helper_fsqrtq(CPUState *env)
}
#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
- void glue(helper_, name) (CPUState *env) \
+ void glue(helper_, name) (CPUSPARCState *env) \
{ \
env->fsr &= FSR_FTT_NMASK; \
if (E && (glue(size, _is_any_nan)(reg1) || \
@@ -370,7 +370,7 @@ void helper_fsqrtq(CPUState *env)
} \
}
#define GEN_FCMP_T(name, size, FS, E) \
- void glue(helper_, name)(CPUState *env, size src1, size src2) \
+ void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \
{ \
env->fsr &= FSR_FTT_NMASK; \
if (E && (glue(size, _is_any_nan)(src1) || \
@@ -443,7 +443,7 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#undef GEN_FCMP_T
#undef GEN_FCMP
-static inline void set_fsr(CPUState *env)
+static inline void set_fsr(CPUSPARCState *env)
{
int rnd_mode;
@@ -465,14 +465,14 @@ static inline void set_fsr(CPUState *env)
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
-void helper_ldfsr(CPUState *env, uint32_t new_fsr)
+void helper_ldfsr(CPUSPARCState *env, uint32_t new_fsr)
{
env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
set_fsr(env);
}
#ifdef TARGET_SPARC64
-void helper_ldxfsr(CPUState *env, uint64_t new_fsr)
+void helper_ldxfsr(CPUSPARCState *env, uint64_t new_fsr)
{
env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env);
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 037a72c..65e1740 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -22,13 +22,13 @@
#include "helper.h"
#include "sysemu.h"
-void helper_raise_exception(CPUState *env, int tt)
+void helper_raise_exception(CPUSPARCState *env, int tt)
{
env->exception_index = tt;
cpu_loop_exit(env);
}
-void helper_debug(CPUState *env)
+void helper_debug(CPUSPARCState *env)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
@@ -64,7 +64,7 @@ void helper_tick_set_limit(void *opaque, uint64_t limit)
}
#endif
-static target_ulong helper_udiv_common(CPUState *env, target_ulong a,
+static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a,
target_ulong b, int cc)
{
int overflow = 0;
@@ -92,17 +92,17 @@ static target_ulong helper_udiv_common(CPUState *env, target_ulong a,
return x0;
}
-target_ulong helper_udiv(CPUState *env, target_ulong a, target_ulong b)
+target_ulong helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong b)
{
return helper_udiv_common(env, a, b, 0);
}
-target_ulong helper_udiv_cc(CPUState *env, target_ulong a, target_ulong b)
+target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)
{
return helper_udiv_common(env, a, b, 1);
}
-static target_ulong helper_sdiv_common(CPUState *env, target_ulong a,
+static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a,
target_ulong b, int cc)
{
int overflow = 0;
@@ -130,12 +130,12 @@ static target_ulong helper_sdiv_common(CPUState *env, target_ulong a,
return x0;
}
-target_ulong helper_sdiv(CPUState *env, target_ulong a, target_ulong b)
+target_ulong helper_sdiv(CPUSPARCState *env, target_ulong a, target_ulong b)
{
return helper_sdiv_common(env, a, b, 0);
}
-target_ulong helper_sdiv_cc(CPUState *env, target_ulong a, target_ulong b)
+target_ulong helper_sdiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)
{
return helper_sdiv_common(env, a, b, 1);
}
diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
index ac9d01e..5e33d50 100644
--- a/target-sparc/int32_helper.c
+++ b/target-sparc/int32_helper.c
@@ -58,7 +58,7 @@ static const char * const excp_names[0x80] = {
};
#endif
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUSPARCState *env)
{
int cwp, intno = env->exception_index;
@@ -132,7 +132,7 @@ void do_interrupt(CPUState *env)
}
#if !defined(CONFIG_USER_ONLY)
-static void leon3_cache_control_int(CPUState *env)
+static void leon3_cache_control_int(CPUSPARCState *env)
{
uint32_t state = 0;
@@ -161,7 +161,7 @@ static void leon3_cache_control_int(CPUState *env)
}
}
-void leon3_irq_manager(CPUState *env, void *irq_manager, int intno)
+void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
{
leon3_irq_ack(irq_manager, intno);
leon3_cache_control_int(env);
diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c
index 1d471db..5e3eff7 100644
--- a/target-sparc/int64_helper.c
+++ b/target-sparc/int64_helper.c
@@ -59,7 +59,7 @@ static const char * const excp_names[0x80] = {
};
#endif
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUSPARCState *env)
{
int intno = env->exception_index;
trap_state *tsptr;
@@ -160,12 +160,12 @@ void do_interrupt(CPUState *env)
env->exception_index = -1;
}
-trap_state *cpu_tsptr(CPUState* env)
+trap_state *cpu_tsptr(CPUSPARCState* env)
{
return &env->ts[env->tl & MAXTL_MASK];
}
-static bool do_modify_softint(CPUState *env, uint32_t value)
+static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
{
if (env->softint != value) {
env->softint = value;
@@ -179,21 +179,21 @@ static bool do_modify_softint(CPUState *env, uint32_t value)
return false;
}
-void helper_set_softint(CPUState *env, uint64_t value)
+void helper_set_softint(CPUSPARCState *env, uint64_t value)
{
if (do_modify_softint(env, env->softint | (uint32_t)value)) {
trace_int_helper_set_softint(env->softint);
}
}
-void helper_clear_softint(CPUState *env, uint64_t value)
+void helper_clear_softint(CPUSPARCState *env, uint64_t value)
{
if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
trace_int_helper_clear_softint(env->softint);
}
}
-void helper_write_softint(CPUState *env, uint64_t value)
+void helper_write_softint(CPUSPARCState *env, uint64_t value)
{
if (do_modify_softint(env, (uint32_t)value)) {
trace_int_helper_write_softint(env->softint);
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index b59707e..48d433c 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -129,7 +129,7 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
static void replace_tlb_entry(SparcTLBEntry *tlb,
uint64_t tlb_tag, uint64_t tlb_tte,
- CPUState *env1)
+ CPUSPARCState *env1)
{
target_ulong mask, size, va, offset;
@@ -152,7 +152,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
}
static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
- const char *strmmu, CPUState *env1)
+ const char *strmmu, CPUSPARCState *env1)
{
unsigned int i;
target_ulong mask;
@@ -213,7 +213,7 @@ static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
uint64_t tlb_tag, uint64_t tlb_tte,
- const char *strmmu, CPUState *env1)
+ const char *strmmu, CPUSPARCState *env1)
{
unsigned int i, replace_used;
@@ -263,7 +263,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
#endif
-static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
+static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
{
#ifdef TARGET_SPARC64
if (AM_CHECK(env1)) {
@@ -300,7 +300,7 @@ static inline int is_translating_asi(int asi)
#endif
}
-static inline target_ulong asi_address_mask(CPUState *env1,
+static inline target_ulong asi_address_mask(CPUSPARCState *env1,
int asi, target_ulong addr)
{
if (is_translating_asi(asi)) {
@@ -323,7 +323,7 @@ void helper_check_align(target_ulong addr, uint32_t align)
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
defined(DEBUG_MXCC)
-static void dump_mxcc(CPUState *env)
+static void dump_mxcc(CPUSPARCState *env)
{
printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
"\n",
@@ -2358,10 +2358,10 @@ static void do_unassigned_access(target_phys_addr_t addr, int is_write,
#endif
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUSPARCState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
- CPUState *saved_env;
+ CPUSPARCState *saved_env;
saved_env = env;
env = env1;
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 235b088..eb4d87f 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -6,7 +6,7 @@
void cpu_save(QEMUFile *f, void *opaque)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
int i;
uint32_t tmp;
@@ -111,7 +111,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
int i;
uint32_t tmp;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index bdff1c3..11fb9f5 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -25,7 +25,7 @@
#if defined(CONFIG_USER_ONLY)
-int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
+int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
int mmu_idx)
{
if (rw & 2) {
@@ -76,7 +76,7 @@ static const int perm_table[2][8] = {
}
};
-static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
@@ -198,7 +198,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
}
/* Perform address translation */
-int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
int mmu_idx)
{
target_phys_addr_t paddr;
@@ -244,7 +244,7 @@ int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
}
}
-target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
+target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
{
target_phys_addr_t pde_ptr;
uint32_t pde;
@@ -310,7 +310,7 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
return 0;
}
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
{
target_ulong va, va1, va2;
unsigned int n, m, o;
@@ -354,7 +354,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
* reads (and only reads) in stack frames as if windows were flushed. We assume
* that the sparc ABI is followed.
*/
-int target_memory_rw_debug(CPUState *env, target_ulong addr,
+int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int i;
@@ -479,7 +479,7 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
return 0;
}
-static int get_physical_address_data(CPUState *env,
+static int get_physical_address_data(CPUSPARCState *env,
target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int mmu_idx)
{
@@ -598,7 +598,7 @@ static int get_physical_address_data(CPUState *env,
return 1;
}
-static int get_physical_address_code(CPUState *env,
+static int get_physical_address_code(CPUSPARCState *env,
target_phys_addr_t *physical, int *prot,
target_ulong address, int mmu_idx)
{
@@ -667,7 +667,7 @@ static int get_physical_address_code(CPUState *env,
return 1;
}
-static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
@@ -701,7 +701,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
}
/* Perform address translation */
-int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
int mmu_idx)
{
target_ulong virt_addr, vaddr;
@@ -727,7 +727,7 @@ int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
return 1;
}
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
{
unsigned int i;
const char *mask;
@@ -813,7 +813,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
#endif /* TARGET_SPARC64 */
-static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
+static int cpu_sparc_get_phys_page(CPUSPARCState *env, target_phys_addr_t *phys,
target_ulong addr, int rw, int mmu_idx)
{
target_ulong page_size;
@@ -824,7 +824,7 @@ static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
}
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
+target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
int mmu_idx)
{
target_phys_addr_t phys_addr;
@@ -836,7 +836,7 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
}
#endif
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr)
{
target_phys_addr_t phys_addr;
int mmu_idx = cpu_mmu_index(env);
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 02b660d..1aff125 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -54,11 +54,11 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUSPARCState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
int ret;
- CPUState *saved_env;
+ CPUSPARCState *saved_env;
saved_env = env;
env = env1;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index d261112..ef176e9 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2209,7 +2209,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
/* calculate offset to current trap state from env->ts, reuse r_tl */
tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
- tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts));
+ tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
/* tsptr = env->ts[env->tl & MAXTL_MASK] */
{
@@ -2600,7 +2600,7 @@ static void disas_sparc_insn(DisasContext * dc)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, tick));
+ offsetof(CPUSPARCState, tick));
gen_helper_tick_get_count(cpu_dst, r_tickptr);
tcg_temp_free_ptr(r_tickptr);
gen_movl_TN_reg(rd, cpu_dst);
@@ -2639,7 +2639,7 @@ static void disas_sparc_insn(DisasContext * dc)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, stick));
+ offsetof(CPUSPARCState, stick));
gen_helper_tick_get_count(cpu_dst, r_tickptr);
tcg_temp_free_ptr(r_tickptr);
gen_movl_TN_reg(rd, cpu_dst);
@@ -2752,7 +2752,7 @@ static void disas_sparc_insn(DisasContext * dc)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, tick));
+ offsetof(CPUSPARCState, tick));
gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
gen_movl_TN_reg(rd, cpu_tmp0);
tcg_temp_free_ptr(r_tickptr);
@@ -3712,7 +3712,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, tick));
+ offsetof(CPUSPARCState, tick));
gen_helper_tick_set_limit(r_tickptr,
cpu_tick_cmpr);
tcg_temp_free_ptr(r_tickptr);
@@ -3730,7 +3730,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, stick));
+ offsetof(CPUSPARCState, stick));
gen_helper_tick_set_count(r_tickptr,
cpu_dst);
tcg_temp_free_ptr(r_tickptr);
@@ -3748,7 +3748,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, stick));
+ offsetof(CPUSPARCState, stick));
gen_helper_tick_set_limit(r_tickptr,
cpu_stick_cmpr);
tcg_temp_free_ptr(r_tickptr);
@@ -3857,7 +3857,7 @@ static void disas_sparc_insn(DisasContext * dc)
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, tick));
+ offsetof(CPUSPARCState, tick));
gen_helper_tick_set_count(r_tickptr,
cpu_tmp0);
tcg_temp_free_ptr(r_tickptr);
@@ -3985,7 +3985,7 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
r_tickptr = tcg_temp_new_ptr();
tcg_gen_ld_ptr(r_tickptr, cpu_env,
- offsetof(CPUState, hstick));
+ offsetof(CPUSPARCState, hstick));
gen_helper_tick_set_limit(r_tickptr,
cpu_hstick_cmpr);
tcg_temp_free_ptr(r_tickptr);
@@ -5045,13 +5045,13 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x25: /* stfsr, V9 stxfsr */
#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
- tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
+ tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUSPARCState, fsr));
if (rd == 1)
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
else
tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
#else
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fsr));
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
#endif
break;
@@ -5403,75 +5403,75 @@ void gen_intermediate_code_init(CPUSPARCState *env)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
- offsetof(CPUState, regwptr),
+ offsetof(CPUSPARCState, regwptr),
"regwptr");
#ifdef TARGET_SPARC64
- cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc),
+ cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc),
"xcc");
- cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi),
+ cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi),
"asi");
- cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs),
+ cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs),
"fprs");
- cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr),
+ cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr),
"gsr");
cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, tick_cmpr),
+ offsetof(CPUSPARCState, tick_cmpr),
"tick_cmpr");
cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, stick_cmpr),
+ offsetof(CPUSPARCState, stick_cmpr),
"stick_cmpr");
cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, hstick_cmpr),
+ offsetof(CPUSPARCState, hstick_cmpr),
"hstick_cmpr");
- cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp),
+ cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp),
"hintp");
- cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba),
+ cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba),
"htba");
- cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver),
+ cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver),
"hver");
cpu_ssr = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, ssr), "ssr");
+ offsetof(CPUSPARCState, ssr), "ssr");
cpu_ver = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, version), "ver");
+ offsetof(CPUSPARCState, version), "ver");
cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, softint),
+ offsetof(CPUSPARCState, softint),
"softint");
#else
- cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim),
+ cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim),
"wim");
#endif
- cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond),
+ cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond),
"cond");
- cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
+ cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src),
"cc_src");
cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, cc_src2),
+ offsetof(CPUSPARCState, cc_src2),
"cc_src2");
- cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
+ cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst),
"cc_dst");
- cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
+ cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op),
"cc_op");
- cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr),
+ cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr),
"psr");
- cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr),
+ cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr),
"fsr");
- cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc),
+ cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc),
"pc");
- cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc),
+ cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc),
"npc");
- cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
+ cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
#ifndef CONFIG_USER_ONLY
- cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr),
+ cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr),
"tbr");
#endif
for (i = 1; i < 8; i++) {
cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, gregs[i]),
+ offsetof(CPUSPARCState, gregs[i]),
gregnames[i]);
}
for (i = 0; i < TARGET_DPREGS; i++) {
cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, fpr[i]),
+ offsetof(CPUSPARCState, fpr[i]),
fregnames[i]);
}
@@ -5482,7 +5482,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
}
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos)
{
target_ulong npc;
env->pc = gen_opc_pc[pc_pos];
diff --git a/target-sparc/win_helper.c b/target-sparc/win_helper.c
index a68c649..3e82eb7 100644
--- a/target-sparc/win_helper.c
+++ b/target-sparc/win_helper.c
@@ -33,7 +33,7 @@ static inline void memcpy32(target_ulong *dst, const target_ulong *src)
dst[7] = src[7];
}
-void cpu_set_cwp(CPUState *env, int new_cwp)
+void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
{
/* put the modified wrap registers at their proper location */
if (env->cwp == env->nwindows - 1) {
@@ -48,7 +48,7 @@ void cpu_set_cwp(CPUState *env, int new_cwp)
env->regwptr = env->regbase + (new_cwp * 16);
}
-target_ulong cpu_get_psr(CPUState *env)
+target_ulong cpu_get_psr(CPUSPARCState *env)
{
helper_compute_psr(env);
@@ -64,7 +64,7 @@ target_ulong cpu_get_psr(CPUState *env)
#endif
}
-void cpu_put_psr(CPUState *env, target_ulong val)
+void cpu_put_psr(CPUSPARCState *env, target_ulong val)
{
env->psr = val & PSR_ICC;
#if !defined(TARGET_SPARC64)
@@ -83,7 +83,7 @@ void cpu_put_psr(CPUState *env, target_ulong val)
env->cc_op = CC_OP_FLAGS;
}
-int cpu_cwp_inc(CPUState *env, int cwp)
+int cpu_cwp_inc(CPUSPARCState *env, int cwp)
{
if (unlikely(cwp >= env->nwindows)) {
cwp -= env->nwindows;
@@ -91,7 +91,7 @@ int cpu_cwp_inc(CPUState *env, int cwp)
return cwp;
}
-int cpu_cwp_dec(CPUState *env, int cwp)
+int cpu_cwp_dec(CPUSPARCState *env, int cwp)
{
if (unlikely(cwp < 0)) {
cwp += env->nwindows;
@@ -100,7 +100,7 @@ int cpu_cwp_dec(CPUState *env, int cwp)
}
#ifndef TARGET_SPARC64
-void helper_rett(CPUState *env)
+void helper_rett(CPUSPARCState *env)
{
unsigned int cwp;
@@ -119,7 +119,7 @@ void helper_rett(CPUState *env)
/* XXX: use another pointer for %iN registers to avoid slow wrapping
handling ? */
-void helper_save(CPUState *env)
+void helper_save(CPUSPARCState *env)
{
uint32_t cwp;
@@ -130,7 +130,7 @@ void helper_save(CPUState *env)
cpu_set_cwp(env, cwp);
}
-void helper_restore(CPUState *env)
+void helper_restore(CPUSPARCState *env)
{
uint32_t cwp;
@@ -141,7 +141,7 @@ void helper_restore(CPUState *env)
cpu_set_cwp(env, cwp);
}
-void helper_wrpsr(CPUState *env, target_ulong new_psr)
+void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
{
if ((new_psr & PSR_CWP) >= env->nwindows) {
helper_raise_exception(env, TT_ILL_INSN);
@@ -150,7 +150,7 @@ void helper_wrpsr(CPUState *env, target_ulong new_psr)
}
}
-target_ulong helper_rdpsr(CPUState *env)
+target_ulong helper_rdpsr(CPUSPARCState *env)
{
return cpu_get_psr(env);
}
@@ -158,7 +158,7 @@ target_ulong helper_rdpsr(CPUState *env)
#else
/* XXX: use another pointer for %iN registers to avoid slow wrapping
handling ? */
-void helper_save(CPUState *env)
+void helper_save(CPUSPARCState *env)
{
uint32_t cwp;
@@ -180,7 +180,7 @@ void helper_save(CPUState *env)
}
}
-void helper_restore(CPUState *env)
+void helper_restore(CPUSPARCState *env)
{
uint32_t cwp;
@@ -197,7 +197,7 @@ void helper_restore(CPUState *env)
}
}
-void helper_flushw(CPUState *env)
+void helper_flushw(CPUSPARCState *env)
{
if (env->cansave != env->nwindows - 2) {
helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
@@ -207,7 +207,7 @@ void helper_flushw(CPUState *env)
}
}
-void helper_saved(CPUState *env)
+void helper_saved(CPUSPARCState *env)
{
env->cansave++;
if (env->otherwin == 0) {
@@ -217,7 +217,7 @@ void helper_saved(CPUState *env)
}
}
-void helper_restored(CPUState *env)
+void helper_restored(CPUSPARCState *env)
{
env->canrestore++;
if (env->cleanwin < env->nwindows - 1) {
@@ -230,7 +230,7 @@ void helper_restored(CPUState *env)
}
}
-target_ulong cpu_get_ccr(CPUState *env)
+target_ulong cpu_get_ccr(CPUSPARCState *env)
{
target_ulong psr;
@@ -239,19 +239,19 @@ target_ulong cpu_get_ccr(CPUState *env)
return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
}
-void cpu_put_ccr(CPUState *env, target_ulong val)
+void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
{
env->xcc = (val >> 4) << 20;
env->psr = (val & 0xf) << 20;
CC_OP = CC_OP_FLAGS;
}
-target_ulong cpu_get_cwp64(CPUState *env)
+target_ulong cpu_get_cwp64(CPUSPARCState *env)
{
return env->nwindows - 1 - env->cwp;
}
-void cpu_put_cwp64(CPUState *env, int cwp)
+void cpu_put_cwp64(CPUSPARCState *env, int cwp)
{
if (unlikely(cwp >= env->nwindows || cwp < 0)) {
cwp %= env->nwindows;
@@ -259,29 +259,29 @@ void cpu_put_cwp64(CPUState *env, int cwp)
cpu_set_cwp(env, env->nwindows - 1 - cwp);
}
-target_ulong helper_rdccr(CPUState *env)
+target_ulong helper_rdccr(CPUSPARCState *env)
{
return cpu_get_ccr(env);
}
-void helper_wrccr(CPUState *env, target_ulong new_ccr)
+void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
{
cpu_put_ccr(env, new_ccr);
}
/* CWP handling is reversed in V9, but we still use the V8 register
order. */
-target_ulong helper_rdcwp(CPUState *env)
+target_ulong helper_rdcwp(CPUSPARCState *env)
{
return cpu_get_cwp64(env);
}
-void helper_wrcwp(CPUState *env, target_ulong new_cwp)
+void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
{
cpu_put_cwp64(env, new_cwp);
}
-static inline uint64_t *get_gregset(CPUState *env, uint32_t pstate)
+static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
{
switch (pstate) {
default:
@@ -298,7 +298,7 @@ static inline uint64_t *get_gregset(CPUState *env, uint32_t pstate)
}
}
-void cpu_change_pstate(CPUState *env, uint32_t new_pstate)
+void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
{
uint32_t pstate_regs, new_pstate_regs;
uint64_t *src, *dst;
@@ -325,7 +325,7 @@ void cpu_change_pstate(CPUState *env, uint32_t new_pstate)
env->pstate = new_pstate;
}
-void helper_wrpstate(CPUState *env, target_ulong new_state)
+void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
{
cpu_change_pstate(env, new_state & 0xf3f);
@@ -336,7 +336,7 @@ void helper_wrpstate(CPUState *env, target_ulong new_state)
#endif
}
-void helper_wrpil(CPUState *env, target_ulong new_pil)
+void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
{
#if !defined(CONFIG_USER_ONLY)
trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);
@@ -349,7 +349,7 @@ void helper_wrpil(CPUState *env, target_ulong new_pil)
#endif
}
-void helper_done(CPUState *env)
+void helper_done(CPUSPARCState *env)
{
trap_state *tsptr = cpu_tsptr(env);
@@ -370,7 +370,7 @@ void helper_done(CPUState *env)
#endif
}
-void helper_retry(CPUState *env)
+void helper_retry(CPUSPARCState *env)
{
trap_state *tsptr = cpu_tsptr(env);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (23 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: " Andreas Färber
` (18 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUUniCore32State/g" target-unicore32/*.[hc]
sed -i "s/#define CPUUniCore32State/#define CPUState/" target-unicore32/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu.h | 24 ++++++++--------
target-unicore32/helper.c | 62 +++++++++++++++++++++---------------------
target-unicore32/op_helper.c | 8 +++---
target-unicore32/translate.c | 60 ++++++++++++++++++++--------------------
4 files changed, 77 insertions(+), 77 deletions(-)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 923db05..171f0a9 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -92,9 +92,9 @@ typedef struct CPUUniCore32State {
#define UC32_EXCP_TRAP (ASR_MODE_TRAP)
/* Return the current ASR value. */
-target_ulong cpu_asr_read(CPUState *env1);
+target_ulong cpu_asr_read(CPUUniCore32State *env1);
/* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
-void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask);
+void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
/* UniCore-F64 system registers. */
#define UC32_UCF64_FPSCR (31)
@@ -128,10 +128,10 @@ void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask);
#define cpu_signal_handler uc32_cpu_signal_handler
#define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault
-CPUState *uc32_cpu_init(const char *cpu_model);
-int uc32_cpu_exec(CPUState *s);
+CPUUniCore32State *uc32_cpu_init(const char *cpu_model);
+int uc32_cpu_exec(CPUUniCore32State *s);
int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
-int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
int mmu_idx);
#define CPU_SAVE_VERSION 2
@@ -140,12 +140,12 @@ int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index(CPUState *env)
+static inline int cpu_mmu_index(CPUUniCore32State *env)
{
return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
}
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUUniCore32State *env, target_ulong newsp)
{
if (newsp) {
env->regs[29] = newsp;
@@ -153,7 +153,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->regs[0] = 0;
}
-static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
+static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls)
{
env->regs[16] = newtls;
}
@@ -161,12 +161,12 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
#include "cpu-all.h"
#include "exec-all.h"
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
{
env->regs[31] = tb->pc;
}
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->regs[31];
@@ -178,10 +178,10 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
void uc32_translate_init(void);
-void do_interrupt(CPUState *);
+void do_interrupt(CPUUniCore32State *);
void switch_mode(CPUUniCore32State *, int);
-static inline bool cpu_has_work(CPUState *env)
+static inline bool cpu_has_work(CPUUniCore32State *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index ee7f82b..6af492d 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -11,7 +11,7 @@
#include "helper.h"
#include "host-utils.h"
-static inline void set_feature(CPUState *env, int feature)
+static inline void set_feature(CPUUniCore32State *env, int feature)
{
env->features |= feature;
}
@@ -43,13 +43,13 @@ static uint32_t uc32_cpu_find_by_name(const char *name)
return id;
}
-CPUState *uc32_cpu_init(const char *cpu_model)
+CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
- CPUState *env;
+ CPUUniCore32State *env;
uint32_t id;
static int inited = 1;
- env = g_malloc0(sizeof(CPUState));
+ env = g_malloc0(sizeof(CPUUniCore32State));
cpu_exec_init(env);
id = uc32_cpu_find_by_name(cpu_model);
@@ -94,12 +94,12 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUUniCore32State *env)
{
env->exception_index = -1;
}
-int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
int mmu_idx)
{
env->exception_index = UC32_EXCP_TRAP;
@@ -108,44 +108,44 @@ int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
}
/* These should probably raise undefined insn exceptions. */
-void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
+void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
int op1 = (insn >> 8) & 0xf;
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
return;
}
-uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
+uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
{
int op1 = (insn >> 8) & 0xf;
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
return 0;
}
-void HELPER(set_cp0)(CPUState *env, uint32_t insn, uint32_t val)
+void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
cpu_abort(env, "cp0 insn %08x\n", insn);
}
-uint32_t HELPER(get_cp0)(CPUState *env, uint32_t insn)
+uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
{
cpu_abort(env, "cp0 insn %08x\n", insn);
return 0;
}
-void switch_mode(CPUState *env, int mode)
+void switch_mode(CPUUniCore32State *env, int mode)
{
if (mode != ASR_MODE_USER) {
cpu_abort(env, "Tried to switch out of user mode\n");
}
}
-void HELPER(set_r29_banked)(CPUState *env, uint32_t mode, uint32_t val)
+void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
{
cpu_abort(env, "banked r29 write\n");
}
-uint32_t HELPER(get_r29_banked)(CPUState *env, uint32_t mode)
+uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
{
cpu_abort(env, "banked r29 read\n");
return 0;
@@ -178,7 +178,7 @@ static inline int ucf64_exceptbits_from_host(int host_bits)
return target_bits;
}
-uint32_t HELPER(ucf64_get_fpscr)(CPUState *env)
+uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
{
int i;
uint32_t fpscr;
@@ -212,7 +212,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
return host_bits;
}
-void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val)
+void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
{
int i;
uint32_t changed;
@@ -246,42 +246,42 @@ void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val)
set_float_exception_flags(i, &env->ucf64.fp_status);
}
-float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUState *env)
+float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
{
return float32_add(a, b, &env->ucf64.fp_status);
}
-float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUState *env)
+float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
{
return float64_add(a, b, &env->ucf64.fp_status);
}
-float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUState *env)
+float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
{
return float32_sub(a, b, &env->ucf64.fp_status);
}
-float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUState *env)
+float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
{
return float64_sub(a, b, &env->ucf64.fp_status);
}
-float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUState *env)
+float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
{
return float32_mul(a, b, &env->ucf64.fp_status);
}
-float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUState *env)
+float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
{
return float64_mul(a, b, &env->ucf64.fp_status);
}
-float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUState *env)
+float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
{
return float32_div(a, b, &env->ucf64.fp_status);
}
-float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUState *env)
+float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
{
return float64_div(a, b, &env->ucf64.fp_status);
}
@@ -307,7 +307,7 @@ float64 HELPER(ucf64_absd)(float64 a)
}
/* XXX: check quiet/signaling case */
-void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env)
+void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
{
int flag;
flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
@@ -355,7 +355,7 @@ void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env)
| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}
-void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUState *env)
+void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
{
int flag;
flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
@@ -449,34 +449,34 @@ static inline uint64_t ucf64_dtoi(float64 d)
}
/* Integer to float conversion. */
-float32 HELPER(ucf64_si2sf)(float32 x, CPUState *env)
+float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
{
return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
}
-float64 HELPER(ucf64_si2df)(float32 x, CPUState *env)
+float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
{
return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
}
/* Float to integer conversion. */
-float32 HELPER(ucf64_sf2si)(float32 x, CPUState *env)
+float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
{
return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
}
-float32 HELPER(ucf64_df2si)(float64 x, CPUState *env)
+float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
{
return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
}
/* floating point conversion */
-float64 HELPER(ucf64_sf2df)(float32 x, CPUState *env)
+float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
{
return float32_to_float64(x, &env->ucf64.fp_status);
}
-float32 HELPER(ucf64_df2sf)(float64 x, CPUState *env)
+float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
{
return float64_to_float32(x, &env->ucf64.fp_status);
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 6cf5255..638a020 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -28,9 +28,9 @@ static target_ulong asr_read(void)
(env->CF << 29) | ((env->VF & 0x80000000) >> 3);
}
-target_ulong cpu_asr_read(CPUState *env1)
+target_ulong cpu_asr_read(CPUUniCore32State *env1)
{
- CPUState *saved_env;
+ CPUUniCore32State *saved_env;
target_ulong ret;
saved_env = env;
@@ -61,9 +61,9 @@ static void asr_write(target_ulong val, target_ulong mask)
env->uncached_asr = (env->uncached_asr & ~mask) | (val & mask);
}
-void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask)
+void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
{
- CPUState *saved_env;
+ CPUUniCore32State *saved_env;
saved_env = env;
env = env1;
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 4d0aa43..3b3ba16 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -64,7 +64,7 @@ void uc32_translate_init(void)
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[i]), regnames[i]);
+ offsetof(CPUUniCore32State, regs[i]), regnames[i]);
}
#define GEN_HELPER 2
@@ -94,7 +94,7 @@ static inline TCGv load_cpu_offset(int offset)
return tmp;
}
-#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
+#define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
static inline void store_cpu_offset(TCGv var, int offset)
{
@@ -103,7 +103,7 @@ static inline void store_cpu_offset(TCGv var, int offset)
}
#define store_cpu_field(var, name) \
- store_cpu_offset(var, offsetof(CPUState, name))
+ store_cpu_offset(var, offsetof(CPUUniCore32State, name))
/* Set a variable to the value of a CPU register. */
static void load_reg_var(DisasContext *s, TCGv var, int reg)
@@ -223,7 +223,7 @@ static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
return tmp1;
}
-#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
+#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
/* Set CF to the top bit of var. */
static void gen_set_CF_bit31(TCGv var)
@@ -237,8 +237,8 @@ static void gen_set_CF_bit31(TCGv var)
/* Set N and Z flags from var. */
static inline void gen_logic_CC(TCGv var)
{
- tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
- tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
+ tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF));
+ tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF));
}
/* dest = T0 + T1 + CF. */
@@ -634,10 +634,10 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
static inline long ucf64_reg_offset(int reg)
{
if (reg & 1) {
- return offsetof(CPUState, ucf64.regs[reg >> 1])
+ return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
+ offsetof(CPU_DoubleU, l.upper);
} else {
- return offsetof(CPUState, ucf64.regs[reg >> 1])
+ return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
+ offsetof(CPU_DoubleU, l.lower);
}
}
@@ -646,7 +646,7 @@ static inline long ucf64_reg_offset(int reg)
#define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
/* UniCore-F64 single load/store I_offset */
-static void do_ucf64_ldst_i(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
int offset;
TCGv tmp;
@@ -692,7 +692,7 @@ static void do_ucf64_ldst_i(CPUState *env, DisasContext *s, uint32_t insn)
}
/* UniCore-F64 load/store multiple words */
-static void do_ucf64_ldst_m(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
unsigned int i;
int j, n, freg;
@@ -777,7 +777,7 @@ static void do_ucf64_ldst_m(CPUState *env, DisasContext *s, uint32_t insn)
}
/* UniCore-F64 mrc/mcr */
-static void do_ucf64_trans(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
TCGv tmp;
@@ -841,7 +841,7 @@ static void do_ucf64_trans(CPUState *env, DisasContext *s, uint32_t insn)
}
/* UniCore-F64 convert instructions */
-static void do_ucf64_fcvt(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
@@ -907,7 +907,7 @@ static void do_ucf64_fcvt(CPUState *env, DisasContext *s, uint32_t insn)
}
/* UniCore-F64 compare instructions */
-static void do_ucf64_fcmp(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
if (UCOP_SET(25)) {
ILLEGAL;
@@ -985,7 +985,7 @@ static void do_ucf64_fcmp(CPUState *env, DisasContext *s, uint32_t insn)
} while (0)
/* UniCore-F64 data processing */
-static void do_ucf64_datap(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
@@ -1018,7 +1018,7 @@ static void do_ucf64_datap(CPUState *env, DisasContext *s, uint32_t insn)
}
/* Disassemble an F64 instruction */
-static void disas_ucf64_insn(CPUState *env, DisasContext *s, uint32_t insn)
+static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
if (!UCOP_SET(29)) {
if (UCOP_SET(26)) {
@@ -1123,7 +1123,7 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
s->is_jmp = DISAS_UPDATE;
}
-static void disas_coproc_insn(CPUState *env, DisasContext *s, uint32_t insn)
+static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
switch (UCOP_CPNUM) {
case 2:
@@ -1168,7 +1168,7 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
}
/* data processing instructions */
-static void do_datap(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
TCGv tmp;
TCGv tmp2;
@@ -1359,7 +1359,7 @@ static void do_datap(CPUState *env, DisasContext *s, uint32_t insn)
}
/* multiply */
-static void do_mult(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
TCGv tmp;
TCGv tmp2;
@@ -1399,7 +1399,7 @@ static void do_mult(CPUState *env, DisasContext *s, uint32_t insn)
}
/* miscellaneous instructions */
-static void do_misc(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
unsigned int val;
TCGv tmp;
@@ -1475,7 +1475,7 @@ static void do_misc(CPUState *env, DisasContext *s, uint32_t insn)
}
/* load/store I_offset and R_offset */
-static void do_ldst_ir(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
unsigned int i;
TCGv tmp;
@@ -1524,7 +1524,7 @@ static void do_ldst_ir(CPUState *env, DisasContext *s, uint32_t insn)
}
/* SWP instruction */
-static void do_swap(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
TCGv addr;
TCGv tmp;
@@ -1551,7 +1551,7 @@ static void do_swap(CPUState *env, DisasContext *s, uint32_t insn)
}
/* load/store hw/sb */
-static void do_ldst_hwsb(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
TCGv addr;
TCGv tmp;
@@ -1603,7 +1603,7 @@ static void do_ldst_hwsb(CPUState *env, DisasContext *s, uint32_t insn)
}
/* load/store multiple words */
-static void do_ldst_m(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
unsigned int val, i;
int j, n, reg, user, loaded_base;
@@ -1743,7 +1743,7 @@ static void do_ldst_m(CPUState *env, DisasContext *s, uint32_t insn)
}
/* branch (and link) */
-static void do_branch(CPUState *env, DisasContext *s, uint32_t insn)
+static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
unsigned int val;
int32_t offset;
@@ -1772,7 +1772,7 @@ static void do_branch(CPUState *env, DisasContext *s, uint32_t insn)
gen_jmp(s, val);
}
-static void disas_uc32_insn(CPUState *env, DisasContext *s)
+static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
{
unsigned int insn;
@@ -1850,7 +1850,7 @@ static void disas_uc32_insn(CPUState *env, DisasContext *s)
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline void gen_intermediate_code_internal(CPUState *env,
+static inline void gen_intermediate_code_internal(CPUUniCore32State *env,
TranslationBlock *tb, int search_pc)
{
DisasContext dc1, *dc = &dc1;
@@ -2030,12 +2030,12 @@ done_generating:
}
}
-void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUUniCore32State *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
@@ -2046,7 +2046,7 @@ static const char *cpu_mode_names[16] = {
};
#define UCF64_DUMP_STATE
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -2097,7 +2097,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
#endif
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int pc_pos)
{
env->regs[31] = gen_opc_pc[pc_pos];
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (24 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState Andreas Färber
` (17 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc]
sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-xtensa/cpu.h | 44 ++++++++++++++++++++++----------------------
target-xtensa/helper.c | 40 ++++++++++++++++++++--------------------
target-xtensa/op_helper.c | 30 +++++++++++++++---------------
target-xtensa/translate.c | 22 +++++++++++-----------
4 files changed, 68 insertions(+), 68 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index fb8a727..b7723ca 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -356,27 +356,27 @@ int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node);
void do_interrupt(CPUXtensaState *s);
void check_interrupts(CPUXtensaState *s);
-void xtensa_irq_init(CPUState *env);
-void *xtensa_get_extint(CPUState *env, unsigned extint);
-void xtensa_advance_ccount(CPUState *env, uint32_t d);
-void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active);
-void xtensa_rearm_ccompare_timer(CPUState *env);
+void xtensa_irq_init(CPUXtensaState *env);
+void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
+void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
+void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
+void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-void xtensa_sync_window_from_phys(CPUState *env);
-void xtensa_sync_phys_from_window(CPUState *env);
-uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way);
-void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb,
+void xtensa_sync_window_from_phys(CPUXtensaState *env);
+void xtensa_sync_phys_from_window(CPUXtensaState *env);
+uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
+void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei);
-int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb,
+int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring);
-void xtensa_tlb_set_entry(CPUState *env, bool dtlb,
+void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
-int xtensa_get_physical_addr(CPUState *env,
+int xtensa_get_physical_addr(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access);
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
-void debug_exception_env(CPUState *new_env, uint32_t cause);
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
+void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
@@ -392,7 +392,7 @@ static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
}
-static inline int xtensa_get_cintlevel(const CPUState *env)
+static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
{
int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
@@ -401,7 +401,7 @@ static inline int xtensa_get_cintlevel(const CPUState *env)
return level;
}
-static inline int xtensa_get_ring(const CPUState *env)
+static inline int xtensa_get_ring(const CPUXtensaState *env)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
@@ -410,7 +410,7 @@ static inline int xtensa_get_ring(const CPUState *env)
}
}
-static inline int xtensa_get_cring(const CPUState *env)
+static inline int xtensa_get_cring(const CPUXtensaState *env)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
(env->sregs[PS] & PS_EXCM) == 0) {
@@ -420,7 +420,7 @@ static inline int xtensa_get_cring(const CPUState *env)
}
}
-static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env,
+static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
bool dtlb, unsigned wi, unsigned ei)
{
return dtlb ?
@@ -434,7 +434,7 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env,
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3
-static inline int cpu_mmu_index(CPUState *env)
+static inline int cpu_mmu_index(CPUXtensaState *env)
{
return xtensa_get_cring(env);
}
@@ -445,7 +445,7 @@ static inline int cpu_mmu_index(CPUState *env)
#define XTENSA_TBFLAG_DEBUG 0x10
#define XTENSA_TBFLAG_ICOUNT 0x20
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
@@ -472,12 +472,12 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
#include "cpu-all.h"
#include "exec-all.h"
-static inline int cpu_has_work(CPUState *env)
+static inline int cpu_has_work(CPUXtensaState *env)
{
return env->pending_irq_level;
}
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 077c20a..dab135c 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -33,7 +33,7 @@
#include "hw/loader.h"
#endif
-static void reset_mmu(CPUState *env);
+static void reset_mmu(CPUXtensaState *env);
void cpu_state_reset(CPUXtensaState *env)
{
@@ -57,7 +57,7 @@ void xtensa_register_core(XtensaConfigList *node)
xtensa_cores = node;
}
-static uint32_t check_hw_breakpoints(CPUState *env)
+static uint32_t check_hw_breakpoints(CPUXtensaState *env)
{
unsigned i;
@@ -72,7 +72,7 @@ static uint32_t check_hw_breakpoints(CPUState *env)
static CPUDebugExcpHandler *prev_debug_excp_handler;
-static void breakpoint_handler(CPUState *env)
+static void breakpoint_handler(CPUXtensaState *env)
{
if (env->watchpoint_hit) {
if (env->watchpoint_hit->flags & BP_CPU) {
@@ -139,7 +139,7 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
{
uint32_t paddr;
uint32_t page_size;
@@ -156,7 +156,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
return ~0;
}
-static uint32_t relocated_vector(CPUState *env, uint32_t vector)
+static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
{
if (xtensa_option_enabled(env->config,
XTENSA_OPTION_RELOCATABLE_VECTOR)) {
@@ -172,7 +172,7 @@ static uint32_t relocated_vector(CPUState *env, uint32_t vector)
* For the level-1 interrupt convert it to either user, kernel or double
* exception with the 'level-1 interrupt' exception cause.
*/
-static void handle_interrupt(CPUState *env)
+static void handle_interrupt(CPUXtensaState *env)
{
int level = env->pending_irq_level;
@@ -209,7 +209,7 @@ static void handle_interrupt(CPUState *env)
}
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUXtensaState *env)
{
if (env->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
@@ -260,7 +260,7 @@ void do_interrupt(CPUState *env)
check_interrupts(env);
}
-static void reset_tlb_mmu_all_ways(CPUState *env,
+static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
unsigned wi, ei;
@@ -273,7 +273,7 @@ static void reset_tlb_mmu_all_ways(CPUState *env,
}
}
-static void reset_tlb_mmu_ways56(CPUState *env,
+static void reset_tlb_mmu_ways56(CPUXtensaState *env,
const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
if (!tlb->varway56) {
@@ -320,7 +320,7 @@ static void reset_tlb_mmu_ways56(CPUState *env,
}
}
-static void reset_tlb_region_way0(CPUState *env,
+static void reset_tlb_region_way0(CPUXtensaState *env,
xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
unsigned ei;
@@ -334,7 +334,7 @@ static void reset_tlb_region_way0(CPUState *env,
}
}
-static void reset_mmu(CPUState *env)
+static void reset_mmu(CPUXtensaState *env)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
env->sregs[RASID] = 0x04030201;
@@ -351,7 +351,7 @@ static void reset_mmu(CPUState *env)
}
}
-static unsigned get_ring(const CPUState *env, uint8_t asid)
+static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
{
unsigned i;
for (i = 0; i < 4; ++i) {
@@ -371,7 +371,7 @@ static unsigned get_ring(const CPUState *env, uint8_t asid)
* \param pring: [out] access ring
* \return 0 if ok, exception cause code otherwise
*/
-int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb,
+int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring)
{
const xtensa_tlb *tlb = dtlb ?
@@ -458,10 +458,10 @@ static bool is_access_granted(unsigned access, int is_write)
}
}
-static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
+static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
uint32_t *wi, uint32_t *ei, uint8_t *ring);
-static int get_physical_addr_mmu(CPUState *env,
+static int get_physical_addr_mmu(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access)
{
@@ -504,7 +504,7 @@ static int get_physical_addr_mmu(CPUState *env,
return 0;
}
-static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
+static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
uint32_t *wi, uint32_t *ei, uint8_t *ring)
{
uint32_t paddr;
@@ -532,7 +532,7 @@ static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
return ret;
}
-static int get_physical_addr_region(CPUState *env,
+static int get_physical_addr_region(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access)
{
@@ -563,7 +563,7 @@ static int get_physical_addr_region(CPUState *env,
*
* \return 0 if ok, exception cause code otherwise
*/
-int xtensa_get_physical_addr(CPUState *env,
+int xtensa_get_physical_addr(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access)
{
@@ -584,7 +584,7 @@ int xtensa_get_physical_addr(CPUState *env,
}
static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
- CPUState *env, bool dtlb)
+ CPUXtensaState *env, bool dtlb)
{
unsigned wi, ei;
const xtensa_tlb *conf =
@@ -634,7 +634,7 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
}
}
-void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
{
if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index e184cf6..cdef0db 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -70,10 +70,10 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
}
}
-void tlb_fill(CPUState *env1, target_ulong vaddr, int is_write, int mmu_idx,
+void tlb_fill(CPUXtensaState *env1, target_ulong vaddr, int is_write, int mmu_idx,
void *retaddr)
{
- CPUState *saved_env = env;
+ CPUXtensaState *saved_env = env;
env = env1;
{
@@ -134,7 +134,7 @@ void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
HELPER(exception_cause)(pc, cause);
}
-void debug_exception_env(CPUState *new_env, uint32_t cause)
+void debug_exception_env(CPUXtensaState *new_env, uint32_t cause)
{
if (xtensa_get_cintlevel(new_env) < new_env->config->debug_level) {
env = new_env;
@@ -168,7 +168,7 @@ uint32_t HELPER(nsau)(uint32_t v)
return v ? clz32(v) : 32;
}
-static void copy_window_from_phys(CPUState *env,
+static void copy_window_from_phys(CPUXtensaState *env,
uint32_t window, uint32_t phys, uint32_t n)
{
assert(phys < env->config->nareg);
@@ -184,7 +184,7 @@ static void copy_window_from_phys(CPUState *env,
}
}
-static void copy_phys_from_window(CPUState *env,
+static void copy_phys_from_window(CPUXtensaState *env,
uint32_t phys, uint32_t window, uint32_t n)
{
assert(phys < env->config->nareg);
@@ -201,22 +201,22 @@ static void copy_phys_from_window(CPUState *env,
}
-static inline unsigned windowbase_bound(unsigned a, const CPUState *env)
+static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
{
return a & (env->config->nareg / 4 - 1);
}
-static inline unsigned windowstart_bit(unsigned a, const CPUState *env)
+static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
{
return 1 << windowbase_bound(a, env);
}
-void xtensa_sync_window_from_phys(CPUState *env)
+void xtensa_sync_window_from_phys(CPUXtensaState *env)
{
copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
}
-void xtensa_sync_phys_from_window(CPUState *env)
+void xtensa_sync_phys_from_window(CPUXtensaState *env)
{
copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
}
@@ -409,7 +409,7 @@ void HELPER(advance_ccount)(uint32_t d)
xtensa_advance_ccount(env, d);
}
-void HELPER(check_interrupts)(CPUState *env)
+void HELPER(check_interrupts)(CPUXtensaState *env)
{
check_interrupts(env);
}
@@ -423,7 +423,7 @@ void HELPER(wsr_rasid)(uint32_t v)
}
}
-static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way)
+static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
{
uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
@@ -445,7 +445,7 @@ static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way)
/*!
* Get bit mask for the virtual address bits translated by the TLB way
*/
-uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way)
+uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
bool varway56 = dtlb ?
@@ -482,7 +482,7 @@ uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way)
* Get bit mask for the 'VPN without index' field.
* See ISA, 4.6.5.6, data format for RxTLB0
*/
-static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way)
+static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{
if (way < 4) {
bool is32 = (dtlb ?
@@ -511,7 +511,7 @@ static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way)
* Split virtual address into VPN (with index) and entry index
* for the given TLB way
*/
-void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb,
+void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei)
{
bool varway56 = dtlb ?
@@ -647,7 +647,7 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
}
}
-void xtensa_tlb_set_entry(CPUState *env, bool dtlb,
+void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 9e8e20a..e0ff72b 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -159,18 +159,18 @@ void xtensa_translate_init(void)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, pc), "pc");
+ offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ offsetof(CPUXtensaState, regs[i]),
regnames[i]);
}
for (i = 0; i < 256; ++i) {
if (sregnames[i]) {
cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, sregs[i]),
+ offsetof(CPUXtensaState, sregs[i]),
sregnames[i]);
}
}
@@ -178,7 +178,7 @@ void xtensa_translate_init(void)
for (i = 0; i < 256; ++i) {
if (uregnames[i]) {
cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, uregs[i]),
+ offsetof(CPUXtensaState, uregs[i]),
uregnames[i]);
}
}
@@ -2493,7 +2493,7 @@ invalid_opcode:
#undef HAS_OPTION
}
-static void check_breakpoint(CPUState *env, DisasContext *dc)
+static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
{
CPUBreakpoint *bp;
@@ -2508,7 +2508,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
}
}
-static void gen_ibreak_check(CPUState *env, DisasContext *dc)
+static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
{
unsigned i;
@@ -2522,7 +2522,7 @@ static void gen_ibreak_check(CPUState *env, DisasContext *dc)
}
static void gen_intermediate_code_internal(
- CPUState *env, TranslationBlock *tb, int search_pc)
+ CPUXtensaState *env, TranslationBlock *tb, int search_pc)
{
DisasContext dc;
int insn_count = 0;
@@ -2644,17 +2644,17 @@ static void gen_intermediate_code_internal(
}
}
-void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i, j;
@@ -2692,7 +2692,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
}
}
-void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
+void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (25 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: " Andreas Färber
@ 2012-03-10 2:27 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: " Andreas Färber
` (16 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUARMState/g" arm-semi.c
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arm-semi.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arm-semi.c b/arm-semi.c
index 873518a..8debd19 100644
--- a/arm-semi.c
+++ b/arm-semi.c
@@ -108,7 +108,7 @@ static inline uint32_t set_swi_errno(TaskState *ts, uint32_t code)
return code;
}
#else
-static inline uint32_t set_swi_errno(CPUState *env, uint32_t code)
+static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code)
{
return code;
}
@@ -122,7 +122,7 @@ static target_ulong arm_semi_syscall_len;
static target_ulong syscall_err;
#endif
-static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err)
+static void arm_semi_cb(CPUARMState *env, target_ulong ret, target_ulong err)
{
#ifdef CONFIG_USER_ONLY
TaskState *ts = env->opaque;
@@ -152,7 +152,7 @@ static void arm_semi_cb(CPUState *env, target_ulong ret, target_ulong err)
}
}
-static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err)
+static void arm_semi_flen_cb(CPUARMState *env, target_ulong ret, target_ulong err)
{
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
@@ -174,7 +174,7 @@ static void arm_semi_flen_cb(CPUState *env, target_ulong ret, target_ulong err)
__arg; \
})
#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
-uint32_t do_arm_semihosting(CPUState *env)
+uint32_t do_arm_semihosting(CPUARMState *env)
{
target_ulong args;
char * s;
@@ -184,7 +184,7 @@ uint32_t do_arm_semihosting(CPUState *env)
#ifdef CONFIG_USER_ONLY
TaskState *ts = env->opaque;
#else
- CPUState *ts = env;
+ CPUARMState *ts = env;
#endif
nr = env->regs[0];
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (26 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: " Andreas Färber
` (15 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUM68KState/g" m68k-semi.c
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
m68k-semi.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/m68k-semi.c b/m68k-semi.c
index bab01ee..3bb30cd 100644
--- a/m68k-semi.c
+++ b/m68k-semi.c
@@ -104,7 +104,7 @@ static int translate_openflags(int flags)
return hf;
}
-static void translate_stat(CPUState *env, target_ulong addr, struct stat *s)
+static void translate_stat(CPUM68KState *env, target_ulong addr, struct stat *s)
{
struct m68k_gdb_stat *p;
@@ -135,7 +135,7 @@ static void translate_stat(CPUState *env, target_ulong addr, struct stat *s)
static int m68k_semi_is_fseek;
-static void m68k_semi_cb(CPUState *env, target_ulong ret, target_ulong err)
+static void m68k_semi_cb(CPUM68KState *env, target_ulong ret, target_ulong err)
{
target_ulong args;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (27 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: " Andreas Färber
` (14 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
sed -i "s/CPUState/CPUXtensaState/g" xtensa-semi.c
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
xtensa-semi.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/xtensa-semi.c b/xtensa-semi.c
index ba0e828..5754b77 100644
--- a/xtensa-semi.c
+++ b/xtensa-semi.c
@@ -55,7 +55,7 @@ enum {
SELECT_ONE_EXCEPT = 3,
};
-void HELPER(simcall)(CPUState *env)
+void HELPER(simcall)(CPUXtensaState *env)
{
uint32_t *regs = env->regs;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (28 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 31/44] arm " Andreas Färber
` (13 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/alpha_*.[hc]; do
sed -i "s/CPUState/CPUAlphaState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/alpha_dp264.c | 2 +-
hw/alpha_sys.h | 2 +-
hw/alpha_typhoon.c | 14 +++++++-------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
index ea0fd95..9eb939f 100644
--- a/hw/alpha_dp264.c
+++ b/hw/alpha_dp264.c
@@ -49,7 +49,7 @@ static void clipper_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *cpus[4];
+ CPUAlphaState *cpus[4];
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq rtc_irq;
diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h
index d54b18f..6c4ebe4 100644
--- a/hw/alpha_sys.h
+++ b/hw/alpha_sys.h
@@ -12,7 +12,7 @@
#include "irq.h"
-PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUState *[4],
+PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4],
pci_map_irq_fn);
/* alpha_pci.c. */
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index b539416..872e112 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -21,7 +21,7 @@ typedef struct TyphoonCchip {
uint64_t drir;
uint64_t dim[4];
uint32_t iic[4];
- CPUState *cpu[4];
+ CPUAlphaState *cpu[4];
} TyphoonCchip;
typedef struct TyphoonWindow {
@@ -52,7 +52,7 @@ typedef struct TyphoonState {
} TyphoonState;
/* Called when one of DRIR or DIM changes. */
-static void cpu_irq_change(CPUState *env, uint64_t req)
+static void cpu_irq_change(CPUAlphaState *env, uint64_t req)
{
/* If there are any non-masked interrupts, tell the cpu. */
if (env) {
@@ -66,7 +66,7 @@ static void cpu_irq_change(CPUState *env, uint64_t req)
static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
- CPUState *env = cpu_single_env;
+ CPUAlphaState *env = cpu_single_env;
TyphoonState *s = opaque;
uint64_t ret = 0;
@@ -347,7 +347,7 @@ static void cchip_write(void *opaque, target_phys_addr_t addr,
if ((newval ^ oldval) & 0xff0) {
int i;
for (i = 0; i < 4; ++i) {
- CPUState *env = s->cchip.cpu[i];
+ CPUAlphaState *env = s->cchip.cpu[i];
if (env) {
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
@@ -655,7 +655,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)
/* Deliver the interrupt to each CPU, considering each CPU's IIC. */
for (i = 0; i < 4; ++i) {
- CPUState *env = s->cchip.cpu[i];
+ CPUAlphaState *env = s->cchip.cpu[i];
if (env) {
uint32_t iic = s->cchip.iic[i];
@@ -693,7 +693,7 @@ static void typhoon_alarm_timer(void *opaque)
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq,
- CPUState *cpus[4], pci_map_irq_fn sys_map_irq)
+ CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq)
{
const uint64_t MB = 1024 * 1024;
const uint64_t GB = 1024 * MB;
@@ -713,7 +713,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Remember the CPUs so that we can deliver interrupts to them. */
for (i = 0; i < 4; i++) {
- CPUState *env = cpus[i];
+ CPUAlphaState *env = cpus[i];
s->cchip.cpu[i] = env;
if (env) {
env->alarm_timer = qemu_new_timer_ns(rtc_clock,
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 31/44] arm hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (29 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 32/44] cris " Andreas Färber
` (12 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c hw/strongarm.h hw/versatilepb.c hw/vexpress.c hw/xilinx_zynq.c ; do
sed -i "s/CPUState/CPUARMState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/arm-misc.h | 8 ++++----
hw/arm_boot.c | 8 ++++----
hw/arm_pic.c | 4 ++--
hw/armv7m.c | 4 ++--
hw/exynos4210.h | 2 +-
hw/highbank.c | 8 ++++----
hw/integratorcp.c | 2 +-
hw/musicpal.c | 2 +-
hw/omap.h | 2 +-
hw/pxa.h | 6 +++---
hw/pxa2xx_gpio.c | 4 ++--
hw/pxa2xx_pic.c | 4 ++--
hw/realview.c | 2 +-
hw/strongarm.h | 2 +-
hw/versatilepb.c | 2 +-
hw/vexpress.c | 4 ++--
hw/xilinx_zynq.c | 2 +-
17 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index 734bd82..2f46e21 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -16,7 +16,7 @@
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
-qemu_irq *arm_pic_init_cpu(CPUState *env);
+qemu_irq *arm_pic_init_cpu(CPUARMState *env);
/* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
@@ -50,16 +50,16 @@ struct arm_boot_info {
* perform any necessary CPU reset handling and set the PC for thei
* secondary CPUs to point at this boot blob.
*/
- void (*write_secondary_boot)(CPUState *env,
+ void (*write_secondary_boot)(CPUARMState *env,
const struct arm_boot_info *info);
- void (*secondary_cpu_reset_hook)(CPUState *env,
+ void (*secondary_cpu_reset_hook)(CPUARMState *env,
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
target_phys_addr_t entry;
};
-void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
+void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info);
/* Multiplication factor to convert from system clock ticks to qemu timer
ticks. */
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index 23b3f0a..7447f5c 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -59,7 +59,7 @@ static uint32_t smpboot[] = {
0 /* bootreg: Boot register address is held here */
};
-static void default_write_secondary(CPUState *env,
+static void default_write_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
int n;
@@ -72,7 +72,7 @@ static void default_write_secondary(CPUState *env,
info->smp_loader_start);
}
-static void default_reset_secondary(CPUState *env,
+static void default_reset_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
stl_phys_notdirty(info->smp_bootreg_addr, 0);
@@ -274,7 +274,7 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
static void do_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUARMState *env = opaque;
const struct arm_boot_info *info = env->boot_info;
cpu_state_reset(env);
@@ -300,7 +300,7 @@ static void do_cpu_reset(void *opaque)
}
}
-void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
+void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
int kernel_size;
int initrd_size;
diff --git a/hw/arm_pic.c b/hw/arm_pic.c
index a2e8a73..1094965 100644
--- a/hw/arm_pic.c
+++ b/hw/arm_pic.c
@@ -13,7 +13,7 @@
/* Input 0 is IRQ and input 1 is FIQ. */
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
- CPUState *env = (CPUState *)opaque;
+ CPUARMState *env = (CPUARMState *)opaque;
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
@@ -32,7 +32,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
}
}
-qemu_irq *arm_pic_init_cpu(CPUState *env)
+qemu_irq *arm_pic_init_cpu(CPUARMState *env)
{
return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
}
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 9cf96f4..4aac076 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque)
{
- cpu_state_reset((CPUState *)opaque);
+ cpu_state_reset((CPUARMState *)opaque);
}
/* Init CPU and memory for a v7-M based board.
@@ -160,7 +160,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUARMState *env;
DeviceState *nvic;
/* FIXME: make this local state. */
static qemu_irq pic[64];
diff --git a/hw/exynos4210.h b/hw/exynos4210.h
index e7522f8..c112e03 100644
--- a/hw/exynos4210.h
+++ b/hw/exynos4210.h
@@ -83,7 +83,7 @@ typedef struct Exynos4210Irq {
} Exynos4210Irq;
typedef struct Exynos4210State {
- CPUState * env[EXYNOS4210_NCPUS];
+ CPUARMState * env[EXYNOS4210_NCPUS];
Exynos4210Irq irqs;
qemu_irq *irq_table;
diff --git a/hw/highbank.c b/hw/highbank.c
index 489c00e..906eed5 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -37,12 +37,12 @@
/* Board init. */
static void highbank_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUARMState *env = opaque;
env->cp15.c15_config_base_address = GIC_BASE_ADDR;
}
-static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
+static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
int n;
uint32_t smpboot[] = {
@@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}
-static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
+static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
switch (info->nb_cpus) {
case 4:
@@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 5b06c81..9bdb9e6 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUARMState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 187a1ae..c9f845a 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUARMState *env;
qemu_irq *cpu_pic;
qemu_irq pic[32];
DeviceState *dev;
diff --git a/hw/omap.h b/hw/omap.h
index 60fa34c..63ef847 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -813,7 +813,7 @@ struct omap_mpu_state_s {
omap3630,
} mpu_model;
- CPUState *env;
+ CPUARMState *env;
qemu_irq *drq;
diff --git a/hw/pxa.h b/hw/pxa.h
index e778739..025be34 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -65,11 +65,11 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env);
/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, DeviceState *pic, int lines);
+ CPUARMState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
@@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;
typedef struct {
- CPUState *env;
+ CPUARMState *env;
DeviceState *pic;
qemu_irq reset;
MemoryRegion sdram;
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index d5f5716..09a408b 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo {
qemu_irq irq0, irq1, irqX;
int lines;
int ncpu;
- CPUState *cpu_env;
+ CPUARMState *cpu_env;
/* XXX: GNU C vectors are more suitable */
uint32_t ilevel[PXA2XX_GPIO_BANKS];
@@ -249,7 +249,7 @@ static const MemoryRegionOps pxa_gpio_ops = {
};
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, DeviceState *pic, int lines)
+ CPUARMState *env, DeviceState *pic, int lines)
{
DeviceState *dev;
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index 6b2bdb0..a806b80 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -34,7 +34,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
- CPUState *cpu_env;
+ CPUARMState *cpu_env;
uint32_t int_enabled[2];
uint32_t int_pending[2];
uint32_t is_fiq[2];
@@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
return 0;
}
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env)
{
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
diff --git a/hw/realview.c b/hw/realview.c
index ae1bbcd..9f31973 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -129,7 +129,7 @@ static void realview_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
enum realview_board_type board_type)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
diff --git a/hw/strongarm.h b/hw/strongarm.h
index 684f61b..02acac3 100644
--- a/hw/strongarm.h
+++ b/hw/strongarm.h
@@ -53,7 +53,7 @@ enum {
};
typedef struct {
- CPUState *env;
+ CPUARMState *env;
MemoryRegion sdram;
DeviceState *pic;
DeviceState *gpio;
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index b9102f4..3cb1d2d 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -168,7 +168,7 @@ static void versatile_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
int board_id)
{
- CPUState *env;
+ CPUARMState *env;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_pic;
diff --git a/hw/vexpress.c b/hw/vexpress.c
index b9aafec..18d87ac 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -159,7 +159,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *lowram = g_new(MemoryRegion, 1);
@@ -259,7 +259,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
qemu_irq *pic, uint32_t *proc_id)
{
int n;
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index ea13e8c..7290c64 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -50,7 +50,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 32/44] cris hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (30 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 31/44] arm " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 33/44] i386 " Andreas Färber
` (11 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/cris-boot.[hc] hw/cris_pic_cpu.c hw/axis_dev88.c hw/etraxfs.h hw/etraxfs_ser.c; do
sed -i "s/CPUState/CPUCRISState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/axis_dev88.c | 2 +-
hw/cris-boot.c | 4 ++--
hw/cris-boot.h | 2 +-
hw/cris_pic_cpu.c | 4 ++--
hw/etraxfs.h | 2 +-
hw/etraxfs_ser.c | 4 ++--
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index c9301fd..2304e35 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -247,7 +247,7 @@ void axisdev88_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUCRISState *env;
DeviceState *dev;
SysBusDevice *s;
DriveInfo *nand;
diff --git a/hw/cris-boot.c b/hw/cris-boot.c
index ade517d..ca6c52f 100644
--- a/hw/cris-boot.c
+++ b/hw/cris-boot.c
@@ -29,7 +29,7 @@
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUCRISState *env = opaque;
struct cris_load_info *li;
li = env->load_info;
@@ -60,7 +60,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x80000000LL;
}
-void cris_load_image(CPUState *env, struct cris_load_info *li)
+void cris_load_image(CPUCRISState *env, struct cris_load_info *li)
{
uint64_t entry, high;
int kcmdline_len;
diff --git a/hw/cris-boot.h b/hw/cris-boot.h
index e9caf8d..ecb9779 100644
--- a/hw/cris-boot.h
+++ b/hw/cris-boot.h
@@ -8,4 +8,4 @@ struct cris_load_info
target_phys_addr_t entry;
};
-void cris_load_image(CPUState *env, struct cris_load_info *li);
+void cris_load_image(CPUCRISState *env, struct cris_load_info *li);
diff --git a/hw/cris_pic_cpu.c b/hw/cris_pic_cpu.c
index 06ae484..3da0e86 100644
--- a/hw/cris_pic_cpu.c
+++ b/hw/cris_pic_cpu.c
@@ -30,7 +30,7 @@
static void cris_pic_cpu_handler(void *opaque, int irq, int level)
{
- CPUState *env = (CPUState *)opaque;
+ CPUCRISState *env = (CPUCRISState *)opaque;
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level)
@@ -39,7 +39,7 @@ static void cris_pic_cpu_handler(void *opaque, int irq, int level)
cpu_reset_interrupt(env, type);
}
-qemu_irq *cris_pic_init_cpu(CPUState *env)
+qemu_irq *cris_pic_init_cpu(CPUCRISState *env)
{
return qemu_allocate_irqs(cris_pic_cpu_handler, env, 2);
}
diff --git a/hw/etraxfs.h b/hw/etraxfs.h
index 24e8fd8..c62f94b 100644
--- a/hw/etraxfs.h
+++ b/hw/etraxfs.h
@@ -25,7 +25,7 @@
#include "net.h"
#include "etraxfs_dma.h"
-qemu_irq *cris_pic_init_cpu(CPUState *env);
+qemu_irq *cris_pic_init_cpu(CPUCRISState *env);
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
index cecd819..5f16b17 100644
--- a/hw/etraxfs_ser.c
+++ b/hw/etraxfs_ser.c
@@ -78,7 +78,7 @@ static uint64_t
ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct etrax_serial *s = opaque;
- D(CPUState *env = s->env);
+ D(CPUCRISState *env = s->env);
uint32_t r = 0;
addr >>= 2;
@@ -116,7 +116,7 @@ ser_write(void *opaque, target_phys_addr_t addr,
struct etrax_serial *s = opaque;
uint32_t value = val64;
unsigned char ch = val64;
- D(CPUState *env = s->env);
+ D(CPUCRISState *env = s->env);
D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
addr >>= 2;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 33/44] i386 hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (31 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 32/44] cris " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 34/44] lm32 " Andreas Färber
` (10 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c hw/xen_machine_pv.c; do
sed -i "s/CPUState/CPUX86State/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/apic.h | 2 +-
hw/kvm/apic.c | 2 +-
hw/kvmvapic.c | 22 +++++++++++-----------
hw/pc.c | 20 ++++++++++----------
hw/vmport.c | 12 ++++++------
hw/xen_machine_pv.c | 2 +-
6 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/hw/apic.h b/hw/apic.h
index d6d6d44..62179ce 100644
--- a/hw/apic.h
+++ b/hw/apic.h
@@ -22,7 +22,7 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
TPRAccess access);
/* pc.c */
-int cpu_is_bsp(CPUState *env);
+int cpu_is_bsp(CPUX86State *env);
DeviceState *cpu_get_current_apic(void);
#endif
diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c
index 9ca68f8..ffe7a52 100644
--- a/hw/kvm/apic.c
+++ b/hw/kvm/apic.c
@@ -124,7 +124,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s)
static void do_inject_external_nmi(void *data)
{
APICCommonState *s = data;
- CPUState *env = s->cpu_env;
+ CPUX86State *env = s->cpu_env;
uint32_t lvt;
int ret;
diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c
index 36ccfbc..c8c1c86 100644
--- a/hw/kvmvapic.c
+++ b/hw/kvmvapic.c
@@ -142,7 +142,7 @@ static void update_guest_rom_state(VAPICROMState *s)
write_guest_rom_state(s);
}
-static int find_real_tpr_addr(VAPICROMState *s, CPUState *env)
+static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
{
target_phys_addr_t paddr;
target_ulong addr;
@@ -185,7 +185,7 @@ static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
modrm_reg(opcode[1]) == instr->modrm_reg);
}
-static int evaluate_tpr_instruction(VAPICROMState *s, CPUState *env,
+static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
target_ulong *pip, TPRAccess access)
{
const TPRInstruction *instr;
@@ -267,7 +267,7 @@ instruction_ok:
return 0;
}
-static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
+static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
target_phys_addr_t paddr;
uint32_t rom_state_vaddr;
@@ -330,7 +330,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
* cannot be accessed or is considered invalid. This also ensures that we are
* not patching the wrong guest.
*/
-static int get_kpcr_number(CPUState *env)
+static int get_kpcr_number(CPUX86State *env)
{
struct kpcr {
uint8_t fill1[0x1c];
@@ -347,7 +347,7 @@ static int get_kpcr_number(CPUState *env)
return kpcr.number;
}
-static int vapic_enable(VAPICROMState *s, CPUState *env)
+static int vapic_enable(VAPICROMState *s, CPUX86State *env)
{
int cpu_number = get_kpcr_number(env);
target_phys_addr_t vapic_paddr;
@@ -367,12 +367,12 @@ static int vapic_enable(VAPICROMState *s, CPUState *env)
return 0;
}
-static void patch_byte(CPUState *env, target_ulong addr, uint8_t byte)
+static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte)
{
cpu_memory_rw_debug(env, addr, &byte, 1, 1);
}
-static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
+static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
uint32_t target)
{
uint32_t offset;
@@ -382,7 +382,7 @@ static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
}
-static void patch_instruction(VAPICROMState *s, CPUState *env, target_ulong ip)
+static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
target_phys_addr_t paddr;
VAPICHandlers *handlers;
@@ -439,7 +439,7 @@ void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
TPRAccess access)
{
VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
- CPUState *env = cpu;
+ CPUX86State *env = cpu;
cpu_synchronize_state(env);
@@ -475,7 +475,7 @@ static void vapic_enable_tpr_reporting(bool enable)
VAPICEnableTPRReporting info = {
.enable = enable,
};
- CPUState *env;
+ CPUX86State *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
info.apic = env->apic_state;
@@ -604,7 +604,7 @@ static int vapic_prepare(VAPICROMState *s)
static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
unsigned int size)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
target_phys_addr_t rom_paddr;
VAPICROMState *s = opaque;
diff --git a/hw/pc.c b/hw/pc.c
index aca4460..83a1b5b 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -140,7 +140,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *arg)
smm_arg = arg;
}
-void cpu_smm_update(CPUState *env)
+void cpu_smm_update(CPUX86State *env)
{
if (smm_set && smm_arg && env == first_cpu)
smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
@@ -148,7 +148,7 @@ void cpu_smm_update(CPUState *env)
/* IRQ handling */
-int cpu_get_pic_interrupt(CPUState *env)
+int cpu_get_pic_interrupt(CPUX86State *env)
{
int intno;
@@ -167,7 +167,7 @@ int cpu_get_pic_interrupt(CPUState *env)
static void pic_irq_request(void *opaque, int irq, int level)
{
- CPUState *env = first_cpu;
+ CPUX86State *env = first_cpu;
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
if (env->apic_state) {
@@ -522,7 +522,7 @@ type_init(port92_register_types)
static void handle_a20_line_change(void *opaque, int irq, int level)
{
- CPUState *cpu = opaque;
+ CPUX86State *cpu = opaque;
/* XXX: send to all CPUs ? */
/* XXX: add logic to handle multiple A20 line sources */
@@ -869,7 +869,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
nb_ne2k++;
}
-int cpu_is_bsp(CPUState *env)
+int cpu_is_bsp(CPUX86State *env)
{
/* We hard-wire the BSP to the first CPU. */
return env->cpu_index == 0;
@@ -917,7 +917,7 @@ static DeviceState *apic_init(void *env, uint8_t apic_id)
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
{
- CPUState *s = opaque;
+ CPUX86State *s = opaque;
if (level) {
cpu_interrupt(s, CPU_INTERRUPT_SMI);
@@ -926,15 +926,15 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
static void pc_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUX86State *env = opaque;
cpu_state_reset(env);
env->halted = !cpu_is_bsp(env);
}
-static CPUState *pc_new_cpu(const char *cpu_model)
+static CPUX86State *pc_new_cpu(const char *cpu_model)
{
- CPUState *env;
+ CPUX86State *env;
env = cpu_init(cpu_model);
if (!env) {
@@ -1070,7 +1070,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
static void cpu_request_exit(void *opaque, int irq, int level)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
diff --git a/hw/vmport.c b/hw/vmport.c
index 9373be9..a4f52ee 100644
--- a/hw/vmport.c
+++ b/hw/vmport.c
@@ -57,7 +57,7 @@ void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque)
static uint32_t vmport_ioport_read(void *opaque, uint32_t addr)
{
VMPortState *s = opaque;
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
unsigned char command;
uint32_t eax;
@@ -83,21 +83,21 @@ static uint32_t vmport_ioport_read(void *opaque, uint32_t addr)
static void vmport_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
env->regs[R_EAX] = vmport_ioport_read(opaque, addr);
}
static uint32_t vmport_cmd_get_version(void *opaque, uint32_t addr)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
env->regs[R_EBX] = VMPORT_MAGIC;
return 6;
}
static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
env->regs[R_EBX] = 0x1177;
return ram_size;
}
@@ -105,7 +105,7 @@ static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr)
/* vmmouse helpers */
void vmmouse_get_data(uint32_t *data)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
data[0] = env->regs[R_EAX]; data[1] = env->regs[R_EBX];
data[2] = env->regs[R_ECX]; data[3] = env->regs[R_EDX];
@@ -114,7 +114,7 @@ void vmmouse_get_data(uint32_t *data)
void vmmouse_set_data(const uint32_t *data)
{
- CPUState *env = cpu_single_env;
+ CPUX86State *env = cpu_single_env;
env->regs[R_EAX] = data[0]; env->regs[R_EBX] = data[1];
env->regs[R_ECX] = data[2]; env->regs[R_EDX] = data[3];
diff --git a/hw/xen_machine_pv.c b/hw/xen_machine_pv.c
index 7985d11..7eee770 100644
--- a/hw/xen_machine_pv.c
+++ b/hw/xen_machine_pv.c
@@ -36,7 +36,7 @@ static void xen_init_pv(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env;
+ CPUX86State *env;
DriveInfo *dinfo;
int i;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 34/44] lm32 hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (32 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 33/44] i386 " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 35/44] m68k " Andreas Färber
` (9 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/lm32_boards.c hw/milkymist.c; do
sed -i "s/CPUState/CPULM32State/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/lm32_boards.c | 10 +++++-----
hw/milkymist.c | 8 ++++----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index 51c8a0f..4dd4f0a 100644
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -31,7 +31,7 @@
#include "exec-memory.h"
typedef struct {
- CPUState *env;
+ CPULM32State *env;
target_phys_addr_t bootstrap_pc;
target_phys_addr_t flash_base;
target_phys_addr_t hwsetup_base;
@@ -42,7 +42,7 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
- CPUState *env = opaque;
+ CPULM32State *env = opaque;
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@@ -54,7 +54,7 @@ static void cpu_irq_handler(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
ResetInfo *reset_info = opaque;
- CPUState *env = reset_info->env;
+ CPULM32State *env = reset_info->env;
cpu_state_reset(env);
@@ -75,7 +75,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPULM32State *env;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
@@ -163,7 +163,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPULM32State *env;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
diff --git a/hw/milkymist.c b/hw/milkymist.c
index 7ec6554..8bb6a97 100644
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -37,7 +37,7 @@
#define KERNEL_LOAD_ADDR 0x40000000
typedef struct {
- CPUState *env;
+ CPULM32State *env;
target_phys_addr_t bootstrap_pc;
target_phys_addr_t flash_base;
target_phys_addr_t initrd_base;
@@ -47,7 +47,7 @@ typedef struct {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
- CPUState *env = opaque;
+ CPULM32State *env = opaque;
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@@ -59,7 +59,7 @@ static void cpu_irq_handler(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
ResetInfo *reset_info = opaque;
- CPUState *env = reset_info->env;
+ CPULM32State *env = reset_info->env;
cpu_state_reset(env);
@@ -79,7 +79,7 @@ milkymist_init(ram_addr_t ram_size_not_used,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPULM32State *env;
int kernel_size;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 35/44] m68k hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (33 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 34/44] lm32 " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 36/44] microblaze " Andreas Färber
` (8 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/an5206.c hw/dummy_m68k.c hw/mcf.h hw/mcf5206.c hw/mcf5208.c hw/mcf_intc.c; do
sed -i "s/CPUState/CPUM68KState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/an5206.c | 2 +-
hw/dummy_m68k.c | 2 +-
hw/mcf.h | 4 ++--
hw/mcf5206.c | 4 ++--
hw/mcf5208.c | 2 +-
hw/mcf_intc.c | 4 ++--
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/an5206.c b/hw/an5206.c
index d57306d..25407c0 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -24,7 +24,7 @@ static void an5206_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c
index e3c5740..7cc7a99 100644
--- a/hw/dummy_m68k.c
+++ b/hw/dummy_m68k.c
@@ -21,7 +21,7 @@ static void dummy_m68k_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUM68KState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
diff --git a/hw/mcf.h b/hw/mcf.h
index baa790b..19a8b54 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -17,7 +17,7 @@ void mcf_uart_mm_init(struct MemoryRegion *sysmem,
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
target_phys_addr_t base,
- CPUState *env);
+ CPUM68KState *env);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
@@ -25,6 +25,6 @@ void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
- uint32_t base, CPUState *env);
+ uint32_t base, CPUM68KState *env);
#endif
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index 5110d83..539b391 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -145,7 +145,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq)
/* System Integration Module. */
typedef struct {
- CPUState *env;
+ CPUM68KState *env;
MemoryRegion iomem;
m5206_timer_state *timer[2];
void *uart[2];
@@ -525,7 +525,7 @@ static const MemoryRegionOps m5206_mbar_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env)
+qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUM68KState *env)
{
m5206_mbar_state *s;
qemu_irq *pic;
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index aa11a75..d3ebe8d 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -192,7 +192,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index 0b498dd..cc1a5f3 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -16,7 +16,7 @@ typedef struct {
uint64_t ifr;
uint64_t enabled;
uint8_t icr[64];
- CPUState *env;
+ CPUM68KState *env;
int active_vector;
} mcf_intc_state;
@@ -139,7 +139,7 @@ static const MemoryRegionOps mcf_intc_ops = {
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
target_phys_addr_t base,
- CPUState *env)
+ CPUM68KState *env)
{
mcf_intc_state *s;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 36/44] microblaze hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (34 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 35/44] m68k " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 37/44] mips " Andreas Färber
` (7 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/microblaze_*.[hc] hw/petalogix_ml605_mmu.c hw/petalogix_s3adsp1800_mmu.c; do
sed -i "s/CPUState/CPUMBState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/microblaze_boot.c | 8 ++++----
hw/microblaze_boot.h | 4 ++--
hw/microblaze_pic_cpu.c | 4 ++--
hw/microblaze_pic_cpu.h | 2 +-
hw/petalogix_ml605_mmu.c | 4 ++--
hw/petalogix_s3adsp1800_mmu.c | 4 ++--
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c
index 7ce04dc..b4fbb10 100644
--- a/hw/microblaze_boot.c
+++ b/hw/microblaze_boot.c
@@ -35,7 +35,7 @@
static struct
{
- void (*machine_cpu_reset)(CPUState *);
+ void (*machine_cpu_reset)(CPUMBState *);
uint32_t bootstrap_pc;
uint32_t cmdline;
uint32_t fdt;
@@ -43,7 +43,7 @@ static struct
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUMBState *env = opaque;
cpu_state_reset(env);
env->regs[5] = boot_info.cmdline;
@@ -99,9 +99,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x30000000LL;
}
-void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base,
+void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
- void (*machine_cpu_reset)(CPUState *))
+ void (*machine_cpu_reset)(CPUMBState *))
{
QemuOpts *machine_opts;
diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h
index 69d4ac6..bf9d136 100644
--- a/hw/microblaze_boot.h
+++ b/hw/microblaze_boot.h
@@ -3,8 +3,8 @@
#include "hw.h"
-void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base,
+void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
- void (*machine_cpu_reset)(CPUState *));
+ void (*machine_cpu_reset)(CPUMBState *));
#endif /* __MICROBLAZE_BOOT __ */
diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c
index 8b5623c..ff36a52 100644
--- a/hw/microblaze_pic_cpu.c
+++ b/hw/microblaze_pic_cpu.c
@@ -29,7 +29,7 @@
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
{
- CPUState *env = (CPUState *)opaque;
+ CPUMBState *env = (CPUMBState *)opaque;
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
if (level)
@@ -38,7 +38,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
cpu_reset_interrupt(env, type);
}
-qemu_irq *microblaze_pic_init_cpu(CPUState *env)
+qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)
{
return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2);
}
diff --git a/hw/microblaze_pic_cpu.h b/hw/microblaze_pic_cpu.h
index 4c76275..43090a4 100644
--- a/hw/microblaze_pic_cpu.h
+++ b/hw/microblaze_pic_cpu.h
@@ -3,6 +3,6 @@
#include "qemu-common.h"
-qemu_irq *microblaze_pic_init_cpu(CPUState *env);
+qemu_irq *microblaze_pic_init_cpu(CPUMBState *env);
#endif /* MICROBLAZE_PIC_CPU_H */
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index c87fa11..31a4348 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -54,7 +54,7 @@
#define AXIENET_BASEADDR 0x82780000
#define AXIDMA_BASEADDR 0x84600000
-static void machine_cpu_reset(CPUState *env)
+static void machine_cpu_reset(CPUMBState *env)
{
env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
/* setup pvr to match kernel setting */
@@ -75,7 +75,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
{
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
- CPUState *env;
+ CPUMBState *env;
DriveInfo *dinfo;
int i;
target_phys_addr_t ddr_base = MEMORY_BASEADDR;
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 2cb0b1f..ff154c7 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -49,7 +49,7 @@
#define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000
-static void machine_cpu_reset(CPUState *env)
+static void machine_cpu_reset(CPUMBState *env)
{
/* FIXME: move to machine specfic cpu reset */
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
@@ -63,7 +63,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
DeviceState *dev;
- CPUState *env;
+ CPUMBState *env;
DriveInfo *dinfo;
int i;
target_phys_addr_t ddr_base = MEMORY_BASEADDR;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 37/44] mips hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (35 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 36/44] microblaze " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 38/44] ppc " Andreas Färber
` (6 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/mips_*.[hc]; do
sed -i "s/CPUState/CPUMIPSState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/mips_cpudevs.h | 4 ++--
hw/mips_fulong2e.c | 10 +++++-----
hw/mips_int.c | 6 +++---
hw/mips_jazz.c | 6 +++---
hw/mips_malta.c | 10 +++++-----
hw/mips_mipssim.c | 6 +++---
hw/mips_r4k.c | 6 +++---
hw/mips_timer.c | 20 ++++++++++----------
8 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/hw/mips_cpudevs.h b/hw/mips_cpudevs.h
index db82b41..6bea24b 100644
--- a/hw/mips_cpudevs.h
+++ b/hw/mips_cpudevs.h
@@ -7,9 +7,9 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
/* mips_int.c */
-void cpu_mips_irq_init_cpu(CPUState *env);
+void cpu_mips_irq_init_cpu(CPUMIPSState *env);
/* mips_timer.c */
-void cpu_mips_clock_init(CPUState *);
+void cpu_mips_clock_init(CPUMIPSState *);
#endif
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index 2db8ba0..dc743ca 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -103,7 +103,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
va_end(ap);
}
-static int64_t load_kernel (CPUState *env)
+static int64_t load_kernel (CPUMIPSState *env)
{
int64_t kernel_entry, kernel_low, kernel_high;
int index = 0;
@@ -169,7 +169,7 @@ static int64_t load_kernel (CPUState *env)
return kernel_entry;
}
-static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr)
+static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
{
uint32_t *p;
@@ -199,7 +199,7 @@ static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr)
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUMIPSState *env = opaque;
cpu_state_reset(env);
/* TODO: 2E reset stuff */
@@ -249,7 +249,7 @@ static void network_init (void)
static void cpu_request_exit(void *opaque, int irq, int level)
{
- CPUState *env = cpu_single_env;
+ CPUMIPSState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@@ -273,7 +273,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
i2c_bus *smbus;
int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
- CPUState *env;
+ CPUMIPSState *env;
/* init CPUs */
if (cpu_model == NULL) {
diff --git a/hw/mips_int.c b/hw/mips_int.c
index 477f6ab..6423fd0 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -26,7 +26,7 @@
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
- CPUState *env = (CPUState *)opaque;
+ CPUMIPSState *env = (CPUMIPSState *)opaque;
if (irq < 0 || irq > 7)
return;
@@ -44,7 +44,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
}
}
-void cpu_mips_irq_init_cpu(CPUState *env)
+void cpu_mips_irq_init_cpu(CPUMIPSState *env)
{
qemu_irq *qi;
int i;
@@ -55,7 +55,7 @@ void cpu_mips_irq_init_cpu(CPUState *env)
}
}
-void cpu_mips_soft_irq(CPUState *env, int irq, int level)
+void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
{
if (irq < 0 || irq > 2) {
return;
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index d5f1b34..a6bc7ba 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -50,7 +50,7 @@ enum jazz_model_e
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUMIPSState *env = opaque;
cpu_state_reset(env);
}
@@ -97,7 +97,7 @@ static const MemoryRegionOps dma_dummy_ops = {
static void cpu_request_exit(void *opaque, int irq, int level)
{
- CPUState *env = cpu_single_env;
+ CPUMIPSState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@@ -112,7 +112,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
{
char *filename;
int bios_size, n;
- CPUState *env;
+ CPUMIPSState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 887faea..c3c5a49 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -501,7 +501,7 @@ static void network_init(void)
a3 - RAM size in bytes
*/
-static void write_bootloader (CPUState *env, uint8_t *base,
+static void write_bootloader (CPUMIPSState *env, uint8_t *base,
int64_t kernel_entry)
{
uint32_t *p;
@@ -737,7 +737,7 @@ static int64_t load_kernel (void)
return kernel_entry;
}
-static void malta_mips_config(CPUState *env)
+static void malta_mips_config(CPUMIPSState *env)
{
env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
@@ -745,7 +745,7 @@ static void malta_mips_config(CPUState *env)
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUMIPSState *env = opaque;
cpu_state_reset(env);
/* The bootloader does not need to be rewritten as it is located in a
@@ -760,7 +760,7 @@ static void main_cpu_reset(void *opaque)
static void cpu_request_exit(void *opaque, int irq, int level)
{
- CPUState *env = cpu_single_env;
+ CPUMIPSState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@@ -782,7 +782,7 @@ void mips_malta_init (ram_addr_t ram_size,
int64_t kernel_entry;
PCIBus *pci_bus;
ISABus *isa_bus;
- CPUState *env;
+ CPUMIPSState *env;
qemu_irq *isa_irq;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index 1fe4ac5..1ea7b58 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -46,7 +46,7 @@ static struct _loaderparams {
} loaderparams;
typedef struct ResetData {
- CPUState *env;
+ CPUMIPSState *env;
uint64_t vector;
} ResetData;
@@ -105,7 +105,7 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
- CPUState *env = s->env;
+ CPUMIPSState *env = s->env;
cpu_state_reset(env);
env->active_tc.PC = s->vector & ~(target_ulong)1;
@@ -140,7 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
- CPUState *env;
+ CPUMIPSState *env;
ResetData *reset_info;
int bios_size;
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 96ad808..e2da49c 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = {
};
typedef struct ResetData {
- CPUState *env;
+ CPUMIPSState *env;
uint64_t vector;
} ResetData;
@@ -143,7 +143,7 @@ static int64_t load_kernel(void)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
- CPUState *env = s->env;
+ CPUMIPSState *env = s->env;
cpu_state_reset(env);
env->active_tc.PC = s->vector;
@@ -162,7 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size,
MemoryRegion *bios;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size;
- CPUState *env;
+ CPUMIPSState *env;
ResetData *reset_info;
int i;
qemu_irq *i8259;
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index cf6ac69..7aa9004 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -27,7 +27,7 @@
#define TIMER_FREQ 100 * 1000 * 1000
/* XXX: do not use a global */
-uint32_t cpu_mips_get_random (CPUState *env)
+uint32_t cpu_mips_get_random (CPUMIPSState *env)
{
static uint32_t lfsr = 1;
static uint32_t prev_idx = 0;
@@ -42,7 +42,7 @@ uint32_t cpu_mips_get_random (CPUState *env)
}
/* MIPS R4K timer */
-static void cpu_mips_timer_update(CPUState *env)
+static void cpu_mips_timer_update(CPUMIPSState *env)
{
uint64_t now, next;
uint32_t wait;
@@ -55,7 +55,7 @@ static void cpu_mips_timer_update(CPUState *env)
}
/* Expire the timer. */
-static void cpu_mips_timer_expire(CPUState *env)
+static void cpu_mips_timer_expire(CPUMIPSState *env)
{
cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2) {
@@ -64,7 +64,7 @@ static void cpu_mips_timer_expire(CPUState *env)
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
-uint32_t cpu_mips_get_count (CPUState *env)
+uint32_t cpu_mips_get_count (CPUMIPSState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count;
@@ -83,7 +83,7 @@ uint32_t cpu_mips_get_count (CPUState *env)
}
}
-void cpu_mips_store_count (CPUState *env, uint32_t count)
+void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
{
if (env->CP0_Cause & (1 << CP0Ca_DC))
env->CP0_Count = count;
@@ -97,7 +97,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count)
}
}
-void cpu_mips_store_compare (CPUState *env, uint32_t value)
+void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
{
env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
@@ -107,12 +107,12 @@ void cpu_mips_store_compare (CPUState *env, uint32_t value)
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
-void cpu_mips_start_count(CPUState *env)
+void cpu_mips_start_count(CPUMIPSState *env)
{
cpu_mips_store_count(env, env->CP0_Count);
}
-void cpu_mips_stop_count(CPUState *env)
+void cpu_mips_stop_count(CPUMIPSState *env)
{
/* Store the current value */
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
@@ -121,7 +121,7 @@ void cpu_mips_stop_count(CPUState *env)
static void mips_timer_cb (void *opaque)
{
- CPUState *env;
+ CPUMIPSState *env;
env = opaque;
#if 0
@@ -139,7 +139,7 @@ static void mips_timer_cb (void *opaque)
env->CP0_Count--;
}
-void cpu_mips_clock_init (CPUState *env)
+void cpu_mips_clock_init (CPUMIPSState *env)
{
env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
env->CP0_Compare = 0;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 38/44] ppc hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (36 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 37/44] mips " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 39/44] s390x " Andreas Färber
` (5 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/ppc*.[hc] hw/mpc8544_guts.c hw/spapr*.[hc] hw/virtex_ml507.c hw/xics.c; do
sed -i "s/CPUState/CPUPPCState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/mpc8544_guts.c | 2 +-
hw/ppc.c | 110 ++++++++++++++++++++++++------------------------
hw/ppc.h | 28 ++++++------
hw/ppc405.h | 8 ++--
hw/ppc405_uc.c | 34 +++++++-------
hw/ppc440_bamboo.c | 6 +-
hw/ppc4xx.h | 8 ++--
hw/ppc4xx_devs.c | 10 ++--
hw/ppc_booke.c | 20 ++++----
hw/ppc_newworld.c | 4 +-
hw/ppc_oldworld.c | 4 +-
hw/ppc_prep.c | 6 +-
hw/ppce500_mpc8544ds.c | 12 +++---
hw/ppce500_spin.c | 8 ++--
hw/spapr.c | 10 ++--
hw/spapr.h | 4 +-
hw/spapr_hcall.c | 42 +++++++++---------
hw/spapr_llan.c | 10 ++--
hw/spapr_rtas.c | 4 +-
hw/spapr_vio.c | 12 +++---
hw/spapr_vty.c | 4 +-
hw/virtex_ml507.c | 10 ++--
hw/xics.c | 10 ++--
23 files changed, 183 insertions(+), 183 deletions(-)
diff --git a/hw/mpc8544_guts.c b/hw/mpc8544_guts.c
index aeb2de7..13b0ddd 100644
--- a/hw/mpc8544_guts.c
+++ b/hw/mpc8544_guts.c
@@ -62,7 +62,7 @@ static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t value = 0;
- CPUState *env = cpu_single_env;
+ CPUPPCState *env = cpu_single_env;
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
switch (addr) {
diff --git a/hw/ppc.c b/hw/ppc.c
index a9516f1..98546de 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -47,10 +47,10 @@
# define LOG_TB(...) do { } while (0)
#endif
-static void cpu_ppc_tb_stop (CPUState *env);
-static void cpu_ppc_tb_start (CPUState *env);
+static void cpu_ppc_tb_stop (CPUPPCState *env);
+static void cpu_ppc_tb_start (CPUPPCState *env);
-void ppc_set_irq(CPUState *env, int n_IRQ, int level)
+void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)
{
unsigned int old_pending = env->pending_interrupts;
@@ -77,7 +77,7 @@ void ppc_set_irq(CPUState *env, int n_IRQ, int level)
/* PowerPC 6xx / 7xx internal IRQ controller */
static void ppc6xx_set_irq (void *opaque, int pin, int level)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -151,7 +151,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
}
}
-void ppc6xx_irq_init (CPUState *env)
+void ppc6xx_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
PPC6xx_INPUT_NB);
@@ -161,7 +161,7 @@ void ppc6xx_irq_init (CPUState *env)
/* PowerPC 970 internal IRQ controller */
static void ppc970_set_irq (void *opaque, int pin, int level)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -233,7 +233,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
}
}
-void ppc970_irq_init (CPUState *env)
+void ppc970_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
PPC970_INPUT_NB);
@@ -242,7 +242,7 @@ void ppc970_irq_init (CPUState *env)
/* POWER7 internal IRQ controller */
static void power7_set_irq (void *opaque, int pin, int level)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
env, pin, level);
@@ -266,7 +266,7 @@ static void power7_set_irq (void *opaque, int pin, int level)
}
}
-void ppcPOWER7_irq_init (CPUState *env)
+void ppcPOWER7_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,
POWER7_INPUT_NB);
@@ -276,7 +276,7 @@ void ppcPOWER7_irq_init (CPUState *env)
/* PowerPC 40x internal IRQ controller */
static void ppc40x_set_irq (void *opaque, int pin, int level)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -346,7 +346,7 @@ static void ppc40x_set_irq (void *opaque, int pin, int level)
}
}
-void ppc40x_irq_init (CPUState *env)
+void ppc40x_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
env, PPC40x_INPUT_NB);
@@ -355,7 +355,7 @@ void ppc40x_irq_init (CPUState *env)
/* PowerPC E500 internal IRQ controller */
static void ppce500_set_irq (void *opaque, int pin, int level)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
int cur_level;
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -407,7 +407,7 @@ static void ppce500_set_irq (void *opaque, int pin, int level)
}
}
-void ppce500_irq_init (CPUState *env)
+void ppce500_irq_init (CPUPPCState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
env, PPCE500_INPUT_NB);
@@ -421,7 +421,7 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
}
-uint64_t cpu_ppc_load_tbl (CPUState *env)
+uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -436,7 +436,7 @@ uint64_t cpu_ppc_load_tbl (CPUState *env)
return tb;
}
-static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
+static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -447,7 +447,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
return tb >> 32;
}
-uint32_t cpu_ppc_load_tbu (CPUState *env)
+uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
{
if (kvm_enabled()) {
return env->spr[SPR_TBU];
@@ -464,7 +464,7 @@ static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
__func__, value, *tb_offsetp);
}
-void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
+void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -475,7 +475,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
&tb_env->tb_offset, tb | (uint64_t)value);
}
-static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
+static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -486,12 +486,12 @@ static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
&tb_env->tb_offset, ((uint64_t)value << 32) | tb);
}
-void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
+void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_tbu(env, value);
}
-uint64_t cpu_ppc_load_atbl (CPUState *env)
+uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -502,7 +502,7 @@ uint64_t cpu_ppc_load_atbl (CPUState *env)
return tb;
}
-uint32_t cpu_ppc_load_atbu (CPUState *env)
+uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -513,7 +513,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
return tb >> 32;
}
-void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
+void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -524,7 +524,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
&tb_env->atb_offset, tb | (uint64_t)value);
}
-void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
+void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -535,7 +535,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
&tb_env->atb_offset, ((uint64_t)value << 32) | tb);
}
-static void cpu_ppc_tb_stop (CPUState *env)
+static void cpu_ppc_tb_stop (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
@@ -557,7 +557,7 @@ static void cpu_ppc_tb_stop (CPUState *env)
}
}
-static void cpu_ppc_tb_start (CPUState *env)
+static void cpu_ppc_tb_start (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
@@ -578,7 +578,7 @@ static void cpu_ppc_tb_start (CPUState *env)
}
}
-static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
+static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
{
ppc_tb_t *tb_env = env->tb_env;
uint32_t decr;
@@ -597,7 +597,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
return decr;
}
-uint32_t cpu_ppc_load_decr (CPUState *env)
+uint32_t cpu_ppc_load_decr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -608,14 +608,14 @@ uint32_t cpu_ppc_load_decr (CPUState *env)
return _cpu_ppc_load_decr(env, tb_env->decr_next);
}
-uint32_t cpu_ppc_load_hdecr (CPUState *env)
+uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
}
-uint64_t cpu_ppc_load_purr (CPUState *env)
+uint64_t cpu_ppc_load_purr (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t diff;
@@ -628,23 +628,23 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
*/
-static inline void cpu_ppc_decr_excp(CPUState *env)
+static inline void cpu_ppc_decr_excp(CPUPPCState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
}
-static inline void cpu_ppc_hdecr_excp(CPUState *env)
+static inline void cpu_ppc_hdecr_excp(CPUPPCState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
}
-static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
+static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp,
struct QEMUTimer *timer,
- void (*raise_excp)(CPUState *),
+ void (*raise_excp)(CPUPPCState *),
uint32_t decr, uint32_t value,
int is_excp)
{
@@ -681,7 +681,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
}
}
-static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
+static inline void _cpu_ppc_store_decr(CPUPPCState *env, uint32_t decr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -690,7 +690,7 @@ static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
&cpu_ppc_decr_excp, decr, value, is_excp);
}
-void cpu_ppc_store_decr (CPUState *env, uint32_t value)
+void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
}
@@ -700,7 +700,7 @@ static void cpu_ppc_decr_cb (void *opaque)
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
-static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
+static inline void _cpu_ppc_store_hdecr(CPUPPCState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -711,7 +711,7 @@ static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
}
}
-void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
+void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
}
@@ -721,7 +721,7 @@ static void cpu_ppc_hdecr_cb (void *opaque)
_cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
-void cpu_ppc_store_purr (CPUState *env, uint64_t value)
+void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -731,7 +731,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value)
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
ppc_tb_t *tb_env = env->tb_env;
tb_env->tb_freq = freq;
@@ -746,7 +746,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
}
/* Set up (once) timebase frequency (in Hz) */
-clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
+clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
{
ppc_tb_t *tb_env;
@@ -769,28 +769,28 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
/* Specific helpers for POWER & PowerPC 601 RTC */
#if 0
-static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
+static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
{
return cpu_ppc_tb_init(env, 7812500);
}
#endif
-void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
+void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
{
_cpu_ppc_store_tbu(env, value);
}
-uint32_t cpu_ppc601_load_rtcu (CPUState *env)
+uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
{
return _cpu_ppc_load_tbu(env);
}
-void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
+void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
{
cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
}
-uint32_t cpu_ppc601_load_rtcl (CPUState *env)
+uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
{
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
}
@@ -814,7 +814,7 @@ struct ppc40x_timer_t {
/* Fixed interval timer */
static void cpu_4xx_fit_cb (void *opaque)
{
- CPUState *env;
+ CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
@@ -853,7 +853,7 @@ static void cpu_4xx_fit_cb (void *opaque)
}
/* Programmable interval timer */
-static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
+static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
{
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
@@ -882,7 +882,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
static void cpu_4xx_pit_cb (void *opaque)
{
- CPUState *env;
+ CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
@@ -904,7 +904,7 @@ static void cpu_4xx_pit_cb (void *opaque)
/* Watchdog timer */
static void cpu_4xx_wdt_cb (void *opaque)
{
- CPUState *env;
+ CPUPPCState *env;
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
uint64_t now, next;
@@ -969,7 +969,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
}
}
-void store_40x_pit (CPUState *env, target_ulong val)
+void store_40x_pit (CPUPPCState *env, target_ulong val)
{
ppc_tb_t *tb_env;
ppc40x_timer_t *ppc40x_timer;
@@ -981,14 +981,14 @@ void store_40x_pit (CPUState *env, target_ulong val)
start_stop_pit(env, tb_env, 0);
}
-target_ulong load_40x_pit (CPUState *env)
+target_ulong load_40x_pit (CPUPPCState *env)
{
return cpu_ppc_load_decr(env);
}
static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
ppc_tb_t *tb_env = env->tb_env;
LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
@@ -998,7 +998,7 @@ static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
/* XXX: we should also update all timers */
}
-clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,
+clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
unsigned int decr_excp)
{
ppc_tb_t *tb_env;
@@ -1084,7 +1084,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
return -1;
}
-int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
+int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
dcr_read_cb dcr_read, dcr_write_cb dcr_write)
{
ppc_dcr_t *dcr_env;
@@ -1107,7 +1107,7 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
return 0;
}
-int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
+int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
int (*write_error)(int dcrn))
{
ppc_dcr_t *dcr_env;
diff --git a/hw/ppc.h b/hw/ppc.h
index 9f91170..2f3ea27 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -1,4 +1,4 @@
-void ppc_set_irq (CPUState *env, int n_IRQ, int level);
+void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);
/* PowerPC hardware exceptions management helpers */
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
@@ -43,32 +43,32 @@ struct ppc_tb_t {
*/
uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
-clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
+clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
/* Embedded PowerPC DCR management */
typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
-int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
+int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
int (*dcr_write_error)(int dcrn));
-int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
+int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
dcr_read_cb drc_read, dcr_write_cb dcr_write);
-clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,
+clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
unsigned int decr_excp);
/* Embedded PowerPC reset */
-void ppc40x_core_reset (CPUState *env);
-void ppc40x_chip_reset (CPUState *env);
-void ppc40x_system_reset (CPUState *env);
+void ppc40x_core_reset (CPUPPCState *env);
+void ppc40x_chip_reset (CPUPPCState *env);
+void ppc40x_system_reset (CPUPPCState *env);
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
extern CPUWriteMemoryFunc * const PPC_io_write[];
extern CPUReadMemoryFunc * const PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
-void ppc40x_irq_init (CPUState *env);
-void ppce500_irq_init (CPUState *env);
-void ppc6xx_irq_init (CPUState *env);
-void ppc970_irq_init (CPUState *env);
-void ppcPOWER7_irq_init (CPUState *env);
+void ppc40x_irq_init (CPUPPCState *env);
+void ppce500_irq_init (CPUPPCState *env);
+void ppc6xx_irq_init (CPUPPCState *env);
+void ppc970_irq_init (CPUPPCState *env);
+void ppcPOWER7_irq_init (CPUPPCState *env);
/* PPC machines for OpenBIOS */
enum {
@@ -89,4 +89,4 @@ enum {
#define PPC_SERIAL_MM_BAUDBASE 399193
/* ppc_booke.c */
-void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags);
+void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags);
diff --git a/hw/ppc405.h b/hw/ppc405.h
index d8fdf09..1f5dc5f 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -56,23 +56,23 @@ struct ppc4xx_bd_info_t {
};
/* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
+ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
-CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
+CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
-CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
+CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
-CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],
+CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 951b389..6f8342e 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -41,7 +41,7 @@
#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
-ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
+ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
ram_addr_t bdloc;
@@ -169,7 +169,7 @@ static void ppc4xx_plb_reset (void *opaque)
plb->besr = 0x00000000;
}
-static void ppc4xx_plb_init(CPUState *env)
+static void ppc4xx_plb_init(CPUPPCState *env)
{
ppc4xx_plb_t *plb;
@@ -245,7 +245,7 @@ static void ppc4xx_pob_reset (void *opaque)
pob->besr[1] = 0x0000000;
}
-static void ppc4xx_pob_init(CPUState *env)
+static void ppc4xx_pob_init(CPUPPCState *env)
{
ppc4xx_pob_t *pob;
@@ -574,7 +574,7 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-static void ppc405_ebc_init(CPUState *env)
+static void ppc405_ebc_init(CPUPPCState *env)
{
ppc4xx_ebc_t *ebc;
@@ -657,7 +657,7 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
-static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
+static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
{
ppc405_dma_t *dma;
@@ -960,7 +960,7 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
-static void ppc405_ocm_init(CPUState *env)
+static void ppc405_ocm_init(CPUPPCState *env)
{
ppc405_ocm_t *ocm;
@@ -1713,7 +1713,7 @@ static void ppc40x_mal_reset (void *opaque)
mal->txeobisr = 0x00000000;
}
-static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
+static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
{
ppc40x_mal_t *mal;
int i;
@@ -1764,7 +1764,7 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
/*****************************************************************************/
/* SPR */
-void ppc40x_core_reset (CPUState *env)
+void ppc40x_core_reset (CPUPPCState *env)
{
target_ulong dbsr;
@@ -1776,7 +1776,7 @@ void ppc40x_core_reset (CPUState *env)
env->spr[SPR_40x_DBSR] = dbsr;
}
-void ppc40x_chip_reset (CPUState *env)
+void ppc40x_chip_reset (CPUPPCState *env)
{
target_ulong dbsr;
@@ -1789,13 +1789,13 @@ void ppc40x_chip_reset (CPUState *env)
env->spr[SPR_40x_DBSR] = dbsr;
}
-void ppc40x_system_reset (CPUState *env)
+void ppc40x_system_reset (CPUPPCState *env)
{
printf("Reset PowerPC system\n");
qemu_system_reset_request();
}
-void store_40x_dbcr0 (CPUState *env, uint32_t val)
+void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
{
switch ((val >> 28) & 0x3) {
case 0x0:
@@ -2066,7 +2066,7 @@ static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
cpc->psr |= D << 17;
}
-static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
+static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
uint32_t sysclk)
{
ppc405cr_cpc_t *cpc;
@@ -2096,7 +2096,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
qemu_register_reset(ppc405cr_cpc_reset, cpc);
}
-CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
+CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
@@ -2105,7 +2105,7 @@ CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
{
clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
- CPUState *env;
+ CPUPPCState *env;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
@@ -2408,7 +2408,7 @@ static void ppc405ep_cpc_reset (void *opaque)
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
+static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
uint32_t sysclk)
{
ppc405ep_cpc_t *cpc;
@@ -2445,7 +2445,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
#endif
}
-CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
+CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
@@ -2454,7 +2454,7 @@ CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
{
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
- CPUState *env;
+ CPUPPCState *env;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index 835e36d..220c81d 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -121,7 +121,7 @@ out:
}
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
-static void mmubooke_create_initial_mapping(CPUState *env,
+static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa)
{
@@ -145,7 +145,7 @@ static void mmubooke_create_initial_mapping(CPUState *env,
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
env->gpr[1] = (16<<20) - 8;
@@ -172,7 +172,7 @@ static void bamboo_init(ram_addr_t ram_size,
qemu_irq *pic;
qemu_irq *irqs;
PCIBus *pcibus;
- CPUState *env;
+ CPUPPCState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
target_phys_addr_t loadaddr = 0;
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index f969e44..b511020 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -28,7 +28,7 @@
#include "pci.h"
/* PowerPC 4xx core initialization */
-CPUState *ppc4xx_init (const char *cpu_model,
+CPUPPCState *ppc4xx_init (const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk);
@@ -38,7 +38,7 @@ enum {
PPCUIC_OUTPUT_CINT = 1,
PPCUIC_OUTPUT_NB,
};
-qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
+qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
@@ -47,13 +47,13 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[]);
-void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init);
-PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
+PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
target_phys_addr_t config_space,
target_phys_addr_t int_ack,
target_phys_addr_t special_cycle,
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 2311162..00e36f4 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -40,18 +40,18 @@
static void ppc4xx_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
}
/*****************************************************************************/
/* Generic PowerPC 4xx processor instantiation */
-CPUState *ppc4xx_init (const char *cpu_model,
+CPUPPCState *ppc4xx_init (const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk)
{
- CPUState *env;
+ CPUPPCState *env;
/* init CPUs */
env = cpu_init(cpu_model);
@@ -295,7 +295,7 @@ static void ppcuic_reset (void *opaque)
}
}
-qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
+qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr)
{
ppcuic_t *uic;
@@ -641,7 +641,7 @@ static void sdram_reset (void *opaque)
sdram->cfg = 0x00800000;
}
-void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c
index 8871945..d51e7fa 100644
--- a/hw/ppc_booke.c
+++ b/hw/ppc_booke.c
@@ -71,7 +71,7 @@ struct booke_timer_t {
uint32_t flags;
};
-static void booke_update_irq(CPUState *env)
+static void booke_update_irq(CPUPPCState *env)
{
ppc_set_irq(env, PPC_INTERRUPT_DECR,
(env->spr[SPR_BOOKE_TSR] & TSR_DIS
@@ -88,7 +88,7 @@ static void booke_update_irq(CPUState *env)
/* Return the location of the bit of time base at which the FIT will raise an
interrupt */
-static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env)
+static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
@@ -106,7 +106,7 @@ static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env)
/* Return the location of the bit of time base at which the WDT will raise an
interrupt */
-static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env)
+static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
@@ -122,7 +122,7 @@ static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env)
return wp;
}
-static void booke_update_fixed_timer(CPUState *env,
+static void booke_update_fixed_timer(CPUPPCState *env,
uint8_t target_bit,
uint64_t *next,
struct QEMUTimer *timer)
@@ -153,7 +153,7 @@ static void booke_update_fixed_timer(CPUState *env,
static void booke_decr_cb(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
booke_update_irq(env);
@@ -166,7 +166,7 @@ static void booke_decr_cb(void *opaque)
static void booke_fit_cb(void *opaque)
{
- CPUState *env;
+ CPUPPCState *env;
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
@@ -185,7 +185,7 @@ static void booke_fit_cb(void *opaque)
static void booke_wdt_cb(void *opaque)
{
- CPUState *env;
+ CPUPPCState *env;
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
@@ -203,13 +203,13 @@ static void booke_wdt_cb(void *opaque)
booke_timer->wdt_timer);
}
-void store_booke_tsr(CPUState *env, target_ulong val)
+void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
env->spr[SPR_BOOKE_TSR] &= ~val;
booke_update_irq(env);
}
-void store_booke_tcr(CPUState *env, target_ulong val)
+void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
ppc_tb_t *tb_env = env->tb_env;
booke_timer_t *booke_timer = tb_env->opaque;
@@ -231,7 +231,7 @@ void store_booke_tcr(CPUState *env, target_ulong val)
}
-void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags)
+void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags)
{
ppc_tb_t *tb_env;
booke_timer_t *booke_timer;
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index fd8e21d..c60cfa0 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -124,7 +124,7 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
static void ppc_core99_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
}
@@ -137,7 +137,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 085b825..36aaf97 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -68,7 +68,7 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
static void ppc_heathrow_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
}
@@ -81,7 +81,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
const char *cpu_model)
{
MemoryRegion *sysmem = get_system_memory();
- CPUState *env = NULL;
+ CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index c5f2542..7a92f49 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -464,7 +464,7 @@ static const MemoryRegionOps PPC_prep_io_ops = {
static void cpu_request_exit(void *opaque, int irq, int level)
{
- CPUState *env = cpu_single_env;
+ CPUPPCState *env = cpu_single_env;
if (env && level) {
cpu_exit(env);
@@ -473,7 +473,7 @@ static void cpu_request_exit(void *opaque, int irq, int level)
static void ppc_prep_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
}
@@ -487,7 +487,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
const char *cpu_model)
{
MemoryRegion *sysmem = get_system_memory();
- CPUState *env = NULL;
+ CPUPPCState *env = NULL;
char *filename;
nvram_t nvram;
M48t59State *m48t59;
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 752aed9..5ee8cb3 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -58,7 +58,7 @@ struct boot_info
uint32_t entry;
};
-static int mpc8544_load_device_tree(CPUState *env,
+static int mpc8544_load_device_tree(CPUPPCState *env,
target_phys_addr_t addr,
uint32_t ramsize,
target_phys_addr_t initrd_base,
@@ -178,7 +178,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
return ffs(size >> 10) - 1;
}
-static void mmubooke_create_initial_mapping(CPUState *env,
+static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa)
{
@@ -196,7 +196,7 @@ static void mmubooke_create_initial_mapping(CPUState *env,
static void mpc8544ds_cpu_reset_sec(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
@@ -208,7 +208,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
static void mpc8544ds_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
struct boot_info *bi = env->load_info;
cpu_state_reset(env);
@@ -231,7 +231,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
PCIBus *pci_bus;
- CPUState *env = NULL;
+ CPUPPCState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
target_phys_addr_t entry=0;
@@ -244,7 +244,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
qemu_irq **irqs, *mpic;
DeviceState *dev;
- CPUState *firstenv = NULL;
+ CPUPPCState *firstenv = NULL;
/* Setup CPUs */
if (cpu_model == NULL) {
diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c
index 6b8a189..268f5fd 100644
--- a/hw/ppce500_spin.c
+++ b/hw/ppce500_spin.c
@@ -49,7 +49,7 @@ typedef struct spin_state {
} SpinState;
typedef struct spin_kick {
- CPUState *env;
+ CPUPPCState *env;
SpinInfo *spin;
} SpinKick;
@@ -73,7 +73,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
return (ffs(size >> 10) - 1) >> 1;
}
-static void mmubooke_create_initial_mapping(CPUState *env,
+static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa,
target_phys_addr_t len)
@@ -91,7 +91,7 @@ static void mmubooke_create_initial_mapping(CPUState *env,
static void spin_kick(void *data)
{
SpinKick *kick = data;
- CPUState *env = kick->env;
+ CPUPPCState *env = kick->env;
SpinInfo *curspin = kick->spin;
target_phys_addr_t map_size = 64 * 1024 * 1024;
target_phys_addr_t map_start;
@@ -121,7 +121,7 @@ static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
{
SpinState *s = opaque;
int env_idx = addr / sizeof(SpinInfo);
- CPUState *env;
+ CPUPPCState *env;
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;
diff --git a/hw/spapr.c b/hw/spapr.c
index 3f9d87c..3719e0e 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -110,7 +110,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr)
{
int ret = 0, offset;
- CPUState *env;
+ CPUPPCState *env;
char cpu_model[32];
int smt = kvmppc_smt_threads();
@@ -155,7 +155,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
long hash_shift)
{
void *fdt;
- CPUState *env;
+ CPUPPCState *env;
uint64_t mem_reg_property[2];
uint32_t start_prop = cpu_to_be32(initrd_base);
uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
@@ -476,7 +476,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static void emulate_spapr_hypercall(CPUState *env)
+static void emulate_spapr_hypercall(CPUPPCState *env)
{
env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
}
@@ -504,7 +504,7 @@ static void spapr_reset(void *opaque)
static void spapr_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
cpu_state_reset(env);
}
@@ -517,7 +517,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env;
+ CPUPPCState *env;
int i;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
diff --git a/hw/spapr.h b/hw/spapr.h
index e946a34..a41641f 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -278,12 +278,12 @@ extern sPAPREnvironment *spapr;
do { } while (0)
#endif
-typedef target_ulong (*spapr_hcall_fn)(CPUState *env, sPAPREnvironment *spapr,
+typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args);
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
-target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
+target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
target_ulong *args);
qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num);
diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
index 6ac7384..634763e 100644
--- a/hw/spapr_hcall.c
+++ b/hw/spapr_hcall.c
@@ -92,7 +92,7 @@ static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
return rb;
}
-static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_enter(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
@@ -181,7 +181,7 @@ enum {
REMOVE_HW = 3,
};
-static target_ulong remove_hpte(CPUState *env, target_ulong ptex,
+static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
target_ulong avpn,
target_ulong flags,
target_ulong *vp, target_ulong *rp)
@@ -219,7 +219,7 @@ static target_ulong remove_hpte(CPUState *env, target_ulong ptex,
return REMOVE_SUCCESS;
}
-static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
@@ -265,7 +265,7 @@ static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
#define H_BULK_REMOVE_MAX_BATCH 4
-static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
int i;
@@ -311,7 +311,7 @@ static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
@@ -356,7 +356,7 @@ static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_set_dabr(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
/* FIXME: actually implement this */
@@ -375,7 +375,7 @@ static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
#define VPA_SHARED_PROC_OFFSET 0x9
#define VPA_SHARED_PROC_VAL 0x2
-static target_ulong register_vpa(CPUState *env, target_ulong vpa)
+static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
{
uint16_t size;
uint8_t tmp;
@@ -410,7 +410,7 @@ static target_ulong register_vpa(CPUState *env, target_ulong vpa)
return H_SUCCESS;
}
-static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
+static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
{
if (env->slb_shadow) {
return H_RESOURCE;
@@ -424,7 +424,7 @@ static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
return H_SUCCESS;
}
-static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
+static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
{
uint32_t size;
@@ -451,13 +451,13 @@ static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
return H_SUCCESS;
}
-static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr)
+static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
{
env->slb_shadow = 0;
return H_SUCCESS;
}
-static target_ulong register_dtl(CPUState *env, target_ulong addr)
+static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
{
uint32_t size;
@@ -482,7 +482,7 @@ static target_ulong register_dtl(CPUState *env, target_ulong addr)
return H_SUCCESS;
}
-static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
+static target_ulong deregister_dtl(CPUPPCState *emv, target_ulong addr)
{
env->dispatch_trace_log = 0;
env->dtl_size = 0;
@@ -490,14 +490,14 @@ static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
return H_SUCCESS;
}
-static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong flags = args[0];
target_ulong procno = args[1];
target_ulong vpa = args[2];
target_ulong ret = H_PARAMETER;
- CPUState *tenv;
+ CPUPPCState *tenv;
for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
if (tenv->cpu_index == procno) {
@@ -538,7 +538,7 @@ static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
return ret;
}
-static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
env->msr |= (1ULL << MSR_EE);
@@ -549,7 +549,7 @@ static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong rtas_r3 = args[0];
@@ -561,7 +561,7 @@ static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
nret, rtas_r3 + 12 + 4*nargs);
}
-static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong size = args[0];
@@ -584,7 +584,7 @@ static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr,
return H_PARAMETER;
}
-static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong size = args[0];
@@ -608,14 +608,14 @@ static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr,
return H_PARAMETER;
}
-static target_ulong h_logical_icbi(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_logical_icbi(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
/* Nothing to do on emulation, KVM will trap this in the kernel */
return H_SUCCESS;
}
-static target_ulong h_logical_dcbf(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_logical_dcbf(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
/* Nothing to do on emulation, KVM will trap this in the kernel */
@@ -644,7 +644,7 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
*slot = fn;
}
-target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
+target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
target_ulong *args)
{
if (msr_pr) {
diff --git a/hw/spapr_llan.c b/hw/spapr_llan.c
index 77d4047..cfc7778 100644
--- a/hw/spapr_llan.c
+++ b/hw/spapr_llan.c
@@ -254,7 +254,7 @@ static int check_bd(VIOsPAPRVLANDevice *dev, vlan_bd_t bd,
return 0;
}
-static target_ulong h_register_logical_lan(CPUState *env,
+static target_ulong h_register_logical_lan(CPUPPCState *env,
sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args)
@@ -320,7 +320,7 @@ static target_ulong h_register_logical_lan(CPUState *env,
}
-static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_free_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -343,7 +343,7 @@ static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_add_logical_lan_buffer(CPUState *env,
+static target_ulong h_add_logical_lan_buffer(CPUPPCState *env,
sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args)
@@ -392,7 +392,7 @@ static target_ulong h_add_logical_lan_buffer(CPUState *env,
return H_SUCCESS;
}
-static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_send_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -461,7 +461,7 @@ static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_multicast_ctrl(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_multicast_ctrl(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index c0723b3..0946585 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -118,7 +118,7 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr,
uint32_t nret, target_ulong rets)
{
target_ulong id;
- CPUState *env;
+ CPUPPCState *env;
if (nargs != 1 || nret != 2) {
rtas_st(rets, 0, -3);
@@ -151,7 +151,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr,
uint32_t nret, target_ulong rets)
{
target_ulong id, start, r3;
- CPUState *env;
+ CPUPPCState *env;
if (nargs != 3 || nret != 1) {
rtas_st(rets, 0, -3);
diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c
index ea317ef..2fb3cee 100644
--- a/hw/spapr_vio.c
+++ b/hw/spapr_vio.c
@@ -194,7 +194,7 @@ static void rtce_init(VIOsPAPRDevice *dev)
}
}
-static target_ulong h_put_tce(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_put_tce(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong liobn = args[0];
@@ -405,7 +405,7 @@ uint64_t ldq_tce(VIOsPAPRDevice *dev, uint64_t taddr)
/*
* CRQ handling
*/
-static target_ulong h_reg_crq(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_reg_crq(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -453,7 +453,7 @@ static target_ulong h_reg_crq(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_free_crq(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_free_crq(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -474,7 +474,7 @@ static target_ulong h_free_crq(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_send_crq(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_send_crq(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -498,7 +498,7 @@ static target_ulong h_send_crq(CPUState *env, sPAPREnvironment *spapr,
return H_HARDWARE;
}
-static target_ulong h_enable_crq(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_enable_crq(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -680,7 +680,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev)
return pc->init(dev);
}
-static target_ulong h_vio_signal(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_vio_signal(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode,
target_ulong *args)
{
diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c
index 3efe242..60e22b1 100644
--- a/hw/spapr_vty.c
+++ b/hw/spapr_vty.c
@@ -72,7 +72,7 @@ static int spapr_vty_init(VIOsPAPRDevice *sdev)
/* Forward declaration */
static VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, target_ulong reg);
-static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_put_term_char(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
@@ -99,7 +99,7 @@ static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_get_term_char(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_get_term_char(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index e672490..4a133b5 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -56,7 +56,7 @@ static struct boot_info
} boot_info;
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
-static void mmubooke_create_initial_mapping(CPUState *env,
+static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
target_phys_addr_t pa)
{
@@ -78,12 +78,12 @@ static void mmubooke_create_initial_mapping(CPUState *env,
tlb->PID = 0;
}
-static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
+static CPUPPCState *ppc440_init_xilinx(ram_addr_t *ram_size,
int do_init,
const char *cpu_model,
uint32_t sysclk)
{
- CPUState *env;
+ CPUPPCState *env;
qemu_irq *irqs;
env = cpu_init(cpu_model);
@@ -106,7 +106,7 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUPPCState *env = opaque;
struct boot_info *bi = env->load_info;
cpu_state_reset(env);
@@ -188,7 +188,7 @@ static void virtex_init(ram_addr_t ram_size,
{
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
- CPUState *env;
+ CPUPPCState *env;
target_phys_addr_t ram_base = 0;
DriveInfo *dinfo;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
diff --git a/hw/xics.c b/hw/xics.c
index 1c5eaa4..f7963f3 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -268,7 +268,7 @@ qemu_irq xics_find_qirq(struct icp_state *icp, int irq)
return icp->ics->qirqs[irq - icp->ics->offset];
}
-static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong cppr = args[0];
@@ -277,7 +277,7 @@ static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong server = args[0];
@@ -292,7 +292,7 @@ static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr,
}
-static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);
@@ -301,7 +301,7 @@ static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr,
return H_SUCCESS;
}
-static target_ulong h_eoi(CPUState *env, sPAPREnvironment *spapr,
+static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong xirr = args[0];
@@ -424,7 +424,7 @@ static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
struct icp_state *xics_system_init(int nr_irqs)
{
- CPUState *env;
+ CPUPPCState *env;
int max_server_num;
int i;
struct icp_state *icp;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 39/44] s390x hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (37 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 38/44] ppc " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 40/44] sh4 " Andreas Färber
` (4 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/s390-*.[hc]; do
sed -i "s/CPUState/CPUS390XState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/s390-virtio-bus.c | 6 +++---
hw/s390-virtio.c | 16 ++++++++--------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/s390-virtio-bus.c b/hw/s390-virtio-bus.c
index c450e4b..be1f5f1 100644
--- a/hw/s390-virtio-bus.c
+++ b/hw/s390-virtio-bus.c
@@ -85,7 +85,7 @@ VirtIOS390Bus *s390_virtio_bus_init(ram_addr_t *ram_size)
return bus;
}
-static void s390_virtio_irq(CPUState *env, int config_change, uint64_t token)
+static void s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token)
{
if (kvm_enabled()) {
kvm_s390_virtio_irq(env, config_change, token);
@@ -116,7 +116,7 @@ static int s390_virtio_device_init(VirtIOS390Device *dev, VirtIODevice *vdev)
s390_virtio_device_sync(dev);
if (dev->qdev.hotplugged) {
- CPUState *env = s390_cpu_addr2state(0);
+ CPUS390XState *env = s390_cpu_addr2state(0);
s390_virtio_irq(env, VIRTIO_PARAM_DEV_ADD, dev->dev_offs);
}
@@ -331,7 +331,7 @@ static void virtio_s390_notify(void *opaque, uint16_t vector)
{
VirtIOS390Device *dev = (VirtIOS390Device*)opaque;
uint64_t token = s390_virtio_device_vq_token(dev, vector);
- CPUState *env = s390_cpu_addr2state(0);
+ CPUS390XState *env = s390_cpu_addr2state(0);
s390_virtio_irq(env, 0, token);
}
diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c
index 15e3ef3..1ebe70d 100644
--- a/hw/s390-virtio.c
+++ b/hw/s390-virtio.c
@@ -61,9 +61,9 @@
#define MAX_BLK_DEVS 10
static VirtIOS390Bus *s390_bus;
-static CPUState **ipi_states;
+static CPUS390XState **ipi_states;
-CPUState *s390_cpu_addr2state(uint16_t cpu_addr)
+CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr)
{
if (cpu_addr >= smp_cpus) {
return NULL;
@@ -72,7 +72,7 @@ CPUState *s390_cpu_addr2state(uint16_t cpu_addr)
return ipi_states[cpu_addr];
}
-int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall)
+int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall)
{
int r = 0, i;
@@ -129,7 +129,7 @@ int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall)
*/
static unsigned s390_running_cpus;
-void s390_add_running_cpu(CPUState *env)
+void s390_add_running_cpu(CPUS390XState *env)
{
if (env->halted) {
s390_running_cpus++;
@@ -138,7 +138,7 @@ void s390_add_running_cpu(CPUState *env)
}
}
-unsigned s390_del_running_cpu(CPUState *env)
+unsigned s390_del_running_cpu(CPUS390XState *env)
{
if (env->halted == 0) {
assert(s390_running_cpus >= 1);
@@ -157,7 +157,7 @@ static void s390_init(ram_addr_t my_ram_size,
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUS390XState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
ram_addr_t kernel_size = 0;
@@ -205,10 +205,10 @@ static void s390_init(ram_addr_t my_ram_size,
cpu_model = "host";
}
- ipi_states = g_malloc(sizeof(CPUState *) * smp_cpus);
+ ipi_states = g_malloc(sizeof(CPUS390XState *) * smp_cpus);
for (i = 0; i < smp_cpus; i++) {
- CPUState *tmp_env;
+ CPUS390XState *tmp_env;
tmp_env = cpu_init(cpu_model);
if (!env) {
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 40/44] sh4 hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (38 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 39/44] s390x " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 41/44] sparc " Andreas Färber
` (3 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/sh.h hw/shix.c hw/r2d.c; do
sed -i "s/CPUState/CPUSH4State/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/r2d.c | 6 +++---
hw/sh.h | 2 +-
hw/shix.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/r2d.c b/hw/r2d.c
index ae327a7..c55de01 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -192,14 +192,14 @@ static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
}
typedef struct ResetData {
- CPUState *env;
+ CPUSH4State *env;
uint32_t vector;
} ResetData;
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
- CPUState *env = s->env;
+ CPUSH4State *env = s->env;
cpu_state_reset(env);
env->pc = s->vector;
@@ -224,7 +224,7 @@ static void r2d_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUSH4State *env;
ResetData *reset_info;
struct SH7750State *s;
MemoryRegion *sdram = g_new(MemoryRegion, 1);
diff --git a/hw/sh.h b/hw/sh.h
index 6488db2..40df18c 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -11,7 +11,7 @@
struct SH7750State;
struct MemoryRegion;
-struct SH7750State *sh7750_init(CPUState * cpu, struct MemoryRegion *sysmem);
+struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *sysmem);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
diff --git a/hw/shix.c b/hw/shix.c
index e259c17..dd9ce17 100644
--- a/hw/shix.c
+++ b/hw/shix.c
@@ -43,7 +43,7 @@ static void shix_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
int ret;
- CPUState *env;
+ CPUSH4State *env;
struct SH7750State *s;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 41/44] sparc hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (39 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 40/44] sh4 " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 42/44] xtensa " Andreas Färber
` (2 subsequent siblings)
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/sun4m.c hw/sun4u.c hw/grlib.h hw/leon3.c; do
sed -i "s/CPUState/CPUSPARCState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/grlib.h | 2 +-
hw/leon3.c | 8 ++++----
hw/sun4m.c | 12 ++++++------
hw/sun4u.c | 24 ++++++++++++------------
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/hw/grlib.h b/hw/grlib.h
index fdf4b11..e1c4137 100644
--- a/hw/grlib.h
+++ b/hw/grlib.h
@@ -42,7 +42,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
DeviceState *grlib_irqmp_create(target_phys_addr_t base,
- CPUState *env,
+ CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
set_pil_in_fn set_pil_in)
diff --git a/hw/leon3.c b/hw/leon3.c
index 1dc5a02..0a5ff16 100644
--- a/hw/leon3.c
+++ b/hw/leon3.c
@@ -42,14 +42,14 @@
#define MAX_PILS 16
typedef struct ResetData {
- CPUState *env;
+ CPUSPARCState *env;
uint32_t entry; /* save kernel entry in case of reset */
} ResetData;
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
- CPUState *env = s->env;
+ CPUSPARCState *env = s->env;
cpu_state_reset(env);
@@ -65,7 +65,7 @@ void leon3_irq_ack(void *irq_manager, int intno)
static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
{
- CPUState *env = (CPUState *)opaque;
+ CPUSPARCState *env = (CPUSPARCState *)opaque;
assert(env != NULL);
@@ -101,7 +101,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env;
+ CPUSPARCState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *prom = g_new(MemoryRegion, 1);
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 4045740..7bcbf37 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -228,7 +228,7 @@ void sun4m_irq_info(Monitor *mon)
slavio_irq_info(mon, slavio_intctl);
}
-void cpu_check_irqs(CPUState *env)
+void cpu_check_irqs(CPUSPARCState *env)
{
if (env->pil_in && (env->interrupt_index == 0 ||
(env->interrupt_index & ~15) == TT_EXTINT)) {
@@ -253,7 +253,7 @@ void cpu_check_irqs(CPUState *env)
}
}
-static void cpu_kick_irq(CPUState *env)
+static void cpu_kick_irq(CPUSPARCState *env)
{
env->halted = 0;
cpu_check_irqs(env);
@@ -262,7 +262,7 @@ static void cpu_kick_irq(CPUState *env)
static void cpu_set_irq(void *opaque, int irq, int level)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
if (level) {
trace_sun4m_cpu_set_irq_raise(irq);
@@ -281,7 +281,7 @@ static void dummy_cpu_set_irq(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
cpu_state_reset(env);
env->halted = 0;
@@ -289,7 +289,7 @@ static void main_cpu_reset(void *opaque)
static void secondary_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
cpu_state_reset(env);
env->halted = 1;
@@ -809,7 +809,7 @@ static TypeInfo ram_info = {
static void cpu_devinit(const char *cpu_model, unsigned int id,
uint64_t prom_addr, qemu_irq **cpu_irqs)
{
- CPUState *env;
+ CPUSPARCState *env;
env = cpu_init(cpu_model);
if (!env) {
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 8b043f2..c32eddb 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -243,7 +243,7 @@ static unsigned long sun4u_load_kernel(const char *kernel_filename,
return kernel_size;
}
-void cpu_check_irqs(CPUState *env)
+void cpu_check_irqs(CPUSPARCState *env)
{
uint32_t pil = env->pil_in |
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
@@ -297,7 +297,7 @@ void cpu_check_irqs(CPUState *env)
}
}
-static void cpu_kick_irq(CPUState *env)
+static void cpu_kick_irq(CPUSPARCState *env)
{
env->halted = 0;
cpu_check_irqs(env);
@@ -306,7 +306,7 @@ static void cpu_kick_irq(CPUState *env)
static void cpu_set_irq(void *opaque, int irq, int level)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
if (level) {
CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
@@ -320,7 +320,7 @@ static void cpu_set_irq(void *opaque, int irq, int level)
}
typedef struct ResetData {
- CPUState *env;
+ CPUSPARCState *env;
uint64_t prom_addr;
} ResetData;
@@ -344,7 +344,7 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s)
qemu_get_timer(f, s->qtimer);
}
-static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
+static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
QEMUBHFunc *cb, uint32_t frequency,
uint64_t disabled_mask)
{
@@ -373,7 +373,7 @@ static void cpu_timer_reset(CPUTimer *timer)
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
- CPUState *env = s->env;
+ CPUSPARCState *env = s->env;
static unsigned int nr_resets;
cpu_state_reset(env);
@@ -396,7 +396,7 @@ static void main_cpu_reset(void *opaque)
static void tick_irq(void *opaque)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
CPUTimer* timer = env->tick;
@@ -413,7 +413,7 @@ static void tick_irq(void *opaque)
static void stick_irq(void *opaque)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
CPUTimer* timer = env->stick;
@@ -430,7 +430,7 @@ static void stick_irq(void *opaque)
static void hstick_irq(void *opaque)
{
- CPUState *env = opaque;
+ CPUSPARCState *env = opaque;
CPUTimer* timer = env->hstick;
@@ -714,9 +714,9 @@ static TypeInfo ram_info = {
.class_init = ram_class_init,
};
-static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
+static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
{
- CPUState *env;
+ CPUSPARCState *env;
ResetData *reset_info;
uint32_t tick_frequency = 100*1000000;
@@ -755,7 +755,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
const char *initrd_filename, const char *cpu_model,
const struct hwdef *hwdef)
{
- CPUState *env;
+ CPUSPARCState *env;
M48t59State *nvram;
unsigned int i;
long initrd_size, kernel_size;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 42/44] xtensa hw/: Don't use CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (40 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 41/44] sparc " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
43 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Scripted conversion:
for file in hw/xtensa_*.[hc]; do
sed -i "s/CPUState/CPUXtensaState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/xtensa_lx60.c | 4 ++--
hw/xtensa_pic.c | 16 ++++++++--------
hw/xtensa_sim.c | 2 +-
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 80ba4d7..afdef49 100644
--- a/hw/xtensa_lx60.c
+++ b/hw/xtensa_lx60.c
@@ -148,7 +148,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
static void lx60_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUXtensaState *env = opaque;
cpu_state_reset(env);
}
@@ -164,7 +164,7 @@ static void lx_init(const LxBoardDesc *board,
int be = 0;
#endif
MemoryRegion *system_memory = get_system_memory();
- CPUState *env = NULL;
+ CPUXtensaState *env = NULL;
MemoryRegion *ram, *rom, *system_io;
DriveInfo *dinfo;
pflash_t *flash = NULL;
diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c
index 71d5fc8..653ded6 100644
--- a/hw/xtensa_pic.c
+++ b/hw/xtensa_pic.c
@@ -29,7 +29,7 @@
#include "qemu-log.h"
#include "qemu-timer.h"
-void xtensa_advance_ccount(CPUState *env, uint32_t d)
+void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
{
uint32_t old_ccount = env->sregs[CCOUNT];
@@ -45,7 +45,7 @@ void xtensa_advance_ccount(CPUState *env, uint32_t d)
}
}
-void check_interrupts(CPUState *env)
+void check_interrupts(CPUXtensaState *env)
{
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
@@ -84,7 +84,7 @@ void check_interrupts(CPUState *env)
static void xtensa_set_irq(void *opaque, int irq, int active)
{
- CPUState *env = opaque;
+ CPUXtensaState *env = opaque;
if (irq >= env->config->ninterrupt) {
qemu_log("%s: bad IRQ %d\n", __func__, irq);
@@ -101,12 +101,12 @@ static void xtensa_set_irq(void *opaque, int irq, int active)
}
}
-void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active)
+void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
{
qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
}
-void xtensa_rearm_ccompare_timer(CPUState *env)
+void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
{
int i;
uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
@@ -125,7 +125,7 @@ void xtensa_rearm_ccompare_timer(CPUState *env)
static void xtensa_ccompare_cb(void *opaque)
{
- CPUState *env = opaque;
+ CPUXtensaState *env = opaque;
if (env->halted) {
env->halt_clock = qemu_get_clock_ns(vm_clock);
@@ -137,7 +137,7 @@ static void xtensa_ccompare_cb(void *opaque)
}
}
-void xtensa_irq_init(CPUState *env)
+void xtensa_irq_init(CPUXtensaState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(
xtensa_set_irq, env, env->config->ninterrupt);
@@ -148,7 +148,7 @@ void xtensa_irq_init(CPUState *env)
}
}
-void *xtensa_get_extint(CPUState *env, unsigned extint)
+void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
{
if (extint < env->config->nextint) {
unsigned irq = env->config->extint[extint];
diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
index 445cfde..c7e05dc 100644
--- a/hw/xtensa_sim.c
+++ b/hw/xtensa_sim.c
@@ -47,7 +47,7 @@ static void sim_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUXtensaState *env = NULL;
MemoryRegion *ram, *rom;
int n;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (41 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 42/44] xtensa " Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-13 18:06 ` Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
bsd-user/main.c | 8 ++--
bsd-user/qemu.h | 12 +++---
bsd-user/signal.c | 2 +-
cpu-all.h | 56 +++++++++++-----------
cpu-defs.h | 2 +-
cpu-exec.c | 16 +++---
cpus.c | 76 ++++++++++++++++----------------
darwin-user/main.c | 6 +-
darwin-user/qemu.h | 6 +-
darwin-user/signal.c | 4 +-
def-helper.h | 2 +-
disas.c | 4 +-
disas.h | 2 +-
dyngen-exec.h | 4 +-
exec-all.h | 38 ++++++++--------
exec.c | 114 +++++++++++++++++++++++-----------------------
gdbstub.c | 44 +++++++++---------
gdbstub.h | 16 +++---
gen-icount.h | 8 ++--
kvm-all.c | 54 +++++++++++-----------
kvm-stub.c | 22 +++++-----
kvm.h | 60 ++++++++++++------------
linux-user/elfload.c | 16 +++---
linux-user/main.c | 14 +++---
linux-user/qemu.h | 14 +++---
linux-user/signal.c | 16 +++---
linux-user/syscall.c | 28 ++++++------
monitor.c | 56 +++++++++++-----------
poison.h | 2 +-
softmmu-semi.h | 12 +++---
target-alpha/cpu.h | 2 +-
target-arm/cpu.h | 2 +-
target-cris/cpu.h | 2 +-
target-i386/cpu.h | 2 +-
target-lm32/cpu.h | 2 +-
target-m68k/cpu.h | 2 +-
target-microblaze/cpu.h | 2 +-
target-mips/cpu.h | 2 +-
target-ppc/cpu.h | 2 +-
target-s390x/cpu.h | 2 +-
target-sh4/cpu.h | 2 +-
target-sparc/cpu.h | 2 +-
target-unicore32/cpu.h | 2 +-
target-xtensa/cpu.h | 2 +-
tcg/arm/tcg-target.c | 22 +++++-----
tcg/hppa/tcg-target.c | 8 ++--
tcg/i386/tcg-target.c | 2 +-
tcg/ia64/tcg-target.c | 10 ++--
tcg/mips/tcg-target.c | 14 +++---
tcg/ppc/tcg-target.c | 4 +-
tcg/ppc64/tcg-target.c | 4 +-
tcg/s390/tcg-target.c | 8 ++--
tcg/sparc/tcg-target.c | 4 +-
tcg/tci/tcg-target.c | 2 +-
tcg/tci/tcg-target.h | 2 +-
tci.c | 4 +-
translate-all.c | 4 +-
user-exec.c | 4 +-
xen-all.c | 4 +-
59 files changed, 419 insertions(+), 419 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 78533d5..48cb715 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -70,11 +70,11 @@ int cpu_get_pic_interrupt(CPUX86State *env)
#endif
/* These are no-ops because we are not threadsafe. */
-static inline void cpu_exec_start(CPUState *env)
+static inline void cpu_exec_start(CPUArchState *env)
{
}
-static inline void cpu_exec_end(CPUState *env)
+static inline void cpu_exec_end(CPUArchState *env)
{
}
@@ -713,7 +713,7 @@ static void usage(void)
exit(1);
}
-THREAD CPUState *thread_env;
+THREAD CPUArchState *thread_env;
/* Assumes contents are already zeroed. */
void init_task_state(TaskState *ts)
@@ -737,7 +737,7 @@ int main(int argc, char **argv)
struct target_pt_regs regs1, *regs = ®s1;
struct image_info info1, *info = &info1;
TaskState ts1, *ts = &ts1;
- CPUState *env;
+ CPUArchState *env;
int optind;
const char *r;
int gdbstub_port = 0;
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 1ba2d08..8a5ee3d 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -139,8 +139,8 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6);
void gemu_log(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
-extern THREAD CPUState *thread_env;
-void cpu_loop(CPUState *env);
+extern THREAD CPUArchState *thread_env;
+void cpu_loop(CPUArchState *env);
char *target_strerror(int err);
int get_osversion(void);
void fork_start(void);
@@ -167,13 +167,13 @@ void print_openbsd_syscall_ret(int num, abi_long ret);
extern int do_strace;
/* signal.c */
-void process_pending_signals(CPUState *cpu_env);
+void process_pending_signals(CPUArchState *cpu_env);
void signal_init(void);
-//int queue_signal(CPUState *env, int sig, target_siginfo_t *info);
+//int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info);
//void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info);
//void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo);
-long do_sigreturn(CPUState *env);
-long do_rt_sigreturn(CPUState *env);
+long do_sigreturn(CPUArchState *env);
+long do_rt_sigreturn(CPUArchState *env);
abi_long do_sigaltstack(abi_ulong uss_addr, abi_ulong uoss_addr, abi_ulong sp);
/* mmap.c */
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index 40313c8..445f69e 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -33,6 +33,6 @@ void signal_init(void)
{
}
-void process_pending_signals(CPUState *cpu_env)
+void process_pending_signals(CPUArchState *cpu_env)
{
}
diff --git a/cpu-all.h b/cpu-all.h
index 7586c0d..f16e157 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -322,20 +322,20 @@ void page_set_flags(target_ulong start, target_ulong end, int flags);
int page_check_range(target_ulong start, target_ulong len, int flags);
#endif
-CPUState *cpu_copy(CPUState *env);
-CPUState *qemu_get_cpu(int cpu);
+CPUArchState *cpu_copy(CPUArchState *env);
+CPUArchState *qemu_get_cpu(int cpu);
#define CPU_DUMP_CODE 0x00010000
-void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
int flags);
-void cpu_dump_statistics(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
int flags);
-void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
+void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
-extern CPUState *first_cpu;
-DECLARE_TLS(CPUState *,cpu_single_env);
+extern CPUArchState *first_cpu;
+DECLARE_TLS(CPUArchState *,cpu_single_env);
#define cpu_single_env tls_var(cpu_single_env)
/* Flags for use in ENV->INTERRUPT_PENDING.
@@ -389,23 +389,23 @@ DECLARE_TLS(CPUState *,cpu_single_env);
| CPU_INTERRUPT_TGT_EXT_4)
#ifndef CONFIG_USER_ONLY
-typedef void (*CPUInterruptHandler)(CPUState *, int);
+typedef void (*CPUInterruptHandler)(CPUArchState *, int);
extern CPUInterruptHandler cpu_interrupt_handler;
-static inline void cpu_interrupt(CPUState *s, int mask)
+static inline void cpu_interrupt(CPUArchState *s, int mask)
{
cpu_interrupt_handler(s, mask);
}
#else /* USER_ONLY */
-void cpu_interrupt(CPUState *env, int mask);
+void cpu_interrupt(CPUArchState *env, int mask);
#endif /* USER_ONLY */
-void cpu_reset_interrupt(CPUState *env, int mask);
+void cpu_reset_interrupt(CPUArchState *env, int mask);
-void cpu_exit(CPUState *s);
+void cpu_exit(CPUArchState *s);
-bool qemu_cpu_has_work(CPUState *env);
+bool qemu_cpu_has_work(CPUArchState *env);
/* Breakpoint/watchpoint flags */
#define BP_MEM_READ 0x01
@@ -416,26 +416,26 @@ bool qemu_cpu_has_work(CPUState *env);
#define BP_GDB 0x10
#define BP_CPU 0x20
-int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
+int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
CPUBreakpoint **breakpoint);
-int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
-void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
-void cpu_breakpoint_remove_all(CPUState *env, int mask);
-int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
+int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
+void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
+void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
+int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint);
-int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
+int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
target_ulong len, int flags);
-void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
-void cpu_watchpoint_remove_all(CPUState *env, int mask);
+void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
+void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
-void cpu_single_step(CPUState *env, int enabled);
-void cpu_state_reset(CPUState *s);
-int cpu_is_stopped(CPUState *env);
-void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
+void cpu_single_step(CPUArchState *env, int enabled);
+void cpu_state_reset(CPUArchState *s);
+int cpu_is_stopped(CPUArchState *env);
+void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
@@ -466,7 +466,7 @@ int cpu_str_to_log_mask(const char *str);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
+target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
/* memory API */
@@ -516,12 +516,12 @@ extern int mem_prealloc;
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << 5)
-void cpu_tlb_update_dirty(CPUState *env);
+void cpu_tlb_update_dirty(CPUArchState *env);
void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
#endif /* !CONFIG_USER_ONLY */
-int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write);
#endif /* CPU_ALL_H */
diff --git a/cpu-defs.h b/cpu-defs.h
index 4527cbf..3268968 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -202,7 +202,7 @@ typedef struct CPUWatchpoint {
jmp_buf jmp_env; \
int exception_index; \
\
- CPUState *next_cpu; /* next CPU sharing TB cache */ \
+ CPUArchState *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
uint32_t host_tid; /* host thread ID */ \
int numa_node; /* NUMA node this cpu is belonging to */ \
diff --git a/cpu-exec.c b/cpu-exec.c
index 2bf1735..bd5791f 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -26,12 +26,12 @@ int tb_invalidated_flag;
//#define CONFIG_DEBUG_EXEC
-bool qemu_cpu_has_work(CPUState *env)
+bool qemu_cpu_has_work(CPUArchState *env)
{
return cpu_has_work(env);
}
-void cpu_loop_exit(CPUState *env)
+void cpu_loop_exit(CPUArchState *env)
{
env->current_tb = NULL;
longjmp(env->jmp_env, 1);
@@ -41,7 +41,7 @@ void cpu_loop_exit(CPUState *env)
restored in a state compatible with the CPU emulator
*/
#if defined(CONFIG_SOFTMMU)
-void cpu_resume_from_signal(CPUState *env, void *puc)
+void cpu_resume_from_signal(CPUArchState *env, void *puc)
{
/* XXX: restore cpu registers saved in host registers */
@@ -52,7 +52,7 @@ void cpu_resume_from_signal(CPUState *env, void *puc)
/* Execute the code without caching the generated code. An interpreter
could be used if available. */
-static void cpu_exec_nocache(CPUState *env, int max_cycles,
+static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
TranslationBlock *orig_tb)
{
unsigned long next_tb;
@@ -79,7 +79,7 @@ static void cpu_exec_nocache(CPUState *env, int max_cycles,
tb_free(tb);
}
-static TranslationBlock *tb_find_slow(CPUState *env,
+static TranslationBlock *tb_find_slow(CPUArchState *env,
target_ulong pc,
target_ulong cs_base,
uint64_t flags)
@@ -135,7 +135,7 @@ static TranslationBlock *tb_find_slow(CPUState *env,
return tb;
}
-static inline TranslationBlock *tb_find_fast(CPUState *env)
+static inline TranslationBlock *tb_find_fast(CPUArchState *env)
{
TranslationBlock *tb;
target_ulong cs_base, pc;
@@ -163,7 +163,7 @@ CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
return old_handler;
}
-static void cpu_handle_debug_exception(CPUState *env)
+static void cpu_handle_debug_exception(CPUArchState *env)
{
CPUWatchpoint *wp;
@@ -181,7 +181,7 @@ static void cpu_handle_debug_exception(CPUState *env)
volatile sig_atomic_t exit_request;
-int cpu_exec(CPUState *env)
+int cpu_exec(CPUArchState *env)
{
int ret, interrupt_request;
TranslationBlock *tb;
diff --git a/cpus.c b/cpus.c
index 17b055f..25ba621 100644
--- a/cpus.c
+++ b/cpus.c
@@ -58,7 +58,7 @@
#endif /* CONFIG_LINUX */
-static CPUState *next_cpu;
+static CPUArchState *next_cpu;
/***********************************************************/
/* guest cycle counter */
@@ -89,7 +89,7 @@ TimersState timers_state;
int64_t cpu_get_icount(void)
{
int64_t icount;
- CPUState *env = cpu_single_env;
+ CPUArchState *env = cpu_single_env;
icount = qemu_icount;
if (env) {
@@ -339,7 +339,7 @@ void configure_icount(const char *option)
void hw_error(const char *fmt, ...)
{
va_list ap;
- CPUState *env;
+ CPUArchState *env;
va_start(ap, fmt);
fprintf(stderr, "qemu: hardware error: ");
@@ -359,7 +359,7 @@ void hw_error(const char *fmt, ...)
void cpu_synchronize_all_states(void)
{
- CPUState *cpu;
+ CPUArchState *cpu;
for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
cpu_synchronize_state(cpu);
@@ -368,7 +368,7 @@ void cpu_synchronize_all_states(void)
void cpu_synchronize_all_post_reset(void)
{
- CPUState *cpu;
+ CPUArchState *cpu;
for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
cpu_synchronize_post_reset(cpu);
@@ -377,14 +377,14 @@ void cpu_synchronize_all_post_reset(void)
void cpu_synchronize_all_post_init(void)
{
- CPUState *cpu;
+ CPUArchState *cpu;
for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) {
cpu_synchronize_post_init(cpu);
}
}
-int cpu_is_stopped(CPUState *env)
+int cpu_is_stopped(CPUArchState *env)
{
return !runstate_is_running() || env->stopped;
}
@@ -402,7 +402,7 @@ static void do_vm_stop(RunState state)
}
}
-static int cpu_can_run(CPUState *env)
+static int cpu_can_run(CPUArchState *env)
{
if (env->stop) {
return 0;
@@ -413,7 +413,7 @@ static int cpu_can_run(CPUState *env)
return 1;
}
-static bool cpu_thread_is_idle(CPUState *env)
+static bool cpu_thread_is_idle(CPUArchState *env)
{
if (env->stop || env->queued_work_first) {
return false;
@@ -430,7 +430,7 @@ static bool cpu_thread_is_idle(CPUState *env)
bool all_cpu_threads_idle(void)
{
- CPUState *env;
+ CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (!cpu_thread_is_idle(env)) {
@@ -440,7 +440,7 @@ bool all_cpu_threads_idle(void)
return true;
}
-static void cpu_handle_guest_debug(CPUState *env)
+static void cpu_handle_guest_debug(CPUArchState *env)
{
gdb_set_stop_cpu(env);
qemu_system_debug_request();
@@ -494,7 +494,7 @@ static void qemu_init_sigbus(void)
prctl(PR_MCE_KILL, PR_MCE_KILL_SET, PR_MCE_KILL_EARLY, 0, 0);
}
-static void qemu_kvm_eat_signals(CPUState *env)
+static void qemu_kvm_eat_signals(CPUArchState *env)
{
struct timespec ts = { 0, 0 };
siginfo_t siginfo;
@@ -537,7 +537,7 @@ static void qemu_init_sigbus(void)
{
}
-static void qemu_kvm_eat_signals(CPUState *env)
+static void qemu_kvm_eat_signals(CPUArchState *env)
{
}
#endif /* !CONFIG_LINUX */
@@ -547,7 +547,7 @@ static void dummy_signal(int sig)
{
}
-static void qemu_kvm_init_cpu_signals(CPUState *env)
+static void qemu_kvm_init_cpu_signals(CPUArchState *env)
{
int r;
sigset_t set;
@@ -582,7 +582,7 @@ static void qemu_tcg_init_cpu_signals(void)
}
#else /* _WIN32 */
-static void qemu_kvm_init_cpu_signals(CPUState *env)
+static void qemu_kvm_init_cpu_signals(CPUArchState *env)
{
abort();
}
@@ -619,7 +619,7 @@ void qemu_init_cpu_loop(void)
qemu_thread_get_self(&io_thread);
}
-void run_on_cpu(CPUState *env, void (*func)(void *data), void *data)
+void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data)
{
struct qemu_work_item wi;
@@ -641,14 +641,14 @@ void run_on_cpu(CPUState *env, void (*func)(void *data), void *data)
qemu_cpu_kick(env);
while (!wi.done) {
- CPUState *self_env = cpu_single_env;
+ CPUArchState *self_env = cpu_single_env;
qemu_cond_wait(&qemu_work_cond, &qemu_global_mutex);
cpu_single_env = self_env;
}
}
-static void flush_queued_work(CPUState *env)
+static void flush_queued_work(CPUArchState *env)
{
struct qemu_work_item *wi;
@@ -665,7 +665,7 @@ static void flush_queued_work(CPUState *env)
qemu_cond_broadcast(&qemu_work_cond);
}
-static void qemu_wait_io_event_common(CPUState *env)
+static void qemu_wait_io_event_common(CPUArchState *env)
{
if (env->stop) {
env->stop = 0;
@@ -678,7 +678,7 @@ static void qemu_wait_io_event_common(CPUState *env)
static void qemu_tcg_wait_io_event(void)
{
- CPUState *env;
+ CPUArchState *env;
while (all_cpu_threads_idle()) {
/* Start accounting real time to the virtual clock if the CPUs
@@ -696,7 +696,7 @@ static void qemu_tcg_wait_io_event(void)
}
}
-static void qemu_kvm_wait_io_event(CPUState *env)
+static void qemu_kvm_wait_io_event(CPUArchState *env)
{
while (cpu_thread_is_idle(env)) {
qemu_cond_wait(env->halt_cond, &qemu_global_mutex);
@@ -708,7 +708,7 @@ static void qemu_kvm_wait_io_event(CPUState *env)
static void *qemu_kvm_cpu_thread_fn(void *arg)
{
- CPUState *env = arg;
+ CPUArchState *env = arg;
int r;
qemu_mutex_lock(&qemu_global_mutex);
@@ -745,7 +745,7 @@ static void tcg_exec_all(void);
static void *qemu_tcg_cpu_thread_fn(void *arg)
{
- CPUState *env = arg;
+ CPUArchState *env = arg;
qemu_tcg_init_cpu_signals();
qemu_thread_get_self(env->thread);
@@ -779,7 +779,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
return NULL;
}
-static void qemu_cpu_kick_thread(CPUState *env)
+static void qemu_cpu_kick_thread(CPUArchState *env)
{
#ifndef _WIN32
int err;
@@ -800,7 +800,7 @@ static void qemu_cpu_kick_thread(CPUState *env)
void qemu_cpu_kick(void *_env)
{
- CPUState *env = _env;
+ CPUArchState *env = _env;
qemu_cond_broadcast(env->halt_cond);
if (kvm_enabled() && !env->thread_kicked) {
@@ -825,7 +825,7 @@ void qemu_cpu_kick_self(void)
int qemu_cpu_is_self(void *_env)
{
- CPUState *env = _env;
+ CPUArchState *env = _env;
return qemu_thread_is_self(env->thread);
}
@@ -852,7 +852,7 @@ void qemu_mutex_unlock_iothread(void)
static int all_vcpus_paused(void)
{
- CPUState *penv = first_cpu;
+ CPUArchState *penv = first_cpu;
while (penv) {
if (!penv->stopped) {
@@ -866,7 +866,7 @@ static int all_vcpus_paused(void)
void pause_all_vcpus(void)
{
- CPUState *penv = first_cpu;
+ CPUArchState *penv = first_cpu;
qemu_clock_enable(vm_clock, false);
while (penv) {
@@ -899,7 +899,7 @@ void pause_all_vcpus(void)
void resume_all_vcpus(void)
{
- CPUState *penv = first_cpu;
+ CPUArchState *penv = first_cpu;
qemu_clock_enable(vm_clock, true);
while (penv) {
@@ -912,7 +912,7 @@ void resume_all_vcpus(void)
static void qemu_tcg_init_vcpu(void *_env)
{
- CPUState *env = _env;
+ CPUArchState *env = _env;
/* share a single thread for all cpus with TCG */
if (!tcg_cpu_thread) {
@@ -935,7 +935,7 @@ static void qemu_tcg_init_vcpu(void *_env)
}
}
-static void qemu_kvm_start_vcpu(CPUState *env)
+static void qemu_kvm_start_vcpu(CPUArchState *env)
{
env->thread = g_malloc0(sizeof(QemuThread));
env->halt_cond = g_malloc0(sizeof(QemuCond));
@@ -949,7 +949,7 @@ static void qemu_kvm_start_vcpu(CPUState *env)
void qemu_init_vcpu(void *_env)
{
- CPUState *env = _env;
+ CPUArchState *env = _env;
env->nr_cores = smp_cores;
env->nr_threads = smp_threads;
@@ -996,7 +996,7 @@ void vm_stop_force_state(RunState state)
}
}
-static int tcg_cpu_exec(CPUState *env)
+static int tcg_cpu_exec(CPUArchState *env)
{
int ret;
#ifdef CONFIG_PROFILER
@@ -1045,7 +1045,7 @@ static void tcg_exec_all(void)
next_cpu = first_cpu;
}
for (; next_cpu != NULL && !exit_request; next_cpu = next_cpu->next_cpu) {
- CPUState *env = next_cpu;
+ CPUArchState *env = next_cpu;
qemu_clock_enable(vm_clock,
(env->singlestep_enabled & SSTEP_NOTIMER) == 0);
@@ -1065,7 +1065,7 @@ static void tcg_exec_all(void)
void set_numa_modes(void)
{
- CPUState *env;
+ CPUArchState *env;
int i;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
@@ -1111,7 +1111,7 @@ void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
CpuInfoList *qmp_query_cpus(Error **errp)
{
CpuInfoList *head = NULL, *cur_item = NULL;
- CPUState *env;
+ CPUArchState *env;
for(env = first_cpu; env != NULL; env = env->next_cpu) {
CpuInfoList *info;
@@ -1157,7 +1157,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
{
FILE *f;
uint32_t l;
- CPUState *env;
+ CPUArchState *env;
uint8_t buf[1024];
if (!has_cpu) {
@@ -1232,7 +1232,7 @@ exit:
void qmp_inject_nmi(Error **errp)
{
#if defined(TARGET_I386)
- CPUState *env;
+ CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (!env->apic_state) {
diff --git a/darwin-user/main.c b/darwin-user/main.c
index f5cadc7..544e219 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -71,7 +71,7 @@ void gemu_log(const char *fmt, ...)
va_end(ap);
}
-int cpu_get_pic_interrupt(CPUState *env)
+int cpu_get_pic_interrupt(CPUArchState *env)
{
return -1;
}
@@ -729,7 +729,7 @@ static void usage(void)
}
/* XXX: currently only used for async signals (see signal.c) */
-CPUState *global_env;
+CPUArchState *global_env;
/* used to free thread contexts */
TaskState *first_task_state;
@@ -741,7 +741,7 @@ int main(int argc, char **argv)
const char *log_mask = NULL;
struct target_pt_regs regs1, *regs = ®s1;
TaskState ts1, *ts = &ts1;
- CPUState *env;
+ CPUArchState *env;
int optind;
short use_gdbstub = 0;
const char *r;
diff --git a/darwin-user/qemu.h b/darwin-user/qemu.h
index b6d3e6c..9e16c8e 100644
--- a/darwin-user/qemu.h
+++ b/darwin-user/qemu.h
@@ -104,8 +104,8 @@ void qerror(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
void write_dt(void *ptr, unsigned long addr, unsigned long limit, int flags);
-extern CPUState *global_env;
-void cpu_loop(CPUState *env);
+extern CPUArchState *global_env;
+void cpu_loop(CPUArchState *env);
void init_paths(const char *prefix);
const char *path(const char *pathname);
@@ -122,7 +122,7 @@ void signal_init(void);
int queue_signal(int sig, target_siginfo_t *info);
void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info);
void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo);
-long do_sigreturn(CPUState *env, int num);
+long do_sigreturn(CPUArchState *env, int num);
/* machload.c */
int mach_exec(const char * filename, char ** argv, char ** envp,
diff --git a/darwin-user/signal.c b/darwin-user/signal.c
index 8f9705d..489cb64 100644
--- a/darwin-user/signal.c
+++ b/darwin-user/signal.c
@@ -377,12 +377,12 @@ long do_sigreturn(CPUX86State *env, int num)
#else
static void setup_frame(int sig, struct emulated_sigaction *ka,
- void *set, CPUState *env)
+ void *set, CPUArchState *env)
{
fprintf(stderr, "setup_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env, int num)
+long do_sigreturn(CPUArchState *env, int num)
{
int i = 0;
struct target_sigcontext *scp = get_int_arg(&i, env);
diff --git a/def-helper.h b/def-helper.h
index 8a822c7..5d057d6 100644
--- a/def-helper.h
+++ b/def-helper.h
@@ -52,7 +52,7 @@
#define dh_ctype_tl target_ulong
#define dh_ctype_ptr void *
#define dh_ctype_void void
-#define dh_ctype_env CPUState *
+#define dh_ctype_env CPUArchState *
#define dh_ctype(t) dh_ctype_##t
/* We can't use glue() here because it falls foul of C preprocessor
diff --git a/disas.c b/disas.c
index 3b1fd97..4945c44 100644
--- a/disas.c
+++ b/disas.c
@@ -339,7 +339,7 @@ const char *lookup_symbol(target_ulong orig_addr)
#include "monitor.h"
static int monitor_disas_is_physical;
-static CPUState *monitor_disas_env;
+static CPUArchState *monitor_disas_env;
static int
monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
@@ -363,7 +363,7 @@ monitor_fprintf(FILE *stream, const char *fmt, ...)
return 0;
}
-void monitor_disas(Monitor *mon, CPUState *env,
+void monitor_disas(Monitor *mon, CPUArchState *env,
target_ulong pc, int nb_insn, int is_physical, int flags)
{
int count, i;
diff --git a/disas.h b/disas.h
index f9287f7..3ab42af 100644
--- a/disas.h
+++ b/disas.h
@@ -8,7 +8,7 @@
void disas(FILE *out, void *code, unsigned long size);
void target_disas(FILE *out, target_ulong code, target_ulong size, int flags);
-void monitor_disas(Monitor *mon, CPUState *env,
+void monitor_disas(Monitor *mon, CPUArchState *env,
target_ulong pc, int nb_insn, int is_physical, int flags);
/* Look up symbol for debugging purpose. Returns "" if unknown. */
diff --git a/dyngen-exec.h b/dyngen-exec.h
index 09be9ea..083e20b 100644
--- a/dyngen-exec.h
+++ b/dyngen-exec.h
@@ -61,10 +61,10 @@
#endif
#if defined(AREG0)
-register CPUState *env asm(AREG0);
+register CPUArchState *env asm(AREG0);
#else
/* TODO: Try env = cpu_single_env. */
-extern CPUState *env;
+extern CPUArchState *env;
#endif
#endif /* !defined(__DYNGEN_EXEC_H__) */
diff --git a/exec-all.h b/exec-all.h
index 51d01f2..0fcdaf0 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -76,30 +76,30 @@ extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
#include "qemu-log.h"
-void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
-void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
-void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
+void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
+void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
+void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
int pc_pos);
void cpu_gen_init(void);
-int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
+int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
- CPUState *env, unsigned long searched_pc);
-void cpu_resume_from_signal(CPUState *env1, void *puc);
-void cpu_io_recompile(CPUState *env, void *retaddr);
-TranslationBlock *tb_gen_code(CPUState *env,
+ CPUArchState *env, unsigned long searched_pc);
+void cpu_resume_from_signal(CPUArchState *env1, void *puc);
+void cpu_io_recompile(CPUArchState *env, void *retaddr);
+TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
-void cpu_exec_init(CPUState *env);
-void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
+void cpu_exec_init(CPUArchState *env);
+void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
-void tlb_flush_page(CPUState *env, target_ulong addr);
-void tlb_flush(CPUState *env, int flush_global);
+void tlb_flush_page(CPUArchState *env, target_ulong addr);
+void tlb_flush(CPUArchState *env, int flush_global);
#if !defined(CONFIG_USER_ONLY)
-void tlb_set_page(CPUState *env, target_ulong vaddr,
+void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
int mmu_idx, target_ulong size);
#endif
@@ -182,7 +182,7 @@ static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
}
void tb_free(TranslationBlock *tb);
-void tb_flush(CPUState *env);
+void tb_flush(CPUArchState *env);
void tb_link_page(TranslationBlock *tb,
tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
@@ -304,7 +304,7 @@ void io_mem_write(int index, target_phys_addr_t addr, uint64_t value,
unsigned size);
extern struct MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
-void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr);
#include "softmmu_defs.h"
@@ -332,15 +332,15 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
#endif
#if defined(CONFIG_USER_ONLY)
-static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
+static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
{
return addr;
}
#else
-tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr);
+tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
#endif
-typedef void (CPUDebugExcpHandler)(CPUState *env);
+typedef void (CPUDebugExcpHandler)(CPUArchState *env);
CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
@@ -352,7 +352,7 @@ extern volatile sig_atomic_t exit_request;
/* Deterministic execution requires that IO only be performed on the last
instruction of a TB so that interrupts take effect immediately. */
-static inline int can_do_io(CPUState *env)
+static inline int can_do_io(CPUArchState *env)
{
if (!use_icount) {
return 1;
diff --git a/exec.c b/exec.c
index 1e5bbd6..e95c377 100644
--- a/exec.c
+++ b/exec.c
@@ -123,10 +123,10 @@ static MemoryRegion io_mem_subpage_ram;
#endif
-CPUState *first_cpu;
+CPUArchState *first_cpu;
/* current CPU in the current thread. It is only valid inside
cpu_exec() */
-DEFINE_TLS(CPUState *,cpu_single_env);
+DEFINE_TLS(CPUArchState *,cpu_single_env);
/* 0 = Do not count executed instructions.
1 = Precise instruction counting.
2 = Adaptive rate instruction counting. */
@@ -511,7 +511,7 @@ not_found:
}
static void tlb_protect_code(ram_addr_t ram_addr);
-static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
+static void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
target_ulong vaddr);
#define mmap_lock() do { } while(0)
#define mmap_unlock() do { } while(0)
@@ -663,7 +663,7 @@ void cpu_exec_init_all(void)
static int cpu_common_post_load(void *opaque, int version_id)
{
- CPUState *env = opaque;
+ CPUArchState *env = opaque;
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
version_id is increased. */
@@ -680,16 +680,16 @@ static const VMStateDescription vmstate_cpu_common = {
.minimum_version_id_old = 1,
.post_load = cpu_common_post_load,
.fields = (VMStateField []) {
- VMSTATE_UINT32(halted, CPUState),
- VMSTATE_UINT32(interrupt_request, CPUState),
+ VMSTATE_UINT32(halted, CPUArchState),
+ VMSTATE_UINT32(interrupt_request, CPUArchState),
VMSTATE_END_OF_LIST()
}
};
#endif
-CPUState *qemu_get_cpu(int cpu)
+CPUArchState *qemu_get_cpu(int cpu)
{
- CPUState *env = first_cpu;
+ CPUArchState *env = first_cpu;
while (env) {
if (env->cpu_index == cpu)
@@ -700,9 +700,9 @@ CPUState *qemu_get_cpu(int cpu)
return env;
}
-void cpu_exec_init(CPUState *env)
+void cpu_exec_init(CPUArchState *env)
{
- CPUState **penv;
+ CPUArchState **penv;
int cpu_index;
#if defined(CONFIG_USER_ONLY)
@@ -801,9 +801,9 @@ static void page_flush_tb(void)
/* flush all the translation blocks */
/* XXX: tb_flush is currently not thread safe */
-void tb_flush(CPUState *env1)
+void tb_flush(CPUArchState *env1)
{
- CPUState *env;
+ CPUArchState *env;
#if defined(DEBUG_FLUSH)
printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
(unsigned long)(code_gen_ptr - code_gen_buffer),
@@ -936,7 +936,7 @@ static inline void tb_reset_jump(TranslationBlock *tb, int n)
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
{
- CPUState *env;
+ CPUArchState *env;
PageDesc *p;
unsigned int h, n1;
tb_page_addr_t phys_pc;
@@ -1045,7 +1045,7 @@ static void build_page_bitmap(PageDesc *p)
}
}
-TranslationBlock *tb_gen_code(CPUState *env,
+TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base,
int flags, int cflags)
{
@@ -1092,7 +1092,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access)
{
TranslationBlock *tb, *tb_next, *saved_tb;
- CPUState *env = cpu_single_env;
+ CPUArchState *env = cpu_single_env;
tb_page_addr_t tb_start, tb_end;
PageDesc *p;
int n;
@@ -1229,7 +1229,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
int n;
#ifdef TARGET_HAS_PRECISE_SMC
TranslationBlock *current_tb = NULL;
- CPUState *env = cpu_single_env;
+ CPUArchState *env = cpu_single_env;
int current_tb_modified = 0;
target_ulong current_pc = 0;
target_ulong current_cs_base = 0;
@@ -1459,12 +1459,12 @@ static void tb_reset_jump_recursive(TranslationBlock *tb)
#if defined(TARGET_HAS_ICE)
#if defined(CONFIG_USER_ONLY)
-static void breakpoint_invalidate(CPUState *env, target_ulong pc)
+static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
{
tb_invalidate_phys_page_range(pc, pc + 1, 0);
}
#else
-static void breakpoint_invalidate(CPUState *env, target_ulong pc)
+static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
{
target_phys_addr_t addr;
ram_addr_t ram_addr;
@@ -1485,19 +1485,19 @@ static void breakpoint_invalidate(CPUState *env, target_ulong pc)
#endif /* TARGET_HAS_ICE */
#if defined(CONFIG_USER_ONLY)
-void cpu_watchpoint_remove_all(CPUState *env, int mask)
+void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
{
}
-int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
+int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint)
{
return -ENOSYS;
}
#else
/* Add a watchpoint. */
-int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
+int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint)
{
target_ulong len_mask = ~(len - 1);
@@ -1530,7 +1530,7 @@ int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
}
/* Remove a specific watchpoint. */
-int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
+int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
int flags)
{
target_ulong len_mask = ~(len - 1);
@@ -1547,7 +1547,7 @@ int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
}
/* Remove a specific watchpoint by reference. */
-void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
+void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
{
QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
@@ -1557,7 +1557,7 @@ void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
}
/* Remove all matching watchpoints. */
-void cpu_watchpoint_remove_all(CPUState *env, int mask)
+void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
{
CPUWatchpoint *wp, *next;
@@ -1569,7 +1569,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask)
#endif
/* Add a breakpoint. */
-int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
+int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
CPUBreakpoint **breakpoint)
{
#if defined(TARGET_HAS_ICE)
@@ -1597,7 +1597,7 @@ int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
}
/* Remove a specific breakpoint. */
-int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
+int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
@@ -1615,7 +1615,7 @@ int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
}
/* Remove a specific breakpoint by reference. */
-void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
+void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
{
#if defined(TARGET_HAS_ICE)
QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
@@ -1627,7 +1627,7 @@ void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
}
/* Remove all matching breakpoints. */
-void cpu_breakpoint_remove_all(CPUState *env, int mask)
+void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
{
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp, *next;
@@ -1641,7 +1641,7 @@ void cpu_breakpoint_remove_all(CPUState *env, int mask)
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
-void cpu_single_step(CPUState *env, int enabled)
+void cpu_single_step(CPUArchState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
if (env->singlestep_enabled != enabled) {
@@ -1697,7 +1697,7 @@ void cpu_set_log_filename(const char *filename)
cpu_set_log(loglevel);
}
-static void cpu_unlink_tb(CPUState *env)
+static void cpu_unlink_tb(CPUArchState *env)
{
/* FIXME: TB unchaining isn't SMP safe. For now just ignore the
problem and hope the cpu will stop of its own accord. For userspace
@@ -1719,7 +1719,7 @@ static void cpu_unlink_tb(CPUState *env)
#ifndef CONFIG_USER_ONLY
/* mask must never be zero, except for A20 change call */
-static void tcg_handle_interrupt(CPUState *env, int mask)
+static void tcg_handle_interrupt(CPUArchState *env, int mask)
{
int old_mask;
@@ -1750,19 +1750,19 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
#else /* CONFIG_USER_ONLY */
-void cpu_interrupt(CPUState *env, int mask)
+void cpu_interrupt(CPUArchState *env, int mask)
{
env->interrupt_request |= mask;
cpu_unlink_tb(env);
}
#endif /* CONFIG_USER_ONLY */
-void cpu_reset_interrupt(CPUState *env, int mask)
+void cpu_reset_interrupt(CPUArchState *env, int mask)
{
env->interrupt_request &= ~mask;
}
-void cpu_exit(CPUState *env)
+void cpu_exit(CPUArchState *env)
{
env->exit_request = 1;
cpu_unlink_tb(env);
@@ -1840,7 +1840,7 @@ int cpu_str_to_log_mask(const char *str)
return mask;
}
-void cpu_abort(CPUState *env, const char *fmt, ...)
+void cpu_abort(CPUArchState *env, const char *fmt, ...)
{
va_list ap;
va_list ap2;
@@ -1880,17 +1880,17 @@ void cpu_abort(CPUState *env, const char *fmt, ...)
abort();
}
-CPUState *cpu_copy(CPUState *env)
+CPUArchState *cpu_copy(CPUArchState *env)
{
- CPUState *new_env = cpu_init(env->cpu_model_str);
- CPUState *next_cpu = new_env->next_cpu;
+ CPUArchState *new_env = cpu_init(env->cpu_model_str);
+ CPUArchState *next_cpu = new_env->next_cpu;
int cpu_index = new_env->cpu_index;
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
#endif
- memcpy(new_env, env, sizeof(CPUState));
+ memcpy(new_env, env, sizeof(CPUArchState));
/* Preserve chaining and index. */
new_env->next_cpu = next_cpu;
@@ -1916,7 +1916,7 @@ CPUState *cpu_copy(CPUState *env)
#if !defined(CONFIG_USER_ONLY)
-static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
+static inline void tlb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
{
unsigned int i;
@@ -1950,7 +1950,7 @@ static CPUTLBEntry s_cputlb_empty_entry = {
* entries from the TLB at any time, so flushing more entries than
* required is only an efficiency issue, not a correctness issue.
*/
-void tlb_flush(CPUState *env, int flush_global)
+void tlb_flush(CPUArchState *env, int flush_global)
{
int i;
@@ -1987,7 +1987,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
}
}
-void tlb_flush_page(CPUState *env, target_ulong addr)
+void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
int i;
int mmu_idx;
@@ -2028,7 +2028,7 @@ static void tlb_protect_code(ram_addr_t ram_addr)
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
-static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
+static void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
target_ulong vaddr)
{
cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
@@ -2050,7 +2050,7 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags)
{
- CPUState *env;
+ CPUArchState *env;
unsigned long length, start1;
int i;
@@ -2105,7 +2105,7 @@ static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
}
/* update the TLB according to the current state of the dirty bits */
-void cpu_tlb_update_dirty(CPUState *env)
+void cpu_tlb_update_dirty(CPUArchState *env)
{
int i;
int mmu_idx;
@@ -2123,7 +2123,7 @@ static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
/* update the TLB corresponding to virtual page vaddr
so that it is no longer dirty */
-static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
+static inline void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
{
int i;
int mmu_idx;
@@ -2136,7 +2136,7 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
/* Our TLB does not support large pages, so remember the area covered by
large pages and trigger a full TLB flush if these are invalidated. */
-static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
+static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
target_ulong size)
{
target_ulong mask = ~(size - 1);
@@ -2177,7 +2177,7 @@ static bool is_ram_rom_romd(MemoryRegionSection *s)
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
-void tlb_set_page(CPUState *env, target_ulong vaddr,
+void tlb_set_page(CPUArchState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
int mmu_idx, target_ulong size)
{
@@ -2280,11 +2280,11 @@ void tlb_set_page(CPUState *env, target_ulong vaddr,
#else
-void tlb_flush(CPUState *env, int flush_global)
+void tlb_flush(CPUArchState *env, int flush_global)
{
}
-void tlb_flush_page(CPUState *env, target_ulong addr)
+void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
}
@@ -2545,7 +2545,7 @@ int page_unprotect(target_ulong address, unsigned long pc, void *puc)
return 0;
}
-static inline void tlb_set_dirty(CPUState *env,
+static inline void tlb_set_dirty(CPUArchState *env,
unsigned long addr, target_ulong vaddr)
{
}
@@ -3302,7 +3302,7 @@ static const MemoryRegionOps notdirty_mem_ops = {
/* Generate a debug exception if a watchpoint has been hit. */
static void check_watchpoint(int offset, int len_mask, int flags)
{
- CPUState *env = cpu_single_env;
+ CPUArchState *env = cpu_single_env;
target_ulong pc, cs_base;
TranslationBlock *tb;
target_ulong vaddr;
@@ -3593,7 +3593,7 @@ static void core_begin(MemoryListener *listener)
static void core_commit(MemoryListener *listener)
{
- CPUState *env;
+ CPUArchState *env;
/* since each CPU stores ram addresses in its TLB cache, we must
reset the modified entries */
@@ -3783,7 +3783,7 @@ MemoryRegion *get_system_io(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
-int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l, flags;
@@ -4528,7 +4528,7 @@ void stq_be_phys(target_phys_addr_t addr, uint64_t val)
}
/* virtual memory access for debug (includes writing to ROM) */
-int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
+int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
@@ -4559,7 +4559,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
/* in deterministic execution mode, instructions doing device I/Os
must be at the end of the TB */
-void cpu_io_recompile(CPUState *env, void *retaddr)
+void cpu_io_recompile(CPUArchState *env, void *retaddr)
{
TranslationBlock *tb;
uint32_t n, cflags;
@@ -4673,7 +4673,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
is the offset relative to phys_ram_base */
-tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
+tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
{
int mmu_idx, page_index, pd;
void *p;
diff --git a/gdbstub.c b/gdbstub.c
index 054e16c..b48464d 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -42,7 +42,7 @@
#include "kvm.h"
#ifndef TARGET_CPU_MEMORY_RW_DEBUG
-static inline int target_memory_rw_debug(CPUState *env, target_ulong addr,
+static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
return cpu_memory_rw_debug(env, addr, buf, len, is_write);
@@ -287,9 +287,9 @@ enum RSState {
RS_SYSCALL,
};
typedef struct GDBState {
- CPUState *c_cpu; /* current CPU for step/continue ops */
- CPUState *g_cpu; /* current CPU for other ops */
- CPUState *query_cpu; /* for q{f|s}ThreadInfo */
+ CPUArchState *c_cpu; /* current CPU for step/continue ops */
+ CPUArchState *g_cpu; /* current CPU for other ops */
+ CPUArchState *query_cpu; /* for q{f|s}ThreadInfo */
enum RSState state; /* parsing state */
char line_buf[MAX_PACKET_LENGTH];
int line_buf_index;
@@ -1655,12 +1655,12 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 0
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
{
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
{
return 0;
}
@@ -1736,7 +1736,7 @@ static const char *get_feature_xml(const char *p, const char **newp)
}
#endif
-static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
+static int gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int reg)
{
GDBRegisterState *r;
@@ -1751,7 +1751,7 @@ static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
return 0;
}
-static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
+static int gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int reg)
{
GDBRegisterState *r;
@@ -1773,7 +1773,7 @@ static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
*/
-void gdb_register_coprocessor(CPUState * env,
+void gdb_register_coprocessor(CPUArchState * env,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos)
{
@@ -1820,7 +1820,7 @@ static const int xlat_gdb_type[] = {
static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
{
- CPUState *env;
+ CPUArchState *env;
int err = 0;
if (kvm_enabled())
@@ -1854,7 +1854,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
{
- CPUState *env;
+ CPUArchState *env;
int err = 0;
if (kvm_enabled())
@@ -1887,7 +1887,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
static void gdb_breakpoint_remove_all(void)
{
- CPUState *env;
+ CPUArchState *env;
if (kvm_enabled()) {
kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
@@ -1939,7 +1939,7 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
#endif
}
-static inline int gdb_id(CPUState *env)
+static inline int gdb_id(CPUArchState *env)
{
#if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
return env->host_tid;
@@ -1948,9 +1948,9 @@ static inline int gdb_id(CPUState *env)
#endif
}
-static CPUState *find_cpu(uint32_t thread_id)
+static CPUArchState *find_cpu(uint32_t thread_id)
{
- CPUState *env;
+ CPUArchState *env;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (gdb_id(env) == thread_id) {
@@ -1963,7 +1963,7 @@ static CPUState *find_cpu(uint32_t thread_id)
static int gdb_handle_packet(GDBState *s, const char *line_buf)
{
- CPUState *env;
+ CPUArchState *env;
const char *p;
uint32_t thread;
int ch, reg_size, type, res;
@@ -2381,7 +2381,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
return RS_IDLE;
}
-void gdb_set_stop_cpu(CPUState *env)
+void gdb_set_stop_cpu(CPUArchState *env)
{
gdbserver_state->c_cpu = env;
gdbserver_state->g_cpu = env;
@@ -2391,7 +2391,7 @@ void gdb_set_stop_cpu(CPUState *env)
static void gdb_vm_state_change(void *opaque, int running, RunState state)
{
GDBState *s = gdbserver_state;
- CPUState *env = s->c_cpu;
+ CPUArchState *env = s->c_cpu;
char buf[256];
const char *type;
int ret;
@@ -2600,7 +2600,7 @@ static void gdb_read_byte(GDBState *s, int ch)
}
/* Tell the remote gdb that the process has exited. */
-void gdb_exit(CPUState *env, int code)
+void gdb_exit(CPUArchState *env, int code)
{
GDBState *s;
char buf[4];
@@ -2640,7 +2640,7 @@ gdb_queuesig (void)
}
int
-gdb_handlesig (CPUState *env, int sig)
+gdb_handlesig (CPUArchState *env, int sig)
{
GDBState *s;
char buf[256];
@@ -2689,7 +2689,7 @@ gdb_handlesig (CPUState *env, int sig)
}
/* Tell the remote gdb that the process has exited due to SIG. */
-void gdb_signalled(CPUState *env, int sig)
+void gdb_signalled(CPUArchState *env, int sig)
{
GDBState *s;
char buf[4];
@@ -2785,7 +2785,7 @@ int gdbserver_start(int port)
}
/* Disable gdb stub for child processes. */
-void gdbserver_fork(CPUState *env)
+void gdbserver_fork(CPUArchState *env)
{
GDBState *s = gdbserver_state;
if (gdbserver_fd < 0 || s->fd < 0)
diff --git a/gdbstub.h b/gdbstub.h
index d82334f..b44e275 100644
--- a/gdbstub.h
+++ b/gdbstub.h
@@ -11,22 +11,22 @@
#define GDB_WATCHPOINT_ACCESS 4
#ifdef NEED_CPU_H
-typedef void (*gdb_syscall_complete_cb)(CPUState *env,
+typedef void (*gdb_syscall_complete_cb)(CPUArchState *env,
target_ulong ret, target_ulong err);
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...);
int use_gdb_syscalls(void);
-void gdb_set_stop_cpu(CPUState *env);
-void gdb_exit(CPUState *, int);
+void gdb_set_stop_cpu(CPUArchState *env);
+void gdb_exit(CPUArchState *, int);
#ifdef CONFIG_USER_ONLY
int gdb_queuesig (void);
-int gdb_handlesig (CPUState *, int);
-void gdb_signalled(CPUState *, int);
-void gdbserver_fork(CPUState *);
+int gdb_handlesig (CPUArchState *, int);
+void gdb_signalled(CPUArchState *, int);
+void gdbserver_fork(CPUArchState *);
#endif
/* Get or set a register. Returns the size of the register. */
-typedef int (*gdb_reg_cb)(CPUState *env, uint8_t *buf, int reg);
-void gdb_register_coprocessor(CPUState *env,
+typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
+void gdb_register_coprocessor(CPUArchState *env,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos);
diff --git a/gen-icount.h b/gen-icount.h
index 5fb3829..430cb44 100644
--- a/gen-icount.h
+++ b/gen-icount.h
@@ -14,13 +14,13 @@ static inline void gen_icount_start(void)
icount_label = gen_new_label();
count = tcg_temp_local_new_i32();
- tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32));
+ tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32));
/* This is a horrid hack to allow fixing up the value later. */
icount_arg = gen_opparam_ptr + 1;
tcg_gen_subi_i32(count, count, 0xdeadbeef);
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label);
- tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low));
+ tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low));
tcg_temp_free_i32(count);
}
@@ -36,13 +36,13 @@ static void gen_icount_end(TranslationBlock *tb, int num_insns)
static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
tcg_temp_free_i32(tmp);
}
static inline void gen_io_end(void)
{
TCGv_i32 tmp = tcg_const_i32(0);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
tcg_temp_free_i32(tmp);
}
diff --git a/kvm-all.c b/kvm-all.c
index 3c6b4f0..42e5e23 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -190,7 +190,7 @@ static int kvm_set_user_memory_region(KVMState *s, KVMSlot *slot)
static void kvm_reset_vcpu(void *opaque)
{
- CPUState *env = opaque;
+ CPUArchState *env = opaque;
kvm_arch_reset_vcpu(env);
}
@@ -200,7 +200,7 @@ int kvm_pit_in_kernel(void)
return kvm_state->pit_in_kernel;
}
-int kvm_init_vcpu(CPUState *env)
+int kvm_init_vcpu(CPUArchState *env)
{
KVMState *s = kvm_state;
long mmap_size;
@@ -830,7 +830,7 @@ static MemoryListener kvm_memory_listener = {
.priority = 10,
};
-static void kvm_handle_interrupt(CPUState *env, int mask)
+static void kvm_handle_interrupt(CPUArchState *env, int mask)
{
env->interrupt_request |= mask;
@@ -1135,7 +1135,7 @@ static void kvm_handle_io(uint16_t port, void *data, int direction, int size,
}
}
-static int kvm_handle_internal_error(CPUState *env, struct kvm_run *run)
+static int kvm_handle_internal_error(CPUArchState *env, struct kvm_run *run)
{
fprintf(stderr, "KVM internal error.");
if (kvm_check_extension(kvm_state, KVM_CAP_INTERNAL_ERROR_DATA)) {
@@ -1190,7 +1190,7 @@ void kvm_flush_coalesced_mmio_buffer(void)
static void do_kvm_cpu_synchronize_state(void *_env)
{
- CPUState *env = _env;
+ CPUArchState *env = _env;
if (!env->kvm_vcpu_dirty) {
kvm_arch_get_registers(env);
@@ -1198,26 +1198,26 @@ static void do_kvm_cpu_synchronize_state(void *_env)
}
}
-void kvm_cpu_synchronize_state(CPUState *env)
+void kvm_cpu_synchronize_state(CPUArchState *env)
{
if (!env->kvm_vcpu_dirty) {
run_on_cpu(env, do_kvm_cpu_synchronize_state, env);
}
}
-void kvm_cpu_synchronize_post_reset(CPUState *env)
+void kvm_cpu_synchronize_post_reset(CPUArchState *env)
{
kvm_arch_put_registers(env, KVM_PUT_RESET_STATE);
env->kvm_vcpu_dirty = 0;
}
-void kvm_cpu_synchronize_post_init(CPUState *env)
+void kvm_cpu_synchronize_post_init(CPUArchState *env)
{
kvm_arch_put_registers(env, KVM_PUT_FULL_STATE);
env->kvm_vcpu_dirty = 0;
}
-int kvm_cpu_exec(CPUState *env)
+int kvm_cpu_exec(CPUArchState *env)
{
struct kvm_run *run = env->kvm_run;
int ret, run_ret;
@@ -1350,7 +1350,7 @@ int kvm_vm_ioctl(KVMState *s, int type, ...)
return ret;
}
-int kvm_vcpu_ioctl(CPUState *env, int type, ...)
+int kvm_vcpu_ioctl(CPUArchState *env, int type, ...)
{
int ret;
void *arg;
@@ -1439,7 +1439,7 @@ void kvm_setup_guest_memory(void *start, size_t size)
}
#ifdef KVM_CAP_SET_GUEST_DEBUG
-struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *env,
+struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUArchState *env,
target_ulong pc)
{
struct kvm_sw_breakpoint *bp;
@@ -1452,26 +1452,26 @@ struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *env,
return NULL;
}
-int kvm_sw_breakpoints_active(CPUState *env)
+int kvm_sw_breakpoints_active(CPUArchState *env)
{
return !QTAILQ_EMPTY(&env->kvm_state->kvm_sw_breakpoints);
}
struct kvm_set_guest_debug_data {
struct kvm_guest_debug dbg;
- CPUState *env;
+ CPUArchState *env;
int err;
};
static void kvm_invoke_set_guest_debug(void *data)
{
struct kvm_set_guest_debug_data *dbg_data = data;
- CPUState *env = dbg_data->env;
+ CPUArchState *env = dbg_data->env;
dbg_data->err = kvm_vcpu_ioctl(env, KVM_SET_GUEST_DEBUG, &dbg_data->dbg);
}
-int kvm_update_guest_debug(CPUState *env, unsigned long reinject_trap)
+int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
{
struct kvm_set_guest_debug_data data;
@@ -1487,11 +1487,11 @@ int kvm_update_guest_debug(CPUState *env, unsigned long reinject_trap)
return data.err;
}
-int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_insert_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type)
{
struct kvm_sw_breakpoint *bp;
- CPUState *env;
+ CPUArchState *env;
int err;
if (type == GDB_BREAKPOINT_SW) {
@@ -1532,11 +1532,11 @@ int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
return 0;
}
-int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_remove_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type)
{
struct kvm_sw_breakpoint *bp;
- CPUState *env;
+ CPUArchState *env;
int err;
if (type == GDB_BREAKPOINT_SW) {
@@ -1573,11 +1573,11 @@ int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
return 0;
}
-void kvm_remove_all_breakpoints(CPUState *current_env)
+void kvm_remove_all_breakpoints(CPUArchState *current_env)
{
struct kvm_sw_breakpoint *bp, *next;
KVMState *s = current_env->kvm_state;
- CPUState *env;
+ CPUArchState *env;
QTAILQ_FOREACH_SAFE(bp, &s->kvm_sw_breakpoints, entry, next) {
if (kvm_arch_remove_sw_breakpoint(current_env, bp) != 0) {
@@ -1598,29 +1598,29 @@ void kvm_remove_all_breakpoints(CPUState *current_env)
#else /* !KVM_CAP_SET_GUEST_DEBUG */
-int kvm_update_guest_debug(CPUState *env, unsigned long reinject_trap)
+int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
{
return -EINVAL;
}
-int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_insert_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_remove_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-void kvm_remove_all_breakpoints(CPUState *current_env)
+void kvm_remove_all_breakpoints(CPUArchState *current_env)
{
}
#endif /* !KVM_CAP_SET_GUEST_DEBUG */
-int kvm_set_signal_mask(CPUState *env, const sigset_t *sigset)
+int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset)
{
struct kvm_signal_mask *sigmask;
int r;
@@ -1690,7 +1690,7 @@ int kvm_set_ioeventfd_pio_word(int fd, uint16_t addr, uint16_t val, bool assign)
return 0;
}
-int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+int kvm_on_sigbus_vcpu(CPUArchState *env, int code, void *addr)
{
return kvm_arch_on_sigbus_vcpu(env, code, addr);
}
diff --git a/kvm-stub.c b/kvm-stub.c
index 1f1c686..69a1228 100644
--- a/kvm-stub.c
+++ b/kvm-stub.c
@@ -22,7 +22,7 @@ int kvm_pit_in_kernel(void)
}
-int kvm_init_vcpu(CPUState *env)
+int kvm_init_vcpu(CPUArchState *env)
{
return -ENOSYS;
}
@@ -46,19 +46,19 @@ void kvm_flush_coalesced_mmio_buffer(void)
{
}
-void kvm_cpu_synchronize_state(CPUState *env)
+void kvm_cpu_synchronize_state(CPUArchState *env)
{
}
-void kvm_cpu_synchronize_post_reset(CPUState *env)
+void kvm_cpu_synchronize_post_reset(CPUArchState *env)
{
}
-void kvm_cpu_synchronize_post_init(CPUState *env)
+void kvm_cpu_synchronize_post_init(CPUArchState *env)
{
}
-int kvm_cpu_exec(CPUState *env)
+int kvm_cpu_exec(CPUArchState *env)
{
abort ();
}
@@ -87,29 +87,29 @@ void kvm_setup_guest_memory(void *start, size_t size)
{
}
-int kvm_update_guest_debug(CPUState *env, unsigned long reinject_trap)
+int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap)
{
return -ENOSYS;
}
-int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_insert_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_remove_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type)
{
return -EINVAL;
}
-void kvm_remove_all_breakpoints(CPUState *current_env)
+void kvm_remove_all_breakpoints(CPUArchState *current_env)
{
}
#ifndef _WIN32
-int kvm_set_signal_mask(CPUState *env, const sigset_t *sigset)
+int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset)
{
abort();
}
@@ -125,7 +125,7 @@ int kvm_set_ioeventfd_mmio_long(int fd, uint32_t adr, uint32_t val, bool assign)
return -ENOSYS;
}
-int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
+int kvm_on_sigbus_vcpu(CPUArchState *env, int code, void *addr)
{
return 1;
}
diff --git a/kvm.h b/kvm.h
index 8ef4476..330f17b 100644
--- a/kvm.h
+++ b/kvm.h
@@ -61,9 +61,9 @@ int kvm_has_gsi_routing(void);
int kvm_allows_irq0_override(void);
#ifdef NEED_CPU_H
-int kvm_init_vcpu(CPUState *env);
+int kvm_init_vcpu(CPUArchState *env);
-int kvm_cpu_exec(CPUState *env);
+int kvm_cpu_exec(CPUArchState *env);
#if !defined(CONFIG_USER_ONLY)
void kvm_setup_guest_memory(void *start, size_t size);
@@ -73,19 +73,19 @@ int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
void kvm_flush_coalesced_mmio_buffer(void);
#endif
-int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_insert_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type);
-int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
+int kvm_remove_breakpoint(CPUArchState *current_env, target_ulong addr,
target_ulong len, int type);
-void kvm_remove_all_breakpoints(CPUState *current_env);
-int kvm_update_guest_debug(CPUState *env, unsigned long reinject_trap);
+void kvm_remove_all_breakpoints(CPUArchState *current_env);
+int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap);
#ifndef _WIN32
-int kvm_set_signal_mask(CPUState *env, const sigset_t *sigset);
+int kvm_set_signal_mask(CPUArchState *env, const sigset_t *sigset);
#endif
int kvm_pit_in_kernel(void);
-int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr);
+int kvm_on_sigbus_vcpu(CPUArchState *env, int code, void *addr);
int kvm_on_sigbus(int code, void *addr);
/* internal API */
@@ -98,20 +98,20 @@ int kvm_ioctl(KVMState *s, int type, ...);
int kvm_vm_ioctl(KVMState *s, int type, ...);
-int kvm_vcpu_ioctl(CPUState *env, int type, ...);
+int kvm_vcpu_ioctl(CPUArchState *env, int type, ...);
/* Arch specific hooks */
extern const KVMCapabilityInfo kvm_arch_required_capabilities[];
-void kvm_arch_pre_run(CPUState *env, struct kvm_run *run);
-void kvm_arch_post_run(CPUState *env, struct kvm_run *run);
+void kvm_arch_pre_run(CPUArchState *env, struct kvm_run *run);
+void kvm_arch_post_run(CPUArchState *env, struct kvm_run *run);
-int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run);
+int kvm_arch_handle_exit(CPUArchState *env, struct kvm_run *run);
-int kvm_arch_process_async_events(CPUState *env);
+int kvm_arch_process_async_events(CPUArchState *env);
-int kvm_arch_get_registers(CPUState *env);
+int kvm_arch_get_registers(CPUArchState *env);
/* state subset only touched by the VCPU itself during runtime */
#define KVM_PUT_RUNTIME_STATE 1
@@ -120,15 +120,15 @@ int kvm_arch_get_registers(CPUState *env);
/* full state set, modified during initialization or on vmload */
#define KVM_PUT_FULL_STATE 3
-int kvm_arch_put_registers(CPUState *env, int level);
+int kvm_arch_put_registers(CPUArchState *env, int level);
int kvm_arch_init(KVMState *s);
-int kvm_arch_init_vcpu(CPUState *env);
+int kvm_arch_init_vcpu(CPUArchState *env);
-void kvm_arch_reset_vcpu(CPUState *env);
+void kvm_arch_reset_vcpu(CPUArchState *env);
-int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr);
+int kvm_arch_on_sigbus_vcpu(CPUArchState *env, int code, void *addr);
int kvm_arch_on_sigbus(int code, void *addr);
void kvm_arch_init_irq_routing(KVMState *s);
@@ -153,14 +153,14 @@ struct kvm_sw_breakpoint {
QTAILQ_HEAD(kvm_sw_breakpoint_head, kvm_sw_breakpoint);
-struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *env,
+struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUArchState *env,
target_ulong pc);
-int kvm_sw_breakpoints_active(CPUState *env);
+int kvm_sw_breakpoints_active(CPUArchState *env);
-int kvm_arch_insert_sw_breakpoint(CPUState *current_env,
+int kvm_arch_insert_sw_breakpoint(CPUArchState *current_env,
struct kvm_sw_breakpoint *bp);
-int kvm_arch_remove_sw_breakpoint(CPUState *current_env,
+int kvm_arch_remove_sw_breakpoint(CPUArchState *current_env,
struct kvm_sw_breakpoint *bp);
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
target_ulong len, int type);
@@ -168,35 +168,35 @@ int kvm_arch_remove_hw_breakpoint(target_ulong addr,
target_ulong len, int type);
void kvm_arch_remove_all_hw_breakpoints(void);
-void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg);
+void kvm_arch_update_guest_debug(CPUArchState *env, struct kvm_guest_debug *dbg);
-bool kvm_arch_stop_on_emulation_error(CPUState *env);
+bool kvm_arch_stop_on_emulation_error(CPUArchState *env);
int kvm_check_extension(KVMState *s, unsigned int extension);
uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
uint32_t index, int reg);
-void kvm_cpu_synchronize_state(CPUState *env);
-void kvm_cpu_synchronize_post_reset(CPUState *env);
-void kvm_cpu_synchronize_post_init(CPUState *env);
+void kvm_cpu_synchronize_state(CPUArchState *env);
+void kvm_cpu_synchronize_post_reset(CPUArchState *env);
+void kvm_cpu_synchronize_post_init(CPUArchState *env);
/* generic hooks - to be moved/refactored once there are more users */
-static inline void cpu_synchronize_state(CPUState *env)
+static inline void cpu_synchronize_state(CPUArchState *env)
{
if (kvm_enabled()) {
kvm_cpu_synchronize_state(env);
}
}
-static inline void cpu_synchronize_post_reset(CPUState *env)
+static inline void cpu_synchronize_post_reset(CPUArchState *env)
{
if (kvm_enabled()) {
kvm_cpu_synchronize_post_reset(env);
}
}
-static inline void cpu_synchronize_post_init(CPUState *env)
+static inline void cpu_synchronize_post_init(CPUArchState *env)
{
if (kvm_enabled()) {
kvm_cpu_synchronize_post_init(env);
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 48e3232..e502b39 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1044,7 +1044,7 @@ static inline void bswap_sym(struct elf_sym *sym) { }
#endif
#ifdef USE_ELF_CORE_DUMP
-static int elf_core_dump(int, const CPUState *);
+static int elf_core_dump(int, const CPUArchState *);
#endif /* USE_ELF_CORE_DUMP */
static void load_symbols(struct elfhdr *hdr, int fd, abi_ulong load_bias);
@@ -1930,7 +1930,7 @@ int load_elf_binary(struct linux_binprm * bprm, struct target_pt_regs * regs,
* from given cpu into just specified register set. Prototype is:
*
* static void elf_core_copy_regs(taret_elf_gregset_t *regs,
- * const CPUState *env);
+ * const CPUArchState *env);
*
* Parameters:
* regs - copy register values into here (allocated and zeroed by caller)
@@ -2054,8 +2054,8 @@ static void fill_auxv_note(struct memelfnote *, const TaskState *);
static void fill_elf_note_phdr(struct elf_phdr *, int, off_t);
static size_t note_size(const struct memelfnote *);
static void free_note_info(struct elf_note_info *);
-static int fill_note_info(struct elf_note_info *, long, const CPUState *);
-static void fill_thread_info(struct elf_note_info *, const CPUState *);
+static int fill_note_info(struct elf_note_info *, long, const CPUArchState *);
+static void fill_thread_info(struct elf_note_info *, const CPUArchState *);
static int core_dump_filename(const TaskState *, char *, size_t);
static int dump_write(int, const void *, size_t);
@@ -2448,7 +2448,7 @@ static int write_note(struct memelfnote *men, int fd)
return (0);
}
-static void fill_thread_info(struct elf_note_info *info, const CPUState *env)
+static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env)
{
TaskState *ts = (TaskState *)env->opaque;
struct elf_thread_status *ets;
@@ -2466,10 +2466,10 @@ static void fill_thread_info(struct elf_note_info *info, const CPUState *env)
}
static int fill_note_info(struct elf_note_info *info,
- long signr, const CPUState *env)
+ long signr, const CPUArchState *env)
{
#define NUMNOTES 3
- CPUState *cpu = NULL;
+ CPUArchState *cpu = NULL;
TaskState *ts = (TaskState *)env->opaque;
int i;
@@ -2595,7 +2595,7 @@ static int write_note_info(struct elf_note_info *info, int fd)
* handler (provided that target process haven't registered
* handler for that) that does the dump when signal is received.
*/
-static int elf_core_dump(int signr, const CPUState *env)
+static int elf_core_dump(int signr, const CPUArchState *env)
{
const TaskState *ts = (const TaskState *)env->opaque;
struct vm_area_struct *vma = NULL;
diff --git a/linux-user/main.c b/linux-user/main.c
index 3b48882..962677e 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -146,7 +146,7 @@ static inline void exclusive_idle(void)
Must only be called from outside cpu_arm_exec. */
static inline void start_exclusive(void)
{
- CPUState *other;
+ CPUArchState *other;
pthread_mutex_lock(&exclusive_lock);
exclusive_idle();
@@ -172,7 +172,7 @@ static inline void end_exclusive(void)
}
/* Wait for exclusive ops to finish, and begin cpu execution. */
-static inline void cpu_exec_start(CPUState *env)
+static inline void cpu_exec_start(CPUArchState *env)
{
pthread_mutex_lock(&exclusive_lock);
exclusive_idle();
@@ -181,7 +181,7 @@ static inline void cpu_exec_start(CPUState *env)
}
/* Mark cpu as not executing, and release pending exclusive ops. */
-static inline void cpu_exec_end(CPUState *env)
+static inline void cpu_exec_end(CPUArchState *env)
{
pthread_mutex_lock(&exclusive_lock);
env->running = 0;
@@ -206,11 +206,11 @@ void cpu_list_unlock(void)
}
#else /* if !CONFIG_USE_NPTL */
/* These are no-ops because we are not threadsafe. */
-static inline void cpu_exec_start(CPUState *env)
+static inline void cpu_exec_start(CPUArchState *env)
{
}
-static inline void cpu_exec_end(CPUState *env)
+static inline void cpu_exec_end(CPUArchState *env)
{
}
@@ -2888,7 +2888,7 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
-THREAD CPUState *thread_env;
+THREAD CPUArchState *thread_env;
void task_settid(TaskState *ts)
{
@@ -3277,7 +3277,7 @@ int main(int argc, char **argv, char **envp)
struct image_info info1, *info = &info1;
struct linux_binprm bprm;
TaskState *ts;
- CPUState *env;
+ CPUArchState *env;
int optind;
char **target_environ, **wrk;
char **target_argv;
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 308dbc0..6889567 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -171,7 +171,7 @@ struct linux_binprm {
char **argv;
char **envp;
char * filename; /* Name of binary */
- int (*core_dump)(int, const CPUState *); /* coredump routine */
+ int (*core_dump)(int, const CPUArchState *); /* coredump routine */
};
void do_init_thread(struct target_pt_regs *regs, struct image_info *infop);
@@ -196,8 +196,8 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg5, abi_long arg6, abi_long arg7,
abi_long arg8);
void gemu_log(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
-extern THREAD CPUState *thread_env;
-void cpu_loop(CPUState *env);
+extern THREAD CPUArchState *thread_env;
+void cpu_loop(CPUArchState *env);
char *target_strerror(int err);
int get_osversion(void);
void fork_start(void);
@@ -219,15 +219,15 @@ void print_syscall_ret(int num, abi_long arg1);
extern int do_strace;
/* signal.c */
-void process_pending_signals(CPUState *cpu_env);
+void process_pending_signals(CPUArchState *cpu_env);
void signal_init(void);
-int queue_signal(CPUState *env, int sig, target_siginfo_t *info);
+int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info);
void host_to_target_siginfo(target_siginfo_t *tinfo, const siginfo_t *info);
void target_to_host_siginfo(siginfo_t *info, const target_siginfo_t *tinfo);
int target_to_host_signal(int sig);
int host_to_target_signal(int sig);
-long do_sigreturn(CPUState *env);
-long do_rt_sigreturn(CPUState *env);
+long do_sigreturn(CPUArchState *env);
+long do_rt_sigreturn(CPUArchState *env);
abi_long do_sigaltstack(abi_ulong uss_addr, abi_ulong uoss_addr, abi_ulong sp);
#ifdef TARGET_I386
diff --git a/linux-user/signal.c b/linux-user/signal.c
index f44f78e..fca51e2 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -347,7 +347,7 @@ void signal_init(void)
/* signal queue handling */
-static inline struct sigqueue *alloc_sigqueue(CPUState *env)
+static inline struct sigqueue *alloc_sigqueue(CPUArchState *env)
{
TaskState *ts = env->opaque;
struct sigqueue *q = ts->first_free;
@@ -357,7 +357,7 @@ static inline struct sigqueue *alloc_sigqueue(CPUState *env)
return q;
}
-static inline void free_sigqueue(CPUState *env, struct sigqueue *q)
+static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q)
{
TaskState *ts = env->opaque;
q->next = ts->first_free;
@@ -415,7 +415,7 @@ static void QEMU_NORETURN force_sig(int target_sig)
/* queue a signal so that it will be send to the virtual CPU as soon
as possible */
-int queue_signal(CPUState *env, int sig, target_siginfo_t *info)
+int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info)
{
TaskState *ts = env->opaque;
struct emulated_sigtable *k;
@@ -5214,25 +5214,25 @@ long do_rt_sigreturn(CPUAlphaState *env)
#else
static void setup_frame(int sig, struct target_sigaction *ka,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUArchState *env)
{
fprintf(stderr, "setup_frame: not implemented\n");
}
static void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
- target_sigset_t *set, CPUState *env)
+ target_sigset_t *set, CPUArchState *env)
{
fprintf(stderr, "setup_rt_frame: not implemented\n");
}
-long do_sigreturn(CPUState *env)
+long do_sigreturn(CPUArchState *env)
{
fprintf(stderr, "do_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
}
-long do_rt_sigreturn(CPUState *env)
+long do_rt_sigreturn(CPUArchState *env)
{
fprintf(stderr, "do_rt_sigreturn: not implemented\n");
return -TARGET_ENOSYS;
@@ -5240,7 +5240,7 @@ long do_rt_sigreturn(CPUState *env)
#endif
-void process_pending_signals(CPUState *cpu_env)
+void process_pending_signals(CPUArchState *cpu_env)
{
int sig;
abi_ulong handler;
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 29888bd..9f5e53a 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -3955,7 +3955,7 @@ static abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
static pthread_mutex_t clone_lock = PTHREAD_MUTEX_INITIALIZER;
typedef struct {
- CPUState *env;
+ CPUArchState *env;
pthread_mutex_t mutex;
pthread_cond_t cond;
pthread_t thread;
@@ -3968,7 +3968,7 @@ typedef struct {
static void *clone_func(void *arg)
{
new_thread_info *info = arg;
- CPUState *env;
+ CPUArchState *env;
TaskState *ts;
env = info->env;
@@ -3998,7 +3998,7 @@ static void *clone_func(void *arg)
static int clone_func(void *arg)
{
- CPUState *env = arg;
+ CPUArchState *env = arg;
cpu_loop(env);
/* never exits */
return 0;
@@ -4007,13 +4007,13 @@ static int clone_func(void *arg)
/* do_fork() Must return host values and target errnos (unlike most
do_*() functions). */
-static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp,
+static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
abi_ulong parent_tidptr, target_ulong newtls,
abi_ulong child_tidptr)
{
int ret;
TaskState *ts;
- CPUState *new_env;
+ CPUArchState *new_env;
#if defined(CONFIG_USE_NPTL)
unsigned int nptl_flags;
sigset_t sigmask;
@@ -4640,7 +4640,7 @@ int get_osversion(void)
static int open_self_maps(void *cpu_env, int fd)
{
- TaskState *ts = ((CPUState *)cpu_env)->opaque;
+ TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
dprintf(fd, "%08llx-%08llx rw-p %08llx 00:00 0 [stack]\n",
(unsigned long long)ts->info->stack_limit,
@@ -4653,7 +4653,7 @@ static int open_self_maps(void *cpu_env, int fd)
static int open_self_stat(void *cpu_env, int fd)
{
- TaskState *ts = ((CPUState *)cpu_env)->opaque;
+ TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
abi_ulong start_stack = ts->info->start_stack;
int i;
@@ -4678,7 +4678,7 @@ static int open_self_stat(void *cpu_env, int fd)
static int open_self_auxv(void *cpu_env, int fd)
{
- TaskState *ts = ((CPUState *)cpu_env)->opaque;
+ TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
abi_ulong auxv = ts->info->saved_auxv;
abi_ulong len = ts->info->auxv_len;
char *ptr;
@@ -4784,13 +4784,13 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
be disabling signals. */
if (first_cpu->next_cpu) {
TaskState *ts;
- CPUState **lastp;
- CPUState *p;
+ CPUArchState **lastp;
+ CPUArchState *p;
cpu_list_lock();
lastp = &first_cpu;
p = first_cpu;
- while (p && p != (CPUState *)cpu_env) {
+ while (p && p != (CPUArchState *)cpu_env) {
lastp = &p->next_cpu;
p = p->next_cpu;
}
@@ -4801,7 +4801,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
/* Remove the CPU from the list. */
*lastp = p->next_cpu;
cpu_list_unlock();
- ts = ((CPUState *)cpu_env)->opaque;
+ ts = ((CPUArchState *)cpu_env)->opaque;
if (ts->child_tidptr) {
put_user_u32(0, ts->child_tidptr);
sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX,
@@ -6091,7 +6091,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
break;
case TARGET_NR_mprotect:
{
- TaskState *ts = ((CPUState *)cpu_env)->opaque;
+ TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
/* Special hack to detect libc making the stack executable. */
if ((arg3 & PROT_GROWSDOWN)
&& arg1 >= ts->info->stack_limit
@@ -7076,7 +7076,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_MIPS) || \
defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_ALPHA) || \
defined(TARGET_M68K) || defined(TARGET_S390X)
- ret = do_sigaltstack(arg1, arg2, get_sp_from_cpustate((CPUState *)cpu_env));
+ ret = do_sigaltstack(arg1, arg2, get_sp_from_cpustate((CPUArchState *)cpu_env));
break;
#else
goto unimplemented;
diff --git a/monitor.c b/monitor.c
index e3b72ff..d57e7bf 100644
--- a/monitor.c
+++ b/monitor.c
@@ -156,7 +156,7 @@ struct Monitor {
int outbuf_index;
ReadLineState *rs;
MonitorControl *mc;
- CPUState *mon_cpu;
+ CPUArchState *mon_cpu;
BlockDriverCompletionFunc *password_completion_cb;
void *password_opaque;
#ifdef CONFIG_DEBUG_MONITOR
@@ -742,7 +742,7 @@ CommandInfoList *qmp_query_commands(Error **errp)
/* set the current CPU defined by the user */
int monitor_set_cpu(int cpu_index)
{
- CPUState *env;
+ CPUArchState *env;
for(env = first_cpu; env != NULL; env = env->next_cpu) {
if (env->cpu_index == cpu_index) {
@@ -753,7 +753,7 @@ int monitor_set_cpu(int cpu_index)
return -1;
}
-static CPUState *mon_get_cpu(void)
+static CPUArchState *mon_get_cpu(void)
{
if (!cur_mon->mon_cpu) {
monitor_set_cpu(0);
@@ -769,7 +769,7 @@ int monitor_get_cpu_index(void)
static void do_info_registers(Monitor *mon)
{
- CPUState *env;
+ CPUArchState *env;
env = mon_get_cpu();
#ifdef TARGET_I386
cpu_dump_state(env, (FILE *)mon, monitor_fprintf,
@@ -806,7 +806,7 @@ static void do_info_history(Monitor *mon)
/* XXX: not implemented in other targets */
static void do_info_cpu_stats(Monitor *mon)
{
- CPUState *env;
+ CPUArchState *env;
env = mon_get_cpu();
cpu_dump_statistics(env, (FILE *)mon, &monitor_fprintf, 0);
@@ -987,7 +987,7 @@ static void monitor_printc(Monitor *mon, int c)
static void memory_dump(Monitor *mon, int count, int format, int wsize,
target_phys_addr_t addr, int is_physical)
{
- CPUState *env;
+ CPUArchState *env;
int l, line_size, i, max_digits, len;
uint8_t buf[16];
uint64_t v;
@@ -1547,7 +1547,7 @@ static void print_pte(Monitor *mon, target_phys_addr_t addr,
pte & PG_RW_MASK ? 'W' : '-');
}
-static void tlb_info_32(Monitor *mon, CPUState *env)
+static void tlb_info_32(Monitor *mon, CPUArchState *env)
{
unsigned int l1, l2;
uint32_t pgd, pde, pte;
@@ -1575,7 +1575,7 @@ static void tlb_info_32(Monitor *mon, CPUState *env)
}
}
-static void tlb_info_pae32(Monitor *mon, CPUState *env)
+static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
{
unsigned int l1, l2, l3;
uint64_t pdpe, pde, pte;
@@ -1615,7 +1615,7 @@ static void tlb_info_pae32(Monitor *mon, CPUState *env)
}
#ifdef TARGET_X86_64
-static void tlb_info_64(Monitor *mon, CPUState *env)
+static void tlb_info_64(Monitor *mon, CPUArchState *env)
{
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
@@ -1674,7 +1674,7 @@ static void tlb_info_64(Monitor *mon, CPUState *env)
static void tlb_info(Monitor *mon)
{
- CPUState *env;
+ CPUArchState *env;
env = mon_get_cpu();
@@ -1719,7 +1719,7 @@ static void mem_print(Monitor *mon, target_phys_addr_t *pstart,
}
}
-static void mem_info_32(Monitor *mon, CPUState *env)
+static void mem_info_32(Monitor *mon, CPUArchState *env)
{
unsigned int l1, l2;
int prot, last_prot;
@@ -1760,7 +1760,7 @@ static void mem_info_32(Monitor *mon, CPUState *env)
mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 32, 0);
}
-static void mem_info_pae32(Monitor *mon, CPUState *env)
+static void mem_info_pae32(Monitor *mon, CPUArchState *env)
{
unsigned int l1, l2, l3;
int prot, last_prot;
@@ -1817,7 +1817,7 @@ static void mem_info_pae32(Monitor *mon, CPUState *env)
#ifdef TARGET_X86_64
-static void mem_info_64(Monitor *mon, CPUState *env)
+static void mem_info_64(Monitor *mon, CPUArchState *env)
{
int prot, last_prot;
uint64_t l1, l2, l3, l4;
@@ -1897,7 +1897,7 @@ static void mem_info_64(Monitor *mon, CPUState *env)
static void mem_info(Monitor *mon)
{
- CPUState *env;
+ CPUArchState *env;
env = mon_get_cpu();
@@ -1936,7 +1936,7 @@ static void print_tlb(Monitor *mon, int idx, tlb_t *tlb)
static void tlb_info(Monitor *mon)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
int i;
monitor_printf (mon, "ITLB:\n");
@@ -1952,7 +1952,7 @@ static void tlb_info(Monitor *mon)
#if defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_XTENSA)
static void tlb_info(Monitor *mon)
{
- CPUState *env1 = mon_get_cpu();
+ CPUArchState *env1 = mon_get_cpu();
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
}
@@ -1966,7 +1966,7 @@ static void do_info_mtree(Monitor *mon)
static void do_info_numa(Monitor *mon)
{
int i;
- CPUState *env;
+ CPUArchState *env;
monitor_printf(mon, "%d nodes\n", nb_numa_nodes);
for (i = 0; i < nb_numa_nodes; i++) {
@@ -2173,7 +2173,7 @@ static void do_acl_remove(Monitor *mon, const QDict *qdict)
#if defined(TARGET_I386)
static void do_inject_mce(Monitor *mon, const QDict *qdict)
{
- CPUState *cenv;
+ CPUArchState *cenv;
int cpu_index = qdict_get_int(qdict, "cpu_index");
int bank = qdict_get_int(qdict, "bank");
uint64_t status = qdict_get_int(qdict, "status");
@@ -2625,7 +2625,7 @@ typedef struct MonitorDef {
#if defined(TARGET_I386)
static target_long monitor_get_pc (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return env->eip + env->segs[R_CS].base;
}
#endif
@@ -2633,7 +2633,7 @@ static target_long monitor_get_pc (const struct MonitorDef *md, int val)
#if defined(TARGET_PPC)
static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
unsigned int u;
int i;
@@ -2646,31 +2646,31 @@ static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
static target_long monitor_get_msr (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return env->msr;
}
static target_long monitor_get_xer (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return env->xer;
}
static target_long monitor_get_decr (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return cpu_ppc_load_decr(env);
}
static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return cpu_ppc_load_tbu(env);
}
static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return cpu_ppc_load_tbl(env);
}
#endif
@@ -2679,7 +2679,7 @@ static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
#ifndef TARGET_SPARC64
static target_long monitor_get_psr (const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return cpu_get_psr(env);
}
@@ -2687,7 +2687,7 @@ static target_long monitor_get_psr (const struct MonitorDef *md, int val)
static target_long monitor_get_reg(const struct MonitorDef *md, int val)
{
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
return env->regwptr[val];
}
#endif
@@ -3019,7 +3019,7 @@ static int get_monitor_def(target_long *pval, const char *name)
if (md->get_value) {
*pval = md->get_value(md, md->offset);
} else {
- CPUState *env = mon_get_cpu();
+ CPUArchState *env = mon_get_cpu();
ptr = (uint8_t *)env + md->offset;
switch(md->type) {
case MD_I32:
diff --git a/poison.h b/poison.h
index 5354e77..d396f20 100644
--- a/poison.h
+++ b/poison.h
@@ -34,7 +34,7 @@
#pragma GCC poison TARGET_PAGE_BITS
#pragma GCC poison TARGET_PAGE_ALIGN
-#pragma GCC poison CPUState
+#pragma GCC poison CPUArchState
#pragma GCC poison env
#pragma GCC poison lduw_phys
diff --git a/softmmu-semi.h b/softmmu-semi.h
index 86a9f8a..648cb95 100644
--- a/softmmu-semi.h
+++ b/softmmu-semi.h
@@ -7,14 +7,14 @@
* This code is licensed under the GPL
*/
-static inline uint32_t softmmu_tget32(CPUState *env, uint32_t addr)
+static inline uint32_t softmmu_tget32(CPUArchState *env, uint32_t addr)
{
uint32_t val;
cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 0);
return tswap32(val);
}
-static inline uint32_t softmmu_tget8(CPUState *env, uint32_t addr)
+static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)
{
uint8_t val;
@@ -26,7 +26,7 @@ static inline uint32_t softmmu_tget8(CPUState *env, uint32_t addr)
#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
#define get_user_ual(arg, p) get_user_u32(arg, p)
-static inline void softmmu_tput32(CPUState *env, uint32_t addr, uint32_t val)
+static inline void softmmu_tput32(CPUArchState *env, uint32_t addr, uint32_t val)
{
val = tswap32(val);
cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 1);
@@ -34,7 +34,7 @@ static inline void softmmu_tput32(CPUState *env, uint32_t addr, uint32_t val)
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
#define put_user_ual(arg, p) put_user_u32(arg, p)
-static void *softmmu_lock_user(CPUState *env, uint32_t addr, uint32_t len,
+static void *softmmu_lock_user(CPUArchState *env, uint32_t addr, uint32_t len,
int copy)
{
uint8_t *p;
@@ -45,7 +45,7 @@ static void *softmmu_lock_user(CPUState *env, uint32_t addr, uint32_t len,
return p;
}
#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
-static char *softmmu_lock_user_string(CPUState *env, uint32_t addr)
+static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)
{
char *p;
char *s;
@@ -60,7 +60,7 @@ static char *softmmu_lock_user_string(CPUState *env, uint32_t addr)
return s;
}
#define lock_user_string(p) softmmu_lock_user_string(env, p)
-static void softmmu_unlock_user(CPUState *env, void *p, target_ulong addr,
+static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
target_ulong len)
{
if (len)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index ecc2a35..48c0fdc 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -25,7 +25,7 @@
#define TARGET_LONG_BITS 64
-#define CPUState struct CPUAlphaState
+#define CPUArchState struct CPUAlphaState
#include "cpu-defs.h"
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2bbb5d1..26c114b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -23,7 +23,7 @@
#define ELF_MACHINE EM_ARM
-#define CPUState struct CPUARMState
+#define CPUArchState struct CPUARMState
#include "config.h"
#include "qemu-common.h"
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index f38393a..31899c2 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -25,7 +25,7 @@
#define TARGET_LONG_BITS 32
-#define CPUState struct CPUCRISState
+#define CPUArchState struct CPUCRISState
#include "cpu-defs.h"
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index f337dd0..aacccb6 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -42,7 +42,7 @@
#define ELF_MACHINE EM_386
#endif
-#define CPUState struct CPUX86State
+#define CPUArchState struct CPUX86State
#include "cpu-defs.h"
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 684b2fa..0902a24 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -22,7 +22,7 @@
#define TARGET_LONG_BITS 32
-#define CPUState struct CPULM32State
+#define CPUArchState struct CPULM32State
#include "config.h"
#include "qemu-common.h"
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 2c83b89..6696e30 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -22,7 +22,7 @@
#define TARGET_LONG_BITS 32
-#define CPUState struct CPUM68KState
+#define CPUArchState struct CPUM68KState
#include "config.h"
#include "qemu-common.h"
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 6ae5649..3b52421 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -24,7 +24,7 @@
#define TARGET_LONG_BITS 32
-#define CPUState struct CPUMBState
+#define CPUArchState struct CPUMBState
#include "cpu-defs.h"
#include "softfloat.h"
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 94381ec..7430aa5 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -7,7 +7,7 @@
#define ELF_MACHINE EM_MIPS
-#define CPUState struct CPUMIPSState
+#define CPUArchState struct CPUMIPSState
#include "config.h"
#include "qemu-common.h"
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3508d8a..ad09cbe 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -71,7 +71,7 @@
#endif /* defined (TARGET_PPC64) */
-#define CPUState struct CPUPPCState
+#define CPUArchState struct CPUPPCState
#include "cpu-defs.h"
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index af6cc4e..ea849fc 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -26,7 +26,7 @@
#define ELF_MACHINE EM_S390
-#define CPUState struct CPUS390XState
+#define CPUArchState struct CPUS390XState
#include "cpu-defs.h"
#define TARGET_PAGE_BITS 12
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index b45e54f..965536d 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -37,7 +37,7 @@
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
-#define CPUState struct CPUSH4State
+#define CPUArchState struct CPUSH4State
#include "cpu-defs.h"
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 2c2cea7..86f9de6 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -23,7 +23,7 @@
# endif
#endif
-#define CPUState struct CPUSPARCState
+#define CPUArchState struct CPUSPARCState
#include "cpu-defs.h"
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 171f0a9..a3f8589 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -18,7 +18,7 @@
#define ELF_MACHINE EM_UNICORE32
-#define CPUState struct CPUUniCore32State
+#define CPUArchState struct CPUUniCore32State
#include "config.h"
#include "qemu-common.h"
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index b7723ca..a7bcf52 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -31,7 +31,7 @@
#define TARGET_LONG_BITS 32
#define ELF_MACHINE EM_XTENSA
-#define CPUState struct CPUXtensaState
+#define CPUArchState struct CPUXtensaState
#include "config.h"
#include "qemu-common.h"
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 5b233f5..5af21b3 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -990,10 +990,10 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
/* In the
- * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
+ * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))]
* below, the offset is likely to exceed 12 bits if mem_index != 0 and
* not exceed otherwise, so use an
- * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
+ * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
* before.
*/
if (mem_index)
@@ -1001,7 +1001,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
(mem_index << (TLB_SHIFT & 1)) |
((16 - (TLB_SHIFT >> 1)) << 8));
tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
- offsetof(CPUState, tlb_table[0][0].addr_read));
+ offsetof(CPUArchState, tlb_table[0][0].addr_read));
tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
/* Check alignment. */
@@ -1012,12 +1012,12 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
/* XXX: possibly we could use a block data load or writeback in
* the first access. */
tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
- offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
+ offsetof(CPUArchState, tlb_table[0][0].addr_read) + 4);
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
# endif
tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
- offsetof(CPUState, tlb_table[0][0].addend));
+ offsetof(CPUArchState, tlb_table[0][0].addend));
switch (opc) {
case 0:
@@ -1210,10 +1210,10 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
/* In the
- * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
+ * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))]
* below, the offset is likely to exceed 12 bits if mem_index != 0 and
* not exceed otherwise, so use an
- * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
+ * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table)
* before.
*/
if (mem_index)
@@ -1221,7 +1221,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
(mem_index << (TLB_SHIFT & 1)) |
((16 - (TLB_SHIFT >> 1)) << 8));
tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
- offsetof(CPUState, tlb_table[0][0].addr_write));
+ offsetof(CPUArchState, tlb_table[0][0].addr_write));
tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
/* Check alignment. */
@@ -1232,12 +1232,12 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
/* XXX: possibly we could use a block data load or writeback in
* the first access. */
tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
- offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
+ offsetof(CPUArchState, tlb_table[0][0].addr_write) + 4);
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
# endif
tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
- offsetof(CPUState, tlb_table[0][0].addend));
+ offsetof(CPUArchState, tlb_table[0][0].addend));
switch (opc) {
case 0:
@@ -1797,7 +1797,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
tcg_add_target_add_op_defs(arm_op_defs);
- tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
+ tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 59d4d12..6a67a41 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -1040,13 +1040,13 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
lab1 = gen_new_label();
lab2 = gen_new_label();
- offset = offsetof(CPUState, tlb_table[mem_index][0].addr_read);
+ offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg, addrhi_reg,
opc & 3, lab1, offset);
/* TLB Hit. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20, (offset ? TCG_REG_R1 : TCG_REG_R25),
- offsetof(CPUState, tlb_table[mem_index][0].addend) - offset);
+ offsetof(CPUArchState, tlb_table[mem_index][0].addend) - offset);
tcg_out_qemu_ld_direct(s, datalo_reg, datahi_reg, addrlo_reg, TCG_REG_R20, opc);
tcg_out_branch(s, lab2, 1);
@@ -1155,13 +1155,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
lab1 = gen_new_label();
lab2 = gen_new_label();
- offset = offsetof(CPUState, tlb_table[mem_index][0].addr_write);
+ offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg, addrhi_reg,
opc, lab1, offset);
/* TLB Hit. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20, (offset ? TCG_REG_R1 : TCG_REG_R25),
- offsetof(CPUState, tlb_table[mem_index][0].addend) - offset);
+ offsetof(CPUArchState, tlb_table[mem_index][0].addend) - offset);
/* There are no indexed stores, so we must do this addition explitly.
Careful to avoid R20, which is used for the bswaps to follow. */
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index dc81572..424a56e 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1031,7 +1031,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0,
- offsetof(CPUState, tlb_table[mem_index][0])
+ offsetof(CPUArchState, tlb_table[mem_index][0])
+ which);
/* cmp 0(r1), r0 */
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index e3de79f..f90252a 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1479,8 +1479,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
/* Read the TLB entry */
tcg_out_qemu_tlb(s, addr_reg, s_bits,
- offsetof(CPUState, tlb_table[mem_index][0].addr_read),
- offsetof(CPUState, tlb_table[mem_index][0].addend));
+ offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
+ offsetof(CPUArchState, tlb_table[mem_index][0].addend));
/* P6 is the fast path, and P7 the slow path */
tcg_out_bundle(s, mLX,
@@ -1570,8 +1570,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
#endif
tcg_out_qemu_tlb(s, addr_reg, opc,
- offsetof(CPUState, tlb_table[mem_index][0].addr_write),
- offsetof(CPUState, tlb_table[mem_index][0].addend));
+ offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
+ offsetof(CPUArchState, tlb_table[mem_index][0].addend));
/* P6 is the fast path, and P7 the slow path */
tcg_out_bundle(s, mLX,
@@ -2368,6 +2368,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
tcg_add_target_add_op_defs(ia64_op_defs);
- tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
+ tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index c5c3282..c6aa5bc 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -827,7 +827,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addr_read) + addr_meml);
+ offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + addr_meml);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, addr_regl);
@@ -837,7 +837,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out_nop(s);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addr_read) + addr_memh);
+ offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + addr_memh);
label1_ptr = s->code_ptr;
tcg_out_opc_br(s, OPC_BEQ, addr_regh, TCG_REG_AT);
@@ -893,7 +893,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addend));
+ offsetof(CPUArchState, tlb_table[mem_index][0].addend));
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_A0, addr_regl);
#else
if (GUEST_BASE == (int16_t)GUEST_BASE) {
@@ -1013,7 +1013,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addr_write) + addr_meml);
+ offsetof(CPUArchState, tlb_table[mem_index][0].addr_write) + addr_meml);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T0, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, addr_regl);
@@ -1023,7 +1023,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_nop(s);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_AT, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addr_write) + addr_memh);
+ offsetof(CPUArchState, tlb_table[mem_index][0].addr_write) + addr_memh);
label1_ptr = s->code_ptr;
tcg_out_opc_br(s, OPC_BEQ, addr_regh, TCG_REG_AT);
@@ -1080,7 +1080,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addend));
+ offsetof(CPUArchState, tlb_table[mem_index][0].addend));
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, addr_regl);
#else
if (GUEST_BASE == (int16_t)GUEST_BASE) {
@@ -1529,6 +1529,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
tcg_add_target_add_op_defs(mips_op_defs);
- tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
+ tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index f5d9bf3..6a34cab 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -564,7 +564,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
tcg_out32 (s, (LWZU
| RT (r1)
| RA (r0)
- | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
+ | offsetof (CPUArchState, tlb_table[mem_index][0].addr_read)
)
);
tcg_out32 (s, (RLWINM
@@ -760,7 +760,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
tcg_out32 (s, (LWZU
| RT (r1)
| RA (r0)
- | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
+ | offsetof (CPUArchState, tlb_table[mem_index][0].addr_write)
)
);
tcg_out32 (s, (RLWINM
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 4419378..7f723b5 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -635,7 +635,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
rbase = 0;
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
- offsetof (CPUState, tlb_table[mem_index][0].addr_read));
+ offsetof (CPUArchState, tlb_table[mem_index][0].addr_read));
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
@@ -782,7 +782,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
rbase = 0;
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
- offsetof (CPUState, tlb_table[mem_index][0].addr_write));
+ offsetof (CPUArchState, tlb_table[mem_index][0].addr_write));
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 9317fe8..47ffcc1 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -1439,9 +1439,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
tgen64_andi_tmp(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
if (is_store) {
- ofs = offsetof(CPUState, tlb_table[mem_index][0].addr_write);
+ ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
} else {
- ofs = offsetof(CPUState, tlb_table[mem_index][0].addr_read);
+ ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
}
assert(ofs < 0x80000);
@@ -1515,7 +1515,7 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
*(label1_ptr + 1) = ((unsigned long)s->code_ptr -
(unsigned long)label1_ptr) >> 1;
- ofs = offsetof(CPUState, tlb_table[mem_index][0].addend);
+ ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
assert(ofs < 0x80000);
tcg_out_mem(s, 0, RXY_AG, arg0, arg1, TCG_AREG0, ofs);
@@ -2293,7 +2293,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_add_target_add_op_defs(s390_op_defs);
- tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
+ tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 5cd5a3b..d723f1b 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -776,7 +776,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
/* add arg1, x, arg1 */
- tcg_out_addi(s, arg1, offsetof(CPUState,
+ tcg_out_addi(s, arg1, offsetof(CPUArchState,
tlb_table[mem_index][0].addr_read));
/* add env, arg1, arg1 */
@@ -988,7 +988,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
/* add arg1, x, arg1 */
- tcg_out_addi(s, arg1, offsetof(CPUState,
+ tcg_out_addi(s, arg1, offsetof(CPUArchState,
tlb_table[mem_index][0].addr_write));
/* add env, arg1, arg1 */
diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
index fc0880c..bd85073 100644
--- a/tcg/tci/tcg-target.c
+++ b/tcg/tci/tcg-target.c
@@ -891,7 +891,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_clear(s->reserved_regs);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_add_target_add_op_defs(tcg_target_op_defs);
- tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
+ tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 81fcc0f..b61e99a 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -154,7 +154,7 @@ typedef enum {
void tci_disas(uint8_t opc);
-unsigned long tcg_qemu_tb_exec(CPUState *env, uint8_t *tb_ptr);
+unsigned long tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
#define tcg_qemu_tb_exec tcg_qemu_tb_exec
static inline void flush_icache_range(tcg_target_ulong start,
diff --git a/tci.c b/tci.c
index a20a714..fb9ebef 100644
--- a/tci.c
+++ b/tci.c
@@ -52,7 +52,7 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
/* TCI can optionally use a global register variable for env. */
#if !defined(AREG0)
-CPUState *env;
+CPUArchState *env;
#endif
/* Targets which don't use GETPC also don't need tci_tb_ptr
@@ -429,7 +429,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
}
/* Interpret pseudo code in tb. */
-unsigned long tcg_qemu_tb_exec(CPUState *cpustate, uint8_t *tb_ptr)
+unsigned long tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
{
unsigned long next_tb = 0;
diff --git a/translate-all.c b/translate-all.c
index 041c108..8c7d303 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -51,7 +51,7 @@ void cpu_gen_init(void)
'*gen_code_size_ptr' contains the size of the generated code (host
code).
*/
-int cpu_gen_code(CPUState *env, TranslationBlock *tb, int *gen_code_size_ptr)
+int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr)
{
TCGContext *s = &tcg_ctx;
uint8_t *gen_code_buf;
@@ -109,7 +109,7 @@ int cpu_gen_code(CPUState *env, TranslationBlock *tb, int *gen_code_size_ptr)
/* The cpu state corresponding to 'searched_pc' is restored.
*/
int cpu_restore_state(TranslationBlock *tb,
- CPUState *env, unsigned long searched_pc)
+ CPUArchState *env, unsigned long searched_pc)
{
TCGContext *s = &tcg_ctx;
int j;
diff --git a/user-exec.c b/user-exec.c
index abf6885..cd905ff 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -38,7 +38,7 @@
//#define DEBUG_SIGNAL
-static void exception_action(CPUState *env1)
+static void exception_action(CPUArchState *env1)
{
#if defined(TARGET_I386)
raise_exception_err_env(env1, env1->exception_index, env1->error_code);
@@ -50,7 +50,7 @@ static void exception_action(CPUState *env1)
/* exit the current TB from a signal handler. The host registers are
restored in a state compatible with the CPU emulator
*/
-void cpu_resume_from_signal(CPUState *env1, void *puc)
+void cpu_resume_from_signal(CPUArchState *env1, void *puc)
{
#ifdef __linux__
struct ucontext *uc = puc;
diff --git a/xen-all.c b/xen-all.c
index 6cef506..493112b 100644
--- a/xen-all.c
+++ b/xen-all.c
@@ -530,14 +530,14 @@ static MemoryListener xen_memory_listener = {
static void xen_reset_vcpu(void *opaque)
{
- CPUState *env = opaque;
+ CPUArchState *env = opaque;
env->halted = 1;
}
void xen_vcpu_init(void)
{
- CPUState *first_cpu;
+ CPUArchState *first_cpu;
if ((first_cpu = qemu_get_cpu(0))) {
qemu_register_reset(xen_reset_vcpu, first_cpu);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
` (42 preceding siblings ...)
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
@ 2012-03-10 2:28 ` Andreas Färber
2012-03-12 9:38 ` Igor Mammedov
43 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 2:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Anthony Liguori
Reintroduce CPUState as QOM object: It's abstract and derived directly
from TYPE_OBJECT for compatibility with the user emulators.
The identifier CPUState avoids conflicts between CPU() and the struct.
Introduce $(qom-twice-y) to build it separately for system and for user
emulators.
Prepare a virtual reset method, (re)introduce cpu_reset() as wrapper.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
Makefile.objs | 3 ++
configure | 1 +
include/qemu/cpu.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++
qom/Makefile | 1 +
qom/cpu.c | 58 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 138 insertions(+), 0 deletions(-)
create mode 100644 include/qemu/cpu.h
create mode 100644 qom/cpu.c
diff --git a/Makefile.objs b/Makefile.objs
index 431b7a1..291baf5 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -14,6 +14,7 @@ universal-obj-y += $(qobject-obj-y)
# QOM
include $(SRC_PATH)/qom/Makefile
qom-obj-y = $(addprefix qom/, $(qom-y))
+qom-obj-twice-y = $(addprefix qom/, $(qom-twice-y))
universal-obj-y += $(qom-obj-y)
@@ -89,6 +90,7 @@ fsdev-obj-$(CONFIG_VIRTFS) += $(addprefix fsdev/, $(fsdev-nested-y))
common-obj-y = $(block-obj-y) blockdev.o
common-obj-y += $(net-obj-y)
+common-obj-y += $(qom-obj-twice-y)
common-obj-$(CONFIG_LINUX) += $(fsdev-obj-$(CONFIG_LINUX))
common-obj-y += readline.o console.o cursor.o
common-obj-y += $(oslib-obj-y)
@@ -194,6 +196,7 @@ user-obj-y += cutils.o cache-utils.o
user-obj-y += module.o
user-obj-y += qemu-user.o
user-obj-y += $(trace-obj-y)
+user-obj-y += $(qom-obj-twice-y)
######################################################################
# libhw
diff --git a/configure b/configure
index 66a65d9..1826af5 100755
--- a/configure
+++ b/configure
@@ -3888,6 +3888,7 @@ fi
d=libuser
mkdir -p $d
mkdir -p $d/trace
+mkdir -p $d/qom
symlink $source_path/Makefile.user $d/Makefile
if test "$docs" = "yes" ; then
diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h
new file mode 100644
index 0000000..4291279
--- /dev/null
+++ b/include/qemu/cpu.h
@@ -0,0 +1,75 @@
+/*
+ * QEMU CPU model
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+#ifndef QEMU_CPU_H
+#define QEMU_CPU_H
+
+#include "qemu/object.h"
+
+/**
+ * SECTION:cpu
+ * @section_id: QEMU-cpu
+ * @title: CPU Class
+ * @short_description: Base class for all CPUs
+ */
+
+#define TYPE_CPU "cpu"
+
+#define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
+#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
+#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
+
+typedef struct CPUState CPUState;
+
+/**
+ * CPUClass:
+ * @reset: Callback to reset the #CPU to its initial state.
+ *
+ * Represents a CPU family or model.
+ */
+typedef struct CPUClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ void (*reset)(CPUState *cpu);
+} CPUClass;
+
+/**
+ * CPUState:
+ *
+ * State of one CPU core or thread.
+ */
+struct CPUState {
+ /*< private >*/
+ Object parent_obj;
+ /*< public >*/
+
+ /* TODO Move common fields from CPUState here. */
+};
+
+
+/**
+ * cpu_reset:
+ * @cpu: The CPU whose state is to be reset.
+ */
+void cpu_reset(CPUState *cpu);
+
+
+#endif
diff --git a/qom/Makefile b/qom/Makefile
index 885a263..34c6de5 100644
--- a/qom/Makefile
+++ b/qom/Makefile
@@ -1 +1,2 @@
qom-y = object.o container.o qom-qobject.o
+qom-twice-y = cpu.o
diff --git a/qom/cpu.c b/qom/cpu.c
new file mode 100644
index 0000000..5b36046
--- /dev/null
+++ b/qom/cpu.c
@@ -0,0 +1,58 @@
+/*
+ * QEMU CPU model
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/cpu.h"
+#include "qemu-common.h"
+
+void cpu_reset(CPUState *cpu)
+{
+ CPUClass *klass = CPU_GET_CLASS(cpu);
+
+ if (klass->reset != NULL) {
+ (*klass->reset)(cpu);
+ }
+}
+
+static void cpu_common_reset(CPUState *cpu)
+{
+}
+
+static void cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *k = CPU_CLASS(klass);
+
+ k->reset = cpu_common_reset;
+}
+
+static TypeInfo cpu_type_info = {
+ .name = TYPE_CPU,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(CPUState),
+ .abstract = true,
+ .class_size = sizeof(CPUClass),
+ .class_init = cpu_class_init,
+};
+
+static void cpu_register_types(void)
+{
+ type_register_static(&cpu_type_info);
+}
+
+type_init(cpu_register_types)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
` (3 preceding siblings ...)
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
` (19 more replies)
2012-03-13 19:52 ` [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Anthony Liguori
` (3 subsequent siblings)
8 siblings, 20 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Paul Brook
Hello,
Since the ARM target lately has been the target with the highest rate of changes,
let's convert it first, as a proof of concept. Especially its reset handler can
be greatly simplified through QOM.
Patch 1 is a RESEND of object_class_get_list() v2. Needed for virtually every target.
Patch 2 moves the CPUID lookup to ARMCPUClass.
Patch 3 integrates legacy CPUARMState into ARMCPU.
Patches 5-17 step by step move CPUID-dependent initializations to CPU-specific code.
Patch 6 is a proof of concept for CPUState -> CPU lookup.
(NEW:)
Patch 18 adds CPU properties to manipulate parts of the CPUID (MIDR).
Patch 19 uses them to drop CPU classes that differ only by variant and revision.
Patch 20 adds a "/cpu" property for -M integratorcp (a single-CPU board for which
we have a test image on qemu.org) to allow inspection of CPU properties over QMP.
Available at:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu-arm.v4
Regards,
Andreas
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Paul Brook <paul@codesourcery.com>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
v3 -> v4:
* Rebased on top of type_init() v2, object_class_get_list() v2, qom-cpu v4.
* Rename cpu-core.h to cpu-qom.h. While the term "ARM core" is quite common,
it is less so for other architectures like s390x so use a neutral term.
* Use container_of() for CPUState -> CPU macros (suggested by Anthony).
* Rework arm_env_get_object() -> arm_env_get_cpu(), avoids some casts
(suggested by Anthony). Also rename ENV_GET_OBJECT() -> ENV_GET_CPU().
* Sort -cpu ? list.
* Use object_class_get_list() and sort ourselves rather than using
object_class_foreach_ordered() with callbacks (suggested by Anthony).
* Drop ARMCPUClass jtag_id since it turned out unneeded in QEMU (Peter+Andrzej).
* Drop experimental "halted" property since that should be in common code.
* Introduce "cpuid-variant" and "cpuid-revision" properties.
* Use CPU properties to drop unneeded pxa270-* classes.
* Move "/cpu" child property to integratorcp machine.
v2 -> v3:
* Rebased against qom-upstream.14 branch (and that against master).
* Rename target-arm/cpu-core.c to cpu.c now that we no longer need VPATH.
* Leave cpu-core.h as is to separate from legacy cpu.h.
* Fix -cpu alias "pxa270": handled in cpu_arm_init().
* Use proper GPL headers.
* Start removing CPUID uses in cpu_reset_model_id() and cpu.h.
* Fully convert cpu_reset_model_id() to ARMCPUInfo or per-model code.
* Experiment with adding properties ("halted").
* For testing, add a "/cpu" child property (HACK).
v1 -> v2:
* Cherry-pick Anthony's object_class_foreach() patch.
* Fix ARMCPUClass type name (arm-cpu-core -> arm-cpu).
* Add documentation.
* Rename ARMCPUDef to ARMCPUInfo.
* Use a C99-style table for initializing the classes through class_data
instead of individual class_init functions (suggested by Anthony).
* Prepare reset callback.
* Make ENV_GET_OBJECT() use an inline function for readability.
* Invoke the CPU's reset method from cpu_reset().
* Do feature initialization via table where sensible.
* Add feature flags to ARMCPU as well (suggested by PMM for future tweaking,
also simplifies load/save a bit) and initialize them from ARMCPUClass.
* Make feature inference work for ARMCPU as well by not passing the ARMCPUClass.
Use function-local macros to avoid the ugliness of deferencing the features pointer.
Andreas Färber (20):
qom: Introduce object_class_get_list()
target-arm: Introduce QOM ARMCPUClass
target-arm: Embed CPUARMState in QOM ARMCPU
target-arm: Prepare model-specific class_init function
target-arm: Overwrite reset handler for ti925t
target-arm: Move CPU feature flags out of CPUState
target-arm: No longer abort on unhandled CPUIDs on reset
target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
target-arm: Store CTR in ARMCPUClass
target-arm: Store SCTLR in ARMCPUClass
target-arm: Drop JTAG_ID documentation
target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
target-arm: Store VFP FPSID register in ARMCPUClass
target-arm: Store VFP MVFR0 and MVFR1 in ARMCPUClass
target-arm: Store CLIDR in ARMCPUClass
target-arm: Store CCSIDRs in ARMCPUClass
target-arm: Kill off cpu_reset_model_id()
target-arm: Add cpuid-{variant,revision} properties to CPU
target-arm: Simplify pxa270 CPU classes
hw/integratorcp: Add child property for CPU
Makefile.target | 1 +
hw/integratorcp.c | 3 +
include/qemu/object.h | 11 +
qom/object.c | 17 ++
target-arm/cpu-qom.h | 98 ++++++++
target-arm/cpu.c | 643 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 27 +--
target-arm/helper.c | 471 ++++++------------------------------
target-arm/machine.c | 6 +-
9 files changed, 851 insertions(+), 426 deletions(-)
create mode 100644 target-arm/cpu-qom.h
create mode 100644 target-arm/cpu.c
--
1.7.7
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list()
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
` (18 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Anthony Liguori
This function allows to obtain a singly-linked list of classes, which
can be sorted by the caller.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
---
include/qemu/object.h | 11 +++++++++++
qom/object.c | 17 +++++++++++++++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index ec2d294..e8fc126 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -560,6 +560,17 @@ ObjectClass *object_class_by_name(const char *typename);
void object_class_foreach(void (*fn)(ObjectClass *klass, void *opaque),
const char *implements_type, bool include_abstract,
void *opaque);
+
+/**
+ * object_class_get_list:
+ * @implements_type: The type to filter for, including its derivatives.
+ * @include_abstract: Whether to include abstract classes.
+ *
+ * Returns: A singly-linked list of the classes in reverse hashtable order.
+ */
+GSList *object_class_get_list(const char *implements_type,
+ bool include_abstract);
+
/**
* object_ref:
* @obj: the object
diff --git a/qom/object.c b/qom/object.c
index aa037d2..eef0b22 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -572,6 +572,23 @@ void object_class_foreach(void (*fn)(ObjectClass *klass, void *opaque),
g_hash_table_foreach(type_table_get(), object_class_foreach_tramp, &data);
}
+static void object_class_get_list_tramp(ObjectClass *klass, void *opaque)
+{
+ GSList **list = opaque;
+
+ *list = g_slist_prepend(*list, klass);
+}
+
+GSList *object_class_get_list(const char *implements_type,
+ bool include_abstract)
+{
+ GSList *list = NULL;
+
+ object_class_foreach(object_class_get_list_tramp,
+ implements_type, include_abstract, &list);
+ return list;
+}
+
void object_ref(Object *obj)
{
obj->ref++;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-13 12:31 ` Igor Mitsyanko
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
` (17 subsequent siblings)
19 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andreas Färber, Anthony Liguori, Paul Brook
Create a CPU subclass, and register classes matching all CPU models
except for "pxa270", which is an alias for "pxa270-a0".
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value "any".
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID in the class.
NB: CPUIDs were first introduced by Paul Brook in r1765 (2006).
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Paul Brook <paul@codesourcery.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
Makefile.target | 1 +
target-arm/cpu-qom.h | 64 +++++++++++++++++
target-arm/cpu.c | 193 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 1 -
target-arm/helper.c | 108 +++++++++++++---------------
5 files changed, 308 insertions(+), 59 deletions(-)
create mode 100644 target-arm/cpu-qom.h
create mode 100644 target-arm/cpu.c
diff --git a/Makefile.target b/Makefile.target
index cb1532a..c2c4bca 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -87,6 +87,7 @@ endif
libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
+libobj-$(TARGET_ARM) += cpu.o
ifeq ($(TARGET_BASE_ARCH), sparc)
libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
libobj-y += cpu_init.o
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
new file mode 100644
index 0000000..b2917ea
--- /dev/null
+++ b/target-arm/cpu-qom.h
@@ -0,0 +1,64 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+#ifndef QEMU_ARM_CPU_QOM_H
+#define QEMU_ARM_CPU_QOM_H
+
+#include "qemu/cpu.h"
+
+#define TYPE_ARM_CPU "arm-cpu"
+
+#define ARM_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
+#define ARM_CPU(obj) \
+ OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
+#define ARM_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
+
+/**
+ * ARMCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An ARM CPU model.
+ */
+typedef struct ARMCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ struct {
+ uint32_t c0_cpuid;
+ } cp15;
+} ARMCPUClass;
+
+/**
+ * ARMCPU:
+ *
+ * An ARM CPU core.
+ */
+typedef struct ARMCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+} ARMCPU;
+
+
+#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
new file mode 100644
index 0000000..dabc094
--- /dev/null
+++ b/target-arm/cpu.c
@@ -0,0 +1,193 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void arm_cpu_reset(CPUState *c)
+{
+ ARMCPUClass *klass = ARM_CPU_GET_CLASS(c);
+
+ klass->parent_reset(c);
+}
+
+/* CPU models */
+
+typedef struct ARMCPUInfo {
+ const char *name;
+ uint32_t id;
+} ARMCPUInfo;
+
+static const ARMCPUInfo arm_cpus[] = {
+ {
+ .name = "arm926",
+ .id = 0x41069265,
+ },
+ {
+ .name = "arm946",
+ .id = 0x41059461,
+ },
+ {
+ .name = "arm1026",
+ .id = 0x4106a262,
+ },
+ /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
+ * older core than plain "arm1136". In particular this does not
+ * have the v6K features.
+ */
+ {
+ .name = "arm1136-r2",
+ .id = 0x4107b362,
+ },
+ {
+ .name = "arm1136",
+ .id = 0x4117b363,
+ },
+ {
+ .name = "arm1176",
+ .id = 0x410fb767,
+ },
+ {
+ .name = "arm11mpcore",
+ .id = 0x410fb022,
+ },
+ {
+ .name = "cortex-m3",
+ .id = 0x410fc231,
+ },
+ {
+ .name = "cortex-a8",
+ .id = 0x410fc080,
+ },
+ {
+ .name = "cortex-a9",
+ .id = 0x410fc090,
+ },
+ {
+ .name = "cortex-a15",
+ .id = 0x412fc0f1,
+ },
+ {
+ .name = "ti925t",
+ .id = 0x54029252,
+ },
+ {
+ .name = "sa1100",
+ .id = 0x4401A11B,
+ },
+ {
+ .name = "sa1110",
+ .id = 0x6901B119,
+ },
+ {
+ .name = "pxa250",
+ .id = 0x69052100,
+ },
+ {
+ .name = "pxa255",
+ .id = 0x69052d00,
+ },
+ {
+ .name = "pxa260",
+ .id = 0x69052903,
+ },
+ {
+ .name = "pxa261",
+ .id = 0x69052d05,
+ },
+ {
+ .name = "pxa262",
+ .id = 0x69052d06,
+ },
+ {
+ .name = "pxa270-a0",
+ .id = 0x69054110,
+ },
+ {
+ .name = "pxa270-a1",
+ .id = 0x69054111,
+ },
+ {
+ .name = "pxa270-b0",
+ .id = 0x69054112,
+ },
+ {
+ .name = "pxa270-b1",
+ .id = 0x69054113,
+ },
+ {
+ .name = "pxa270-c0",
+ .id = 0x69054114,
+ },
+ {
+ .name = "pxa270-c5",
+ .id = 0x69054117,
+ },
+ {
+ .name = "any",
+ .id = 0xffffffff,
+ },
+};
+
+static void arm_cpu_class_init(ObjectClass *klass, void *data)
+{
+ ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ const ARMCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = arm_cpu_reset;
+
+ k->cp15.c0_cpuid = info->id;
+}
+
+static void cpu_register(const ARMCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_ARM_CPU,
+ .instance_size = sizeof(ARMCPU),
+ .class_size = sizeof(ARMCPUClass),
+ .class_init = arm_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static TypeInfo arm_cpu_type_info = {
+ .name = TYPE_ARM_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(ARMCPU),
+ .abstract = true,
+ .class_size = sizeof(ARMCPUClass),
+};
+
+static void arm_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&arm_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
+ cpu_register(&arm_cpus[i]);
+ }
+}
+
+type_init(arm_cpu_register_types)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 26c114b..4cfa09c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -420,7 +420,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_PXA260 0x69052903
#define ARM_CPUID_PXA261 0x69052d05
#define ARM_CPUID_PXA262 0x69052d06
-#define ARM_CPUID_PXA270 0x69054110
#define ARM_CPUID_PXA270_A0 0x69054110
#define ARM_CPUID_PXA270_A1 0x69054111
#define ARM_CPUID_PXA270_B0 0x69054112
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8a08db8..bc29183 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6,6 +6,7 @@
#include "hw/loader.h"
#endif
#include "sysemu.h"
+#include "cpu-qom.h"
static uint32_t cortexa15_cp15_c0_c1[8] = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
@@ -46,8 +47,6 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static uint32_t cpu_arm_find_by_name(const char *name);
-
static inline void set_feature(CPUARMState *env, int feature)
{
env->features |= 1u << feature;
@@ -400,13 +399,21 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
CPUARMState *cpu_arm_init(const char *cpu_model)
{
+ ObjectClass *klass;
+ ARMCPUClass *cpu_class;
CPUARMState *env;
- uint32_t id;
static int inited = 0;
- id = cpu_arm_find_by_name(cpu_model);
- if (id == 0)
+ /* One legacy alias to check */
+ if (strcmp(cpu_model, "pxa270") == 0) {
+ cpu_model = "pxa270-a0";
+ }
+
+ klass = object_class_by_name(cpu_model);
+ if (klass == NULL) {
return NULL;
+ }
+ cpu_class = ARM_CPU_CLASS(klass);
env = g_malloc0(sizeof(CPUARMState));
cpu_exec_init(env);
if (tcg_enabled() && !inited) {
@@ -415,7 +422,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
}
env->cpu_model_str = cpu_model;
- env->cp15.c0_cpuid = id;
+ env->cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
cpu_state_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
@@ -431,66 +438,51 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
return env;
}
-struct arm_cpu_t {
- uint32_t id;
- const char *name;
-};
-
-static const struct arm_cpu_t arm_cpu_names[] = {
- { ARM_CPUID_ARM926, "arm926"},
- { ARM_CPUID_ARM946, "arm946"},
- { ARM_CPUID_ARM1026, "arm1026"},
- { ARM_CPUID_ARM1136, "arm1136"},
- { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
- { ARM_CPUID_ARM1176, "arm1176"},
- { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
- { ARM_CPUID_CORTEXM3, "cortex-m3"},
- { ARM_CPUID_CORTEXA8, "cortex-a8"},
- { ARM_CPUID_CORTEXA9, "cortex-a9"},
- { ARM_CPUID_CORTEXA15, "cortex-a15" },
- { ARM_CPUID_TI925T, "ti925t" },
- { ARM_CPUID_PXA250, "pxa250" },
- { ARM_CPUID_SA1100, "sa1100" },
- { ARM_CPUID_SA1110, "sa1110" },
- { ARM_CPUID_PXA255, "pxa255" },
- { ARM_CPUID_PXA260, "pxa260" },
- { ARM_CPUID_PXA261, "pxa261" },
- { ARM_CPUID_PXA262, "pxa262" },
- { ARM_CPUID_PXA270, "pxa270" },
- { ARM_CPUID_PXA270_A0, "pxa270-a0" },
- { ARM_CPUID_PXA270_A1, "pxa270-a1" },
- { ARM_CPUID_PXA270_B0, "pxa270-b0" },
- { ARM_CPUID_PXA270_B1, "pxa270-b1" },
- { ARM_CPUID_PXA270_C0, "pxa270-c0" },
- { ARM_CPUID_PXA270_C5, "pxa270-c5" },
- { ARM_CPUID_ANY, "any"},
- { 0, NULL}
-};
+typedef struct ARMCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} ARMCPUListState;
-void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+/* Sort alphabetically by type name, except for "any". */
+static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- int i;
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
- (*cpu_fprintf)(f, "Available CPUs:\n");
- for (i = 0; arm_cpu_names[i].name; i++) {
- (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ if (strcmp(name_a, "any") == 0) {
+ return 1;
+ } else if (strcmp(name_b, "any") == 0) {
+ return -1;
+ } else {
+ return strcmp(name_a, name_b);
}
}
-/* return 0 if not found */
-static uint32_t cpu_arm_find_by_name(const char *name)
+static void arm_cpu_list_entry(gpointer data, gpointer user_data)
{
- int i;
- uint32_t id;
+ ObjectClass *klass = data;
+ ARMCPUListState *s = user_data;
- id = 0;
- for (i = 0; arm_cpu_names[i].name; i++) {
- if (strcmp(name, arm_cpu_names[i].name) == 0) {
- id = arm_cpu_names[i].id;
- break;
- }
- }
- return id;
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
+}
+
+void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ ARMCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_ARM_CPU, false);
+ list = g_slist_sort(list, arm_cpu_list_compare);
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ g_slist_foreach(list, arm_cpu_list_entry, &s);
+ g_slist_free(list);
}
void cpu_arm_close(CPUARMState *env)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-13 13:18 ` Paolo Bonzini
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function Andreas Färber
` (16 subsequent siblings)
19 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Paul Brook, Andreas Färber, Anthony Liguori,
Richard Henderson
We g_malloc0()'ed CPUARMState ourself, and exec.c's cpu_copy() runs
through cpu_init() as well, so we are at liberty to supply the CPUState
any way we see fit. Having CPUARMState as field in the QOM CPU allows
both to access env from an ARMCPU object and to access the QOM Object
and its ObjectClass from an env pointer, in ARM code for now.
The goal is to convert all CPUs to QOM and to use CPU objects in central
places, especially once we have property support for Object.
This will then allow to have TCG AREG0 point to target-specific fields
where small immediate offsets are desired (as pointed out by rth) while
allowing for common fields at known offsets from the base class.
Having the CPUID in ARMCPUClass, we can set it from the instance_init
function. Same for cpu_model_str, which is now the QOM class name.
Make cpu_state_reset() call cpu_reset() and move most of its code to
arm_cpu_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>
---
target-arm/cpu-qom.h | 12 +++++++
target-arm/cpu.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/helper.c | 75 ++++------------------------------------------
3 files changed, 100 insertions(+), 69 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index b2917ea..9e33b6a 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -21,6 +21,7 @@
#define QEMU_ARM_CPU_QOM_H
#include "qemu/cpu.h"
+#include "cpu.h"
#define TYPE_ARM_CPU "arm-cpu"
@@ -51,6 +52,7 @@ typedef struct ARMCPUClass {
/**
* ARMCPU:
+ * @env: Legacy CPU state.
*
* An ARM CPU core.
*/
@@ -58,7 +60,17 @@ typedef struct ARMCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
+
+ /* TODO Inline this and split off common state */
+ CPUARMState env;
} ARMCPU;
+static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
+{
+ return ARM_CPU(container_of(env, ARMCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index dabc094..00b7ecc 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -20,12 +20,81 @@
#include "cpu-qom.h"
#include "qemu-common.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/loader.h"
+#endif
static void arm_cpu_reset(CPUState *c)
{
ARMCPUClass *klass = ARM_CPU_GET_CLASS(c);
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+ uint32_t id;
+ uint32_t tmp;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
klass->parent_reset(c);
+
+ id = env->cp15.c0_cpuid;
+ tmp = env->cp15.c15_config_base_address;
+ memset(env, 0, offsetof(CPUARMState, breakpoints));
+ env->cp15.c0_cpuid = id;
+ env->cp15.c15_config_base_address = tmp;
+
+#if defined(CONFIG_USER_ONLY)
+ env->uncached_cpsr = ARM_CPU_MODE_USR;
+ /* For user mode we must enable access to coprocessors */
+ env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ env->cp15.c15_cpar = 3;
+ } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ env->cp15.c15_cpar = 1;
+ }
+#else
+ /* SVC mode with interrupts disabled. */
+ env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
+ /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
+ clear at reset. Initial SP and PC are loaded from ROM. */
+ if (IS_M(env)) {
+ uint32_t pc;
+ uint8_t *rom;
+ env->uncached_cpsr &= ~CPSR_I;
+ rom = rom_ptr(0);
+ if (rom) {
+ /* We should really use ldl_phys here, in case the guest
+ modified flash and reset itself. However images
+ loaded via -kernel have not been copied yet, so load the
+ values directly from there. */
+ env->regs[13] = ldl_p(rom);
+ pc = ldl_p(rom + 4);
+ env->thumb = pc & 1;
+ env->regs[15] = pc & ~1;
+ }
+ }
+ env->vfp.xregs[ARM_VFP_FPEXC] = 0;
+ env->cp15.c2_base_mask = 0xffffc000u;
+ /* v7 performance monitor control register: same implementor
+ * field as main ID register, and we implement no event counters.
+ */
+ env->cp15.c9_pmcr = (id & 0xff000000);
+#endif
+ set_flush_to_zero(1, &env->vfp.standard_fp_status);
+ set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
+ set_default_nan_mode(1, &env->vfp.standard_fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->vfp.fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &env->vfp.standard_fp_status);
+ tlb_flush(env, 1);
+ /* Reset is a state change for some CPUState fields which we
+ * bake assumptions about into translated code, so we need to
+ * tb_flush().
+ */
+ tb_flush(env);
}
/* CPU models */
@@ -146,6 +215,18 @@ static const ARMCPUInfo arm_cpus[] = {
},
};
+static void arm_cpu_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ ARMCPUClass *cpu_class = ARM_CPU_GET_CLASS(obj);
+
+ memset(&cpu->env, 0, sizeof(CPUARMState));
+ cpu_exec_init(&cpu->env);
+
+ cpu->env.cpu_model_str = object_get_typename(obj);
+ cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
+}
+
static void arm_cpu_class_init(ObjectClass *klass, void *data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
@@ -164,6 +245,7 @@ static void cpu_register(const ARMCPUInfo *info)
.name = info->name,
.parent = TYPE_ARM_CPU,
.instance_size = sizeof(ARMCPU),
+ .instance_init = arm_cpu_initfn,
.class_size = sizeof(ARMCPUClass),
.class_init = arm_cpu_class_init,
.class_data = (void *)info,
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bc29183..39f3c40 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2,9 +2,6 @@
#include "gdbstub.h"
#include "helper.h"
#include "host-utils.h"
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/loader.h"
-#endif
#include "sysemu.h"
#include "cpu-qom.h"
@@ -54,7 +51,6 @@ static inline void set_feature(CPUARMState *env, int feature)
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
- env->cp15.c0_cpuid = id;
switch (id) {
case ARM_CPUID_ARM926:
set_feature(env, ARM_FEATURE_V5);
@@ -280,69 +276,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
void cpu_state_reset(CPUARMState *env)
{
uint32_t id;
- uint32_t tmp = 0;
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
+ cpu_reset(ENV_GET_CPU(env));
id = env->cp15.c0_cpuid;
- tmp = env->cp15.c15_config_base_address;
- memset(env, 0, offsetof(CPUARMState, breakpoints));
if (id)
cpu_reset_model_id(env, id);
- env->cp15.c15_config_base_address = tmp;
-#if defined (CONFIG_USER_ONLY)
- env->uncached_cpsr = ARM_CPU_MODE_USR;
- /* For user mode we must enable access to coprocessors */
- env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- env->cp15.c15_cpar = 3;
- } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- env->cp15.c15_cpar = 1;
- }
-#else
- /* SVC mode with interrupts disabled. */
- env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
- /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
- clear at reset. Initial SP and PC are loaded from ROM. */
- if (IS_M(env)) {
- uint32_t pc;
- uint8_t *rom;
- env->uncached_cpsr &= ~CPSR_I;
- rom = rom_ptr(0);
- if (rom) {
- /* We should really use ldl_phys here, in case the guest
- modified flash and reset itself. However images
- loaded via -kernel have not been copied yet, so load the
- values directly from there. */
- env->regs[13] = ldl_p(rom);
- pc = ldl_p(rom + 4);
- env->thumb = pc & 1;
- env->regs[15] = pc & ~1;
- }
- }
- env->vfp.xregs[ARM_VFP_FPEXC] = 0;
- env->cp15.c2_base_mask = 0xffffc000u;
- /* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement no event counters.
- */
- env->cp15.c9_pmcr = (id & 0xff000000);
-#endif
- set_flush_to_zero(1, &env->vfp.standard_fp_status);
- set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
- set_default_nan_mode(1, &env->vfp.standard_fp_status);
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->vfp.fp_status);
- set_float_detect_tininess(float_tininess_before_rounding,
- &env->vfp.standard_fp_status);
- tlb_flush(env, 1);
- /* Reset is a state change for some CPUARMState fields which we
- * bake assumptions about into translated code, so we need to
- * tb_flush().
- */
- tb_flush(env);
}
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
@@ -400,7 +339,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
CPUARMState *cpu_arm_init(const char *cpu_model)
{
ObjectClass *klass;
- ARMCPUClass *cpu_class;
+ ARMCPU *cpu;
CPUARMState *env;
static int inited = 0;
@@ -413,16 +352,14 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
if (klass == NULL) {
return NULL;
}
- cpu_class = ARM_CPU_CLASS(klass);
- env = g_malloc0(sizeof(CPUARMState));
- cpu_exec_init(env);
+ cpu = ARM_CPU(object_new(cpu_model));
+ env = &cpu->env;
+
if (tcg_enabled() && !inited) {
inited = 1;
arm_translate_init();
}
- env->cpu_model_str = cpu_model;
- env->cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
cpu_state_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
@@ -487,7 +424,7 @@ void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
void cpu_arm_close(CPUARMState *env)
{
- g_free(env);
+ object_delete(OBJECT(ENV_GET_CPU(env)));
}
static int bad_mode_switch(CPUARMState *env, int mode)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (2 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t Andreas Färber
` (15 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
This allows to share initialization between CPU models.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-arm/cpu.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 00b7ecc..1e34cba 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -102,6 +102,7 @@ static void arm_cpu_reset(CPUState *c)
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
static const ARMCPUInfo arm_cpus[] = {
@@ -237,6 +238,10 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+
+ if (info->class_init != NULL) {
+ (*info->class_init)(k, info);
+ }
}
static void cpu_register(const ARMCPUInfo *info)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (3 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
` (14 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
The OMAPCP feature allows to switch between TI915T and TI925T via
cp15 c15_ticonfig register. Move reset into ti925t-specific callback.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 18 ++++++++++++++++++
target-arm/helper.c | 1 -
2 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1e34cba..097701f 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -105,6 +105,23 @@ typedef struct ARMCPUInfo {
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
+static void ti925t_reset(CPUState *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+
+ arm_cpu_reset(c);
+
+ env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
+}
+
+static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+
+ cpu_class->reset = ti925t_reset;
+}
+
static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm926",
@@ -157,6 +174,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "ti925t",
.id = 0x54029252,
+ .class_init = ti925t_class_init,
},
{
.name = "sa1100",
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 39f3c40..5ebe308 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -196,7 +196,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_TI925T:
set_feature(env, ARM_FEATURE_V4T);
set_feature(env, ARM_FEATURE_OMAPCP);
- env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (4 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-15 18:56 ` Paul Brook
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
` (13 subsequent siblings)
19 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
The internal CPU feature flags were only ever set in
cpu_reset_model_id(). Therefore move their initialization into
ARMCPUClass. We might want to tweak them in the future though (e.g.,
-cpu cortex-r4,+fpu), so keep a copy in ARMCPU. This in turn means we
need to infer features for both ARMCPUClass and ARMCPU, so move feature
inference to arm_infer_features() and use macros to simplify it.
Since cpu.h defines ARMCPUState, which has been incorporated into
ARMCPU, and tries to use arm_feature() in cpu_get_tb_cpu_state(),
move arm_feature() to cpu-core.h and add a forward declaration.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 12 ++++
target-arm/cpu.c | 159 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu.h | 9 +--
target-arm/helper.c | 95 ------------------------------
target-arm/machine.c | 6 +-
5 files changed, 177 insertions(+), 104 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 9e33b6a..6c97337 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -35,6 +35,7 @@
/**
* ARMCPUClass:
* @parent_reset: The parent class' reset handler.
+ * @features: Internal CPU feature flags.
*
* An ARM CPU model.
*/
@@ -48,10 +49,13 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
} cp15;
+
+ uint32_t features;
} ARMCPUClass;
/**
* ARMCPU:
+ * @features: Internal CPU feature flags.
* @env: Legacy CPU state.
*
* An ARM CPU core.
@@ -61,6 +65,8 @@ typedef struct ARMCPU {
CPUState parent_obj;
/*< public >*/
+ uint32_t features;
+
/* TODO Inline this and split off common state */
CPUARMState env;
} ARMCPU;
@@ -72,5 +78,11 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
+static inline int arm_feature(CPUARMState *env, int feature)
+{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ return (cpu->features & (1u << feature)) != 0;
+}
+
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 097701f..f4c05d8 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -97,14 +97,88 @@ static void arm_cpu_reset(CPUState *c)
tb_flush(env);
}
+/* CPU feature flags */
+
+#define ARM_FEATURE(x) (1u << ARM_FEATURE_ ## x)
+
+#define has_feature(x) ((*features & ARM_FEATURE(x)) != 0)
+#define set_feature(x) (*features |= ARM_FEATURE(x))
+
+/**
+ * arm_infer_features:
+ * @features: Pointer to the feature flags of #ARMCPUClass or #ARMCPU.
+ *
+ * Some features automatically imply others.
+ */
+static void arm_infer_features(uint32_t *features)
+{
+ if (has_feature(V7)) {
+ set_feature(VAPA);
+ set_feature(THUMB2);
+ if (!has_feature(M)) {
+ set_feature(V6K);
+ } else {
+ set_feature(V6);
+ }
+ }
+ if (has_feature(V6K)) {
+ set_feature(V6);
+ }
+ if (has_feature(V6)) {
+ set_feature(V5);
+ if (!has_feature(M)) {
+ set_feature(AUXCR);
+ }
+ }
+ if (has_feature(V5)) {
+ set_feature(V4T);
+ }
+ if (has_feature(M)) {
+ set_feature(THUMB_DIV);
+ }
+ if (has_feature(ARM_DIV)) {
+ set_feature(THUMB_DIV);
+ }
+ if (has_feature(VFP4)) {
+ set_feature(VFP3);
+ }
+ if (has_feature(VFP3)) {
+ set_feature(VFP);
+ }
+}
+
+#undef has_feature
+#undef set_feature
+
+static inline void set_class_feature(ARMCPUClass *klass, int feature)
+{
+ klass->features |= 1u << feature;
+}
+
+static inline void unset_class_feature(ARMCPUClass *klass, int feature)
+{
+ klass->features &= ~(1u << feature);
+}
+
/* CPU models */
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
+static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ ARMCPUClass *r1_class;
+
+ r1_class = ARM_CPU_CLASS(object_class_by_name("arm1136"));
+
+ k->features = r1_class->features;
+ unset_class_feature(k, ARM_FEATURE_V6K);
+}
+
static void ti925t_reset(CPUState *c)
{
ARMCPU *cpu = ARM_CPU(c);
@@ -122,18 +196,43 @@ static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
cpu_class->reset = ti925t_reset;
}
+static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ set_class_feature(k, ARM_FEATURE_STRONGARM);
+}
+
+static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ set_class_feature(k, ARM_FEATURE_V5);
+ set_class_feature(k, ARM_FEATURE_XSCALE);
+}
+
+static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
+{
+ set_class_feature(k, ARM_FEATURE_V5);
+ set_class_feature(k, ARM_FEATURE_XSCALE);
+ set_class_feature(k, ARM_FEATURE_IWMMXT);
+}
+
static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm926",
.id = 0x41069265,
+ .features = ARM_FEATURE(V5) |
+ ARM_FEATURE(VFP),
},
{
.name = "arm946",
.id = 0x41059461,
+ .features = ARM_FEATURE(V5) |
+ ARM_FEATURE(MPU),
},
{
.name = "arm1026",
.id = 0x4106a262,
+ .features = ARM_FEATURE(V5) |
+ ARM_FEATURE(VFP) |
+ ARM_FEATURE(AUXCR),
},
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
* older core than plain "arm1136". In particular this does not
@@ -142,95 +241,150 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1136-r2",
.id = 0x4107b362,
+ .class_init = arm1136_r0_class_init,
},
{
.name = "arm1136",
.id = 0x4117b363,
+ .features = ARM_FEATURE(V6) |
+ ARM_FEATURE(VFP),
},
{
.name = "arm1176",
.id = 0x410fb767,
+ .features = ARM_FEATURE(V6K) |
+ ARM_FEATURE(VFP) |
+ ARM_FEATURE(VAPA),
},
{
.name = "arm11mpcore",
.id = 0x410fb022,
+ .features = ARM_FEATURE(V6K) |
+ ARM_FEATURE(VFP) |
+ ARM_FEATURE(VAPA),
},
{
.name = "cortex-m3",
.id = 0x410fc231,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(M),
},
{
.name = "cortex-a8",
.id = 0x410fc080,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP3) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE),
},
{
.name = "cortex-a9",
.id = 0x410fc090,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP3) |
+ ARM_FEATURE(VFP_FP16) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE) |
+ /* Note that A9 supports the MP extensions even for
+ * A9UP and single-core A9MP (which are both different
+ * and valid configurations; we don't model A9UP).
+ */
+ ARM_FEATURE(V7MP),
},
{
.name = "cortex-a15",
.id = 0x412fc0f1,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP4) |
+ ARM_FEATURE(VFP_FP16) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE) |
+ ARM_FEATURE(ARM_DIV) |
+ ARM_FEATURE(V7MP) |
+ ARM_FEATURE(GENERIC_TIMER),
},
{
.name = "ti925t",
.id = 0x54029252,
+ .features = ARM_FEATURE(V4T) |
+ ARM_FEATURE(OMAPCP),
.class_init = ti925t_class_init,
},
{
.name = "sa1100",
.id = 0x4401A11B,
+ .class_init = sa11xx_class_init,
},
{
.name = "sa1110",
.id = 0x6901B119,
+ .class_init = sa11xx_class_init,
},
{
.name = "pxa250",
.id = 0x69052100,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa255",
.id = 0x69052d00,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa260",
.id = 0x69052903,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa261",
.id = 0x69052d05,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa262",
.id = 0x69052d06,
+ .class_init = pxa25x_class_init,
},
{
.name = "pxa270-a0",
.id = 0x69054110,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-a1",
.id = 0x69054111,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-b0",
.id = 0x69054112,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-b1",
.id = 0x69054113,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-c0",
.id = 0x69054114,
+ .class_init = pxa270_class_init,
},
{
.name = "pxa270-c5",
.id = 0x69054117,
+ .class_init = pxa270_class_init,
},
{
.name = "any",
.id = 0xffffffff,
+ .features = ARM_FEATURE(V7) |
+ ARM_FEATURE(VFP4) |
+ ARM_FEATURE(VFP_FP16) |
+ ARM_FEATURE(NEON) |
+ ARM_FEATURE(THUMB2EE) |
+ ARM_FEATURE(ARM_DIV) |
+ ARM_FEATURE(V7MP),
},
};
@@ -239,6 +393,8 @@ static void arm_cpu_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
ARMCPUClass *cpu_class = ARM_CPU_GET_CLASS(obj);
+ cpu->features = cpu_class->features;
+
memset(&cpu->env, 0, sizeof(CPUARMState));
cpu_exec_init(&cpu->env);
@@ -256,10 +412,13 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+ k->features = info->features;
if (info->class_init != NULL) {
(*info->class_init)(k, info);
}
+
+ arm_infer_features(&k->features);
}
static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4cfa09c..d14fb01 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -170,9 +170,6 @@ typedef struct CPUARMState {
uint32_t teecr;
uint32_t teehbr;
- /* Internal CPU feature flags. */
- uint32_t features;
-
/* VFP coprocessor state. */
struct {
float64 regs[32];
@@ -385,10 +382,7 @@ enum arm_features {
ARM_FEATURE_GENERIC_TIMER,
};
-static inline int arm_feature(CPUARMState *env, int feature)
-{
- return (env->features & (1u << feature)) != 0;
-}
+static inline int arm_feature(CPUARMState *env, int feature);
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@@ -475,6 +469,7 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
#endif
#include "cpu-all.h"
+#include "cpu-qom.h"
/* Bit usage in the TB flags field: */
#define ARM_TBFLAG_THUMB_SHIFT 0
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5ebe308..0dd6065 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -44,46 +44,31 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1u << feature;
-}
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_ARM926:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_MPU);
env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_AUXCR);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
- set_feature(env, ARM_FEATURE_V6K);
/* Fall through */
case ARM_CPUID_ARM1136_R2:
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
*/
- set_feature(env, ARM_FEATURE_V6);
- set_feature(env, ARM_FEATURE_VFP);
/* These ID register values are correct for 1136 but may be wrong
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
@@ -97,9 +82,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -109,9 +91,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -120,10 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
@@ -137,16 +112,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- /* Note that A9 supports the MP extensions even for
- * A9UP and single-core A9MP (which are both different
- * and valid configurations; we don't model A9UP).
- */
- set_feature(env, ARM_FEATURE_V7MP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
@@ -159,14 +124,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
- set_feature(env, ARM_FEATURE_GENERIC_TIMER);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
@@ -180,22 +137,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXM3:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_M);
break;
case ARM_CPUID_ANY: /* For userspace emulation. */
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- set_feature(env, ARM_FEATURE_V4T);
- set_feature(env, ARM_FEATURE_OMAPCP);
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
@@ -206,8 +152,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA260:
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
@@ -218,58 +162,19 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
- set_feature(env, ARM_FEATURE_IWMMXT);
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
- set_feature(env, ARM_FEATURE_STRONGARM);
env->cp15.c1_sys = 0x00000070;
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
}
-
- /* Some features automatically imply others: */
- if (arm_feature(env, ARM_FEATURE_V7)) {
- set_feature(env, ARM_FEATURE_VAPA);
- set_feature(env, ARM_FEATURE_THUMB2);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_V6K);
- } else {
- set_feature(env, ARM_FEATURE_V6);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V6K)) {
- set_feature(env, ARM_FEATURE_V6);
- }
- if (arm_feature(env, ARM_FEATURE_V6)) {
- set_feature(env, ARM_FEATURE_V5);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_AUXCR);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V5)) {
- set_feature(env, ARM_FEATURE_V4T);
- }
- if (arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_VFP4)) {
- set_feature(env, ARM_FEATURE_VFP3);
- }
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- set_feature(env, ARM_FEATURE_VFP);
- }
}
void cpu_state_reset(CPUARMState *env)
diff --git a/target-arm/machine.c b/target-arm/machine.c
index f66b8df..19c0c65 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -5,6 +5,7 @@ void cpu_save(QEMUFile *f, void *opaque)
{
int i;
CPUARMState *env = (CPUARMState *)opaque;
+ ARMCPU *cpu = arm_env_get_cpu(env);
for (i = 0; i < 16; i++) {
qemu_put_be32(f, env->regs[i]);
@@ -61,7 +62,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->cp15.c15_diagnostic);
qemu_put_be32(f, env->cp15.c15_power_diagnostic);
- qemu_put_be32(f, env->features);
+ qemu_put_be32(f, cpu->features);
if (arm_feature(env, ARM_FEATURE_VFP)) {
for (i = 0; i < 16; i++) {
@@ -115,6 +116,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUARMState *env = (CPUARMState *)opaque;
+ ARMCPU *cpu = arm_env_get_cpu(env);
int i;
uint32_t val;
@@ -179,7 +181,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->cp15.c15_diagnostic = qemu_get_be32(f);
env->cp15.c15_power_diagnostic = qemu_get_be32(f);
- env->features = qemu_get_be32(f);
+ cpu->features = qemu_get_be32(f);
if (arm_feature(env, ARM_FEATURE_VFP)) {
for (i = 0; i < 16; i++) {
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (5 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
` (12 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Having moved the reset code for some CPUs to class_init, we can drop
some of the cases in the switch.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 2 --
target-arm/helper.c | 5 -----
2 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d14fb01..48d42b7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -427,8 +427,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_CORTEXA8 0x410fc080
#define ARM_CPUID_CORTEXA9 0x410fc090
#define ARM_CPUID_CORTEXA15 0x412fc0f1
-#define ARM_CPUID_CORTEXM3 0x410fc231
-#define ARM_CPUID_ANY 0xffffffff
#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0dd6065..59a9812 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -136,10 +136,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
env->cp15.c1_sys = 0x00c50078;
break;
- case ARM_CPUID_CORTEXM3:
- break;
- case ARM_CPUID_ANY: /* For userspace emulation. */
- break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
env->cp15.c0_cachetype = 0x5109149;
@@ -172,7 +168,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00000070;
break;
default:
- cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
}
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (6 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-15 19:08 ` Paul Brook
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR " Andreas Färber
` (11 subsequent siblings)
19 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
For now set them in the reset function.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 2 +
target-arm/cpu.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/helper.c | 51 ----------------------------------------
3 files changed, 65 insertions(+), 51 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 6c97337..0148d18 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -48,6 +48,8 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
+ uint32_t c0_c1[8];
+ uint32_t c0_c2[8];
} cp15;
uint32_t features;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f4c05d8..74be400 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -45,6 +45,10 @@ static void arm_cpu_reset(CPUState *c)
env->cp15.c0_cpuid = id;
env->cp15.c15_config_base_address = tmp;
+ /* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
+ memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
+ memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
+
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
@@ -165,6 +169,8 @@ static inline void unset_class_feature(ARMCPUClass *klass, int feature)
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ uint32_t cp15_c0_c1[8];
+ uint32_t cp15_c0_c2[8];
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -177,6 +183,13 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
k->features = r1_class->features;
unset_class_feature(k, ARM_FEATURE_V6K);
+
+ /* These ID register values are correct for 1136 but may be wrong
+ * for 1136_r2 (in particular r0p2 does not actually implement most
+ * of the ID registers).
+ */
+ memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
+ memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
}
static void ti925t_reset(CPUState *c)
@@ -246,12 +259,28 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1136",
.id = 0x4117b363,
+ .cp15_c0_c1 = {
+ 0x111, 0x1, 0x2, 0x3,
+ 0x01130003, 0x10030302, 0x01222110, 0
+ },
+ .cp15_c0_c2 = {
+ 0x00140011, 0x12002111, 0x11231111, 0x01102131,
+ 0x141, 0, 0, 0
+ },
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
{
.name = "arm1176",
.id = 0x410fb767,
+ .cp15_c0_c1 = {
+ 0x111, 0x11, 0x33, 0,
+ 0x01130003, 0x10030302, 0x01222100, 0
+ },
+ .cp15_c0_c2 = {
+ 0x0140011, 0x12002111, 0x11231121, 0x01102131,
+ 0x01141, 0, 0, 0
+ },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -259,6 +288,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm11mpcore",
.id = 0x410fb022,
+ .cp15_c0_c1 = {
+ 0x111, 0x1, 0, 0x2,
+ 0x01100103, 0x10020302, 0x01222000, 0
+ },
+ .cp15_c0_c2 = {
+ 0x00100011, 0x12002111, 0x11221011, 0x01102131,
+ 0x141, 0, 0, 0
+ },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -272,6 +309,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a8",
.id = 0x410fc080,
+ .cp15_c0_c1 = {
+ 0x1031, 0x11, 0x400, 0,
+ 0x31100003, 0x20000000, 0x01202000, 0x11
+ },
+ .cp15_c0_c2 = {
+ 0x00101111, 0x12112111, 0x21232031, 0x11112131,
+ 0x00111142, 0, 0, 0
+ },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -280,6 +325,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a9",
.id = 0x410fc090,
+ .cp15_c0_c1 = {
+ 0x1031, 0x11, 0x000, 0,
+ 0x00100103, 0x20000000, 0x01230000, 0x00002111
+ },
+ .cp15_c0_c2 = {
+ 0x00101111, 0x13112111, 0x21232041, 0x11112131,
+ 0x00111142, 0, 0, 0
+ },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -294,6 +347,14 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a15",
.id = 0x412fc0f1,
+ .cp15_c0_c1 = {
+ 0x00001131, 0x00011011, 0x02010555, 0x00000000,
+ 0x10201105, 0x20000000, 0x01240000, 0x02102211
+ },
+ .cp15_c0_c2 = {
+ 0x02101110, 0x13112111, 0x21232041, 0x11112131,
+ 0x10011142, 0, 0, 0
+ },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -412,6 +473,8 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+ memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
+ memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 59a9812..c0cfa17 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5,45 +5,6 @@
#include "sysemu.h"
#include "cpu-qom.h"
-static uint32_t cortexa15_cp15_c0_c1[8] = {
- 0x00001131, 0x00011011, 0x02010555, 0x00000000,
- 0x10201105, 0x20000000, 0x01240000, 0x02102211
-};
-
-static uint32_t cortexa15_cp15_c0_c2[8] = {
- 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
-};
-
-static uint32_t cortexa9_cp15_c0_c1[8] =
-{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
-
-static uint32_t cortexa9_cp15_c0_c2[8] =
-{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
-
-static uint32_t cortexa8_cp15_c0_c1[8] =
-{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
-
-static uint32_t cortexa8_cp15_c0_c2[8] =
-{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
-
-static uint32_t mpcore_cp15_c0_c1[8] =
-{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
-
-static uint32_t mpcore_cp15_c0_c2[8] =
-{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
-
-static uint32_t arm1136_cp15_c0_c1[8] =
-{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
-
-static uint32_t arm1136_cp15_c0_c2[8] =
-{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
-
-static uint32_t arm1176_cp15_c0_c1[8] =
-{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
-
-static uint32_t arm1176_cp15_c0_c2[8] =
-{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
@@ -76,8 +37,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
@@ -85,8 +44,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
@@ -94,16 +51,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
- memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x82048004;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
@@ -115,8 +68,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
- memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x80038003;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
@@ -127,8 +78,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
- memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
- memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x8444c004;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (7 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR " Andreas Färber
` (10 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 18 ++++++++++++++++++
target-arm/helper.c | 12 ------------
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 0148d18..722d164 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -48,6 +48,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
+ uint32_t c0_cachetype;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
} cp15;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 74be400..c7cf46d 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -46,6 +46,7 @@ static void arm_cpu_reset(CPUState *c)
env->cp15.c15_config_base_address = tmp;
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
+ env->cp15.c0_cachetype = klass->cp15.c0_cachetype;
memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
@@ -169,6 +170,7 @@ static inline void unset_class_feature(ARMCPUClass *klass, int feature)
typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
+ uint32_t cp15_c0_cachetype;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
uint32_t features;
@@ -188,6 +190,7 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
+ k->cp15.c0_cachetype = r1_class->cp15.c0_cachetype;
memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
}
@@ -216,12 +219,16 @@ static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ k->cp15.c0_cachetype = 0xd172172;
+
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
}
static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ k->cp15.c0_cachetype = 0xd172172;
+
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
set_class_feature(k, ARM_FEATURE_IWMMXT);
@@ -231,18 +238,21 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm926",
.id = 0x41069265,
+ .cp15_c0_cachetype = 0x1dd20d2,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP),
},
{
.name = "arm946",
.id = 0x41059461,
+ .cp15_c0_cachetype = 0x0f004006,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(MPU),
},
{
.name = "arm1026",
.id = 0x4106a262,
+ .cp15_c0_cachetype = 0x1dd20d2,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP) |
ARM_FEATURE(AUXCR),
@@ -259,6 +269,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1136",
.id = 0x4117b363,
+ .cp15_c0_cachetype = 0x1dd20d2,
.cp15_c0_c1 = {
0x111, 0x1, 0x2, 0x3,
0x01130003, 0x10030302, 0x01222110, 0
@@ -273,6 +284,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm1176",
.id = 0x410fb767,
+ .cp15_c0_cachetype = 0x1dd20d2,
.cp15_c0_c1 = {
0x111, 0x11, 0x33, 0,
0x01130003, 0x10030302, 0x01222100, 0
@@ -288,6 +300,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "arm11mpcore",
.id = 0x410fb022,
+ .cp15_c0_cachetype = 0x1dd20d2,
.cp15_c0_c1 = {
0x111, 0x1, 0, 0x2,
0x01100103, 0x10020302, 0x01222000, 0
@@ -309,6 +322,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a8",
.id = 0x410fc080,
+ .cp15_c0_cachetype = 0x82048004,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
0x31100003, 0x20000000, 0x01202000, 0x11
@@ -325,6 +339,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a9",
.id = 0x410fc090,
+ .cp15_c0_cachetype = 0x80038003,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
0x00100103, 0x20000000, 0x01230000, 0x00002111
@@ -347,6 +362,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "cortex-a15",
.id = 0x412fc0f1,
+ .cp15_c0_cachetype = 0x8444c004,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
0x10201105, 0x20000000, 0x01240000, 0x02102211
@@ -367,6 +383,7 @@ static const ARMCPUInfo arm_cpus[] = {
{
.name = "ti925t",
.id = 0x54029252,
+ .cp15_c0_cachetype = 0x5109149,
.features = ARM_FEATURE(V4T) |
ARM_FEATURE(OMAPCP),
.class_init = ti925t_class_init,
@@ -473,6 +490,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
cpu_class->reset = arm_cpu_reset;
k->cp15.c0_cpuid = info->id;
+ k->cp15.c0_cachetype = info->cp15_c0_cachetype;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->features = info->features;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c0cfa17..14ed890 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,16 +10,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
switch (id) {
case ARM_CPUID_ARM926:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
@@ -37,27 +34,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
- env->cp15.c0_cachetype = 0x82048004;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
@@ -68,7 +61,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
- env->cp15.c0_cachetype = 0x80038003;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
@@ -78,7 +70,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
- env->cp15.c0_cachetype = 0x8444c004;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
@@ -87,7 +78,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
@@ -98,7 +88,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
@@ -109,7 +98,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (8 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR " Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation Andreas Färber
` (9 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 19 +++++++++++++++++++
target-arm/cpu.h | 3 ---
target-arm/helper.c | 17 -----------------
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 722d164..3832986 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -51,6 +51,7 @@ typedef struct ARMCPUClass {
uint32_t c0_cachetype;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
+ uint32_t c1_sys;
} cp15;
uint32_t features;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index c7cf46d..2f3190a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -50,6 +50,9 @@ static void arm_cpu_reset(CPUState *c)
memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
+ /* Genuine reset */
+ env->cp15.c1_sys = klass->cp15.c1_sys;
+
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
@@ -173,6 +176,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_cachetype;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
+ uint32_t cp15_c1_sys;
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -193,6 +197,7 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
k->cp15.c0_cachetype = r1_class->cp15.c0_cachetype;
memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+ k->cp15.c1_sys = r1_class->cp15.c1_sys;
}
static void ti925t_reset(CPUState *c)
@@ -214,12 +219,15 @@ static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
static void sa11xx_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ k->cp15.c1_sys = 0x00000070;
+
set_class_feature(k, ARM_FEATURE_STRONGARM);
}
static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
k->cp15.c0_cachetype = 0xd172172;
+ k->cp15.c1_sys = 0x00000078;
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -228,6 +236,7 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
k->cp15.c0_cachetype = 0xd172172;
+ k->cp15.c1_sys = 0x00000078;
set_class_feature(k, ARM_FEATURE_V5);
set_class_feature(k, ARM_FEATURE_XSCALE);
@@ -239,6 +248,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "arm926",
.id = 0x41069265,
.cp15_c0_cachetype = 0x1dd20d2,
+ .cp15_c1_sys = 0x00090078,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP),
},
@@ -246,6 +256,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "arm946",
.id = 0x41059461,
.cp15_c0_cachetype = 0x0f004006,
+ .cp15_c1_sys = 0x00000078,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(MPU),
},
@@ -253,6 +264,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "arm1026",
.id = 0x4106a262,
.cp15_c0_cachetype = 0x1dd20d2,
+ .cp15_c1_sys = 0x00090078,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP) |
ARM_FEATURE(AUXCR),
@@ -278,6 +290,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00140011, 0x12002111, 0x11231111, 0x01102131,
0x141, 0, 0, 0
},
+ .cp15_c1_sys = 0x00050078,
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -293,6 +306,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x0140011, 0x12002111, 0x11231121, 0x01102131,
0x01141, 0, 0, 0
},
+ .cp15_c1_sys = 0x00050078,
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -331,6 +345,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00101111, 0x12112111, 0x21232031, 0x11112131,
0x00111142, 0, 0, 0
},
+ .cp15_c1_sys = 0x00c50078,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -348,6 +363,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00101111, 0x13112111, 0x21232041, 0x11112131,
0x00111142, 0, 0, 0
},
+ .cp15_c1_sys = 0x00c50078,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -371,6 +387,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x02101110, 0x13112111, 0x21232041, 0x11112131,
0x10011142, 0, 0, 0
},
+ .cp15_c1_sys = 0x00c50078,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -384,6 +401,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "ti925t",
.id = 0x54029252,
.cp15_c0_cachetype = 0x5109149,
+ .cp15_c1_sys = 0x00000070,
.features = ARM_FEATURE(V4T) |
ARM_FEATURE(OMAPCP),
.class_init = ti925t_class_init,
@@ -493,6 +511,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
+ k->cp15.c1_sys = info->cp15_c1_sys;
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 48d42b7..66e62e2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -404,11 +404,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM1026 0x4106a262
#define ARM_CPUID_ARM926 0x41069265
-#define ARM_CPUID_ARM946 0x41059461
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_SA1100 0x4401A11B
-#define ARM_CPUID_SA1110 0x6901B119
#define ARM_CPUID_PXA250 0x69052100
#define ARM_CPUID_PXA255 0x69052d00
#define ARM_CPUID_PXA260 0x69052903
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 14ed890..548d8cf 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,14 +10,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
switch (id) {
case ARM_CPUID_ARM926:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
- env->cp15.c1_sys = 0x00090078;
- break;
- case ARM_CPUID_ARM946:
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
- env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
@@ -34,13 +29,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
@@ -55,7 +48,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
@@ -64,7 +56,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
@@ -74,11 +65,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
@@ -88,7 +77,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
@@ -98,11 +86,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c1_sys = 0x00000078;
- break;
- case ARM_CPUID_SA1100:
- case ARM_CPUID_SA1110:
- env->cp15.c1_sys = 0x00000070;
break;
default:
break;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (9 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR " Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
` (8 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
None of the machines in QEMU offer a JTAG debug interface, so this info
was unused. Further, the PXA250 ID contradicts the February 2002
Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
---
target-arm/cpu.h | 5 -----
target-arm/helper.c | 8 --------
2 files changed, 0 insertions(+), 13 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 66e62e2..d7e73d8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -406,11 +406,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_PXA250 0x69052100
-#define ARM_CPUID_PXA255 0x69052d00
-#define ARM_CPUID_PXA260 0x69052903
-#define ARM_CPUID_PXA261 0x69052d05
-#define ARM_CPUID_PXA262 0x69052d06
#define ARM_CPUID_PXA270_A0 0x69054110
#define ARM_CPUID_PXA270_A1 0x69054111
#define ARM_CPUID_PXA270_B0 0x69054112
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 548d8cf..46e9dc5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -71,20 +71,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
- case ARM_CPUID_PXA250:
- case ARM_CPUID_PXA255:
- case ARM_CPUID_PXA260:
- case ARM_CPUID_PXA261:
- case ARM_CPUID_PXA262:
- /* JTAG_ID is ((id << 28) | 0x09265013) */
- break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
case ARM_CPUID_PXA270_B0:
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- /* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
break;
default:
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset()
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (10 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
` (7 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
No other emulated CPU uses this at this time.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
---
target-arm/cpu.c | 14 ++++++++++++++
target-arm/cpu.h | 6 ------
target-arm/helper.c | 8 --------
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2f3190a..1614be4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -233,8 +233,22 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
set_class_feature(k, ARM_FEATURE_XSCALE);
}
+static void pxa270_reset(CPUState *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+
+ arm_cpu_reset(c);
+
+ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
+}
+
static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
{
+ CPUClass *cpu_class = CPU_CLASS(k);
+
+ cpu_class->reset = pxa270_reset;
+
k->cp15.c0_cachetype = 0xd172172;
k->cp15.c1_sys = 0x00000078;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d7e73d8..d135221 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -406,12 +406,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_PXA270_A0 0x69054110
-#define ARM_CPUID_PXA270_A1 0x69054111
-#define ARM_CPUID_PXA270_B0 0x69054112
-#define ARM_CPUID_PXA270_B1 0x69054113
-#define ARM_CPUID_PXA270_C0 0x69054114
-#define ARM_CPUID_PXA270_C5 0x69054117
#define ARM_CPUID_ARM1136 0x4117b363
#define ARM_CPUID_ARM1136_R2 0x4107b362
#define ARM_CPUID_ARM1176 0x410fb767
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 46e9dc5..421ce98 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -71,14 +71,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
- case ARM_CPUID_PXA270_A0:
- case ARM_CPUID_PXA270_A1:
- case ARM_CPUID_PXA270_B0:
- case ARM_CPUID_PXA270_B1:
- case ARM_CPUID_PXA270_C0:
- case ARM_CPUID_PXA270_C5:
- env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- break;
default:
break;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (11 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
` (6 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 3 +++
target-arm/cpu.c | 11 +++++++++++
target-arm/cpu.h | 1 -
target-arm/helper.c | 12 ------------
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 3832986..6cb7891 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -53,6 +53,9 @@ typedef struct ARMCPUClass {
uint32_t c0_c2[8];
uint32_t c1_sys;
} cp15;
+ struct {
+ uint32_t fpsid;
+ } vfp;
uint32_t features;
} ARMCPUClass;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1614be4..ad4a90a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -52,6 +52,7 @@ static void arm_cpu_reset(CPUState *c)
/* Genuine reset */
env->cp15.c1_sys = klass->cp15.c1_sys;
+ env->vfp.xregs[ARM_VFP_FPSID] = klass->vfp.fpsid;
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
@@ -177,6 +178,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
+ uint32_t vfp_fpsid;
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -263,6 +265,7 @@ static const ARMCPUInfo arm_cpus[] = {
.id = 0x41069265,
.cp15_c0_cachetype = 0x1dd20d2,
.cp15_c1_sys = 0x00090078,
+ .vfp_fpsid = 0x41011090,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP),
},
@@ -279,6 +282,7 @@ static const ARMCPUInfo arm_cpus[] = {
.id = 0x4106a262,
.cp15_c0_cachetype = 0x1dd20d2,
.cp15_c1_sys = 0x00090078,
+ .vfp_fpsid = 0x410110a0,
.features = ARM_FEATURE(V5) |
ARM_FEATURE(VFP) |
ARM_FEATURE(AUXCR),
@@ -305,6 +309,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x141, 0, 0, 0
},
.cp15_c1_sys = 0x00050078,
+ .vfp_fpsid = 0x410120b4,
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -321,6 +326,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x01141, 0, 0, 0
},
.cp15_c1_sys = 0x00050078,
+ .vfp_fpsid = 0x410120b5,
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -337,6 +343,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00100011, 0x12002111, 0x11221011, 0x01102131,
0x141, 0, 0, 0
},
+ .vfp_fpsid = 0x410120b4,
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -360,6 +367,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00111142, 0, 0, 0
},
.cp15_c1_sys = 0x00c50078,
+ .vfp_fpsid = 0x410330c0,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -378,6 +386,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x00111142, 0, 0, 0
},
.cp15_c1_sys = 0x00c50078,
+ .vfp_fpsid = 0x41033090,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -402,6 +411,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x10011142, 0, 0, 0
},
.cp15_c1_sys = 0x00c50078,
+ .vfp_fpsid = 0x410430f0,
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -526,6 +536,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
+ k->vfp.fpsid = info->vfp_fpsid;
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d135221..e0d711f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -403,7 +403,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID(env) (env->cp15.c0_cpuid)
#define ARM_CPUID_ARM1026 0x4106a262
-#define ARM_CPUID_ARM926 0x41069265
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
#define ARM_CPUID_ARM1136 0x4117b363
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 421ce98..6ea656c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8,12 +8,6 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_ARM926:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
- break;
- case ARM_CPUID_ARM1026:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
- break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
/* Fall through */
@@ -26,22 +20,18 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
@@ -50,7 +40,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
@@ -58,7 +47,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
env->cp15.c0_clid = 0x0a200023;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (12 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR " Andreas Färber
` (5 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 11 +++++++++++
target-arm/helper.c | 29 -----------------------------
3 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 6cb7891..cd711fa 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -55,6 +55,7 @@ typedef struct ARMCPUClass {
} cp15;
struct {
uint32_t fpsid;
+ uint32_t mvfr[2];
} vfp;
uint32_t features;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ad4a90a..850aff1 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -49,6 +49,8 @@ static void arm_cpu_reset(CPUState *c)
env->cp15.c0_cachetype = klass->cp15.c0_cachetype;
memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
+ env->vfp.xregs[ARM_VFP_MVFR0] = klass->vfp.mvfr[0];
+ env->vfp.xregs[ARM_VFP_MVFR1] = klass->vfp.mvfr[1];
/* Genuine reset */
env->cp15.c1_sys = klass->cp15.c1_sys;
@@ -179,6 +181,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
uint32_t vfp_fpsid;
+ uint32_t vfp_mvfr[2];
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -310,6 +313,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00050078,
.vfp_fpsid = 0x410120b4,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -327,6 +331,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00050078,
.vfp_fpsid = 0x410120b5,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -344,6 +349,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x141, 0, 0, 0
},
.vfp_fpsid = 0x410120b4,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -368,6 +374,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x410330c0,
+ .vfp_mvfr = { 0x11110222, 0x00011100 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -387,6 +394,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x41033090,
+ .vfp_mvfr = { 0x11110222, 0x01111111 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -412,6 +420,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x410430f0,
+ .vfp_mvfr = { 0x10110222, 0x11111111 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -537,6 +546,8 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
k->vfp.fpsid = info->vfp_fpsid;
+ k->vfp.mvfr[0] = info->vfp_mvfr[0];
+ k->vfp.mvfr[1] = info->vfp_mvfr[1];
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ea656c..1f5043c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8,47 +8,18 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_ARM1136:
- /* This is the 1136 r1, which is a v6K core */
- /* Fall through */
- case ARM_CPUID_ARM1136_R2:
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- */
- /* These ID register values are correct for 1136 but may be wrong
- * for 1136_r2 (in particular r0p2 does not actually implement most
- * of the ID registers).
- */
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
- case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
- case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (13 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs " Andreas Färber
` (4 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 6 ++++++
target-arm/helper.c | 3 ---
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index cd711fa..101cdb1 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -49,6 +49,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c0_clid;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
uint32_t c1_sys;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 850aff1..1a06c52 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -47,6 +47,7 @@ static void arm_cpu_reset(CPUState *c)
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
env->cp15.c0_cachetype = klass->cp15.c0_cachetype;
+ env->cp15.c0_clid = klass->cp15.c0_clid;
memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
env->vfp.xregs[ARM_VFP_MVFR0] = klass->vfp.mvfr[0];
@@ -177,6 +178,7 @@ typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
uint32_t cp15_c0_cachetype;
+ uint32_t cp15_c0_clid;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
@@ -364,6 +366,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a8",
.id = 0x410fc080,
.cp15_c0_cachetype = 0x82048004,
+ .cp15_c0_clid = (1 << 27) | (2 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
0x31100003, 0x20000000, 0x01202000, 0x11
@@ -384,6 +387,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a9",
.id = 0x410fc090,
.cp15_c0_cachetype = 0x80038003,
+ .cp15_c0_clid = (1 << 27) | (1 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
0x00100103, 0x20000000, 0x01230000, 0x00002111
@@ -410,6 +414,7 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a15",
.id = 0x412fc0f1,
.cp15_c0_cachetype = 0x8444c004,
+ .cp15_c0_clid = 0x0a200023,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
0x10201105, 0x20000000, 0x01240000, 0x02102211
@@ -542,6 +547,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
k->cp15.c0_cpuid = info->id;
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
+ k->cp15.c0_clid = info->cp15_c0_clid;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1f5043c..1e3576c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -9,18 +9,15 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
case ARM_CPUID_CORTEXA8:
- env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (14 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR " Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id() Andreas Färber
` (3 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 17 +++++++++++++++++
target-arm/helper.c | 14 --------------
3 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 101cdb1..cf79ed6 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -49,6 +49,7 @@ typedef struct ARMCPUClass {
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c0_ccsid[16];
uint32_t c0_clid;
uint32_t c0_c1[8];
uint32_t c0_c2[8];
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1a06c52..9f571a1 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -47,6 +47,7 @@ static void arm_cpu_reset(CPUState *c)
/* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
env->cp15.c0_cachetype = klass->cp15.c0_cachetype;
+ memcpy(env->cp15.c0_ccsid, klass->cp15.c0_ccsid, 16 * sizeof(uint32_t));
env->cp15.c0_clid = klass->cp15.c0_clid;
memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t));
@@ -178,6 +179,7 @@ typedef struct ARMCPUInfo {
const char *name;
uint32_t id;
uint32_t cp15_c0_cachetype;
+ uint32_t cp15_c0_ccsid[16];
uint32_t cp15_c0_clid;
uint32_t cp15_c0_c1[8];
uint32_t cp15_c0_c2[8];
@@ -366,6 +368,11 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a8",
.id = 0x410fc080,
.cp15_c0_cachetype = 0x82048004,
+ .cp15_c0_ccsid = {
+ 0xe007e01a, /* 16k L1 dcache. */
+ 0x2007e01a, /* 16k L1 icache. */
+ 0xf0000000, /* No L2 icache. */
+ },
.cp15_c0_clid = (1 << 27) | (2 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x400, 0,
@@ -387,6 +394,10 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a9",
.id = 0x410fc090,
.cp15_c0_cachetype = 0x80038003,
+ .cp15_c0_ccsid = {
+ 0xe00fe015, /* 16k L1 dcache. */
+ 0x200fe015, /* 16k L1 icache. */
+ },
.cp15_c0_clid = (1 << 27) | (1 << 24) | 3,
.cp15_c0_c1 = {
0x1031, 0x11, 0x000, 0,
@@ -414,6 +425,11 @@ static const ARMCPUInfo arm_cpus[] = {
.name = "cortex-a15",
.id = 0x412fc0f1,
.cp15_c0_cachetype = 0x8444c004,
+ .cp15_c0_ccsid = {
+ 0x701fe00a, /* 32K L1 dcache */
+ 0x201fe00a, /* 32K L1 icache */
+ 0x711fe07a, /* 4096K L2 unified cache */
+ },
.cp15_c0_clid = 0x0a200023,
.cp15_c0_c1 = {
0x00001131, 0x00011011, 0x02010555, 0x00000000,
@@ -547,6 +563,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void *data)
k->cp15.c0_cpuid = info->id;
k->cp15.c0_cachetype = info->cp15_c0_cachetype;
+ memcpy(k->cp15.c0_ccsid, info->cp15_c0_ccsid, 16 * sizeof(uint32_t));
k->cp15.c0_clid = info->cp15_c0_clid;
memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1e3576c..ba8a4ae 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8,20 +8,6 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_CORTEXA8:
- env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
- env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- break;
- case ARM_CPUID_CORTEXA9:
- env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
- env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- break;
- case ARM_CPUID_CORTEXA15:
- env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
- env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
- env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
env->cp15.c15_i_max = 0x000;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id()
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (15 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs " Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU Andreas Färber
` (2 subsequent siblings)
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Move last remaining TI925T bits to ti925t_reset().
This reduces cpu_state_reset() to triviality and lets us reset the CPU
directly from arm_cpu_initfn().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 4 ++++
target-arm/helper.c | 20 --------------------
2 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 9f571a1..8917a20 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -217,6 +217,8 @@ static void ti925t_reset(CPUState *c)
arm_cpu_reset(c);
env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
+ env->cp15.c15_i_max = 0x000;
+ env->cp15.c15_i_min = 0xff0;
}
static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info)
@@ -550,6 +552,8 @@ static void arm_cpu_initfn(Object *obj)
cpu->env.cpu_model_str = object_get_typename(obj);
cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
+
+ cpu_reset(CPU(cpu));
}
static void arm_cpu_class_init(ObjectClass *klass, void *data)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ba8a4ae..2d6331d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5,28 +5,9 @@
#include "sysemu.h"
#include "cpu-qom.h"
-static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
-{
- switch (id) {
- case ARM_CPUID_TI915T:
- case ARM_CPUID_TI925T:
- env->cp15.c15_i_max = 0x000;
- env->cp15.c15_i_min = 0xff0;
- break;
- default:
- break;
- }
-}
-
void cpu_state_reset(CPUARMState *env)
{
- uint32_t id;
-
cpu_reset(ENV_GET_CPU(env));
-
- id = env->cp15.c0_cpuid;
- if (id)
- cpu_reset_model_id(env, id);
}
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
@@ -105,7 +86,6 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
arm_translate_init();
}
- cpu_state_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (16 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id() Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU Andreas Färber
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Allow to inspect and manipulate MIDR variant and revision fields.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8917a20..ad33742 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -20,6 +20,7 @@
#include "cpu-qom.h"
#include "qemu-common.h"
+#include "qapi/qapi-visit-core.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
@@ -173,6 +174,46 @@ static inline void unset_class_feature(ARMCPUClass *klass, int feature)
klass->features &= ~(1u << feature);
}
+static void arm_cpuid_variant_get(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ int64_t value = (cpu->env.cp15.c0_cpuid >> 20) & 0xf;
+
+ visit_type_int(v, &value, name, errp);
+}
+
+static void arm_cpuid_variant_set(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ int64_t value;
+
+ visit_type_int(v, &value, name, errp);
+ cpu->env.cp15.c0_cpuid &= ~(0xf << 20);
+ cpu->env.cp15.c0_cpuid |= (value << 20) & 0xf;
+}
+
+static void arm_cpuid_revision_get(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ int64_t value = cpu->env.cp15.c0_cpuid & 0xf;
+
+ visit_type_int(v, &value, name, errp);
+}
+
+static void arm_cpuid_revision_set(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ int64_t value;
+
+ visit_type_int(v, &value, name, errp);
+ cpu->env.cp15.c0_cpuid &= ~0xf;
+ cpu->env.cp15.c0_cpuid |= value & 0xf;
+}
+
/* CPU models */
typedef struct ARMCPUInfo {
@@ -554,6 +595,13 @@ static void arm_cpu_initfn(Object *obj)
cpu->env.cp15.c0_cpuid = cpu_class->cp15.c0_cpuid;
cpu_reset(CPU(cpu));
+
+ object_property_add(obj, "cpuid-variant", "uint4",
+ arm_cpuid_variant_get,
+ arm_cpuid_variant_set, NULL, NULL, NULL);
+ object_property_add(obj, "cpuid-revision", "uint4",
+ arm_cpuid_revision_get,
+ arm_cpuid_revision_set, NULL, NULL, NULL);
}
static void arm_cpu_class_init(ObjectClass *klass, void *data)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (17 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU Andreas Färber
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Instead of having classes per CPUID value, keep just one pxa270 class
and use pxa270-a1 etc. as aliases that override default CPU properties.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Paul Brook <paul@codesourcery.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 27 +--------------------------
target-arm/helper.c | 29 ++++++++++++++++++++++++-----
2 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ad33742..da5bb6e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -539,36 +539,11 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = pxa25x_class_init,
},
{
- .name = "pxa270-a0",
+ .name = "pxa270",
.id = 0x69054110,
.class_init = pxa270_class_init,
},
{
- .name = "pxa270-a1",
- .id = 0x69054111,
- .class_init = pxa270_class_init,
- },
- {
- .name = "pxa270-b0",
- .id = 0x69054112,
- .class_init = pxa270_class_init,
- },
- {
- .name = "pxa270-b1",
- .id = 0x69054113,
- .class_init = pxa270_class_init,
- },
- {
- .name = "pxa270-c0",
- .id = 0x69054114,
- .class_init = pxa270_class_init,
- },
- {
- .name = "pxa270-c5",
- .id = 0x69054117,
- .class_init = pxa270_class_init,
- },
- {
.name = "any",
.id = 0xffffffff,
.features = ARM_FEATURE(V7) |
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2d6331d..f66f500 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -64,22 +64,41 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
CPUARMState *cpu_arm_init(const char *cpu_model)
{
+ const char *cpu_typename = cpu_model;
ObjectClass *klass;
ARMCPU *cpu;
CPUARMState *env;
static int inited = 0;
- /* One legacy alias to check */
- if (strcmp(cpu_model, "pxa270") == 0) {
- cpu_model = "pxa270-a0";
+ /* Map legacy aliases to base class */
+ if (strcmp(cpu_model, "pxa270-a0") == 0 ||
+ strcmp(cpu_model, "pxa270-a1") == 0 ||
+ strcmp(cpu_model, "pxa270-b0") == 0 ||
+ strcmp(cpu_model, "pxa270-b1") == 0 ||
+ strcmp(cpu_model, "pxa270-c0") == 0 ||
+ strcmp(cpu_model, "pxa270-c5") == 0) {
+ cpu_typename = "pxa270";
}
- klass = object_class_by_name(cpu_model);
+ klass = object_class_by_name(cpu_typename);
if (klass == NULL) {
return NULL;
}
- cpu = ARM_CPU(object_new(cpu_model));
+ cpu = ARM_CPU(object_new(cpu_typename));
env = &cpu->env;
+ env->cpu_model_str = cpu_model;
+ /* Set properties on base object */
+ if (strcmp(cpu_model, "pxa270-a1") == 0) {
+ object_property_set_int(OBJECT(cpu), 0x1, "cpuid-revision", NULL);
+ } else if (strcmp(cpu_model, "pxa270-b0") == 0) {
+ object_property_set_int(OBJECT(cpu), 0x2, "cpuid-revision", NULL);
+ } else if (strcmp(cpu_model, "pxa270-b1") == 0) {
+ object_property_set_int(OBJECT(cpu), 0x3, "cpuid-revision", NULL);
+ } else if (strcmp(cpu_model, "pxa270-c0") == 0) {
+ object_property_set_int(OBJECT(cpu), 0x4, "cpuid-revision", NULL);
+ } else if (strcmp(cpu_model, "pxa270-c5") == 0) {
+ object_property_set_int(OBJECT(cpu), 0x7, "cpuid-revision", NULL);
+ }
if (tcg_enabled() && !inited) {
inited = 1;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
` (18 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes Andreas Färber
@ 2012-03-10 16:53 ` Andreas Färber
19 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-10 16:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Andreas Färber, Paul Brook
Only one CPU is created on this board, so we can use "/cpu".
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/integratorcp.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 9bdb9e6..ac3fd7e 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -443,6 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
+ ARMCPU *cpu;
CPUARMState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
@@ -459,6 +460,8 @@ static void integratorcp_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ cpu = arm_env_get_cpu(env);
+ object_property_add_child(object_get_root(), "cpu", OBJECT(cpu), NULL);
memory_region_init_ram(ram, "integrator.ram", ram_size);
vmstate_register_ram_global(ram);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
@ 2012-03-12 9:38 ` Igor Mammedov
2012-03-13 12:13 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Igor Mammedov @ 2012-03-12 9:38 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori
On 03/10/2012 03:28 AM, Andreas Färber wrote:
> Reintroduce CPUState as QOM object: It's abstract and derived directly
> from TYPE_OBJECT for compatibility with the user emulators.
> The identifier CPUState avoids conflicts between CPU() and the struct.
>
> Introduce $(qom-twice-y) to build it separately for system and for user
> emulators.
>
> Prepare a virtual reset method, (re)introduce cpu_reset() as wrapper.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> Cc: Anthony Liguori<anthony@codemonkey.ws>
> ---
> Makefile.objs | 3 ++
> configure | 1 +
> include/qemu/cpu.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> qom/Makefile | 1 +
> qom/cpu.c | 58 ++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 138 insertions(+), 0 deletions(-)
> create mode 100644 include/qemu/cpu.h
> create mode 100644 qom/cpu.c
>
> diff --git a/Makefile.objs b/Makefile.objs
> index 431b7a1..291baf5 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -14,6 +14,7 @@ universal-obj-y += $(qobject-obj-y)
> # QOM
> include $(SRC_PATH)/qom/Makefile
> qom-obj-y = $(addprefix qom/, $(qom-y))
> +qom-obj-twice-y = $(addprefix qom/, $(qom-twice-y))
>
> universal-obj-y += $(qom-obj-y)
>
> @@ -89,6 +90,7 @@ fsdev-obj-$(CONFIG_VIRTFS) += $(addprefix fsdev/, $(fsdev-nested-y))
>
> common-obj-y = $(block-obj-y) blockdev.o
> common-obj-y += $(net-obj-y)
> +common-obj-y += $(qom-obj-twice-y)
> common-obj-$(CONFIG_LINUX) += $(fsdev-obj-$(CONFIG_LINUX))
> common-obj-y += readline.o console.o cursor.o
> common-obj-y += $(oslib-obj-y)
> @@ -194,6 +196,7 @@ user-obj-y += cutils.o cache-utils.o
> user-obj-y += module.o
> user-obj-y += qemu-user.o
> user-obj-y += $(trace-obj-y)
> +user-obj-y += $(qom-obj-twice-y)
>
> ######################################################################
> # libhw
> diff --git a/configure b/configure
> index 66a65d9..1826af5 100755
> --- a/configure
> +++ b/configure
> @@ -3888,6 +3888,7 @@ fi
> d=libuser
> mkdir -p $d
> mkdir -p $d/trace
> +mkdir -p $d/qom
> symlink $source_path/Makefile.user $d/Makefile
>
> if test "$docs" = "yes" ; then
> diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h
> new file mode 100644
> index 0000000..4291279
> --- /dev/null
> +++ b/include/qemu/cpu.h
> @@ -0,0 +1,75 @@
> +/*
> + * QEMU CPU model
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +#ifndef QEMU_CPU_H
> +#define QEMU_CPU_H
> +
> +#include "qemu/object.h"
> +
> +/**
> + * SECTION:cpu
> + * @section_id: QEMU-cpu
> + * @title: CPU Class
> + * @short_description: Base class for all CPUs
> + */
> +
> +#define TYPE_CPU "cpu"
> +
> +#define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
> +#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
> +#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
> +
> +typedef struct CPUState CPUState;
> +
> +/**
> + * CPUClass:
> + * @reset: Callback to reset the #CPU to its initial state.
> + *
> + * Represents a CPU family or model.
> + */
> +typedef struct CPUClass {
> + /*< private>*/
> + ObjectClass parent_class;
> + /*< public>*/
> +
> + void (*reset)(CPUState *cpu);
Why not use Object* as argument here?
It will be easier to generalize later qdev code and not make special case when
adding cpus.
BTW how we are going to generalize qdev and make its infrastructure available
to other types except of DEVICE_TYPE.
Maybe we should introduce some (abstract) base class (or interface) for basic
device that will define methods like reset, realize, unrealize and use it in
qdev code instead of DEVICE_TYPE?
> +} CPUClass;
> +
> +/**
> + * CPUState:
> + *
> + * State of one CPU core or thread.
> + */
> +struct CPUState {
> + /*< private>*/
> + Object parent_obj;
> + /*< public>*/
> +
> + /* TODO Move common fields from CPUState here. */
> +};
> +
> +
> +/**
> + * cpu_reset:
> + * @cpu: The CPU whose state is to be reset.
> + */
> +void cpu_reset(CPUState *cpu);
> +
> +
> +#endif
> diff --git a/qom/Makefile b/qom/Makefile
> index 885a263..34c6de5 100644
> --- a/qom/Makefile
> +++ b/qom/Makefile
> @@ -1 +1,2 @@
> qom-y = object.o container.o qom-qobject.o
> +qom-twice-y = cpu.o
> diff --git a/qom/cpu.c b/qom/cpu.c
> new file mode 100644
> index 0000000..5b36046
> --- /dev/null
> +++ b/qom/cpu.c
> @@ -0,0 +1,58 @@
> +/*
> + * QEMU CPU model
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +
> +#include "qemu/cpu.h"
> +#include "qemu-common.h"
> +
> +void cpu_reset(CPUState *cpu)
> +{
> + CPUClass *klass = CPU_GET_CLASS(cpu);
> +
> + if (klass->reset != NULL) {
> + (*klass->reset)(cpu);
> + }
> +}
> +
> +static void cpu_common_reset(CPUState *cpu)
> +{
> +}
> +
> +static void cpu_class_init(ObjectClass *klass, void *data)
> +{
> + CPUClass *k = CPU_CLASS(klass);
> +
> + k->reset = cpu_common_reset;
> +}
> +
> +static TypeInfo cpu_type_info = {
> + .name = TYPE_CPU,
> + .parent = TYPE_OBJECT,
> + .instance_size = sizeof(CPUState),
> + .abstract = true,
> + .class_size = sizeof(CPUClass),
> + .class_init = cpu_class_init,
> +};
> +
> +static void cpu_register_types(void)
> +{
> + type_register_static(&cpu_type_info);
> +}
> +
> +type_init(cpu_register_types)
--
-----
Igor
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type
2012-03-10 1:35 ` Andreas Färber
@ 2012-03-12 10:36 ` Avi Kivity
0 siblings, 0 replies; 175+ messages in thread
From: Avi Kivity @ 2012-03-12 10:36 UTC (permalink / raw)
To: Andreas Färber; +Cc: Marcelo Tosatti, qemu-devel, anthony, lcapitulino
On 03/10/2012 03:35 AM, Andreas Färber wrote:
> Am 05.03.2012 10:23, schrieb Avi Kivity:
> > On 03/04/2012 10:32 PM, Andreas Färber wrote:
> >> Currently, the "kvmclock" type is only registered when kvm_enabled().
> >>
> >> This breaks when moving type registration to before command line
> >> parsing (so that QOM types can be used for CPU and machine).
> >>
> >> Since the QOM classes are lazy-initialized anyway and kvmclock_create()
> >> has another kvm_enabled() check, simply drop the KVM check in
> >> kvmclock_register_types().
> >>
> >> kvm-i8259, kvm-apic and kvm-ioapic do not suffer from such a check.
> >
> > Patch looks good.
>
> Ping for series.
>
> Avi, do you want to sign this patch off through uq/master? Or should I
> make the above a Reviewed-by (and remove the Cc:) within this series?
>
Reviewed-by: please.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-12 9:38 ` Igor Mammedov
@ 2012-03-13 12:13 ` Andreas Färber
2012-03-13 12:20 ` Paolo Bonzini
2012-03-14 20:37 ` Igor Mitsyanko
0 siblings, 2 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-13 12:13 UTC (permalink / raw)
To: Igor Mammedov; +Cc: Paolo Bonzini, qemu-devel, Anthony Liguori
Am 12.03.2012 10:38, schrieb Igor Mammedov:
> On 03/10/2012 03:28 AM, Andreas Färber wrote:
>> Reintroduce CPUState as QOM object: It's abstract and derived directly
>> from TYPE_OBJECT for compatibility with the user emulators.
>> The identifier CPUState avoids conflicts between CPU() and the struct.
>>
>> Introduce $(qom-twice-y) to build it separately for system and for user
>> emulators.
>>
>> Prepare a virtual reset method, (re)introduce cpu_reset() as wrapper.
>>
>> Signed-off-by: Andreas Färber<afaerber@suse.de>
>> Cc: Anthony Liguori<anthony@codemonkey.ws>
>> ---
>> Makefile.objs | 3 ++
>> configure | 1 +
>> include/qemu/cpu.h | 75
>> ++++++++++++++++++++++++++++++++++++++++++++++++++++
>> qom/Makefile | 1 +
>> qom/cpu.c | 58 ++++++++++++++++++++++++++++++++++++++++
>> 5 files changed, 138 insertions(+), 0 deletions(-)
>> create mode 100644 include/qemu/cpu.h
>> create mode 100644 qom/cpu.c
>> diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h
>> new file mode 100644
>> index 0000000..4291279
>> --- /dev/null
>> +++ b/include/qemu/cpu.h
>> +/**
>> + * CPUClass:
>> + * @reset: Callback to reset the #CPU to its initial state.
>> + *
>> + * Represents a CPU family or model.
>> + */
>> +typedef struct CPUClass {
>> + /*< private>*/
>> + ObjectClass parent_class;
>> + /*< public>*/
>> +
>> + void (*reset)(CPUState *cpu);
> Why not use Object* as argument here?
In SysBusDeviceClass etc. we use the specific object type, too.
Obviously my CPU is the first "new" QOM type, so we can go different
ways if we want to. As long as it's a CPU-specific mechanism, using the
specific type avoids some casts.
> It will be easier to generalize later qdev code and not make special
> case when
> adding cpus.
I never heard anyone wanting to generalize reset so far. I don't think
it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
> BTW how we are going to generalize qdev and make its infrastructure
> available
> to other types except of DEVICE_TYPE.
> Maybe we should introduce some (abstract) base class (or interface) for
> basic
> device that will define methods like reset, realize, unrealize and use
> it in
> qdev code instead of DEVICE_TYPE?
I thought Anthony wanted to do realize/unrealize and "realized" property
in Object.
For SH4 I worked around that with my own sh7750_realize() function. This
series is taking much too long to move forward (the QOM "steam" seems to
be gone?) and I'm worried that introducing much more basic
infrastructure will make review and applying even slower, cf.
object_class_foreach_ordered()/_get_list().
Thanks for reviewing so far,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-13 12:13 ` Andreas Färber
@ 2012-03-13 12:20 ` Paolo Bonzini
2012-03-13 12:53 ` Andreas Färber
2012-03-13 18:16 ` Anthony Liguori
2012-03-14 20:37 ` Igor Mitsyanko
1 sibling, 2 replies; 175+ messages in thread
From: Paolo Bonzini @ 2012-03-13 12:20 UTC (permalink / raw)
To: Andreas Färber; +Cc: Igor Mammedov, qemu-devel, Anthony Liguori
Il 13/03/2012 13:13, Andreas Färber ha scritto:
> > It will be easier to generalize later qdev code and not make special
> > case when adding cpus.
>
> I never heard anyone wanting to generalize reset so far. I don't think
> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
I believe long term we want CPUs to become a DeviceState. For now, I
think Andreas's prototype is fine. Methods should not take a superclass
argument in general.
> This series is taking much too long to move forward (the QOM "steam"
> seems to be gone?) and I'm worried that introducing much more basic
> infrastructure will make review and applying even slower, cf.
> object_class_foreach_ordered()/_get_list().
Agreed, this series looks more or less good (and mostly mechanical
anyway). Is it an RFC or what? :) I wonder if reviewers are put off by
the subject.
Paolo
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
@ 2012-03-13 12:31 ` Igor Mitsyanko
2012-03-13 17:58 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Igor Mitsyanko @ 2012-03-13 12:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Dmitry Solodkiy, Anthony Liguori, Paul Brook
On 03/10/2012 08:53 PM, Andreas Färber wrote:
> Create a CPU subclass, and register classes matching all CPU models
> except for "pxa270", which is an alias for "pxa270-a0".
>
> Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
> except for special value "any".
>
> Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
> CPUID in the class.
> NB: CPUIDs were first introduced by Paul Brook in r1765 (2006).
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> Cc: Anthony Liguori<anthony@codemonkey.ws>
> Cc: Paul Brook<paul@codesourcery.com>
> Cc: Peter Maydell<peter.maydell@linaro.org>
> ---
> Makefile.target | 1 +
> target-arm/cpu-qom.h | 64 +++++++++++++++++
> target-arm/cpu.c | 193 ++++++++++++++++++++++++++++++++++++++++++++++++++
> target-arm/cpu.h | 1 -
> target-arm/helper.c | 108 +++++++++++++---------------
> 5 files changed, 308 insertions(+), 59 deletions(-)
> create mode 100644 target-arm/cpu-qom.h
> create mode 100644 target-arm/cpu.c
>
> diff --git a/Makefile.target b/Makefile.target
> index cb1532a..c2c4bca 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -87,6 +87,7 @@ endif
> libobj-$(TARGET_SPARC64) += vis_helper.o
> libobj-$(CONFIG_NEED_MMU) += mmu.o
> libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
> +libobj-$(TARGET_ARM) += cpu.o
> ifeq ($(TARGET_BASE_ARCH), sparc)
> libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
> libobj-y += cpu_init.o
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> new file mode 100644
> index 0000000..b2917ea
> --- /dev/null
> +++ b/target-arm/cpu-qom.h
> @@ -0,0 +1,64 @@
> +/*
> + * QEMU ARM CPU
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +#ifndef QEMU_ARM_CPU_QOM_H
> +#define QEMU_ARM_CPU_QOM_H
> +
> +#include "qemu/cpu.h"
> +
> +#define TYPE_ARM_CPU "arm-cpu"
> +
> +#define ARM_CPU_CLASS(klass) \
> + OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
> +#define ARM_CPU(obj) \
> + OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
> +#define ARM_CPU_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
> +
> +/**
> + * ARMCPUClass:
> + * @parent_reset: The parent class' reset handler.
> + *
> + * An ARM CPU model.
> + */
> +typedef struct ARMCPUClass {
> + /*< private>*/
> + CPUClass parent_class;
> + /*< public>*/
> +
> + void (*parent_reset)(CPUState *cpu);
> +
> + struct {
> + uint32_t c0_cpuid;
> + } cp15;
> +} ARMCPUClass;
> +
> +/**
> + * ARMCPU:
> + *
> + * An ARM CPU core.
> + */
> +typedef struct ARMCPU {
> + /*< private>*/
> + CPUState parent_obj;
> + /*< public>*/
> +} ARMCPU;
> +
> +
> +#endif
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> new file mode 100644
> index 0000000..dabc094
> --- /dev/null
> +++ b/target-arm/cpu.c
> @@ -0,0 +1,193 @@
> +/*
> + * QEMU ARM CPU
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + *<http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +
> +#include "cpu-qom.h"
> +#include "qemu-common.h"
> +
> +static void arm_cpu_reset(CPUState *c)
> +{
> + ARMCPUClass *klass = ARM_CPU_GET_CLASS(c);
> +
> + klass->parent_reset(c);
> +}
> +
> +/* CPU models */
> +
> +typedef struct ARMCPUInfo {
> + const char *name;
> + uint32_t id;
> +} ARMCPUInfo;
> +
> +static const ARMCPUInfo arm_cpus[] = {
> + {
> + .name = "arm926",
> + .id = 0x41069265,
> + },
> + {
> + .name = "arm946",
> + .id = 0x41059461,
> + },
> + {
> + .name = "arm1026",
> + .id = 0x4106a262,
> + },
> + /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
> + * older core than plain "arm1136". In particular this does not
> + * have the v6K features.
> + */
> + {
> + .name = "arm1136-r2",
> + .id = 0x4107b362,
> + },
> + {
> + .name = "arm1136",
> + .id = 0x4117b363,
> + },
> + {
> + .name = "arm1176",
> + .id = 0x410fb767,
> + },
> + {
> + .name = "arm11mpcore",
> + .id = 0x410fb022,
> + },
> + {
> + .name = "cortex-m3",
> + .id = 0x410fc231,
> + },
> + {
> + .name = "cortex-a8",
> + .id = 0x410fc080,
> + },
> + {
> + .name = "cortex-a9",
> + .id = 0x410fc090,
> + },
> + {
> + .name = "cortex-a15",
> + .id = 0x412fc0f1,
> + },
> + {
> + .name = "ti925t",
> + .id = 0x54029252,
> + },
> + {
> + .name = "sa1100",
> + .id = 0x4401A11B,
> + },
> + {
> + .name = "sa1110",
> + .id = 0x6901B119,
> + },
> + {
> + .name = "pxa250",
> + .id = 0x69052100,
> + },
> + {
> + .name = "pxa255",
> + .id = 0x69052d00,
> + },
> + {
> + .name = "pxa260",
> + .id = 0x69052903,
> + },
> + {
> + .name = "pxa261",
> + .id = 0x69052d05,
> + },
> + {
> + .name = "pxa262",
> + .id = 0x69052d06,
> + },
> + {
> + .name = "pxa270-a0",
> + .id = 0x69054110,
> + },
> + {
> + .name = "pxa270-a1",
> + .id = 0x69054111,
> + },
> + {
> + .name = "pxa270-b0",
> + .id = 0x69054112,
> + },
> + {
> + .name = "pxa270-b1",
> + .id = 0x69054113,
> + },
> + {
> + .name = "pxa270-c0",
> + .id = 0x69054114,
> + },
> + {
> + .name = "pxa270-c5",
> + .id = 0x69054117,
> + },
> + {
> + .name = "any",
> + .id = 0xffffffff,
> + },
> +};
> +
> +static void arm_cpu_class_init(ObjectClass *klass, void *data)
> +{
> + ARMCPUClass *k = ARM_CPU_CLASS(klass);
> + CPUClass *cpu_class = CPU_CLASS(klass);
> + const ARMCPUInfo *info = data;
> +
> + k->parent_reset = cpu_class->reset;
> + cpu_class->reset = arm_cpu_reset;
> +
> + k->cp15.c0_cpuid = info->id;
> +}
> +
> +static void cpu_register(const ARMCPUInfo *info)
> +{
> + TypeInfo type = {
> + .name = info->name,
> + .parent = TYPE_ARM_CPU,
> + .instance_size = sizeof(ARMCPU),
> + .class_size = sizeof(ARMCPUClass),
> + .class_init = arm_cpu_class_init,
> + .class_data = (void *)info,
> + };
Are non-initialized members guaranteed to be zero here?
> + type_register_static(&type);
> +}
> +
Probably should be type_register() here in case these two will actually
differ in the future.
If this information is of any help, we've got no problems when emulating
ARM-based Exynos boards in QEMU with this whole patchset applied.
--
Mitsyanko Igor
ASWG, Moscow R&D center, Samsung Electronics
email: i.mitsyanko@samsung.com
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-13 12:20 ` Paolo Bonzini
@ 2012-03-13 12:53 ` Andreas Färber
2012-03-13 13:03 ` Paolo Bonzini
2012-03-13 18:16 ` Anthony Liguori
1 sibling, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-13 12:53 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Igor Mammedov, qemu-devel, Anthony Liguori
Am 13.03.2012 13:20, schrieb Paolo Bonzini:
> Il 13/03/2012 13:13, Andreas Färber ha scritto:
>>> It will be easier to generalize later qdev code and not make special
>>> case when adding cpus.
>>
>> I never heard anyone wanting to generalize reset so far. I don't think
>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>
> I believe long term we want CPUs to become a DeviceState. For now, I
> think Andreas's prototype is fine.
I have prepared $(qom-obj-twice-y) to allow for:
#ifdef CONFIG_SOFTMMU
.parent = TYPE_DEVICE, // or TYPE_SYS_BUS_DEVICE
#else
.parent = TYPE_OBJECT,
#endif
So far it was not needed. :)
> Methods should not take a superclass
> argument in general.
So to clarify, this is pro CPUState?
>> This series is taking much too long to move forward (the QOM "steam"
>> seems to be gone?) and I'm worried that introducing much more basic
>> infrastructure will make review and applying even slower, cf.
>> object_class_foreach_ordered()/_get_list().
>
> Agreed, this series looks more or less good (and mostly mechanical
> anyway).
Thanks.
> Is it an RFC or what? :) I wonder if reviewers are put off by
> the subject.
The implied RFC is, are we okay with reusing "CPUState" this way? Or
does someone - last call! - have a better identifier name?
Getting this series merged either means coordinating the PULL with a
maintainer so that no merge conflicts arise in-flight, or having the
maintainer re-run the commit-creating script himself.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-13 12:53 ` Andreas Färber
@ 2012-03-13 13:03 ` Paolo Bonzini
0 siblings, 0 replies; 175+ messages in thread
From: Paolo Bonzini @ 2012-03-13 13:03 UTC (permalink / raw)
To: Andreas Färber; +Cc: Igor Mammedov, qemu-devel, Anthony Liguori
Il 13/03/2012 13:53, Andreas Färber ha scritto:
>> > Methods should not take a superclass
>> > argument in general.
> So to clarify, this is pro CPUState?
Yes.
>>> >> This series is taking much too long to move forward (the QOM "steam"
>>> >> seems to be gone?) and I'm worried that introducing much more basic
>>> >> infrastructure will make review and applying even slower, cf.
>>> >> object_class_foreach_ordered()/_get_list().
>> >
>> > Agreed, this series looks more or less good (and mostly mechanical
>> > anyway).
> Thanks.
>
>> > Is it an RFC or what? :) I wonder if reviewers are put off by
>> > the subject.
> The implied RFC is, are we okay with reusing "CPUState" this way? Or
> does someone - last call! - have a better identifier name?
>
> Getting this series merged either means coordinating the PULL with a
> maintainer so that no merge conflicts arise in-flight, or having the
> maintainer re-run the commit-creating script himself.
FWIW I like it. :)
Paolo
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
@ 2012-03-13 13:18 ` Paolo Bonzini
2012-03-14 22:30 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Paolo Bonzini @ 2012-03-13 13:18 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Richard Henderson, qemu-devel, Anthony Liguori,
Paul Brook
Il 10/03/2012 17:53, Andreas Färber ha scritto:
> /**
> * ARMCPU:
> + * @env: Legacy CPU state.
> *
> * An ARM CPU core.
> */
> @@ -58,7 +60,17 @@ typedef struct ARMCPU {
> /*< private >*/
> CPUState parent_obj;
> /*< public >*/
> +
> + /* TODO Inline this and split off common state */
> + CPUARMState env;
> } ARMCPU;
>
As usual I don't like "legacy". :) A more interesting distinction is
between state that is relevant to the emulation, and state that is
relevant to the main loop or the machine. The former is reinitialized
after reset and can remain in CPUFooState. The latter is not
reinitialized after reset, can move to QOM, and in most cases that's
what we access when we use CPUArchState.
Also, I understand that the conversion is not fully mechanical, but
perhaps it can be made "more" mechanical than this? Splitting this
patch in two would be nice, but I can't say I read it fully.
Paolo
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-13 12:31 ` Igor Mitsyanko
@ 2012-03-13 17:58 ` Andreas Färber
2012-03-13 18:04 ` Eric Blake
` (3 more replies)
0 siblings, 4 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-13 17:58 UTC (permalink / raw)
To: i.mitsyanko
Cc: Peter Maydell, Paul Brook, qemu-devel, Anthony Liguori, Dmitry Solodkiy
Am 13.03.2012 13:31, schrieb Igor Mitsyanko:
> On 03/10/2012 08:53 PM, Andreas Färber wrote:
>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> new file mode 100644
>> index 0000000..dabc094
>> --- /dev/null
>> +++ b/target-arm/cpu.c
[...]
>> +static void cpu_register(const ARMCPUInfo *info)
>> +{
>> + TypeInfo type = {
>> + .name = info->name,
>> + .parent = TYPE_ARM_CPU,
>> + .instance_size = sizeof(ARMCPU),
>> + .class_size = sizeof(ARMCPUClass),
>> + .class_init = arm_cpu_class_init,
>> + .class_data = (void *)info,
>> + };
>
> Are non-initialized members guaranteed to be zero here?
I thought so for the C99-style struct initialization... I never ran into
crashes while testing. Do we need static to be safe?
>> + type_register_static(&type);
>> +}
>> +
>
> Probably should be type_register() here in case these two will actually
> differ in the future.
My thinking was we don't need it here because the data (esp. strings)
are not dynamically allocated. By comparison, I used type_register() for
-cpudef in target-i386, I believe.
But I really guess it's a bug that they're just an alias right now! ;)
> If this information is of any help, we've got no problems when emulating
> ARM-based Exynos boards in QEMU with this whole patchset applied.
Thanks a lot for testing!
Have you thought about how to QOM'ify your boards? Mid-term I'd like to
see an "exynos4210" object with the CPUs on it - maybe "cpu[0]" and
"cpu[1]" child properties? Or "core[x]"? I had played with the sh7750 a
bit on my branch but like the arm926 it's a single-core.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset()
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
@ 2012-03-13 18:02 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:02 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> Frees the identifier cpu_reset for QOM CPUs (manual rename).
>
> Don't hide the parameter type behind explicit casts, use static
> functions with strongly typed argument to indirect.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Regards,
Anthony Liguori
> ---
> bsd-user/main.c | 2 +-
> cpu-all.h | 2 +-
> cpu-exec.c | 2 +-
> darwin-user/main.c | 2 +-
> hw/arm_boot.c | 2 +-
> hw/armv7m.c | 2 +-
> hw/cris-boot.c | 2 +-
> hw/leon3.c | 2 +-
> hw/lm32_boards.c | 2 +-
> hw/microblaze_boot.c | 2 +-
> hw/milkymist.c | 2 +-
> hw/mips_fulong2e.c | 2 +-
> hw/mips_jazz.c | 2 +-
> hw/mips_malta.c | 2 +-
> hw/mips_mipssim.c | 2 +-
> hw/mips_r4k.c | 2 +-
> hw/omap1.c | 2 +-
> hw/omap2.c | 2 +-
> hw/pc.c | 2 +-
> hw/ppc440_bamboo.c | 2 +-
> hw/ppc4xx_devs.c | 9 ++++++++-
> hw/ppc_newworld.c | 9 ++++++++-
> hw/ppc_oldworld.c | 9 ++++++++-
> hw/ppc_prep.c | 9 ++++++++-
> hw/ppce500_mpc8544ds.c | 4 ++--
> hw/pxa2xx.c | 2 +-
> hw/r2d.c | 2 +-
> hw/spapr.c | 9 ++++++++-
> hw/sun4m.c | 4 ++--
> hw/sun4u.c | 2 +-
> hw/virtex_ml507.c | 2 +-
> hw/xtensa_lx60.c | 8 +++++---
> hw/xtensa_sim.c | 2 +-
> linux-user/main.c | 2 +-
> linux-user/syscall.c | 2 +-
> target-arm/helper.c | 4 ++--
> target-cris/translate.c | 4 ++--
> target-i386/helper.c | 4 ++--
> target-lm32/helper.c | 4 ++--
> target-m68k/helper.c | 4 ++--
> target-microblaze/translate.c | 4 ++--
> target-mips/helper.c | 2 +-
> target-mips/translate.c | 4 ++--
> target-ppc/helper.c | 2 +-
> target-s390x/helper.c | 4 ++--
> target-sh4/translate.c | 4 ++--
> target-sparc/cpu_init.c | 2 +-
> target-xtensa/helper.c | 2 +-
> 48 files changed, 98 insertions(+), 61 deletions(-)
>
> diff --git a/bsd-user/main.c b/bsd-user/main.c
> index cdb0d0a..c3af395 100644
> --- a/bsd-user/main.c
> +++ b/bsd-user/main.c
> @@ -917,7 +917,7 @@ int main(int argc, char **argv)
> exit(1);
> }
> #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
> - cpu_reset(env);
> + cpu_state_reset(env);
> #endif
> thread_env = env;
>
> diff --git a/cpu-all.h b/cpu-all.h
> index 80e6d42..7586c0d 100644
> --- a/cpu-all.h
> +++ b/cpu-all.h
> @@ -433,7 +433,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask);
> #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
>
> void cpu_single_step(CPUState *env, int enabled);
> -void cpu_reset(CPUState *s);
> +void cpu_state_reset(CPUState *s);
> int cpu_is_stopped(CPUState *env);
> void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
>
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 3d28053..2bf1735 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -340,7 +340,7 @@ int cpu_exec(CPUState *env)
> }
> #elif defined(TARGET_PPC)
> if ((interrupt_request& CPU_INTERRUPT_RESET)) {
> - cpu_reset(env);
> + cpu_state_reset(env);
> }
> if (interrupt_request& CPU_INTERRUPT_HARD) {
> ppc_hw_interrupt(env);
> diff --git a/darwin-user/main.c b/darwin-user/main.c
> index e1519c7..13c1f05 100644
> --- a/darwin-user/main.c
> +++ b/darwin-user/main.c
> @@ -858,7 +858,7 @@ int main(int argc, char **argv)
> /* NOTE: we need to init the CPU at this stage to get
> qemu_host_page_size */
> env = cpu_init(cpu_model);
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> printf("Starting %s with qemu\n----------------\n", filename);
>
> diff --git a/hw/arm_boot.c b/hw/arm_boot.c
> index fc66910..23b3f0a 100644
> --- a/hw/arm_boot.c
> +++ b/hw/arm_boot.c
> @@ -277,7 +277,7 @@ static void do_cpu_reset(void *opaque)
> CPUState *env = opaque;
> const struct arm_boot_info *info = env->boot_info;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> if (info) {
> if (!info->is_linux) {
> /* Jump to the entry point. */
> diff --git a/hw/armv7m.c b/hw/armv7m.c
> index 6b80579..9cf96f4 100644
> --- a/hw/armv7m.c
> +++ b/hw/armv7m.c
> @@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
>
> static void armv7m_reset(void *opaque)
> {
> - cpu_reset((CPUState *)opaque);
> + cpu_state_reset((CPUState *)opaque);
> }
>
> /* Init CPU and memory for a v7-M based board.
> diff --git a/hw/cris-boot.c b/hw/cris-boot.c
> index 37894f8..ade517d 100644
> --- a/hw/cris-boot.c
> +++ b/hw/cris-boot.c
> @@ -34,7 +34,7 @@ static void main_cpu_reset(void *opaque)
>
> li = env->load_info;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> if (!li) {
> /* nothing more to do. */
> diff --git a/hw/leon3.c b/hw/leon3.c
> index 71d79a6..1dc5a02 100644
> --- a/hw/leon3.c
> +++ b/hw/leon3.c
> @@ -51,7 +51,7 @@ static void main_cpu_reset(void *opaque)
> ResetData *s = (ResetData *)opaque;
> CPUState *env = s->env;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> env->halted = 0;
> env->pc = s->entry;
> diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
> index 3cdf120..51c8a0f 100644
> --- a/hw/lm32_boards.c
> +++ b/hw/lm32_boards.c
> @@ -56,7 +56,7 @@ static void main_cpu_reset(void *opaque)
> ResetInfo *reset_info = opaque;
> CPUState *env = reset_info->env;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> /* init defaults */
> env->pc = (uint32_t)reset_info->bootstrap_pc;
> diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c
> index b2f96df..7ce04dc 100644
> --- a/hw/microblaze_boot.c
> +++ b/hw/microblaze_boot.c
> @@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->regs[5] = boot_info.cmdline;
> env->regs[7] = boot_info.fdt;
> env->sregs[SR_PC] = boot_info.bootstrap_pc;
> diff --git a/hw/milkymist.c b/hw/milkymist.c
> index eaef0c2..7ec6554 100644
> --- a/hw/milkymist.c
> +++ b/hw/milkymist.c
> @@ -61,7 +61,7 @@ static void main_cpu_reset(void *opaque)
> ResetInfo *reset_info = opaque;
> CPUState *env = reset_info->env;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> /* init defaults */
> env->pc = reset_info->bootstrap_pc;
> diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
> index e3ba9dd..2db8ba0 100644
> --- a/hw/mips_fulong2e.c
> +++ b/hw/mips_fulong2e.c
> @@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> /* TODO: 2E reset stuff */
> if (loaderparams.kernel_filename) {
> env->CP0_Status&= ~((1<< CP0St_BEV) | (1<< CP0St_ERL));
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 2b4678e..d5f1b34 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -51,7 +51,7 @@ enum jazz_model_e
> static void main_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
> - cpu_reset(env);
> + cpu_state_reset(env);
> }
>
> static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
> diff --git a/hw/mips_malta.c b/hw/mips_malta.c
> index b1563ed..887faea 100644
> --- a/hw/mips_malta.c
> +++ b/hw/mips_malta.c
> @@ -746,7 +746,7 @@ static void malta_mips_config(CPUState *env)
> static void main_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> /* The bootloader does not need to be rewritten as it is located in a
> read only location. The kernel location and the arguments table
> diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
> index 76c95b2..1fe4ac5 100644
> --- a/hw/mips_mipssim.c
> +++ b/hw/mips_mipssim.c
> @@ -107,7 +107,7 @@ static void main_cpu_reset(void *opaque)
> ResetData *s = (ResetData *)opaque;
> CPUState *env = s->env;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->active_tc.PC = s->vector& ~(target_ulong)1;
> if (s->vector& 1) {
> env->hflags |= MIPS_HFLAG_M16;
> diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
> index 83401f0..96ad808 100644
> --- a/hw/mips_r4k.c
> +++ b/hw/mips_r4k.c
> @@ -145,7 +145,7 @@ static void main_cpu_reset(void *opaque)
> ResetData *s = (ResetData *)opaque;
> CPUState *env = s->env;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->active_tc.PC = s->vector;
> }
>
> diff --git a/hw/omap1.c b/hw/omap1.c
> index 1aa5f23..5317b9b 100644
> --- a/hw/omap1.c
> +++ b/hw/omap1.c
> @@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque)
> omap_lpg_reset(mpu->led[0]);
> omap_lpg_reset(mpu->led[1]);
> omap_clkm_reset(mpu);
> - cpu_reset(mpu->env);
> + cpu_state_reset(mpu->env);
> }
>
> static const struct omap_map_s {
> diff --git a/hw/omap2.c b/hw/omap2.c
> index a6851b0..157defb 100644
> --- a/hw/omap2.c
> +++ b/hw/omap2.c
> @@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque)
> omap_mcspi_reset(mpu->mcspi[1]);
> omap_i2c_reset(mpu->i2c[0]);
> omap_i2c_reset(mpu->i2c[1]);
> - cpu_reset(mpu->env);
> + cpu_state_reset(mpu->env);
> }
>
> static int omap2_validate_addr(struct omap_mpu_state_s *s,
> diff --git a/hw/pc.c b/hw/pc.c
> index bb9867b..aca4460 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -928,7 +928,7 @@ static void pc_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->halted = !cpu_is_bsp(env);
> }
>
> diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
> index f86b168..835e36d 100644
> --- a/hw/ppc440_bamboo.c
> +++ b/hw/ppc440_bamboo.c
> @@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->gpr[1] = (16<<20) - 8;
> env->gpr[3] = FDT_ADDR;
> env->nip = entry;
> diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
> index 26040ac..2311162 100644
> --- a/hw/ppc4xx_devs.c
> +++ b/hw/ppc4xx_devs.c
> @@ -38,6 +38,13 @@
> # define LOG_UIC(...) do { } while (0)
> #endif
>
> +static void ppc4xx_reset(void *opaque)
> +{
> + CPUState *env = opaque;
> +
> + cpu_state_reset(env);
> +}
> +
> /*****************************************************************************/
> /* Generic PowerPC 4xx processor instantiation */
> CPUState *ppc4xx_init (const char *cpu_model,
> @@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
> tb_clk->opaque = env;
> ppc_dcr_init(env, NULL, NULL);
> /* Register qemu callbacks */
> - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
> + qemu_register_reset(ppc4xx_reset, env);
>
> return env;
> }
> diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
> index 506187b..fd8e21d 100644
> --- a/hw/ppc_newworld.c
> +++ b/hw/ppc_newworld.c
> @@ -122,6 +122,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
> return (addr + TARGET_PAGE_SIZE - 1)& TARGET_PAGE_MASK;
> }
>
> +static void ppc_core99_reset(void *opaque)
> +{
> + CPUState *env = opaque;
> +
> + cpu_state_reset(env);
> +}
> +
> /* PowerPC Mac99 hardware initialisation */
> static void ppc_core99_init (ram_addr_t ram_size,
> const char *boot_device,
> @@ -167,7 +174,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
> }
> /* Set time-base frequency to 100 Mhz */
> cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
> - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
> + qemu_register_reset(ppc_core99_reset, env);
> }
>
> /* allocate RAM */
> diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
> index 9295a34..085b825 100644
> --- a/hw/ppc_oldworld.c
> +++ b/hw/ppc_oldworld.c
> @@ -66,6 +66,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
> return (addr + TARGET_PAGE_SIZE - 1)& TARGET_PAGE_MASK;
> }
>
> +static void ppc_heathrow_reset(void *opaque)
> +{
> + CPUState *env = opaque;
> +
> + cpu_state_reset(env);
> +}
> +
> static void ppc_heathrow_init (ram_addr_t ram_size,
> const char *boot_device,
> const char *kernel_filename,
> @@ -105,7 +112,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
> }
> /* Set time-base frequency to 16.6 Mhz */
> cpu_ppc_tb_init(env, 16600000UL);
> - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
> + qemu_register_reset(ppc_heathrow_reset, env);
> }
>
> /* allocate RAM */
> diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
> index eb43fb5..c5f2542 100644
> --- a/hw/ppc_prep.c
> +++ b/hw/ppc_prep.c
> @@ -471,6 +471,13 @@ static void cpu_request_exit(void *opaque, int irq, int level)
> }
> }
>
> +static void ppc_prep_reset(void *opaque)
> +{
> + CPUState *env = opaque;
> +
> + cpu_state_reset(env);
> +}
> +
> /* PowerPC PREP hardware initialisation */
> static void ppc_prep_init (ram_addr_t ram_size,
> const char *boot_device,
> @@ -525,7 +532,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
> /* Set time-base frequency to 100 Mhz */
> cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
> }
> - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
> + qemu_register_reset(ppc_prep_reset, env);
> }
>
> /* allocate RAM */
> diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
> index d69f78c..752aed9 100644
> --- a/hw/ppce500_mpc8544ds.c
> +++ b/hw/ppce500_mpc8544ds.c
> @@ -198,7 +198,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> /* Secondary CPU starts in halted state for now. Needs to change when
> implementing non-kernel boot. */
> @@ -211,7 +211,7 @@ static void mpc8544ds_cpu_reset(void *opaque)
> CPUState *env = opaque;
> struct boot_info *bi = env->load_info;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> /* Set initial guest state. */
> env->halted = 0;
> diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
> index 1ab2701..f552877 100644
> --- a/hw/pxa2xx.c
> +++ b/hw/pxa2xx.c
> @@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level)
> PXA2xxState *s = (PXA2xxState *) opaque;
>
> if (level&& (s->pm_regs[PCFR>> 2]& 0x10)) { /* GPR_EN */
> - cpu_reset(s->env);
> + cpu_state_reset(s->env);
> /* TODO: reset peripherals */
> }
> }
> diff --git a/hw/r2d.c b/hw/r2d.c
> index c80f9e3..ae327a7 100644
> --- a/hw/r2d.c
> +++ b/hw/r2d.c
> @@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque)
> ResetData *s = (ResetData *)opaque;
> CPUState *env = s->env;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->pc = s->vector;
> }
>
> diff --git a/hw/spapr.c b/hw/spapr.c
> index dffb6a2..3f9d87c 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -502,6 +502,13 @@ static void spapr_reset(void *opaque)
>
> }
>
> +static void spapr_cpu_reset(void *opaque)
> +{
> + CPUState *env = opaque;
> +
> + cpu_state_reset(env);
> +}
> +
> /* pSeries LPAR / sPAPR hardware init */
> static void ppc_spapr_init(ram_addr_t ram_size,
> const char *boot_device,
> @@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
> }
> /* Set time-base frequency to 512 MHz */
> cpu_ppc_tb_init(env, TIMEBASE_FREQ);
> - qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
> + qemu_register_reset(spapr_cpu_reset, env);
>
> env->hreset_vector = 0x60;
> env->hreset_excp_prefix = 0;
> diff --git a/hw/sun4m.c b/hw/sun4m.c
> index 99fb219..4045740 100644
> --- a/hw/sun4m.c
> +++ b/hw/sun4m.c
> @@ -283,7 +283,7 @@ static void main_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->halted = 0;
> }
>
> @@ -291,7 +291,7 @@ static void secondary_cpu_reset(void *opaque)
> {
> CPUState *env = opaque;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->halted = 1;
> }
>
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index 423108f..8b043f2 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -376,7 +376,7 @@ static void main_cpu_reset(void *opaque)
> CPUState *env = s->env;
> static unsigned int nr_resets;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
>
> cpu_timer_reset(env->tick);
> cpu_timer_reset(env->stick);
> diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
> index f8d2b1b..e672490 100644
> --- a/hw/virtex_ml507.c
> +++ b/hw/virtex_ml507.c
> @@ -109,7 +109,7 @@ static void main_cpu_reset(void *opaque)
> CPUState *env = opaque;
> struct boot_info *bi = env->load_info;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> /* Linux Kernel Parameters (passing device tree):
> * r3: pointer to the fdt
> * r4: 0
> diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
> index 26112c3..80ba4d7 100644
> --- a/hw/xtensa_lx60.c
> +++ b/hw/xtensa_lx60.c
> @@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
> return cpu_get_phys_page_debug(env, addr);
> }
>
> -static void lx60_reset(void *env)
> +static void lx60_reset(void *opaque)
> {
> - cpu_reset(env);
> + CPUState *env = opaque;
> +
> + cpu_state_reset(env);
> }
>
> static void lx_init(const LxBoardDesc *board,
> @@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board,
> /* Need MMU initialized prior to ELF loading,
> * so that ELF gets loaded into virtual addresses
> */
> - cpu_reset(env);
> + cpu_state_reset(env);
> }
>
> ram = g_malloc(sizeof(*ram));
> diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
> index 104e5dc..445cfde 100644
> --- a/hw/xtensa_sim.c
> +++ b/hw/xtensa_sim.c
> @@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
>
> static void sim_reset(void *env)
> {
> - cpu_reset(env);
> + cpu_state_reset(env);
> }
>
> static void sim_init(ram_addr_t ram_size,
> diff --git a/linux-user/main.c b/linux-user/main.c
> index bd47489..01129f2 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -3375,7 +3375,7 @@ int main(int argc, char **argv, char **envp)
> exit(1);
> }
> #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
> - cpu_reset(env);
> + cpu_state_reset(env);
> #endif
>
> thread_env = env;
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 8a11213..29888bd 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -4036,7 +4036,7 @@ static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp,
> /* we create a new CPU instance. */
> new_env = cpu_copy(env);
> #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
> - cpu_reset(new_env);
> + cpu_state_reset(new_env);
> #endif
> /* Init regs that differ from the parent. */
> cpu_clone_regs(new_env, newsp);
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index abe1c30..13ff474 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -278,7 +278,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
> }
> }
>
> -void cpu_reset(CPUARMState *env)
> +void cpu_state_reset(CPUARMState *env)
> {
> uint32_t id;
> uint32_t tmp = 0;
> @@ -416,7 +416,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
>
> env->cpu_model_str = cpu_model;
> env->cp15.c0_cpuid = id;
> - cpu_reset(env);
> + cpu_state_reset(env);
> if (arm_feature(env, ARM_FEATURE_NEON)) {
> gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
> 51, "arm-neon.xml", 0);
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index cbdc72c..f360c31 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -3513,7 +3513,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
>
> env->pregs[PR_VR] = vr_by_name(cpu_model);
> cpu_exec_init(env);
> - cpu_reset(env);
> + cpu_state_reset(env);
> qemu_init_vcpu(env);
>
> if (tcg_initialized)
> @@ -3573,7 +3573,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
> return env;
> }
>
> -void cpu_reset (CPUCRISState *env)
> +void cpu_state_reset(CPUCRISState *env)
> {
> uint32_t vr;
>
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index af6bba2..0d84c27 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -27,7 +27,7 @@
> //#define DEBUG_MMU
>
> /* NOTE: must be called outside the CPU execute loop */
> -void cpu_reset(CPUX86State *env)
> +void cpu_state_reset(CPUState *env)
> {
> int i;
>
> @@ -1281,7 +1281,7 @@ void do_cpu_init(CPUState *env)
> int sipi = env->interrupt_request& CPU_INTERRUPT_SIPI;
> uint64_t pat = env->pat;
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> env->interrupt_request = sipi;
> env->pat = pat;
> apic_init_reset(env->apic_state);
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index 2637c03..6834401 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -212,7 +212,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
> env->flags = 0;
>
> cpu_exec_init(env);
> - cpu_reset(env);
> + cpu_state_reset(env);
> qemu_init_vcpu(env);
>
> if (!tcg_initialized) {
> @@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
> }
> }
>
> -void cpu_reset(CPUState *env)
> +void cpu_state_reset(CPUState *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index fa675bf..3647366 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -143,7 +143,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
> return 0;
> }
>
> -void cpu_reset(CPUM68KState *env)
> +void cpu_state_reset(CPUM68KState *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> @@ -181,7 +181,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
> return NULL;
> }
>
> - cpu_reset(env);
> + cpu_state_reset(env);
> qemu_init_vcpu(env);
> return env;
> }
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 725c2dd..e34e88d 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1897,7 +1897,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
> env = g_malloc0(sizeof(CPUState));
>
> cpu_exec_init(env);
> - cpu_reset(env);
> + cpu_state_reset(env);
> qemu_init_vcpu(env);
> set_float_rounding_mode(float_round_nearest_even,&env->fp_status);
>
> @@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
> return env;
> }
>
> -void cpu_reset (CPUState *env)
> +void cpu_state_reset(CPUState *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index 7225616..4d1cf98 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -452,7 +452,7 @@ void do_interrupt (CPUState *env)
> set_hflags_for_handler(env);
> break;
> case EXCP_RESET:
> - cpu_reset(env);
> + cpu_state_reset(env);
> break;
> case EXCP_SRESET:
> env->CP0_Status |= (1<< CP0St_SR);
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 8361d88..5061e78 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12708,12 +12708,12 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
> fpu_init(env, def);
> mvp_init(env, def);
> mips_tcg_init();
> - cpu_reset(env);
> + cpu_state_reset(env);
> qemu_init_vcpu(env);
> return env;
> }
>
> -void cpu_reset (CPUMIPSState *env)
> +void cpu_state_reset(CPUMIPSState *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> index bb76a8b..f4552e8 100644
> --- a/target-ppc/helper.c
> +++ b/target-ppc/helper.c
> @@ -3136,7 +3136,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
> TARGET_FMT_lx "\n", RA, msr);
> }
>
> -void cpu_reset(CPUPPCState *env)
> +void cpu_state_reset(CPUPPCState *env)
> {
> target_ulong msr;
>
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index c0ec890..1a1cc0eb 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -95,7 +95,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
> env->cpu_model_str = cpu_model;
> env->cpu_num = cpu_num++;
> env->ext_index = -1;
> - cpu_reset(env);
> + cpu_state_reset(env);
> qemu_init_vcpu(env);
> return env;
> }
> @@ -119,7 +119,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
>
> #endif /* CONFIG_USER_ONLY */
>
> -void cpu_reset(CPUS390XState *env)
> +void cpu_state_reset(CPUS390XState *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index dd0ee4b..c385de8 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -178,7 +178,7 @@ void cpu_dump_state(CPUState * env, FILE * f,
> }
> }
>
> -void cpu_reset(CPUSH4State * env)
> +void cpu_state_reset(CPUSH4State *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> @@ -279,7 +279,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
> env->movcal_backup_tail =&(env->movcal_backup);
> sh4_translate_init();
> env->cpu_model_str = cpu_model;
> - cpu_reset(env);
> + cpu_state_reset(env);
> cpu_register(env, def);
> qemu_init_vcpu(env);
> return env;
> diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
> index c7269b5..bb8b761 100644
> --- a/target-sparc/cpu_init.c
> +++ b/target-sparc/cpu_init.c
> @@ -23,7 +23,7 @@
>
> static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
>
> -void cpu_reset(CPUSPARCState *env)
> +void cpu_state_reset(CPUSPARCState *env)
> {
> if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
> index 42a559f..077c20a 100644
> --- a/target-xtensa/helper.c
> +++ b/target-xtensa/helper.c
> @@ -35,7 +35,7 @@
>
> static void reset_mmu(CPUState *env);
>
> -void cpu_reset(CPUXtensaState *env)
> +void cpu_state_reset(CPUXtensaState *env)
> {
> env->exception_taken = 0;
> env->pc = env->config->exception_vector[EXC_RESET];
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
@ 2012-03-13 18:02 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:02 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> Use CPUX86State etc. instead (hand-converted).
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Regards,
Anthony Liguori
> ---
> monitor.c | 488 ++++++++++++++++++++++++++++++------------------------------
> 1 files changed, 244 insertions(+), 244 deletions(-)
>
> diff --git a/monitor.c b/monitor.c
> index cbdfbad..e3b72ff 100644
> --- a/monitor.c
> +++ b/monitor.c
> @@ -2696,30 +2696,30 @@ static const MonitorDef monitor_defs[] = {
> #ifdef TARGET_I386
>
> #define SEG(name, seg) \
> - { name, offsetof(CPUState, segs[seg].selector), NULL, MD_I32 },\
> - { name ".base", offsetof(CPUState, segs[seg].base) },\
> - { name ".limit", offsetof(CPUState, segs[seg].limit), NULL, MD_I32 },
> + { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
> + { name ".base", offsetof(CPUX86State, segs[seg].base) },\
> + { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
>
> - { "eax", offsetof(CPUState, regs[0]) },
> - { "ecx", offsetof(CPUState, regs[1]) },
> - { "edx", offsetof(CPUState, regs[2]) },
> - { "ebx", offsetof(CPUState, regs[3]) },
> - { "esp|sp", offsetof(CPUState, regs[4]) },
> - { "ebp|fp", offsetof(CPUState, regs[5]) },
> - { "esi", offsetof(CPUState, regs[6]) },
> - { "edi", offsetof(CPUState, regs[7]) },
> + { "eax", offsetof(CPUX86State, regs[0]) },
> + { "ecx", offsetof(CPUX86State, regs[1]) },
> + { "edx", offsetof(CPUX86State, regs[2]) },
> + { "ebx", offsetof(CPUX86State, regs[3]) },
> + { "esp|sp", offsetof(CPUX86State, regs[4]) },
> + { "ebp|fp", offsetof(CPUX86State, regs[5]) },
> + { "esi", offsetof(CPUX86State, regs[6]) },
> + { "edi", offsetof(CPUX86State, regs[7]) },
> #ifdef TARGET_X86_64
> - { "r8", offsetof(CPUState, regs[8]) },
> - { "r9", offsetof(CPUState, regs[9]) },
> - { "r10", offsetof(CPUState, regs[10]) },
> - { "r11", offsetof(CPUState, regs[11]) },
> - { "r12", offsetof(CPUState, regs[12]) },
> - { "r13", offsetof(CPUState, regs[13]) },
> - { "r14", offsetof(CPUState, regs[14]) },
> - { "r15", offsetof(CPUState, regs[15]) },
> + { "r8", offsetof(CPUX86State, regs[8]) },
> + { "r9", offsetof(CPUX86State, regs[9]) },
> + { "r10", offsetof(CPUX86State, regs[10]) },
> + { "r11", offsetof(CPUX86State, regs[11]) },
> + { "r12", offsetof(CPUX86State, regs[12]) },
> + { "r13", offsetof(CPUX86State, regs[13]) },
> + { "r14", offsetof(CPUX86State, regs[14]) },
> + { "r15", offsetof(CPUX86State, regs[15]) },
> #endif
> - { "eflags", offsetof(CPUState, eflags) },
> - { "eip", offsetof(CPUState, eip) },
> + { "eflags", offsetof(CPUX86State, eflags) },
> + { "eip", offsetof(CPUX86State, eip) },
> SEG("cs", R_CS)
> SEG("ds", R_DS)
> SEG("es", R_ES)
> @@ -2729,76 +2729,76 @@ static const MonitorDef monitor_defs[] = {
> { "pc", 0, monitor_get_pc, },
> #elif defined(TARGET_PPC)
> /* General purpose registers */
> - { "r0", offsetof(CPUState, gpr[0]) },
> - { "r1", offsetof(CPUState, gpr[1]) },
> - { "r2", offsetof(CPUState, gpr[2]) },
> - { "r3", offsetof(CPUState, gpr[3]) },
> - { "r4", offsetof(CPUState, gpr[4]) },
> - { "r5", offsetof(CPUState, gpr[5]) },
> - { "r6", offsetof(CPUState, gpr[6]) },
> - { "r7", offsetof(CPUState, gpr[7]) },
> - { "r8", offsetof(CPUState, gpr[8]) },
> - { "r9", offsetof(CPUState, gpr[9]) },
> - { "r10", offsetof(CPUState, gpr[10]) },
> - { "r11", offsetof(CPUState, gpr[11]) },
> - { "r12", offsetof(CPUState, gpr[12]) },
> - { "r13", offsetof(CPUState, gpr[13]) },
> - { "r14", offsetof(CPUState, gpr[14]) },
> - { "r15", offsetof(CPUState, gpr[15]) },
> - { "r16", offsetof(CPUState, gpr[16]) },
> - { "r17", offsetof(CPUState, gpr[17]) },
> - { "r18", offsetof(CPUState, gpr[18]) },
> - { "r19", offsetof(CPUState, gpr[19]) },
> - { "r20", offsetof(CPUState, gpr[20]) },
> - { "r21", offsetof(CPUState, gpr[21]) },
> - { "r22", offsetof(CPUState, gpr[22]) },
> - { "r23", offsetof(CPUState, gpr[23]) },
> - { "r24", offsetof(CPUState, gpr[24]) },
> - { "r25", offsetof(CPUState, gpr[25]) },
> - { "r26", offsetof(CPUState, gpr[26]) },
> - { "r27", offsetof(CPUState, gpr[27]) },
> - { "r28", offsetof(CPUState, gpr[28]) },
> - { "r29", offsetof(CPUState, gpr[29]) },
> - { "r30", offsetof(CPUState, gpr[30]) },
> - { "r31", offsetof(CPUState, gpr[31]) },
> + { "r0", offsetof(CPUPPCState, gpr[0]) },
> + { "r1", offsetof(CPUPPCState, gpr[1]) },
> + { "r2", offsetof(CPUPPCState, gpr[2]) },
> + { "r3", offsetof(CPUPPCState, gpr[3]) },
> + { "r4", offsetof(CPUPPCState, gpr[4]) },
> + { "r5", offsetof(CPUPPCState, gpr[5]) },
> + { "r6", offsetof(CPUPPCState, gpr[6]) },
> + { "r7", offsetof(CPUPPCState, gpr[7]) },
> + { "r8", offsetof(CPUPPCState, gpr[8]) },
> + { "r9", offsetof(CPUPPCState, gpr[9]) },
> + { "r10", offsetof(CPUPPCState, gpr[10]) },
> + { "r11", offsetof(CPUPPCState, gpr[11]) },
> + { "r12", offsetof(CPUPPCState, gpr[12]) },
> + { "r13", offsetof(CPUPPCState, gpr[13]) },
> + { "r14", offsetof(CPUPPCState, gpr[14]) },
> + { "r15", offsetof(CPUPPCState, gpr[15]) },
> + { "r16", offsetof(CPUPPCState, gpr[16]) },
> + { "r17", offsetof(CPUPPCState, gpr[17]) },
> + { "r18", offsetof(CPUPPCState, gpr[18]) },
> + { "r19", offsetof(CPUPPCState, gpr[19]) },
> + { "r20", offsetof(CPUPPCState, gpr[20]) },
> + { "r21", offsetof(CPUPPCState, gpr[21]) },
> + { "r22", offsetof(CPUPPCState, gpr[22]) },
> + { "r23", offsetof(CPUPPCState, gpr[23]) },
> + { "r24", offsetof(CPUPPCState, gpr[24]) },
> + { "r25", offsetof(CPUPPCState, gpr[25]) },
> + { "r26", offsetof(CPUPPCState, gpr[26]) },
> + { "r27", offsetof(CPUPPCState, gpr[27]) },
> + { "r28", offsetof(CPUPPCState, gpr[28]) },
> + { "r29", offsetof(CPUPPCState, gpr[29]) },
> + { "r30", offsetof(CPUPPCState, gpr[30]) },
> + { "r31", offsetof(CPUPPCState, gpr[31]) },
> /* Floating point registers */
> - { "f0", offsetof(CPUState, fpr[0]) },
> - { "f1", offsetof(CPUState, fpr[1]) },
> - { "f2", offsetof(CPUState, fpr[2]) },
> - { "f3", offsetof(CPUState, fpr[3]) },
> - { "f4", offsetof(CPUState, fpr[4]) },
> - { "f5", offsetof(CPUState, fpr[5]) },
> - { "f6", offsetof(CPUState, fpr[6]) },
> - { "f7", offsetof(CPUState, fpr[7]) },
> - { "f8", offsetof(CPUState, fpr[8]) },
> - { "f9", offsetof(CPUState, fpr[9]) },
> - { "f10", offsetof(CPUState, fpr[10]) },
> - { "f11", offsetof(CPUState, fpr[11]) },
> - { "f12", offsetof(CPUState, fpr[12]) },
> - { "f13", offsetof(CPUState, fpr[13]) },
> - { "f14", offsetof(CPUState, fpr[14]) },
> - { "f15", offsetof(CPUState, fpr[15]) },
> - { "f16", offsetof(CPUState, fpr[16]) },
> - { "f17", offsetof(CPUState, fpr[17]) },
> - { "f18", offsetof(CPUState, fpr[18]) },
> - { "f19", offsetof(CPUState, fpr[19]) },
> - { "f20", offsetof(CPUState, fpr[20]) },
> - { "f21", offsetof(CPUState, fpr[21]) },
> - { "f22", offsetof(CPUState, fpr[22]) },
> - { "f23", offsetof(CPUState, fpr[23]) },
> - { "f24", offsetof(CPUState, fpr[24]) },
> - { "f25", offsetof(CPUState, fpr[25]) },
> - { "f26", offsetof(CPUState, fpr[26]) },
> - { "f27", offsetof(CPUState, fpr[27]) },
> - { "f28", offsetof(CPUState, fpr[28]) },
> - { "f29", offsetof(CPUState, fpr[29]) },
> - { "f30", offsetof(CPUState, fpr[30]) },
> - { "f31", offsetof(CPUState, fpr[31]) },
> - { "fpscr", offsetof(CPUState, fpscr) },
> + { "f0", offsetof(CPUPPCState, fpr[0]) },
> + { "f1", offsetof(CPUPPCState, fpr[1]) },
> + { "f2", offsetof(CPUPPCState, fpr[2]) },
> + { "f3", offsetof(CPUPPCState, fpr[3]) },
> + { "f4", offsetof(CPUPPCState, fpr[4]) },
> + { "f5", offsetof(CPUPPCState, fpr[5]) },
> + { "f6", offsetof(CPUPPCState, fpr[6]) },
> + { "f7", offsetof(CPUPPCState, fpr[7]) },
> + { "f8", offsetof(CPUPPCState, fpr[8]) },
> + { "f9", offsetof(CPUPPCState, fpr[9]) },
> + { "f10", offsetof(CPUPPCState, fpr[10]) },
> + { "f11", offsetof(CPUPPCState, fpr[11]) },
> + { "f12", offsetof(CPUPPCState, fpr[12]) },
> + { "f13", offsetof(CPUPPCState, fpr[13]) },
> + { "f14", offsetof(CPUPPCState, fpr[14]) },
> + { "f15", offsetof(CPUPPCState, fpr[15]) },
> + { "f16", offsetof(CPUPPCState, fpr[16]) },
> + { "f17", offsetof(CPUPPCState, fpr[17]) },
> + { "f18", offsetof(CPUPPCState, fpr[18]) },
> + { "f19", offsetof(CPUPPCState, fpr[19]) },
> + { "f20", offsetof(CPUPPCState, fpr[20]) },
> + { "f21", offsetof(CPUPPCState, fpr[21]) },
> + { "f22", offsetof(CPUPPCState, fpr[22]) },
> + { "f23", offsetof(CPUPPCState, fpr[23]) },
> + { "f24", offsetof(CPUPPCState, fpr[24]) },
> + { "f25", offsetof(CPUPPCState, fpr[25]) },
> + { "f26", offsetof(CPUPPCState, fpr[26]) },
> + { "f27", offsetof(CPUPPCState, fpr[27]) },
> + { "f28", offsetof(CPUPPCState, fpr[28]) },
> + { "f29", offsetof(CPUPPCState, fpr[29]) },
> + { "f30", offsetof(CPUPPCState, fpr[30]) },
> + { "f31", offsetof(CPUPPCState, fpr[31]) },
> + { "fpscr", offsetof(CPUPPCState, fpscr) },
> /* Next instruction pointer */
> - { "nip|pc", offsetof(CPUState, nip) },
> - { "lr", offsetof(CPUState, lr) },
> - { "ctr", offsetof(CPUState, ctr) },
> + { "nip|pc", offsetof(CPUPPCState, nip) },
> + { "lr", offsetof(CPUPPCState, lr) },
> + { "ctr", offsetof(CPUPPCState, ctr) },
> { "decr", 0,&monitor_get_decr, },
> { "ccr", 0,&monitor_get_ccr, },
> /* Machine state register */
> @@ -2808,105 +2808,105 @@ static const MonitorDef monitor_defs[] = {
> { "tbl", 0,&monitor_get_tbl, },
> #if defined(TARGET_PPC64)
> /* Address space register */
> - { "asr", offsetof(CPUState, asr) },
> + { "asr", offsetof(CPUPPCState, asr) },
> #endif
> /* Segment registers */
> - { "sdr1", offsetof(CPUState, spr[SPR_SDR1]) },
> - { "sr0", offsetof(CPUState, sr[0]) },
> - { "sr1", offsetof(CPUState, sr[1]) },
> - { "sr2", offsetof(CPUState, sr[2]) },
> - { "sr3", offsetof(CPUState, sr[3]) },
> - { "sr4", offsetof(CPUState, sr[4]) },
> - { "sr5", offsetof(CPUState, sr[5]) },
> - { "sr6", offsetof(CPUState, sr[6]) },
> - { "sr7", offsetof(CPUState, sr[7]) },
> - { "sr8", offsetof(CPUState, sr[8]) },
> - { "sr9", offsetof(CPUState, sr[9]) },
> - { "sr10", offsetof(CPUState, sr[10]) },
> - { "sr11", offsetof(CPUState, sr[11]) },
> - { "sr12", offsetof(CPUState, sr[12]) },
> - { "sr13", offsetof(CPUState, sr[13]) },
> - { "sr14", offsetof(CPUState, sr[14]) },
> - { "sr15", offsetof(CPUState, sr[15]) },
> + { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
> + { "sr0", offsetof(CPUPPCState, sr[0]) },
> + { "sr1", offsetof(CPUPPCState, sr[1]) },
> + { "sr2", offsetof(CPUPPCState, sr[2]) },
> + { "sr3", offsetof(CPUPPCState, sr[3]) },
> + { "sr4", offsetof(CPUPPCState, sr[4]) },
> + { "sr5", offsetof(CPUPPCState, sr[5]) },
> + { "sr6", offsetof(CPUPPCState, sr[6]) },
> + { "sr7", offsetof(CPUPPCState, sr[7]) },
> + { "sr8", offsetof(CPUPPCState, sr[8]) },
> + { "sr9", offsetof(CPUPPCState, sr[9]) },
> + { "sr10", offsetof(CPUPPCState, sr[10]) },
> + { "sr11", offsetof(CPUPPCState, sr[11]) },
> + { "sr12", offsetof(CPUPPCState, sr[12]) },
> + { "sr13", offsetof(CPUPPCState, sr[13]) },
> + { "sr14", offsetof(CPUPPCState, sr[14]) },
> + { "sr15", offsetof(CPUPPCState, sr[15]) },
> /* Too lazy to put BATs... */
> - { "pvr", offsetof(CPUState, spr[SPR_PVR]) },
> + { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
>
> - { "srr0", offsetof(CPUState, spr[SPR_SRR0]) },
> - { "srr1", offsetof(CPUState, spr[SPR_SRR1]) },
> - { "sprg0", offsetof(CPUState, spr[SPR_SPRG0]) },
> - { "sprg1", offsetof(CPUState, spr[SPR_SPRG1]) },
> - { "sprg2", offsetof(CPUState, spr[SPR_SPRG2]) },
> - { "sprg3", offsetof(CPUState, spr[SPR_SPRG3]) },
> - { "sprg4", offsetof(CPUState, spr[SPR_SPRG4]) },
> - { "sprg5", offsetof(CPUState, spr[SPR_SPRG5]) },
> - { "sprg6", offsetof(CPUState, spr[SPR_SPRG6]) },
> - { "sprg7", offsetof(CPUState, spr[SPR_SPRG7]) },
> - { "pid", offsetof(CPUState, spr[SPR_BOOKE_PID]) },
> - { "csrr0", offsetof(CPUState, spr[SPR_BOOKE_CSRR0]) },
> - { "csrr1", offsetof(CPUState, spr[SPR_BOOKE_CSRR1]) },
> - { "esr", offsetof(CPUState, spr[SPR_BOOKE_ESR]) },
> - { "dear", offsetof(CPUState, spr[SPR_BOOKE_DEAR]) },
> - { "mcsr", offsetof(CPUState, spr[SPR_BOOKE_MCSR]) },
> - { "tsr", offsetof(CPUState, spr[SPR_BOOKE_TSR]) },
> - { "tcr", offsetof(CPUState, spr[SPR_BOOKE_TCR]) },
> - { "vrsave", offsetof(CPUState, spr[SPR_VRSAVE]) },
> - { "pir", offsetof(CPUState, spr[SPR_BOOKE_PIR]) },
> - { "mcsrr0", offsetof(CPUState, spr[SPR_BOOKE_MCSRR0]) },
> - { "mcsrr1", offsetof(CPUState, spr[SPR_BOOKE_MCSRR1]) },
> - { "decar", offsetof(CPUState, spr[SPR_BOOKE_DECAR]) },
> - { "ivpr", offsetof(CPUState, spr[SPR_BOOKE_IVPR]) },
> - { "epcr", offsetof(CPUState, spr[SPR_BOOKE_EPCR]) },
> - { "sprg8", offsetof(CPUState, spr[SPR_BOOKE_SPRG8]) },
> - { "ivor0", offsetof(CPUState, spr[SPR_BOOKE_IVOR0]) },
> - { "ivor1", offsetof(CPUState, spr[SPR_BOOKE_IVOR1]) },
> - { "ivor2", offsetof(CPUState, spr[SPR_BOOKE_IVOR2]) },
> - { "ivor3", offsetof(CPUState, spr[SPR_BOOKE_IVOR3]) },
> - { "ivor4", offsetof(CPUState, spr[SPR_BOOKE_IVOR4]) },
> - { "ivor5", offsetof(CPUState, spr[SPR_BOOKE_IVOR5]) },
> - { "ivor6", offsetof(CPUState, spr[SPR_BOOKE_IVOR6]) },
> - { "ivor7", offsetof(CPUState, spr[SPR_BOOKE_IVOR7]) },
> - { "ivor8", offsetof(CPUState, spr[SPR_BOOKE_IVOR8]) },
> - { "ivor9", offsetof(CPUState, spr[SPR_BOOKE_IVOR9]) },
> - { "ivor10", offsetof(CPUState, spr[SPR_BOOKE_IVOR10]) },
> - { "ivor11", offsetof(CPUState, spr[SPR_BOOKE_IVOR11]) },
> - { "ivor12", offsetof(CPUState, spr[SPR_BOOKE_IVOR12]) },
> - { "ivor13", offsetof(CPUState, spr[SPR_BOOKE_IVOR13]) },
> - { "ivor14", offsetof(CPUState, spr[SPR_BOOKE_IVOR14]) },
> - { "ivor15", offsetof(CPUState, spr[SPR_BOOKE_IVOR15]) },
> - { "ivor32", offsetof(CPUState, spr[SPR_BOOKE_IVOR32]) },
> - { "ivor33", offsetof(CPUState, spr[SPR_BOOKE_IVOR33]) },
> - { "ivor34", offsetof(CPUState, spr[SPR_BOOKE_IVOR34]) },
> - { "ivor35", offsetof(CPUState, spr[SPR_BOOKE_IVOR35]) },
> - { "ivor36", offsetof(CPUState, spr[SPR_BOOKE_IVOR36]) },
> - { "ivor37", offsetof(CPUState, spr[SPR_BOOKE_IVOR37]) },
> - { "mas0", offsetof(CPUState, spr[SPR_BOOKE_MAS0]) },
> - { "mas1", offsetof(CPUState, spr[SPR_BOOKE_MAS1]) },
> - { "mas2", offsetof(CPUState, spr[SPR_BOOKE_MAS2]) },
> - { "mas3", offsetof(CPUState, spr[SPR_BOOKE_MAS3]) },
> - { "mas4", offsetof(CPUState, spr[SPR_BOOKE_MAS4]) },
> - { "mas6", offsetof(CPUState, spr[SPR_BOOKE_MAS6]) },
> - { "mas7", offsetof(CPUState, spr[SPR_BOOKE_MAS7]) },
> - { "mmucfg", offsetof(CPUState, spr[SPR_MMUCFG]) },
> - { "tlb0cfg", offsetof(CPUState, spr[SPR_BOOKE_TLB0CFG]) },
> - { "tlb1cfg", offsetof(CPUState, spr[SPR_BOOKE_TLB1CFG]) },
> - { "epr", offsetof(CPUState, spr[SPR_BOOKE_EPR]) },
> - { "eplc", offsetof(CPUState, spr[SPR_BOOKE_EPLC]) },
> - { "epsc", offsetof(CPUState, spr[SPR_BOOKE_EPSC]) },
> - { "svr", offsetof(CPUState, spr[SPR_E500_SVR]) },
> - { "mcar", offsetof(CPUState, spr[SPR_Exxx_MCAR]) },
> - { "pid1", offsetof(CPUState, spr[SPR_BOOKE_PID1]) },
> - { "pid2", offsetof(CPUState, spr[SPR_BOOKE_PID2]) },
> - { "hid0", offsetof(CPUState, spr[SPR_HID0]) },
> + { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
> + { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
> + { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
> + { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
> + { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
> + { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
> + { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
> + { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
> + { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
> + { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
> + { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
> + { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
> + { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
> + { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
> + { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
> + { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
> + { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
> + { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
> + { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
> + { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
> + { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
> + { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
> + { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
> + { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
> + { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
> + { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
> + { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
> + { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
> + { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
> + { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
> + { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
> + { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
> + { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
> + { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
> + { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
> + { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
> + { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
> + { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
> + { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
> + { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
> + { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
> + { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
> + { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
> + { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
> + { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
> + { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
> + { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
> + { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
> + { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
> + { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
> + { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
> + { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
> + { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
> + { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
> + { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
> + { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
> + { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
> + { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
> + { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
> + { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
> + { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
> + { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
> + { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
> + { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
> + { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
> + { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
>
> #elif defined(TARGET_SPARC)
> - { "g0", offsetof(CPUState, gregs[0]) },
> - { "g1", offsetof(CPUState, gregs[1]) },
> - { "g2", offsetof(CPUState, gregs[2]) },
> - { "g3", offsetof(CPUState, gregs[3]) },
> - { "g4", offsetof(CPUState, gregs[4]) },
> - { "g5", offsetof(CPUState, gregs[5]) },
> - { "g6", offsetof(CPUState, gregs[6]) },
> - { "g7", offsetof(CPUState, gregs[7]) },
> + { "g0", offsetof(CPUSPARCState, gregs[0]) },
> + { "g1", offsetof(CPUSPARCState, gregs[1]) },
> + { "g2", offsetof(CPUSPARCState, gregs[2]) },
> + { "g3", offsetof(CPUSPARCState, gregs[3]) },
> + { "g4", offsetof(CPUSPARCState, gregs[4]) },
> + { "g5", offsetof(CPUSPARCState, gregs[5]) },
> + { "g6", offsetof(CPUSPARCState, gregs[6]) },
> + { "g7", offsetof(CPUSPARCState, gregs[7]) },
> { "o0", 0, monitor_get_reg },
> { "o1", 1, monitor_get_reg },
> { "o2", 2, monitor_get_reg },
> @@ -2931,72 +2931,72 @@ static const MonitorDef monitor_defs[] = {
> { "i5", 21, monitor_get_reg },
> { "i6", 22, monitor_get_reg },
> { "i7", 23, monitor_get_reg },
> - { "pc", offsetof(CPUState, pc) },
> - { "npc", offsetof(CPUState, npc) },
> - { "y", offsetof(CPUState, y) },
> + { "pc", offsetof(CPUSPARCState, pc) },
> + { "npc", offsetof(CPUSPARCState, npc) },
> + { "y", offsetof(CPUSPARCState, y) },
> #ifndef TARGET_SPARC64
> { "psr", 0,&monitor_get_psr, },
> - { "wim", offsetof(CPUState, wim) },
> + { "wim", offsetof(CPUSPARCState, wim) },
> #endif
> - { "tbr", offsetof(CPUState, tbr) },
> - { "fsr", offsetof(CPUState, fsr) },
> - { "f0", offsetof(CPUState, fpr[0].l.upper) },
> - { "f1", offsetof(CPUState, fpr[0].l.lower) },
> - { "f2", offsetof(CPUState, fpr[1].l.upper) },
> - { "f3", offsetof(CPUState, fpr[1].l.lower) },
> - { "f4", offsetof(CPUState, fpr[2].l.upper) },
> - { "f5", offsetof(CPUState, fpr[2].l.lower) },
> - { "f6", offsetof(CPUState, fpr[3].l.upper) },
> - { "f7", offsetof(CPUState, fpr[3].l.lower) },
> - { "f8", offsetof(CPUState, fpr[4].l.upper) },
> - { "f9", offsetof(CPUState, fpr[4].l.lower) },
> - { "f10", offsetof(CPUState, fpr[5].l.upper) },
> - { "f11", offsetof(CPUState, fpr[5].l.lower) },
> - { "f12", offsetof(CPUState, fpr[6].l.upper) },
> - { "f13", offsetof(CPUState, fpr[6].l.lower) },
> - { "f14", offsetof(CPUState, fpr[7].l.upper) },
> - { "f15", offsetof(CPUState, fpr[7].l.lower) },
> - { "f16", offsetof(CPUState, fpr[8].l.upper) },
> - { "f17", offsetof(CPUState, fpr[8].l.lower) },
> - { "f18", offsetof(CPUState, fpr[9].l.upper) },
> - { "f19", offsetof(CPUState, fpr[9].l.lower) },
> - { "f20", offsetof(CPUState, fpr[10].l.upper) },
> - { "f21", offsetof(CPUState, fpr[10].l.lower) },
> - { "f22", offsetof(CPUState, fpr[11].l.upper) },
> - { "f23", offsetof(CPUState, fpr[11].l.lower) },
> - { "f24", offsetof(CPUState, fpr[12].l.upper) },
> - { "f25", offsetof(CPUState, fpr[12].l.lower) },
> - { "f26", offsetof(CPUState, fpr[13].l.upper) },
> - { "f27", offsetof(CPUState, fpr[13].l.lower) },
> - { "f28", offsetof(CPUState, fpr[14].l.upper) },
> - { "f29", offsetof(CPUState, fpr[14].l.lower) },
> - { "f30", offsetof(CPUState, fpr[15].l.upper) },
> - { "f31", offsetof(CPUState, fpr[15].l.lower) },
> + { "tbr", offsetof(CPUSPARCState, tbr) },
> + { "fsr", offsetof(CPUSPARCState, fsr) },
> + { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
> + { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
> + { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
> + { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
> + { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
> + { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
> + { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
> + { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
> + { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
> + { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
> + { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
> + { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
> + { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
> + { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
> + { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
> + { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
> + { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
> + { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
> + { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
> + { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
> + { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
> + { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
> + { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
> + { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
> + { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
> + { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
> + { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
> + { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
> + { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
> + { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
> + { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
> + { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
> #ifdef TARGET_SPARC64
> - { "f32", offsetof(CPUState, fpr[16]) },
> - { "f34", offsetof(CPUState, fpr[17]) },
> - { "f36", offsetof(CPUState, fpr[18]) },
> - { "f38", offsetof(CPUState, fpr[19]) },
> - { "f40", offsetof(CPUState, fpr[20]) },
> - { "f42", offsetof(CPUState, fpr[21]) },
> - { "f44", offsetof(CPUState, fpr[22]) },
> - { "f46", offsetof(CPUState, fpr[23]) },
> - { "f48", offsetof(CPUState, fpr[24]) },
> - { "f50", offsetof(CPUState, fpr[25]) },
> - { "f52", offsetof(CPUState, fpr[26]) },
> - { "f54", offsetof(CPUState, fpr[27]) },
> - { "f56", offsetof(CPUState, fpr[28]) },
> - { "f58", offsetof(CPUState, fpr[29]) },
> - { "f60", offsetof(CPUState, fpr[30]) },
> - { "f62", offsetof(CPUState, fpr[31]) },
> - { "asi", offsetof(CPUState, asi) },
> - { "pstate", offsetof(CPUState, pstate) },
> - { "cansave", offsetof(CPUState, cansave) },
> - { "canrestore", offsetof(CPUState, canrestore) },
> - { "otherwin", offsetof(CPUState, otherwin) },
> - { "wstate", offsetof(CPUState, wstate) },
> - { "cleanwin", offsetof(CPUState, cleanwin) },
> - { "fprs", offsetof(CPUState, fprs) },
> + { "f32", offsetof(CPUSPARCState, fpr[16]) },
> + { "f34", offsetof(CPUSPARCState, fpr[17]) },
> + { "f36", offsetof(CPUSPARCState, fpr[18]) },
> + { "f38", offsetof(CPUSPARCState, fpr[19]) },
> + { "f40", offsetof(CPUSPARCState, fpr[20]) },
> + { "f42", offsetof(CPUSPARCState, fpr[21]) },
> + { "f44", offsetof(CPUSPARCState, fpr[22]) },
> + { "f46", offsetof(CPUSPARCState, fpr[23]) },
> + { "f48", offsetof(CPUSPARCState, fpr[24]) },
> + { "f50", offsetof(CPUSPARCState, fpr[25]) },
> + { "f52", offsetof(CPUSPARCState, fpr[26]) },
> + { "f54", offsetof(CPUSPARCState, fpr[27]) },
> + { "f56", offsetof(CPUSPARCState, fpr[28]) },
> + { "f58", offsetof(CPUSPARCState, fpr[29]) },
> + { "f60", offsetof(CPUSPARCState, fpr[30]) },
> + { "f62", offsetof(CPUSPARCState, fpr[31]) },
> + { "asi", offsetof(CPUSPARCState, asi) },
> + { "pstate", offsetof(CPUSPARCState, pstate) },
> + { "cansave", offsetof(CPUSPARCState, cansave) },
> + { "canrestore", offsetof(CPUSPARCState, canrestore) },
> + { "otherwin", offsetof(CPUSPARCState, otherwin) },
> + { "wstate", offsetof(CPUSPARCState, wstate) },
> + { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
> + { "fprs", offsetof(CPUSPARCState, fprs) },
> #endif
> #endif
> { NULL },
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
@ 2012-03-13 18:03 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:03 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> Signed-off-by: Andreas Färber<afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Regards,
Anthony Liguori
> ---
> gdbstub.c | 56 ++++++++++++++++++++++++++++----------------------------
> 1 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 7d470b6..054e16c 100644
> --- a/gdbstub.c
> +++ b/gdbstub.c
> @@ -533,7 +533,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
> #define IDX_XMM_REGS (IDX_FP_REGS + 16)
> #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
> {
> if (n< CPU_NB_REGS) {
> if (TARGET_LONG_BITS == 64&& env->hflags& HF_CS64_MASK) {
> @@ -590,7 +590,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
> +static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
> {
> uint16_t selector = ldl_p(mem_buf);
>
> @@ -615,7 +615,7 @@ static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
> return 4;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -703,7 +703,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> #define GDB_CORE_XML "power-core.xml"
> #endif
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
> {
> if (n< 32) {
> /* gprs */
> @@ -740,7 +740,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
> {
> if (n< 32) {
> /* gprs */
> @@ -801,7 +801,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> #define GET_REGA(val) GET_REGL(val)
> #endif
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
> {
> if (n< 8) {
> /* g0..g7 */
> @@ -860,7 +860,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
> {
> #if defined(TARGET_ABI32)
> abi_ulong tmp;
> @@ -944,7 +944,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> #define NUM_CORE_REGS 26
> #define GDB_CORE_XML "arm-core.xml"
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
> {
> if (n< 16) {
> /* Core integer register. */
> @@ -971,7 +971,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -1014,7 +1014,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
>
> #define GDB_CORE_XML "cf-core.xml"
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
> {
> if (n< 8) {
> /* D0-D7 */
> @@ -1033,7 +1033,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -1058,7 +1058,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
>
> #define NUM_CORE_REGS 73
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
> {
> if (n< 32) {
> GET_REGL(env->active_tc.gpr[n]);
> @@ -1104,7 +1104,7 @@ static unsigned int ieee_rm[] =
> #define RESTORE_ROUNDING_MODE \
> set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31& 3],&env->active_fpu.fp_status)
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
> {
> target_ulong tmp;
>
> @@ -1163,7 +1163,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
>
> #define NUM_CORE_REGS 59
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
> {
> if (n< 8) {
> if ((env->sr& (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
> @@ -1197,7 +1197,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -1244,7 +1244,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
>
> #define NUM_CORE_REGS (32 + 5)
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
> {
> if (n< 32) {
> GET_REG32(env->regs[n]);
> @@ -1254,7 +1254,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -1275,7 +1275,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> #define NUM_CORE_REGS 49
>
> static int
> -read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
> +read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
> {
> if (n< 15) {
> GET_REG32(env->regs[n]);
> @@ -1307,7 +1307,7 @@ read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
> {
> uint8_t srs;
>
> @@ -1337,7 +1337,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -1370,7 +1370,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
>
> #define NUM_CORE_REGS 67
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
> {
> uint64_t val;
> CPU_DoubleU d;
> @@ -1404,7 +1404,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> GET_REGL(val);
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
> {
> target_ulong tmp = ldtul_p(mem_buf);
> CPU_DoubleU d;
> @@ -1440,7 +1440,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
>
> #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
> {
> switch (n) {
> case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
> @@ -1464,7 +1464,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
> {
> target_ulong tmpl;
> uint32_t tmp32;
> @@ -1494,7 +1494,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> #include "hw/lm32_pic.h"
> #define NUM_CORE_REGS (32 + 7)
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
> {
> if (n< 32) {
> GET_REG32(env->regs[n]);
> @@ -1527,7 +1527,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> return 0;
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
>
> @@ -1573,7 +1573,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> #define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
> #define num_g_regs NUM_CORE_REGS
>
> -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
> {
> const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
>
> @@ -1610,7 +1610,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
> }
> }
>
> -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
> +static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
> {
> uint32_t tmp;
> const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
@ 2012-03-13 18:04 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:04 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> Signed-off-by: Andreas Färber<afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
For 5, 6, 7. I'd suggest folding this into a single patch.
Regards,
Anthony Liguori
> ---
> target-lm32/cpu.h | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index b6b6b4c..cc9b53b 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -28,6 +28,7 @@
> #include "qemu-common.h"
> #include "cpu-defs.h"
> struct CPULM32State;
> +typedef struct CPULM32State CPULM32State;
>
> #define TARGET_HAS_ICE 1
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-13 17:58 ` Andreas Färber
@ 2012-03-13 18:04 ` Eric Blake
2012-03-13 18:09 ` Eric Blake
2012-03-13 18:05 ` Paolo Bonzini
` (2 subsequent siblings)
3 siblings, 1 reply; 175+ messages in thread
From: Eric Blake @ 2012-03-13 18:04 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, i.mitsyanko, qemu-devel, Dmitry Solodkiy,
Anthony Liguori, Paul Brook
[-- Attachment #1: Type: text/plain, Size: 850 bytes --]
On 03/13/2012 11:58 AM, Andreas Färber wrote:
>>> +static void cpu_register(const ARMCPUInfo *info)
>>> +{
>>> + TypeInfo type = {
>>> + .name = info->name,
>>
>> Are non-initialized members guaranteed to be zero here?
>
> I thought so for the C99-style struct initialization... I never ran into
> crashes while testing. Do we need static to be safe?
Yes, C99 guarantees in 6.7.8 p19:
The initialization shall occur in initializer list order, each
initializer provided for a particular subobject overriding any
previously listed initializer for the same subobject; all subobjects
that are not initialized explicitly shall be initialized implicitly the
same as objects that have static storage duration.
--
Eric Blake eblake@redhat.com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 620 bytes --]
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-13 17:58 ` Andreas Färber
2012-03-13 18:04 ` Eric Blake
@ 2012-03-13 18:05 ` Paolo Bonzini
2012-03-13 18:12 ` Peter Maydell
2012-03-14 8:58 ` Igor Mitsyanko
3 siblings, 0 replies; 175+ messages in thread
From: Paolo Bonzini @ 2012-03-13 18:05 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, i.mitsyanko, qemu-devel, Dmitry Solodkiy,
Anthony Liguori, Paul Brook
Il 13/03/2012 18:58, Andreas Färber ha scritto:
>> > Are non-initialized members guaranteed to be zero here?
> I thought so for the C99-style struct initialization...
Yes.
> I never ran into
> crashes while testing. Do we need static to be safe?
No, I don't think so. It would raise other questions (static seems to
imply that the lifetime needs to extend across multiple calls, one could
wonder if it is safe to reuse TypeInfos that way; with stack-allocated
storage it's more obvious).
Paolo
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
@ 2012-03-13 18:05 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:05 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> This aids in refactoring CPUState by adopting the common naming scheme.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Regards,
Anthony Liguori
> ---
> target-unicore32/cpu.h | 8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index f725634..923db05 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -18,7 +18,7 @@
>
> #define ELF_MACHINE EM_UNICORE32
>
> -#define CPUState struct CPUState_UniCore32
> +#define CPUState struct CPUUniCore32State
>
> #include "config.h"
> #include "qemu-common.h"
> @@ -27,7 +27,7 @@
>
> #define NB_MMU_MODES 2
>
> -typedef struct CPUState_UniCore32 {
> +typedef struct CPUUniCore32State {
> /* Regs for current mode. */
> uint32_t regs[32];
> /* Frequently accessed ASR bits are stored separately for efficiently.
> @@ -71,7 +71,7 @@ typedef struct CPUState_UniCore32 {
> /* Internal CPU feature flags. */
> uint32_t features;
>
> -} CPUState_UniCore32;
> +} CPUUniCore32State;
>
> #define ASR_M (0x1f)
> #define ASR_MODE_USER (0x10)
> @@ -179,7 +179,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
>
> void uc32_translate_init(void);
> void do_interrupt(CPUState *);
> -void switch_mode(CPUState_UniCore32 *, int);
> +void switch_mode(CPUUniCore32State *, int);
>
> static inline bool cpu_has_work(CPUState *env)
> {
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
@ 2012-03-13 18:06 ` Andreas Färber
2012-03-13 18:11 ` Anthony Liguori
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-13 18:06 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
Am 10.03.2012 03:28, schrieb Andreas Färber:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
FWIW this commit message is missing the sed command used for automatic
conversion. It's in the cover letter, and I'll add it for v5/PULL if
there is consensus to go ahead with "CPUState".
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
@ 2012-03-13 18:07 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:07 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> pc.h and apic.h are not needed; apic.h would drag in x86 CPUState and
> is now included directly for TARGET_I386.
>
> isa.h is already #included from mc146818rtc.h.
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Regards,
Anthony Liguori
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> ---
> hw/mc146818rtc.c | 2 --
> 1 files changed, 0 insertions(+), 2 deletions(-)
>
> diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
> index 8b5cf8c..2b59c36 100644
> --- a/hw/mc146818rtc.c
> +++ b/hw/mc146818rtc.c
> @@ -24,8 +24,6 @@
> #include "hw.h"
> #include "qemu-timer.h"
> #include "sysemu.h"
> -#include "pc.h"
> -#include "isa.h"
> #include "mc146818rtc.h"
>
> #ifdef TARGET_I386
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
@ 2012-03-13 18:08 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:08 UTC (permalink / raw)
To: Andreas Färber; +Cc: Riku Voipio, qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> In target-specific code use CPU*State.
>
> While at it, fix indentation on those lines.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
Looks good, but make sure Riku agrees.
Regards,
Anthony Liguori
> ---
> linux-user/elfload.c | 24 +++---
> linux-user/m68k/syscall.h | 2 +-
> linux-user/main.c | 28 +++---
> linux-user/signal.c | 201 +++++++++++++++++++++++----------------------
> 4 files changed, 131 insertions(+), 124 deletions(-)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 2fd4a93..48e3232 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -157,7 +157,7 @@ typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
> *
> * See linux kernel: arch/x86/include/asm/elf.h
> */
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *env)
> {
> (*regs)[0] = env->regs[15];
> (*regs)[1] = env->regs[14];
> @@ -229,7 +229,7 @@ typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
> *
> * See linux kernel: arch/x86/include/asm/elf.h
> */
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *env)
> {
> (*regs)[0] = env->regs[R_EBX];
> (*regs)[1] = env->regs[R_ECX];
> @@ -288,7 +288,7 @@ static inline void init_thread(struct target_pt_regs *regs,
> #define ELF_NREG 18
> typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
>
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUARMState *env)
> {
> (*regs)[0] = tswapl(env->regs[0]);
> (*regs)[1] = tswapl(env->regs[1]);
> @@ -307,7 +307,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> (*regs)[14] = tswapl(env->regs[14]);
> (*regs)[15] = tswapl(env->regs[15]);
>
> - (*regs)[16] = tswapl(cpsr_read((CPUState *)env));
> + (*regs)[16] = tswapl(cpsr_read((CPUARMState *)env));
> (*regs)[17] = tswapl(env->regs[0]); /* XXX */
> }
>
> @@ -410,7 +410,7 @@ static inline void init_thread(struct target_pt_regs *regs,
> #define ELF_NREG 34
> typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
>
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUUniCore32State *env)
> {
> (*regs)[0] = env->regs[0];
> (*regs)[1] = env->regs[1];
> @@ -445,7 +445,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> (*regs)[30] = env->regs[30];
> (*regs)[31] = env->regs[31];
>
> - (*regs)[32] = cpu_asr_read((CPUState *)env);
> + (*regs)[32] = cpu_asr_read((CPUUniCore32State *)env);
> (*regs)[33] = env->regs[0]; /* XXX */
> }
>
> @@ -572,7 +572,7 @@ enum {
>
> static uint32_t get_elf_hwcap(void)
> {
> - CPUState *e = thread_env;
> + CPUPPCState *e = thread_env;
> uint32_t features = 0;
>
> /* We don't have to be terribly complete here; the high points are
> @@ -628,7 +628,7 @@ static inline void init_thread(struct target_pt_regs *_regs, struct image_info *
> #define ELF_NREG 48
> typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
>
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *env)
> {
> int i;
> target_ulong ccr = 0;
> @@ -697,7 +697,7 @@ enum {
> };
>
> /* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *env)
> {
> int i;
>
> @@ -749,7 +749,7 @@ static inline void init_thread(struct target_pt_regs *regs,
> typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
>
> /* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env)
> {
> int i, pos = 0;
>
> @@ -797,7 +797,7 @@ enum {
> };
>
> static inline void elf_core_copy_regs(target_elf_gregset_t *regs,
> - const CPUState *env)
> + const CPUSH4State *env)
> {
> int i;
>
> @@ -862,7 +862,7 @@ static inline void init_thread(struct target_pt_regs *regs,
> #define ELF_NREG 20
> typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
>
> -static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUState *env)
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUM68KState *env)
> {
> (*regs)[0] = tswapl(env->dregs[1]);
> (*regs)[1] = tswapl(env->dregs[2]);
> diff --git a/linux-user/m68k/syscall.h b/linux-user/m68k/syscall.h
> index 2fd85dd..2618793 100644
> --- a/linux-user/m68k/syscall.h
> +++ b/linux-user/m68k/syscall.h
> @@ -18,4 +18,4 @@ struct target_pt_regs {
>
> #define UNAME_MACHINE "m68k"
>
> -void do_m68k_simcall(CPUState *, int);
> +void do_m68k_simcall(CPUM68KState *, int);
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 01129f2..3b48882 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -71,7 +71,7 @@ void gemu_log(const char *fmt, ...)
> }
>
> #if defined(TARGET_I386)
> -int cpu_get_pic_interrupt(CPUState *env)
> +int cpu_get_pic_interrupt(CPUX86State *env)
> {
> return -1;
> }
> @@ -247,7 +247,7 @@ void cpu_list_unlock(void)
> /***********************************************************/
> /* CPUX86 core interface */
>
> -void cpu_smm_update(CPUState *env)
> +void cpu_smm_update(CPUX86State *env)
> {
> }
>
> @@ -889,7 +889,7 @@ void cpu_loop(CPUARMState *env)
>
> #ifdef TARGET_UNICORE32
>
> -void cpu_loop(CPUState *env)
> +void cpu_loop(CPUUniCore32State *env)
> {
> int trapnr;
> unsigned int n, insn;
> @@ -1226,36 +1226,36 @@ void cpu_loop (CPUSPARCState *env)
> #endif
>
> #ifdef TARGET_PPC
> -static inline uint64_t cpu_ppc_get_tb (CPUState *env)
> +static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
> {
> /* TO FIX */
> return 0;
> }
>
> -uint64_t cpu_ppc_load_tbl (CPUState *env)
> +uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
> {
> return cpu_ppc_get_tb(env);
> }
>
> -uint32_t cpu_ppc_load_tbu (CPUState *env)
> +uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
> {
> return cpu_ppc_get_tb(env)>> 32;
> }
>
> -uint64_t cpu_ppc_load_atbl (CPUState *env)
> +uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
> {
> return cpu_ppc_get_tb(env);
> }
>
> -uint32_t cpu_ppc_load_atbu (CPUState *env)
> +uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
> {
> return cpu_ppc_get_tb(env)>> 32;
> }
>
> -uint32_t cpu_ppc601_load_rtcu (CPUState *env)
> +uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
> __attribute__ (( alias ("cpu_ppc_load_tbu") ));
>
> -uint32_t cpu_ppc601_load_rtcl (CPUState *env)
> +uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
> {
> return cpu_ppc_load_tbl(env)& 0x3FFFFF80;
> }
> @@ -2276,7 +2276,7 @@ done_syscall:
> #endif
>
> #ifdef TARGET_SH4
> -void cpu_loop (CPUState *env)
> +void cpu_loop(CPUSH4State *env)
> {
> int trapnr, ret;
> target_siginfo_t info;
> @@ -2335,7 +2335,7 @@ void cpu_loop (CPUState *env)
> #endif
>
> #ifdef TARGET_CRIS
> -void cpu_loop (CPUState *env)
> +void cpu_loop(CPUCRISState *env)
> {
> int trapnr, ret;
> target_siginfo_t info;
> @@ -2393,7 +2393,7 @@ void cpu_loop (CPUState *env)
> #endif
>
> #ifdef TARGET_MICROBLAZE
> -void cpu_loop (CPUState *env)
> +void cpu_loop(CPUMBState *env)
> {
> int trapnr, ret;
> target_siginfo_t info;
> @@ -2630,7 +2630,7 @@ static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
> queue_signal(env, TARGET_SIGSEGV,&info);
> }
>
> -void cpu_loop (CPUState *env)
> +void cpu_loop(CPUAlphaState *env)
> {
> int trapnr;
> target_siginfo_t info;
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index cefd2ff..f44f78e 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -1205,14 +1205,14 @@ static const abi_ulong retcodes[4] = {
>
> #define __get_user_error(x,p,e) __get_user(x, p)
>
> -static inline int valid_user_regs(CPUState *regs)
> +static inline int valid_user_regs(CPUARMState *regs)
> {
> return 1;
> }
>
> static void
> setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
> - CPUState *env, abi_ulong mask)
> + CPUARMState *env, abi_ulong mask)
> {
> __put_user(env->regs[0],&sc->arm_r0);
> __put_user(env->regs[1],&sc->arm_r1);
> @@ -1241,7 +1241,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
> }
>
> static inline abi_ulong
> -get_sigframe(struct target_sigaction *ka, CPUState *regs, int framesize)
> +get_sigframe(struct target_sigaction *ka, CPUARMState *regs, int framesize)
> {
> unsigned long sp = regs->regs[13];
>
> @@ -1257,7 +1257,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, int framesize)
> }
>
> static int
> -setup_return(CPUState *env, struct target_sigaction *ka,
> +setup_return(CPUARMState *env, struct target_sigaction *ka,
> abi_ulong *rc, abi_ulong frame_addr, int usig, abi_ulong rc_addr)
> {
> abi_ulong handler = ka->_sa_handler;
> @@ -1295,7 +1295,7 @@ setup_return(CPUState *env, struct target_sigaction *ka,
> return 0;
> }
>
> -static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUState *env)
> +static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUARMState *env)
> {
> int i;
> struct target_vfp_sigframe *vfpframe;
> @@ -1312,7 +1312,8 @@ static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUState *env)
> return (abi_ulong*)(vfpframe+1);
> }
>
> -static abi_ulong *setup_sigframe_v2_iwmmxt(abi_ulong *regspace, CPUState *env)
> +static abi_ulong *setup_sigframe_v2_iwmmxt(abi_ulong *regspace,
> + CPUARMState *env)
> {
> int i;
> struct target_iwmmxt_sigframe *iwmmxtframe;
> @@ -1332,7 +1333,7 @@ static abi_ulong *setup_sigframe_v2_iwmmxt(abi_ulong *regspace, CPUState *env)
> }
>
> static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUARMState *env)
> {
> struct target_sigaltstack stack;
> int i;
> @@ -1367,7 +1368,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
>
> /* compare linux/arch/arm/kernel/signal.c:setup_frame() */
> static void setup_frame_v1(int usig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *regs)
> + target_sigset_t *set, CPUARMState *regs)
> {
> struct sigframe_v1 *frame;
> abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame));
> @@ -1391,7 +1392,7 @@ end:
> }
>
> static void setup_frame_v2(int usig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *regs)
> + target_sigset_t *set, CPUARMState *regs)
> {
> struct sigframe_v2 *frame;
> abi_ulong frame_addr = get_sigframe(ka, regs, sizeof(*frame));
> @@ -1408,7 +1409,7 @@ static void setup_frame_v2(int usig, struct target_sigaction *ka,
> }
>
> static void setup_frame(int usig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *regs)
> + target_sigset_t *set, CPUARMState *regs)
> {
> if (get_osversion()>= 0x020612) {
> setup_frame_v2(usig, ka, set, regs);
> @@ -1420,7 +1421,7 @@ static void setup_frame(int usig, struct target_sigaction *ka,
> /* compare linux/arch/arm/kernel/signal.c:setup_rt_frame() */
> static void setup_rt_frame_v1(int usig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUARMState *env)
> {
> struct rt_sigframe_v1 *frame;
> abi_ulong frame_addr = get_sigframe(ka, env, sizeof(*frame));
> @@ -1464,7 +1465,7 @@ end:
>
> static void setup_rt_frame_v2(int usig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUARMState *env)
> {
> struct rt_sigframe_v2 *frame;
> abi_ulong frame_addr = get_sigframe(ka, env, sizeof(*frame));
> @@ -1490,7 +1491,7 @@ static void setup_rt_frame_v2(int usig, struct target_sigaction *ka,
>
> static void setup_rt_frame(int usig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUARMState *env)
> {
> if (get_osversion()>= 0x020612) {
> setup_rt_frame_v2(usig, ka, info, set, env);
> @@ -1500,7 +1501,7 @@ static void setup_rt_frame(int usig, struct target_sigaction *ka,
> }
>
> static int
> -restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
> +restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
> {
> int err = 0;
> uint32_t cpsr;
> @@ -1531,7 +1532,7 @@ restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
> return err;
> }
>
> -static long do_sigreturn_v1(CPUState *env)
> +static long do_sigreturn_v1(CPUARMState *env)
> {
> abi_ulong frame_addr;
> struct sigframe_v1 *frame;
> @@ -1578,7 +1579,7 @@ badframe:
> return 0;
> }
>
> -static abi_ulong *restore_sigframe_v2_vfp(CPUState *env, abi_ulong *regspace)
> +static abi_ulong *restore_sigframe_v2_vfp(CPUARMState *env, abi_ulong *regspace)
> {
> int i;
> abi_ulong magic, sz;
> @@ -1608,7 +1609,8 @@ static abi_ulong *restore_sigframe_v2_vfp(CPUState *env, abi_ulong *regspace)
> return (abi_ulong*)(vfpframe + 1);
> }
>
> -static abi_ulong *restore_sigframe_v2_iwmmxt(CPUState *env, abi_ulong *regspace)
> +static abi_ulong *restore_sigframe_v2_iwmmxt(CPUARMState *env,
> + abi_ulong *regspace)
> {
> int i;
> abi_ulong magic, sz;
> @@ -1632,7 +1634,7 @@ static abi_ulong *restore_sigframe_v2_iwmmxt(CPUState *env, abi_ulong *regspace)
> return (abi_ulong*)(iwmmxtframe + 1);
> }
>
> -static int do_sigframe_return_v2(CPUState *env, target_ulong frame_addr,
> +static int do_sigframe_return_v2(CPUARMState *env, target_ulong frame_addr,
> struct target_ucontext_v2 *uc)
> {
> sigset_t host_set;
> @@ -1671,7 +1673,7 @@ static int do_sigframe_return_v2(CPUState *env, target_ulong frame_addr,
> return 0;
> }
>
> -static long do_sigreturn_v2(CPUState *env)
> +static long do_sigreturn_v2(CPUARMState *env)
> {
> abi_ulong frame_addr;
> struct sigframe_v2 *frame;
> @@ -1700,7 +1702,7 @@ badframe:
> return 0;
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUARMState *env)
> {
> if (get_osversion()>= 0x020612) {
> return do_sigreturn_v2(env);
> @@ -1709,7 +1711,7 @@ long do_sigreturn(CPUState *env)
> }
> }
>
> -static long do_rt_sigreturn_v1(CPUState *env)
> +static long do_rt_sigreturn_v1(CPUARMState *env)
> {
> abi_ulong frame_addr;
> struct rt_sigframe_v1 *frame;
> @@ -1750,7 +1752,7 @@ badframe:
> return 0;
> }
>
> -static long do_rt_sigreturn_v2(CPUState *env)
> +static long do_rt_sigreturn_v2(CPUARMState *env)
> {
> abi_ulong frame_addr;
> struct rt_sigframe_v2 *frame;
> @@ -1779,7 +1781,7 @@ badframe:
> return 0;
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUARMState *env)
> {
> if (get_osversion()>= 0x020612) {
> return do_rt_sigreturn_v2(env);
> @@ -1888,7 +1890,8 @@ struct target_rt_signal_frame {
> #define UREG_SP UREG_O6
>
> static inline abi_ulong get_sigframe(struct target_sigaction *sa,
> - CPUState *env, unsigned long framesize)
> + CPUSPARCState *env,
> + unsigned long framesize)
> {
> abi_ulong sp;
>
> @@ -1904,7 +1907,7 @@ static inline abi_ulong get_sigframe(struct target_sigaction *sa,
> }
>
> static int
> -setup___siginfo(__siginfo_t *si, CPUState *env, abi_ulong mask)
> +setup___siginfo(__siginfo_t *si, CPUSPARCState *env, abi_ulong mask)
> {
> int err = 0, i;
>
> @@ -1925,7 +1928,7 @@ setup___siginfo(__siginfo_t *si, CPUState *env, abi_ulong mask)
> #if 0
> static int
> setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
> - CPUState *env, unsigned long mask)
> + CPUSPARCState *env, unsigned long mask)
> {
> int err = 0;
>
> @@ -1943,7 +1946,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
> #define NF_ALIGNEDSZ (((sizeof(struct target_signal_frame) + 7)& (~7)))
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUSPARCState *env)
> {
> abi_ulong sf_addr;
> struct target_signal_frame *sf;
> @@ -2032,7 +2035,7 @@ sigsegv:
> force_sig(TARGET_SIGSEGV);
> }
> static inline int
> -restore_fpu_state(CPUState *env, qemu_siginfo_fpu_t *fpu)
> +restore_fpu_state(CPUSPARCState *env, qemu_siginfo_fpu_t *fpu)
> {
> int err;
> #if 0
> @@ -2073,12 +2076,12 @@ restore_fpu_state(CPUState *env, qemu_siginfo_fpu_t *fpu)
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUSPARCState *env)
> {
> fprintf(stderr, "setup_rt_frame: not implemented\n");
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUSPARCState *env)
> {
> abi_ulong sf_addr;
> struct target_signal_frame *sf;
> @@ -2151,7 +2154,7 @@ segv_and_exit:
> force_sig(TARGET_SIGSEGV);
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUSPARCState *env)
> {
> fprintf(stderr, "do_rt_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> @@ -2427,25 +2430,25 @@ void sparc64_get_context(CPUSPARCState *env)
> # warning signal handling not implemented
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMIPSState *env)
> {
> fprintf(stderr, "setup_frame: not implemented\n");
> }
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMIPSState *env)
> {
> fprintf(stderr, "setup_rt_frame: not implemented\n");
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUMIPSState *env)
> {
> fprintf(stderr, "do_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUMIPSState *env)
> {
> fprintf(stderr, "do_rt_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> @@ -2456,25 +2459,25 @@ long do_rt_sigreturn(CPUState *env)
> # warning signal handling not implemented
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMIPSState *env)
> {
> fprintf(stderr, "setup_frame: not implemented\n");
> }
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMIPSState *env)
> {
> fprintf(stderr, "setup_rt_frame: not implemented\n");
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUMIPSState *env)
> {
> fprintf(stderr, "do_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUMIPSState *env)
> {
> fprintf(stderr, "do_rt_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> @@ -2546,7 +2549,7 @@ static inline int install_sigtramp(unsigned int *tramp, unsigned int syscall)
> }
>
> static inline int
> -setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
> +setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
> {
> int err = 0;
>
> @@ -2621,7 +2624,7 @@ setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
> }
>
> static inline int
> -restore_sigcontext(CPUState *regs, struct target_sigcontext *sc)
> +restore_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
> {
> int err = 0;
>
> @@ -2692,7 +2695,7 @@ restore_sigcontext(CPUState *regs, struct target_sigcontext *sc)
> * Determine which stack to use..
> */
> static inline abi_ulong
> -get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
> +get_sigframe(struct target_sigaction *ka, CPUMIPSState *regs, size_t frame_size)
> {
> unsigned long sp;
>
> @@ -2716,7 +2719,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
>
> /* compare linux/arch/mips/kernel/signal.c:setup_frame() */
> static void setup_frame(int sig, struct target_sigaction * ka,
> - target_sigset_t *set, CPUState *regs)
> + target_sigset_t *set, CPUMIPSState *regs)
> {
> struct sigframe *frame;
> abi_ulong frame_addr;
> @@ -2764,7 +2767,7 @@ give_sigsegv:
> return;
> }
>
> -long do_sigreturn(CPUState *regs)
> +long do_sigreturn(CPUMIPSState *regs)
> {
> struct sigframe *frame;
> abi_ulong frame_addr;
> @@ -2815,7 +2818,7 @@ badframe:
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMIPSState *env)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr;
> @@ -2873,7 +2876,7 @@ give_sigsegv:
> return;
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUMIPSState *env)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr;
> @@ -2974,7 +2977,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
> }
>
> static int setup_sigcontext(struct target_sigcontext *sc,
> - CPUState *regs, unsigned long mask)
> + CPUSH4State *regs, unsigned long mask)
> {
> int err = 0;
> int i;
> @@ -3005,7 +3008,7 @@ static int setup_sigcontext(struct target_sigcontext *sc,
> return err;
> }
>
> -static int restore_sigcontext(CPUState *regs, struct target_sigcontext *sc,
> +static int restore_sigcontext(CPUSH4State *regs, struct target_sigcontext *sc,
> target_ulong *r0_p)
> {
> unsigned int err = 0;
> @@ -3037,7 +3040,7 @@ static int restore_sigcontext(CPUState *regs, struct target_sigcontext *sc,
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *regs)
> + target_sigset_t *set, CPUSH4State *regs)
> {
> struct target_sigframe *frame;
> abi_ulong frame_addr;
> @@ -3089,7 +3092,7 @@ give_sigsegv:
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *regs)
> + target_sigset_t *set, CPUSH4State *regs)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr;
> @@ -3150,7 +3153,7 @@ give_sigsegv:
> force_sig(TARGET_SIGSEGV);
> }
>
> -long do_sigreturn(CPUState *regs)
> +long do_sigreturn(CPUSH4State *regs)
> {
> struct target_sigframe *frame;
> abi_ulong frame_addr;
> @@ -3190,7 +3193,7 @@ badframe:
> return 0;
> }
>
> -long do_rt_sigreturn(CPUState *regs)
> +long do_rt_sigreturn(CPUSH4State *regs)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr;
> @@ -3257,7 +3260,7 @@ struct rt_signal_frame {
> uint32_t tramp[2];
> };
>
> -static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
> +static void setup_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
> {
> __put_user(env->regs[0],&sc->regs.r0);
> __put_user(env->regs[1],&sc->regs.r1);
> @@ -3294,7 +3297,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
> __put_user(env->sregs[SR_PC],&sc->regs.pc);
> }
>
> -static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
> +static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
> {
> __get_user(env->regs[0],&sc->regs.r0);
> __get_user(env->regs[1],&sc->regs.r1);
> @@ -3332,7 +3335,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
> }
>
> static abi_ulong get_sigframe(struct target_sigaction *ka,
> - CPUState *env, int frame_size)
> + CPUMBState *env, int frame_size)
> {
> abi_ulong sp = env->regs[1];
>
> @@ -3343,7 +3346,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMBState *env)
> {
> struct target_signal_frame *frame;
> abi_ulong frame_addr;
> @@ -3409,12 +3412,12 @@ static void setup_frame(int sig, struct target_sigaction *ka,
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUMBState *env)
> {
> fprintf(stderr, "Microblaze setup_rt_frame: not implemented\n");
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUMBState *env)
> {
> struct target_signal_frame *frame;
> abi_ulong frame_addr;
> @@ -3449,7 +3452,7 @@ long do_sigreturn(CPUState *env)
> force_sig(TARGET_SIGSEGV);
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUMBState *env)
> {
> fprintf(stderr, "Microblaze do_rt_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> @@ -3478,7 +3481,7 @@ struct rt_signal_frame {
> uint8_t retcode[8]; /* Trampoline code. */
> };
>
> -static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
> +static void setup_sigcontext(struct target_sigcontext *sc, CPUCRISState *env)
> {
> __put_user(env->regs[0],&sc->regs.r0);
> __put_user(env->regs[1],&sc->regs.r1);
> @@ -3501,7 +3504,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUState *env)
> __put_user(env->pc,&sc->regs.erp);
> }
>
> -static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
> +static void restore_sigcontext(struct target_sigcontext *sc, CPUCRISState *env)
> {
> __get_user(env->regs[0],&sc->regs.r0);
> __get_user(env->regs[1],&sc->regs.r1);
> @@ -3524,7 +3527,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUState *env)
> __get_user(env->pc,&sc->regs.erp);
> }
>
> -static abi_ulong get_sigframe(CPUState *env, int framesize)
> +static abi_ulong get_sigframe(CPUCRISState *env, int framesize)
> {
> abi_ulong sp;
> /* Align the stack downwards to 4. */
> @@ -3533,7 +3536,7 @@ static abi_ulong get_sigframe(CPUState *env, int framesize)
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUCRISState *env)
> {
> struct target_signal_frame *frame;
> abi_ulong frame_addr;
> @@ -3584,12 +3587,12 @@ static void setup_frame(int sig, struct target_sigaction *ka,
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUCRISState *env)
> {
> fprintf(stderr, "CRIS setup_rt_frame: not implemented\n");
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUCRISState *env)
> {
> struct target_signal_frame *frame;
> abi_ulong frame_addr;
> @@ -3620,7 +3623,7 @@ long do_sigreturn(CPUState *env)
> force_sig(TARGET_SIGSEGV);
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUCRISState *env)
> {
> fprintf(stderr, "CRIS do_rt_sigreturn: not implemented\n");
> return -TARGET_ENOSYS;
> @@ -3687,7 +3690,7 @@ typedef struct {
> } rt_sigframe;
>
> static inline abi_ulong
> -get_sigframe(struct target_sigaction *ka, CPUState *env, size_t frame_size)
> +get_sigframe(struct target_sigaction *ka, CPUS390XState *env, size_t frame_size)
> {
> abi_ulong sp;
>
> @@ -3712,7 +3715,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *env, size_t frame_size)
> return (sp - frame_size)& -8ul;
> }
>
> -static void save_sigregs(CPUState *env, target_sigregs *sregs)
> +static void save_sigregs(CPUS390XState *env, target_sigregs *sregs)
> {
> int i;
> //save_access_regs(current->thread.acrs); FIXME
> @@ -3738,7 +3741,7 @@ static void save_sigregs(CPUState *env, target_sigregs *sregs)
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUS390XState *env)
> {
> sigframe *frame;
> abi_ulong frame_addr;
> @@ -3805,7 +3808,7 @@ give_sigsegv:
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUS390XState *env)
> {
> int i;
> rt_sigframe *frame;
> @@ -3869,7 +3872,7 @@ give_sigsegv:
> }
>
> static int
> -restore_sigregs(CPUState *env, target_sigregs *sc)
> +restore_sigregs(CPUS390XState *env, target_sigregs *sc)
> {
> int err = 0;
> int i;
> @@ -3895,7 +3898,7 @@ restore_sigregs(CPUState *env, target_sigregs *sc)
> return err;
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUS390XState *env)
> {
> sigframe *frame;
> abi_ulong frame_addr = env->regs[15];
> @@ -3927,7 +3930,7 @@ badframe:
> return 0;
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUS390XState *env)
> {
> rt_sigframe *frame;
> abi_ulong frame_addr = env->regs[15];
> @@ -4107,7 +4110,7 @@ struct target_rt_sigframe {
>
> /* See arch/powerpc/kernel/signal.c. */
> static target_ulong get_sigframe(struct target_sigaction *ka,
> - CPUState *env,
> + CPUPPCState *env,
> int frame_size)
> {
> target_ulong oldsp, newsp;
> @@ -4125,7 +4128,7 @@ static target_ulong get_sigframe(struct target_sigaction *ka,
> return newsp;
> }
>
> -static int save_user_regs(CPUState *env, struct target_mcontext *frame,
> +static int save_user_regs(CPUPPCState *env, struct target_mcontext *frame,
> int sigret)
> {
> target_ulong msr = env->msr;
> @@ -4221,7 +4224,7 @@ static int save_user_regs(CPUState *env, struct target_mcontext *frame,
> return 0;
> }
>
> -static int restore_user_regs(CPUState *env,
> +static int restore_user_regs(CPUPPCState *env,
> struct target_mcontext *frame, int sig)
> {
> target_ulong save_r2 = 0;
> @@ -4320,7 +4323,7 @@ static int restore_user_regs(CPUState *env,
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUPPCState *env)
> {
> struct target_sigframe *frame;
> struct target_sigcontext *sc;
> @@ -4382,7 +4385,7 @@ sigsegv:
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUPPCState *env)
> {
> struct target_rt_sigframe *rt_sf;
> struct target_mcontext *frame;
> @@ -4450,7 +4453,7 @@ sigsegv:
>
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUPPCState *env)
> {
> struct target_sigcontext *sc = NULL;
> struct target_mcontext *sr = NULL;
> @@ -4493,7 +4496,7 @@ sigsegv:
> }
>
> /* See arch/powerpc/kernel/signal_32.c. */
> -static int do_setcontext(struct target_ucontext *ucp, CPUState *env, int sig)
> +static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
> {
> struct target_mcontext *mcp;
> target_ulong mcp_addr;
> @@ -4528,7 +4531,7 @@ sigsegv:
> #endif
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUPPCState *env)
> {
> struct target_rt_sigframe *rt_sf = NULL;
> target_ulong rt_sf_addr;
> @@ -4617,7 +4620,8 @@ struct target_rt_sigframe
> };
>
> static int
> -setup_sigcontext(struct target_sigcontext *sc, CPUState *env, abi_ulong mask)
> +setup_sigcontext(struct target_sigcontext *sc, CPUM68KState *env,
> + abi_ulong mask)
> {
> int err = 0;
>
> @@ -4634,7 +4638,7 @@ setup_sigcontext(struct target_sigcontext *sc, CPUState *env, abi_ulong mask)
> }
>
> static int
> -restore_sigcontext(CPUState *env, struct target_sigcontext *sc, int *pd0)
> +restore_sigcontext(CPUM68KState *env, struct target_sigcontext *sc, int *pd0)
> {
> int err = 0;
> int temp;
> @@ -4656,7 +4660,8 @@ restore_sigcontext(CPUState *env, struct target_sigcontext *sc, int *pd0)
> * Determine which stack to use..
> */
> static inline abi_ulong
> -get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
> +get_sigframe(struct target_sigaction *ka, CPUM68KState *regs,
> + size_t frame_size)
> {
> unsigned long sp;
>
> @@ -4671,7 +4676,7 @@ get_sigframe(struct target_sigaction *ka, CPUState *regs, size_t frame_size)
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUM68KState *env)
> {
> struct target_sigframe *frame;
> abi_ulong frame_addr;
> @@ -4725,7 +4730,7 @@ give_sigsegv:
> }
>
> static inline int target_rt_setup_ucontext(struct target_ucontext *uc,
> - CPUState *env)
> + CPUM68KState *env)
> {
> target_greg_t *gregs = uc->tuc_mcontext.gregs;
> int err;
> @@ -4753,7 +4758,7 @@ static inline int target_rt_setup_ucontext(struct target_ucontext *uc,
> return err;
> }
>
> -static inline int target_rt_restore_ucontext(CPUState *env,
> +static inline int target_rt_restore_ucontext(CPUM68KState *env,
> struct target_ucontext *uc,
> int *pd0)
> {
> @@ -4795,7 +4800,7 @@ badframe:
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUM68KState *env)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr;
> @@ -4866,7 +4871,7 @@ give_sigsegv:
> force_sig(TARGET_SIGSEGV);
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUM68KState *env)
> {
> struct target_sigframe *frame;
> abi_ulong frame_addr = env->aregs[7] - 4;
> @@ -4904,7 +4909,7 @@ badframe:
> return 0;
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUM68KState *env)
> {
> struct target_rt_sigframe *frame;
> abi_ulong frame_addr = env->aregs[7] - 4;
> @@ -4985,7 +4990,7 @@ struct target_rt_sigframe {
> #define INSN_LDI_R0 0x201f0000
> #define INSN_CALLSYS 0x00000083
>
> -static int setup_sigcontext(struct target_sigcontext *sc, CPUState *env,
> +static int setup_sigcontext(struct target_sigcontext *sc, CPUAlphaState *env,
> abi_ulong frame_addr, target_sigset_t *set)
> {
> int i, err = 0;
> @@ -5013,7 +5018,8 @@ static int setup_sigcontext(struct target_sigcontext *sc, CPUState *env,
> return err;
> }
>
> -static int restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
> +static int restore_sigcontext(CPUAlphaState *env,
> + struct target_sigcontext *sc)
> {
> uint64_t fpcr;
> int i, err = 0;
> @@ -5034,7 +5040,8 @@ static int restore_sigcontext(CPUState *env, struct target_sigcontext *sc)
> }
>
> static inline abi_ulong get_sigframe(struct target_sigaction *sa,
> - CPUState *env, unsigned long framesize)
> + CPUAlphaState *env,
> + unsigned long framesize)
> {
> abi_ulong sp = env->ir[IR_SP];
>
> @@ -5046,7 +5053,7 @@ static inline abi_ulong get_sigframe(struct target_sigaction *sa,
> }
>
> static void setup_frame(int sig, struct target_sigaction *ka,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUAlphaState *env)
> {
> abi_ulong frame_addr, r26;
> struct target_sigframe *frame;
> @@ -5090,7 +5097,7 @@ static void setup_frame(int sig, struct target_sigaction *ka,
>
> static void setup_rt_frame(int sig, struct target_sigaction *ka,
> target_siginfo_t *info,
> - target_sigset_t *set, CPUState *env)
> + target_sigset_t *set, CPUAlphaState *env)
> {
> abi_ulong frame_addr, r26;
> struct target_rt_sigframe *frame;
> @@ -5144,7 +5151,7 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
> env->ir[IR_SP] = frame_addr;
> }
>
> -long do_sigreturn(CPUState *env)
> +long do_sigreturn(CPUAlphaState *env)
> {
> struct target_sigcontext *sc;
> abi_ulong sc_addr = env->ir[IR_A0];
> @@ -5174,7 +5181,7 @@ long do_sigreturn(CPUState *env)
> force_sig(TARGET_SIGSEGV);
> }
>
> -long do_rt_sigreturn(CPUState *env)
> +long do_rt_sigreturn(CPUAlphaState *env)
> {
> abi_ulong frame_addr = env->ir[IR_A0];
> struct target_rt_sigframe *frame;
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-13 18:04 ` Eric Blake
@ 2012-03-13 18:09 ` Eric Blake
0 siblings, 0 replies; 175+ messages in thread
From: Eric Blake @ 2012-03-13 18:09 UTC (permalink / raw)
To: Eric Blake
Cc: Peter Maydell, i.mitsyanko, qemu-devel, Dmitry Solodkiy,
Anthony Liguori, Andreas Färber, Paul Brook
[-- Attachment #1: Type: text/plain, Size: 792 bytes --]
On 03/13/2012 12:04 PM, Eric Blake wrote:
> On 03/13/2012 11:58 AM, Andreas Färber wrote:
>
>>>> +static void cpu_register(const ARMCPUInfo *info)
>>>> +{
>>>> + TypeInfo type = {
>>>> + .name = info->name,
>
>>>
>>> Are non-initialized members guaranteed to be zero here?
>>
>> I thought so for the C99-style struct initialization... I never ran into
>> crashes while testing. Do we need static to be safe?
>
> Yes, C99 guarantees in 6.7.8 p19:
Apologies for my ambiguous answer. Yes, C99 guarantees that
non-mentioned members are 0-initialized if you have at least one
explicit initialization. Therefore, no, you don't need static to be safe.
--
Eric Blake eblake@redhat.com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 620 bytes --]
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
@ 2012-03-13 18:10 ` Anthony Liguori
2012-03-14 20:50 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:10 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/09/2012 08:27 PM, Andreas Färber wrote:
> Scripted conversion:
> sed -i "s/CPUState/CPUAlphaState/g" target-alpha/*.[hc]
> sed -i "s/#define CPUAlphaState/#define CPUState/" target-alpha/cpu.h
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
For 13-42.
I reviewed the target-i386 changes pretty closely and I'm confident that if the
conversion went bad, we'll pick it up very quickly via a build or smoke test.
Regards,
Anthony Liguori
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> ---
> target-alpha/cpu.h | 24 ++++++++++----------
> target-alpha/helper.c | 18 +++++++-------
> target-alpha/machine.c | 44 ++++++++++++++++++------------------
> target-alpha/op_helper.c | 6 ++--
> target-alpha/translate.c | 56 +++++++++++++++++++++++-----------------------
> 5 files changed, 74 insertions(+), 74 deletions(-)
>
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index 5cd6fd8..ecc2a35 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -375,7 +375,7 @@ enum {
> PS_USER_MODE = 8
> };
>
> -static inline int cpu_mmu_index(CPUState *env)
> +static inline int cpu_mmu_index(CPUAlphaState *env)
> {
> if (env->pal_mode) {
> return MMU_KERNEL_IDX;
> @@ -430,16 +430,16 @@ int cpu_alpha_exec(CPUAlphaState *s);
> is returned if the signal was handled by the virtual CPU. */
> int cpu_alpha_signal_handler(int host_signum, void *pinfo,
> void *puc);
> -int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
> +int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
> int mmu_idx);
> #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
> -void do_interrupt (CPUState *env);
> +void do_interrupt (CPUAlphaState *env);
>
> -uint64_t cpu_alpha_load_fpcr (CPUState *env);
> -void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
> +uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
> +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
> #ifndef CONFIG_USER_ONLY
> -void swap_shadow_regs(CPUState *env);
> -QEMU_NORETURN void cpu_unassigned_access(CPUState *env1,
> +void swap_shadow_regs(CPUAlphaState *env);
> +QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
> target_phys_addr_t addr, int is_write,
> int is_exec, int unused, int size);
> #endif
> @@ -459,7 +459,7 @@ enum {
> TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH<< TB_FLAGS_AMASK_SHIFT,
> };
>
> -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
> +static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
> target_ulong *cs_base, int *pflags)
> {
> int flags = 0;
> @@ -481,7 +481,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
> }
>
> #if defined(CONFIG_USER_ONLY)
> -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
> +static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
> {
> if (newsp) {
> env->ir[IR_SP] = newsp;
> @@ -490,13 +490,13 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
> env->ir[IR_A3] = 0;
> }
>
> -static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
> +static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
> {
> env->unique = newtls;
> }
> #endif
>
> -static inline bool cpu_has_work(CPUState *env)
> +static inline bool cpu_has_work(CPUAlphaState *env)
> {
> /* Here we are checking to see if the CPU should wake up from HALT.
> We will have gotten into this state only for WTINT from PALmode. */
> @@ -513,7 +513,7 @@ static inline bool cpu_has_work(CPUState *env)
>
> #include "exec-all.h"
>
> -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
> +static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb)
> {
> env->pc = tb->pc;
> }
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index 06d2565..3f2e7c3 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -24,7 +24,7 @@
> #include "cpu.h"
> #include "softfloat.h"
>
> -uint64_t cpu_alpha_load_fpcr (CPUState *env)
> +uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
> {
> uint64_t r = 0;
> uint8_t t;
> @@ -94,7 +94,7 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env)
> return r;
> }
>
> -void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
> +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
> {
> uint8_t t;
>
> @@ -159,7 +159,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
> }
>
> #if defined(CONFIG_USER_ONLY)
> -int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
> +int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, target_ulong address, int rw,
> int mmu_idx)
> {
> env->exception_index = EXCP_MMFAULT;
> @@ -167,7 +167,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
> return 1;
> }
> #else
> -void swap_shadow_regs(CPUState *env)
> +void swap_shadow_regs(CPUAlphaState *env)
> {
> uint64_t i0, i1, i2, i3, i4, i5, i6, i7;
>
> @@ -200,7 +200,7 @@ void swap_shadow_regs(CPUState *env)
> }
>
> /* Returns the OSF/1 entMM failure indication, or -1 on success. */
> -static int get_physical_address(CPUState *env, target_ulong addr,
> +static int get_physical_address(CPUAlphaState *env, target_ulong addr,
> int prot_need, int mmu_idx,
> target_ulong *pphys, int *pprot)
> {
> @@ -306,7 +306,7 @@ static int get_physical_address(CPUState *env, target_ulong addr,
> return ret;
> }
>
> -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
> +target_phys_addr_t cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr)
> {
> target_ulong phys;
> int prot, fail;
> @@ -315,7 +315,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
> return (fail>= 0 ? -1 : phys);
> }
>
> -int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
> +int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw,
> int mmu_idx)
> {
> target_ulong phys;
> @@ -336,7 +336,7 @@ int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
> }
> #endif /* USER_ONLY */
>
> -void do_interrupt (CPUState *env)
> +void do_interrupt (CPUAlphaState *env)
> {
> int i = env->exception_index;
>
> @@ -453,7 +453,7 @@ void do_interrupt (CPUState *env)
> #endif /* !USER_ONLY */
> }
>
> -void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
> +void cpu_dump_state (CPUAlphaState *env, FILE *f, fprintf_function cpu_fprintf,
> int flags)
> {
> static const char *linux_reg_names[] = {
> diff --git a/target-alpha/machine.c b/target-alpha/machine.c
> index 76d70d9..1c9edd1 100644
> --- a/target-alpha/machine.c
> +++ b/target-alpha/machine.c
> @@ -21,8 +21,8 @@ static const VMStateInfo vmstate_fpcr = {
> };
>
> static VMStateField vmstate_cpu_fields[] = {
> - VMSTATE_UINTTL_ARRAY(ir, CPUState, 31),
> - VMSTATE_UINTTL_ARRAY(fir, CPUState, 31),
> + VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
> + VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
> /* Save the architecture value of the fpcr, not the internally
> expanded version. Since this architecture value does not
> exist in memory to be stored, this requires a but of hoop
> @@ -37,33 +37,33 @@ static VMStateField vmstate_cpu_fields[] = {
> .flags = VMS_SINGLE,
> .offset = 0
> },
> - VMSTATE_UINTTL(pc, CPUState),
> - VMSTATE_UINTTL(unique, CPUState),
> - VMSTATE_UINTTL(lock_addr, CPUState),
> - VMSTATE_UINTTL(lock_value, CPUState),
> + VMSTATE_UINTTL(pc, CPUAlphaState),
> + VMSTATE_UINTTL(unique, CPUAlphaState),
> + VMSTATE_UINTTL(lock_addr, CPUAlphaState),
> + VMSTATE_UINTTL(lock_value, CPUAlphaState),
> /* Note that lock_st_addr is not saved; it is a temporary
> used during the execution of the st[lq]_c insns. */
>
> - VMSTATE_UINT8(ps, CPUState),
> - VMSTATE_UINT8(intr_flag, CPUState),
> - VMSTATE_UINT8(pal_mode, CPUState),
> - VMSTATE_UINT8(fen, CPUState),
> + VMSTATE_UINT8(ps, CPUAlphaState),
> + VMSTATE_UINT8(intr_flag, CPUAlphaState),
> + VMSTATE_UINT8(pal_mode, CPUAlphaState),
> + VMSTATE_UINT8(fen, CPUAlphaState),
>
> - VMSTATE_UINT32(pcc_ofs, CPUState),
> + VMSTATE_UINT32(pcc_ofs, CPUAlphaState),
>
> - VMSTATE_UINTTL(trap_arg0, CPUState),
> - VMSTATE_UINTTL(trap_arg1, CPUState),
> - VMSTATE_UINTTL(trap_arg2, CPUState),
> + VMSTATE_UINTTL(trap_arg0, CPUAlphaState),
> + VMSTATE_UINTTL(trap_arg1, CPUAlphaState),
> + VMSTATE_UINTTL(trap_arg2, CPUAlphaState),
>
> - VMSTATE_UINTTL(exc_addr, CPUState),
> - VMSTATE_UINTTL(palbr, CPUState),
> - VMSTATE_UINTTL(ptbr, CPUState),
> - VMSTATE_UINTTL(vptptr, CPUState),
> - VMSTATE_UINTTL(sysval, CPUState),
> - VMSTATE_UINTTL(usp, CPUState),
> + VMSTATE_UINTTL(exc_addr, CPUAlphaState),
> + VMSTATE_UINTTL(palbr, CPUAlphaState),
> + VMSTATE_UINTTL(ptbr, CPUAlphaState),
> + VMSTATE_UINTTL(vptptr, CPUAlphaState),
> + VMSTATE_UINTTL(sysval, CPUAlphaState),
> + VMSTATE_UINTTL(usp, CPUAlphaState),
>
> - VMSTATE_UINTTL_ARRAY(shadow, CPUState, 8),
> - VMSTATE_UINTTL_ARRAY(scratch, CPUState, 24),
> + VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8),
> + VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24),
>
> VMSTATE_END_OF_LIST()
> };
> diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
> index cc102db..c77f009 100644
> --- a/target-alpha/op_helper.c
> +++ b/target-alpha/op_helper.c
> @@ -1329,7 +1329,7 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
> helper_excp(EXCP_UNALIGN, 0);
> }
>
> -void QEMU_NORETURN cpu_unassigned_access(CPUState *env1,
> +void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1,
> target_phys_addr_t addr, int is_write,
> int is_exec, int unused, int size)
> {
> @@ -1360,10 +1360,10 @@ void QEMU_NORETURN cpu_unassigned_access(CPUState *env1,
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUAlphaState *env1, target_ulong addr, int is_write, int mmu_idx,
> void *retaddr)
> {
> - CPUState *saved_env;
> + CPUAlphaState *saved_env;
> int ret;
>
> saved_env = env;
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 1d2142b..b51fe5c 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -105,35 +105,35 @@ static void alpha_translate_init(void)
> for (i = 0; i< 31; i++) {
> sprintf(p, "ir%d", i);
> cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, ir[i]), p);
> + offsetof(CPUAlphaState, ir[i]), p);
> p += (i< 10) ? 4 : 5;
>
> sprintf(p, "fir%d", i);
> cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, fir[i]), p);
> + offsetof(CPUAlphaState, fir[i]), p);
> p += (i< 10) ? 5 : 6;
> }
>
> cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, pc), "pc");
> + offsetof(CPUAlphaState, pc), "pc");
>
> cpu_lock_addr = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, lock_addr),
> + offsetof(CPUAlphaState, lock_addr),
> "lock_addr");
> cpu_lock_st_addr = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, lock_st_addr),
> + offsetof(CPUAlphaState, lock_st_addr),
> "lock_st_addr");
> cpu_lock_value = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, lock_value),
> + offsetof(CPUAlphaState, lock_value),
> "lock_value");
>
> cpu_unique = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, unique), "unique");
> + offsetof(CPUAlphaState, unique), "unique");
> #ifndef CONFIG_USER_ONLY
> cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, sysval), "sysval");
> + offsetof(CPUAlphaState, sysval), "sysval");
> cpu_usp = tcg_global_mem_new_i64(TCG_AREG0,
> - offsetof(CPUState, usp), "usp");
> + offsetof(CPUAlphaState, usp), "usp");
> #endif
>
> /* register helpers */
> @@ -611,7 +611,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
> tcg_gen_movi_i32(tmp, float_round_down);
> break;
> case QUAL_RM_D:
> - tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round));
> + tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_dyn_round));
> break;
> }
>
> @@ -620,7 +620,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11)
> With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
> sets the one field. */
> tcg_gen_st8_i32(tmp, cpu_env,
> - offsetof(CPUState, fp_status.float_rounding_mode));
> + offsetof(CPUAlphaState, fp_status.float_rounding_mode));
> #else
> gen_helper_setroundmode(tmp);
> #endif
> @@ -641,7 +641,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
> tmp = tcg_temp_new_i32();
> if (fn11) {
> /* Underflow is enabled, use the FPCR setting. */
> - tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_zero));
> + tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_flush_to_zero));
> } else {
> /* Underflow is disabled, force flush-to-zero. */
> tcg_gen_movi_i32(tmp, 1);
> @@ -649,7 +649,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11)
>
> #if defined(CONFIG_SOFTFLOAT_INLINE)
> tcg_gen_st8_i32(tmp, cpu_env,
> - offsetof(CPUState, fp_status.flush_to_zero));
> + offsetof(CPUAlphaState, fp_status.flush_to_zero));
> #else
> gen_helper_setflushzero(tmp);
> #endif
> @@ -677,7 +677,7 @@ static void gen_fp_exc_clear(void)
> #if defined(CONFIG_SOFTFLOAT_INLINE)
> TCGv_i32 zero = tcg_const_i32(0);
> tcg_gen_st8_i32(zero, cpu_env,
> - offsetof(CPUState, fp_status.float_exception_flags));
> + offsetof(CPUAlphaState, fp_status.float_exception_flags));
> tcg_temp_free_i32(zero);
> #else
> gen_helper_fp_exc_clear();
> @@ -696,7 +696,7 @@ static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore)
>
> #if defined(CONFIG_SOFTFLOAT_INLINE)
> tcg_gen_ld8u_i32(exc, cpu_env,
> - offsetof(CPUState, fp_status.float_exception_flags));
> + offsetof(CPUAlphaState, fp_status.float_exception_flags));
> #else
> gen_helper_fp_exc_get(exc);
> #endif
> @@ -1456,11 +1456,11 @@ static void gen_rx(int ra, int set)
> TCGv_i32 tmp;
>
> if (ra != 31) {
> - tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_flag));
> + tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUAlphaState, intr_flag));
> }
>
> tmp = tcg_const_i32(set);
> - tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag));
> + tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag));
> tcg_temp_free_i32(tmp);
> }
>
> @@ -1504,7 +1504,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
> break;
> case 0x2D:
> /* WRVPTPTR */
> - tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vptptr));
> + tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUAlphaState, vptptr));
> break;
> case 0x31:
> /* WRVAL */
> @@ -1521,19 +1521,19 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
>
> /* Note that we already know we're in kernel mode, so we know
> that PS only contains the 3 IPL bits. */
> - tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
> + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps));
>
> /* But make sure and store only the 3 IPL bits from the user. */
> tmp = tcg_temp_new();
> tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK);
> - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps));
> + tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps));
> tcg_temp_free(tmp);
> break;
> }
>
> case 0x36:
> /* RDPS */
> - tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
> + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps));
> break;
> case 0x38:
> /* WRUSP */
> @@ -1546,7 +1546,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
> case 0x3C:
> /* WHAMI */
> tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env,
> - offsetof(CPUState, cpu_index));
> + offsetof(CPUAlphaState, cpu_index));
> break;
>
> default:
> @@ -1654,7 +1654,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
> case 253:
> /* WAIT */
> tmp = tcg_const_i64(1);
> - tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted));
> + tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted));
> return gen_excp(ctx, EXCP_HLT, 0);
>
> case 252:
> @@ -3107,7 +3107,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
> address from EXC_ADDR. This turns out to be useful for our
> emulation PALcode, so continue to accept it. */
> TCGv tmp = tcg_temp_new();
> - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, exc_addr));
> + tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
> gen_helper_hw_ret(tmp);
> tcg_temp_free(tmp);
> } else {
> @@ -3325,7 +3325,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
> return ret;
> }
>
> -static inline void gen_intermediate_code_internal(CPUState *env,
> +static inline void gen_intermediate_code_internal(CPUAlphaState *env,
> TranslationBlock *tb,
> int search_pc)
> {
> @@ -3450,12 +3450,12 @@ static inline void gen_intermediate_code_internal(CPUState *env,
> #endif
> }
>
> -void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code (CPUAlphaState *env, struct TranslationBlock *tb)
> {
> gen_intermediate_code_internal(env, tb, 0);
> }
>
> -void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb)
> {
> gen_intermediate_code_internal(env, tb, 1);
> }
> @@ -3522,7 +3522,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
> return env;
> }
>
> -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
> +void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos)
> {
> env->pc = gen_opc_pc[pc_pos];
> }
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState
2012-03-13 18:06 ` Andreas Färber
@ 2012-03-13 18:11 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:11 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/13/2012 01:06 PM, Andreas Färber wrote:
> Am 10.03.2012 03:28, schrieb Andreas Färber:
>> Signed-off-by: Andreas Färber<afaerber@suse.de>
>> ---
>
> FWIW this commit message is missing the sed command used for automatic
> conversion. It's in the cover letter, and I'll add it for v5/PULL if
> there is consensus to go ahead with "CPUState".
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Even without the sed command, the conversion is straight forward.
Regards,
Anthony Liguori
>
> Andreas
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-13 17:58 ` Andreas Färber
2012-03-13 18:04 ` Eric Blake
2012-03-13 18:05 ` Paolo Bonzini
@ 2012-03-13 18:12 ` Peter Maydell
2012-03-14 8:58 ` Igor Mitsyanko
3 siblings, 0 replies; 175+ messages in thread
From: Peter Maydell @ 2012-03-13 18:12 UTC (permalink / raw)
To: Andreas Färber
Cc: Paul Brook, i.mitsyanko, qemu-devel, Anthony Liguori, Dmitry Solodkiy
On 13 March 2012 17:58, Andreas Färber <afaerber@suse.de> wrote:
> Have you thought about how to QOM'ify your boards? Mid-term I'd like to
> see an "exynos4210" object with the CPUs on it - maybe "cpu[0]" and
> "cpu[1]" child properties? Or "core[x]"? I had played with the sh7750 a
> bit on my branch but like the arm926 it's a single-core.
I think the exynos4210 object should have a single child object
cortex-a9 which in turn has child objects for core[0], core[1],
gic, scu, and the private timers and watchdogs.
In hardware the A9 is a single block which includes all the
cores and all the onboard peripherals; we should model it
the same way.
One step in this direction might be to disentangle the GIC
so that a9mpcore_priv and friends instantiate a GIC object
as a child object rather than subclassing the GIC. I think
now that Avi has made sub-page-size memory regions work
we can get the M profile NVIC code out of arm_gic.c and
have a standalone GIC object everybody instantiates.
-- PMM
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-13 12:20 ` Paolo Bonzini
2012-03-13 12:53 ` Andreas Färber
@ 2012-03-13 18:16 ` Anthony Liguori
1 sibling, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 18:16 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Igor Mammedov, Andreas Färber, qemu-devel
On 03/13/2012 07:20 AM, Paolo Bonzini wrote:
> Il 13/03/2012 13:13, Andreas Färber ha scritto:
>>> It will be easier to generalize later qdev code and not make special
>>> case when adding cpus.
>>
>> I never heard anyone wanting to generalize reset so far. I don't think
>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>
> I believe long term we want CPUs to become a DeviceState. For now, I
> think Andreas's prototype is fine. Methods should not take a superclass
> argument in general.
Agreed 100%. Methods should take whatever there class is as the argument.
>
>> This series is taking much too long to move forward (the QOM "steam"
>> seems to be gone?) and I'm worried that introducing much more basic
>> infrastructure will make review and applying even slower, cf.
>> object_class_foreach_ordered()/_get_list().
>
> Agreed, this series looks more or less good (and mostly mechanical
> anyway). Is it an RFC or what? :) I wonder if reviewers are put off by
> the subject.
44 patches is a bit scary. Had I realized it was so straight forward, I would
have reviewed it faster.
Anyway, I'm really happy with the whole series. If it weren't an RFC, I'd apply
it right now.
Andreas, please send out a new series that's !rfc or a pull request.
Really great work here, btw!
Regards,
Anthony Liguori
>
> Paolo
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
` (4 preceding siblings ...)
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
@ 2012-03-13 19:52 ` Anthony Liguori
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (2 subsequent siblings)
8 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-13 19:52 UTC (permalink / raw)
To: Andreas Färber; +Cc: lcapitulino, qemu-devel, Avi Kivity
On 03/04/2012 02:32 PM, Andreas Färber wrote:
> Hello Anthony,
>
> This series prepares for QOM'ification of CPUs and machines by rearranging
> constructor calls and Makefile dependency rules. I've separated it out due
> to complaints about patch series length for conversion of all targets.
>
> Patch 1 is a RESEND that avoids an abort after patch 2.
>
> Patch 2 rearranges module init for QOM in the system emulators, so that
> objects can really be used beyond devices.
>
> Patch 3 adds QOM support to the user emulators. As required by Anthony,
> they are now only built once.
>
> Available at:
> http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-user.v4
Applied. Thanks.
Regards,
Anthony Liguori
>
> Regards,
> Andreas
>
> Cc: Anthony Liguori<anthony@codemonkey.ws>
> Cc: Avi Kivity<avi@redhat.com>
>
> v3 -> v4:
> * Fix kvmclock abort due to too early kvm_enabled() check.
> * Introduce $(universal-obj-y) to build some objects only once.
> * Fix GPLv2 license link.
>
> v2 -> v3:
> * Rebased against qom-upstream.14 branch (and that against master).
>
> * Build common dependencies for user emulators in libuser/.
> * New dependencies needed after moving properties into object.c.
> * Add a qemu-user.c with stubs needed for successful linking.
>
> v1 -> v2:
>
> * Don't introduce extra early_init(), just relocate former MODULE_INIT_DEVICE.
> * Provide new type_init() macro to be used instead of device_init().
>
> Andreas Färber (3):
> kvmclock: Always register type
> qom: Register QOM infrastructure early
> qom: Add QOM support to user emulators
>
> Makefile | 6 +++---
> Makefile.objs | 23 ++++++++++++++++++-----
> Makefile.target | 4 ++++
> Makefile.user | 1 +
> bsd-user/main.c | 2 ++
> darwin-user/main.c | 3 +++
> hw/kvm/clock.c | 2 --
> linux-user/main.c | 2 ++
> qemu-user.c | 37 +++++++++++++++++++++++++++++++++++++
> vl.c | 4 ++--
> 10 files changed, 72 insertions(+), 12 deletions(-)
> create mode 100644 qemu-user.c
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
` (5 preceding siblings ...)
2012-03-13 19:52 ` [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Anthony Liguori
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
` (8 more replies)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
8 siblings, 9 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xue-tao, Andreas Färber, Anthony Liguori
Hello,
Based on qom-cpu v4 and object_class_get_list() v2, this series converts
the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to
target-arm and faces a similar issue of CPU-dependent init code, so let's
tackle it next.
Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS,
so that the target-unicore32 author gets notified of patches against his code.
Patch 2, based on feedback from Guan Xuetao, changes the license of most
target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a
qemu_malloc() -> g_malloc() substitution that he can't relicense at this time,
so leave that as GPLv2 and declare my following patches explicitly as GPLv2+.
Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h header
can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2 for now.
Patches 4-7 move code out of the uc32_cpu_init() function and into classes.
Regards,
Andreas
Cc: Guan Xue-tao <gxt@mprc.pku.edu.cn>
Cc: Anthony Liguori <anthony@codemonkey.ws>
Changes from former repo.or.cz qom-cpu[-wip] branch:
* Drop duplicate .instance_init.
Andreas Färber (7):
MAINTAINERS: Add entry for UniCore32
target-unicore32: Relicense to GPLv2+
target-unicore32: QOM'ify CPU
target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass
target-unicore32: Store cp0 c1_sys in UniCore32CPUClass
target-unicore32: Store feature flags in UniCore32CPUClass
target-unicore32: Store ucf64 fpscr in UniCore32CPUClass
MAINTAINERS | 5 ++
Makefile.target | 1 +
target-unicore32/cpu-qom.h | 81 ++++++++++++++++++++++++++++++
target-unicore32/cpu.c | 112 ++++++++++++++++++++++++++++++++++++++++++
target-unicore32/cpu.h | 10 +---
target-unicore32/helper.c | 62 ++---------------------
target-unicore32/helper.h | 5 +-
target-unicore32/op_helper.c | 5 +-
target-unicore32/translate.c | 5 +-
9 files changed, 213 insertions(+), 73 deletions(-)
create mode 100644 target-unicore32/cpu-qom.h
create mode 100644 target-unicore32/cpu.c
--
1.7.7
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 7:44 ` Guan Xuetao
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
` (7 subsequent siblings)
8 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
Consider it Odd Fixes for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
MAINTAINERS | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index f83d07c2..44ff923 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -112,6 +112,11 @@ M: Blue Swirl <blauwirbel@gmail.com>
S: Maintained
F: target-sparc/
+UniCore32
+M: Guan Xuetao <gxt@mprc.pku.edu.cn>
+S: Odd Fixes
+F: target-unicore32/
+
X86
M: qemu-devel@nongnu.org
S: Odd Fixes
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 7:53 ` Guan Xuetao
` (2 more replies)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Andreas Färber
` (6 subsequent siblings)
8 siblings, 3 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel
Cc: Blue Swirl, Stefan Weil, Guan Xuetao, Dor Laor, Andreas Färber
Adopt the license text suggested by Guan Xue-tao for all files except
helper.c, to which Anthony Liguori (IBM) contributed a g_malloc() call.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Dor Laor <dlaor@redhat.com>
---
target-unicore32/cpu.h | 5 ++---
target-unicore32/helper.h | 5 ++---
target-unicore32/op_helper.c | 5 ++---
target-unicore32/translate.c | 5 ++---
4 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index a3f8589..9cbee7a 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -3,9 +3,8 @@
*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This program is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
*/
#ifndef __CPU_UC32_H__
#define __CPU_UC32_H__
diff --git a/target-unicore32/helper.h b/target-unicore32/helper.h
index 615de2a..5aa7de8 100644
--- a/target-unicore32/helper.h
+++ b/target-unicore32/helper.h
@@ -1,9 +1,8 @@
/*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This program is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
*/
#include "def-helper.h"
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 638a020..9fc2b1f 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -3,9 +3,8 @@
*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This program is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
*/
#include "cpu.h"
#include "dyngen-exec.h"
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 3b3ba16..c01e636 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -3,9 +3,8 @@
*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This program is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
*/
#include <stdarg.h>
#include <stdlib.h>
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 7:56 ` Guan Xuetao
2012-03-14 1:39 ` [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass Andreas Färber
` (5 subsequent siblings)
8 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
Embed CPUUniCore32State into UniCore32CPU.
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-unicore32/cpu-qom.h | 72 ++++++++++++++++++++++++++++++++++
target-unicore32/cpu.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
target-unicore32/cpu.h | 1 +
target-unicore32/helper.c | 43 +++-----------------
5 files changed, 172 insertions(+), 36 deletions(-)
create mode 100644 target-unicore32/cpu-qom.h
create mode 100644 target-unicore32/cpu.c
diff --git a/Makefile.target b/Makefile.target
index cbf62c0..7033df0 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -94,6 +94,7 @@ libobj-y += cpu_init.o
endif
libobj-$(TARGET_SPARC) += int32_helper.o
libobj-$(TARGET_SPARC64) += int64_helper.o
+libobj-$(TARGET_UNICORE32) += cpu.o
libobj-y += disas.o
libobj-$(CONFIG_TCI_DIS) += tci-dis.o
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
new file mode 100644
index 0000000..afe47e8
--- /dev/null
+++ b/target-unicore32/cpu-qom.h
@@ -0,0 +1,72 @@
+/*
+ * QEMU UniCore32 CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+#ifndef QEMU_UC32_CPU_QOM_H
+#define QEMU_UC32_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_UNICORE32_CPU "unicore32-cpu"
+
+#define UNICORE32_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(UniCore32CPUClass, (klass), TYPE_UNICORE32_CPU)
+#define UNICORE32_CPU(obj) \
+ OBJECT_CHECK(UniCore32CPU, (obj), TYPE_UNICORE32_CPU)
+#define UNICORE32_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(UniCore32CPUClass, (obj), TYPE_UNICORE32_CPU)
+
+/**
+ * UniCore32CPUClass:
+ *
+ * A UniCore32 CPU model.
+ */
+typedef struct UniCore32CPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ struct {
+ uint32_t c0_cpuid;
+ } cp0;
+} UniCore32CPUClass;
+
+/**
+ * UniCore32CPU:
+ * @env: Legacy CPU state.
+ *
+ * A UniCore32 CPU.
+ */
+typedef struct UniCore32CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUUniCore32State env;
+} UniCore32CPU;
+
+static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
+{
+ return UNICORE32_CPU(container_of(env, UniCore32CPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
+
+
+#endif
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
new file mode 100644
index 0000000..b89a1c6
--- /dev/null
+++ b/target-unicore32/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * QEMU UniCore32 CPU
+ *
+ * Copyright (c) 2010-2011 GUAN Xue-tao
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+/* CPU models */
+
+typedef struct UniCore32CPUInfo {
+ const char *name;
+ uint32_t cp0_c0_cpuid;
+} UniCore32CPUInfo;
+
+static const UniCore32CPUInfo uc32_cpus[] = {
+ {
+ .name = "UniCore-II",
+ .cp0_c0_cpuid = 0x40010863,
+ },
+ {
+ .name = "any",
+ .cp0_c0_cpuid = 0xffffffff,
+ }
+};
+
+static void uc32_cpu_initfn(Object *obj)
+{
+ UniCore32CPU *cpu = UNICORE32_CPU(obj);
+ UniCore32CPUClass *klass = UNICORE32_CPU_GET_CLASS(cpu);
+ CPUUniCore32State *env = &cpu->env;
+
+ memset(env, 0, sizeof(CPUUniCore32State));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+ env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
+
+ env->uncached_asr = ASR_MODE_USER;
+ env->regs[31] = 0;
+
+ tlb_flush(env, 1);
+}
+
+static void uc32_cpu_class_init(ObjectClass *klass, void *data)
+{
+ UniCore32CPUClass *k = UNICORE32_CPU_CLASS(klass);
+ const UniCore32CPUInfo *info = data;
+
+ k->cp0.c0_cpuid = info->cp0_c0_cpuid;
+}
+
+static void uc32_register_cpu(const UniCore32CPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_UNICORE32_CPU,
+ .instance_size = sizeof(UniCore32CPU),
+ .class_size = sizeof(UniCore32CPUClass),
+ .class_init = uc32_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo uc32_cpu_info = {
+ .name = TYPE_UNICORE32_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(UniCore32CPU),
+ .instance_init = uc32_cpu_initfn,
+ .abstract = true,
+ .class_size = sizeof(UniCore32CPUClass),
+};
+
+static void uc32_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&uc32_cpu_info);
+ for (i = 0; i < ARRAY_SIZE(uc32_cpus); i++) {
+ uc32_register_cpu(&uc32_cpus[i]);
+ }
+}
+
+type_init(uc32_cpu_register_types)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 9cbee7a..1ddd272 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -158,6 +158,7 @@ static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls)
}
#include "cpu-all.h"
+#include "cpu-qom.h"
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 6af492d..44b7842 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -16,43 +16,20 @@ static inline void set_feature(CPUUniCore32State *env, int feature)
env->features |= feature;
}
-struct uc32_cpu_t {
- uint32_t id;
- const char *name;
-};
-
-static const struct uc32_cpu_t uc32_cpu_names[] = {
- { UC32_CPUID_UCV2, "UniCore-II"},
- { UC32_CPUID_ANY, "any"},
- { 0, NULL}
-};
-
-/* return 0 if not found */
-static uint32_t uc32_cpu_find_by_name(const char *name)
-{
- int i;
- uint32_t id;
-
- id = 0;
- for (i = 0; uc32_cpu_names[i].name; i++) {
- if (strcmp(name, uc32_cpu_names[i].name) == 0) {
- id = uc32_cpu_names[i].id;
- break;
- }
- }
- return id;
-}
-
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
+ UniCore32CPU *cpu;
CPUUniCore32State *env;
uint32_t id;
static int inited = 1;
- env = g_malloc0(sizeof(CPUUniCore32State));
- cpu_exec_init(env);
+ if (object_class_by_name(cpu_model) == NULL) {
+ return NULL;
+ }
+ cpu = UNICORE32_CPU(object_new(cpu_model));
+ env = &cpu->env;
- id = uc32_cpu_find_by_name(cpu_model);
+ id = env->cp0.c0_cpuid;
switch (id) {
case UC32_CPUID_UCV2:
set_feature(env, UC32_HWCAP_CMOV);
@@ -69,17 +46,11 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
cpu_abort(env, "Bad CPU ID: %x\n", id);
}
- env->cpu_model_str = cpu_model;
- env->cp0.c0_cpuid = id;
- env->uncached_asr = ASR_MODE_USER;
- env->regs[31] = 0;
-
if (inited) {
inited = 0;
uc32_translate_init();
}
- tlb_flush(env, 1);
qemu_init_vcpu(env);
return env;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (2 preceding siblings ...)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys " Andreas Färber
` (4 subsequent siblings)
8 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu-qom.h | 1 +
target-unicore32/cpu.c | 4 ++++
target-unicore32/helper.c | 1 -
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index afe47e8..f3592d0 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -44,6 +44,7 @@ typedef struct UniCore32CPUClass {
struct {
uint32_t c0_cpuid;
+ uint32_t c0_cachetype;
} cp0;
} UniCore32CPUClass;
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index b89a1c6..c17b880 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -17,12 +17,14 @@
typedef struct UniCore32CPUInfo {
const char *name;
uint32_t cp0_c0_cpuid;
+ uint32_t cp0_c0_cachetype;
} UniCore32CPUInfo;
static const UniCore32CPUInfo uc32_cpus[] = {
{
.name = "UniCore-II",
.cp0_c0_cpuid = 0x40010863,
+ .cp0_c0_cachetype = 0x1dd20d2,
},
{
.name = "any",
@@ -40,6 +42,7 @@ static void uc32_cpu_initfn(Object *obj)
cpu_exec_init(env);
env->cpu_model_str = object_get_typename(obj);
env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
+ env->cp0.c0_cachetype = klass->cp0.c0_cachetype;
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
@@ -53,6 +56,7 @@ static void uc32_cpu_class_init(ObjectClass *klass, void *data)
const UniCore32CPUInfo *info = data;
k->cp0.c0_cpuid = info->cp0_c0_cpuid;
+ k->cp0.c0_cachetype = info->cp0_c0_cachetype;
}
static void uc32_register_cpu(const UniCore32CPUInfo *info)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 44b7842..5e5e34d 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -35,7 +35,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
- env->cp0.c0_cachetype = 0x1dd20d2;
env->cp0.c1_sys = 0x00090078;
break;
case UC32_CPUID_ANY: /* For userspace emulation. */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys in UniCore32CPUClass
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (3 preceding siblings ...)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags " Andreas Färber
` (3 subsequent siblings)
8 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu-qom.h | 1 +
target-unicore32/cpu.c | 4 ++++
target-unicore32/helper.c | 1 -
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index f3592d0..4d730f0 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -45,6 +45,7 @@ typedef struct UniCore32CPUClass {
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c1_sys;
} cp0;
} UniCore32CPUClass;
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index c17b880..fa5c280 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -18,6 +18,7 @@ typedef struct UniCore32CPUInfo {
const char *name;
uint32_t cp0_c0_cpuid;
uint32_t cp0_c0_cachetype;
+ uint32_t cp0_c1_sys;
} UniCore32CPUInfo;
static const UniCore32CPUInfo uc32_cpus[] = {
@@ -25,6 +26,7 @@ static const UniCore32CPUInfo uc32_cpus[] = {
.name = "UniCore-II",
.cp0_c0_cpuid = 0x40010863,
.cp0_c0_cachetype = 0x1dd20d2,
+ .cp0_c1_sys = 0x00090078,
},
{
.name = "any",
@@ -43,6 +45,7 @@ static void uc32_cpu_initfn(Object *obj)
env->cpu_model_str = object_get_typename(obj);
env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
env->cp0.c0_cachetype = klass->cp0.c0_cachetype;
+ env->cp0.c1_sys = klass->cp0.c1_sys;
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
@@ -57,6 +60,7 @@ static void uc32_cpu_class_init(ObjectClass *klass, void *data)
k->cp0.c0_cpuid = info->cp0_c0_cpuid;
k->cp0.c0_cachetype = info->cp0_c0_cachetype;
+ k->cp0.c1_sys = info->cp0_c1_sys;
}
static void uc32_register_cpu(const UniCore32CPUInfo *info)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 5e5e34d..ba9318b 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -35,7 +35,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
- env->cp0.c1_sys = 0x00090078;
break;
case UC32_CPUID_ANY: /* For userspace emulation. */
set_feature(env, UC32_HWCAP_CMOV);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags in UniCore32CPUClass
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (4 preceding siblings ...)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys " Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr " Andreas Färber
` (2 subsequent siblings)
8 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu-qom.h | 3 +++
target-unicore32/cpu.c | 9 +++++++++
target-unicore32/helper.c | 9 ---------
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index 4d730f0..c8178a5 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -34,6 +34,7 @@
/**
* UniCore32CPUClass:
+ * @features: Internal CPU feature flags.
*
* A UniCore32 CPU model.
*/
@@ -47,6 +48,8 @@ typedef struct UniCore32CPUClass {
uint32_t c0_cachetype;
uint32_t c1_sys;
} cp0;
+
+ uint32_t features;
} UniCore32CPUClass;
/**
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index fa5c280..d4b47d6 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -19,18 +19,25 @@ typedef struct UniCore32CPUInfo {
uint32_t cp0_c0_cpuid;
uint32_t cp0_c0_cachetype;
uint32_t cp0_c1_sys;
+ uint32_t features;
} UniCore32CPUInfo;
+#define UC32_FEATURE(feature) (1u << feature)
+
static const UniCore32CPUInfo uc32_cpus[] = {
{
.name = "UniCore-II",
.cp0_c0_cpuid = 0x40010863,
.cp0_c0_cachetype = 0x1dd20d2,
.cp0_c1_sys = 0x00090078,
+ .features = UC32_FEATURE(UC32_HWCAP_CMOV) |
+ UC32_FEATURE(UC32_HWCAP_UCF64),
},
{
.name = "any",
.cp0_c0_cpuid = 0xffffffff,
+ .features = UC32_FEATURE(UC32_HWCAP_CMOV) |
+ UC32_FEATURE(UC32_HWCAP_UCF64),
}
};
@@ -46,6 +53,7 @@ static void uc32_cpu_initfn(Object *obj)
env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
env->cp0.c0_cachetype = klass->cp0.c0_cachetype;
env->cp0.c1_sys = klass->cp0.c1_sys;
+ env->features = klass->features;
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
@@ -61,6 +69,7 @@ static void uc32_cpu_class_init(ObjectClass *klass, void *data)
k->cp0.c0_cpuid = info->cp0_c0_cpuid;
k->cp0.c0_cachetype = info->cp0_c0_cachetype;
k->cp0.c1_sys = info->cp0_c1_sys;
+ k->features = info->features;
}
static void uc32_register_cpu(const UniCore32CPUInfo *info)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index ba9318b..fb6713c 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -11,11 +11,6 @@
#include "helper.h"
#include "host-utils.h"
-static inline void set_feature(CPUUniCore32State *env, int feature)
-{
- env->features |= feature;
-}
-
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
UniCore32CPU *cpu;
@@ -32,13 +27,9 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
id = env->cp0.c0_cpuid;
switch (id) {
case UC32_CPUID_UCV2:
- set_feature(env, UC32_HWCAP_CMOV);
- set_feature(env, UC32_HWCAP_UCF64);
env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
break;
case UC32_CPUID_ANY: /* For userspace emulation. */
- set_feature(env, UC32_HWCAP_CMOV);
- set_feature(env, UC32_HWCAP_UCF64);
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr in UniCore32CPUClass
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (5 preceding siblings ...)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags " Andreas Färber
@ 2012-03-14 1:39 ` Andreas Färber
2012-03-14 7:32 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
2012-03-14 20:02 ` Blue Swirl
8 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Guan Xuetao, Andreas Färber
This removes the remaining CPUID dependency.
Contributed under GPLv2+.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-unicore32/cpu-qom.h | 4 ++++
target-unicore32/cpu.c | 4 ++++
target-unicore32/cpu.h | 4 ----
target-unicore32/helper.c | 12 ------------
4 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index c8178a5..594df73 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -49,6 +49,10 @@ typedef struct UniCore32CPUClass {
uint32_t c1_sys;
} cp0;
+ struct {
+ uint32_t fpscr;
+ } ucf64;
+
uint32_t features;
} UniCore32CPUClass;
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index d4b47d6..6966186 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -19,6 +19,7 @@ typedef struct UniCore32CPUInfo {
uint32_t cp0_c0_cpuid;
uint32_t cp0_c0_cachetype;
uint32_t cp0_c1_sys;
+ uint32_t ucf64_fpscr;
uint32_t features;
} UniCore32CPUInfo;
@@ -30,6 +31,7 @@ static const UniCore32CPUInfo uc32_cpus[] = {
.cp0_c0_cpuid = 0x40010863,
.cp0_c0_cachetype = 0x1dd20d2,
.cp0_c1_sys = 0x00090078,
+ .ucf64_fpscr = 0,
.features = UC32_FEATURE(UC32_HWCAP_CMOV) |
UC32_FEATURE(UC32_HWCAP_UCF64),
},
@@ -53,6 +55,7 @@ static void uc32_cpu_initfn(Object *obj)
env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
env->cp0.c0_cachetype = klass->cp0.c0_cachetype;
env->cp0.c1_sys = klass->cp0.c1_sys;
+ env->ucf64.xregs[UC32_UCF64_FPSCR] = klass->ucf64.fpscr;
env->features = klass->features;
env->uncached_asr = ASR_MODE_USER;
@@ -69,6 +72,7 @@ static void uc32_cpu_class_init(ObjectClass *klass, void *data)
k->cp0.c0_cpuid = info->cp0_c0_cpuid;
k->cp0.c0_cachetype = info->cp0_c0_cachetype;
k->cp0.c1_sys = info->cp0_c1_sys;
+ k->ucf64.fpscr = info->ucf64_fpscr;
k->features = info->features;
}
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 1ddd272..81d9e54 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -118,10 +118,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
#define UC32_HWCAP_CMOV 4 /* 1 << 2 */
#define UC32_HWCAP_UCF64 8 /* 1 << 3 */
-#define UC32_CPUID(env) (env->cp0.c0_cpuid)
-#define UC32_CPUID_UCV2 0x40010863
-#define UC32_CPUID_ANY 0xffffffff
-
#define cpu_init uc32_cpu_init
#define cpu_exec uc32_cpu_exec
#define cpu_signal_handler uc32_cpu_signal_handler
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index fb6713c..39ab488 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -15,7 +15,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
UniCore32CPU *cpu;
CPUUniCore32State *env;
- uint32_t id;
static int inited = 1;
if (object_class_by_name(cpu_model) == NULL) {
@@ -24,17 +23,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
cpu = UNICORE32_CPU(object_new(cpu_model));
env = &cpu->env;
- id = env->cp0.c0_cpuid;
- switch (id) {
- case UC32_CPUID_UCV2:
- env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
- break;
- case UC32_CPUID_ANY: /* For userspace emulation. */
- break;
- default:
- cpu_abort(env, "Bad CPU ID: %x\n", id);
- }
-
if (inited) {
inited = 0;
uc32_translate_init();
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (6 preceding siblings ...)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr " Andreas Färber
@ 2012-03-14 7:32 ` Guan Xuetao
2012-03-23 16:53 ` Andreas Färber
2012-03-14 20:02 ` Blue Swirl
8 siblings, 1 reply; 175+ messages in thread
From: Guan Xuetao @ 2012-03-14 7:32 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori
On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
> Hello,
>
> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
> the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to
> target-arm and faces a similar issue of CPU-dependent init code, so let's
> tackle it next.
>
> Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS,
> so that the target-unicore32 author gets notified of patches against his code.
>
> Patch 2, based on feedback from Guan Xuetao, changes the license of most
> target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a
> qemu_malloc() -> g_malloc() substitution that he can't relicense at this time,
> so leave that as GPLv2 and declare my following patches explicitly as GPLv2+.
>
> Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h header
> can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2 for now.
>
> Patches 4-7 move code out of the uc32_cpu_init() function and into classes.
>
> Regards,
> Andreas
Thanks for your help, and I'm sorry for my procrastination.
I pulled the latest qemu code, but these patches seems to rely on the
former qom-cpu v4 series.
Could you tell me where I can pull the testable branch/tree?
BTW: are there some robots to test qemu automatically? Then, I can put
binary files (from simple helloworld to complicated spec benchmark) into
it, perhaps write a script for running, and receive the result daily or
weekly.
Thanks and Regards
Guan Xuetao
> Cc: Guan Xue-tao <gxt@mprc.pku.edu.cn>
> Cc: Anthony Liguori <anthony@codemonkey.ws>
>
> Changes from former repo.or.cz qom-cpu[-wip] branch:
> * Drop duplicate .instance_init.
>
> Andreas Färber (7):
> MAINTAINERS: Add entry for UniCore32
> target-unicore32: Relicense to GPLv2+
> target-unicore32: QOM'ify CPU
> target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass
> target-unicore32: Store cp0 c1_sys in UniCore32CPUClass
> target-unicore32: Store feature flags in UniCore32CPUClass
> target-unicore32: Store ucf64 fpscr in UniCore32CPUClass
>
> MAINTAINERS | 5 ++
> Makefile.target | 1 +
> target-unicore32/cpu-qom.h | 81 ++++++++++++++++++++++++++++++
> target-unicore32/cpu.c | 112 ++++++++++++++++++++++++++++++++++++++++++
> target-unicore32/cpu.h | 10 +---
> target-unicore32/helper.c | 62 ++---------------------
> target-unicore32/helper.h | 5 +-
> target-unicore32/op_helper.c | 5 +-
> target-unicore32/translate.c | 5 +-
> 9 files changed, 213 insertions(+), 73 deletions(-)
> create mode 100644 target-unicore32/cpu-qom.h
> create mode 100644 target-unicore32/cpu.c
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32
2012-03-14 1:39 ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
@ 2012-03-14 7:44 ` Guan Xuetao
0 siblings, 0 replies; 175+ messages in thread
From: Guan Xuetao @ 2012-03-14 7:44 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
> Consider it Odd Fixes for now.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
> ---
> MAINTAINERS | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f83d07c2..44ff923 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -112,6 +112,11 @@ M: Blue Swirl <blauwirbel@gmail.com>
> S: Maintained
> F: target-sparc/
>
> +UniCore32
> +M: Guan Xuetao <gxt@mprc.pku.edu.cn>
> +S: Odd Fixes
The status can be changed to Maintained.
I will try my best to maintain it.
Guan Xuetao
> +F: target-unicore32/
> +
> X86
> M: qemu-devel@nongnu.org
> S: Odd Fixes
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
@ 2012-03-14 7:53 ` Guan Xuetao
2012-03-14 10:46 ` Andreas Färber
2012-03-14 20:03 ` Blue Swirl
2012-03-14 21:09 ` Stefan Weil
2 siblings, 1 reply; 175+ messages in thread
From: Guan Xuetao @ 2012-03-14 7:53 UTC (permalink / raw)
To: Andreas Färber; +Cc: Blue Swirl, Stefan Weil, Dor Laor, qemu-devel
On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
> Adopt the license text suggested by Guan Xue-tao for all files except
> helper.c, to which Anthony Liguori (IBM) contributed a g_malloc() call.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> Signed-off-by: Dor Laor <dlaor@redhat.com>
> ---
> target-unicore32/cpu.h | 5 ++---
> target-unicore32/helper.h | 5 ++---
> target-unicore32/op_helper.c | 5 ++---
> target-unicore32/translate.c | 5 ++---
target-unicore32/helper.c is skipped.
Guan Xuetao
> 4 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index a3f8589..9cbee7a 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -3,9 +3,8 @@
> *
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #ifndef __CPU_UC32_H__
> #define __CPU_UC32_H__
> diff --git a/target-unicore32/helper.h b/target-unicore32/helper.h
> index 615de2a..5aa7de8 100644
> --- a/target-unicore32/helper.h
> +++ b/target-unicore32/helper.h
> @@ -1,9 +1,8 @@
> /*
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #include "def-helper.h"
>
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 638a020..9fc2b1f 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -3,9 +3,8 @@
> *
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #include "cpu.h"
> #include "dyngen-exec.h"
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index 3b3ba16..c01e636 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -3,9 +3,8 @@
> *
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #include <stdarg.h>
> #include <stdlib.h>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU
2012-03-14 1:39 ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Andreas Färber
@ 2012-03-14 7:56 ` Guan Xuetao
2012-03-14 10:56 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Guan Xuetao @ 2012-03-14 7:56 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
> Embed CPUUniCore32State into UniCore32CPU.
>
> Contributed under GPLv2+.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> Makefile.target | 1 +
> target-unicore32/cpu-qom.h | 72 ++++++++++++++++++++++++++++++++++
> target-unicore32/cpu.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
I hope the gpl information for cpu.c and cpu-qom.h could be consistent
with other files.
Guan Xuetao
> target-unicore32/cpu.h | 1 +
> target-unicore32/helper.c | 43 +++-----------------
> 5 files changed, 172 insertions(+), 36 deletions(-)
> create mode 100644 target-unicore32/cpu-qom.h
> create mode 100644 target-unicore32/cpu.c
>
> diff --git a/Makefile.target b/Makefile.target
> index cbf62c0..7033df0 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -94,6 +94,7 @@ libobj-y += cpu_init.o
> endif
> libobj-$(TARGET_SPARC) += int32_helper.o
> libobj-$(TARGET_SPARC64) += int64_helper.o
> +libobj-$(TARGET_UNICORE32) += cpu.o
>
> libobj-y += disas.o
> libobj-$(CONFIG_TCI_DIS) += tci-dis.o
> diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
> new file mode 100644
> index 0000000..afe47e8
> --- /dev/null
> +++ b/target-unicore32/cpu-qom.h
> @@ -0,0 +1,72 @@
> +/*
> + * QEMU UniCore32 CPU
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + * <http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +#ifndef QEMU_UC32_CPU_QOM_H
> +#define QEMU_UC32_CPU_QOM_H
> +
> +#include "qemu/cpu.h"
> +#include "cpu.h"
> +
> +#define TYPE_UNICORE32_CPU "unicore32-cpu"
> +
> +#define UNICORE32_CPU_CLASS(klass) \
> + OBJECT_CLASS_CHECK(UniCore32CPUClass, (klass), TYPE_UNICORE32_CPU)
> +#define UNICORE32_CPU(obj) \
> + OBJECT_CHECK(UniCore32CPU, (obj), TYPE_UNICORE32_CPU)
> +#define UNICORE32_CPU_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(UniCore32CPUClass, (obj), TYPE_UNICORE32_CPU)
> +
> +/**
> + * UniCore32CPUClass:
> + *
> + * A UniCore32 CPU model.
> + */
> +typedef struct UniCore32CPUClass {
> + /*< private >*/
> + CPUClass parent_class;
> + /*< public >*/
> +
> + struct {
> + uint32_t c0_cpuid;
> + } cp0;
> +} UniCore32CPUClass;
> +
> +/**
> + * UniCore32CPU:
> + * @env: Legacy CPU state.
> + *
> + * A UniCore32 CPU.
> + */
> +typedef struct UniCore32CPU {
> + /*< private >*/
> + CPUState parent_obj;
> + /*< public >*/
> +
> + CPUUniCore32State env;
> +} UniCore32CPU;
> +
> +static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
> +{
> + return UNICORE32_CPU(container_of(env, UniCore32CPU, env));
> +}
> +
> +#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
> +
> +
> +#endif
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> new file mode 100644
> index 0000000..b89a1c6
> --- /dev/null
> +++ b/target-unicore32/cpu.c
> @@ -0,0 +1,91 @@
> +/*
> + * QEMU UniCore32 CPU
> + *
> + * Copyright (c) 2010-2011 GUAN Xue-tao
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "cpu-qom.h"
> +#include "qemu-common.h"
> +
> +/* CPU models */
> +
> +typedef struct UniCore32CPUInfo {
> + const char *name;
> + uint32_t cp0_c0_cpuid;
> +} UniCore32CPUInfo;
> +
> +static const UniCore32CPUInfo uc32_cpus[] = {
> + {
> + .name = "UniCore-II",
> + .cp0_c0_cpuid = 0x40010863,
> + },
> + {
> + .name = "any",
> + .cp0_c0_cpuid = 0xffffffff,
> + }
> +};
> +
> +static void uc32_cpu_initfn(Object *obj)
> +{
> + UniCore32CPU *cpu = UNICORE32_CPU(obj);
> + UniCore32CPUClass *klass = UNICORE32_CPU_GET_CLASS(cpu);
> + CPUUniCore32State *env = &cpu->env;
> +
> + memset(env, 0, sizeof(CPUUniCore32State));
> + cpu_exec_init(env);
> + env->cpu_model_str = object_get_typename(obj);
> + env->cp0.c0_cpuid = klass->cp0.c0_cpuid;
> +
> + env->uncached_asr = ASR_MODE_USER;
> + env->regs[31] = 0;
> +
> + tlb_flush(env, 1);
> +}
> +
> +static void uc32_cpu_class_init(ObjectClass *klass, void *data)
> +{
> + UniCore32CPUClass *k = UNICORE32_CPU_CLASS(klass);
> + const UniCore32CPUInfo *info = data;
> +
> + k->cp0.c0_cpuid = info->cp0_c0_cpuid;
> +}
> +
> +static void uc32_register_cpu(const UniCore32CPUInfo *info)
> +{
> + TypeInfo type = {
> + .name = info->name,
> + .parent = TYPE_UNICORE32_CPU,
> + .instance_size = sizeof(UniCore32CPU),
> + .class_size = sizeof(UniCore32CPUClass),
> + .class_init = uc32_cpu_class_init,
> + .class_data = (void *)info,
> + };
> +
> + type_register_static(&type);
> +}
> +
> +static const TypeInfo uc32_cpu_info = {
> + .name = TYPE_UNICORE32_CPU,
> + .parent = TYPE_CPU,
> + .instance_size = sizeof(UniCore32CPU),
> + .instance_init = uc32_cpu_initfn,
> + .abstract = true,
> + .class_size = sizeof(UniCore32CPUClass),
> +};
> +
> +static void uc32_cpu_register_types(void)
> +{
> + int i;
> +
> + type_register_static(&uc32_cpu_info);
> + for (i = 0; i < ARRAY_SIZE(uc32_cpus); i++) {
> + uc32_register_cpu(&uc32_cpus[i]);
> + }
> +}
> +
> +type_init(uc32_cpu_register_types)
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 9cbee7a..1ddd272 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -158,6 +158,7 @@ static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls)
> }
>
> #include "cpu-all.h"
> +#include "cpu-qom.h"
> #include "exec-all.h"
>
> static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index 6af492d..44b7842 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -16,43 +16,20 @@ static inline void set_feature(CPUUniCore32State *env, int feature)
> env->features |= feature;
> }
>
> -struct uc32_cpu_t {
> - uint32_t id;
> - const char *name;
> -};
> -
> -static const struct uc32_cpu_t uc32_cpu_names[] = {
> - { UC32_CPUID_UCV2, "UniCore-II"},
> - { UC32_CPUID_ANY, "any"},
> - { 0, NULL}
> -};
> -
> -/* return 0 if not found */
> -static uint32_t uc32_cpu_find_by_name(const char *name)
> -{
> - int i;
> - uint32_t id;
> -
> - id = 0;
> - for (i = 0; uc32_cpu_names[i].name; i++) {
> - if (strcmp(name, uc32_cpu_names[i].name) == 0) {
> - id = uc32_cpu_names[i].id;
> - break;
> - }
> - }
> - return id;
> -}
> -
> CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
> {
> + UniCore32CPU *cpu;
> CPUUniCore32State *env;
> uint32_t id;
> static int inited = 1;
>
> - env = g_malloc0(sizeof(CPUUniCore32State));
> - cpu_exec_init(env);
> + if (object_class_by_name(cpu_model) == NULL) {
> + return NULL;
> + }
> + cpu = UNICORE32_CPU(object_new(cpu_model));
> + env = &cpu->env;
>
> - id = uc32_cpu_find_by_name(cpu_model);
> + id = env->cp0.c0_cpuid;
> switch (id) {
> case UC32_CPUID_UCV2:
> set_feature(env, UC32_HWCAP_CMOV);
> @@ -69,17 +46,11 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
> cpu_abort(env, "Bad CPU ID: %x\n", id);
> }
>
> - env->cpu_model_str = cpu_model;
> - env->cp0.c0_cpuid = id;
> - env->uncached_asr = ASR_MODE_USER;
> - env->regs[31] = 0;
> -
> if (inited) {
> inited = 0;
> uc32_translate_init();
> }
>
> - tlb_flush(env, 1);
> qemu_init_vcpu(env);
> return env;
> }
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass
2012-03-13 17:58 ` Andreas Färber
` (2 preceding siblings ...)
2012-03-13 18:12 ` Peter Maydell
@ 2012-03-14 8:58 ` Igor Mitsyanko
3 siblings, 0 replies; 175+ messages in thread
From: Igor Mitsyanko @ 2012-03-14 8:58 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Paul Brook, qemu-devel, Anthony Liguori, Dmitry Solodkiy
[-- Attachment #1: Type: text/plain, Size: 3202 bytes --]
On 03/13/2012 09:58 PM, Andreas Färber wrote:
> Am 13.03.2012 13:31, schrieb Igor Mitsyanko:
>> On 03/10/2012 08:53 PM, Andreas Färber wrote:
>>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>>> new file mode 100644
>>> index 0000000..dabc094
>>> --- /dev/null
>>> +++ b/target-arm/cpu.c
> [...]
>>> +static void cpu_register(const ARMCPUInfo *info)
>>> +{
>>> + TypeInfo type = {
>>> + .name = info->name,
>>> + .parent = TYPE_ARM_CPU,
>>> + .instance_size = sizeof(ARMCPU),
>>> + .class_size = sizeof(ARMCPUClass),
>>> + .class_init = arm_cpu_class_init,
>>> + .class_data = (void *)info,
>>> + };
>> Are non-initialized members guaranteed to be zero here?
> I thought so for the C99-style struct initialization... I never ran into
> crashes while testing. Do we need static to be safe?
>
>>> + type_register_static(&type);
>>> +}
>>> +
>> Probably should be type_register() here in case these two will actually
>> differ in the future.
> My thinking was we don't need it here because the data (esp. strings)
> are not dynamically allocated. By comparison, I used type_register() for
> -cpudef in target-i386, I believe.
>
> But I really guess it's a bug that they're just an alias right now! ;)
>
Object.h states we need to use type_register_static() only when TypeInfo
exists for the lifetime of
Type. As I understand this, TypeInfo must have *static const* storage
qualifier when used with type_register_static() and can have automatic
storage qualifier when used with type_register().
Maybe in the future type_register_static() will just copy a pointer to
string variables of passed
TypeInfo instead of g_strdup() them, then your code wouldn't work as
expected.
>> If this information is of any help, we've got no problems when emulating
>> ARM-based Exynos boards in QEMU with this whole patchset applied.
> Thanks a lot for testing!
>
> Have you thought about how to QOM'ify your boards? Mid-term I'd like to
> see an "exynos4210" object with the CPUs on it - maybe "cpu[0]" and
> "cpu[1]" child properties? Or "core[x]"? I had played with the sh7750 a
> bit on my branch but like the arm926 it's a single-core.
>
> Andreas
>
Yes, we've done some work on this, but we are waiting to see how you
want to proceed with SoC
QOM type, and if you're going to introduce it at all. Personally I have
no idea what members and
methods a general SoC type could have.
And another question, should we somehow exploit a fact that majority of
peripheral devices on
SoCs share i/o ports with each other and only a handful of them are
actually active at the same
time. Currently we instantiate all SoC devices even if half of them are
not used in emulated configuration. Maybe we should dynamically
create/destroy devices depending on runtime GPIO
configuration, or make all devices a board's child instead of SoC's
child. Not sure that it's worth an effort though.
As for CPU's object, Peter's idea with CortexA9 and core1, core2 childs
looks good to me.
--
Mitsyanko Igor
ASWG, Moscow R&D center, Samsung Electronics
email: i.mitsyanko@samsung.com
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^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+
2012-03-14 7:53 ` Guan Xuetao
@ 2012-03-14 10:46 ` Andreas Färber
0 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 10:46 UTC (permalink / raw)
To: gxt
Cc: Stefan Weil, Dor Laor, qemu-devel, Blue Swirl, Anthony Liguori,
Paolo Bonzini
Am 14.03.2012 08:53, schrieb Guan Xuetao:
> On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
>> Adopt the license text suggested by Guan Xue-tao for all files except
>> helper.c, to which Anthony Liguori (IBM) contributed a g_malloc() call.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>> Signed-off-by: Stefan Weil <sw@weilnetz.de>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> Signed-off-by: Dor Laor <dlaor@redhat.com>
>> ---
>> target-unicore32/cpu.h | 5 ++---
>> target-unicore32/helper.h | 5 ++---
>> target-unicore32/op_helper.c | 5 ++---
>> target-unicore32/translate.c | 5 ++---
> target-unicore32/helper.c is skipped.
...which is explained in the above commit message and in the cover
letter. :)
Whether we can relicense it to GPLv2+ after patch 3/7 (which redoes
object instantiation in a way not derived from an IBM contribution)
remained an open question. IANAL.
What we can do, similar to Paolo's solution for central files, is to add
a notice to helper.c that makes new contributions from, e.g., today on
GPLv2+ so we don't need to ask for more people's permission.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU
2012-03-14 7:56 ` Guan Xuetao
@ 2012-03-14 10:56 ` Andreas Färber
2012-03-15 1:04 ` Guan Xuetao
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 10:56 UTC (permalink / raw)
To: gxt; +Cc: qemu-devel
Am 14.03.2012 08:56, schrieb Guan Xuetao:
> On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
>> Embed CPUUniCore32State into UniCore32CPU.
>>
>> Contributed under GPLv2+.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>> ---
>> Makefile.target | 1 +
>> target-unicore32/cpu-qom.h | 72 ++++++++++++++++++++++++++++++++++
>> target-unicore32/cpu.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
> I hope the gpl information for cpu.c and cpu-qom.h could be consistent
> with other files.
Copy&paste from other cpu-qom.h files. :) I can change it to match the
rest of target-unicore32.
But speaking of matching licenses, your previous text has "as published
by the Free Software Foundation", which I think is a bit safer in theory
(no company X can publish a "GPL" v4 of their own and change it to their
liking) and would make the change smaller. For example:
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * published by the Free Software Foundation, or (at your option) any
+ * later version. See the COPYING file in the top-level directory.
What do you think?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 14/44] target-arm: Don't overuse CPUState
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
@ 2012-03-14 14:39 ` Peter Maydell
2012-03-14 18:33 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Peter Maydell @ 2012-03-14 14:39 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 10 March 2012 02:27, Andreas Färber <afaerber@suse.de> wrote:
> Scripted conversion:
> sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc]
> sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
Some of these automated changes in iwmmxt_helper.c break the
neatly lined up '\' macro continuation characters...
I'm not sure I care enough to suggest that we should manually fix
this though, especially not for the ones which are full of hard
coded tabs.
Acked-by: Peter Maydell <peter.maydell@linaro.org>
-- PMM
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
` (6 preceding siblings ...)
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU Andreas Färber
` (12 more replies)
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
8 siblings, 13 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurélien Jarno
Hello,
Based on qom-cpu v4 and object_class_get_list() v2, this series converts
the SuperH CPU to QOM.
The SH7750 SoC code invited to do some cleanups, making use of the SuperHCPU,
so I've QOM'ified the SoC and added the CPU as a link<SuperHCPU> for now.
I'm not so happy about the link construct, so it may need to be redone
as a SysBus device with qdev properties - long-term I'd like to have a
"system-on-chip" type derived from TYPE_DEVICE. Deriving it from
TYPE_SYS_BUS_DEVICE might make for a better v2.
Patch 1 does the actual CPU QOM'ification, introducing SuperHCPU.
Patch 2 is a bugfix noticed during QOM'ification.
Patches 3-11 start using QOM SuperHCPU in place of CPUSH4State.
Patch 12 QOM'ifies the SH7750 SoC. Optional.
Available at:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu-sh4.v1
Regards,
Andreas
Cc: Aurélien Jarno <aurelien@aurel32.net>
Andreas Färber (12):
target-sh4: QOM'ify CPU
target-sh4: Do not reset features on reset
hw/sh7750: Use SuperHCPU
target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU
target-sh4: Make increment_urc() take SuperHCPU
target-sh4: Make find_*tlb_entry() take SuperHCPU
target-sh4: Make cpu_sh4_{read,write}_mmaped_{i,u}tlb_addr() take CPU
target-sh4: Make get_{physical,mmu}_address() take SuperHCPU
target-sh4: Make copy_utlb_entry_itlb() take SuperHCPU
target-sh4: Make update_itlb_use() take SuperHCPU
target-sh4: Make itlb_replacement() use SuperHCPU
hw/sh7750: QOM'ify SH7750 SoC
Makefile.target | 1 +
hw/r2d.c | 9 ++-
hw/sh.h | 6 +-
hw/sh7750.c | 95 ++++++++++++++++---------
hw/shix.c | 8 ++-
target-sh4/cpu-qom.h | 81 +++++++++++++++++++++
target-sh4/cpu.c | 162 +++++++++++++++++++++++++++++++++++++++++
target-sh4/cpu.h | 24 +++---
target-sh4/helper.c | 188 +++++++++++++++++++++++++-----------------------
target-sh4/translate.c | 122 ++++++++++---------------------
10 files changed, 474 insertions(+), 222 deletions(-)
create mode 100644 target-sh4/cpu-qom.h
create mode 100644 target-sh4/cpu.c
--
1.7.7
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset Andreas Färber
` (11 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Embed CPUSH4State into SuperHCPU. Let cpu_state_reset() call
cpu_reset(). Let sh4_cpu_list() enumerate CPU classes alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-sh4/cpu-qom.h | 78 +++++++++++++++++++++++
target-sh4/cpu.c | 161 ++++++++++++++++++++++++++++++++++++++++++++++++
target-sh4/cpu.h | 1 +
target-sh4/translate.c | 119 +++++++++++------------------------
5 files changed, 278 insertions(+), 82 deletions(-)
create mode 100644 target-sh4/cpu-qom.h
create mode 100644 target-sh4/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 7033df0..c48a849 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -88,6 +88,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ARM) += cpu.o
+libobj-$(TARGET_SH4) += cpu.o
ifeq ($(TARGET_BASE_ARCH), sparc)
libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
libobj-y += cpu_init.o
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
new file mode 100644
index 0000000..1441328
--- /dev/null
+++ b/target-sh4/cpu-qom.h
@@ -0,0 +1,78 @@
+/*
+ * QEMU SuperH CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_SUPERH_CPU_QOM_H
+#define QEMU_SUPERH_CPU_QOM_H
+
+#include "qemu-common.h"
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_SUPERH_CPU "superh-cpu"
+
+#define SUPERH_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
+#define SUPERH_CPU(obj) \
+ OBJECT_CHECK(SuperHCPU, (obj), TYPE_SUPERH_CPU)
+#define SUPERH_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SuperHCPUClass, (obj), TYPE_SUPERH_CPU)
+
+/**
+ * SuperHCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A SuperH CPU model.
+ */
+typedef struct SuperHCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ int id;
+ uint32_t pvr;
+ uint32_t prr;
+ uint32_t cvr;
+ uint32_t features;
+} SuperHCPUClass;
+
+/**
+ * SuperHCPU:
+ * @env: Legacy CPU state.
+ *
+ * A SuperH CPU.
+ */
+typedef struct SuperHCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUSH4State env;
+} SuperHCPU;
+
+static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
+{
+ return SUPERH_CPU(container_of(env, SuperHCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
+
+
+#endif
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
new file mode 100644
index 0000000..68034b6
--- /dev/null
+++ b/target-sh4/cpu.c
@@ -0,0 +1,161 @@
+/*
+ * QEMU SuperH CPU
+ *
+ * Copyright (c) 2005 Samuel Tardieu
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void superh_cpu_reset(CPUState *c)
+{
+ SuperHCPU *cpu = SUPERH_CPU(c);
+ SuperHCPUClass *klass = SUPERH_CPU_GET_CLASS(cpu);
+ CPUSH4State *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUSH4State, breakpoints));
+ tlb_flush(env, 1);
+
+ env->pc = 0xA0000000;
+#if defined(CONFIG_USER_ONLY)
+ env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
+ set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
+#else
+ env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
+ env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to
+ SH4 manual */
+ set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+ set_flush_to_zero(1, &env->fp_status);
+#endif
+ set_default_nan_mode(1, &env->fp_status);
+}
+
+/* CPU models */
+
+typedef struct {
+ const char *name;
+ int id;
+ uint32_t pvr;
+ uint32_t prr;
+ uint32_t cvr;
+ uint32_t features;
+} SuperHCPUInfo;
+
+static const SuperHCPUInfo superh_cpus[] = {
+ {
+ .name = "SH7750R",
+ .id = SH_CPU_SH7750R,
+ .pvr = 0x00050000,
+ .prr = 0x00000100,
+ .cvr = 0x00110000,
+ .features = SH_FEATURE_BCR3_AND_BCR4,
+ }, {
+ .name = "SH7751R",
+ .id = SH_CPU_SH7751R,
+ .pvr = 0x04050005,
+ .prr = 0x00000113,
+ .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
+ .features = SH_FEATURE_BCR3_AND_BCR4,
+ }, {
+ .name = "SH7785",
+ .id = SH_CPU_SH7785,
+ .pvr = 0x10300700,
+ .prr = 0x00000200,
+ .cvr = 0x71440211,
+ .features = SH_FEATURE_SH4A,
+ },
+};
+
+static void superh_cpu_initfn(Object *obj)
+{
+ SuperHCPU *cpu = SUPERH_CPU(obj);
+ SuperHCPUClass *klass = SUPERH_CPU_GET_CLASS(cpu);
+ CPUSH4State *env = &cpu->env;
+
+ memset(env, 0, sizeof(CPUSH4State));
+ env->cpu_model_str = object_get_typename(obj);
+ cpu_exec_init(env);
+
+ env->id = klass->id;
+ env->pvr = klass->pvr;
+ env->prr = klass->prr;
+ env->cvr = klass->cvr;
+ env->features = klass->features;
+
+ env->movcal_backup_tail = &(env->movcal_backup);
+
+ cpu_reset(CPU(cpu));
+}
+
+static void superh_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ SuperHCPUClass *k = SUPERH_CPU_CLASS(klass);
+ const SuperHCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = superh_cpu_reset;
+
+ k->id = info->id;
+ k->pvr = info->pvr;
+ k->prr = info->prr;
+ k->cvr = info->cvr;
+ k->features = info->features;
+}
+
+static void cpu_register(const SuperHCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_SUPERH_CPU,
+ .instance_size = sizeof(SuperHCPU),
+ .instance_init = superh_cpu_initfn,
+ .class_size = sizeof(SuperHCPUClass),
+ .class_init = superh_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo superh_cpu_type_info = {
+ .name = TYPE_SUPERH_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(SuperHCPU),
+ .abstract = true,
+ .class_size = sizeof(SuperHCPUClass),
+};
+
+static void superh_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&superh_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(superh_cpus); i++) {
+ cpu_register(&superh_cpus[i]);
+ }
+}
+
+type_init(superh_cpu_register_types)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 965536d..ec5e6cf 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -255,6 +255,7 @@ static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
#endif
#include "cpu-all.h"
+#include "cpu-qom.h"
/* Memory access type */
enum {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index a337beb..71434d0 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -180,107 +180,62 @@ void cpu_dump_state(CPUSH4State * env, FILE * f,
void cpu_state_reset(CPUSH4State *env)
{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- memset(env, 0, offsetof(CPUSH4State, breakpoints));
- tlb_flush(env, 1);
-
- env->pc = 0xA0000000;
-#if defined(CONFIG_USER_ONLY)
- env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
- set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
-#else
- env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
- env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
- set_float_rounding_mode(float_round_to_zero, &env->fp_status);
- set_flush_to_zero(1, &env->fp_status);
-#endif
- set_default_nan_mode(1, &env->fp_status);
+ cpu_reset(ENV_GET_CPU(env));
}
-typedef struct {
- const char *name;
- int id;
- uint32_t pvr;
- uint32_t prr;
- uint32_t cvr;
- uint32_t features;
-} sh4_def_t;
-
-static sh4_def_t sh4_defs[] = {
- {
- .name = "SH7750R",
- .id = SH_CPU_SH7750R,
- .pvr = 0x00050000,
- .prr = 0x00000100,
- .cvr = 0x00110000,
- .features = SH_FEATURE_BCR3_AND_BCR4,
- }, {
- .name = "SH7751R",
- .id = SH_CPU_SH7751R,
- .pvr = 0x04050005,
- .prr = 0x00000113,
- .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
- .features = SH_FEATURE_BCR3_AND_BCR4,
- }, {
- .name = "SH7785",
- .id = SH_CPU_SH7785,
- .pvr = 0x10300700,
- .prr = 0x00000200,
- .cvr = 0x71440211,
- .features = SH_FEATURE_SH4A,
- },
-};
+typedef struct SuperHCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} SuperHCPUListState;
-static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
+static gint sh_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- int i;
-
- if (strcasecmp(name, "any") == 0)
- return &sh4_defs[0];
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
- for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
- if (strcasecmp(name, sh4_defs[i].name) == 0)
- return &sh4_defs[i];
-
- return NULL;
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
}
-void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+static void sh_cpu_list_entry(gpointer data, gpointer user_data)
{
- int i;
+ ObjectClass *klass = data;
+ SuperHCPUListState *s = user_data;
- for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
- (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
+ (*s->cpu_fprintf)(s->file, "%s\n",
+ object_class_get_name(klass));
}
-static void cpu_register(CPUSH4State *env, const sh4_def_t *def)
+void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
- env->pvr = def->pvr;
- env->prr = def->prr;
- env->cvr = def->cvr;
- env->id = def->id;
+ SuperHCPUListState s = {
+ .cpu_fprintf = cpu_fprintf,
+ .file = f,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_SUPERH_CPU, false);
+ list = g_slist_sort(list, sh_cpu_list_compare);
+ g_slist_foreach(list, sh_cpu_list_entry, &s);
+ g_slist_free(list);
}
CPUSH4State *cpu_sh4_init(const char *cpu_model)
{
+ SuperHCPU *cpu;
CPUSH4State *env;
- const sh4_def_t *def;
- def = cpu_sh4_find_by_name(cpu_model);
- if (!def)
- return NULL;
- env = g_malloc0(sizeof(CPUSH4State));
- env->features = def->features;
- cpu_exec_init(env);
- env->movcal_backup_tail = &(env->movcal_backup);
+ if (strcasecmp(cpu_model, "any") == 0) {
+ cpu_model = "SH7750R";
+ }
+ if (object_class_by_name(cpu_model) == NULL) {
+ return NULL;
+ }
+ cpu = SUPERH_CPU(object_new(cpu_model));
+ env = &cpu->env;
+
sh4_translate_init();
- env->cpu_model_str = cpu_model;
- cpu_state_reset(env);
- cpu_register(env, def);
+
qemu_init_vcpu(env);
return env;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU Andreas Färber
` (10 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Move them out of CPUSH4State so that they are not zero'ed on reset.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/sh7750.c | 5 +++--
target-sh4/cpu-qom.h | 3 +++
target-sh4/cpu.c | 3 ++-
target-sh4/cpu.h | 3 ---
target-sh4/translate.c | 3 ++-
5 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index e712928..c7e653c 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -77,10 +77,11 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-static inline int has_bcr3_and_bcr4(SH7750State * s)
+static inline int has_bcr3_and_bcr4(SH7750State *s)
{
- return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+ return sh_env_get_cpu(s->cpu)->features & SH_FEATURE_BCR3_AND_BCR4;
}
+
/**********************************************************************
I/O ports
**********************************************************************/
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 1441328..c8cc63e 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -55,6 +55,7 @@ typedef struct SuperHCPUClass {
/**
* SuperHCPU:
+ * @features: CPU feature flags, see #sh_features.
* @env: Legacy CPU state.
*
* A SuperH CPU.
@@ -64,6 +65,8 @@ typedef struct SuperHCPU {
CPUState parent_obj;
/*< public >*/
+ uint32_t features;
+
CPUSH4State env;
} SuperHCPU;
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 68034b6..d1bd156 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -94,6 +94,8 @@ static void superh_cpu_initfn(Object *obj)
SuperHCPUClass *klass = SUPERH_CPU_GET_CLASS(cpu);
CPUSH4State *env = &cpu->env;
+ cpu->features = klass->features;
+
memset(env, 0, sizeof(CPUSH4State));
env->cpu_model_str = object_get_typename(obj);
cpu_exec_init(env);
@@ -102,7 +104,6 @@ static void superh_cpu_initfn(Object *obj)
env->pvr = klass->pvr;
env->prr = klass->prr;
env->cvr = klass->cvr;
- env->features = klass->features;
env->movcal_backup_tail = &(env->movcal_backup);
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index ec5e6cf..ee8ba5e 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -157,9 +157,6 @@ typedef struct CPUSH4State {
/* float point status register */
float_status fp_status;
- /* The features that we should emulate. See sh_features above. */
- uint32_t features;
-
/* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 71434d0..d43cd8c 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1876,6 +1876,7 @@ static inline void
gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
int search_pc)
{
+ SuperHCPU *cpu = sh_env_get_cpu(env);
DisasContext ctx;
target_ulong pc_start;
static uint16_t *gen_opc_end;
@@ -1897,7 +1898,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
ctx.singlestep_enabled = env->singlestep_enabled;
- ctx.features = env->features;
+ ctx.features = cpu->features;
ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
ii = -1;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU Andreas Färber
` (9 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
In place of CPUSH4State use SuperHCPU for SH7750State::cpu field.
Fix tab indentation on those lines and add braces.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/sh7750.c | 69 ++++++++++++++++++++++++++++++-----------------------------
1 files changed, 35 insertions(+), 34 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index c7e653c..23950aa 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -44,7 +44,7 @@ typedef struct SH7750State {
MemoryRegion iomem_ffc;
MemoryRegion mmct_iomem;
/* CPU */
- CPUSH4State *cpu;
+ SuperHCPU *cpu;
/* Peripheral frequency in Hz */
uint32_t periph_freq;
/* SDRAM controller */
@@ -79,7 +79,7 @@ typedef struct SH7750State {
static inline int has_bcr3_and_bcr4(SH7750State *s)
{
- return sh_env_get_cpu(s->cpu)->features & SH_FEATURE_BCR3_AND_BCR4;
+ return s->cpu->features & SH_FEATURE_BCR3_AND_BCR4;
}
/**********************************************************************
@@ -271,29 +271,29 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
ignore_access("long read", addr);
return 0;
case SH7750_MMUCR_A7:
- return s->cpu->mmucr;
+ return s->cpu->env.mmucr;
case SH7750_PTEH_A7:
- return s->cpu->pteh;
+ return s->cpu->env.pteh;
case SH7750_PTEL_A7:
- return s->cpu->ptel;
+ return s->cpu->env.ptel;
case SH7750_TTB_A7:
- return s->cpu->ttb;
+ return s->cpu->env.ttb;
case SH7750_TEA_A7:
- return s->cpu->tea;
+ return s->cpu->env.tea;
case SH7750_TRA_A7:
- return s->cpu->tra;
+ return s->cpu->env.tra;
case SH7750_EXPEVT_A7:
- return s->cpu->expevt;
+ return s->cpu->env.expevt;
case SH7750_INTEVT_A7:
- return s->cpu->intevt;
+ return s->cpu->env.intevt;
case SH7750_CCR_A7:
return s->ccr;
case 0x1f000030: /* Processor version */
- return s->cpu->pvr;
+ return s->cpu->env.pvr;
case 0x1f000040: /* Cache version */
- return s->cpu->cvr;
+ return s->cpu->env.cvr;
case 0x1f000044: /* Processor revision */
- return s->cpu->prr;
+ return s->cpu->env.prr;
default:
error_access("long read", addr);
abort();
@@ -406,36 +406,37 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
return;
case SH7750_MMUCR_A7:
if (mem_value & MMUCR_TI) {
- cpu_sh4_invalidate_tlb(s->cpu);
+ cpu_sh4_invalidate_tlb(&s->cpu->env);
}
- s->cpu->mmucr = mem_value & ~MMUCR_TI;
+ s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
return;
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
- if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
- tlb_flush(s->cpu, 1);
- s->cpu->pteh = mem_value;
+ if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
+ tlb_flush(&s->cpu->env, 1);
+ }
+ s->cpu->env.pteh = mem_value;
return;
case SH7750_PTEL_A7:
- s->cpu->ptel = mem_value;
+ s->cpu->env.ptel = mem_value;
return;
case SH7750_PTEA_A7:
- s->cpu->ptea = mem_value & 0x0000000f;
+ s->cpu->env.ptea = mem_value & 0x0000000f;
return;
case SH7750_TTB_A7:
- s->cpu->ttb = mem_value;
+ s->cpu->env.ttb = mem_value;
return;
case SH7750_TEA_A7:
- s->cpu->tea = mem_value;
+ s->cpu->env.tea = mem_value;
return;
case SH7750_TRA_A7:
- s->cpu->tra = mem_value & 0x000007ff;
+ s->cpu->env.tra = mem_value & 0x000007ff;
return;
case SH7750_EXPEVT_A7:
- s->cpu->expevt = mem_value & 0x000007ff;
+ s->cpu->env.expevt = mem_value & 0x000007ff;
return;
case SH7750_INTEVT_A7:
- s->cpu->intevt = mem_value & 0x000007ff;
+ s->cpu->env.intevt = mem_value & 0x000007ff;
return;
case SH7750_CCR_A7:
s->ccr = mem_value;
@@ -648,20 +649,20 @@ static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
/* do nothing */
break;
case MM_ITLB_ADDR:
- ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
break;
case MM_ITLB_DATA:
- ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
break;
case MM_OCACHE_ADDR:
case MM_OCACHE_DATA:
/* do nothing */
break;
case MM_UTLB_ADDR:
- ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
break;
case MM_UTLB_DATA:
- ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr);
+ ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
break;
default:
abort();
@@ -691,10 +692,10 @@ static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
/* do nothing */
break;
case MM_ITLB_ADDR:
- cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
break;
case MM_ITLB_DATA:
- cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
abort();
break;
case MM_OCACHE_ADDR:
@@ -702,10 +703,10 @@ static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
/* do nothing */
break;
case MM_UTLB_ADDR:
- cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
break;
case MM_UTLB_DATA:
- cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value);
+ cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
break;
default:
abort();
@@ -724,7 +725,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
SH7750State *s;
s = g_malloc0(sizeof(SH7750State));
- s->cpu = cpu;
+ s->cpu = sh_env_get_cpu(cpu);
s->periph_freq = 60000000; /* 60MHz */
memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
"memory", 0x1fc01000);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (2 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() " Andreas Färber
` (8 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Change argument type from CPUSH4State to SuperHCPU.
This simplifies the SH7750 SoC as its only caller.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/sh7750.c | 2 +-
target-sh4/cpu.h | 4 +++-
target-sh4/helper.c | 8 ++++----
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 23950aa..ca7839e 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -406,7 +406,7 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
return;
case SH7750_MMUCR_A7:
if (mem_value & MMUCR_TI) {
- cpu_sh4_invalidate_tlb(&s->cpu->env);
+ cpu_sh4_invalidate_tlb(s->cpu);
}
s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
return;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index ee8ba5e..32e59e7 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -186,6 +186,8 @@ typedef struct CPUSH4State {
memory_content **movcal_backup_tail;
} CPUSH4State;
+typedef struct SuperHCPU SuperHCPU;
+
CPUSH4State *cpu_sh4_init(const char *cpu_model);
int cpu_sh4_exec(CPUSH4State * s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
@@ -197,7 +199,7 @@ void do_interrupt(CPUSH4State * env);
void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#if !defined(CONFIG_USER_ONLY)
-void cpu_sh4_invalidate_tlb(CPUSH4State *s);
+void cpu_sh4_invalidate_tlb(SuperHCPU *cpu);
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
target_phys_addr_t addr);
void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 5c57380..655faaa 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -555,22 +555,22 @@ void cpu_load_tlb(CPUSH4State * env)
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
}
- void cpu_sh4_invalidate_tlb(CPUSH4State *s)
+void cpu_sh4_invalidate_tlb(SuperHCPU *cpu)
{
int i;
/* UTLB */
for (i = 0; i < UTLB_SIZE; i++) {
- tlb_t * entry = &s->utlb[i];
+ tlb_t *entry = &cpu->env.utlb[i];
entry->v = 0;
}
/* ITLB */
for (i = 0; i < ITLB_SIZE; i++) {
- tlb_t * entry = &s->itlb[i];
+ tlb_t *entry = &cpu->env.itlb[i];
entry->v = 0;
}
- tlb_flush(s, 1);
+ tlb_flush(&cpu->env, 1);
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() take SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (3 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() " Andreas Färber
` (7 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/helper.c | 23 ++++++++++++-----------
1 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 655faaa..2d5a4e4 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -269,17 +269,18 @@ static int find_tlb_entry(CPUSH4State * env, target_ulong address,
return match;
}
-static void increment_urc(CPUSH4State * env)
+static void increment_urc(SuperHCPU *cpu)
{
uint8_t urb, urc;
/* Increment URC */
- urb = ((env->mmucr) >> 18) & 0x3f;
- urc = ((env->mmucr) >> 10) & 0x3f;
+ urb = ((cpu->env.mmucr) >> 18) & 0x3f;
+ urc = ((cpu->env.mmucr) >> 10) & 0x3f;
urc++;
- if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
+ if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) {
urc = 0;
- env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
+ }
+ cpu->env.mmucr = (cpu->env.mmucr & 0xffff03ff) | (urc << 10);
}
/* Copy and utlb entry into itlb
@@ -324,7 +325,7 @@ static int find_itlb_entry(CPUSH4State * env, target_ulong address,
static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
{
/* per utlb access */
- increment_urc(env);
+ increment_urc(sh_env_get_cpu(env));
/* Return entry */
return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
@@ -660,7 +661,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
- increment_urc(s); /* per utlb access */
+ increment_urc(sh_env_get_cpu(s)); /* per utlb access */
return (entry->vpn << 10) |
(entry->v << 8) |
@@ -702,7 +703,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
entry->d = d;
utlb_match_entry = entry;
}
- increment_urc(s); /* per utlb access */
+ increment_urc(sh_env_get_cpu(s)); /* per utlb access */
}
/* search ITLB */
@@ -735,7 +736,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
entry->vpn = vpn;
entry->d = d;
entry->v = v;
- increment_urc(s);
+ increment_urc(sh_env_get_cpu(s));
}
}
@@ -746,7 +747,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
- increment_urc(s); /* per utlb access */
+ increment_urc(sh_env_get_cpu(s)); /* per utlb access */
if (array == 0) {
/* ITLB Data Array 1 */
@@ -773,7 +774,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
- increment_urc(s); /* per utlb access */
+ increment_urc(sh_env_get_cpu(s)); /* per utlb access */
if (array == 0) {
/* UTLB Data Array 1 */
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() take SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (4 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() " Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU Andreas Färber
` (6 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/helper.c | 29 +++++++++++++++--------------
1 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 2d5a4e4..d2186ed 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -243,15 +243,15 @@ static int itlb_replacement(CPUSH4State * env)
/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
-static int find_tlb_entry(CPUSH4State * env, target_ulong address,
- tlb_t * entries, uint8_t nbtlb, int use_asid)
+static int find_tlb_entry(SuperHCPU *cpu, target_ulong address,
+ tlb_t *entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
uint32_t start, end;
uint8_t asid;
int i;
- asid = env->pteh & 0xff;
+ asid = cpu->env.pteh & 0xff;
for (i = 0; i < nbtlb; i++) {
if (!entries[i].v)
@@ -304,31 +304,31 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
/* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/
-static int find_itlb_entry(CPUSH4State * env, target_ulong address,
+static int find_itlb_entry(SuperHCPU *cpu, target_ulong address,
int use_asid)
{
int e;
- e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
+ e = find_tlb_entry(cpu, address, cpu->env.itlb, ITLB_SIZE, use_asid);
if (e == MMU_DTLB_MULTIPLE) {
e = MMU_ITLB_MULTIPLE;
} else if (e == MMU_DTLB_MISS) {
e = MMU_ITLB_MISS;
} else if (e >= 0) {
- update_itlb_use(env, e);
+ update_itlb_use(&cpu->env, e);
}
return e;
}
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
+static int find_utlb_entry(SuperHCPU *cpu, target_ulong address, int use_asid)
{
/* per utlb access */
- increment_urc(sh_env_get_cpu(env));
+ increment_urc(cpu);
/* Return entry */
- return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
+ return find_tlb_entry(cpu, address, cpu->env.utlb, UTLB_SIZE, use_asid);
}
/* Match address against MMU
@@ -348,7 +348,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
if (rw == 2) {
- n = find_itlb_entry(env, address, use_asid);
+ n = find_itlb_entry(sh_env_get_cpu(env), address, use_asid);
if (n >= 0) {
matching = &env->itlb[n];
if (!(env->sr & SR_MD) && !(matching->pr & 2))
@@ -356,7 +356,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
else
*prot = PAGE_EXEC;
} else {
- n = find_utlb_entry(env, address, use_asid);
+ n = find_utlb_entry(sh_env_get_cpu(env), address, use_asid);
if (n >= 0) {
n = copy_utlb_entry_itlb(env, n);
matching = &env->itlb[n];
@@ -375,7 +375,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
}
}
} else {
- n = find_utlb_entry(env, address, use_asid);
+ n = find_utlb_entry(sh_env_get_cpu(env), address, use_asid);
if (n >= 0) {
matching = &env->utlb[n];
if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
@@ -801,6 +801,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
{
+ SuperHCPU *cpu = sh_env_get_cpu(env);
int n;
int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
@@ -832,11 +833,11 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
return 1;
/* check TLB */
- n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
+ n = find_tlb_entry(cpu, addr, env->itlb, ITLB_SIZE, use_asid);
if (n >= 0)
return env->itlb[n].c;
- n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
+ n = find_tlb_entry(cpu, addr, env->utlb, UTLB_SIZE, use_asid);
if (n >= 0)
return env->utlb[n].c;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (5 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() " Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU Andreas Färber
` (5 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Change argument type to SuperHCPU and update the SH7750 SoC.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/sh7750.c | 16 ++++++------
target-sh4/cpu.h | 16 ++++++------
target-sh4/helper.c | 63 ++++++++++++++++++++++++++-------------------------
3 files changed, 48 insertions(+), 47 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index ca7839e..c3cea9f 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -649,20 +649,20 @@ static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
/* do nothing */
break;
case MM_ITLB_ADDR:
- ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
+ ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr);
break;
case MM_ITLB_DATA:
- ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
+ ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr);
break;
case MM_OCACHE_ADDR:
case MM_OCACHE_DATA:
/* do nothing */
break;
case MM_UTLB_ADDR:
- ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
+ ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr);
break;
case MM_UTLB_DATA:
- ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
+ ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr);
break;
default:
abort();
@@ -692,10 +692,10 @@ static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
/* do nothing */
break;
case MM_ITLB_ADDR:
- cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
+ cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value);
break;
case MM_ITLB_DATA:
- cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
+ cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value);
abort();
break;
case MM_OCACHE_ADDR:
@@ -703,10 +703,10 @@ static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
/* do nothing */
break;
case MM_UTLB_ADDR:
- cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
+ cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
break;
case MM_UTLB_DATA:
- cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
+ cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value);
break;
default:
abort();
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 32e59e7..b3abece 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -200,21 +200,21 @@ void do_interrupt(CPUSH4State * env);
void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#if !defined(CONFIG_USER_ONLY)
void cpu_sh4_invalidate_tlb(SuperHCPU *cpu);
-uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_itlb_addr(SuperHCPU *cpu,
target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_addr(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value);
-uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_itlb_data(SuperHCPU *cpu,
target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_data(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value);
-uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_utlb_addr(SuperHCPU *cpu,
target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_addr(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value);
-uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_utlb_data(SuperHCPU *cpu,
target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_data(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value);
#endif
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index d2186ed..3653ece 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -574,18 +574,18 @@ void cpu_sh4_invalidate_tlb(SuperHCPU *cpu)
tlb_flush(&cpu->env, 1);
}
-uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_itlb_addr(SuperHCPU *cpu,
target_phys_addr_t addr)
{
int index = (addr & 0x00000300) >> 8;
- tlb_t * entry = &s->itlb[index];
+ tlb_t *entry = &cpu->env.itlb[index];
return (entry->vpn << 10) |
(entry->v << 8) |
(entry->asid);
}
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_addr(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value)
{
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
@@ -593,23 +593,23 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
int index = (addr & 0x00000300) >> 8;
- tlb_t * entry = &s->itlb[index];
+ tlb_t *entry = &cpu->env.itlb[index];
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(&cpu->env, address);
}
entry->asid = asid;
entry->vpn = vpn;
entry->v = v;
}
-uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_itlb_data(SuperHCPU *cpu,
target_phys_addr_t addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00000300) >> 8;
- tlb_t * entry = &s->itlb[index];
+ tlb_t *entry = &cpu->env.itlb[index];
if (array == 0) {
/* ITLB Data Array 1 */
@@ -627,19 +627,19 @@ uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
}
}
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_data(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00000300) >> 8;
- tlb_t * entry = &s->itlb[index];
+ tlb_t *entry = &cpu->env.itlb[index];
if (array == 0) {
/* ITLB Data Array 1 */
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(&cpu->env, address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
@@ -655,20 +655,20 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
}
}
-uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_utlb_addr(SuperHCPU *cpu,
target_phys_addr_t addr)
{
int index = (addr & 0x00003f00) >> 8;
- tlb_t * entry = &s->utlb[index];
+ tlb_t *entry = &cpu->env.utlb[index];
- increment_urc(sh_env_get_cpu(s)); /* per utlb access */
+ increment_urc(cpu); /* per utlb access */
return (entry->vpn << 10) |
(entry->v << 8) |
(entry->asid);
}
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_addr(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value)
{
int associate = addr & 0x0000080;
@@ -676,7 +676,8 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
- int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
+ int use_asid = (cpu->env.mmucr & MMUCR_SV) == 0 ||
+ (cpu->env.sr & SR_MD) == 0;
if (associate) {
int i;
@@ -685,7 +686,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
/* search UTLB */
for (i = 0; i < UTLB_SIZE; i++) {
- tlb_t * entry = &s->utlb[i];
+ tlb_t *entry = &cpu->env.utlb[i];
if (!entry->v)
continue;
@@ -693,8 +694,8 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) {
/* Multiple TLB Exception */
- s->exception_index = 0x140;
- s->tea = addr;
+ cpu->env.exception_index = 0x140;
+ cpu->env.tea = addr;
break;
}
if (entry->v && !v)
@@ -703,12 +704,12 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
entry->d = d;
utlb_match_entry = entry;
}
- increment_urc(sh_env_get_cpu(s)); /* per utlb access */
+ increment_urc(cpu); /* per utlb access */
}
/* search ITLB */
for (i = 0; i < ITLB_SIZE; i++) {
- tlb_t * entry = &s->itlb[i];
+ tlb_t *entry = &cpu->env.itlb[i];
if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (entry->v && !v)
@@ -722,32 +723,32 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
}
if (needs_tlb_flush)
- tlb_flush_page(s, vpn << 10);
+ tlb_flush_page(&cpu->env, vpn << 10);
} else {
int index = (addr & 0x00003f00) >> 8;
- tlb_t * entry = &s->utlb[index];
+ tlb_t *entry = &cpu->env.utlb[index];
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(&cpu->env, address);
}
entry->asid = asid;
entry->vpn = vpn;
entry->d = d;
entry->v = v;
- increment_urc(sh_env_get_cpu(s));
+ increment_urc(cpu);
}
}
-uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
+uint32_t cpu_sh4_read_mmaped_utlb_data(SuperHCPU *cpu,
target_phys_addr_t addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00003f00) >> 8;
- tlb_t * entry = &s->utlb[index];
+ tlb_t *entry = &cpu->env.utlb[index];
- increment_urc(sh_env_get_cpu(s)); /* per utlb access */
+ increment_urc(cpu); /* per utlb access */
if (array == 0) {
/* ITLB Data Array 1 */
@@ -767,21 +768,21 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
}
}
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_data(SuperHCPU *cpu, target_phys_addr_t addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00003f00) >> 8;
- tlb_t * entry = &s->utlb[index];
+ tlb_t *entry = &cpu->env.utlb[index];
- increment_urc(sh_env_get_cpu(s)); /* per utlb access */
+ increment_urc(cpu); /* per utlb access */
if (array == 0) {
/* UTLB Data Array 1 */
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(&cpu->env, address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (6 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() " Andreas Färber
` (4 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Simplifies TLB helper code.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/helper.c | 49 +++++++++++++++++++++++++------------------------
1 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 3653ece..d273097 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -338,30 +338,32 @@ static int find_utlb_entry(SuperHCPU *cpu, target_ulong address, int use_asid)
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
-static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
- int *prot, target_ulong address,
- int rw, int access_type)
+static int get_mmu_address(SuperHCPU *cpu, target_ulong *physical,
+ int *prot, target_ulong address,
+ int rw, int access_type)
{
int use_asid, n;
tlb_t *matching = NULL;
- use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
+ use_asid = (cpu->env.mmucr & MMUCR_SV) == 0 ||
+ (cpu->env.sr & SR_MD) == 0;
if (rw == 2) {
- n = find_itlb_entry(sh_env_get_cpu(env), address, use_asid);
+ n = find_itlb_entry(cpu, address, use_asid);
if (n >= 0) {
- matching = &env->itlb[n];
- if (!(env->sr & SR_MD) && !(matching->pr & 2))
+ matching = &cpu->env.itlb[n];
+ if (!(cpu->env.sr & SR_MD) && !(matching->pr & 2)) {
n = MMU_ITLB_VIOLATION;
- else
+ } else {
*prot = PAGE_EXEC;
+ }
} else {
- n = find_utlb_entry(sh_env_get_cpu(env), address, use_asid);
+ n = find_utlb_entry(cpu, address, use_asid);
if (n >= 0) {
- n = copy_utlb_entry_itlb(env, n);
- matching = &env->itlb[n];
- if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
- n = MMU_ITLB_VIOLATION;
+ n = copy_utlb_entry_itlb(&cpu->env, n);
+ matching = &cpu->env.itlb[n];
+ if (!(cpu->env.sr & SR_MD) && !(matching->pr & 2)) {
+ n = MMU_ITLB_VIOLATION;
} else {
*prot = PAGE_READ | PAGE_EXEC;
if ((matching->pr & 1) && matching->d) {
@@ -375,10 +377,10 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
}
}
} else {
- n = find_utlb_entry(sh_env_get_cpu(env), address, use_asid);
+ n = find_utlb_entry(cpu, address, use_asid);
if (n >= 0) {
- matching = &env->utlb[n];
- if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
+ matching = &cpu->env.utlb[n];
+ if (!(cpu->env.sr & SR_MD) && !(matching->pr & 2)) {
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
MMU_DTLB_VIOLATION_READ;
} else if ((rw == 1) && !(matching->pr & 1)) {
@@ -404,14 +406,14 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
return n;
}
-static int get_physical_address(CPUSH4State * env, target_ulong * physical,
+static int get_physical_address(SuperHCPU *cpu, target_ulong *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
/* P1, P2 and P4 areas do not use translation */
if ((address >= 0x80000000 && address < 0xc0000000) ||
address >= 0xe0000000) {
- if (!(env->sr & SR_MD)
+ if (!(cpu->env.sr & SR_MD)
&& (address < 0xe0000000 || address >= 0xe4000000)) {
/* Unauthorized access in user mode (only store queues are available) */
fprintf(stderr, "Unauthorized access\n");
@@ -433,14 +435,14 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
}
/* If MMU is disabled, return the corresponding physical page */
- if (!(env->mmucr & MMUCR_AT)) {
+ if (!(cpu->env.mmucr & MMUCR_AT)) {
*physical = address & 0x1FFFFFFF;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return MMU_OK;
}
/* We need to resort to the MMU */
- return get_mmu_address(env, physical, prot, address, rw, access_type);
+ return get_mmu_address(cpu, physical, prot, address, rw, access_type);
}
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
@@ -450,9 +452,8 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int prot, ret, access_type;
access_type = ACCESS_INT;
- ret =
- get_physical_address(env, &physical, &prot, address, rw,
- access_type);
+ ret = get_physical_address(sh_env_get_cpu(env), &physical, &prot, address,
+ rw, access_type);
if (ret != MMU_OK) {
env->tea = address;
@@ -509,7 +510,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
target_ulong physical;
int prot;
- get_physical_address(env, &physical, &prot, addr, 0, 0);
+ get_physical_address(sh_env_get_cpu(env), &physical, &prot, addr, 0, 0);
return physical;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() take SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (7 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() " Andreas Färber
` (3 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/helper.c | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index d273097..ffe79ec 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -286,18 +286,18 @@ static void increment_urc(SuperHCPU *cpu)
/* Copy and utlb entry into itlb
Return entry
*/
-static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
+static int copy_utlb_entry_itlb(SuperHCPU *cpu, int utlb)
{
int itlb;
tlb_t * ientry;
- itlb = itlb_replacement(env);
- ientry = &env->itlb[itlb];
+ itlb = itlb_replacement(&cpu->env);
+ ientry = &cpu->env.itlb[itlb];
if (ientry->v) {
- tlb_flush_page(env, ientry->vpn << 10);
+ tlb_flush_page(&cpu->env, ientry->vpn << 10);
}
- *ientry = env->utlb[utlb];
- update_itlb_use(env, itlb);
+ *ientry = cpu->env.utlb[utlb];
+ update_itlb_use(&cpu->env, itlb);
return itlb;
}
@@ -360,7 +360,7 @@ static int get_mmu_address(SuperHCPU *cpu, target_ulong *physical,
} else {
n = find_utlb_entry(cpu, address, use_asid);
if (n >= 0) {
- n = copy_utlb_entry_itlb(&cpu->env, n);
+ n = copy_utlb_entry_itlb(cpu, n);
matching = &cpu->env.itlb[n];
if (!(cpu->env.sr & SR_MD) && !(matching->pr & 2)) {
n = MMU_ITLB_VIOLATION;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() take SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (8 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() " Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU Andreas Färber
` (2 subsequent siblings)
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/helper.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index ffe79ec..c5c0593 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -202,7 +202,7 @@ void do_interrupt(CPUSH4State * env)
}
}
-static void update_itlb_use(CPUSH4State * env, int itlbnb)
+static void update_itlb_use(SuperHCPU *cpu, int itlbnb)
{
uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
@@ -223,8 +223,8 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
break;
}
- env->mmucr &= (and_mask << 24) | 0x00ffffff;
- env->mmucr |= (or_mask << 24);
+ cpu->env.mmucr &= (and_mask << 24) | 0x00ffffff;
+ cpu->env.mmucr |= (or_mask << 24);
}
static int itlb_replacement(CPUSH4State * env)
@@ -297,7 +297,7 @@ static int copy_utlb_entry_itlb(SuperHCPU *cpu, int utlb)
tlb_flush_page(&cpu->env, ientry->vpn << 10);
}
*ientry = cpu->env.utlb[utlb];
- update_itlb_use(&cpu->env, itlb);
+ update_itlb_use(cpu, itlb);
return itlb;
}
@@ -315,7 +315,7 @@ static int find_itlb_entry(SuperHCPU *cpu, target_ulong address,
} else if (e == MMU_DTLB_MISS) {
e = MMU_ITLB_MISS;
} else if (e >= 0) {
- update_itlb_use(&cpu->env, e);
+ update_itlb_use(cpu, e);
}
return e;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (9 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() " Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC Andreas Färber
2012-03-14 16:06 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Aurelien Jarno
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-sh4/helper.c | 18 +++++++++++-------
1 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index c5c0593..c291eee 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -227,17 +227,21 @@ static void update_itlb_use(SuperHCPU *cpu, int itlbnb)
cpu->env.mmucr |= (or_mask << 24);
}
-static int itlb_replacement(CPUSH4State * env)
+static int itlb_replacement(SuperHCPU *cpu)
{
- if ((env->mmucr & 0xe0000000) == 0xe0000000)
+ if ((cpu->env.mmucr & 0xe0000000) == 0xe0000000) {
return 0;
- if ((env->mmucr & 0x98000000) == 0x18000000)
+ }
+ if ((cpu->env.mmucr & 0x98000000) == 0x18000000) {
return 1;
- if ((env->mmucr & 0x54000000) == 0x04000000)
+ }
+ if ((cpu->env.mmucr & 0x54000000) == 0x04000000) {
return 2;
- if ((env->mmucr & 0x2c000000) == 0x00000000)
+ }
+ if ((cpu->env.mmucr & 0x2c000000) == 0x00000000) {
return 3;
- cpu_abort(env, "Unhandled itlb_replacement");
+ }
+ cpu_abort(&cpu->env, "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
@@ -291,7 +295,7 @@ static int copy_utlb_entry_itlb(SuperHCPU *cpu, int utlb)
int itlb;
tlb_t * ientry;
- itlb = itlb_replacement(&cpu->env);
+ itlb = itlb_replacement(cpu);
ientry = &cpu->env.itlb[itlb];
if (ientry->v) {
tlb_flush_page(&cpu->env, ientry->vpn << 10);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (10 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU Andreas Färber
@ 2012-03-14 16:01 ` Andreas Färber
2012-03-14 16:06 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
12 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 16:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
For now derive directly from Object. Move CPU-independent initialization
to an initfn. Add a "cpu" link<superh-cpu> property and move
CPU-dependent init code to sh7750_realize().
Update SHIX and R2D boards accordingly. Add the CPU as /cpu so that it
can be set as link target, and add the SoC as /sh7750 to inspect it.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/r2d.c | 9 ++++++++-
hw/sh.h | 6 ++++--
hw/sh7750.c | 43 +++++++++++++++++++++++++++++++++++--------
hw/shix.c | 8 +++++++-
4 files changed, 54 insertions(+), 12 deletions(-)
diff --git a/hw/r2d.c b/hw/r2d.c
index c55de01..509bc69 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -224,6 +224,7 @@ static void r2d_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
+ SuperHCPU *cpu;
CPUSH4State *env;
ResetData *reset_info;
struct SH7750State *s;
@@ -243,6 +244,9 @@ static void r2d_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
+ cpu = sh_env_get_cpu(env);
+ object_property_add_child(object_get_root(), "cpu", OBJECT(cpu), NULL);
+
reset_info = g_malloc0(sizeof(ResetData));
reset_info->env = env;
reset_info->vector = env->pc;
@@ -253,7 +257,10 @@ static void r2d_init(ram_addr_t ram_size,
vmstate_register_ram_global(sdram);
memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
/* Register peripherals */
- s = sh7750_init(env, address_space_mem);
+ s = SH7750(object_new(TYPE_SH7750));
+ object_property_add_child(object_get_root(), "sh7750", OBJECT(s), NULL);
+ object_property_set_link(OBJECT(s), OBJECT(cpu), "cpu", NULL);
+ sh7750_realize(s);
irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
dev = qdev_create(NULL, "sh_pci");
diff --git a/hw/sh.h b/hw/sh.h
index 40df18c..b39881e 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -8,10 +8,12 @@
#define P4ADDR(x) ((x) | 0xe0000000)
/* sh7750.c */
-struct SH7750State;
+#define TYPE_SH7750 "sh7750-soc"
+#define SH7750(obj) OBJECT_CHECK(SH7750State, (obj), TYPE_SH7750)
+typedef struct SH7750State SH7750State;
struct MemoryRegion;
-struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *sysmem);
+void sh7750_realize(SH7750State *s);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
diff --git a/hw/sh7750.c b/hw/sh7750.c
index c3cea9f..80c63fa 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -35,6 +35,10 @@
#define NB_DEVICES 4
typedef struct SH7750State {
+ /*< private >*/
+ Object parent_obj;
+ /*< public >*/
+
MemoryRegion iomem;
MemoryRegion iomem_1f0;
MemoryRegion iomem_ff0;
@@ -720,13 +724,16 @@ static const MemoryRegionOps sh7750_mmct_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
+static void sh7750_initfn(Object *obj)
{
- SH7750State *s;
+ SH7750State *s = SH7750(obj);
+ MemoryRegion *sysmem = get_system_memory();
+
+ object_property_add_link(obj, "cpu", TYPE_SUPERH_CPU,
+ (Object **)&s->cpu, NULL);
+
+ s->periph_freq = 60000000; /* 60MHz */
- s = g_malloc0(sizeof(SH7750State));
- s->cpu = sh_env_get_cpu(cpu);
- s->periph_freq = 60000000; /* 60MHz */
memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
"memory", 0x1fc01000);
@@ -766,8 +773,6 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
_INTC_ARRAY(vectors),
_INTC_ARRAY(groups));
- cpu->intc_handle = &s->intc;
-
sh_serial_init(sysmem, 0x1fe00000,
0, s->periph_freq, serial_hds[0],
s->intc.irqs[SCI1_ERI],
@@ -791,6 +796,14 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
s->intc.irqs[TMU1],
s->intc.irqs[TMU2_TUNI],
s->intc.irqs[TMU2_TICPI]);
+}
+
+void sh7750_realize(SH7750State *s)
+{
+ MemoryRegion *sysmem = get_system_memory();
+ CPUSH4State *cpu = &s->cpu->env;
+
+ cpu->intc_handle = &s->intc;
if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc,
@@ -829,7 +842,6 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irl),
_INTC_ARRAY(groups_irl));
- return s;
}
qemu_irq sh7750_irl(SH7750State *s)
@@ -838,3 +850,18 @@ qemu_irq sh7750_irl(SH7750State *s)
return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
1)[0];
}
+
+static const TypeInfo sh7750_info = {
+ .name = TYPE_SH7750,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(SH7750State),
+ .instance_init = sh7750_initfn,
+ .class_size = sizeof(ObjectClass),
+};
+
+static void sh7750_register_types(void)
+{
+ type_register_static(&sh7750_info);
+}
+
+type_init(sh7750_register_types)
diff --git a/hw/shix.c b/hw/shix.c
index dd9ce17..66c749a 100644
--- a/hw/shix.c
+++ b/hw/shix.c
@@ -43,6 +43,7 @@ static void shix_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
int ret;
+ SuperHCPU *cpu;
CPUSH4State *env;
struct SH7750State *s;
MemoryRegion *sysmem = get_system_memory();
@@ -54,6 +55,8 @@ static void shix_init(ram_addr_t ram_size,
printf("Initializing CPU\n");
env = cpu_init(cpu_model);
+ cpu = sh_env_get_cpu(env);
+ object_property_add_child(object_get_root(), "cpu", OBJECT(cpu), NULL);
/* Allocate memory space */
printf("Allocating ROM\n");
@@ -83,7 +86,10 @@ static void shix_init(ram_addr_t ram_size,
}
/* Register peripherals */
- s = sh7750_init(env, sysmem);
+ s = SH7750(object_new(TYPE_SH7750));
+ object_property_add_child(object_get_root(), "sh7750", OBJECT(s), NULL);
+ object_property_set_link(OBJECT(s), OBJECT(cpu), "cpu", NULL);
+ sh7750_realize(s);
/* XXXXX Check success */
tc58128_init(s, "shix_linux_nand.bin", NULL);
fprintf(stderr, "initialization terminated\n");
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
` (11 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC Andreas Färber
@ 2012-03-14 16:06 ` Peter Maydell
2012-03-14 18:25 ` Andreas Färber
12 siblings, 1 reply; 175+ messages in thread
From: Peter Maydell @ 2012-03-14 16:06 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Aurélien Jarno
On 14 March 2012 16:01, Andreas Färber <afaerber@suse.de> wrote:
> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
> the SuperH CPU to QOM.
>
> The SH7750 SoC code invited to do some cleanups, making use of the SuperHCPU,
> so I've QOM'ified the SoC and added the CPU as a link<SuperHCPU> for now.
>
> I'm not so happy about the link construct, so it may need to be redone
> as a SysBus device with qdev properties
Shouldn't the CPU be a child of the SoC, not a link?
>- long-term I'd like to have a
> "system-on-chip" type derived from TYPE_DEVICE. Deriving it from
> TYPE_SYS_BUS_DEVICE might make for a better v2.
I think TYPE_SYS_BUS_DEVICE should go away in favour of everything
being a TYPE_DEVICE.
What do you think a "system-on-chip" type would be needed for?
I would have expected that SoCs would basically just be "containers"
of devices and directly be TYPE_DEVICEs...
-- PMM
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
` (7 preceding siblings ...)
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
` (11 more replies)
8 siblings, 12 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel
Cc: Liu Jinsong, Jan Kiszka, Peter A. G. Crosthwaite, Max Filippov,
Edgar E. Iglesias, Khansa Butt, Jia Liu, Alexander Graf,
qemu-ppc, John Williams, Eduardo Habkost, Paul Brook,
Anthony Liguori, Richard Henderson, Blue Swirl, Lai Jiangshan,
Vasilis Liaskovitis, Michael Walle, Igor Mammedov, Meador Inge,
Andreas Färber, Aurélien Jarno
Hello,
Based on qom-cpu v4 and object_class_get_list() v2, this series converts
the remaining CPUs to QOM. Their only intersection point is Makefile.target.
TODO: Review LGPLv2.1 text differences (bug in German GNU webpage).
TODO: Check that cpu_model_str is set correctly everywhere.
target-i386:
Eduardo Habkost has already pointed out that it might be better to use
QOM properties for -cpudef in target-i386, so that we use the same code paths
internally as QMP users or machine compatibility code would.
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Liu Jinsong <jinsong.liu@intel.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Vasilis Liaskovitis <vasilis.liaskovitis@profitbricks.com>
(Sorry if I forget someone.)
target-ppc:
As already discussed with Alex, I didn't manage to split out the QOM PowerPCCPU
into cpu.c from translate.c #including translate_init.c within a reasonable time,
so this becomes an exception in Makefile.target in the follow-up series.
The initfn/uninitfn can be simplified in v2 by putting them in powerpc_cpu_info.
Cc: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc <qemu-ppc@nongnu.org>
target-xtensa:
Xtensa was problematic in that it used declarative definitions for XtensaConfig
whose macros I did not manage to convert to an imperative class_init with
reasonable effort. I therefore resorted to a really ugly memcpy(), better ideas
or follow-up patches welcome!
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Anthony Liguori <anthony@codemonkey.ws>
target-mips:
Note that MIPSCPU conflicts with an in-flight FPU reset fix from Khansa and Mentor
and with ASE DSP series by Jia Liu.
Cc: Khansa Butt <khansa@kics.edu.pk>
Cc: Meador Inge <meadori@codesourcery.com>
Cc: Jia Liu <proljc@gmail.com>
Cc: Aurélien Jarno <aurelien@aurel32.net>
Most conversions were pretty straightforward. Pattern was always:
* Add a new cpu-qom.h header to entangle QOM data and cpu.h #defines
* Add a new cpu.c file implement FooCPU, FooCPUClass
* If available, move list of CPU models into FooCPUInfo cpus[] in cpu.c
* Embed CPUFooState as member of FooCPU
* Define ENV_GET_OBJECT(env) macro
* Make cpu-qom.h globally available through cpu.h (for now)
* Move cpu_foo_init() code into foo_cpu_initfn()
* Change cpu_foo_init() to use object_new() with a CPU type
=> Some parts remain that might be moved into initfn in follow-ups.
* Move cpu_foo_reset() code into foo_cpu_reset()
* Let cpu_foo_reset() just call cpu_reset()
* If implemented, change cpu_foo_list_cpu() to get, sort, print GSList of FooCPUClass
=> This may change the sometimes arbitrary order in user-visible -cpu ? output.
* If any, fix cpu.h vs. cpu-qom.h circular dependency issues through static inline helpers
Available at:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu-others.v1
Regards,
Andreas
target-alpha:
Cc: Richard Henderson <rth@twiddle.net>
target-cris:
target-microblaze:
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Cc: John Williams <john.williams@petalogix.com>
target-lm32:
Cc: Michael Walle <michael@walle.cc>
target-m68k:
Cc: Paul Brook <paul@codesourcery.com>
target-s390x:
Cc: Alexander Graf <agraf@suse.de>
Cc: Ulrich Hecht <uli@suse.de>
target-sparc:
Cc: Blue Swirl <blauwirbel@gmail.com>
Andreas Färber (12):
target-s390x: QOM'ify CPU
target-mips: QOM'ify CPU
target-m68k: QOM'ify CPU
target-alpha: QOM'ify CPU
target-i386: QOM'ify CPU
target-ppc: QOM'ify CPU
target-ppc: Prepare finalizer for PowerPCCPU
target-cris: QOM'ify CPU
target-lm32: QOM'ify CPU
target-microblaze: QOM'ify CPU
target-sparc: QOM'ify CPU
target-xtensa: QOM'ify CPU
Makefile.target | 14 +-
gdbstub.c | 19 +-
hw/xtensa_pic.c | 51 +-
target-alpha/cpu-qom.h | 74 ++
target-alpha/cpu.c | 127 ++++
target-alpha/cpu.h | 1 +
target-alpha/translate.c | 60 +--
target-cris/cpu-qom.h | 73 ++
target-cris/cpu.c | 144 ++++
target-cris/cpu.h | 2 +
target-cris/translate.c | 93 ++--
target-i386/cpu-qom.h | 87 +++
target-i386/cpu.c | 1598 +++++++++++++++++++++++++++++++++++++++++
target-i386/cpu.h | 6 +-
target-i386/cpuid.c | 1369 -----------------------------------
target-i386/helper.c | 101 +---
target-lm32/cpu-qom.h | 77 ++
target-lm32/cpu.c | 188 +++++
target-lm32/cpu.h | 1 +
target-lm32/helper.c | 142 +---
target-m68k/cpu-qom.h | 75 ++
target-m68k/cpu.c | 161 +++++
target-m68k/cpu.h | 1 +
target-m68k/helper.c | 158 ++---
target-microblaze/cpu-qom.h | 71 ++
target-microblaze/cpu.c | 120 +++
target-microblaze/cpu.h | 2 +
target-microblaze/translate.c | 58 +--
target-mips/cpu-qom.h | 110 +++
target-mips/cpu.c | 806 +++++++++++++++++++++
target-mips/cpu.h | 2 +-
target-mips/translate.c | 183 ++----
target-mips/translate_init.c | 594 ---------------
target-ppc/cpu-qom.h | 84 +++
target-ppc/cpu.h | 26 +-
target-ppc/helper.c | 73 +--
target-ppc/kvm.c | 30 +-
target-ppc/kvm_ppc.h | 6 -
target-ppc/translate.c | 2 +-
target-ppc/translate_init.c | 270 ++++++-
target-s390x/cpu-qom.h | 71 ++
target-s390x/cpu.c | 96 +++
target-s390x/cpu.h | 5 +
target-s390x/helper.c | 42 +-
target-sparc/cpu-qom.h | 95 +++
target-sparc/cpu.c | 949 ++++++++++++++++++++++++
target-sparc/cpu.h | 29 +-
target-sparc/cpu_init.c | 848 ----------------------
target-sparc/int32_helper.c | 5 +-
target-sparc/ldst_helper.c | 19 +-
target-sparc/mmu_helper.c | 4 +-
target-sparc/translate.c | 4 +-
target-sparc/win_helper.c | 3 +-
target-xtensa/core-dc232b.c | 5 +-
target-xtensa/core-fsf.c | 5 +-
target-xtensa/cpu-qom.h | 186 +++++
target-xtensa/cpu.c | 87 +++
target-xtensa/cpu.h | 125 +---
target-xtensa/helper.c | 151 +++--
target-xtensa/op_helper.c | 104 ++-
target-xtensa/overlay_tool.h | 28 +-
target-xtensa/translate.c | 9 +-
62 files changed, 6059 insertions(+), 3870 deletions(-)
create mode 100644 target-alpha/cpu-qom.h
create mode 100644 target-alpha/cpu.c
create mode 100644 target-cris/cpu-qom.h
create mode 100644 target-cris/cpu.c
create mode 100644 target-i386/cpu-qom.h
create mode 100644 target-i386/cpu.c
delete mode 100644 target-i386/cpuid.c
create mode 100644 target-lm32/cpu-qom.h
create mode 100644 target-lm32/cpu.c
create mode 100644 target-m68k/cpu-qom.h
create mode 100644 target-m68k/cpu.c
create mode 100644 target-microblaze/cpu-qom.h
create mode 100644 target-microblaze/cpu.c
create mode 100644 target-mips/cpu-qom.h
create mode 100644 target-mips/cpu.c
delete mode 100644 target-mips/translate_init.c
create mode 100644 target-ppc/cpu-qom.h
create mode 100644 target-s390x/cpu-qom.h
create mode 100644 target-s390x/cpu.c
create mode 100644 target-sparc/cpu-qom.h
create mode 100644 target-sparc/cpu.c
delete mode 100644 target-sparc/cpu_init.c
create mode 100644 target-xtensa/cpu-qom.h
create mode 100644 target-xtensa/cpu.c
--
1.7.7
^ permalink raw reply [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
` (10 subsequent siblings)
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Alexander Graf
S/390 ignored -cpu, so there's only one S390CPUClass for now.
Let cpu_s390x_init() instantiate it.
Embed CPUS390XState into S390CPU. Keep s390x_{tod,cpu}_timer() in
helper.c but pass the S390CPU to them. Let cpu_state_reset() call
cpu_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Ulrich Hecht <uli@suse.de>
---
Makefile.target | 1 +
target-s390x/cpu-qom.h | 71 +++++++++++++++++++++++++++++++++++
target-s390x/cpu.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++
target-s390x/cpu.h | 5 ++
target-s390x/helper.c | 42 ++++++---------------
5 files changed, 185 insertions(+), 30 deletions(-)
create mode 100644 target-s390x/cpu-qom.h
create mode 100644 target-s390x/cpu.c
diff --git a/Makefile.target b/Makefile.target
index c48a849..737c1e5 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -88,6 +88,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ARM) += cpu.o
+libobj-$(TARGET_S390X) += cpu.o
libobj-$(TARGET_SH4) += cpu.o
ifeq ($(TARGET_BASE_ARCH), sparc)
libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h
new file mode 100644
index 0000000..6482969
--- /dev/null
+++ b/target-s390x/cpu-qom.h
@@ -0,0 +1,71 @@
+/*
+ * QEMU S/390 CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_S390_CPU_QOM_H
+#define QEMU_S390_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_S390_CPU "s390-cpu"
+
+#define S390_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(S390CPUClass, (klass), TYPE_S390_CPU)
+#define S390_CPU(obj) \
+ OBJECT_CHECK(S390CPU, (obj), TYPE_S390_CPU)
+#define S390_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(S390CPUClass, (obj), TYPE_S390_CPU)
+
+/**
+ * S390CPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An S/390 CPU model.
+ */
+typedef struct S390CPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+} S390CPUClass;
+
+/**
+ * S390CPU:
+ * @env: Legacy CPU state.
+ *
+ * An S/390 CPU.
+ */
+typedef struct S390CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUS390XState env;
+} S390CPU;
+
+static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
+{
+ return S390_CPU(container_of(env, S390CPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
+
+
+#endif
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
new file mode 100644
index 0000000..b0d5726
--- /dev/null
+++ b/target-s390x/cpu.c
@@ -0,0 +1,96 @@
+/*
+ * QEMU S/390 CPU
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * Copyright (c) 2011 Alexander Graf
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+#include "qemu-timer.h"
+
+
+static void s390_cpu_reset(CPUState *c)
+{
+ S390CPU *cpu = S390_CPU(c);
+ S390CPUClass *klass = S390_CPU_GET_CLASS(c);
+ CPUS390XState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUS390XState, breakpoints));
+ /* FIXME: reset vector? */
+ tlb_flush(env, 1);
+ s390_add_running_cpu(env);
+}
+
+static void s390_cpu_initfn(Object *obj)
+{
+ S390CPU *cpu = S390_CPU(obj);
+ CPUS390XState *env = &cpu->env;
+#if !defined(CONFIG_USER_ONLY)
+ struct tm tm;
+#endif
+ static int cpu_num;
+
+ memset(&cpu->env, 0, sizeof(CPUS390XState));
+ cpu_exec_init(env);
+
+#if !defined(CONFIG_USER_ONLY)
+ qemu_get_timedate(&tm, 0);
+ env->tod_offset = TOD_UNIX_EPOCH +
+ (time2tod(mktimegm(&tm)) * 1000000000ULL);
+ env->tod_basetime = 0;
+ env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, cpu);
+ env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, cpu);
+#endif
+ env->cpu_num = cpu_num++;
+ env->ext_index = -1;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void s390_cpu_class_init(ObjectClass *klass, void *data)
+{
+ S390CPUClass *k = S390_CPU_CLASS(klass);
+ CPUClass *cpu_class = CPU_CLASS(klass);
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = s390_cpu_reset;
+}
+
+static const TypeInfo s390_cpu_info = {
+ .name = TYPE_S390_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(S390CPU),
+ .instance_init = s390_cpu_initfn,
+ .class_size = sizeof(S390CPUClass),
+ .class_init = s390_cpu_class_init,
+};
+
+static void s390_cpu_register_types(void)
+{
+ type_register_static(&s390_cpu_info);
+}
+
+type_init(s390_cpu_register_types)
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index ea849fc..2f3f394 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -288,6 +288,9 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw
#ifndef CONFIG_USER_ONLY
+void s390x_tod_timer(void *opaque);
+void s390x_cpu_timer(void *opaque);
+
int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall);
#ifdef CONFIG_KVM
@@ -991,4 +994,6 @@ static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
env->psw.addr = tb->pc;
}
+#include "cpu-qom.h"
+
#endif
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 44d5048..0068b2b 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -24,6 +24,7 @@
#ifndef CONFIG_USER_ONLY
#include "sysemu.h"
#endif
+#include "cpu-qom.h"
//#define DEBUG_S390
//#define DEBUG_S390_PTE
@@ -51,17 +52,19 @@
#endif
#ifndef CONFIG_USER_ONLY
-static void s390x_tod_timer(void *opaque)
+void s390x_tod_timer(void *opaque)
{
- CPUS390XState *env = opaque;
+ S390CPU *cpu = opaque;
+ CPUS390XState *env = &cpu->env;
env->pending_int |= INTERRUPT_TOD;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
-static void s390x_cpu_timer(void *opaque)
+void s390x_cpu_timer(void *opaque)
{
- CPUS390XState *env = opaque;
+ S390CPU *cpu = opaque;
+ CPUS390XState *env = &cpu->env;
env->pending_int |= INTERRUPT_CPUTIMER;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
@@ -70,32 +73,19 @@ static void s390x_cpu_timer(void *opaque)
CPUS390XState *cpu_s390x_init(const char *cpu_model)
{
+ S390CPU *cpu;
CPUS390XState *env;
-#if !defined (CONFIG_USER_ONLY)
- struct tm tm;
-#endif
static int inited = 0;
- static int cpu_num = 0;
- env = g_malloc0(sizeof(CPUS390XState));
- cpu_exec_init(env);
+ cpu = S390_CPU(object_new(TYPE_S390_CPU));
+ env = &cpu->env;
+
if (tcg_enabled() && !inited) {
inited = 1;
s390x_translate_init();
}
-#if !defined(CONFIG_USER_ONLY)
- qemu_get_timedate(&tm, 0);
- env->tod_offset = TOD_UNIX_EPOCH +
- (time2tod(mktimegm(&tm)) * 1000000000ULL);
- env->tod_basetime = 0;
- env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, env);
- env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, env);
-#endif
env->cpu_model_str = cpu_model;
- env->cpu_num = cpu_num++;
- env->ext_index = -1;
- cpu_state_reset(env);
qemu_init_vcpu(env);
return env;
}
@@ -121,15 +111,7 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw
void cpu_state_reset(CPUS390XState *env)
{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- memset(env, 0, offsetof(CPUS390XState, breakpoints));
- /* FIXME: reset vector? */
- tlb_flush(env, 1);
- s390_add_running_cpu(env);
+ cpu_reset(ENV_GET_CPU(env));
}
#ifndef CONFIG_USER_ONLY
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 02/12] target-mips: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 03/12] target-m68k: " Andreas Färber
` (9 subsequent siblings)
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel
Cc: Meador Inge, Jia Liu, Stefan Weil, Hervé Poussineau,
Khansa Butt, Andreas Färber, Aurelien Jarno
MIPS was very close to QOM in referencing a CPU definition from
CPUMIPSState. Turn those structs into classes. This moves most of
translate_init.c into cpu.c; move the remainder into translate.c
so that we no longer #include "translate_init.c" there.
Embed CPUMIPSState into MIPSCPU. Let cpu_state_reset() call cpu_reset().
Let mips_cpu_list() enumerate available CPU classes in alphabetical
order.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Stefan Weil <sw@weilnetz.de>
Cc: Khansa Butt <khansa@kics.edu.pk>
Cc: Meador Inge <meadori@codesourcery.com>
Cc: Jia Liu <proljc@gmail.com>
---
Makefile.target | 3 +
target-mips/cpu-qom.h | 110 ++++++
target-mips/cpu.c | 806 ++++++++++++++++++++++++++++++++++++++++++
target-mips/cpu.h | 2 +-
target-mips/translate.c | 183 +++-------
target-mips/translate_init.c | 594 -------------------------------
6 files changed, 965 insertions(+), 733 deletions(-)
create mode 100644 target-mips/cpu-qom.h
create mode 100644 target-mips/cpu.c
delete mode 100644 target-mips/translate_init.c
diff --git a/Makefile.target b/Makefile.target
index 737c1e5..878807b 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -88,6 +88,9 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ARM) += cpu.o
+ifeq ($(TARGET_BASE_ARCH), mips)
+libobj-y += cpu.o
+endif
libobj-$(TARGET_S390X) += cpu.o
libobj-$(TARGET_SH4) += cpu.o
ifeq ($(TARGET_BASE_ARCH), sparc)
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h
new file mode 100644
index 0000000..3af1b9e
--- /dev/null
+++ b/target-mips/cpu-qom.h
@@ -0,0 +1,110 @@
+/*
+ * QEMU MIPS CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_MIPS_CPU_QOM_H
+#define QEMU_MIPS_CPU_QOM_H
+
+#include "qemu-common.h"
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_MIPS_CPU "mips-cpu"
+
+/**
+ * MIPSMMUTypes:
+ *
+ * MMU types, the first four entries have the same layout as the
+ * CP0C0_MT field.
+ */
+enum MIPSMMUTypes {
+ MMU_TYPE_NONE,
+ MMU_TYPE_R4000,
+ MMU_TYPE_RESERVED,
+ MMU_TYPE_FMT,
+ MMU_TYPE_R3000,
+ MMU_TYPE_R6000,
+ MMU_TYPE_R8000
+};
+
+#define MIPS_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
+#define MIPS_CPU(obj) \
+ OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
+#define MIPS_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)
+
+/**
+ * MIPSCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A MIPS CPU model.
+ */
+typedef struct MIPSCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ int32_t cp0_prid;
+ int32_t cp0_config0;
+ int32_t cp0_config1;
+ int32_t cp0_config2;
+ int32_t cp0_config3;
+ int32_t cp0_config6;
+ int32_t cp0_config7;
+ target_ulong cp0_lladdr_rw_bitmask;
+ int cp0_lladdr_shift;
+ int32_t synci_step;
+ int32_t ccres;
+ int32_t cp0_status_rw_bitmask;
+ int32_t cp0_tcstatus_rw_bitmask;
+ int32_t cp0_srsctl;
+ int32_t cp1_fcr0;
+ int32_t segbits;
+ int32_t pabits;
+ int32_t cp0_srsconf_rw_bitmask[5];
+ int32_t cp0_srsconf[5];
+ int insn_flags;
+ enum MIPSMMUTypes mmu_type;
+} MIPSCPUClass;
+
+/**
+ * MIPSCPU:
+ * @env: Legacy CPU state.
+ *
+ * A MIPS CPU.
+ */
+typedef struct MIPSCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUMIPSState env;
+} MIPSCPU;
+
+static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
+{
+ return MIPS_CPU(container_of(env, MIPSCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
+
+
+#endif
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
new file mode 100644
index 0000000..f692134
--- /dev/null
+++ b/target-mips/cpu.c
@@ -0,0 +1,806 @@
+/*
+ * QEMU MIPS CPU
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2007 Herve Poussineau
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+#ifndef CONFIG_USER_ONLY
+static void no_mmu_init(MIPSCPU *cpu)
+{
+ CPUMIPSState *env = &cpu->env;
+
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &no_mmu_map_address;
+}
+
+static void fixed_mmu_init(MIPSCPU *cpu)
+{
+ CPUMIPSState *env = &cpu->env;
+
+ env->tlb->nb_tlb = 1;
+ env->tlb->map_address = &fixed_mmu_map_address;
+}
+
+static void r4k_mmu_init(MIPSCPU *cpu)
+{
+ MIPSCPUClass *cpu_class = MIPS_CPU_GET_CLASS(cpu);
+ CPUMIPSState *env = &cpu->env;
+
+ env->tlb->nb_tlb = 1 + ((cpu_class->cp0_config1 >> CP0C1_MMU) & 63);
+ env->tlb->map_address = &r4k_map_address;
+ env->tlb->helper_tlbwi = r4k_helper_tlbwi;
+ env->tlb->helper_tlbwr = r4k_helper_tlbwr;
+ env->tlb->helper_tlbp = r4k_helper_tlbp;
+ env->tlb->helper_tlbr = r4k_helper_tlbr;
+}
+
+static void mmu_init(MIPSCPU *cpu)
+{
+ MIPSCPUClass *cpu_class = MIPS_CPU_GET_CLASS(cpu);
+ CPUMIPSState *env = &cpu->env;
+
+ env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
+
+ switch (cpu_class->mmu_type) {
+ case MMU_TYPE_NONE:
+ no_mmu_init(cpu);
+ break;
+ case MMU_TYPE_R4000:
+ r4k_mmu_init(cpu);
+ break;
+ case MMU_TYPE_FMT:
+ fixed_mmu_init(cpu);
+ break;
+ case MMU_TYPE_R3000:
+ case MMU_TYPE_R6000:
+ case MMU_TYPE_R8000:
+ default:
+ cpu_abort(env, "MMU type not supported\n");
+ }
+}
+#endif /* CONFIG_USER_ONLY */
+
+static void fpu_init(MIPSCPU *cpu)
+{
+ MIPSCPUClass *cpu_class = MIPS_CPU_GET_CLASS(cpu);
+ CPUMIPSState *env = &cpu->env;
+ int i;
+
+ for (i = 0; i < MIPS_FPU_MAX; i++) {
+ env->fpus[i].fcr0 = cpu_class->cp1_fcr0;
+ }
+
+ memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
+}
+
+static void mvp_init(MIPSCPU *cpu)
+{
+ CPUMIPSState *env = &cpu->env;
+ env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
+
+ /* MVPConf1 implemented, TLB sharable, no gating storage support,
+ programmable cache partitioning implemented, number of allocatable
+ and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+ implemented, 5 TCs implemented. */
+ env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+ (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+/* TODO: actually do 2 VPEs.
+ * (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
+ * (0x04 << CP0MVPC0_PTC);
+ */
+ (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+ (0x00 << CP0MVPC0_PTC);
+#if !defined(CONFIG_USER_ONLY)
+ /* Usermode has no TLB support */
+ env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+#endif
+
+ /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
+ no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
+ env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+ (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
+ (0x1 << CP0MVPC1_PCP1);
+}
+
+static void mips_cpu_reset(CPUState *c)
+{
+ MIPSCPU *cpu = MIPS_CPU(c);
+ MIPSCPUClass *cpu_class = MIPS_CPU_GET_CLASS(cpu);
+ CPUMIPSState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ cpu_class->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUMIPSState, breakpoints));
+ tlb_flush(env, 1);
+
+ /* Reset registers to their default values */
+ env->CP0_PRid = cpu_class->cp0_prid;
+ env->CP0_Config0 = cpu_class->cp0_config0;
+#ifdef TARGET_WORDS_BIGENDIAN
+ env->CP0_Config0 |= (1 << CP0C0_BE);
+#endif
+ env->CP0_Config1 = cpu_class->cp0_config1;
+ env->CP0_Config2 = cpu_class->cp0_config2;
+ env->CP0_Config3 = cpu_class->cp0_config3;
+ env->CP0_Config6 = cpu_class->cp0_config6;
+ env->CP0_Config7 = cpu_class->cp0_config7;
+ env->CP0_LLAddr_rw_bitmask = cpu_class->cp0_lladdr_rw_bitmask
+ << cpu_class->cp0_lladdr_shift;
+ env->CP0_LLAddr_shift = cpu_class->cp0_lladdr_shift;
+ env->SYNCI_Step = cpu_class->synci_step;
+ env->CCRes = cpu_class->ccres;
+ env->CP0_Status_rw_bitmask = cpu_class->cp0_status_rw_bitmask;
+ env->CP0_TCStatus_rw_bitmask = cpu_class->cp0_tcstatus_rw_bitmask;
+ env->CP0_SRSCtl = cpu_class->cp0_srsctl;
+ env->current_tc = 0;
+ env->SEGBITS = cpu_class->segbits;
+ env->SEGMask = (target_ulong)((1ULL << cpu_class->segbits) - 1);
+#if defined(TARGET_MIPS64)
+ if (cpu_class->insn_flags & ISA_MIPS3) {
+ env->SEGMask |= 3ULL << 62;
+ }
+#endif
+ env->PABITS = cpu_class->pabits;
+ env->PAMask = (target_ulong)((1ULL << cpu_class->pabits) - 1);
+ env->CP0_SRSConf0_rw_bitmask = cpu_class->cp0_srsconf_rw_bitmask[0];
+ env->CP0_SRSConf0 = cpu_class->cp0_srsconf[0];
+ env->CP0_SRSConf1_rw_bitmask = cpu_class->cp0_srsconf_rw_bitmask[1];
+ env->CP0_SRSConf1 = cpu_class->cp0_srsconf[1];
+ env->CP0_SRSConf2_rw_bitmask = cpu_class->cp0_srsconf_rw_bitmask[2];
+ env->CP0_SRSConf2 = cpu_class->cp0_srsconf[2];
+ env->CP0_SRSConf3_rw_bitmask = cpu_class->cp0_srsconf_rw_bitmask[3];
+ env->CP0_SRSConf3 = cpu_class->cp0_srsconf[3];
+ env->CP0_SRSConf4_rw_bitmask = cpu_class->cp0_srsconf_rw_bitmask[4];
+ env->CP0_SRSConf4 = cpu_class->cp0_srsconf[4];
+ env->insn_flags = cpu_class->insn_flags;
+
+#if defined(CONFIG_USER_ONLY)
+ env->hflags = MIPS_HFLAG_UM;
+ /* Enable access to the SYNCI_Step register. */
+ env->CP0_HWREna |= (1 << 1);
+ if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+ env->hflags |= MIPS_HFLAG_FPU;
+ }
+#ifdef TARGET_MIPS64
+ if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
+ env->hflags |= MIPS_HFLAG_F64;
+ }
+#endif
+#else
+ if (env->hflags & MIPS_HFLAG_BMASK) {
+ /* If the exception was raised from a delay slot,
+ come back to the jump. */
+ env->CP0_ErrorEPC = env->active_tc.PC - 4;
+ } else {
+ env->CP0_ErrorEPC = env->active_tc.PC;
+ }
+ env->active_tc.PC = (int32_t)0xBFC00000;
+ env->CP0_Random = env->tlb->nb_tlb - 1;
+ env->tlb->tlb_in_use = env->tlb->nb_tlb;
+ env->CP0_Wired = 0;
+ env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
+ env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
+ /* vectored interrupts not implemented, timer on int 7,
+ no performance counters. */
+ env->CP0_IntCtl = 0xe0000000;
+ {
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ env->CP0_WatchLo[i] = 0;
+ env->CP0_WatchHi[i] = 0x80000000;
+ }
+ env->CP0_WatchLo[7] = 0;
+ env->CP0_WatchHi[7] = 0;
+ }
+ /* Count register increments in debug mode, EJTAG version 1 */
+ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
+ env->hflags = MIPS_HFLAG_CP0;
+
+ if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ int i;
+
+ /* Only TC0 on VPE 0 starts as active. */
+ for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
+ env->tcs[i].CP0_TCBind = env->cpu_index << CP0TCBd_CurVPE;
+ env->tcs[i].CP0_TCHalt = 1;
+ }
+ env->active_tc.CP0_TCHalt = 1;
+ env->halted = 1;
+
+ if (!env->cpu_index) {
+ /* VPE0 starts up enabled. */
+ env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
+
+ /* TC0 starts up unhalted. */
+ env->halted = 0;
+ env->active_tc.CP0_TCHalt = 0;
+ env->tcs[0].CP0_TCHalt = 0;
+ /* With thread 0 active. */
+ env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
+ env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
+ }
+ }
+#endif
+#if defined(TARGET_MIPS64)
+ if (cpu_class->insn_flags & ISA_MIPS3) {
+ env->hflags |= MIPS_HFLAG_64;
+ }
+#endif
+ env->exception_index = EXCP_NONE;
+}
+
+/* CPU / CPU family specific config register values. */
+
+/* Have config1, uncached coherency */
+#define MIPS_CONFIG0 \
+ ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
+
+/* Have config2, no coprocessor2 attached, no MDMX support attached,
+ no performance counters, watch registers present,
+ no code compression, EJTAG present, no FPU */
+#define MIPS_CONFIG1 \
+((1 << CP0C1_M) | \
+ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
+ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
+ (0 << CP0C1_FP))
+
+/* Have config3, no tertiary/secondary caches implemented */
+#define MIPS_CONFIG2 \
+((1 << CP0C2_M))
+
+/* No config4, no DSP ASE, no large physaddr (PABITS),
+ no external interrupt controller, no vectored interrupts,
+ no 1kb pages, no SmartMIPS ASE, no trace logic */
+#define MIPS_CONFIG3 \
+((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
+ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
+ (0 << CP0C3_SM) | (0 << CP0C3_TL))
+
+typedef struct MIPSCPUInfo {
+ const char *name;
+ int32_t CP0_PRid;
+ int32_t CP0_Config0;
+ int32_t CP0_Config1;
+ int32_t CP0_Config2;
+ int32_t CP0_Config3;
+ int32_t CP0_Config6;
+ int32_t CP0_Config7;
+ target_ulong CP0_LLAddr_rw_bitmask;
+ int CP0_LLAddr_shift;
+ int32_t SYNCI_Step;
+ int32_t CCRes;
+ int32_t CP0_Status_rw_bitmask;
+ int32_t CP0_TCStatus_rw_bitmask;
+ int32_t CP0_SRSCtl;
+ int32_t CP1_fcr0;
+ int32_t SEGBITS;
+ int32_t PABITS;
+ int32_t CP0_SRSConf0_rw_bitmask;
+ int32_t CP0_SRSConf0;
+ int32_t CP0_SRSConf1_rw_bitmask;
+ int32_t CP0_SRSConf1;
+ int32_t CP0_SRSConf2_rw_bitmask;
+ int32_t CP0_SRSConf2;
+ int32_t CP0_SRSConf3_rw_bitmask;
+ int32_t CP0_SRSConf3;
+ int32_t CP0_SRSConf4_rw_bitmask;
+ int32_t CP0_SRSConf4;
+ int insn_flags;
+ enum MIPSMMUTypes mmu_type;
+} MIPSCPUInfo;
+
+/*****************************************************************************/
+/* MIPS CPU definitions */
+static const MIPSCPUInfo mips_cpus[] = {
+ {
+ .name = "4Kc",
+ .CP0_PRid = 0x00018000,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "4Km",
+ .CP0_PRid = 0x00018300,
+ /* Config1 implemented, fixed mapping MMU,
+ no virtual icache, uncached coherency. */
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "4KEcR1",
+ .CP0_PRid = 0x00018400,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "4KEmR1",
+ .CP0_PRid = 0x00018500,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "4KEc",
+ .CP0_PRid = 0x00019000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "4KEm",
+ .CP0_PRid = 0x00019100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
+ .name = "24Kc",
+ .CP0_PRid = 0x00019300,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x1278FF1F,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "24Kf",
+ .CP0_PRid = 0x00019300,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x3678FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "34Kf",
+ .CP0_PRid = 0x00019500,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x3678FF1F,
+ /* No DSP implemented. */
+ .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
+ (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
+ (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
+ (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
+ (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
+ (0xff << CP0TCSt_TASID),
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
+ .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
+ .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
+ (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
+ .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
+ (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
+ .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
+ (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
+ .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
+ (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
+ .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
+ .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
+ (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+#if defined(TARGET_MIPS64)
+ {
+ .name = "R4000",
+ .CP0_PRid = 0x00000400,
+ /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
+ .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
+ /* Note: Config1 is only used internally, the R4000 has only Config0. */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3678FFFF,
+ /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 40,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS3,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "VR5432",
+ .CP0_PRid = 0x00005400,
+ /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
+ .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3678FFFF,
+ /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 40,
+ .PABITS = 32,
+ .insn_flags = CPU_VR54XX,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "5Kc",
+ .CP0_PRid = 0x00018100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x32F8FFFF,
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "5Kf",
+ .CP0_PRid = 0x00018100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x36F8FFFF,
+ /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 42,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "20Kc",
+ /* We emulate a later version of the 20Kc, earlier ones had a broken
+ WAIT instruction. */
+ .CP0_PRid = 0x000182a0,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 1,
+ .CP0_Status_rw_bitmask = 0x36FBFFFF,
+ /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
+ .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
+ (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 40,
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ /* A generic CPU providing MIPS64 Release 2 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "MIPS64R2-generic",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x36FBFFFF,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .SEGBITS = 42,
+ /* The architectural limit is 59, but we have hardcoded 36 bit
+ in some places...
+ .PABITS = 59, */ /* the architectural limit */
+ .PABITS = 36,
+ .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-2E",
+ .CP0_PRid = 0x6302,
+ /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
+ .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
+ (0x1<<4) | (0x1<<1),
+ /* Note: Config1 is only used internally,
+ Loongson-2E has only Config0. */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x35D0FFFF,
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+ .SEGBITS = 40,
+ .PABITS = 40,
+ .insn_flags = CPU_LOONGSON2E,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-2F",
+ .CP0_PRid = 0x6303,
+ /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
+ .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
+ (0x1<<4) | (0x1<<1),
+ /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+ .SEGBITS = 40,
+ .PABITS = 40,
+ .insn_flags = CPU_LOONGSON2F,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+
+#endif
+};
+
+static void mips_cpu_initfn(Object *obj)
+{
+ MIPSCPU *cpu = MIPS_CPU(obj);
+ CPUMIPSState *env = &cpu->env;
+
+ memset(env, 0, sizeof(CPUMIPSState));
+ env->cpu_model_str = object_get_typename(obj);
+ cpu_exec_init(env);
+
+#ifndef CONFIG_USER_ONLY
+ mmu_init(cpu);
+#endif
+ fpu_init(cpu);
+ mvp_init(cpu);
+ CPU_CLASS(MIPS_CPU_GET_CLASS(cpu))->reset(CPU(cpu));
+}
+
+static void mips_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ MIPSCPUClass *k = MIPS_CPU_CLASS(klass);
+ const MIPSCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = mips_cpu_reset;
+
+ k->cp0_prid = info->CP0_PRid;
+ k->cp0_config0 = info->CP0_Config0;
+ k->cp0_config1 = info->CP0_Config1;
+ k->cp0_config2 = info->CP0_Config2;
+ k->cp0_config3 = info->CP0_Config3;
+ k->cp0_config6 = info->CP0_Config6;
+ k->cp0_config7 = info->CP0_Config7;
+ k->cp0_lladdr_rw_bitmask = info->CP0_LLAddr_rw_bitmask;
+ k->cp0_lladdr_shift = info->CP0_LLAddr_shift;
+ k->synci_step = info->SYNCI_Step;
+ k->ccres = info->CCRes;
+ k->cp0_status_rw_bitmask = info->CP0_Status_rw_bitmask;
+ k->cp0_tcstatus_rw_bitmask = info->CP0_TCStatus_rw_bitmask;
+ k->cp0_srsctl = info->CP0_SRSCtl;
+ k->cp1_fcr0 = info->CP1_fcr0;
+ k->segbits = info->SEGBITS;
+ k->pabits = info->PABITS;
+ k->cp0_srsconf_rw_bitmask[0] = info->CP0_SRSConf0_rw_bitmask;
+ k->cp0_srsconf_rw_bitmask[1] = info->CP0_SRSConf1_rw_bitmask;
+ k->cp0_srsconf_rw_bitmask[2] = info->CP0_SRSConf2_rw_bitmask;
+ k->cp0_srsconf_rw_bitmask[3] = info->CP0_SRSConf3_rw_bitmask;
+ k->cp0_srsconf_rw_bitmask[4] = info->CP0_SRSConf4_rw_bitmask;
+ k->cp0_srsconf[0] = info->CP0_SRSConf0;
+ k->cp0_srsconf[1] = info->CP0_SRSConf1;
+ k->cp0_srsconf[2] = info->CP0_SRSConf2;
+ k->cp0_srsconf[3] = info->CP0_SRSConf3;
+ k->cp0_srsconf[4] = info->CP0_SRSConf4;
+ k->insn_flags = info->insn_flags;
+ k->mmu_type = info->mmu_type;
+}
+
+static void mips_register_cpu(const MIPSCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_MIPS_CPU,
+ .instance_size = sizeof(MIPSCPU),
+ .instance_init = mips_cpu_initfn,
+ .class_size = sizeof(MIPSCPUClass),
+ .class_init = mips_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo mips_cpu_info = {
+ .name = TYPE_MIPS_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(MIPSCPU),
+ .abstract = true,
+ .class_size = sizeof(MIPSCPUClass),
+};
+
+static void mips_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&mips_cpu_info);
+ for (i = 0; i < ARRAY_SIZE(mips_cpus); i++) {
+ mips_register_cpu(&mips_cpus[i]);
+ }
+}
+
+type_init(mips_cpu_register_types)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7430aa5..12e9d6f 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -478,7 +478,6 @@ struct CPUMIPSState {
CPUMIPSTLBContext *tlb;
#endif
- const mips_def_t *cpu_model;
void *irq[8];
struct QEMUTimer *timer; /* Internal timer */
};
@@ -729,6 +728,7 @@ static inline int cpu_has_work(CPUMIPSState *env)
}
#include "exec-all.h"
+#include "cpu-qom.h"
static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
{
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a663b74..db0ebda 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4,6 +4,7 @@
* Copyright (c) 2004-2005 Jocelyn Mayer
* Copyright (c) 2006 Marius Groeger (FPU operations)
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2007 Hervé Poussineau
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
*
* This library is free software; you can redistribute it and/or
@@ -12687,158 +12688,64 @@ static void mips_tcg_init(void)
inited = 1;
}
-#include "translate_init.c"
+struct MIPSCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+};
-CPUMIPSState *cpu_mips_init (const char *cpu_model)
+/* Sort alphabetically. */
+static gint mips_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- CPUMIPSState *env;
- const mips_def_t *def;
-
- def = cpu_mips_find_by_name(cpu_model);
- if (!def)
- return NULL;
- env = g_malloc0(sizeof(CPUMIPSState));
- env->cpu_model = def;
- env->cpu_model_str = cpu_model;
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
- cpu_exec_init(env);
-#ifndef CONFIG_USER_ONLY
- mmu_init(env, def);
-#endif
- fpu_init(env, def);
- mvp_init(env, def);
- mips_tcg_init();
- cpu_state_reset(env);
- qemu_init_vcpu(env);
- return env;
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
}
-void cpu_state_reset(CPUMIPSState *env)
+static void mips_cpu_list_entry(gpointer data, gpointer user_data)
{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
+ ObjectClass *klass = data;
+ struct MIPSCPUListState *s = user_data;
- memset(env, 0, offsetof(CPUMIPSState, breakpoints));
- tlb_flush(env, 1);
+ (*s->cpu_fprintf)(s->file, "MIPS '%s'\n",
+ object_class_get_name(klass));
+}
- /* Reset registers to their default values */
- env->CP0_PRid = env->cpu_model->CP0_PRid;
- env->CP0_Config0 = env->cpu_model->CP0_Config0;
-#ifdef TARGET_WORDS_BIGENDIAN
- env->CP0_Config0 |= (1 << CP0C0_BE);
-#endif
- env->CP0_Config1 = env->cpu_model->CP0_Config1;
- env->CP0_Config2 = env->cpu_model->CP0_Config2;
- env->CP0_Config3 = env->cpu_model->CP0_Config3;
- env->CP0_Config6 = env->cpu_model->CP0_Config6;
- env->CP0_Config7 = env->cpu_model->CP0_Config7;
- env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
- << env->cpu_model->CP0_LLAddr_shift;
- env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
- env->SYNCI_Step = env->cpu_model->SYNCI_Step;
- env->CCRes = env->cpu_model->CCRes;
- env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
- env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
- env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
- env->current_tc = 0;
- env->SEGBITS = env->cpu_model->SEGBITS;
- env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
-#if defined(TARGET_MIPS64)
- if (env->cpu_model->insn_flags & ISA_MIPS3) {
- env->SEGMask |= 3ULL << 62;
- }
-#endif
- env->PABITS = env->cpu_model->PABITS;
- env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1);
- env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
- env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
- env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
- env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
- env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
- env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
- env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
- env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
- env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
- env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
- env->insn_flags = env->cpu_model->insn_flags;
+void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ struct MIPSCPUListState s = {
+ .cpu_fprintf = cpu_fprintf,
+ .file = f,
+ };
+ GSList *list;
-#if defined(CONFIG_USER_ONLY)
- env->hflags = MIPS_HFLAG_UM;
- /* Enable access to the SYNCI_Step register. */
- env->CP0_HWREna |= (1 << 1);
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- env->hflags |= MIPS_HFLAG_FPU;
- }
-#ifdef TARGET_MIPS64
- if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
- env->hflags |= MIPS_HFLAG_F64;
- }
-#endif
-#else
- if (env->hflags & MIPS_HFLAG_BMASK) {
- /* If the exception was raised from a delay slot,
- come back to the jump. */
- env->CP0_ErrorEPC = env->active_tc.PC - 4;
- } else {
- env->CP0_ErrorEPC = env->active_tc.PC;
- }
- env->active_tc.PC = (int32_t)0xBFC00000;
- env->CP0_Random = env->tlb->nb_tlb - 1;
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
- env->CP0_Wired = 0;
- env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
- env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
- /* vectored interrupts not implemented, timer on int 7,
- no performance counters. */
- env->CP0_IntCtl = 0xe0000000;
- {
- int i;
+ list = object_class_get_list(TYPE_MIPS_CPU, false);
+ list = g_slist_sort(list, mips_cpu_list_compare);
+ g_slist_foreach(list, mips_cpu_list_entry, &s);
+ g_slist_free(list);
+}
- for (i = 0; i < 7; i++) {
- env->CP0_WatchLo[i] = 0;
- env->CP0_WatchHi[i] = 0x80000000;
- }
- env->CP0_WatchLo[7] = 0;
- env->CP0_WatchHi[7] = 0;
- }
- /* Count register increments in debug mode, EJTAG version 1 */
- env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
- env->hflags = MIPS_HFLAG_CP0;
+CPUMIPSState *cpu_mips_init(const char *cpu_model)
+{
+ MIPSCPU *cpu;
+ CPUMIPSState *env;
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
- int i;
+ if (object_class_by_name(cpu_model) == NULL) {
+ return NULL;
+ }
+ cpu = MIPS_CPU(object_new(cpu_model));
+ env = &cpu->env;
- /* Only TC0 on VPE 0 starts as active. */
- for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
- env->tcs[i].CP0_TCBind = env->cpu_index << CP0TCBd_CurVPE;
- env->tcs[i].CP0_TCHalt = 1;
- }
- env->active_tc.CP0_TCHalt = 1;
- env->halted = 1;
+ mips_tcg_init();
- if (!env->cpu_index) {
- /* VPE0 starts up enabled. */
- env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
+ qemu_init_vcpu(env);
+ return env;
+}
- /* TC0 starts up unhalted. */
- env->halted = 0;
- env->active_tc.CP0_TCHalt = 0;
- env->tcs[0].CP0_TCHalt = 0;
- /* With thread 0 active. */
- env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
- env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
- }
- }
-#endif
-#if defined(TARGET_MIPS64)
- if (env->cpu_model->insn_flags & ISA_MIPS3) {
- env->hflags |= MIPS_HFLAG_64;
- }
-#endif
- env->exception_index = EXCP_NONE;
+void cpu_state_reset(CPUMIPSState *env)
+{
+ cpu_reset(ENV_GET_CPU(env));
}
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
deleted file mode 100644
index c39138f..0000000
--- a/target-mips/translate_init.c
+++ /dev/null
@@ -1,594 +0,0 @@
-/*
- * MIPS emulation for qemu: CPU initialisation routines.
- *
- * Copyright (c) 2004-2005 Jocelyn Mayer
- * Copyright (c) 2007 Herve Poussineau
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/* CPU / CPU family specific config register values. */
-
-/* Have config1, uncached coherency */
-#define MIPS_CONFIG0 \
- ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
-
-/* Have config2, no coprocessor2 attached, no MDMX support attached,
- no performance counters, watch registers present,
- no code compression, EJTAG present, no FPU */
-#define MIPS_CONFIG1 \
-((1 << CP0C1_M) | \
- (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
- (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
- (0 << CP0C1_FP))
-
-/* Have config3, no tertiary/secondary caches implemented */
-#define MIPS_CONFIG2 \
-((1 << CP0C2_M))
-
-/* No config4, no DSP ASE, no large physaddr (PABITS),
- no external interrupt controller, no vectored interrupts,
- no 1kb pages, no SmartMIPS ASE, no trace logic */
-#define MIPS_CONFIG3 \
-((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
- (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
- (0 << CP0C3_SM) | (0 << CP0C3_TL))
-
-/* MMU types, the first four entries have the same layout as the
- CP0C0_MT field. */
-enum mips_mmu_types {
- MMU_TYPE_NONE,
- MMU_TYPE_R4000,
- MMU_TYPE_RESERVED,
- MMU_TYPE_FMT,
- MMU_TYPE_R3000,
- MMU_TYPE_R6000,
- MMU_TYPE_R8000
-};
-
-struct mips_def_t {
- const char *name;
- int32_t CP0_PRid;
- int32_t CP0_Config0;
- int32_t CP0_Config1;
- int32_t CP0_Config2;
- int32_t CP0_Config3;
- int32_t CP0_Config6;
- int32_t CP0_Config7;
- target_ulong CP0_LLAddr_rw_bitmask;
- int CP0_LLAddr_shift;
- int32_t SYNCI_Step;
- int32_t CCRes;
- int32_t CP0_Status_rw_bitmask;
- int32_t CP0_TCStatus_rw_bitmask;
- int32_t CP0_SRSCtl;
- int32_t CP1_fcr0;
- int32_t SEGBITS;
- int32_t PABITS;
- int32_t CP0_SRSConf0_rw_bitmask;
- int32_t CP0_SRSConf0;
- int32_t CP0_SRSConf1_rw_bitmask;
- int32_t CP0_SRSConf1;
- int32_t CP0_SRSConf2_rw_bitmask;
- int32_t CP0_SRSConf2;
- int32_t CP0_SRSConf3_rw_bitmask;
- int32_t CP0_SRSConf3;
- int32_t CP0_SRSConf4_rw_bitmask;
- int32_t CP0_SRSConf4;
- int insn_flags;
- enum mips_mmu_types mmu_type;
-};
-
-/*****************************************************************************/
-/* MIPS CPU definitions */
-static const mips_def_t mips_defs[] =
-{
- {
- .name = "4Kc",
- .CP0_PRid = 0x00018000,
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (0 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "4Km",
- .CP0_PRid = 0x00018300,
- /* Config1 implemented, fixed mapping MMU,
- no virtual icache, uncached coherency. */
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "4KEcR1",
- .CP0_PRid = 0x00018400,
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (0 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "4KEmR1",
- .CP0_PRid = 0x00018500,
- .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "4KEc",
- .CP0_PRid = 0x00019000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (0 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1278FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "4KEm",
- .CP0_PRid = 0x00019100,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_FMT << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x1258FF17,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_FMT,
- },
- {
- .name = "24Kc",
- .CP0_PRid = 0x00019300,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- /* No DSP implemented. */
- .CP0_Status_rw_bitmask = 0x1278FF1F,
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "24Kf",
- .CP0_PRid = 0x00019300,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- /* No DSP implemented. */
- .CP0_Status_rw_bitmask = 0x3678FF1F,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "34Kf",
- .CP0_PRid = 0x00019500,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
- (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
- (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_CA),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- /* No DSP implemented. */
- .CP0_Status_rw_bitmask = 0x3678FF1F,
- /* No DSP implemented. */
- .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
- (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
- (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
- (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
- (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
- (0xff << CP0TCSt_TASID),
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
- (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
- .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
- .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
- (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
- .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
- (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
- .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
- (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
- .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
- (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
- .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
- .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
- (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
- .SEGBITS = 32,
- .PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
- .mmu_type = MMU_TYPE_R4000,
- },
-#if defined(TARGET_MIPS64)
- {
- .name = "R4000",
- .CP0_PRid = 0x00000400,
- /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
- /* Note: Config1 is only used internally, the R4000 has only Config0. */
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3678FFFF,
- /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
- .SEGBITS = 40,
- .PABITS = 36,
- .insn_flags = CPU_MIPS3,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "VR5432",
- .CP0_PRid = 0x00005400,
- /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
- .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x3678FFFF,
- /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
- .SEGBITS = 40,
- .PABITS = 32,
- .insn_flags = CPU_VR54XX,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "5Kc",
- .CP0_PRid = 0x00018100,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
- (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
- (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x32F8FFFF,
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "5Kf",
- .CP0_PRid = 0x00018100,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
- (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
- (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 4,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x36F8FFFF,
- /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
- (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
- .SEGBITS = 42,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "20Kc",
- /* We emulate a later version of the 20Kc, earlier ones had a broken
- WAIT instruction. */
- .CP0_PRid = 0x000182a0,
- .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3,
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 1,
- .CP0_Status_rw_bitmask = 0x36FBFFFF,
- /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
- .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
- (1 << FCR0_D) | (1 << FCR0_S) |
- (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
- .SEGBITS = 40,
- .PABITS = 36,
- .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- /* A generic CPU providing MIPS64 Release 2 features.
- FIXME: Eventually this should be replaced by a real CPU model. */
- .name = "MIPS64R2-generic",
- .CP0_PRid = 0x00010000,
- .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
- (MMU_TYPE_R4000 << CP0C0_MT),
- .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
- (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
- (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
- (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
- .CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
- .CP0_LLAddr_rw_bitmask = 0,
- .CP0_LLAddr_shift = 0,
- .SYNCI_Step = 32,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x36FBFFFF,
- .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
- (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
- (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
- .SEGBITS = 42,
- /* The architectural limit is 59, but we have hardcoded 36 bit
- in some places...
- .PABITS = 59, */ /* the architectural limit */
- .PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "Loongson-2E",
- .CP0_PRid = 0x6302,
- /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
- (0x1<<4) | (0x1<<1),
- /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0x35D0FFFF,
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
- .SEGBITS = 40,
- .PABITS = 40,
- .insn_flags = CPU_LOONGSON2E,
- .mmu_type = MMU_TYPE_R4000,
- },
- {
- .name = "Loongson-2F",
- .CP0_PRid = 0x6303,
- /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
- .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
- (0x1<<4) | (0x1<<1),
- /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
- .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
- .SYNCI_Step = 16,
- .CCRes = 2,
- .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
- .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
- .SEGBITS = 40,
- .PABITS = 40,
- .insn_flags = CPU_LOONGSON2F,
- .mmu_type = MMU_TYPE_R4000,
- },
-
-#endif
-};
-
-static const mips_def_t *cpu_mips_find_by_name (const char *name)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
- if (strcasecmp(name, mips_defs[i].name) == 0) {
- return &mips_defs[i];
- }
- }
- return NULL;
-}
-
-void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
- (*cpu_fprintf)(f, "MIPS '%s'\n",
- mips_defs[i].name);
- }
-}
-
-#ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &no_mmu_map_address;
-}
-
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &fixed_mmu_map_address;
-}
-
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
- env->tlb->map_address = &r4k_map_address;
- env->tlb->helper_tlbwi = r4k_helper_tlbwi;
- env->tlb->helper_tlbwr = r4k_helper_tlbwr;
- env->tlb->helper_tlbp = r4k_helper_tlbp;
- env->tlb->helper_tlbr = r4k_helper_tlbr;
-}
-
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
- switch (def->mmu_type) {
- case MMU_TYPE_NONE:
- no_mmu_init(env, def);
- break;
- case MMU_TYPE_R4000:
- r4k_mmu_init(env, def);
- break;
- case MMU_TYPE_FMT:
- fixed_mmu_init(env, def);
- break;
- case MMU_TYPE_R3000:
- case MMU_TYPE_R6000:
- case MMU_TYPE_R8000:
- default:
- cpu_abort(env, "MMU type not supported\n");
- }
-}
-#endif /* CONFIG_USER_ONLY */
-
-static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
-{
- int i;
-
- for (i = 0; i < MIPS_FPU_MAX; i++)
- env->fpus[i].fcr0 = def->CP1_fcr0;
-
- memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
-}
-
-static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
-{
- env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
- /* MVPConf1 implemented, TLB sharable, no gating storage support,
- programmable cache partitioning implemented, number of allocatable
- and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
- implemented, 5 TCs implemented. */
- env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
- (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
-// TODO: actually do 2 VPEs.
-// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
-// (0x04 << CP0MVPC0_PTC);
- (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
- (0x00 << CP0MVPC0_PTC);
-#if !defined(CONFIG_USER_ONLY)
- /* Usermode has no TLB support */
- env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
-#endif
-
- /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
- no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
- env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
- (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
- (0x1 << CP0MVPC1_PCP1);
-}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 03/12] target-m68k: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
` (8 subsequent siblings)
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Paul Brook
Embed CPUM68KState in M68kCPU. Let cpu_state_reset() call cpu_reset().
Let m68k_cpu_list() enumerate CPU classes alphabetically, except for
"any".
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-m68k/cpu-qom.h | 75 +++++++++++++++++++++++
target-m68k/cpu.c | 161 +++++++++++++++++++++++++++++++++++++++++++++++++
target-m68k/cpu.h | 1 +
target-m68k/helper.c | 158 ++++++++++++++++--------------------------------
5 files changed, 289 insertions(+), 107 deletions(-)
create mode 100644 target-m68k/cpu-qom.h
create mode 100644 target-m68k/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 878807b..47854a7 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -88,6 +88,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ARM) += cpu.o
+libobj-$(TARGET_M68K) += cpu.o
ifeq ($(TARGET_BASE_ARCH), mips)
libobj-y += cpu.o
endif
diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h
new file mode 100644
index 0000000..f115ab0
--- /dev/null
+++ b/target-m68k/cpu-qom.h
@@ -0,0 +1,75 @@
+/*
+ * QEMU Motorola 68k CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_M68K_CPU_QOM_H
+#define QEMU_M68K_CPU_QOM_H
+
+#include "qemu-common.h"
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_M68K_CPU "m68k-cpu"
+
+#define M68K_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(M68kCPUClass, (klass), TYPE_M68K_CPU)
+#define M68K_CPU(obj) \
+ OBJECT_CHECK(M68kCPU, (obj), TYPE_M68K_CPU)
+#define M68K_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(M68kCPUClass, (obj), TYPE_M68K_CPU)
+
+/**
+ * M68kCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ * @features: CPU feature flags.
+ *
+ * A Motorola 68k CPU model.
+ */
+typedef struct M68kCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t features;
+} M68kCPUClass;
+
+/**
+ * M68kCPU:
+ * @env: Legacy CPU state.
+ *
+ * A Motorola 68k CPU.
+ */
+typedef struct M68kCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUM68KState env;
+} M68kCPU;
+
+static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
+{
+ return M68K_CPU(container_of(env, M68kCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
+
+
+#endif
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
new file mode 100644
index 0000000..66d7564
--- /dev/null
+++ b/target-m68k/cpu.c
@@ -0,0 +1,161 @@
+/*
+ * QEMU Motorola 68k CPU
+ *
+ * Copyright (c) 2006-2007 CodeSourcery
+ * Written by Paul Brook
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void m68k_cpu_reset(CPUState *c)
+{
+ M68kCPU *cpu = M68K_CPU(c);
+ M68kCPUClass *klass = M68K_CPU_GET_CLASS(cpu);
+ CPUM68KState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUM68KState, breakpoints));
+#if !defined(CONFIG_USER_ONLY)
+ env->sr = 0x2700;
+#endif
+ m68k_switch_sp(env);
+ /* ??? FP regs should be initialized to NaN. */
+ env->cc_op = CC_OP_FLAGS;
+ /* TODO: We should set PC from the interrupt vector. */
+ env->pc = 0;
+ tlb_flush(env, 1);
+}
+
+/* CPU models */
+
+typedef struct M68kCPUInfo {
+ const char *name;
+ uint32_t features;
+} M68kCPUInfo;
+
+#define M68K_FEATURE(feature) (1u << M68K_FEATURE_ ## feature)
+
+static const M68kCPUInfo m68k_cpus[] = {
+ {
+ .name = "m5206",
+ .features = M68K_FEATURE(CF_ISA_A),
+ },
+ {
+ .name = "m5208",
+ .features = M68K_FEATURE(CF_ISA_A) |
+ M68K_FEATURE(CF_ISA_APLUSC) |
+ M68K_FEATURE(BRAL) |
+ M68K_FEATURE(CF_EMAC) |
+ M68K_FEATURE(USP),
+ },
+ {
+ .name = "cfv4e",
+ .features = M68K_FEATURE(CF_ISA_A) |
+ M68K_FEATURE(CF_ISA_B) |
+ M68K_FEATURE(BRAL) |
+ M68K_FEATURE(CF_FPU) |
+ M68K_FEATURE(CF_EMAC) |
+ M68K_FEATURE(USP),
+ },
+ {
+ .name = "any",
+ .features = M68K_FEATURE(CF_ISA_A) |
+ M68K_FEATURE(CF_ISA_APLUSC) |
+ M68K_FEATURE(CF_ISA_B) |
+ M68K_FEATURE(BRAL) |
+ M68K_FEATURE(CF_FPU) |
+ /* MAC and EMAC are mututally exclusive, so pick EMAC.
+ It's mostly backwards compatible. */
+ M68K_FEATURE(CF_EMAC) |
+ M68K_FEATURE(CF_EMAC_B) |
+ M68K_FEATURE(USP) |
+ M68K_FEATURE(EXT_FULL) |
+ M68K_FEATURE(WORD_INDEX),
+ },
+};
+
+
+static void m68k_cpu_initfn(Object *obj)
+{
+ M68kCPU *cpu = M68K_CPU(obj);
+ M68kCPUClass *klass = M68K_CPU_GET_CLASS(cpu);
+ CPUM68KState *env = &cpu->env;
+
+ memset(env, 0, sizeof(CPUM68KState));
+ cpu_exec_init(env);
+
+ env->cpu_model_str = object_get_typename(obj);
+ env->features = klass->features;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void m68k_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ M68kCPUClass *k = M68K_CPU_CLASS(klass);
+ const M68kCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = m68k_cpu_reset;
+
+ k->features = info->features;
+}
+
+static void cpu_register(const M68kCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_M68K_CPU,
+ .instance_size = sizeof(M68kCPU),
+ .instance_init = m68k_cpu_initfn,
+ .class_size = sizeof(M68kCPUClass),
+ .class_init = m68k_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo m68k_cpu_type_info = {
+ .name = TYPE_M68K_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(M68kCPU),
+ .abstract = true,
+ .class_size = sizeof(M68kCPUClass),
+};
+
+static void m68k_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&m68k_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(m68k_cpus); i++) {
+ cpu_register(&m68k_cpus[i]);
+ }
+}
+
+type_init(m68k_cpu_register_types)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 6696e30..77db787 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -245,6 +245,7 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp)
#endif
#include "cpu-all.h"
+#include "cpu-qom.h"
static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 1feed9b..b5f51dd 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -25,35 +25,50 @@
#define SIGNBIT (1u << 31)
-enum m68k_cpuid {
- M68K_CPUID_M5206,
- M68K_CPUID_M5208,
- M68K_CPUID_CFV4E,
- M68K_CPUID_ANY,
-};
+typedef struct M68kCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} M68kCPUListState;
-typedef struct m68k_def_t m68k_def_t;
+/* Sort alphabetically, except for "any". */
+static gint m68k_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
+
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ if (strcmp(name_a, "any") == 0) {
+ return 1;
+ } else if (strcmp(name_b, "any") == 0) {
+ return -1;
+ } else {
+ return strcasecmp(name_a, name_b);
+ }
+}
-struct m68k_def_t {
- const char * name;
- enum m68k_cpuid id;
-};
+static void m68k_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *klass = data;
+ M68kCPUListState *s = user_data;
-static m68k_def_t m68k_cpu_defs[] = {
- {"m5206", M68K_CPUID_M5206},
- {"m5208", M68K_CPUID_M5208},
- {"cfv4e", M68K_CPUID_CFV4E},
- {"any", M68K_CPUID_ANY},
- {NULL, 0},
-};
+ (*s->cpu_fprintf)(s->file, "%s\n",
+ object_class_get_name(klass));
+}
void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
- unsigned int i;
+ M68kCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
- for (i = 0; m68k_cpu_defs[i].name; i++) {
- (*cpu_fprintf)(f, "%s\n", m68k_cpu_defs[i].name);
- }
+ list = object_class_get_list(TYPE_M68K_CPU, false);
+ list = g_slist_sort(list, m68k_cpu_list_compare);
+ g_slist_foreach(list, m68k_cpu_list_entry, &s);
+ g_slist_free(list);
}
static int fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
@@ -83,112 +98,41 @@ static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
return 0;
}
-static void m68k_set_feature(CPUM68KState *env, int feature)
-{
- env->features |= (1u << feature);
-}
-
-static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
-{
- m68k_def_t *def;
-
- for (def = m68k_cpu_defs; def->name; def++) {
- if (strcmp(def->name, name) == 0)
- break;
- }
- if (!def->name)
- return -1;
-
- switch (def->id) {
- case M68K_CPUID_M5206:
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
- break;
- case M68K_CPUID_M5208:
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
- m68k_set_feature(env, M68K_FEATURE_BRAL);
- m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
- m68k_set_feature(env, M68K_FEATURE_USP);
- break;
- case M68K_CPUID_CFV4E:
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
- m68k_set_feature(env, M68K_FEATURE_BRAL);
- m68k_set_feature(env, M68K_FEATURE_CF_FPU);
- m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
- m68k_set_feature(env, M68K_FEATURE_USP);
- break;
- case M68K_CPUID_ANY:
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
- m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
- m68k_set_feature(env, M68K_FEATURE_BRAL);
- m68k_set_feature(env, M68K_FEATURE_CF_FPU);
- /* MAC and EMAC are mututally exclusive, so pick EMAC.
- It's mostly backwards compatible. */
- m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
- m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B);
- m68k_set_feature(env, M68K_FEATURE_USP);
- m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
- m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
- break;
- }
-
- register_m68k_insns(env);
- if (m68k_feature (env, M68K_FEATURE_CF_FPU)) {
- gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg,
- 11, "cf-fp.xml", 18);
- }
- /* TODO: Add [E]MAC registers. */
- return 0;
-}
-
void cpu_state_reset(CPUM68KState *env)
{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- memset(env, 0, offsetof(CPUM68KState, breakpoints));
-#if !defined (CONFIG_USER_ONLY)
- env->sr = 0x2700;
-#endif
- m68k_switch_sp(env);
- /* ??? FP regs should be initialized to NaN. */
- env->cc_op = CC_OP_FLAGS;
- /* TODO: We should set PC from the interrupt vector. */
- env->pc = 0;
- tlb_flush(env, 1);
+ cpu_reset(ENV_GET_CPU(env));
}
CPUM68KState *cpu_m68k_init(const char *cpu_model)
{
+ M68kCPU *cpu;
CPUM68KState *env;
static int inited;
- env = g_malloc0(sizeof(CPUM68KState));
- cpu_exec_init(env);
+ if (object_class_by_name(cpu_model) == NULL) {
+ return NULL;
+ }
+ cpu = M68K_CPU(object_new(cpu_model));
+ env = &cpu->env;
+
if (!inited) {
inited = 1;
m68k_tcg_init();
}
-
- env->cpu_model_str = cpu_model;
-
- if (cpu_m68k_set_model(env, cpu_model) < 0) {
- cpu_m68k_close(env);
- return NULL;
+ register_m68k_insns(env);
+ if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
+ gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg,
+ 11, "cf-fp.xml", 18);
}
+ /* TODO: Add [E]MAC registers. */
- cpu_state_reset(env);
qemu_init_vcpu(env);
return env;
}
void cpu_m68k_close(CPUM68KState *env)
{
- g_free(env);
+ object_delete(OBJECT(m68k_env_get_cpu(env)));
}
void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 04/12] target-alpha: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (2 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] [RFC 03/12] target-m68k: " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:59 ` Richard Henderson
2012-03-14 17:53 ` [Qemu-devel] [RFC 05/12] target-i386: " Andreas Färber
` (7 subsequent siblings)
11 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Richard Henderson
Embed CPUAlphaState in AlphaCPU.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-alpha/cpu-qom.h | 74 +++++++++++++++++++++++++++
target-alpha/cpu.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++
target-alpha/cpu.h | 1 +
target-alpha/translate.c | 60 +++-------------------
5 files changed, 211 insertions(+), 52 deletions(-)
create mode 100644 target-alpha/cpu-qom.h
create mode 100644 target-alpha/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 47854a7..74604fd 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -87,6 +87,7 @@ endif
libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
+libobj-$(TARGET_ALPHA) += cpu.o
libobj-$(TARGET_ARM) += cpu.o
libobj-$(TARGET_M68K) += cpu.o
ifeq ($(TARGET_BASE_ARCH), mips)
diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h
new file mode 100644
index 0000000..889d05c
--- /dev/null
+++ b/target-alpha/cpu-qom.h
@@ -0,0 +1,74 @@
+/*
+ * QEMU Alpha CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_ALPHA_CPU_QOM_H
+#define QEMU_ALPHA_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_ALPHA_CPU "alpha-cpu"
+
+#define ALPHA_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AlphaCPUClass, (klass), TYPE_ALPHA_CPU)
+#define ALPHA_CPU(obj) \
+ OBJECT_CHECK(AlphaCPU, (obj), TYPE_ALPHA_CPU)
+#define ALPHA_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AlphaCPUClass, (obj), TYPE_ALPHA_CPU)
+
+/**
+ * AlphaCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An Alpha CPU model.
+ */
+typedef struct AlphaCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ int implver;
+ int amask;
+} AlphaCPUClass;
+
+/**
+ * AlphaCPU:
+ * @env: Legacy CPU state.
+ *
+ * An Alpha CPU.
+ */
+typedef struct AlphaCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUAlphaState env;
+} AlphaCPU;
+
+static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
+{
+ return ALPHA_CPU(container_of(env, AlphaCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e))
+
+
+#endif
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
new file mode 100644
index 0000000..f5c037f
--- /dev/null
+++ b/target-alpha/cpu.c
@@ -0,0 +1,127 @@
+/*
+ * QEMU Alpha CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void alpha_cpu_reset(CPUState *c)
+{
+ AlphaCPU *cpu = ALPHA_CPU(c);
+ AlphaCPUClass *klass = ALPHA_CPU_GET_CLASS(cpu);
+
+ klass->parent_reset(c);
+}
+
+/* CPU models */
+
+typedef struct AlphaCPUInfo {
+ const char *name;
+ int implver, amask;
+} AlphaCPUInfo;
+
+static const AlphaCPUInfo alpha_cpus[] = {
+ { "ev4", IMPLVER_2106x, 0 },
+ { "ev5", IMPLVER_21164, 0 },
+ { "ev56", IMPLVER_21164, AMASK_BWX },
+ { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
+ { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
+ { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
+ | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
+ { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
+ | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
+ { "21064", IMPLVER_2106x, 0 },
+ { "21164", IMPLVER_21164, 0 },
+ { "21164a", IMPLVER_21164, AMASK_BWX },
+ { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
+ { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
+ { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
+ | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }
+};
+
+static void alpha_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ AlphaCPUClass *klass = ALPHA_CPU_GET_CLASS(cpu);
+ CPUAlphaState *env = &cpu->env;
+
+ env->implver = klass->implver;
+ env->amask = klass->amask;
+
+ memset(env, 0, sizeof(CPUAlphaState));
+ cpu_exec_init(env);
+ tlb_flush(env, 1);
+
+#if defined(CONFIG_USER_ONLY)
+ env->ps = PS_USER_MODE;
+ cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
+ | FPCR_UNFD | FPCR_INED | FPCR_DNOD));
+#endif
+ env->lock_addr = -1;
+ env->fen = 1;
+}
+
+static void alpha_cpu_class_init(ObjectClass *klass, void *data)
+{
+ AlphaCPUClass *k = ALPHA_CPU_CLASS(klass);
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ const AlphaCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = alpha_cpu_reset;
+
+ k->implver = info->implver;
+ k->amask = info->amask;
+}
+
+static void alpha_register_cpu(const AlphaCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_ALPHA_CPU,
+ .instance_size = sizeof(AlphaCPU),
+ .instance_init = alpha_cpu_initfn,
+ .class_size = sizeof(AlphaCPUClass),
+ .class_init = alpha_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo alpha_cpu_info = {
+ .name = TYPE_ALPHA_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(AlphaCPU),
+ .instance_init = alpha_cpu_initfn,
+ .abstract = true,
+ .class_size = sizeof(AlphaCPUClass),
+};
+
+static void alpha_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&alpha_cpu_info);
+ for (i = 0; i < ARRAY_SIZE(alpha_cpus); i++) {
+ alpha_register_cpu(&alpha_cpus[i]);
+ }
+}
+
+type_init(alpha_cpu_register_types)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 48c0fdc..4126b3d 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -293,6 +293,7 @@ struct CPUAlphaState {
#define cpu_signal_handler cpu_alpha_signal_handler
#include "cpu-all.h"
+#include "cpu-qom.h"
enum {
FEATURE_ASN = 0x00000001,
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index b51fe5c..d51000b 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3460,63 +3460,19 @@ void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb)
gen_intermediate_code_internal(env, tb, 1);
}
-struct cpu_def_t {
- const char *name;
- int implver, amask;
-};
-
-static const struct cpu_def_t cpu_defs[] = {
- { "ev4", IMPLVER_2106x, 0 },
- { "ev5", IMPLVER_21164, 0 },
- { "ev56", IMPLVER_21164, AMASK_BWX },
- { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
- { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
- { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
- { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
- { "21064", IMPLVER_2106x, 0 },
- { "21164", IMPLVER_21164, 0 },
- { "21164a", IMPLVER_21164, AMASK_BWX },
- { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
- { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
- { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }
-};
-
-CPUAlphaState * cpu_alpha_init (const char *cpu_model)
+CPUAlphaState *cpu_alpha_init(const char *cpu_model)
{
+ AlphaCPU *cpu;
CPUAlphaState *env;
- int implver, amask, i, max;
-
- env = g_malloc0(sizeof(CPUAlphaState));
- cpu_exec_init(env);
- alpha_translate_init();
- tlb_flush(env, 1);
- /* Default to ev67; no reason not to emulate insns by default. */
- implver = IMPLVER_21264;
- amask = (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI
- | AMASK_TRAP | AMASK_PREFETCH);
-
- max = ARRAY_SIZE(cpu_defs);
- for (i = 0; i < max; i++) {
- if (strcmp (cpu_model, cpu_defs[i].name) == 0) {
- implver = cpu_defs[i].implver;
- amask = cpu_defs[i].amask;
- break;
- }
+ if (object_class_by_name(cpu_model) == NULL) {
+ /* Default to ev67; no reason not to emulate insns by default. */
+ cpu_model = "ev67";
}
- env->implver = implver;
- env->amask = amask;
+ cpu = ALPHA_CPU(object_new(cpu_model));
+ env = &cpu->env;
-#if defined (CONFIG_USER_ONLY)
- env->ps = PS_USER_MODE;
- cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
- | FPCR_UNFD | FPCR_INED | FPCR_DNOD));
-#endif
- env->lock_addr = -1;
- env->fen = 1;
+ alpha_translate_init();
qemu_init_vcpu(env);
return env;
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 05/12] target-i386: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (3 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-15 19:30 ` Eduardo Habkost
2012-03-14 17:53 ` [Qemu-devel] " Andreas Färber
` (6 subsequent siblings)
11 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 2 +-
target-i386/cpu-qom.h | 87 +++
target-i386/cpu.c | 1598 +++++++++++++++++++++++++++++++++++++++++++++++++
target-i386/cpu.h | 6 +-
target-i386/cpuid.c | 1369 ------------------------------------------
target-i386/helper.c | 101 +---
6 files changed, 1697 insertions(+), 1466 deletions(-)
create mode 100644 target-i386/cpu-qom.h
create mode 100644 target-i386/cpu.c
delete mode 100644 target-i386/cpuid.c
diff --git a/Makefile.target b/Makefile.target
index 74604fd..c655091 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -82,7 +82,7 @@ libobj-$(CONFIG_TCG_INTERPRETER) += tci.o
libobj-y += fpu/softfloat.o
libobj-y += op_helper.o helper.o
ifeq ($(TARGET_BASE_ARCH), i386)
-libobj-y += cpuid.o
+libobj-y += cpu.o
endif
libobj-$(TARGET_SPARC64) += vis_helper.o
libobj-$(CONFIG_NEED_MMU) += mmu.o
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
new file mode 100644
index 0000000..729e67c
--- /dev/null
+++ b/target-i386/cpu-qom.h
@@ -0,0 +1,87 @@
+/*
+ * QEMU x86 CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_I386_CPU_QOM_H
+#define QEMU_I386_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_X86_CPU "x86-cpu"
+
+#define X86_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
+#define X86_CPU(obj) \
+ OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
+#define X86_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
+
+/**
+ * X86CPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An x86 CPU model or family.
+ */
+typedef struct X86CPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t level;
+ uint32_t vendor1, vendor2, vendor3;
+ int family;
+ int model;
+ int stepping;
+ int tsc_khz;
+ uint32_t features, ext_features, ext2_features, ext3_features;
+ uint32_t kvm_features, svm_features;
+ uint32_t xlevel;
+ char model_id[48];
+ int vendor_override;
+ uint32_t flags;
+ /* Store the results of Centaur's CPUID instructions */
+ uint32_t ext4_features;
+ uint32_t xlevel2;
+} X86CPUClass;
+
+/**
+ * X86CPU:
+ * @env: Legacy CPU state.
+ *
+ * An x86 CPU.
+ */
+typedef struct X86CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUX86State env;
+} X86CPU;
+
+static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
+{
+ return X86_CPU(container_of(env, X86CPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
+
+
+#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
new file mode 100644
index 0000000..fd57166
--- /dev/null
+++ b/target-i386/cpu.c
@@ -0,0 +1,1598 @@
+/*
+ * QEMU i386 CPU and CPUID helper functions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "cpu.h"
+#include "kvm.h"
+
+#include "qemu-option.h"
+#include "qemu-config.h"
+
+#include "hyperv.h"
+
+/* feature flags taken from "Intel Processor Identification and the CPUID
+ * Instruction" and AMD's "CPUID Specification". In cases of disagreement
+ * between feature naming conventions, aliases may be added.
+ */
+static const char *feature_name[] = {
+ "fpu", "vme", "de", "pse",
+ "tsc", "msr", "pae", "mce",
+ "cx8", "apic", NULL, "sep",
+ "mtrr", "pge", "mca", "cmov",
+ "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
+ NULL, "ds" /* Intel dts */, "acpi", "mmx",
+ "fxsr", "sse", "sse2", "ss",
+ "ht" /* Intel htt */, "tm", "ia64", "pbe",
+};
+static const char *ext_feature_name[] = {
+ "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
+ "ds_cpl", "vmx", "smx", "est",
+ "tm2", "ssse3", "cid", NULL,
+ "fma", "cx16", "xtpr", "pdcm",
+ NULL, NULL, "dca", "sse4.1|sse4_1",
+ "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
+ "tsc-deadline", "aes", "xsave", "osxsave",
+ "avx", NULL, NULL, "hypervisor",
+};
+static const char *ext2_feature_name[] = {
+ "fpu", "vme", "de", "pse",
+ "tsc", "msr", "pae", "mce",
+ "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
+ "mtrr", "pge", "mca", "cmov",
+ "pat", "pse36", NULL, NULL /* Linux mp */,
+ "nx|xd", NULL, "mmxext", "mmx",
+ "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
+ NULL, "lm|i64", "3dnowext", "3dnow",
+};
+static const char *ext3_feature_name[] = {
+ "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
+ "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
+ "3dnowprefetch", "osvw", "ibs", "xop",
+ "skinit", "wdt", NULL, NULL,
+ "fma4", NULL, "cvt16", "nodeid_msr",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+};
+
+static const char *kvm_feature_name[] = {
+ "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+};
+
+static const char *svm_feature_name[] = {
+ "npt", "lbrv", "svm_lock", "nrip_save",
+ "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
+ NULL, NULL, "pause_filter", NULL,
+ "pfthreshold", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+};
+
+/* collects per-function cpuid data
+ */
+typedef struct model_features_t {
+ uint32_t *guest_feat;
+ uint32_t *host_feat;
+ uint32_t check_feat;
+ const char **flag_names;
+ uint32_t cpuid;
+ } model_features_t;
+
+int check_cpuid = 0;
+int enforce_cpuid = 0;
+
+void host_cpuid(uint32_t function, uint32_t count,
+ uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
+{
+#if defined(CONFIG_KVM)
+ uint32_t vec[4];
+
+#ifdef __x86_64__
+ asm volatile("cpuid"
+ : "=a"(vec[0]), "=b"(vec[1]),
+ "=c"(vec[2]), "=d"(vec[3])
+ : "0"(function), "c"(count) : "cc");
+#else
+ asm volatile("pusha \n\t"
+ "cpuid \n\t"
+ "mov %%eax, 0(%2) \n\t"
+ "mov %%ebx, 4(%2) \n\t"
+ "mov %%ecx, 8(%2) \n\t"
+ "mov %%edx, 12(%2) \n\t"
+ "popa"
+ : : "a"(function), "c"(count), "S"(vec)
+ : "memory", "cc");
+#endif
+
+ if (eax)
+ *eax = vec[0];
+ if (ebx)
+ *ebx = vec[1];
+ if (ecx)
+ *ecx = vec[2];
+ if (edx)
+ *edx = vec[3];
+#endif
+}
+
+#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
+
+/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
+ * a substring. ex if !NULL points to the first char after a substring,
+ * otherwise the string is assumed to sized by a terminating nul.
+ * Return lexical ordering of *s1:*s2.
+ */
+static int sstrcmp(const char *s1, const char *e1, const char *s2,
+ const char *e2)
+{
+ for (;;) {
+ if (!*s1 || !*s2 || *s1 != *s2)
+ return (*s1 - *s2);
+ ++s1, ++s2;
+ if (s1 == e1 && s2 == e2)
+ return (0);
+ else if (s1 == e1)
+ return (*s2);
+ else if (s2 == e2)
+ return (*s1);
+ }
+}
+
+/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
+ * '|' delimited (possibly empty) strings in which case search for a match
+ * within the alternatives proceeds left to right. Return 0 for success,
+ * non-zero otherwise.
+ */
+static int altcmp(const char *s, const char *e, const char *altstr)
+{
+ const char *p, *q;
+
+ for (q = p = altstr; ; ) {
+ while (*p && *p != '|')
+ ++p;
+ if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
+ return (0);
+ if (!*p)
+ return (1);
+ else
+ q = ++p;
+ }
+}
+
+/* search featureset for flag *[s..e), if found set corresponding bit in
+ * *pval and return true, otherwise return false
+ */
+static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
+ const char **featureset)
+{
+ uint32_t mask;
+ const char **ppc;
+ bool found = false;
+
+ for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
+ if (*ppc && !altcmp(s, e, *ppc)) {
+ *pval |= mask;
+ found = true;
+ }
+ }
+ return found;
+}
+
+static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
+ uint32_t *ext_features,
+ uint32_t *ext2_features,
+ uint32_t *ext3_features,
+ uint32_t *kvm_features,
+ uint32_t *svm_features)
+{
+ if (!lookup_feature(features, flagname, NULL, feature_name) &&
+ !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
+ !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
+ !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
+ !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
+ !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
+ fprintf(stderr, "CPU feature %s not found\n", flagname);
+}
+
+typedef struct X86CPUInfo {
+ const char *name;
+ uint32_t level;
+ uint32_t vendor1, vendor2, vendor3;
+ int family;
+ int model;
+ int stepping;
+ int tsc_khz;
+ uint32_t features, ext_features, ext2_features, ext3_features;
+ uint32_t kvm_features, svm_features;
+ uint32_t xlevel;
+ char model_id[48];
+ int vendor_override;
+ uint32_t flags;
+ /* Store the results of Centaur's CPUID instructions */
+ uint32_t ext4_features;
+ uint32_t xlevel2;
+} X86CPUInfo;
+
+static void x86_cpu_class_init(ObjectClass *klass, void *data)
+{
+ X86CPUClass *k = X86_CPU_CLASS(klass);
+ const X86CPUInfo *info = data;
+
+ k->level = info->level;
+ k->vendor1 = info->vendor1;
+ k->vendor2 = info->vendor2;
+ k->vendor3 = info->vendor3;
+ k->family = info->family;
+ k->model = info->model;
+ k->stepping = info->stepping;
+ k->tsc_khz = info->tsc_khz;
+ k->features = info->features;
+ k->ext_features = info->ext_features;
+ k->ext2_features = info->ext2_features;
+ k->ext3_features = info->ext3_features;
+ k->kvm_features = info->kvm_features;
+ k->svm_features = info->svm_features;
+ k->xlevel = info->xlevel;
+ memcpy(k->model_id, info->model_id, 48);
+ k->vendor_override = info->vendor_override;
+ k->flags = info->flags;
+ k->ext4_features = info->ext4_features;
+ k->xlevel2 = info->xlevel2;
+}
+
+#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
+#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
+ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
+#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
+ CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
+ CPUID_PSE36 | CPUID_FXSR)
+#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
+#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
+ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
+ CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
+ CPUID_PAE | CPUID_SEP | CPUID_APIC)
+#define EXT2_FEATURE_MASK 0x0183F3FF
+
+#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
+ CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
+ CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
+ CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
+ /* partly implemented:
+ CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
+ CPUID_PSE36 (needed for Solaris) */
+ /* missing:
+ CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
+#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
+ CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
+ CPUID_EXT_HYPERVISOR)
+ /* missing:
+ CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
+ CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
+#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
+ CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
+ CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
+ /* missing:
+ CPUID_EXT2_PDPE1GB */
+#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
+ CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
+#define TCG_SVM_FEATURES 0
+
+/* built-in cpu model definitions (deprecated)
+ */
+static const X86CPUInfo builtin_x86_cpus[] = {
+ {
+ .name = "qemu64",
+ .level = 4,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 6,
+ .model = 2,
+ .stepping = 3,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
+ .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
+ CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
+ .xlevel = 0x8000000A,
+ .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
+ },
+ {
+ .name = "phenom",
+ .level = 5,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 16,
+ .model = 2,
+ .stepping = 3,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36 | CPUID_VME | CPUID_HT,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
+ CPUID_EXT_POPCNT,
+ .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
+ CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
+ CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
+ CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
+ /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
+ CPUID_EXT3_CR8LEG,
+ CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
+ CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
+ .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
+ .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
+ .xlevel = 0x8000001A,
+ .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
+ },
+ {
+ .name = "core2duo",
+ .level = 10,
+ .family = 6,
+ .model = 15,
+ .stepping = 11,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
+ CPUID_HT | CPUID_TM | CPUID_PBE,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
+ CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
+ CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000008,
+ .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
+ },
+ {
+ .name = "kvm64",
+ .level = 5,
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .family = 15,
+ .model = 6,
+ .stepping = 1,
+ /* Missing: CPUID_VME, CPUID_HT */
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36,
+ /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
+ /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
+ .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
+ CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
+ CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
+ CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
+ CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
+ .ext3_features = 0,
+ .xlevel = 0x80000008,
+ .model_id = "Common KVM processor"
+ },
+ {
+ .name = "qemu32",
+ .level = 4,
+ .family = 6,
+ .model = 3,
+ .stepping = 3,
+ .features = PPRO_FEATURES,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
+ .xlevel = 0x80000004,
+ .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
+ },
+ {
+ .name = "kvm32",
+ .level = 5,
+ .family = 15,
+ .model = 6,
+ .stepping = 1,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
+ .ext_features = CPUID_EXT_SSE3,
+ .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
+ .ext3_features = 0,
+ .xlevel = 0x80000008,
+ .model_id = "Common 32-bit KVM processor"
+ },
+ {
+ .name = "coreduo",
+ .level = 10,
+ .family = 6,
+ .model = 14,
+ .stepping = 8,
+ .features = PPRO_FEATURES | CPUID_VME |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
+ CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
+ CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
+ .ext2_features = CPUID_EXT2_NX,
+ .xlevel = 0x80000008,
+ .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
+ },
+ {
+ .name = "486",
+ .level = 1,
+ .family = 4,
+ .model = 0,
+ .stepping = 0,
+ .features = I486_FEATURES,
+ .xlevel = 0,
+ },
+ {
+ .name = "pentium",
+ .level = 1,
+ .family = 5,
+ .model = 4,
+ .stepping = 3,
+ .features = PENTIUM_FEATURES,
+ .xlevel = 0,
+ },
+ {
+ .name = "pentium2",
+ .level = 2,
+ .family = 6,
+ .model = 5,
+ .stepping = 2,
+ .features = PENTIUM2_FEATURES,
+ .xlevel = 0,
+ },
+ {
+ .name = "pentium3",
+ .level = 2,
+ .family = 6,
+ .model = 7,
+ .stepping = 3,
+ .features = PENTIUM3_FEATURES,
+ .xlevel = 0,
+ },
+ {
+ .name = "athlon",
+ .level = 2,
+ .vendor1 = CPUID_VENDOR_AMD_1,
+ .vendor2 = CPUID_VENDOR_AMD_2,
+ .vendor3 = CPUID_VENDOR_AMD_3,
+ .family = 6,
+ .model = 2,
+ .stepping = 3,
+ .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
+ .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
+ .xlevel = 0x80000008,
+ /* XXX: put another string ? */
+ .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
+ },
+ {
+ .name = "n270",
+ /* original is on level 10 */
+ .level = 5,
+ .family = 6,
+ .model = 28,
+ .stepping = 2,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
+ CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
+ /* Some CPUs got no CPUID_SEP */
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
+ CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
+ .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
+ },
+};
+
+static int cpu_x86_fill_model_id(char *str)
+{
+ uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
+ memcpy(str + i * 16 + 0, &eax, 4);
+ memcpy(str + i * 16 + 4, &ebx, 4);
+ memcpy(str + i * 16 + 8, &ecx, 4);
+ memcpy(str + i * 16 + 12, &edx, 4);
+ }
+ return 0;
+}
+
+static void x86_host_cpu_class_init(ObjectClass *klass, void *data)
+{
+ X86CPUClass *x86_cpu_def = X86_CPU_CLASS(klass);
+ uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+
+ host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_def->level = eax;
+ x86_cpu_def->vendor1 = ebx;
+ x86_cpu_def->vendor2 = edx;
+ x86_cpu_def->vendor3 = ecx;
+
+ host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
+ x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
+ x86_cpu_def->stepping = eax & 0x0F;
+ x86_cpu_def->ext_features = ecx;
+ x86_cpu_def->features = edx;
+
+ host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_def->xlevel = eax;
+
+ host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_def->ext2_features = edx;
+ x86_cpu_def->ext3_features = ecx;
+ cpu_x86_fill_model_id(x86_cpu_def->model_id);
+ x86_cpu_def->vendor_override = 0;
+
+ /* Call Centaur's CPUID instruction. */
+ if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
+ x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
+ x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
+ host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
+ if (eax >= 0xC0000001) {
+ /* Support VIA max extended level */
+ x86_cpu_def->xlevel2 = eax;
+ host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_def->ext4_features = edx;
+ }
+ }
+
+ /*
+ * Every SVM feature requires emulation support in KVM - so we can't just
+ * read the host features here. KVM might even support SVM features not
+ * available on the host hardware. Just set all bits and mask out the
+ * unsupported ones later.
+ */
+ x86_cpu_def->svm_features = -1;
+}
+
+static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
+{
+ int i;
+
+ for (i = 0; i < 32; ++i)
+ if (1 << i & mask) {
+ fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
+ " flag '%s' [0x%08x]\n",
+ f->cpuid >> 16, f->cpuid & 0xffff,
+ f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
+ break;
+ }
+ return 0;
+}
+
+/* best effort attempt to inform user requested cpu flags aren't making
+ * their way to the guest. Note: ft[].check_feat ideally should be
+ * specified via a guest_def field to suppress report of extraneous flags.
+ */
+static int check_features_against_host(X86CPU *guest_cpu)
+{
+ X86CPUClass *host_class;
+ uint32_t mask;
+ int rv, i;
+ struct model_features_t ft[] = {
+ {&guest_cpu->env.cpuid_features, &host_class->features,
+ ~0, feature_name, 0x00000000},
+ {&guest_cpu->env.cpuid_ext_features, &host_class->ext_features,
+ ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
+ {&guest_cpu->env.cpuid_ext2_features, &host_class->ext2_features,
+ ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
+ {&guest_cpu->env.cpuid_ext3_features, &host_class->ext3_features,
+ ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
+
+ host_class = X86_CPU_CLASS(object_class_by_name("host"));
+ for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
+ for (mask = 1; mask; mask <<= 1)
+ if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
+ !(*ft[i].host_feat & mask)) {
+ unavailable_host_feature(&ft[i], mask);
+ rv = 1;
+ }
+ return rv;
+}
+
+static void x86_cpuid_version_set_family(X86CPU *cpu, int family)
+{
+ CPUX86State *env = &cpu->env;
+
+ env->cpuid_version &= ~0xff00f00;
+ if (family > 0x0f) {
+ env->cpuid_version |= 0xf00 | ((family - 0x0f) << 20);
+ } else {
+ env->cpuid_version |= family << 8;
+ }
+}
+
+static void x86_cpuid_version_set_model(X86CPU *cpu, int model)
+{
+ CPUX86State *env = &cpu->env;
+
+ env->cpuid_version &= ~0xf00f0;
+ env->cpuid_version |= ((model & 0xf) << 4) | ((model >> 4) << 16);
+}
+
+static void x86_cpuid_version_set_stepping(X86CPU *cpu, int stepping)
+{
+ CPUX86State *env = &cpu->env;
+
+ env->cpuid_version &= ~0xf;
+ env->cpuid_version |= stepping & 0xf;
+}
+
+static void x86_cpuid_set_model_id(X86CPU *cpu, const char *model_id)
+{
+ CPUX86State *env = &cpu->env;
+ int c, len, i;
+
+ if (model_id == NULL) {
+ model_id = "";
+ }
+ len = strlen(model_id);
+ for (i = 0; i < 48; i++) {
+ if (i >= len) {
+ c = '\0';
+ } else {
+ c = (uint8_t)model_id[i];
+ }
+ env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
+ }
+}
+
+X86CPU *cpu_x86_find_by_name(const char *cpu_model)
+{
+ unsigned int i;
+ X86CPU *cpu = NULL;
+
+ char *s = g_strdup(cpu_model);
+ char *featurestr, *name = strtok(s, ",");
+ /* Features to be added*/
+ uint32_t plus_features = 0, plus_ext_features = 0;
+ uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
+ uint32_t plus_kvm_features = 0, plus_svm_features = 0;
+ /* Features to be removed */
+ uint32_t minus_features = 0, minus_ext_features = 0;
+ uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
+ uint32_t minus_kvm_features = 0, minus_svm_features = 0;
+ uint32_t numvalue;
+
+ if (name == NULL || (!kvm_enabled() && strcmp(name, "host") == 0)) {
+ goto error;
+ }
+ if (object_class_by_name(name) == NULL) {
+ goto error;
+ }
+ cpu = X86_CPU(object_new(name));
+
+ plus_kvm_features = ~0; /* not supported bits will be filtered out later */
+
+ add_flagname_to_bitmaps("hypervisor", &plus_features,
+ &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
+ &plus_kvm_features, &plus_svm_features);
+
+ featurestr = strtok(NULL, ",");
+
+ while (featurestr) {
+ char *val;
+ if (featurestr[0] == '+') {
+ add_flagname_to_bitmaps(featurestr + 1, &plus_features,
+ &plus_ext_features, &plus_ext2_features,
+ &plus_ext3_features, &plus_kvm_features,
+ &plus_svm_features);
+ } else if (featurestr[0] == '-') {
+ add_flagname_to_bitmaps(featurestr + 1, &minus_features,
+ &minus_ext_features, &minus_ext2_features,
+ &minus_ext3_features, &minus_kvm_features,
+ &minus_svm_features);
+ } else if ((val = strchr(featurestr, '='))) {
+ *val = 0; val++;
+ if (!strcmp(featurestr, "family")) {
+ char *err;
+ numvalue = strtoul(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ x86_cpuid_version_set_family(cpu, numvalue);
+ } else if (!strcmp(featurestr, "model")) {
+ char *err;
+ numvalue = strtoul(val, &err, 0);
+ if (!*val || *err || numvalue > 0xff) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ x86_cpuid_version_set_model(cpu, numvalue);
+ } else if (!strcmp(featurestr, "stepping")) {
+ char *err;
+ numvalue = strtoul(val, &err, 0);
+ if (!*val || *err || numvalue > 0xf) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ x86_cpuid_version_set_stepping(cpu, numvalue);
+ } else if (!strcmp(featurestr, "level")) {
+ char *err;
+ numvalue = strtoul(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ cpu->env.cpuid_level = numvalue;
+ } else if (!strcmp(featurestr, "xlevel")) {
+ char *err;
+ numvalue = strtoul(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ if (numvalue < 0x80000000) {
+ numvalue += 0x80000000;
+ }
+ cpu->env.cpuid_xlevel = numvalue;
+ } else if (!strcmp(featurestr, "vendor")) {
+ if (strlen(val) != 12) {
+ fprintf(stderr, "vendor string must be 12 chars long\n");
+ goto error;
+ }
+ cpu->env.cpuid_vendor1 = 0;
+ cpu->env.cpuid_vendor2 = 0;
+ cpu->env.cpuid_vendor3 = 0;
+ for(i = 0; i < 4; i++) {
+ cpu->env.cpuid_vendor1 |= ((uint8_t)val[i ]) << (8 * i);
+ cpu->env.cpuid_vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
+ cpu->env.cpuid_vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
+ }
+ cpu->env.cpuid_vendor_override = 1;
+ } else if (!strcmp(featurestr, "model_id")) {
+ x86_cpuid_set_model_id(cpu, val);
+ } else if (!strcmp(featurestr, "tsc_freq")) {
+ int64_t tsc_freq;
+ char *err;
+
+ tsc_freq = strtosz_suffix_unit(val, &err,
+ STRTOSZ_DEFSUFFIX_B, 1000);
+ if (tsc_freq < 0 || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ cpu->env.tsc_khz = tsc_freq / 1000;
+ } else if (!strcmp(featurestr, "hv_spinlocks")) {
+ char *err;
+ numvalue = strtoul(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ hyperv_set_spinlock_retries(numvalue);
+ } else {
+ fprintf(stderr, "unrecognized feature %s\n", featurestr);
+ goto error;
+ }
+ } else if (!strcmp(featurestr, "check")) {
+ check_cpuid = 1;
+ } else if (!strcmp(featurestr, "enforce")) {
+ check_cpuid = enforce_cpuid = 1;
+ } else if (!strcmp(featurestr, "hv_relaxed")) {
+ hyperv_enable_relaxed_timing(true);
+ } else if (!strcmp(featurestr, "hv_vapic")) {
+ hyperv_enable_vapic_recommended(true);
+ } else {
+ fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
+ goto error;
+ }
+ featurestr = strtok(NULL, ",");
+ }
+ cpu->env.cpuid_features |= plus_features;
+ cpu->env.cpuid_ext_features |= plus_ext_features;
+ cpu->env.cpuid_ext2_features |= plus_ext2_features;
+ cpu->env.cpuid_ext3_features |= plus_ext3_features;
+ cpu->env.cpuid_kvm_features |= plus_kvm_features;
+ cpu->env.cpuid_svm_features |= plus_svm_features;
+ cpu->env.cpuid_features &= ~minus_features;
+ cpu->env.cpuid_ext_features &= ~minus_ext_features;
+ cpu->env.cpuid_ext2_features &= ~minus_ext2_features;
+ cpu->env.cpuid_ext3_features &= ~minus_ext3_features;
+ cpu->env.cpuid_kvm_features &= ~minus_kvm_features;
+ cpu->env.cpuid_svm_features &= ~minus_svm_features;
+ if (check_cpuid) {
+ if (check_features_against_host(cpu) && enforce_cpuid)
+ goto error;
+ }
+ g_free(s);
+ return cpu;
+
+error:
+ if (cpu != NULL) {
+ object_delete(OBJECT(cpu));
+ }
+ g_free(s);
+ return NULL;
+}
+
+/* generate a composite string into buf of all cpuid names in featureset
+ * selected by fbits. indicate truncation at bufsize in the event of overflow.
+ * if flags, suppress names undefined in featureset.
+ */
+static void listflags(char *buf, int bufsize, uint32_t fbits,
+ const char **featureset, uint32_t flags)
+{
+ const char **p = &featureset[31];
+ char *q, *b, bit;
+ int nc;
+
+ b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
+ *buf = '\0';
+ for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
+ if (fbits & 1 << bit && (*p || !flags)) {
+ if (*p)
+ nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
+ else
+ nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
+ if (bufsize <= nc) {
+ if (b) {
+ memcpy(b, "...", sizeof("..."));
+ }
+ return;
+ }
+ q += nc;
+ bufsize -= nc;
+ }
+}
+
+typedef struct X86CPUListState {
+ FILE *file;
+ fprintf_function cpu_fprintf;
+ bool model;
+ bool dump;
+} X86CPUListState;
+
+static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
+}
+
+static void x86_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *klass = data;
+ X86CPUClass *def = X86_CPU_CLASS(klass);
+ X86CPUListState *s = user_data;
+ const char *name;
+ char buf[256];
+
+ name = object_class_get_name(klass);
+ if (strcmp(name, "host") == 0) {
+ return; /* -cpu host is special-cased */
+ }
+ snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", name);
+ if (s->model || s->dump) {
+ (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n", buf, def->model_id);
+ } else {
+ (*s->cpu_fprintf)(s->file, "x86 %16s\n", buf);
+ }
+ if (s->dump) {
+ memcpy(buf, &def->vendor1, sizeof (def->vendor1));
+ memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
+ memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
+ buf[12] = '\0';
+ (*s->cpu_fprintf)(s->file,
+ " family %d model %d stepping %d level %d xlevel 0x%x"
+ " vendor \"%s\"\n",
+ def->family, def->model, def->stepping, def->level,
+ def->xlevel, buf);
+ listflags(buf, sizeof (buf), def->features, feature_name, 0);
+ (*s->cpu_fprintf)(s->file, " feature_edx %08x (%s)\n", def->features,
+ buf);
+ listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
+ 0);
+ (*s->cpu_fprintf)(s->file, " feature_ecx %08x (%s)\n", def->ext_features,
+ buf);
+ listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
+ 0);
+ (*s->cpu_fprintf)(s->file, " extfeature_edx %08x (%s)\n",
+ def->ext2_features, buf);
+ listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
+ 0);
+ (*s->cpu_fprintf)(s->file, " extfeature_ecx %08x (%s)\n",
+ def->ext3_features, buf);
+ (*s->cpu_fprintf)(s->file, "\n");
+ }
+}
+
+/* generate CPU information:
+ * -? list model names
+ * -?model list model names/IDs
+ * -?dump output all model (x86_def_t) data
+ * -?cpuid list all recognized cpuid flag names
+ */
+void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
+{
+ char buf[256];
+ GSList *list;
+ X86CPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ .model = strcmp("?model", optarg) == 0,
+ .dump = strcmp("?dump", optarg) == 0,
+ };
+ bool cpuid = strcmp("?cpuid", optarg) == 0;
+
+ if (cpuid) {
+ (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
+ listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
+ (*cpu_fprintf)(f, " f_edx: %s\n", buf);
+ listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
+ (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
+ listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
+ (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
+ listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
+ (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
+ return;
+ }
+ list = object_class_get_list(TYPE_X86_CPU, false);
+ list = g_slist_sort(list, x86_cpu_list_compare);
+ g_slist_foreach(list, x86_cpu_list_entry, &s);
+ g_slist_free(list);
+ if (kvm_enabled()) {
+ (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
+ }
+}
+
+static void mce_init(CPUX86State *cenv)
+{
+ unsigned int bank;
+
+ if (((cenv->cpuid_version >> 8) & 0xf) >= 6
+ && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
+ (CPUID_MCE | CPUID_MCA)) {
+ cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
+ cenv->mcg_ctl = ~(uint64_t)0;
+ for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
+ cenv->mce_banks[bank * 4] = ~(uint64_t)0;
+ }
+ }
+}
+
+static void x86_cpu_initfn(Object *obj)
+{
+ X86CPU *cpu = X86_CPU(obj);
+ X86CPUClass *def = X86_CPU_GET_CLASS(cpu);
+ CPUX86State *env = &cpu->env;
+
+ memset(env, 0, sizeof(CPUX86State));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ if (def->vendor1) {
+ env->cpuid_vendor1 = def->vendor1;
+ env->cpuid_vendor2 = def->vendor2;
+ env->cpuid_vendor3 = def->vendor3;
+ } else {
+ env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
+ env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
+ env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
+ }
+ env->cpuid_vendor_override = def->vendor_override;
+ env->cpuid_level = def->level;
+ x86_cpuid_version_set_family(cpu, def->family);
+ x86_cpuid_version_set_model(cpu, def->model);
+ x86_cpuid_version_set_stepping(cpu, def->stepping);
+ env->cpuid_features = def->features;
+ env->cpuid_ext_features = def->ext_features;
+ env->cpuid_ext2_features = def->ext2_features;
+ env->cpuid_ext3_features = def->ext3_features;
+ env->cpuid_xlevel = def->xlevel;
+ env->cpuid_kvm_features = def->kvm_features;
+ env->cpuid_svm_features = def->svm_features;
+ env->cpuid_ext4_features = def->ext4_features;
+ env->cpuid_xlevel2 = def->xlevel2;
+ env->tsc_khz = def->tsc_khz;
+ if (!kvm_enabled()) {
+ env->cpuid_features &= TCG_FEATURES;
+ env->cpuid_ext_features &= TCG_EXT_FEATURES;
+ env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
+#ifdef TARGET_X86_64
+ | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
+#endif
+ );
+ env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
+ env->cpuid_svm_features &= TCG_SVM_FEATURES;
+ }
+ x86_cpuid_set_model_id(cpu, def->model_id);
+
+ mce_init(env);
+ env->cpuid_apic_id = env->cpu_index;
+}
+
+#if !defined(CONFIG_USER_ONLY)
+/* copy vendor id string to 32 bit register, nul pad as needed
+ */
+static void cpyid(const char *s, uint32_t *id)
+{
+ char *d = (char *)id;
+ char i;
+
+ for (i = sizeof (*id); i--; )
+ *d++ = *s ? *s++ : '\0';
+}
+
+/* interpret radix and convert from string to arbitrary scalar,
+ * otherwise flag failure
+ */
+#define setscalar(pval, str, perr) \
+{ \
+ char *pend; \
+ unsigned long ul; \
+ \
+ ul = strtoul(str, &pend, 0); \
+ *str && !*pend ? (*pval = ul) : (*perr = 1); \
+}
+
+/* map cpuid options to feature bits, otherwise return failure
+ * (option tags in *str are delimited by whitespace)
+ */
+static void setfeatures(uint32_t *pval, const char *str,
+ const char **featureset, int *perr)
+{
+ const char *p, *q;
+
+ for (q = p = str; *p || *q; q = p) {
+ while (iswhite(*p))
+ q = ++p;
+ while (*p && !iswhite(*p))
+ ++p;
+ if (!*q && !*p)
+ return;
+ if (!lookup_feature(pval, q, p, featureset)) {
+ fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
+ (int)(p - q), q);
+ *perr = 1;
+ return;
+ }
+ }
+}
+
+/* map config file options to #X86CPUInfo form
+ */
+static int cpudef_setfield(const char *name, const char *str, void *opaque)
+{
+ X86CPUInfo *def = opaque;
+ int err = 0;
+
+ if (!strcmp(name, "name")) {
+ g_free((void *)def->name);
+ def->name = g_strdup(str);
+ } else if (!strcmp(name, "model_id")) {
+ strncpy(def->model_id, str, sizeof (def->model_id));
+ } else if (!strcmp(name, "level")) {
+ setscalar(&def->level, str, &err)
+ } else if (!strcmp(name, "vendor")) {
+ cpyid(&str[0], &def->vendor1);
+ cpyid(&str[4], &def->vendor2);
+ cpyid(&str[8], &def->vendor3);
+ } else if (!strcmp(name, "family")) {
+ setscalar(&def->family, str, &err)
+ } else if (!strcmp(name, "model")) {
+ setscalar(&def->model, str, &err)
+ } else if (!strcmp(name, "stepping")) {
+ setscalar(&def->stepping, str, &err)
+ } else if (!strcmp(name, "feature_edx")) {
+ setfeatures(&def->features, str, feature_name, &err);
+ } else if (!strcmp(name, "feature_ecx")) {
+ setfeatures(&def->ext_features, str, ext_feature_name, &err);
+ } else if (!strcmp(name, "extfeature_edx")) {
+ setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
+ } else if (!strcmp(name, "extfeature_ecx")) {
+ setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
+ } else if (!strcmp(name, "xlevel")) {
+ setscalar(&def->xlevel, str, &err)
+ } else {
+ fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
+ return (1);
+ }
+ if (err) {
+ fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
+ return (1);
+ }
+ return (0);
+}
+
+/* register config file entry as #X86CPUClass
+ */
+static int cpudef_register(QemuOpts *opts, void *opaque)
+{
+ X86CPUInfo *info = g_malloc0(sizeof(X86CPUInfo));
+ ObjectClass *klass;
+
+ qemu_opt_foreach(opts, cpudef_setfield, info, 1);
+ if (info->name == NULL) {
+ return 1;
+ }
+ klass = object_class_by_name(info->name);
+ if (klass != NULL) {
+ /* The class already exists, overwrite it. */
+ x86_cpu_class_init(klass, info);
+ } else {
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_X86_CPU,
+ .instance_size = sizeof(X86CPU),
+ .instance_init = x86_cpu_initfn,
+ .class_size = sizeof(X86CPUClass),
+ .class_init = x86_cpu_class_init,
+ .class_data = info,
+ };
+
+ type_register(&type);
+ }
+ g_free(info);
+ return (0);
+}
+
+void cpu_clear_apic_feature(CPUX86State *env)
+{
+ env->cpuid_features &= ~CPUID_APIC;
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+/* register "cpudef" models defined in configuration file. Here we first
+ * preload any built-in definitions
+ */
+void x86_cpudef_setup(void)
+{
+#if !defined(CONFIG_USER_ONLY)
+ qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
+#endif
+}
+
+static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
+{
+ *ebx = env->cpuid_vendor1;
+ *edx = env->cpuid_vendor2;
+ *ecx = env->cpuid_vendor3;
+
+ /* sysenter isn't supported on compatibility mode on AMD, syscall
+ * isn't supported in compatibility mode on Intel.
+ * Normally we advertise the actual cpu vendor, but you can override
+ * this if you want to use KVM's sysenter/syscall emulation
+ * in compatibility mode and when doing cross vendor migration
+ */
+ if (kvm_enabled() && ! env->cpuid_vendor_override) {
+ host_cpuid(0, 0, NULL, ebx, ecx, edx);
+ }
+}
+
+void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
+{
+ /* test if maximum index reached */
+ if (index & 0x80000000) {
+ if (index > env->cpuid_xlevel) {
+ if (env->cpuid_xlevel2 > 0) {
+ /* Handle the Centaur's CPUID instruction. */
+ if (index > env->cpuid_xlevel2) {
+ index = env->cpuid_xlevel2;
+ } else if (index < 0xC0000000) {
+ index = env->cpuid_xlevel;
+ }
+ } else {
+ index = env->cpuid_xlevel;
+ }
+ }
+ } else {
+ if (index > env->cpuid_level)
+ index = env->cpuid_level;
+ }
+
+ switch(index) {
+ case 0:
+ *eax = env->cpuid_level;
+ get_cpuid_vendor(env, ebx, ecx, edx);
+ break;
+ case 1:
+ *eax = env->cpuid_version;
+ *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
+ *ecx = env->cpuid_ext_features;
+ *edx = env->cpuid_features;
+ if (env->nr_cores * env->nr_threads > 1) {
+ *ebx |= (env->nr_cores * env->nr_threads) << 16;
+ *edx |= 1 << 28; /* HTT bit */
+ }
+ break;
+ case 2:
+ /* cache info: needed for Pentium Pro compatibility */
+ *eax = 1;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0x2c307d;
+ break;
+ case 4:
+ /* cache info: needed for Core compatibility */
+ if (env->nr_cores > 1) {
+ *eax = (env->nr_cores - 1) << 26;
+ } else {
+ *eax = 0;
+ }
+ switch (count) {
+ case 0: /* L1 dcache info */
+ *eax |= 0x0000121;
+ *ebx = 0x1c0003f;
+ *ecx = 0x000003f;
+ *edx = 0x0000001;
+ break;
+ case 1: /* L1 icache info */
+ *eax |= 0x0000122;
+ *ebx = 0x1c0003f;
+ *ecx = 0x000003f;
+ *edx = 0x0000001;
+ break;
+ case 2: /* L2 cache info */
+ *eax |= 0x0000143;
+ if (env->nr_threads > 1) {
+ *eax |= (env->nr_threads - 1) << 14;
+ }
+ *ebx = 0x3c0003f;
+ *ecx = 0x0000fff;
+ *edx = 0x0000001;
+ break;
+ default: /* end of info */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ }
+ break;
+ case 5:
+ /* mwait info: needed for Core compatibility */
+ *eax = 0; /* Smallest monitor-line size in bytes */
+ *ebx = 0; /* Largest monitor-line size in bytes */
+ *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
+ *edx = 0;
+ break;
+ case 6:
+ /* Thermal and Power Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 7:
+ if (kvm_enabled()) {
+ KVMState *s = env->kvm_state;
+
+ *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
+ *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
+ *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
+ *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
+ } else {
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ }
+ break;
+ case 9:
+ /* Direct Cache Access Information Leaf */
+ *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0xA:
+ /* Architectural Performance Monitoring Leaf */
+ if (kvm_enabled()) {
+ KVMState *s = env->kvm_state;
+
+ *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
+ *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
+ *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
+ *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
+ } else {
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ }
+ break;
+ case 0xD:
+ /* Processor Extended State */
+ if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ }
+ if (kvm_enabled()) {
+ KVMState *s = env->kvm_state;
+
+ *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
+ *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
+ *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
+ *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
+ } else {
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ }
+ break;
+ case 0x80000000:
+ *eax = env->cpuid_xlevel;
+ *ebx = env->cpuid_vendor1;
+ *edx = env->cpuid_vendor2;
+ *ecx = env->cpuid_vendor3;
+ break;
+ case 0x80000001:
+ *eax = env->cpuid_version;
+ *ebx = 0;
+ *ecx = env->cpuid_ext3_features;
+ *edx = env->cpuid_ext2_features;
+
+ /* The Linux kernel checks for the CMPLegacy bit and
+ * discards multiple thread information if it is set.
+ * So dont set it here for Intel to make Linux guests happy.
+ */
+ if (env->nr_cores * env->nr_threads > 1) {
+ uint32_t tebx, tecx, tedx;
+ get_cpuid_vendor(env, &tebx, &tecx, &tedx);
+ if (tebx != CPUID_VENDOR_INTEL_1 ||
+ tedx != CPUID_VENDOR_INTEL_2 ||
+ tecx != CPUID_VENDOR_INTEL_3) {
+ *ecx |= 1 << 1; /* CmpLegacy bit */
+ }
+ }
+ break;
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
+ *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
+ *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
+ *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
+ break;
+ case 0x80000005:
+ /* cache info (L1 cache) */
+ *eax = 0x01ff01ff;
+ *ebx = 0x01ff01ff;
+ *ecx = 0x40020140;
+ *edx = 0x40020140;
+ break;
+ case 0x80000006:
+ /* cache info (L2 cache) */
+ *eax = 0;
+ *ebx = 0x42004200;
+ *ecx = 0x02008140;
+ *edx = 0;
+ break;
+ case 0x80000008:
+ /* virtual & phys address size in low 2 bytes. */
+/* XXX: This value must match the one used in the MMU code. */
+ if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
+ /* 64 bit processor */
+/* XXX: The physical address space is limited to 42 bits in exec.c. */
+ *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
+ } else {
+ if (env->cpuid_features & CPUID_PSE36)
+ *eax = 0x00000024; /* 36 bits physical */
+ else
+ *eax = 0x00000020; /* 32 bits physical */
+ }
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (env->nr_cores * env->nr_threads > 1) {
+ *ecx |= (env->nr_cores * env->nr_threads) - 1;
+ }
+ break;
+ case 0x8000000A:
+ if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
+ *eax = 0x00000001; /* SVM Revision */
+ *ebx = 0x00000010; /* nr of ASIDs */
+ *ecx = 0;
+ *edx = env->cpuid_svm_features; /* optional features */
+ } else {
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ }
+ break;
+ case 0xC0000000:
+ *eax = env->cpuid_xlevel2;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0xC0000001:
+ /* Support for VIA CPU's CPUID instruction */
+ *eax = env->cpuid_version;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = env->cpuid_ext4_features;
+ break;
+ case 0xC0000002:
+ case 0xC0000003:
+ case 0xC0000004:
+ /* Reserved for the future, and now filled with zero */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ default:
+ /* reserved values: zero */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ }
+}
+
+static void x86_cpu_reset(CPUState *c)
+{
+ X86CPU *cpu = X86_CPU(c);
+ X86CPUClass *klass = X86_CPU_GET_CLASS(cpu);
+ CPUX86State *env = &cpu->env;
+ int i;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
+ }
+
+ klass->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUX86State, breakpoints));
+
+ tlb_flush(env, 1);
+
+ env->old_exception = -1;
+
+ /* init to reset state */
+
+#ifdef CONFIG_SOFTMMU
+ env->hflags |= HF_SOFTMMU_MASK;
+#endif
+ env->hflags2 |= HF2_GIF_MASK;
+
+ cpu_x86_update_cr0(env, 0x60000010);
+ env->a20_mask = ~0x0;
+ env->smbase = 0x30000;
+
+ env->idt.limit = 0xffff;
+ env->gdt.limit = 0xffff;
+ env->ldt.limit = 0xffff;
+ env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
+ env->tr.limit = 0xffff;
+ env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
+
+ cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
+ DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
+ DESC_R_MASK | DESC_A_MASK);
+ cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
+ cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
+ cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
+ cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
+ cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
+ DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
+ DESC_A_MASK);
+
+ env->eip = 0xfff0;
+ env->regs[R_EDX] = env->cpuid_version;
+
+ env->eflags = 0x2;
+
+ /* FPU init */
+ for (i = 0; i < 8; i++) {
+ env->fptags[i] = 1;
+ }
+ env->fpuc = 0x37f;
+
+ env->mxcsr = 0x1f80;
+
+ env->pat = 0x0007040600070406ULL;
+ env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
+
+ memset(env->dr, 0, sizeof(env->dr));
+ env->dr[6] = DR6_FIXED_1;
+ env->dr[7] = DR7_FIXED_1;
+ cpu_breakpoint_remove_all(env, BP_CPU);
+ cpu_watchpoint_remove_all(env, BP_CPU);
+}
+
+static void x86_cpu_common_class_init(ObjectClass *klass, void *data)
+{
+ X86CPUClass *k = X86_CPU_CLASS(klass);
+ CPUClass *cpu_class = CPU_CLASS(klass);
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = x86_cpu_reset;
+}
+
+static void x86_register_builtin_cpu(const X86CPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_X86_CPU,
+ .instance_size = sizeof(X86CPU),
+ .instance_init = x86_cpu_initfn,
+ .class_size = sizeof(X86CPUClass),
+ .class_init = x86_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo x86_host_cpu_info = {
+ .name = "host",
+ .parent = TYPE_X86_CPU,
+ .instance_size = sizeof(X86CPU),
+ .instance_init = x86_cpu_initfn,
+ .class_size = sizeof(X86CPUClass),
+ .class_init = x86_host_cpu_class_init,
+};
+
+static const TypeInfo x86_cpu_info = {
+ .name = TYPE_X86_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(X86CPU),
+ .abstract = true,
+ .class_size = sizeof(X86CPUClass),
+ .class_init = x86_cpu_common_class_init,
+};
+
+static void x86_cpuid_register_types(void)
+{
+ int i;
+
+ type_register_static(&x86_cpu_info);
+ type_register_static(&x86_host_cpu_info);
+ for (i = 0; i < ARRAY_SIZE(builtin_x86_cpus); i++) {
+ x86_register_builtin_cpu(&builtin_x86_cpus[i]);
+ }
+}
+
+type_init(x86_cpuid_register_types)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index a1ed3e7..c43d45f 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -783,6 +783,8 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
} CPUX86State;
+#include "cpu-qom.h"
+
CPUX86State *cpu_x86_init(const char *cpu_model);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
@@ -896,11 +898,11 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
int cpu_x86_signal_handler(int host_signum, void *pinfo,
void *puc);
-/* cpuid.c */
+/* cpu.c */
+X86CPU *cpu_x86_find_by_name(const char *cpu_model);
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx);
-int cpu_x86_register (CPUX86State *env, const char *cpu_model);
void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
deleted file mode 100644
index 465ea15..0000000
--- a/target-i386/cpuid.c
+++ /dev/null
@@ -1,1369 +0,0 @@
-/*
- * i386 CPUID helper functions
- *
- * Copyright (c) 2003 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <inttypes.h>
-
-#include "cpu.h"
-#include "kvm.h"
-
-#include "qemu-option.h"
-#include "qemu-config.h"
-
-#include "hyperv.h"
-
-/* feature flags taken from "Intel Processor Identification and the CPUID
- * Instruction" and AMD's "CPUID Specification". In cases of disagreement
- * between feature naming conventions, aliases may be added.
- */
-static const char *feature_name[] = {
- "fpu", "vme", "de", "pse",
- "tsc", "msr", "pae", "mce",
- "cx8", "apic", NULL, "sep",
- "mtrr", "pge", "mca", "cmov",
- "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
- NULL, "ds" /* Intel dts */, "acpi", "mmx",
- "fxsr", "sse", "sse2", "ss",
- "ht" /* Intel htt */, "tm", "ia64", "pbe",
-};
-static const char *ext_feature_name[] = {
- "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
- "ds_cpl", "vmx", "smx", "est",
- "tm2", "ssse3", "cid", NULL,
- "fma", "cx16", "xtpr", "pdcm",
- NULL, NULL, "dca", "sse4.1|sse4_1",
- "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
- "tsc-deadline", "aes", "xsave", "osxsave",
- "avx", NULL, NULL, "hypervisor",
-};
-static const char *ext2_feature_name[] = {
- "fpu", "vme", "de", "pse",
- "tsc", "msr", "pae", "mce",
- "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
- "mtrr", "pge", "mca", "cmov",
- "pat", "pse36", NULL, NULL /* Linux mp */,
- "nx|xd", NULL, "mmxext", "mmx",
- "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
- NULL, "lm|i64", "3dnowext", "3dnow",
-};
-static const char *ext3_feature_name[] = {
- "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
- "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
- "3dnowprefetch", "osvw", "ibs", "xop",
- "skinit", "wdt", NULL, NULL,
- "fma4", NULL, "cvt16", "nodeid_msr",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
-};
-
-static const char *kvm_feature_name[] = {
- "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-};
-
-static const char *svm_feature_name[] = {
- "npt", "lbrv", "svm_lock", "nrip_save",
- "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
- NULL, NULL, "pause_filter", NULL,
- "pfthreshold", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
-};
-
-/* collects per-function cpuid data
- */
-typedef struct model_features_t {
- uint32_t *guest_feat;
- uint32_t *host_feat;
- uint32_t check_feat;
- const char **flag_names;
- uint32_t cpuid;
- } model_features_t;
-
-int check_cpuid = 0;
-int enforce_cpuid = 0;
-
-void host_cpuid(uint32_t function, uint32_t count,
- uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
-{
-#if defined(CONFIG_KVM)
- uint32_t vec[4];
-
-#ifdef __x86_64__
- asm volatile("cpuid"
- : "=a"(vec[0]), "=b"(vec[1]),
- "=c"(vec[2]), "=d"(vec[3])
- : "0"(function), "c"(count) : "cc");
-#else
- asm volatile("pusha \n\t"
- "cpuid \n\t"
- "mov %%eax, 0(%2) \n\t"
- "mov %%ebx, 4(%2) \n\t"
- "mov %%ecx, 8(%2) \n\t"
- "mov %%edx, 12(%2) \n\t"
- "popa"
- : : "a"(function), "c"(count), "S"(vec)
- : "memory", "cc");
-#endif
-
- if (eax)
- *eax = vec[0];
- if (ebx)
- *ebx = vec[1];
- if (ecx)
- *ecx = vec[2];
- if (edx)
- *edx = vec[3];
-#endif
-}
-
-#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
-
-/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
- * a substring. ex if !NULL points to the first char after a substring,
- * otherwise the string is assumed to sized by a terminating nul.
- * Return lexical ordering of *s1:*s2.
- */
-static int sstrcmp(const char *s1, const char *e1, const char *s2,
- const char *e2)
-{
- for (;;) {
- if (!*s1 || !*s2 || *s1 != *s2)
- return (*s1 - *s2);
- ++s1, ++s2;
- if (s1 == e1 && s2 == e2)
- return (0);
- else if (s1 == e1)
- return (*s2);
- else if (s2 == e2)
- return (*s1);
- }
-}
-
-/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
- * '|' delimited (possibly empty) strings in which case search for a match
- * within the alternatives proceeds left to right. Return 0 for success,
- * non-zero otherwise.
- */
-static int altcmp(const char *s, const char *e, const char *altstr)
-{
- const char *p, *q;
-
- for (q = p = altstr; ; ) {
- while (*p && *p != '|')
- ++p;
- if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
- return (0);
- if (!*p)
- return (1);
- else
- q = ++p;
- }
-}
-
-/* search featureset for flag *[s..e), if found set corresponding bit in
- * *pval and return true, otherwise return false
- */
-static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
- const char **featureset)
-{
- uint32_t mask;
- const char **ppc;
- bool found = false;
-
- for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
- if (*ppc && !altcmp(s, e, *ppc)) {
- *pval |= mask;
- found = true;
- }
- }
- return found;
-}
-
-static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
- uint32_t *ext_features,
- uint32_t *ext2_features,
- uint32_t *ext3_features,
- uint32_t *kvm_features,
- uint32_t *svm_features)
-{
- if (!lookup_feature(features, flagname, NULL, feature_name) &&
- !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
- !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
- !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
- !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
- !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
- fprintf(stderr, "CPU feature %s not found\n", flagname);
-}
-
-typedef struct x86_def_t {
- struct x86_def_t *next;
- const char *name;
- uint32_t level;
- uint32_t vendor1, vendor2, vendor3;
- int family;
- int model;
- int stepping;
- int tsc_khz;
- uint32_t features, ext_features, ext2_features, ext3_features;
- uint32_t kvm_features, svm_features;
- uint32_t xlevel;
- char model_id[48];
- int vendor_override;
- uint32_t flags;
- /* Store the results of Centaur's CPUID instructions */
- uint32_t ext4_features;
- uint32_t xlevel2;
-} x86_def_t;
-
-#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
-#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
- CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
-#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
- CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
- CPUID_PSE36 | CPUID_FXSR)
-#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
-#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
- CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
- CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
- CPUID_PAE | CPUID_SEP | CPUID_APIC)
-#define EXT2_FEATURE_MASK 0x0183F3FF
-
-#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
- CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
- CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
- CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
- CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
- /* partly implemented:
- CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
- CPUID_PSE36 (needed for Solaris) */
- /* missing:
- CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
-#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
- CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
- CPUID_EXT_HYPERVISOR)
- /* missing:
- CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
- CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
-#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
- CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
- CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
- /* missing:
- CPUID_EXT2_PDPE1GB */
-#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
- CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
-#define TCG_SVM_FEATURES 0
-
-/* maintains list of cpu model definitions
- */
-static x86_def_t *x86_defs = {NULL};
-
-/* built-in cpu model definitions (deprecated)
- */
-static x86_def_t builtin_x86_defs[] = {
- {
- .name = "qemu64",
- .level = 4,
- .vendor1 = CPUID_VENDOR_AMD_1,
- .vendor2 = CPUID_VENDOR_AMD_2,
- .vendor3 = CPUID_VENDOR_AMD_3,
- .family = 6,
- .model = 2,
- .stepping = 3,
- .features = PPRO_FEATURES |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
- CPUID_PSE36,
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
- .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
- CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
- .xlevel = 0x8000000A,
- .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
- },
- {
- .name = "phenom",
- .level = 5,
- .vendor1 = CPUID_VENDOR_AMD_1,
- .vendor2 = CPUID_VENDOR_AMD_2,
- .vendor3 = CPUID_VENDOR_AMD_3,
- .family = 16,
- .model = 2,
- .stepping = 3,
- .features = PPRO_FEATURES |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
- CPUID_PSE36 | CPUID_VME | CPUID_HT,
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
- CPUID_EXT_POPCNT,
- .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
- CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
- CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
- /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
- CPUID_EXT3_CR8LEG,
- CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
- CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
- .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
- CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
- .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
- .xlevel = 0x8000001A,
- .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
- },
- {
- .name = "core2duo",
- .level = 10,
- .family = 6,
- .model = 15,
- .stepping = 11,
- .features = PPRO_FEATURES |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
- CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
- CPUID_HT | CPUID_TM | CPUID_PBE,
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
- CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
- CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
- .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .ext3_features = CPUID_EXT3_LAHF_LM,
- .xlevel = 0x80000008,
- .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
- },
- {
- .name = "kvm64",
- .level = 5,
- .vendor1 = CPUID_VENDOR_INTEL_1,
- .vendor2 = CPUID_VENDOR_INTEL_2,
- .vendor3 = CPUID_VENDOR_INTEL_3,
- .family = 15,
- .model = 6,
- .stepping = 1,
- /* Missing: CPUID_VME, CPUID_HT */
- .features = PPRO_FEATURES |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
- CPUID_PSE36,
- /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
- /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
- .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
- CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
- CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
- CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
- .ext3_features = 0,
- .xlevel = 0x80000008,
- .model_id = "Common KVM processor"
- },
- {
- .name = "qemu32",
- .level = 4,
- .family = 6,
- .model = 3,
- .stepping = 3,
- .features = PPRO_FEATURES,
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
- .xlevel = 0x80000004,
- .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
- },
- {
- .name = "kvm32",
- .level = 5,
- .family = 15,
- .model = 6,
- .stepping = 1,
- .features = PPRO_FEATURES |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
- .ext_features = CPUID_EXT_SSE3,
- .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
- .ext3_features = 0,
- .xlevel = 0x80000008,
- .model_id = "Common 32-bit KVM processor"
- },
- {
- .name = "coreduo",
- .level = 10,
- .family = 6,
- .model = 14,
- .stepping = 8,
- .features = PPRO_FEATURES | CPUID_VME |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
- CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
- CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
- .ext2_features = CPUID_EXT2_NX,
- .xlevel = 0x80000008,
- .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
- },
- {
- .name = "486",
- .level = 1,
- .family = 4,
- .model = 0,
- .stepping = 0,
- .features = I486_FEATURES,
- .xlevel = 0,
- },
- {
- .name = "pentium",
- .level = 1,
- .family = 5,
- .model = 4,
- .stepping = 3,
- .features = PENTIUM_FEATURES,
- .xlevel = 0,
- },
- {
- .name = "pentium2",
- .level = 2,
- .family = 6,
- .model = 5,
- .stepping = 2,
- .features = PENTIUM2_FEATURES,
- .xlevel = 0,
- },
- {
- .name = "pentium3",
- .level = 2,
- .family = 6,
- .model = 7,
- .stepping = 3,
- .features = PENTIUM3_FEATURES,
- .xlevel = 0,
- },
- {
- .name = "athlon",
- .level = 2,
- .vendor1 = CPUID_VENDOR_AMD_1,
- .vendor2 = CPUID_VENDOR_AMD_2,
- .vendor3 = CPUID_VENDOR_AMD_3,
- .family = 6,
- .model = 2,
- .stepping = 3,
- .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
- .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
- .xlevel = 0x80000008,
- /* XXX: put another string ? */
- .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
- },
- {
- .name = "n270",
- /* original is on level 10 */
- .level = 5,
- .family = 6,
- .model = 28,
- .stepping = 2,
- .features = PPRO_FEATURES |
- CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
- CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
- /* Some CPUs got no CPUID_SEP */
- .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
- CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
- .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
- .ext3_features = CPUID_EXT3_LAHF_LM,
- .xlevel = 0x8000000A,
- .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
- },
-};
-
-static int cpu_x86_fill_model_id(char *str)
-{
- uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
- int i;
-
- for (i = 0; i < 3; i++) {
- host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
- memcpy(str + i * 16 + 0, &eax, 4);
- memcpy(str + i * 16 + 4, &ebx, 4);
- memcpy(str + i * 16 + 8, &ecx, 4);
- memcpy(str + i * 16 + 12, &edx, 4);
- }
- return 0;
-}
-
-static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
-{
- uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
-
- x86_cpu_def->name = "host";
- host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_def->level = eax;
- x86_cpu_def->vendor1 = ebx;
- x86_cpu_def->vendor2 = edx;
- x86_cpu_def->vendor3 = ecx;
-
- host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
- x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
- x86_cpu_def->stepping = eax & 0x0F;
- x86_cpu_def->ext_features = ecx;
- x86_cpu_def->features = edx;
-
- host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_def->xlevel = eax;
-
- host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_def->ext2_features = edx;
- x86_cpu_def->ext3_features = ecx;
- cpu_x86_fill_model_id(x86_cpu_def->model_id);
- x86_cpu_def->vendor_override = 0;
-
- /* Call Centaur's CPUID instruction. */
- if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
- x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
- x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
- host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
- if (eax >= 0xC0000001) {
- /* Support VIA max extended level */
- x86_cpu_def->xlevel2 = eax;
- host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_def->ext4_features = edx;
- }
- }
-
- /*
- * Every SVM feature requires emulation support in KVM - so we can't just
- * read the host features here. KVM might even support SVM features not
- * available on the host hardware. Just set all bits and mask out the
- * unsupported ones later.
- */
- x86_cpu_def->svm_features = -1;
-
- return 0;
-}
-
-static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
-{
- int i;
-
- for (i = 0; i < 32; ++i)
- if (1 << i & mask) {
- fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
- " flag '%s' [0x%08x]\n",
- f->cpuid >> 16, f->cpuid & 0xffff,
- f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
- break;
- }
- return 0;
-}
-
-/* best effort attempt to inform user requested cpu flags aren't making
- * their way to the guest. Note: ft[].check_feat ideally should be
- * specified via a guest_def field to suppress report of extraneous flags.
- */
-static int check_features_against_host(x86_def_t *guest_def)
-{
- x86_def_t host_def;
- uint32_t mask;
- int rv, i;
- struct model_features_t ft[] = {
- {&guest_def->features, &host_def.features,
- ~0, feature_name, 0x00000000},
- {&guest_def->ext_features, &host_def.ext_features,
- ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
- {&guest_def->ext2_features, &host_def.ext2_features,
- ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
- {&guest_def->ext3_features, &host_def.ext3_features,
- ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
-
- cpu_x86_fill_host(&host_def);
- for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
- for (mask = 1; mask; mask <<= 1)
- if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
- !(*ft[i].host_feat & mask)) {
- unavailable_host_feature(&ft[i], mask);
- rv = 1;
- }
- return rv;
-}
-
-static void x86_cpuid_version_set_family(CPUX86State *env, int family)
-{
- env->cpuid_version &= ~0xff00f00;
- if (family > 0x0f) {
- env->cpuid_version |= 0xf00 | ((family - 0x0f) << 20);
- } else {
- env->cpuid_version |= family << 8;
- }
-}
-
-static void x86_cpuid_version_set_model(CPUX86State *env, int model)
-{
- env->cpuid_version &= ~0xf00f0;
- env->cpuid_version |= ((model & 0xf) << 4) | ((model >> 4) << 16);
-}
-
-static void x86_cpuid_version_set_stepping(CPUX86State *env, int stepping)
-{
- env->cpuid_version &= ~0xf;
- env->cpuid_version |= stepping & 0xf;
-}
-
-static void x86_cpuid_set_model_id(CPUX86State *env, const char *model_id)
-{
- int c, len, i;
-
- if (model_id == NULL) {
- model_id = "";
- }
- len = strlen(model_id);
- for (i = 0; i < 48; i++) {
- if (i >= len) {
- c = '\0';
- } else {
- c = (uint8_t)model_id[i];
- }
- env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
- }
-}
-
-static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
-{
- unsigned int i;
- x86_def_t *def;
-
- char *s = g_strdup(cpu_model);
- char *featurestr, *name = strtok(s, ",");
- /* Features to be added*/
- uint32_t plus_features = 0, plus_ext_features = 0;
- uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
- uint32_t plus_kvm_features = 0, plus_svm_features = 0;
- /* Features to be removed */
- uint32_t minus_features = 0, minus_ext_features = 0;
- uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
- uint32_t minus_kvm_features = 0, minus_svm_features = 0;
- uint32_t numvalue;
-
- for (def = x86_defs; def; def = def->next)
- if (name && !strcmp(name, def->name))
- break;
- if (kvm_enabled() && name && strcmp(name, "host") == 0) {
- cpu_x86_fill_host(x86_cpu_def);
- } else if (!def) {
- goto error;
- } else {
- memcpy(x86_cpu_def, def, sizeof(*def));
- }
-
- plus_kvm_features = ~0; /* not supported bits will be filtered out later */
-
- add_flagname_to_bitmaps("hypervisor", &plus_features,
- &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
- &plus_kvm_features, &plus_svm_features);
-
- featurestr = strtok(NULL, ",");
-
- while (featurestr) {
- char *val;
- if (featurestr[0] == '+') {
- add_flagname_to_bitmaps(featurestr + 1, &plus_features,
- &plus_ext_features, &plus_ext2_features,
- &plus_ext3_features, &plus_kvm_features,
- &plus_svm_features);
- } else if (featurestr[0] == '-') {
- add_flagname_to_bitmaps(featurestr + 1, &minus_features,
- &minus_ext_features, &minus_ext2_features,
- &minus_ext3_features, &minus_kvm_features,
- &minus_svm_features);
- } else if ((val = strchr(featurestr, '='))) {
- *val = 0; val++;
- if (!strcmp(featurestr, "family")) {
- char *err;
- numvalue = strtoul(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- x86_cpu_def->family = numvalue;
- } else if (!strcmp(featurestr, "model")) {
- char *err;
- numvalue = strtoul(val, &err, 0);
- if (!*val || *err || numvalue > 0xff) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- x86_cpu_def->model = numvalue;
- } else if (!strcmp(featurestr, "stepping")) {
- char *err;
- numvalue = strtoul(val, &err, 0);
- if (!*val || *err || numvalue > 0xf) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- x86_cpu_def->stepping = numvalue ;
- } else if (!strcmp(featurestr, "level")) {
- char *err;
- numvalue = strtoul(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- x86_cpu_def->level = numvalue;
- } else if (!strcmp(featurestr, "xlevel")) {
- char *err;
- numvalue = strtoul(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- if (numvalue < 0x80000000) {
- numvalue += 0x80000000;
- }
- x86_cpu_def->xlevel = numvalue;
- } else if (!strcmp(featurestr, "vendor")) {
- if (strlen(val) != 12) {
- fprintf(stderr, "vendor string must be 12 chars long\n");
- goto error;
- }
- x86_cpu_def->vendor1 = 0;
- x86_cpu_def->vendor2 = 0;
- x86_cpu_def->vendor3 = 0;
- for(i = 0; i < 4; i++) {
- x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
- x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
- x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
- }
- x86_cpu_def->vendor_override = 1;
- } else if (!strcmp(featurestr, "model_id")) {
- pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
- val);
- } else if (!strcmp(featurestr, "tsc_freq")) {
- int64_t tsc_freq;
- char *err;
-
- tsc_freq = strtosz_suffix_unit(val, &err,
- STRTOSZ_DEFSUFFIX_B, 1000);
- if (tsc_freq < 0 || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- x86_cpu_def->tsc_khz = tsc_freq / 1000;
- } else if (!strcmp(featurestr, "hv_spinlocks")) {
- char *err;
- numvalue = strtoul(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- hyperv_set_spinlock_retries(numvalue);
- } else {
- fprintf(stderr, "unrecognized feature %s\n", featurestr);
- goto error;
- }
- } else if (!strcmp(featurestr, "check")) {
- check_cpuid = 1;
- } else if (!strcmp(featurestr, "enforce")) {
- check_cpuid = enforce_cpuid = 1;
- } else if (!strcmp(featurestr, "hv_relaxed")) {
- hyperv_enable_relaxed_timing(true);
- } else if (!strcmp(featurestr, "hv_vapic")) {
- hyperv_enable_vapic_recommended(true);
- } else {
- fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
- goto error;
- }
- featurestr = strtok(NULL, ",");
- }
- x86_cpu_def->features |= plus_features;
- x86_cpu_def->ext_features |= plus_ext_features;
- x86_cpu_def->ext2_features |= plus_ext2_features;
- x86_cpu_def->ext3_features |= plus_ext3_features;
- x86_cpu_def->kvm_features |= plus_kvm_features;
- x86_cpu_def->svm_features |= plus_svm_features;
- x86_cpu_def->features &= ~minus_features;
- x86_cpu_def->ext_features &= ~minus_ext_features;
- x86_cpu_def->ext2_features &= ~minus_ext2_features;
- x86_cpu_def->ext3_features &= ~minus_ext3_features;
- x86_cpu_def->kvm_features &= ~minus_kvm_features;
- x86_cpu_def->svm_features &= ~minus_svm_features;
- if (check_cpuid) {
- if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
- goto error;
- }
- g_free(s);
- return 0;
-
-error:
- g_free(s);
- return -1;
-}
-
-/* generate a composite string into buf of all cpuid names in featureset
- * selected by fbits. indicate truncation at bufsize in the event of overflow.
- * if flags, suppress names undefined in featureset.
- */
-static void listflags(char *buf, int bufsize, uint32_t fbits,
- const char **featureset, uint32_t flags)
-{
- const char **p = &featureset[31];
- char *q, *b, bit;
- int nc;
-
- b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
- *buf = '\0';
- for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
- if (fbits & 1 << bit && (*p || !flags)) {
- if (*p)
- nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
- else
- nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
- if (bufsize <= nc) {
- if (b) {
- memcpy(b, "...", sizeof("..."));
- }
- return;
- }
- q += nc;
- bufsize -= nc;
- }
-}
-
-/* generate CPU information:
- * -? list model names
- * -?model list model names/IDs
- * -?dump output all model (x86_def_t) data
- * -?cpuid list all recognized cpuid flag names
- */
-void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
-{
- unsigned char model = !strcmp("?model", optarg);
- unsigned char dump = !strcmp("?dump", optarg);
- unsigned char cpuid = !strcmp("?cpuid", optarg);
- x86_def_t *def;
- char buf[256];
-
- if (cpuid) {
- (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
- listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
- (*cpu_fprintf)(f, " f_edx: %s\n", buf);
- listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
- (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
- listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
- (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
- listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
- (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
- return;
- }
- for (def = x86_defs; def; def = def->next) {
- snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
- if (model || dump) {
- (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
- } else {
- (*cpu_fprintf)(f, "x86 %16s\n", buf);
- }
- if (dump) {
- memcpy(buf, &def->vendor1, sizeof (def->vendor1));
- memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
- memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
- buf[12] = '\0';
- (*cpu_fprintf)(f,
- " family %d model %d stepping %d level %d xlevel 0x%x"
- " vendor \"%s\"\n",
- def->family, def->model, def->stepping, def->level,
- def->xlevel, buf);
- listflags(buf, sizeof (buf), def->features, feature_name, 0);
- (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
- buf);
- listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
- 0);
- (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
- buf);
- listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
- 0);
- (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
- def->ext2_features, buf);
- listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
- 0);
- (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
- def->ext3_features, buf);
- (*cpu_fprintf)(f, "\n");
- }
- }
- if (kvm_enabled()) {
- (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
- }
-}
-
-int cpu_x86_register (CPUX86State *env, const char *cpu_model)
-{
- x86_def_t def1, *def = &def1;
-
- memset(def, 0, sizeof(*def));
-
- if (cpu_x86_find_by_name(def, cpu_model) < 0)
- return -1;
- if (def->vendor1) {
- env->cpuid_vendor1 = def->vendor1;
- env->cpuid_vendor2 = def->vendor2;
- env->cpuid_vendor3 = def->vendor3;
- } else {
- env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
- env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
- env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
- }
- env->cpuid_vendor_override = def->vendor_override;
- env->cpuid_level = def->level;
- x86_cpuid_version_set_family(env, def->family);
- x86_cpuid_version_set_model(env, def->model);
- x86_cpuid_version_set_stepping(env, def->stepping);
- env->cpuid_features = def->features;
- env->cpuid_ext_features = def->ext_features;
- env->cpuid_ext2_features = def->ext2_features;
- env->cpuid_ext3_features = def->ext3_features;
- env->cpuid_xlevel = def->xlevel;
- env->cpuid_kvm_features = def->kvm_features;
- env->cpuid_svm_features = def->svm_features;
- env->cpuid_ext4_features = def->ext4_features;
- env->cpuid_xlevel2 = def->xlevel2;
- env->tsc_khz = def->tsc_khz;
- if (!kvm_enabled()) {
- env->cpuid_features &= TCG_FEATURES;
- env->cpuid_ext_features &= TCG_EXT_FEATURES;
- env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
-#ifdef TARGET_X86_64
- | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
-#endif
- );
- env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
- env->cpuid_svm_features &= TCG_SVM_FEATURES;
- }
- x86_cpuid_set_model_id(env, def->model_id);
- return 0;
-}
-
-#if !defined(CONFIG_USER_ONLY)
-/* copy vendor id string to 32 bit register, nul pad as needed
- */
-static void cpyid(const char *s, uint32_t *id)
-{
- char *d = (char *)id;
- char i;
-
- for (i = sizeof (*id); i--; )
- *d++ = *s ? *s++ : '\0';
-}
-
-/* interpret radix and convert from string to arbitrary scalar,
- * otherwise flag failure
- */
-#define setscalar(pval, str, perr) \
-{ \
- char *pend; \
- unsigned long ul; \
- \
- ul = strtoul(str, &pend, 0); \
- *str && !*pend ? (*pval = ul) : (*perr = 1); \
-}
-
-/* map cpuid options to feature bits, otherwise return failure
- * (option tags in *str are delimited by whitespace)
- */
-static void setfeatures(uint32_t *pval, const char *str,
- const char **featureset, int *perr)
-{
- const char *p, *q;
-
- for (q = p = str; *p || *q; q = p) {
- while (iswhite(*p))
- q = ++p;
- while (*p && !iswhite(*p))
- ++p;
- if (!*q && !*p)
- return;
- if (!lookup_feature(pval, q, p, featureset)) {
- fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
- (int)(p - q), q);
- *perr = 1;
- return;
- }
- }
-}
-
-/* map config file options to x86_def_t form
- */
-static int cpudef_setfield(const char *name, const char *str, void *opaque)
-{
- x86_def_t *def = opaque;
- int err = 0;
-
- if (!strcmp(name, "name")) {
- g_free((void *)def->name);
- def->name = g_strdup(str);
- } else if (!strcmp(name, "model_id")) {
- strncpy(def->model_id, str, sizeof (def->model_id));
- } else if (!strcmp(name, "level")) {
- setscalar(&def->level, str, &err)
- } else if (!strcmp(name, "vendor")) {
- cpyid(&str[0], &def->vendor1);
- cpyid(&str[4], &def->vendor2);
- cpyid(&str[8], &def->vendor3);
- } else if (!strcmp(name, "family")) {
- setscalar(&def->family, str, &err)
- } else if (!strcmp(name, "model")) {
- setscalar(&def->model, str, &err)
- } else if (!strcmp(name, "stepping")) {
- setscalar(&def->stepping, str, &err)
- } else if (!strcmp(name, "feature_edx")) {
- setfeatures(&def->features, str, feature_name, &err);
- } else if (!strcmp(name, "feature_ecx")) {
- setfeatures(&def->ext_features, str, ext_feature_name, &err);
- } else if (!strcmp(name, "extfeature_edx")) {
- setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
- } else if (!strcmp(name, "extfeature_ecx")) {
- setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
- } else if (!strcmp(name, "xlevel")) {
- setscalar(&def->xlevel, str, &err)
- } else {
- fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
- return (1);
- }
- if (err) {
- fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
- return (1);
- }
- return (0);
-}
-
-/* register config file entry as x86_def_t
- */
-static int cpudef_register(QemuOpts *opts, void *opaque)
-{
- x86_def_t *def = g_malloc0(sizeof (x86_def_t));
-
- qemu_opt_foreach(opts, cpudef_setfield, def, 1);
- def->next = x86_defs;
- x86_defs = def;
- return (0);
-}
-
-void cpu_clear_apic_feature(CPUX86State *env)
-{
- env->cpuid_features &= ~CPUID_APIC;
-}
-
-#endif /* !CONFIG_USER_ONLY */
-
-/* register "cpudef" models defined in configuration file. Here we first
- * preload any built-in definitions
- */
-void x86_cpudef_setup(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
- builtin_x86_defs[i].next = x86_defs;
- builtin_x86_defs[i].flags = 1;
- x86_defs = &builtin_x86_defs[i];
- }
-#if !defined(CONFIG_USER_ONLY)
- qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
-#endif
-}
-
-static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
- uint32_t *ecx, uint32_t *edx)
-{
- *ebx = env->cpuid_vendor1;
- *edx = env->cpuid_vendor2;
- *ecx = env->cpuid_vendor3;
-
- /* sysenter isn't supported on compatibility mode on AMD, syscall
- * isn't supported in compatibility mode on Intel.
- * Normally we advertise the actual cpu vendor, but you can override
- * this if you want to use KVM's sysenter/syscall emulation
- * in compatibility mode and when doing cross vendor migration
- */
- if (kvm_enabled() && ! env->cpuid_vendor_override) {
- host_cpuid(0, 0, NULL, ebx, ecx, edx);
- }
-}
-
-void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
- uint32_t *eax, uint32_t *ebx,
- uint32_t *ecx, uint32_t *edx)
-{
- /* test if maximum index reached */
- if (index & 0x80000000) {
- if (index > env->cpuid_xlevel) {
- if (env->cpuid_xlevel2 > 0) {
- /* Handle the Centaur's CPUID instruction. */
- if (index > env->cpuid_xlevel2) {
- index = env->cpuid_xlevel2;
- } else if (index < 0xC0000000) {
- index = env->cpuid_xlevel;
- }
- } else {
- index = env->cpuid_xlevel;
- }
- }
- } else {
- if (index > env->cpuid_level)
- index = env->cpuid_level;
- }
-
- switch(index) {
- case 0:
- *eax = env->cpuid_level;
- get_cpuid_vendor(env, ebx, ecx, edx);
- break;
- case 1:
- *eax = env->cpuid_version;
- *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
- *ecx = env->cpuid_ext_features;
- *edx = env->cpuid_features;
- if (env->nr_cores * env->nr_threads > 1) {
- *ebx |= (env->nr_cores * env->nr_threads) << 16;
- *edx |= 1 << 28; /* HTT bit */
- }
- break;
- case 2:
- /* cache info: needed for Pentium Pro compatibility */
- *eax = 1;
- *ebx = 0;
- *ecx = 0;
- *edx = 0x2c307d;
- break;
- case 4:
- /* cache info: needed for Core compatibility */
- if (env->nr_cores > 1) {
- *eax = (env->nr_cores - 1) << 26;
- } else {
- *eax = 0;
- }
- switch (count) {
- case 0: /* L1 dcache info */
- *eax |= 0x0000121;
- *ebx = 0x1c0003f;
- *ecx = 0x000003f;
- *edx = 0x0000001;
- break;
- case 1: /* L1 icache info */
- *eax |= 0x0000122;
- *ebx = 0x1c0003f;
- *ecx = 0x000003f;
- *edx = 0x0000001;
- break;
- case 2: /* L2 cache info */
- *eax |= 0x0000143;
- if (env->nr_threads > 1) {
- *eax |= (env->nr_threads - 1) << 14;
- }
- *ebx = 0x3c0003f;
- *ecx = 0x0000fff;
- *edx = 0x0000001;
- break;
- default: /* end of info */
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- }
- break;
- case 5:
- /* mwait info: needed for Core compatibility */
- *eax = 0; /* Smallest monitor-line size in bytes */
- *ebx = 0; /* Largest monitor-line size in bytes */
- *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
- *edx = 0;
- break;
- case 6:
- /* Thermal and Power Leaf */
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 7:
- if (kvm_enabled()) {
- KVMState *s = env->kvm_state;
-
- *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
- *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
- *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
- *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
- } else {
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- }
- break;
- case 9:
- /* Direct Cache Access Information Leaf */
- *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 0xA:
- /* Architectural Performance Monitoring Leaf */
- if (kvm_enabled()) {
- KVMState *s = env->kvm_state;
-
- *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
- *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
- *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
- *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
- } else {
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- }
- break;
- case 0xD:
- /* Processor Extended State */
- if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- }
- if (kvm_enabled()) {
- KVMState *s = env->kvm_state;
-
- *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
- *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
- *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
- *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
- } else {
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- }
- break;
- case 0x80000000:
- *eax = env->cpuid_xlevel;
- *ebx = env->cpuid_vendor1;
- *edx = env->cpuid_vendor2;
- *ecx = env->cpuid_vendor3;
- break;
- case 0x80000001:
- *eax = env->cpuid_version;
- *ebx = 0;
- *ecx = env->cpuid_ext3_features;
- *edx = env->cpuid_ext2_features;
-
- /* The Linux kernel checks for the CMPLegacy bit and
- * discards multiple thread information if it is set.
- * So dont set it here for Intel to make Linux guests happy.
- */
- if (env->nr_cores * env->nr_threads > 1) {
- uint32_t tebx, tecx, tedx;
- get_cpuid_vendor(env, &tebx, &tecx, &tedx);
- if (tebx != CPUID_VENDOR_INTEL_1 ||
- tedx != CPUID_VENDOR_INTEL_2 ||
- tecx != CPUID_VENDOR_INTEL_3) {
- *ecx |= 1 << 1; /* CmpLegacy bit */
- }
- }
- break;
- case 0x80000002:
- case 0x80000003:
- case 0x80000004:
- *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
- *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
- *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
- *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
- break;
- case 0x80000005:
- /* cache info (L1 cache) */
- *eax = 0x01ff01ff;
- *ebx = 0x01ff01ff;
- *ecx = 0x40020140;
- *edx = 0x40020140;
- break;
- case 0x80000006:
- /* cache info (L2 cache) */
- *eax = 0;
- *ebx = 0x42004200;
- *ecx = 0x02008140;
- *edx = 0;
- break;
- case 0x80000008:
- /* virtual & phys address size in low 2 bytes. */
-/* XXX: This value must match the one used in the MMU code. */
- if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
- /* 64 bit processor */
-/* XXX: The physical address space is limited to 42 bits in exec.c. */
- *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
- } else {
- if (env->cpuid_features & CPUID_PSE36)
- *eax = 0x00000024; /* 36 bits physical */
- else
- *eax = 0x00000020; /* 32 bits physical */
- }
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- if (env->nr_cores * env->nr_threads > 1) {
- *ecx |= (env->nr_cores * env->nr_threads) - 1;
- }
- break;
- case 0x8000000A:
- if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
- *eax = 0x00000001; /* SVM Revision */
- *ebx = 0x00000010; /* nr of ASIDs */
- *ecx = 0;
- *edx = env->cpuid_svm_features; /* optional features */
- } else {
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- }
- break;
- case 0xC0000000:
- *eax = env->cpuid_xlevel2;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 0xC0000001:
- /* Support for VIA CPU's CPUID instruction */
- *eax = env->cpuid_version;
- *ebx = 0;
- *ecx = 0;
- *edx = env->cpuid_ext4_features;
- break;
- case 0xC0000002:
- case 0xC0000003:
- case 0xC0000004:
- /* Reserved for the future, and now filled with zero */
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- default:
- /* reserved values: zero */
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- }
-}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 83122bf..5e5bf92 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -29,76 +29,7 @@
/* NOTE: must be called outside the CPU execute loop */
void cpu_state_reset(CPUX86State *env)
{
- int i;
-
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
- }
-
- memset(env, 0, offsetof(CPUX86State, breakpoints));
-
- tlb_flush(env, 1);
-
- env->old_exception = -1;
-
- /* init to reset state */
-
-#ifdef CONFIG_SOFTMMU
- env->hflags |= HF_SOFTMMU_MASK;
-#endif
- env->hflags2 |= HF2_GIF_MASK;
-
- cpu_x86_update_cr0(env, 0x60000010);
- env->a20_mask = ~0x0;
- env->smbase = 0x30000;
-
- env->idt.limit = 0xffff;
- env->gdt.limit = 0xffff;
- env->ldt.limit = 0xffff;
- env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
- env->tr.limit = 0xffff;
- env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
-
- cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
- DESC_R_MASK | DESC_A_MASK);
- cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
- cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
- cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
- cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
- cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
- DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
-
- env->eip = 0xfff0;
- env->regs[R_EDX] = env->cpuid_version;
-
- env->eflags = 0x2;
-
- /* FPU init */
- for(i = 0;i < 8; i++)
- env->fptags[i] = 1;
- env->fpuc = 0x37f;
-
- env->mxcsr = 0x1f80;
-
- env->pat = 0x0007040600070406ULL;
- env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
-
- memset(env->dr, 0, sizeof(env->dr));
- env->dr[6] = DR6_FIXED_1;
- env->dr[7] = DR7_FIXED_1;
- cpu_breakpoint_remove_all(env, BP_CPU);
- cpu_watchpoint_remove_all(env, BP_CPU);
+ cpu_reset(ENV_GET_CPU(env));
}
void cpu_x86_close(CPUX86State *env)
@@ -1202,21 +1133,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
}
#endif /* !CONFIG_USER_ONLY */
-static void mce_init(CPUX86State *cenv)
-{
- unsigned int bank;
-
- if (((cenv->cpuid_version >> 8) & 0xf) >= 6
- && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
- (CPUID_MCE | CPUID_MCA)) {
- cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
- cenv->mcg_ctl = ~(uint64_t)0;
- for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
- cenv->mce_banks[bank * 4] = ~(uint64_t)0;
- }
- }
-}
-
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
target_ulong *base, unsigned int *limit,
unsigned int *flags)
@@ -1248,12 +1164,15 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
CPUX86State *cpu_x86_init(const char *cpu_model)
{
+ X86CPU *cpu;
CPUX86State *env;
static int inited;
- env = g_malloc0(sizeof(CPUX86State));
- cpu_exec_init(env);
- env->cpu_model_str = cpu_model;
+ cpu = cpu_x86_find_by_name(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ env = &cpu->env;
/* init various static tables used in TCG mode */
if (tcg_enabled() && !inited) {
@@ -1264,12 +1183,6 @@ CPUX86State *cpu_x86_init(const char *cpu_model)
cpu_set_debug_excp_handler(breakpoint_handler);
#endif
}
- if (cpu_x86_register(env, cpu_model) < 0) {
- cpu_x86_close(env);
- return NULL;
- }
- env->cpuid_apic_id = env->cpu_index;
- mce_init(env);
qemu_init_vcpu(env);
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [RFC 06/12] target-ppc: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
` (10 subsequent siblings)
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel
Cc: Andreas Färber, Alexander Graf, Avi Kivity, Marcelo Tosatti,
open list:PowerPC, open list:Overall
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-ppc/cpu-qom.h | 84 ++++++++++++++
target-ppc/cpu.h | 25 +----
target-ppc/helper.c | 72 ++----------
target-ppc/kvm.c | 29 +++--
target-ppc/kvm_ppc.h | 6 -
target-ppc/translate.c | 2 +-
target-ppc/translate_init.c | 264 ++++++++++++++++++++++++++++++++++++-------
7 files changed, 342 insertions(+), 140 deletions(-)
create mode 100644 target-ppc/cpu-qom.h
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
new file mode 100644
index 0000000..9236dcc
--- /dev/null
+++ b/target-ppc/cpu-qom.h
@@ -0,0 +1,84 @@
+/*
+ * QEMU PowerPC CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_PPC_CPU_QOM_H
+#define QEMU_PPC_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_POWERPC_CPU "powerpc-cpu"
+
+#define POWERPC_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
+#define POWERPC_CPU(obj) \
+ OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
+#define POWERPC_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
+
+/**
+ * PowerPCCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A PowerPC CPU model.
+ */
+typedef struct PowerPCCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t pvr;
+ uint32_t svr;
+ uint64_t insns_flags;
+ uint64_t insns_flags2;
+ uint64_t msr_mask;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
+ uint32_t flags;
+ int bfd_mach;
+ void (*init_proc)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
+} PowerPCCPUClass;
+
+/**
+ * PowerPCCPU:
+ * @env: Legacy CPU state.
+ *
+ * A PowerPC CPU.
+ */
+typedef struct PowerPCCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUPPCState env;
+} PowerPCCPU;
+
+static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
+{
+ return POWERPC_CPU(container_of(env, PowerPCCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
+
+
+#endif
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ad09cbe..ff28843 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -305,7 +305,6 @@ enum powerpc_input_t {
#define PPC_INPUT(env) (env->bus_model)
/*****************************************************************************/
-typedef struct ppc_def_t ppc_def_t;
typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
@@ -877,22 +876,6 @@ enum {
/* The whole PowerPC CPU context */
#define NB_MMU_MODES 3
-struct ppc_def_t {
- const char *name;
- uint32_t pvr;
- uint32_t svr;
- uint64_t insns_flags;
- uint64_t insns_flags2;
- uint64_t msr_mask;
- powerpc_mmu_t mmu_model;
- powerpc_excp_t excp_model;
- powerpc_input_t bus_model;
- uint32_t flags;
- int bfd_mach;
- void (*init_proc)(CPUPPCState *env);
- int (*check_pow)(CPUPPCState *env);
-};
-
struct CPUPPCState {
/* First are the most commonly used resources
* during translated code execution
@@ -1096,6 +1079,8 @@ struct mmu_ctx_t {
};
#endif
+#include "cpu-qom.h"
+
/*****************************************************************************/
CPUPPCState *cpu_ppc_init (const char *cpu_model);
void ppc_translate_init(void);
@@ -1142,9 +1127,9 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
-const ppc_def_t *ppc_find_by_pvr(uint32_t pvr);
-const ppc_def_t *cpu_ppc_find_by_name (const char *name);
-int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
+void ppc_cpu_initfn(Object *obj);
+const char *ppc_find_by_pvr(uint32_t pvr);
+PowerPCCPU *cpu_ppc_find_by_name(const char *name);
/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index bd711b6..7d26cb5 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3138,85 +3138,31 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
void cpu_state_reset(CPUPPCState *env)
{
- target_ulong msr;
-
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- msr = (target_ulong)0;
- if (0) {
- /* XXX: find a suitable condition to enable the hypervisor mode */
- msr |= (target_ulong)MSR_HVB;
- }
- msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
- msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
- msr |= (target_ulong)1 << MSR_EP;
-#if defined (DO_SINGLE_STEP) && 0
- /* Single step trace mode */
- msr |= (target_ulong)1 << MSR_SE;
- msr |= (target_ulong)1 << MSR_BE;
-#endif
-#if defined(CONFIG_USER_ONLY)
- msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
- msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
- msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
- msr |= (target_ulong)1 << MSR_PR;
-#else
- env->excp_prefix = env->hreset_excp_prefix;
- env->nip = env->hreset_vector | env->excp_prefix;
- if (env->mmu_model != POWERPC_MMU_REAL)
- ppc_tlb_invalidate_all(env);
-#endif
- env->msr = msr & env->msr_mask;
-#if defined(TARGET_PPC64)
- if (env->mmu_model & POWERPC_MMU_64)
- env->msr |= (1ULL << MSR_SF);
-#endif
- hreg_compute_hflags(env);
- env->reserve_addr = (target_ulong)-1ULL;
- /* Be sure no exception or interrupt is pending */
- env->pending_interrupts = 0;
- env->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- /* Flush all TLBs */
- tlb_flush(env, 1);
+ cpu_reset(ENV_GET_CPU(env));
}
-CPUPPCState *cpu_ppc_init (const char *cpu_model)
+CPUPPCState *cpu_ppc_init(const char *cpu_model)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
- const ppc_def_t *def;
- def = cpu_ppc_find_by_name(cpu_model);
- if (!def)
+ cpu = cpu_ppc_find_by_name(cpu_model);
+ if (cpu == NULL) {
return NULL;
+ }
+ env = &cpu->env;
- env = g_malloc0(sizeof(CPUPPCState));
- cpu_exec_init(env);
if (tcg_enabled()) {
ppc_translate_init();
}
- /* Adjust cpu index for SMT */
-#if !defined(CONFIG_USER_ONLY)
- if (kvm_enabled()) {
- int smt = kvmppc_smt_threads();
-
- env->cpu_index = (env->cpu_index / smp_threads)*smt
- + (env->cpu_index % smp_threads);
- }
-#endif /* !CONFIG_USER_ONLY */
- env->cpu_model_str = cpu_model;
- cpu_ppc_register_internal(env, def);
qemu_init_vcpu(env);
return env;
}
-void cpu_ppc_close (CPUPPCState *env)
+void cpu_ppc_close(CPUPPCState *env)
{
/* Should also remove all opcode tables... */
- g_free(env);
+ object_delete(OBJECT(ppc_env_get_cpu(env)));
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index aeb3de9..2ee5bc0 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -902,19 +902,12 @@ static void alter_insns(uint64_t *word, uint64_t flags, bool on)
}
}
-const ppc_def_t *kvmppc_host_cpu_def(void)
+static void kvmppc_host_cpu_class_init(ObjectClass *klass, void *data)
{
- uint32_t host_pvr = mfpvr();
- const ppc_def_t *base_spec;
- ppc_def_t *spec;
+ PowerPCCPUClass *spec = POWERPC_CPU_CLASS(klass);
uint32_t vmx = kvmppc_get_vmx();
uint32_t dfp = kvmppc_get_dfp();
- base_spec = ppc_find_by_pvr(host_pvr);
-
- spec = g_malloc0(sizeof(*spec));
- memcpy(spec, base_spec, sizeof(*spec));
-
/* Now fix up the spec with information we can query from the host */
if (vmx != -1) {
@@ -926,8 +919,6 @@ const ppc_def_t *kvmppc_host_cpu_def(void)
/* Only override when we know what the host supports */
alter_insns(&spec->insns_flags2, PPC2_DFP, dfp);
}
-
- return spec;
}
bool kvm_arch_stop_on_emulation_error(CPUPPCState *env)
@@ -944,3 +935,19 @@ int kvm_arch_on_sigbus(int code, void *addr)
{
return 1;
}
+
+static void kvmppc_register_types(void)
+{
+ TypeInfo type = {
+ .name = "host",
+ .instance_size = sizeof(PowerPCCPU),
+ .instance_init = ppc_cpu_initfn,
+ .class_size = sizeof(PowerPCCPUClass),
+ .class_init = kvmppc_host_cpu_class_init,
+ };
+ uint32_t host_pvr = mfpvr();
+ type.parent = ppc_find_by_pvr(host_pvr);
+ type_register_static(&type);
+}
+
+type_init(kvmppc_register_types)
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 8f1267c..ce5be6e 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -28,7 +28,6 @@ off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem);
void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd);
int kvmppc_remove_spapr_tce(void *table, int pfd, uint32_t window_size);
#endif /* !CONFIG_USER_ONLY */
-const ppc_def_t *kvmppc_host_cpu_def(void);
#else
@@ -90,11 +89,6 @@ static inline int kvmppc_remove_spapr_tce(void *table, int pfd,
}
#endif /* !CONFIG_USER_ONLY */
-static inline const ppc_def_t *kvmppc_host_cpu_def(void)
-{
- return NULL;
-}
-
#endif
#ifndef CONFIG_KVM
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3ec59a7..e43160d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9272,8 +9272,8 @@ GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
};
-#include "translate_init.c"
#include "helper_regs.h"
+#include "translate_init.c"
/*****************************************************************************/
/* Misc PowerPC helpers */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1ec6f42..52264c8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2003-2007 Jocelyn Mayer
* Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -27,6 +28,7 @@
#include "gdbstub.h"
#include <kvm.h>
#include "kvm_ppc.h"
+#include "cpus.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
@@ -7583,6 +7585,51 @@ enum {
/*****************************************************************************/
/* PowerPC CPU definitions */
+
+typedef struct PowerPCCPUInfo PowerPCCPUInfo;
+
+struct PowerPCCPUInfo {
+ const char *name;
+ uint32_t pvr;
+ uint32_t svr;
+ uint64_t insns_flags;
+ uint64_t insns_flags2;
+ uint64_t msr_mask;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
+ uint32_t flags;
+ int bfd_mach;
+ void (*init_proc)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
+};
+
+static void ppc_cpu_reset(CPUState *cpu);
+
+static void ppc_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ PowerPCCPUClass *k = POWERPC_CPU_CLASS(klass);
+ const PowerPCCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = ppc_cpu_reset;
+
+ k->pvr = info->pvr;
+ k->svr = info->svr;
+ k->insns_flags = info->insns_flags;
+ k->insns_flags2 = info->insns_flags2;
+ k->msr_mask = info->msr_mask;
+ k->mmu_model = info->mmu_model;
+ k->excp_model = info->excp_model;
+ k->bus_model = info->bus_model;
+ k->flags = info->flags;
+ k->bfd_mach = info->bfd_mach;
+
+ k->init_proc = info->init_proc;
+ k->check_pow = info->check_pow;
+}
+
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
{ \
.name = _name, \
@@ -7602,7 +7649,7 @@ enum {
#define POWERPC_DEF(_name, _pvr, _type) \
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
-static const ppc_def_t ppc_defs[] = {
+static const PowerPCCPUInfo ppc_cpus[] = {
/* Embedded PowerPC */
/* PowerPC 401 family */
/* Generic PowerPC 401 */
@@ -9280,7 +9327,7 @@ static const ppc_def_t ppc_defs[] = {
/*****************************************************************************/
/* Generic CPU instantiation routine */
-static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
+static void init_ppc_proc(CPUPPCState *env, PowerPCCPUClass *def)
{
#if !defined(CONFIG_USER_ONLY)
int i;
@@ -9672,7 +9719,7 @@ static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
}
/*****************************************************************************/
-static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
+static int create_ppc_opcodes(CPUPPCState *env, const PowerPCCPUClass *def)
{
opcode_t *opc;
@@ -9884,8 +9931,26 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
-int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
+void ppc_cpu_initfn(Object *obj)
{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+ PowerPCCPUClass *def = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ /* Adjust cpu index for SMT */
+#if !defined(CONFIG_USER_ONLY)
+ if (kvm_enabled()) {
+ int smt = kvmppc_smt_threads();
+
+ env->cpu_index = (env->cpu_index / smp_threads) * smt
+ + (env->cpu_index % smp_threads);
+ }
+#endif /* !CONFIG_USER_ONLY */
+
env->msr_mask = def->msr_mask;
env->mmu_model = def->mmu_model;
env->excp_model = def->excp_model;
@@ -9911,8 +9976,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
env->flags = def->flags;
env->bfd_mach = def->bfd_mach;
env->check_pow = def->check_pow;
- if (create_ppc_opcodes(env, def) < 0)
- return -1;
+ if (create_ppc_opcodes(env, def) < 0) {
+ abort();
+ }
init_ppc_proc(env, def);
if (def->insns_flags & PPC_FLOAT) {
@@ -10089,11 +10155,64 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
dump_ppc_sprs(env);
fflush(stdout);
#endif
+}
- return 0;
+static void ppc_cpu_reset(CPUState *c)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(c);
+ PowerPCCPUClass *klass = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+ target_ulong msr;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ msr = (target_ulong)0;
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ msr |= (target_ulong)MSR_HVB;
+ }
+ msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
+ msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
+ msr |= (target_ulong)1 << MSR_EP;
+#if defined(DO_SINGLE_STEP) && 0
+ /* Single step trace mode */
+ msr |= (target_ulong)1 << MSR_SE;
+ msr |= (target_ulong)1 << MSR_BE;
+#endif
+#if defined(CONFIG_USER_ONLY)
+ msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
+ msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
+ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
+ msr |= (target_ulong)1 << MSR_PR;
+#else
+ env->excp_prefix = env->hreset_excp_prefix;
+ env->nip = env->hreset_vector | env->excp_prefix;
+ if (env->mmu_model != POWERPC_MMU_REAL) {
+ ppc_tlb_invalidate_all(env);
+ }
+#endif
+ env->msr = msr & env->msr_mask;
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64) {
+ env->msr |= (1ULL << MSR_SF);
+ }
+#endif
+ hreg_compute_hflags(env);
+ env->reserve_addr = (target_ulong)-1ULL;
+ /* Be sure no exception or interrupt is pending */
+ env->pending_interrupts = 0;
+ env->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ /* Flush all TLBs */
+ tlb_flush(env, 1);
}
-static bool ppc_cpu_usable(const ppc_def_t *def)
+static bool ppc_cpu_usable(const PowerPCCPUInfo *def)
{
#if defined(TARGET_PPCEMB)
/* When using the ppcemb target, we only support 440 style cores */
@@ -10105,18 +10224,18 @@ static bool ppc_cpu_usable(const ppc_def_t *def)
return true;
}
-const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
+const char *ppc_find_by_pvr(uint32_t pvr)
{
int i;
- for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
- if (!ppc_cpu_usable(&ppc_defs[i])) {
+ for (i = 0; i < ARRAY_SIZE(ppc_cpus); i++) {
+ if (!ppc_cpu_usable(&ppc_cpus[i])) {
continue;
}
/* If we have an exact match, we're done */
- if (pvr == ppc_defs[i].pvr) {
- return &ppc_defs[i];
+ if (pvr == ppc_cpus[i].pvr) {
+ return ppc_cpus[i].name;
}
}
@@ -10125,14 +10244,13 @@ const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
#include <ctype.h>
-const ppc_def_t *cpu_ppc_find_by_name (const char *name)
+PowerPCCPU *cpu_ppc_find_by_name(const char *name)
{
- const ppc_def_t *ret;
const char *p;
- int i, max, len;
+ int i, len;
- if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
- return kvmppc_host_cpu_def();
+ if (!kvm_enabled() && (strcasecmp(name, "host") == 0)) {
+ return NULL;
}
/* Check if the given name is a PVR */
@@ -10147,36 +10265,104 @@ const ppc_def_t *cpu_ppc_find_by_name (const char *name)
if (!qemu_isxdigit(*p++))
break;
}
- if (i == 8)
- return ppc_find_by_pvr(strtoul(name, NULL, 16));
- }
- ret = NULL;
- max = ARRAY_SIZE(ppc_defs);
- for (i = 0; i < max; i++) {
- if (!ppc_cpu_usable(&ppc_defs[i])) {
- continue;
+ if (i == 8) {
+ name = ppc_find_by_pvr(strtoul(name, NULL, 16));
+ if (name == NULL) {
+ return NULL;
+ }
}
+ }
- if (strcasecmp(name, ppc_defs[i].name) == 0) {
- ret = &ppc_defs[i];
- break;
- }
+ if (object_class_by_name(name) == NULL) {
+ return NULL;
}
+ return POWERPC_CPU(object_new(name));
+}
- return ret;
+typedef struct PowerPCCPUListState {
+ FILE *file;
+ fprintf_function cpu_fprintf;
+} PowerPCCPUListState;
+
+/* Sort by PVR and alphabetically. */
+static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ PowerPCCPUClass *class_a = POWERPC_CPU_CLASS(a);
+ PowerPCCPUClass *class_b = POWERPC_CPU_CLASS(b);
+
+ if (class_a->pvr == class_b->pvr) {
+ return strcasecmp(object_class_get_name(OBJECT_CLASS(class_a)),
+ object_class_get_name(OBJECT_CLASS(class_b)));
+ } else if (class_a->pvr > class_b->pvr) {
+ return 1;
+ } else {
+ return -1;
+ }
+}
+
+static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *klass = data;
+ PowerPCCPUClass *k = POWERPC_CPU_CLASS(klass);
+ PowerPCCPUListState *s = user_data;
+ const char *name;
+
+ name = object_class_get_name(klass);
+ if (strcmp(name, "host") == 0) {
+ return;
+ }
+ (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
+ name, k->pvr);
+}
+
+void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ PowerPCCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_POWERPC_CPU, false);
+ list = g_slist_sort(list, ppc_cpu_list_compare);
+ g_slist_foreach(list, ppc_cpu_list_entry, &s);
+ g_slist_free(list);
+}
+
+static void ppc_register_cpu(const PowerPCCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_POWERPC_CPU,
+ .instance_size = sizeof(PowerPCCPU),
+ .instance_init = ppc_cpu_initfn,
+ .class_size = sizeof(PowerPCCPUClass),
+ .class_init = ppc_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
}
-void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
+static TypeInfo ppc_cpu_type_info = {
+ .name = TYPE_POWERPC_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(PowerPCCPU),
+ .abstract = true,
+ .class_size = sizeof(PowerPCCPUClass),
+};
+
+static void ppc_cpu_register_types(void)
{
- int i, max;
+ int i;
- max = ARRAY_SIZE(ppc_defs);
- for (i = 0; i < max; i++) {
- if (!ppc_cpu_usable(&ppc_defs[i])) {
+ type_register_static(&ppc_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(ppc_cpus); i++) {
+ if (!ppc_cpu_usable(&ppc_cpus[i])) {
continue;
}
-
- (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
- ppc_defs[i].name, ppc_defs[i].pvr);
+ ppc_register_cpu(&ppc_cpus[i]);
}
}
+
+type_init(ppc_cpu_register_types)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 06/12] target-ppc: QOM'ify CPU
@ 2012-03-14 17:53 ` Andreas Färber
0 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel
Cc: open list:Overall, Marcelo Tosatti, Alexander Graf,
open list:PowerPC, Avi Kivity, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-ppc/cpu-qom.h | 84 ++++++++++++++
target-ppc/cpu.h | 25 +----
target-ppc/helper.c | 72 ++----------
target-ppc/kvm.c | 29 +++--
target-ppc/kvm_ppc.h | 6 -
target-ppc/translate.c | 2 +-
target-ppc/translate_init.c | 264 ++++++++++++++++++++++++++++++++++++-------
7 files changed, 342 insertions(+), 140 deletions(-)
create mode 100644 target-ppc/cpu-qom.h
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
new file mode 100644
index 0000000..9236dcc
--- /dev/null
+++ b/target-ppc/cpu-qom.h
@@ -0,0 +1,84 @@
+/*
+ * QEMU PowerPC CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_PPC_CPU_QOM_H
+#define QEMU_PPC_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_POWERPC_CPU "powerpc-cpu"
+
+#define POWERPC_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
+#define POWERPC_CPU(obj) \
+ OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
+#define POWERPC_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
+
+/**
+ * PowerPCCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A PowerPC CPU model.
+ */
+typedef struct PowerPCCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t pvr;
+ uint32_t svr;
+ uint64_t insns_flags;
+ uint64_t insns_flags2;
+ uint64_t msr_mask;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
+ uint32_t flags;
+ int bfd_mach;
+ void (*init_proc)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
+} PowerPCCPUClass;
+
+/**
+ * PowerPCCPU:
+ * @env: Legacy CPU state.
+ *
+ * A PowerPC CPU.
+ */
+typedef struct PowerPCCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUPPCState env;
+} PowerPCCPU;
+
+static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
+{
+ return POWERPC_CPU(container_of(env, PowerPCCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
+
+
+#endif
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ad09cbe..ff28843 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -305,7 +305,6 @@ enum powerpc_input_t {
#define PPC_INPUT(env) (env->bus_model)
/*****************************************************************************/
-typedef struct ppc_def_t ppc_def_t;
typedef struct opc_handler_t opc_handler_t;
/*****************************************************************************/
@@ -877,22 +876,6 @@ enum {
/* The whole PowerPC CPU context */
#define NB_MMU_MODES 3
-struct ppc_def_t {
- const char *name;
- uint32_t pvr;
- uint32_t svr;
- uint64_t insns_flags;
- uint64_t insns_flags2;
- uint64_t msr_mask;
- powerpc_mmu_t mmu_model;
- powerpc_excp_t excp_model;
- powerpc_input_t bus_model;
- uint32_t flags;
- int bfd_mach;
- void (*init_proc)(CPUPPCState *env);
- int (*check_pow)(CPUPPCState *env);
-};
-
struct CPUPPCState {
/* First are the most commonly used resources
* during translated code execution
@@ -1096,6 +1079,8 @@ struct mmu_ctx_t {
};
#endif
+#include "cpu-qom.h"
+
/*****************************************************************************/
CPUPPCState *cpu_ppc_init (const char *cpu_model);
void ppc_translate_init(void);
@@ -1142,9 +1127,9 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
-const ppc_def_t *ppc_find_by_pvr(uint32_t pvr);
-const ppc_def_t *cpu_ppc_find_by_name (const char *name);
-int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
+void ppc_cpu_initfn(Object *obj);
+const char *ppc_find_by_pvr(uint32_t pvr);
+PowerPCCPU *cpu_ppc_find_by_name(const char *name);
/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index bd711b6..7d26cb5 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3138,85 +3138,31 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
void cpu_state_reset(CPUPPCState *env)
{
- target_ulong msr;
-
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- msr = (target_ulong)0;
- if (0) {
- /* XXX: find a suitable condition to enable the hypervisor mode */
- msr |= (target_ulong)MSR_HVB;
- }
- msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
- msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
- msr |= (target_ulong)1 << MSR_EP;
-#if defined (DO_SINGLE_STEP) && 0
- /* Single step trace mode */
- msr |= (target_ulong)1 << MSR_SE;
- msr |= (target_ulong)1 << MSR_BE;
-#endif
-#if defined(CONFIG_USER_ONLY)
- msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
- msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
- msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
- msr |= (target_ulong)1 << MSR_PR;
-#else
- env->excp_prefix = env->hreset_excp_prefix;
- env->nip = env->hreset_vector | env->excp_prefix;
- if (env->mmu_model != POWERPC_MMU_REAL)
- ppc_tlb_invalidate_all(env);
-#endif
- env->msr = msr & env->msr_mask;
-#if defined(TARGET_PPC64)
- if (env->mmu_model & POWERPC_MMU_64)
- env->msr |= (1ULL << MSR_SF);
-#endif
- hreg_compute_hflags(env);
- env->reserve_addr = (target_ulong)-1ULL;
- /* Be sure no exception or interrupt is pending */
- env->pending_interrupts = 0;
- env->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- /* Flush all TLBs */
- tlb_flush(env, 1);
+ cpu_reset(ENV_GET_CPU(env));
}
-CPUPPCState *cpu_ppc_init (const char *cpu_model)
+CPUPPCState *cpu_ppc_init(const char *cpu_model)
{
+ PowerPCCPU *cpu;
CPUPPCState *env;
- const ppc_def_t *def;
- def = cpu_ppc_find_by_name(cpu_model);
- if (!def)
+ cpu = cpu_ppc_find_by_name(cpu_model);
+ if (cpu == NULL) {
return NULL;
+ }
+ env = &cpu->env;
- env = g_malloc0(sizeof(CPUPPCState));
- cpu_exec_init(env);
if (tcg_enabled()) {
ppc_translate_init();
}
- /* Adjust cpu index for SMT */
-#if !defined(CONFIG_USER_ONLY)
- if (kvm_enabled()) {
- int smt = kvmppc_smt_threads();
-
- env->cpu_index = (env->cpu_index / smp_threads)*smt
- + (env->cpu_index % smp_threads);
- }
-#endif /* !CONFIG_USER_ONLY */
- env->cpu_model_str = cpu_model;
- cpu_ppc_register_internal(env, def);
qemu_init_vcpu(env);
return env;
}
-void cpu_ppc_close (CPUPPCState *env)
+void cpu_ppc_close(CPUPPCState *env)
{
/* Should also remove all opcode tables... */
- g_free(env);
+ object_delete(OBJECT(ppc_env_get_cpu(env)));
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index aeb3de9..2ee5bc0 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -902,19 +902,12 @@ static void alter_insns(uint64_t *word, uint64_t flags, bool on)
}
}
-const ppc_def_t *kvmppc_host_cpu_def(void)
+static void kvmppc_host_cpu_class_init(ObjectClass *klass, void *data)
{
- uint32_t host_pvr = mfpvr();
- const ppc_def_t *base_spec;
- ppc_def_t *spec;
+ PowerPCCPUClass *spec = POWERPC_CPU_CLASS(klass);
uint32_t vmx = kvmppc_get_vmx();
uint32_t dfp = kvmppc_get_dfp();
- base_spec = ppc_find_by_pvr(host_pvr);
-
- spec = g_malloc0(sizeof(*spec));
- memcpy(spec, base_spec, sizeof(*spec));
-
/* Now fix up the spec with information we can query from the host */
if (vmx != -1) {
@@ -926,8 +919,6 @@ const ppc_def_t *kvmppc_host_cpu_def(void)
/* Only override when we know what the host supports */
alter_insns(&spec->insns_flags2, PPC2_DFP, dfp);
}
-
- return spec;
}
bool kvm_arch_stop_on_emulation_error(CPUPPCState *env)
@@ -944,3 +935,19 @@ int kvm_arch_on_sigbus(int code, void *addr)
{
return 1;
}
+
+static void kvmppc_register_types(void)
+{
+ TypeInfo type = {
+ .name = "host",
+ .instance_size = sizeof(PowerPCCPU),
+ .instance_init = ppc_cpu_initfn,
+ .class_size = sizeof(PowerPCCPUClass),
+ .class_init = kvmppc_host_cpu_class_init,
+ };
+ uint32_t host_pvr = mfpvr();
+ type.parent = ppc_find_by_pvr(host_pvr);
+ type_register_static(&type);
+}
+
+type_init(kvmppc_register_types)
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 8f1267c..ce5be6e 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -28,7 +28,6 @@ off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem);
void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd);
int kvmppc_remove_spapr_tce(void *table, int pfd, uint32_t window_size);
#endif /* !CONFIG_USER_ONLY */
-const ppc_def_t *kvmppc_host_cpu_def(void);
#else
@@ -90,11 +89,6 @@ static inline int kvmppc_remove_spapr_tce(void *table, int pfd,
}
#endif /* !CONFIG_USER_ONLY */
-static inline const ppc_def_t *kvmppc_host_cpu_def(void)
-{
- return NULL;
-}
-
#endif
#ifndef CONFIG_KVM
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3ec59a7..e43160d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9272,8 +9272,8 @@ GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
};
-#include "translate_init.c"
#include "helper_regs.h"
+#include "translate_init.c"
/*****************************************************************************/
/* Misc PowerPC helpers */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1ec6f42..52264c8 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2003-2007 Jocelyn Mayer
* Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -27,6 +28,7 @@
#include "gdbstub.h"
#include <kvm.h>
#include "kvm_ppc.h"
+#include "cpus.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
@@ -7583,6 +7585,51 @@ enum {
/*****************************************************************************/
/* PowerPC CPU definitions */
+
+typedef struct PowerPCCPUInfo PowerPCCPUInfo;
+
+struct PowerPCCPUInfo {
+ const char *name;
+ uint32_t pvr;
+ uint32_t svr;
+ uint64_t insns_flags;
+ uint64_t insns_flags2;
+ uint64_t msr_mask;
+ powerpc_mmu_t mmu_model;
+ powerpc_excp_t excp_model;
+ powerpc_input_t bus_model;
+ uint32_t flags;
+ int bfd_mach;
+ void (*init_proc)(CPUPPCState *env);
+ int (*check_pow)(CPUPPCState *env);
+};
+
+static void ppc_cpu_reset(CPUState *cpu);
+
+static void ppc_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ PowerPCCPUClass *k = POWERPC_CPU_CLASS(klass);
+ const PowerPCCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = ppc_cpu_reset;
+
+ k->pvr = info->pvr;
+ k->svr = info->svr;
+ k->insns_flags = info->insns_flags;
+ k->insns_flags2 = info->insns_flags2;
+ k->msr_mask = info->msr_mask;
+ k->mmu_model = info->mmu_model;
+ k->excp_model = info->excp_model;
+ k->bus_model = info->bus_model;
+ k->flags = info->flags;
+ k->bfd_mach = info->bfd_mach;
+
+ k->init_proc = info->init_proc;
+ k->check_pow = info->check_pow;
+}
+
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
{ \
.name = _name, \
@@ -7602,7 +7649,7 @@ enum {
#define POWERPC_DEF(_name, _pvr, _type) \
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
-static const ppc_def_t ppc_defs[] = {
+static const PowerPCCPUInfo ppc_cpus[] = {
/* Embedded PowerPC */
/* PowerPC 401 family */
/* Generic PowerPC 401 */
@@ -9280,7 +9327,7 @@ static const ppc_def_t ppc_defs[] = {
/*****************************************************************************/
/* Generic CPU instantiation routine */
-static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
+static void init_ppc_proc(CPUPPCState *env, PowerPCCPUClass *def)
{
#if !defined(CONFIG_USER_ONLY)
int i;
@@ -9672,7 +9719,7 @@ static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
}
/*****************************************************************************/
-static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
+static int create_ppc_opcodes(CPUPPCState *env, const PowerPCCPUClass *def)
{
opcode_t *opc;
@@ -9884,8 +9931,26 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 0;
}
-int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
+void ppc_cpu_initfn(Object *obj)
{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+ PowerPCCPUClass *def = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ /* Adjust cpu index for SMT */
+#if !defined(CONFIG_USER_ONLY)
+ if (kvm_enabled()) {
+ int smt = kvmppc_smt_threads();
+
+ env->cpu_index = (env->cpu_index / smp_threads) * smt
+ + (env->cpu_index % smp_threads);
+ }
+#endif /* !CONFIG_USER_ONLY */
+
env->msr_mask = def->msr_mask;
env->mmu_model = def->mmu_model;
env->excp_model = def->excp_model;
@@ -9911,8 +9976,9 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
env->flags = def->flags;
env->bfd_mach = def->bfd_mach;
env->check_pow = def->check_pow;
- if (create_ppc_opcodes(env, def) < 0)
- return -1;
+ if (create_ppc_opcodes(env, def) < 0) {
+ abort();
+ }
init_ppc_proc(env, def);
if (def->insns_flags & PPC_FLOAT) {
@@ -10089,11 +10155,64 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
dump_ppc_sprs(env);
fflush(stdout);
#endif
+}
- return 0;
+static void ppc_cpu_reset(CPUState *c)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(c);
+ PowerPCCPUClass *klass = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+ target_ulong msr;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ msr = (target_ulong)0;
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ msr |= (target_ulong)MSR_HVB;
+ }
+ msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
+ msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
+ msr |= (target_ulong)1 << MSR_EP;
+#if defined(DO_SINGLE_STEP) && 0
+ /* Single step trace mode */
+ msr |= (target_ulong)1 << MSR_SE;
+ msr |= (target_ulong)1 << MSR_BE;
+#endif
+#if defined(CONFIG_USER_ONLY)
+ msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
+ msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
+ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
+ msr |= (target_ulong)1 << MSR_PR;
+#else
+ env->excp_prefix = env->hreset_excp_prefix;
+ env->nip = env->hreset_vector | env->excp_prefix;
+ if (env->mmu_model != POWERPC_MMU_REAL) {
+ ppc_tlb_invalidate_all(env);
+ }
+#endif
+ env->msr = msr & env->msr_mask;
+#if defined(TARGET_PPC64)
+ if (env->mmu_model & POWERPC_MMU_64) {
+ env->msr |= (1ULL << MSR_SF);
+ }
+#endif
+ hreg_compute_hflags(env);
+ env->reserve_addr = (target_ulong)-1ULL;
+ /* Be sure no exception or interrupt is pending */
+ env->pending_interrupts = 0;
+ env->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ /* Flush all TLBs */
+ tlb_flush(env, 1);
}
-static bool ppc_cpu_usable(const ppc_def_t *def)
+static bool ppc_cpu_usable(const PowerPCCPUInfo *def)
{
#if defined(TARGET_PPCEMB)
/* When using the ppcemb target, we only support 440 style cores */
@@ -10105,18 +10224,18 @@ static bool ppc_cpu_usable(const ppc_def_t *def)
return true;
}
-const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
+const char *ppc_find_by_pvr(uint32_t pvr)
{
int i;
- for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
- if (!ppc_cpu_usable(&ppc_defs[i])) {
+ for (i = 0; i < ARRAY_SIZE(ppc_cpus); i++) {
+ if (!ppc_cpu_usable(&ppc_cpus[i])) {
continue;
}
/* If we have an exact match, we're done */
- if (pvr == ppc_defs[i].pvr) {
- return &ppc_defs[i];
+ if (pvr == ppc_cpus[i].pvr) {
+ return ppc_cpus[i].name;
}
}
@@ -10125,14 +10244,13 @@ const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
#include <ctype.h>
-const ppc_def_t *cpu_ppc_find_by_name (const char *name)
+PowerPCCPU *cpu_ppc_find_by_name(const char *name)
{
- const ppc_def_t *ret;
const char *p;
- int i, max, len;
+ int i, len;
- if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
- return kvmppc_host_cpu_def();
+ if (!kvm_enabled() && (strcasecmp(name, "host") == 0)) {
+ return NULL;
}
/* Check if the given name is a PVR */
@@ -10147,36 +10265,104 @@ const ppc_def_t *cpu_ppc_find_by_name (const char *name)
if (!qemu_isxdigit(*p++))
break;
}
- if (i == 8)
- return ppc_find_by_pvr(strtoul(name, NULL, 16));
- }
- ret = NULL;
- max = ARRAY_SIZE(ppc_defs);
- for (i = 0; i < max; i++) {
- if (!ppc_cpu_usable(&ppc_defs[i])) {
- continue;
+ if (i == 8) {
+ name = ppc_find_by_pvr(strtoul(name, NULL, 16));
+ if (name == NULL) {
+ return NULL;
+ }
}
+ }
- if (strcasecmp(name, ppc_defs[i].name) == 0) {
- ret = &ppc_defs[i];
- break;
- }
+ if (object_class_by_name(name) == NULL) {
+ return NULL;
}
+ return POWERPC_CPU(object_new(name));
+}
- return ret;
+typedef struct PowerPCCPUListState {
+ FILE *file;
+ fprintf_function cpu_fprintf;
+} PowerPCCPUListState;
+
+/* Sort by PVR and alphabetically. */
+static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ PowerPCCPUClass *class_a = POWERPC_CPU_CLASS(a);
+ PowerPCCPUClass *class_b = POWERPC_CPU_CLASS(b);
+
+ if (class_a->pvr == class_b->pvr) {
+ return strcasecmp(object_class_get_name(OBJECT_CLASS(class_a)),
+ object_class_get_name(OBJECT_CLASS(class_b)));
+ } else if (class_a->pvr > class_b->pvr) {
+ return 1;
+ } else {
+ return -1;
+ }
+}
+
+static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *klass = data;
+ PowerPCCPUClass *k = POWERPC_CPU_CLASS(klass);
+ PowerPCCPUListState *s = user_data;
+ const char *name;
+
+ name = object_class_get_name(klass);
+ if (strcmp(name, "host") == 0) {
+ return;
+ }
+ (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
+ name, k->pvr);
+}
+
+void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ PowerPCCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_POWERPC_CPU, false);
+ list = g_slist_sort(list, ppc_cpu_list_compare);
+ g_slist_foreach(list, ppc_cpu_list_entry, &s);
+ g_slist_free(list);
+}
+
+static void ppc_register_cpu(const PowerPCCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_POWERPC_CPU,
+ .instance_size = sizeof(PowerPCCPU),
+ .instance_init = ppc_cpu_initfn,
+ .class_size = sizeof(PowerPCCPUClass),
+ .class_init = ppc_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
}
-void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
+static TypeInfo ppc_cpu_type_info = {
+ .name = TYPE_POWERPC_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(PowerPCCPU),
+ .abstract = true,
+ .class_size = sizeof(PowerPCCPUClass),
+};
+
+static void ppc_cpu_register_types(void)
{
- int i, max;
+ int i;
- max = ARRAY_SIZE(ppc_defs);
- for (i = 0; i < max; i++) {
- if (!ppc_cpu_usable(&ppc_defs[i])) {
+ type_register_static(&ppc_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(ppc_cpus); i++) {
+ if (!ppc_cpu_usable(&ppc_cpus[i])) {
continue;
}
-
- (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
- ppc_defs[i].name, ppc_defs[i].pvr);
+ ppc_register_cpu(&ppc_cpus[i]);
}
}
+
+type_init(ppc_cpu_register_types)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
` (10 subsequent siblings)
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel
Cc: Andreas Färber, Alexander Graf, Avi Kivity, Marcelo Tosatti,
open list:PowerPC, open list:Overall
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-ppc/cpu.h | 1 +
target-ppc/helper.c | 1 -
target-ppc/kvm.c | 1 +
target-ppc/translate_init.c | 6 ++++++
4 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ff28843..3ff2156 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1128,6 +1128,7 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
void ppc_cpu_initfn(Object *obj);
+void ppc_cpu_finalize(Object *obj);
const char *ppc_find_by_pvr(uint32_t pvr);
PowerPCCPU *cpu_ppc_find_by_name(const char *name);
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 7d26cb5..1467cf7 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3163,6 +3163,5 @@ CPUPPCState *cpu_ppc_init(const char *cpu_model)
void cpu_ppc_close(CPUPPCState *env)
{
- /* Should also remove all opcode tables... */
object_delete(OBJECT(ppc_env_get_cpu(env)));
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 2ee5bc0..8be235b 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -942,6 +942,7 @@ static void kvmppc_register_types(void)
.name = "host",
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_initfn,
+ .instance_finalize = ppc_cpu_finalize,
.class_size = sizeof(PowerPCCPUClass),
.class_init = kvmppc_host_cpu_class_init,
};
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 52264c8..c167595 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10212,6 +10212,11 @@ static void ppc_cpu_reset(CPUState *c)
tlb_flush(env, 1);
}
+void ppc_cpu_finalize(Object *obj)
+{
+ /* Should remove all opcode tables... */
+}
+
static bool ppc_cpu_usable(const PowerPCCPUInfo *def)
{
#if defined(TARGET_PPCEMB)
@@ -10336,6 +10341,7 @@ static void ppc_register_cpu(const PowerPCCPUInfo *info)
.parent = TYPE_POWERPC_CPU,
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_initfn,
+ .instance_finalize = ppc_cpu_finalize,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
.class_data = (void *)info,
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU
@ 2012-03-14 17:53 ` Andreas Färber
0 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel
Cc: open list:Overall, Marcelo Tosatti, Alexander Graf,
open list:PowerPC, Avi Kivity, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-ppc/cpu.h | 1 +
target-ppc/helper.c | 1 -
target-ppc/kvm.c | 1 +
target-ppc/translate_init.c | 6 ++++++
4 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ff28843..3ff2156 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1128,6 +1128,7 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
void ppc_cpu_initfn(Object *obj);
+void ppc_cpu_finalize(Object *obj);
const char *ppc_find_by_pvr(uint32_t pvr);
PowerPCCPU *cpu_ppc_find_by_name(const char *name);
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 7d26cb5..1467cf7 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -3163,6 +3163,5 @@ CPUPPCState *cpu_ppc_init(const char *cpu_model)
void cpu_ppc_close(CPUPPCState *env)
{
- /* Should also remove all opcode tables... */
object_delete(OBJECT(ppc_env_get_cpu(env)));
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 2ee5bc0..8be235b 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -942,6 +942,7 @@ static void kvmppc_register_types(void)
.name = "host",
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_initfn,
+ .instance_finalize = ppc_cpu_finalize,
.class_size = sizeof(PowerPCCPUClass),
.class_init = kvmppc_host_cpu_class_init,
};
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 52264c8..c167595 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10212,6 +10212,11 @@ static void ppc_cpu_reset(CPUState *c)
tlb_flush(env, 1);
}
+void ppc_cpu_finalize(Object *obj)
+{
+ /* Should remove all opcode tables... */
+}
+
static bool ppc_cpu_usable(const PowerPCCPUInfo *def)
{
#if defined(TARGET_PPCEMB)
@@ -10336,6 +10341,7 @@ static void ppc_register_cpu(const PowerPCCPUInfo *info)
.parent = TYPE_POWERPC_CPU,
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_initfn,
+ .instance_finalize = ppc_cpu_finalize,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
.class_data = (void *)info,
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (6 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 09/12] target-lm32: " Andreas Färber
` (3 subsequent siblings)
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
Let cris_cpu_list() enumerate CPU classes sorted by version.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-cris/cpu-qom.h | 73 ++++++++++++++++++++++++
target-cris/cpu.c | 144 +++++++++++++++++++++++++++++++++++++++++++++++
target-cris/cpu.h | 2 +
target-cris/translate.c | 93 ++++++++++++++----------------
5 files changed, 264 insertions(+), 49 deletions(-)
create mode 100644 target-cris/cpu-qom.h
create mode 100644 target-cris/cpu.c
diff --git a/Makefile.target b/Makefile.target
index c655091..3b7a4da 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -89,6 +89,7 @@ libobj-$(CONFIG_NEED_MMU) += mmu.o
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ALPHA) += cpu.o
libobj-$(TARGET_ARM) += cpu.o
+libobj-$(TARGET_CRIS) += cpu.o
libobj-$(TARGET_M68K) += cpu.o
ifeq ($(TARGET_BASE_ARCH), mips)
libobj-y += cpu.o
diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
new file mode 100644
index 0000000..bbd0c71
--- /dev/null
+++ b/target-cris/cpu-qom.h
@@ -0,0 +1,73 @@
+/*
+ * QEMU CRIS CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_CRIS_CPU_QOM_H
+#define QEMU_CRIS_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_CRIS_CPU "cris-cpu"
+
+#define CRIS_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(CRISCPUClass, (klass), TYPE_CRIS_CPU)
+#define CRIS_CPU(obj) \
+ OBJECT_CHECK(CRISCPU, (obj), TYPE_CRIS_CPU)
+#define CRIS_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(CRISCPUClass, (obj), TYPE_CRIS_CPU)
+
+/**
+ * CRISCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A CRIS CPU model.
+ */
+typedef struct CRISCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t vr;
+} CRISCPUClass;
+
+/**
+ * CRISCPU:
+ * @env: Legacy CPU state.
+ *
+ * A CRIS CPU.
+ */
+typedef struct CRISCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUCRISState env;
+} CRISCPU;
+
+static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
+{
+ return CRIS_CPU(container_of(env, CRISCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
+
+
+#endif
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
new file mode 100644
index 0000000..01bce90
--- /dev/null
+++ b/target-cris/cpu.c
@@ -0,0 +1,144 @@
+/*
+ * QEMU CRIS CPU
+ *
+ * Copyright (c) 2008 AXIS Communications AB
+ * Written by Edgar E. Iglesias.
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+#include "mmu.h"
+
+static void cris_cpu_reset(CPUState *c)
+{
+ CRISCPU *cpu = CRIS_CPU(c);
+ CRISCPUClass *klass = CRIS_CPU_GET_CLASS(cpu);
+ CPUCRISState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUCRISState, breakpoints));
+ env->pregs[PR_VR] = klass->vr;
+ tlb_flush(env, 1);
+
+#if defined(CONFIG_USER_ONLY)
+ /* start in user mode with interrupts enabled. */
+ env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
+#else
+ cris_mmu_init(env);
+ env->pregs[PR_CCS] = 0;
+#endif
+}
+
+/* CPU models */
+
+typedef struct CRISCPUInfo {
+ const char *name;
+ uint32_t vr;
+} CRISCPUInfo;
+
+static const CRISCPUInfo cris_cpus[] = {
+ {
+ .name = "crisv8",
+ .vr = 8,
+ },
+ {
+ .name = "crisv9",
+ .vr = 9,
+ },
+ {
+ .name = "crisv10",
+ .vr = 10,
+ },
+ {
+ .name = "crisv11",
+ .vr = 11,
+ },
+ {
+ .name = "crisv32",
+ .vr = 32,
+ },
+};
+
+static void cris_cpu_initfn(Object *obj)
+{
+ CRISCPU *cpu = CRIS_CPU(obj);
+ CRISCPUClass *klass = CRIS_CPU_GET_CLASS(cpu);
+ CPUCRISState *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ env->pregs[PR_VR] = klass->vr;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void cris_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ CRISCPUClass *k = CRIS_CPU_CLASS(klass);
+ const CRISCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = cris_cpu_reset;
+
+ k->vr = info->vr;
+}
+
+static void cpu_register(const CRISCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_CRIS_CPU,
+ .instance_size = sizeof(CRISCPU),
+ .instance_init = cris_cpu_initfn,
+ .class_size = sizeof(CRISCPUClass),
+ .class_init = cris_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo cris_cpu_type_info = {
+ .name = TYPE_CRIS_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(CRISCPU),
+ .abstract = true,
+ .class_size = sizeof(CRISCPUClass),
+};
+
+static void cris_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&cris_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(cris_cpus); i++) {
+ cpu_register(&cris_cpus[i]);
+ }
+}
+
+type_init(cris_cpu_register_types)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 31899c2..5449cc4 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -169,6 +169,8 @@ typedef struct CPUCRISState {
void *load_info;
} CPUCRISState;
+#include "cpu-qom.h"
+
CPUCRISState *cpu_cris_init(const char *cpu_model);
int cpu_cris_exec(CPUCRISState *s);
void cpu_cris_close(CPUCRISState *s);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 7224f46..4097ecd 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3470,50 +3470,63 @@ void cpu_dump_state (CPUCRISState *env, FILE *f, fprintf_function cpu_fprintf,
}
-struct
-{
- uint32_t vr;
- const char *name;
-} cris_cores[] = {
- {8, "crisv8"},
- {9, "crisv9"},
- {10, "crisv10"},
- {11, "crisv11"},
- {32, "crisv32"},
-};
+typedef struct CRISCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} CRISCPUListState;
-void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+/* Sort by version. */
+static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- unsigned int i;
+ CRISCPUClass *class_a = CRIS_CPU_CLASS(a);
+ CRISCPUClass *class_b = CRIS_CPU_CLASS(b);
- (*cpu_fprintf)(f, "Available CPUs:\n");
- for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
- (*cpu_fprintf)(f, " %s\n", cris_cores[i].name);
+ if (class_a->vr == class_b->vr) {
+ return 0;
+ } else if (class_a->vr > class_b->vr) {
+ return 1;
+ } else {
+ return -1;
}
}
-static uint32_t vr_by_name(const char *name)
+static void cris_cpu_list_entry(gpointer data, gpointer user_data)
{
- unsigned int i;
- for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
- if (strcmp(name, cris_cores[i].name) == 0) {
- return cris_cores[i].vr;
- }
- }
- return 32;
+ ObjectClass *klass = data;
+ CRISCPUListState *s = user_data;
+
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
}
-CPUCRISState *cpu_cris_init (const char *cpu_model)
+void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
- CPUCRISState *env;
+ CRISCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_CRIS_CPU, false);
+ list = g_slist_sort(list, cris_cpu_list_compare);
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ g_slist_foreach(list, cris_cpu_list_entry, &s);
+ g_slist_free(list);
+}
+
+CPUCRISState *cpu_cris_init(const char *cpu_model)
+{
+ CRISCPU *cpu;
+ CPUCRISState *env;
static int tcg_initialized = 0;
int i;
- env = g_malloc0(sizeof(CPUCRISState));
+ if (object_class_by_name(cpu_model) == NULL) {
+ return NULL;
+ }
+ cpu = CRIS_CPU(object_new(cpu_model));
+ env = &cpu->env;
- env->pregs[PR_VR] = vr_by_name(cpu_model);
- cpu_exec_init(env);
- cpu_state_reset(env);
qemu_init_vcpu(env);
if (tcg_initialized)
@@ -3575,25 +3588,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
void cpu_state_reset(CPUCRISState *env)
{
- uint32_t vr;
-
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- vr = env->pregs[PR_VR];
- memset(env, 0, offsetof(CPUCRISState, breakpoints));
- env->pregs[PR_VR] = vr;
- tlb_flush(env, 1);
-
-#if defined(CONFIG_USER_ONLY)
- /* start in user mode with interrupts enabled. */
- env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
-#else
- cris_mmu_init(env);
- env->pregs[PR_CCS] = 0;
-#endif
+ cpu_reset(ENV_GET_CPU(env));
}
void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (7 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-15 22:42 ` Michael Walle
2012-03-14 17:53 ` [Qemu-devel] [RFC 10/12] target-microblaze: " Andreas Färber
` (2 subsequent siblings)
11 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Michael Walle, Andreas Färber
Let cpu_lm32_list() enumerate CPU classes sorted alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-lm32/cpu-qom.h | 77 ++++++++++++++++++++
target-lm32/cpu.c | 188 +++++++++++++++++++++++++++++++++++++++++++++++++
target-lm32/cpu.h | 1 +
target-lm32/helper.c | 142 ++++++++-----------------------------
5 files changed, 297 insertions(+), 112 deletions(-)
create mode 100644 target-lm32/cpu-qom.h
create mode 100644 target-lm32/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 3b7a4da..8c8f4a8 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -90,6 +90,7 @@ libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ALPHA) += cpu.o
libobj-$(TARGET_ARM) += cpu.o
libobj-$(TARGET_CRIS) += cpu.o
+libobj-$(TARGET_LM32) += cpu.o
libobj-$(TARGET_M68K) += cpu.o
ifeq ($(TARGET_BASE_ARCH), mips)
libobj-y += cpu.o
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
new file mode 100644
index 0000000..dc3d434
--- /dev/null
+++ b/target-lm32/cpu-qom.h
@@ -0,0 +1,77 @@
+/*
+ * QEMU LatticeMico32 CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_LM32_CPU_QOM_H
+#define QEMU_LM32_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_LM32_CPU "lm32-cpu"
+
+#define LM32_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
+#define LM32_CPU(obj) \
+ OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU)
+#define LM32_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU)
+
+/**
+ * LM32CPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A LatticeMico32 CPU model.
+ */
+typedef struct LM32CPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t revision;
+ uint8_t num_interrupts;
+ uint8_t num_breakpoints;
+ uint8_t num_watchpoints;
+ uint32_t features;
+} LM32CPUClass;
+
+/**
+ * LM32CPU:
+ * @env: Legacy CPU state.
+ *
+ * A LatticeMico32 CPU.
+ */
+typedef struct LM32CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPULM32State env;
+} LM32CPU;
+
+static inline LM32CPU *cris_env_get_cpu(CPULM32State *env)
+{
+ return LM32_CPU(container_of(env, LM32CPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
+
+
+#endif
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
new file mode 100644
index 0000000..7f5308a
--- /dev/null
+++ b/target-lm32/cpu.c
@@ -0,0 +1,188 @@
+/*
+ * QEMU LatticeMico32 CPU
+ *
+ * Copyright (c) 2010 Michael Walle <michael@walle.cc>
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void lm32_cpu_reset(CPUState *c)
+{
+}
+
+/* CPU models */
+
+typedef struct LM32CPUInfo {
+ const char *name;
+ uint32_t revision;
+ uint8_t num_interrupts;
+ uint8_t num_breakpoints;
+ uint8_t num_watchpoints;
+ uint32_t features;
+} LM32CPUInfo;
+
+static const LM32CPUInfo lm32_cpus[] = {
+ {
+ .name = "lm32-basic",
+ .revision = 3,
+ .num_interrupts = 32,
+ .num_breakpoints = 4,
+ .num_watchpoints = 4,
+ .features = (LM32_FEATURE_SHIFT
+ | LM32_FEATURE_SIGN_EXTEND
+ | LM32_FEATURE_CYCLE_COUNT),
+ },
+ {
+ .name = "lm32-standard",
+ .revision = 3,
+ .num_interrupts = 32,
+ .num_breakpoints = 4,
+ .num_watchpoints = 4,
+ .features = (LM32_FEATURE_MULTIPLY
+ | LM32_FEATURE_DIVIDE
+ | LM32_FEATURE_SHIFT
+ | LM32_FEATURE_SIGN_EXTEND
+ | LM32_FEATURE_I_CACHE
+ | LM32_FEATURE_CYCLE_COUNT),
+ },
+ {
+ .name = "lm32-full",
+ .revision = 3,
+ .num_interrupts = 32,
+ .num_breakpoints = 4,
+ .num_watchpoints = 4,
+ .features = (LM32_FEATURE_MULTIPLY
+ | LM32_FEATURE_DIVIDE
+ | LM32_FEATURE_SHIFT
+ | LM32_FEATURE_SIGN_EXTEND
+ | LM32_FEATURE_I_CACHE
+ | LM32_FEATURE_D_CACHE
+ | LM32_FEATURE_CYCLE_COUNT),
+ }
+};
+
+static uint32_t cfg_by_class(LM32CPUClass *def)
+{
+ uint32_t cfg = 0;
+
+ if (def->features & LM32_FEATURE_MULTIPLY) {
+ cfg |= CFG_M;
+ }
+
+ if (def->features & LM32_FEATURE_DIVIDE) {
+ cfg |= CFG_D;
+ }
+
+ if (def->features & LM32_FEATURE_SHIFT) {
+ cfg |= CFG_S;
+ }
+
+ if (def->features & LM32_FEATURE_SIGN_EXTEND) {
+ cfg |= CFG_X;
+ }
+
+ if (def->features & LM32_FEATURE_I_CACHE) {
+ cfg |= CFG_IC;
+ }
+
+ if (def->features & LM32_FEATURE_D_CACHE) {
+ cfg |= CFG_DC;
+ }
+
+ if (def->features & LM32_FEATURE_CYCLE_COUNT) {
+ cfg |= CFG_CC;
+ }
+
+ cfg |= (def->num_interrupts << CFG_INT_SHIFT);
+ cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
+ cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
+ cfg |= (def->revision << CFG_REV_SHIFT);
+
+ return cfg;
+}
+
+static void lm32_cpu_initfn(Object *obj)
+{
+ LM32CPU *cpu = LM32_CPU(obj);
+ LM32CPUClass *klass = LM32_CPU_GET_CLASS(cpu);
+ CPULM32State *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ env->features = klass->features;
+ env->num_bps = klass->num_breakpoints;
+ env->num_wps = klass->num_watchpoints;
+ env->cfg = cfg_by_class(klass);
+ env->flags = 0;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void lm32_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ LM32CPUClass *k = LM32_CPU_CLASS(klass);
+ const LM32CPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = lm32_cpu_reset;
+
+ k->revision = info->revision;
+ k->num_interrupts = info->num_interrupts;
+ k->num_breakpoints = info->num_breakpoints;
+ k->num_watchpoints = info->num_watchpoints;
+ k->features = info->features;
+}
+
+static void cpu_register(const LM32CPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_LM32_CPU,
+ .instance_size = sizeof(LM32CPU),
+ .instance_init = lm32_cpu_initfn,
+ .class_size = sizeof(LM32CPUClass),
+ .class_init = lm32_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo lm32_cpu_type_info = {
+ .name = TYPE_LM32_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(LM32CPU),
+ .abstract = true,
+ .class_size = sizeof(LM32CPUClass),
+};
+
+static void lm32_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&lm32_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
+ cpu_register(&lm32_cpus[i]);
+ }
+}
+
+type_init(lm32_cpu_register_types)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 0902a24..c1be305 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -184,6 +184,7 @@ typedef struct CPULM32State {
} CPULM32State;
+#include "cpu-qom.h"
CPULM32State *cpu_lm32_init(const char *cpu_model);
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 5db8f8d..e89cc0e 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -80,139 +80,57 @@ void do_interrupt(CPULM32State *env)
}
}
-typedef struct {
- const char *name;
- uint32_t revision;
- uint8_t num_interrupts;
- uint8_t num_breakpoints;
- uint8_t num_watchpoints;
- uint32_t features;
-} LM32Def;
+typedef struct LM32CPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} LM32CPUListState;
-static const LM32Def lm32_defs[] = {
- {
- .name = "lm32-basic",
- .revision = 3,
- .num_interrupts = 32,
- .num_breakpoints = 4,
- .num_watchpoints = 4,
- .features = (LM32_FEATURE_SHIFT
- | LM32_FEATURE_SIGN_EXTEND
- | LM32_FEATURE_CYCLE_COUNT),
- },
- {
- .name = "lm32-standard",
- .revision = 3,
- .num_interrupts = 32,
- .num_breakpoints = 4,
- .num_watchpoints = 4,
- .features = (LM32_FEATURE_MULTIPLY
- | LM32_FEATURE_DIVIDE
- | LM32_FEATURE_SHIFT
- | LM32_FEATURE_SIGN_EXTEND
- | LM32_FEATURE_I_CACHE
- | LM32_FEATURE_CYCLE_COUNT),
- },
- {
- .name = "lm32-full",
- .revision = 3,
- .num_interrupts = 32,
- .num_breakpoints = 4,
- .num_watchpoints = 4,
- .features = (LM32_FEATURE_MULTIPLY
- | LM32_FEATURE_DIVIDE
- | LM32_FEATURE_SHIFT
- | LM32_FEATURE_SIGN_EXTEND
- | LM32_FEATURE_I_CACHE
- | LM32_FEATURE_D_CACHE
- | LM32_FEATURE_CYCLE_COUNT),
- }
-};
-
-void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
+/* Sort alphabetically. */
+static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- int i;
+ ObjectClass *class_a = OBJECT_CLASS(a);
+ ObjectClass *class_b = OBJECT_CLASS(b);
- cpu_fprintf(f, "Available CPUs:\n");
- for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
- cpu_fprintf(f, " %s\n", lm32_defs[i].name);
- }
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
}
-static const LM32Def *cpu_lm32_find_by_name(const char *name)
+static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
- if (strcasecmp(name, lm32_defs[i].name) == 0) {
- return &lm32_defs[i];
- }
- }
+ ObjectClass *klass = data;
+ LM32CPUListState *s = user_data;
- return NULL;
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
}
-static uint32_t cfg_by_def(const LM32Def *def)
+void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
{
- uint32_t cfg = 0;
-
- if (def->features & LM32_FEATURE_MULTIPLY) {
- cfg |= CFG_M;
- }
+ LM32CPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
- if (def->features & LM32_FEATURE_DIVIDE) {
- cfg |= CFG_D;
- }
-
- if (def->features & LM32_FEATURE_SHIFT) {
- cfg |= CFG_S;
- }
-
- if (def->features & LM32_FEATURE_SIGN_EXTEND) {
- cfg |= CFG_X;
- }
-
- if (def->features & LM32_FEATURE_I_CACHE) {
- cfg |= CFG_IC;
- }
-
- if (def->features & LM32_FEATURE_D_CACHE) {
- cfg |= CFG_DC;
- }
-
- if (def->features & LM32_FEATURE_CYCLE_COUNT) {
- cfg |= CFG_CC;
- }
-
- cfg |= (def->num_interrupts << CFG_INT_SHIFT);
- cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
- cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
- cfg |= (def->revision << CFG_REV_SHIFT);
-
- return cfg;
+ list = object_class_get_list(TYPE_LM32_CPU, false);
+ list = g_slist_sort(list, lm32_cpu_list_compare);
+ cpu_fprintf(f, "Available CPUs:\n");
+ g_slist_foreach(list, lm32_cpu_list_entry, &s);
+ g_slist_free(list);
}
CPULM32State *cpu_lm32_init(const char *cpu_model)
{
+ LM32CPU *cpu;
CPULM32State *env;
- const LM32Def *def;
static int tcg_initialized;
- def = cpu_lm32_find_by_name(cpu_model);
- if (!def) {
+ if (object_class_by_name(cpu_model) == NULL) {
return NULL;
}
+ cpu = LM32_CPU(object_new(cpu_model));
+ env = &cpu->env;
- env = g_malloc0(sizeof(CPULM32State));
-
- env->features = def->features;
- env->num_bps = def->num_breakpoints;
- env->num_wps = def->num_watchpoints;
- env->cfg = cfg_by_def(def);
- env->flags = 0;
-
- cpu_exec_init(env);
- cpu_state_reset(env);
qemu_init_vcpu(env);
if (!tcg_initialized) {
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 10/12] target-microblaze: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (8 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] [RFC 09/12] target-lm32: " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
11 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
There were no CPU models, so make TYPE_MICROBLAZE_CPU non-abstract.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
target-microblaze/cpu-qom.h | 71 ++++++++++++++++++++++++
target-microblaze/cpu.c | 120 +++++++++++++++++++++++++++++++++++++++++
target-microblaze/cpu.h | 2 +
target-microblaze/translate.c | 58 ++------------------
5 files changed, 199 insertions(+), 53 deletions(-)
create mode 100644 target-microblaze/cpu-qom.h
create mode 100644 target-microblaze/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 8c8f4a8..82171ca 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -92,6 +92,7 @@ libobj-$(TARGET_ARM) += cpu.o
libobj-$(TARGET_CRIS) += cpu.o
libobj-$(TARGET_LM32) += cpu.o
libobj-$(TARGET_M68K) += cpu.o
+libobj-$(TARGET_MICROBLAZE) += cpu.o
ifeq ($(TARGET_BASE_ARCH), mips)
libobj-y += cpu.o
endif
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
new file mode 100644
index 0000000..576be10
--- /dev/null
+++ b/target-microblaze/cpu-qom.h
@@ -0,0 +1,71 @@
+/*
+ * QEMU MicroBlaze CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_MICROBLAZE_CPU_QOM_H
+#define QEMU_MICROBLAZE_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
+
+#define MICROBLAZE_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
+#define MICROBLAZE_CPU(obj) \
+ OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU)
+#define MICROBLAZE_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU)
+
+/**
+ * MicroBlazeCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A MicroBlaze CPU model.
+ */
+typedef struct MicroBlazeCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+} MicroBlazeCPUClass;
+
+/**
+ * MicroBlazeCPU:
+ * @env: Legacy CPU state.
+ *
+ * A MicroBlaze CPU.
+ */
+typedef struct MicroBlazeCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUMBState env;
+} MicroBlazeCPU;
+
+static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
+{
+ return MICROBLAZE_CPU(container_of(env, MicroBlazeCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
+
+
+#endif
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
new file mode 100644
index 0000000..ae55376
--- /dev/null
+++ b/target-microblaze/cpu.c
@@ -0,0 +1,120 @@
+/*
+ * QEMU MicroBlaze CPU
+ *
+ * Copyright (c) 2009 Edgar E. Iglesias.
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void mb_cpu_reset(CPUState *c)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(c);
+ MicroBlazeCPUClass *klass = MICROBLAZE_CPU_GET_CLASS(cpu);
+ CPUMBState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ memset(env, 0, offsetof(CPUMBState, breakpoints));
+ tlb_flush(env, 1);
+
+ /* Disable stack protector. */
+ env->shr = ~0;
+
+ env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
+ | PVR0_USE_BARREL_MASK \
+ | PVR0_USE_DIV_MASK \
+ | PVR0_USE_HW_MUL_MASK \
+ | PVR0_USE_EXC_MASK \
+ | PVR0_USE_ICACHE_MASK \
+ | PVR0_USE_DCACHE_MASK \
+ | PVR0_USE_MMU \
+ | (0xb << 8);
+ env->pvr.regs[2] = PVR2_D_OPB_MASK \
+ | PVR2_D_LMB_MASK \
+ | PVR2_I_OPB_MASK \
+ | PVR2_I_LMB_MASK \
+ | PVR2_USE_MSR_INSTR \
+ | PVR2_USE_PCMP_INSTR \
+ | PVR2_USE_BARREL_MASK \
+ | PVR2_USE_DIV_MASK \
+ | PVR2_USE_HW_MUL_MASK \
+ | PVR2_USE_MUL64_MASK \
+ | PVR2_USE_FPU_MASK \
+ | PVR2_USE_FPU2_MASK \
+ | PVR2_FPU_EXC_MASK \
+ | 0;
+ env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
+ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
+
+#if defined(CONFIG_USER_ONLY)
+ /* Start in user mode with interrupts enabled. */
+ env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
+ env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
+#else
+ env->sregs[SR_MSR] = 0;
+ mmu_init(&env->mmu);
+ env->mmu.c_mmu = 3;
+ env->mmu.c_mmu_tlb_access = 3;
+ env->mmu.c_mmu_zones = 16;
+#endif
+}
+
+static void mb_cpu_initfn(Object *obj)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
+ CPUMBState *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+
+ cpu_reset(CPU(cpu));
+}
+
+static void mb_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ MicroBlazeCPUClass *k = MICROBLAZE_CPU_CLASS(klass);
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = mb_cpu_reset;
+}
+
+static const TypeInfo mb_cpu_type_info = {
+ .name = TYPE_MICROBLAZE_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(MicroBlazeCPU),
+ .instance_init = mb_cpu_initfn,
+ .class_size = sizeof(MicroBlazeCPUClass),
+ .class_init = mb_cpu_class_init,
+};
+
+static void mb_cpu_register_types(void)
+{
+ type_register_static(&mb_cpu_type_info);
+}
+
+type_init(mb_cpu_register_types)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 3b52421..279c143 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -266,6 +266,8 @@ typedef struct CPUMBState {
CPU_COMMON
} CPUMBState;
+#include "cpu-qom.h"
+
CPUMBState *cpu_mb_init(const char *cpu_model);
int cpu_mb_exec(CPUMBState *s);
void cpu_mb_close(CPUMBState *s);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 64cbfb8..b188f6c 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1888,18 +1888,17 @@ void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n\n");
}
-CPUMBState *cpu_mb_init (const char *cpu_model)
+CPUMBState *cpu_mb_init(const char *cpu_model)
{
+ MicroBlazeCPU *cpu;
CPUMBState *env;
static int tcg_initialized = 0;
int i;
- env = g_malloc0(sizeof(CPUMBState));
+ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ env = &cpu->env;
- cpu_exec_init(env);
- cpu_state_reset(env);
qemu_init_vcpu(env);
- set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
if (tcg_initialized)
return env;
@@ -1941,54 +1940,7 @@ CPUMBState *cpu_mb_init (const char *cpu_model)
void cpu_state_reset(CPUMBState *env)
{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- memset(env, 0, offsetof(CPUMBState, breakpoints));
- tlb_flush(env, 1);
-
- /* Disable stack protector. */
- env->shr = ~0;
-
- env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
- | PVR0_USE_BARREL_MASK \
- | PVR0_USE_DIV_MASK \
- | PVR0_USE_HW_MUL_MASK \
- | PVR0_USE_EXC_MASK \
- | PVR0_USE_ICACHE_MASK \
- | PVR0_USE_DCACHE_MASK \
- | PVR0_USE_MMU \
- | (0xb << 8);
- env->pvr.regs[2] = PVR2_D_OPB_MASK \
- | PVR2_D_LMB_MASK \
- | PVR2_I_OPB_MASK \
- | PVR2_I_LMB_MASK \
- | PVR2_USE_MSR_INSTR \
- | PVR2_USE_PCMP_INSTR \
- | PVR2_USE_BARREL_MASK \
- | PVR2_USE_DIV_MASK \
- | PVR2_USE_HW_MUL_MASK \
- | PVR2_USE_MUL64_MASK \
- | PVR2_USE_FPU_MASK \
- | PVR2_USE_FPU2_MASK \
- | PVR2_FPU_EXC_MASK \
- | 0;
- env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
- env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
-
-#if defined(CONFIG_USER_ONLY)
- /* start in user mode with interrupts enabled. */
- env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
- env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
-#else
- env->sregs[SR_MSR] = 0;
- mmu_init(&env->mmu);
- env->mmu.c_mmu = 3;
- env->mmu.c_mmu_tlb_access = 3;
- env->mmu.c_mmu_zones = 16;
-#endif
+ cpu_reset(ENV_GET_CPU(env));
}
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 11/12] target-sparc: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (9 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] [RFC 10/12] target-microblaze: " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-14 20:16 ` Blue Swirl
2012-03-14 17:53 ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
11 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Andreas Färber
Let sparc_cpu_list() enumerate CPU classes alphabetically.
Introduce sparc_env_get_features() to workaround a circular dependency.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 2 +-
target-sparc/cpu-qom.h | 95 +++++
target-sparc/cpu.c | 949 +++++++++++++++++++++++++++++++++++++++++++
target-sparc/cpu.h | 29 +-
target-sparc/cpu_init.c | 848 --------------------------------------
target-sparc/int32_helper.c | 5 +-
target-sparc/ldst_helper.c | 19 +-
target-sparc/mmu_helper.c | 4 +-
target-sparc/translate.c | 4 +-
target-sparc/win_helper.c | 3 +-
10 files changed, 1075 insertions(+), 883 deletions(-)
create mode 100644 target-sparc/cpu-qom.h
create mode 100644 target-sparc/cpu.c
delete mode 100644 target-sparc/cpu_init.c
diff --git a/Makefile.target b/Makefile.target
index 82171ca..1c6ed12 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -100,7 +100,7 @@ libobj-$(TARGET_S390X) += cpu.o
libobj-$(TARGET_SH4) += cpu.o
ifeq ($(TARGET_BASE_ARCH), sparc)
libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
-libobj-y += cpu_init.o
+libobj-y += cpu.o
endif
libobj-$(TARGET_SPARC) += int32_helper.o
libobj-$(TARGET_SPARC64) += int64_helper.o
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
new file mode 100644
index 0000000..15dcf84
--- /dev/null
+++ b/target-sparc/cpu-qom.h
@@ -0,0 +1,95 @@
+/*
+ * QEMU SPARC CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_SPARC_CPU_QOM_H
+#define QEMU_SPARC_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_SPARC_CPU "sparc-cpu"
+
+#define SPARC_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SPARCCPUClass, (klass), TYPE_SPARC_CPU)
+#define SPARC_CPU(obj) \
+ OBJECT_CHECK(SPARCCPU, (obj), TYPE_SPARC_CPU)
+#define SPARC_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU)
+
+/**
+ * SPARCCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A SPARC CPU model.
+ */
+typedef struct SPARCCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ target_ulong iu_version;
+ uint32_t fpu_version;
+ uint32_t mmu_version;
+ uint32_t mmu_bm;
+ uint32_t mmu_ctpr_mask;
+ uint32_t mmu_cxr_mask;
+ uint32_t mmu_sfsr_mask;
+ uint32_t mmu_trcr_mask;
+ uint32_t mxcc_version;
+ uint32_t features;
+ uint32_t nwindows;
+ uint32_t maxtl;
+} SPARCCPUClass;
+
+/**
+ * SPARCCPU:
+ * @env: Legacy CPU state.
+ *
+ * A SPARC CPU.
+ */
+typedef struct SPARCCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUSPARCState env;
+
+ target_ulong iu_version;
+ uint32_t fpu_version;
+ uint32_t mmu_version;
+ uint32_t features;
+ uint32_t nwindows;
+} SPARCCPU;
+
+static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
+{
+ return SPARC_CPU(container_of(env, SPARCCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e))
+
+static inline uint32_t sparc_env_get_features(CPUSPARCState *env)
+{
+ return sparc_env_get_cpu(env)->features;
+}
+
+
+#endif
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
new file mode 100644
index 0000000..4c960a9
--- /dev/null
+++ b/target-sparc/cpu.c
@@ -0,0 +1,949 @@
+/*
+ * Sparc CPU init helpers
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu-qom.h"
+
+//#define DEBUG_FEATURES
+
+void cpu_state_reset(CPUSPARCState *env)
+{
+ cpu_reset(ENV_GET_CPU(env));
+}
+
+static void sparc_cpu_reset(CPUState *c)
+{
+ SPARCCPU *cpu = SPARC_CPU(c);
+ SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
+ CPUSPARCState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ klass->parent_reset(c);
+
+ tlb_flush(env, 1);
+ env->cwp = 0;
+#ifndef TARGET_SPARC64
+ env->wim = 1;
+#endif
+ env->regwptr = env->regbase + (env->cwp * 16);
+ CC_OP = CC_OP_FLAGS;
+#if defined(CONFIG_USER_ONLY)
+#ifdef TARGET_SPARC64
+ env->cleanwin = env->nwindows - 2;
+ env->cansave = env->nwindows - 2;
+ env->pstate = PS_RMO | PS_PEF | PS_IE;
+ env->asi = 0x82; /* Primary no-fault */
+#endif
+#else
+#if !defined(TARGET_SPARC64)
+ env->psret = 0;
+ env->psrs = 1;
+ env->psrps = 1;
+#endif
+#ifdef TARGET_SPARC64
+ env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
+ env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
+ env->tl = env->maxtl;
+ cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
+ env->lsu = 0;
+#else
+ env->mmuregs[0] &= ~(MMU_E | MMU_NF);
+ env->mmuregs[0] |= klass->mmu_bm;
+#endif
+ env->pc = 0;
+ env->npc = env->pc + 4;
+#endif
+ env->cache_control = 0;
+}
+
+static void sparc_cpu_initfn(Object *obj)
+{
+ SPARCCPU *cpu = SPARC_CPU(obj);
+ SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
+ CPUSPARCState *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+
+#if defined(CONFIG_USER_ONLY)
+ if ((cpu->features & CPU_FEATURE_FLOAT)) {
+ cpu->features |= CPU_FEATURE_FLOAT128;
+ }
+#endif
+ env->version = cpu->iu_version;
+ env->fsr = cpu->fpu_version;
+ env->nwindows = cpu->nwindows;
+#if !defined(TARGET_SPARC64)
+ env->mmuregs[0] |= cpu->mmu_version;
+ cpu_sparc_set_id(env, 0);
+ env->mxccregs[7] |= klass->mxcc_version;
+#else
+ env->mmu_version = cpu->mmu_version;
+ env->maxtl = klass->maxtl;
+ env->version |= klass->maxtl << 8;
+ env->version |= cpu->nwindows - 1;
+#endif
+}
+
+void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
+{
+#if !defined(TARGET_SPARC64)
+ env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
+#endif
+}
+
+/* CPU models */
+
+typedef struct SPARCCPUInfo {
+ const char *name;
+ target_ulong iu_version;
+ uint32_t fpu_version;
+ uint32_t mmu_version;
+ uint32_t mmu_bm;
+ uint32_t mmu_ctpr_mask;
+ uint32_t mmu_cxr_mask;
+ uint32_t mmu_sfsr_mask;
+ uint32_t mmu_trcr_mask;
+ uint32_t mxcc_version;
+ uint32_t features;
+ uint32_t nwindows;
+ uint32_t maxtl;
+} SPARCCPUInfo;
+
+static void sparc_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ SPARCCPUClass *k = SPARC_CPU_CLASS(klass);
+ const SPARCCPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = sparc_cpu_reset;
+
+ k->iu_version = info->iu_version;
+ k->fpu_version = info->fpu_version;
+ k->mmu_version = info->mmu_version;
+ k->mmu_bm = info->mmu_bm;
+ k->mmu_ctpr_mask = info->mmu_ctpr_mask;
+ k->mmu_cxr_mask = info->mmu_cxr_mask;
+ k->mmu_sfsr_mask = info->mmu_sfsr_mask;
+ k->mmu_trcr_mask = info->mmu_trcr_mask;
+ k->mxcc_version = info->mxcc_version;
+ k->features = info->features;
+ k->nwindows = info->nwindows;
+ k->maxtl = info->maxtl;
+}
+
+static const SPARCCPUInfo sparc_cpus[] = {
+#ifdef TARGET_SPARC64
+ {
+ .name = "Fujitsu Sparc64",
+ .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 4,
+ .maxtl = 4,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Fujitsu Sparc64 III",
+ .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 5,
+ .maxtl = 4,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Fujitsu Sparc64 IV",
+ .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Fujitsu Sparc64 V",
+ .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI UltraSparc I",
+ .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI UltraSparc II",
+ .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI UltraSparc IIi",
+ .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI UltraSparc IIe",
+ .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Sun UltraSparc III",
+ .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Sun UltraSparc III Cu",
+ .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_3,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Sun UltraSparc IIIi",
+ .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Sun UltraSparc IV",
+ .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_4,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Sun UltraSparc IV+",
+ .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
+ },
+ {
+ .name = "Sun UltraSparc IIIi+",
+ .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_3,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Sun UltraSparc T1",
+ /* defined in sparc_ifu_fdp.v and ctu.h */
+ .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_sun4v,
+ .nwindows = 8,
+ .maxtl = 6,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
+ | CPU_FEATURE_GL,
+ },
+ {
+ .name = "Sun UltraSparc T2",
+ /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
+ .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_sun4v,
+ .nwindows = 8,
+ .maxtl = 6,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
+ | CPU_FEATURE_GL,
+ },
+ {
+ .name = "NEC UltraSparc I",
+ .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_us_12,
+ .nwindows = 8,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+#else
+ {
+ .name = "Fujitsu MB86900",
+ .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
+ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
+ .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 7,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
+ },
+ {
+ .name = "Fujitsu MB86904",
+ .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
+ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
+ .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x00ffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Fujitsu MB86907",
+ .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
+ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
+ .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "LSI L64811",
+ .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
+ .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
+ .mmu_version = 0x10 << 24,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
+ CPU_FEATURE_FSMULD,
+ },
+ {
+ .name = "Cypress CY7C601",
+ .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
+ .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
+ .mmu_version = 0x10 << 24,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
+ CPU_FEATURE_FSMULD,
+ },
+ {
+ .name = "Cypress CY7C611",
+ .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
+ .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
+ .mmu_version = 0x10 << 24,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
+ CPU_FEATURE_FSMULD,
+ },
+ {
+ .name = "TI MicroSparc I",
+ .iu_version = 0x41000000,
+ .fpu_version = 4 << 17,
+ .mmu_version = 0x41000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x0000003f,
+ .nwindows = 7,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
+ CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
+ CPU_FEATURE_FMUL,
+ },
+ {
+ .name = "TI MicroSparc II",
+ .iu_version = 0x42000000,
+ .fpu_version = 4 << 17,
+ .mmu_version = 0x02000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x00ffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI MicroSparc IIep",
+ .iu_version = 0x42000000,
+ .fpu_version = 4 << 17,
+ .mmu_version = 0x04000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016bff,
+ .mmu_trcr_mask = 0x00ffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc 40", /* STP1020NPGA */
+ .iu_version = 0x41000000, /* SuperSPARC 2.x */
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc 50", /* STP1020PGA */
+ .iu_version = 0x40000000, /* SuperSPARC 3.x */
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc 51",
+ .iu_version = 0x40000000, /* SuperSPARC 3.x */
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .mxcc_version = 0x00000104,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc 60", /* STP1020APGA */
+ .iu_version = 0x40000000, /* SuperSPARC 3.x */
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc 61",
+ .iu_version = 0x44000000, /* SuperSPARC 3.x */
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .mxcc_version = 0x00000104,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "TI SuperSparc II",
+ .iu_version = 0x40000000, /* SuperSPARC II 1.x */
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
+ .mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .mxcc_version = 0x00000104,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Ross RT625",
+ .iu_version = 0x1e000000,
+ .fpu_version = 1 << 17,
+ .mmu_version = 0x1e000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "Ross RT620",
+ .iu_version = 0x1f000000,
+ .fpu_version = 1 << 17,
+ .mmu_version = 0x1f000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "BIT B5010",
+ .iu_version = 0x20000000,
+ .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
+ .mmu_version = 0x20000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
+ CPU_FEATURE_FSMULD,
+ },
+ {
+ .name = "Matsushita MN10501",
+ .iu_version = 0x50000000,
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x50000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
+ CPU_FEATURE_FSMULD,
+ },
+ {
+ .name = "Weitek W8601",
+ .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
+ .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
+ .mmu_version = 0x10 << 24,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES,
+ },
+ {
+ .name = "LEON2",
+ .iu_version = 0xf2000000,
+ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
+ .mmu_version = 0xf2000000,
+ .mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
+ },
+ {
+ .name = "LEON3",
+ .iu_version = 0xf3000000,
+ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
+ .mmu_version = 0xf3000000,
+ .mmu_bm = 0x00000000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
+ .nwindows = 8,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
+ CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
+ },
+#endif
+};
+
+static const char * const feature_name[] = {
+ "float",
+ "float128",
+ "swap",
+ "mul",
+ "div",
+ "flush",
+ "fsqrt",
+ "fmul",
+ "vis1",
+ "vis2",
+ "fsmuld",
+ "hypv",
+ "cmt",
+ "gl",
+};
+
+static void print_features(FILE *f, fprintf_function cpu_fprintf,
+ uint32_t features, const char *prefix)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
+ if (feature_name[i] && (features & (1 << i))) {
+ if (prefix) {
+ (*cpu_fprintf)(f, "%s", prefix);
+ }
+ (*cpu_fprintf)(f, "%s ", feature_name[i]);
+ }
+ }
+}
+
+static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
+ if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
+ *features |= 1 << i;
+ return;
+ }
+ }
+ fprintf(stderr, "CPU feature %s not found\n", flagname);
+}
+
+static SPARCCPU *cpu_sparc_find_by_name(const char *cpu_model)
+{
+ SPARCCPU *cpu;
+ char *s = strdup(cpu_model);
+ char *featurestr, *name = strtok(s, ",");
+ uint32_t plus_features = 0;
+ uint32_t minus_features = 0;
+ uint64_t iu_version;
+ uint32_t fpu_version, mmu_version, nwindows;
+
+ if (object_class_by_name(name) == NULL) {
+ goto error;
+ }
+ cpu = SPARC_CPU(object_new(name));
+
+ featurestr = strtok(NULL, ",");
+ while (featurestr) {
+ char *val;
+
+ if (featurestr[0] == '+') {
+ add_flagname_to_bitmaps(featurestr + 1, &plus_features);
+ } else if (featurestr[0] == '-') {
+ add_flagname_to_bitmaps(featurestr + 1, &minus_features);
+ } else if ((val = strchr(featurestr, '='))) {
+ *val = 0; val++;
+ if (!strcmp(featurestr, "iu_version")) {
+ char *err;
+
+ iu_version = strtoll(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ cpu->iu_version = iu_version;
+#ifdef DEBUG_FEATURES
+ fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
+#endif
+ } else if (!strcmp(featurestr, "fpu_version")) {
+ char *err;
+
+ fpu_version = strtol(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ cpu->fpu_version = fpu_version;
+#ifdef DEBUG_FEATURES
+ fprintf(stderr, "fpu_version %x\n", fpu_version);
+#endif
+ } else if (!strcmp(featurestr, "mmu_version")) {
+ char *err;
+
+ mmu_version = strtol(val, &err, 0);
+ if (!*val || *err) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ cpu->mmu_version = mmu_version;
+#ifdef DEBUG_FEATURES
+ fprintf(stderr, "mmu_version %x\n", mmu_version);
+#endif
+ } else if (!strcmp(featurestr, "nwindows")) {
+ char *err;
+
+ nwindows = strtol(val, &err, 0);
+ if (!*val || *err || nwindows > MAX_NWINDOWS ||
+ nwindows < MIN_NWINDOWS) {
+ fprintf(stderr, "bad numerical value %s\n", val);
+ goto error;
+ }
+ cpu->nwindows = nwindows;
+#ifdef DEBUG_FEATURES
+ fprintf(stderr, "nwindows %d\n", nwindows);
+#endif
+ } else {
+ fprintf(stderr, "unrecognized feature %s\n", featurestr);
+ goto error;
+ }
+ } else {
+ fprintf(stderr, "feature string `%s' not in format "
+ "(+feature|-feature|feature=xyz)\n", featurestr);
+ goto error;
+ }
+ featurestr = strtok(NULL, ",");
+ }
+ cpu->features |= plus_features;
+ cpu->features &= ~minus_features;
+#ifdef DEBUG_FEATURES
+ print_features(stderr, fprintf, cpu->features, NULL);
+#endif
+ free(s);
+ return cpu;
+
+ error:
+ free(s);
+ return NULL;
+}
+
+CPUSPARCState *cpu_sparc_init(const char *cpu_model)
+{
+ SPARCCPU *cpu;
+ CPUSPARCState *env;
+
+ cpu = cpu_sparc_find_by_name(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ env = &cpu->env;
+ env->cpu_model_str = cpu_model;
+
+ gen_intermediate_code_init(env);
+
+ qemu_init_vcpu(env);
+
+ return env;
+}
+
+typedef struct SPARCCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} SPARCCPUListState;
+
+/* Sort alphabetically. */
+static gint sparc_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
+}
+
+static void sparc_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *klass = data;
+ SPARCCPUClass *k = SPARC_CPU_CLASS(klass);
+ SPARCCPUListState *s = user_data;
+
+ (*s->cpu_fprintf)(s->file, "Sparc %16s IU " TARGET_FMT_lx
+ " FPU %08x MMU %08x NWINS %d ",
+ object_class_get_name(klass),
+ k->iu_version,
+ k->fpu_version,
+ k->mmu_version,
+ k->nwindows);
+ print_features(s->file, s->cpu_fprintf, CPU_DEFAULT_FEATURES &
+ ~k->features, "-");
+ print_features(s->file, s->cpu_fprintf, ~CPU_DEFAULT_FEATURES &
+ k->features, "+");
+ (*s->cpu_fprintf)(s->file, "\n");
+}
+
+void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ SPARCCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_SPARC_CPU, false);
+ list = g_slist_sort(list, sparc_cpu_list_compare);
+ g_slist_foreach(list, sparc_cpu_list_entry, &s);
+ g_slist_free(list);
+ (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
+ print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
+ (*cpu_fprintf)(f, "\n");
+ (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
+ print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
+ (*cpu_fprintf)(f, "\n");
+ (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
+ "fpu_version mmu_version nwindows\n");
+}
+
+static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
+ uint32_t cc)
+{
+ cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
+ cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
+ cc & PSR_CARRY ? 'C' : '-');
+}
+
+#ifdef TARGET_SPARC64
+#define REGS_PER_LINE 4
+#else
+#define REGS_PER_LINE 8
+#endif
+
+void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
+{
+ int i, x;
+
+ cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
+ env->npc);
+ cpu_fprintf(f, "General Registers:\n");
+
+ for (i = 0; i < 8; i++) {
+ if (i % REGS_PER_LINE == 0) {
+ cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
+ }
+ cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
+ if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
+ cpu_fprintf(f, "\n");
+ }
+ }
+ cpu_fprintf(f, "\nCurrent Register Window:\n");
+ for (x = 0; x < 3; x++) {
+ for (i = 0; i < 8; i++) {
+ if (i % REGS_PER_LINE == 0) {
+ cpu_fprintf(f, "%%%c%d-%d: ",
+ x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
+ i, i + REGS_PER_LINE - 1);
+ }
+ cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
+ if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
+ cpu_fprintf(f, "\n");
+ }
+ }
+ }
+ cpu_fprintf(f, "\nFloating Point Registers:\n");
+ for (i = 0; i < TARGET_DPREGS; i++) {
+ if ((i & 3) == 0) {
+ cpu_fprintf(f, "%%f%02d:", i * 2);
+ }
+ cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
+ if ((i & 3) == 3) {
+ cpu_fprintf(f, "\n");
+ }
+ }
+#ifdef TARGET_SPARC64
+ cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
+ (unsigned)cpu_get_ccr(env));
+ cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
+ cpu_fprintf(f, " xcc: ");
+ cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
+ cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
+ env->psrpil);
+ cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
+ "cleanwin: %d cwp: %d\n",
+ env->cansave, env->canrestore, env->otherwin, env->wstate,
+ env->cleanwin, env->nwindows - 1 - env->cwp);
+ cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
+ TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
+#else
+ cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
+ cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
+ cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
+ env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
+ env->wim);
+ cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
+ env->fsr, env->y);
+#endif
+}
+
+static void cpu_type_register(const SPARCCPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_SPARC_CPU,
+ .instance_size = sizeof(SPARCCPU),
+ .instance_init = sparc_cpu_initfn,
+ .class_size = sizeof(SPARCCPUClass),
+ .class_init = sparc_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo sparc_cpu_info = {
+ .name = TYPE_SPARC_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(SPARCCPU),
+ .abstract = true,
+ .class_size = sizeof(SPARCCPUClass),
+};
+
+static void sparc_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&sparc_cpu_info);
+ for (i = 0; i < ARRAY_SIZE(sparc_cpus); i++) {
+ cpu_type_register(&sparc_cpus[i]);
+ }
+}
+
+type_init(sparc_cpu_register_types)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 86f9de6..10b05ac 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -237,22 +237,6 @@ typedef struct trap_state {
} trap_state;
#endif
-typedef struct sparc_def_t {
- const char *name;
- target_ulong iu_version;
- uint32_t fpu_version;
- uint32_t mmu_version;
- uint32_t mmu_bm;
- uint32_t mmu_ctpr_mask;
- uint32_t mmu_cxr_mask;
- uint32_t mmu_sfsr_mask;
- uint32_t mmu_trcr_mask;
- uint32_t mxcc_version;
- uint32_t features;
- uint32_t nwindows;
- uint32_t maxtl;
-} sparc_def_t;
-
#define CPU_FEATURE_FLOAT (1 << 0)
#define CPU_FEATURE_FLOAT128 (1 << 1)
#define CPU_FEATURE_SWAP (1 << 2)
@@ -498,7 +482,6 @@ struct CPUSPARCState {
#define SOFTINT_INTRMASK (0xFFFE)
#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
#endif
- sparc_def_t *def;
void *irq_manager;
void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
@@ -507,6 +490,7 @@ struct CPUSPARCState {
uint32_t cache_control;
};
+
#ifndef NO_CPU_IO_DEFS
/* cpu_init.c */
CPUSPARCState *cpu_sparc_init(const char *cpu_model);
@@ -616,10 +600,12 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define MMU_MODE1_SUFFIX _kernel
#endif
+static inline uint32_t sparc_env_get_features(CPUSPARCState *env);
+
#if defined (TARGET_SPARC64)
static inline int cpu_has_hypervisor(CPUSPARCState *env1)
{
- return env1->def->features & CPU_FEATURE_HYPV;
+ return sparc_env_get_features(env1) & CPU_FEATURE_HYPV;
}
static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
@@ -688,6 +674,7 @@ static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp)
#endif
#include "cpu-all.h"
+#include "cpu-qom.h"
#ifdef TARGET_SPARC64
/* sun4u.c */
@@ -714,14 +701,14 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
if (env->pstate & PS_AM) {
*flags |= TB_FLAG_AM_ENABLED;
}
- if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
- && (env->fprs & FPRS_FEF)) {
+ if ((sparc_env_get_features(env) & CPU_FEATURE_FLOAT)
+ && (env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
*flags |= TB_FLAG_FPU_ENABLED;
}
#else
// FPU enable . Supervisor
*flags = env->psrs;
- if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
+ if ((sparc_env_get_features(env) & CPU_FEATURE_FLOAT) && env->psref) {
*flags |= TB_FLAG_FPU_ENABLED;
}
#endif
diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
deleted file mode 100644
index 29132fb..0000000
--- a/target-sparc/cpu_init.c
+++ /dev/null
@@ -1,848 +0,0 @@
-/*
- * Sparc CPU init helpers
- *
- * Copyright (c) 2003-2005 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "cpu.h"
-
-//#define DEBUG_FEATURES
-
-static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
-
-void cpu_state_reset(CPUSPARCState *env)
-{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- tlb_flush(env, 1);
- env->cwp = 0;
-#ifndef TARGET_SPARC64
- env->wim = 1;
-#endif
- env->regwptr = env->regbase + (env->cwp * 16);
- CC_OP = CC_OP_FLAGS;
-#if defined(CONFIG_USER_ONLY)
-#ifdef TARGET_SPARC64
- env->cleanwin = env->nwindows - 2;
- env->cansave = env->nwindows - 2;
- env->pstate = PS_RMO | PS_PEF | PS_IE;
- env->asi = 0x82; /* Primary no-fault */
-#endif
-#else
-#if !defined(TARGET_SPARC64)
- env->psret = 0;
- env->psrs = 1;
- env->psrps = 1;
-#endif
-#ifdef TARGET_SPARC64
- env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
- env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
- env->tl = env->maxtl;
- cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
- env->lsu = 0;
-#else
- env->mmuregs[0] &= ~(MMU_E | MMU_NF);
- env->mmuregs[0] |= env->def->mmu_bm;
-#endif
- env->pc = 0;
- env->npc = env->pc + 4;
-#endif
- env->cache_control = 0;
-}
-
-static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
-{
- sparc_def_t def1, *def = &def1;
-
- if (cpu_sparc_find_by_name(def, cpu_model) < 0) {
- return -1;
- }
-
- env->def = g_new0(sparc_def_t, 1);
- memcpy(env->def, def, sizeof(*def));
-#if defined(CONFIG_USER_ONLY)
- if ((env->def->features & CPU_FEATURE_FLOAT)) {
- env->def->features |= CPU_FEATURE_FLOAT128;
- }
-#endif
- env->cpu_model_str = cpu_model;
- env->version = def->iu_version;
- env->fsr = def->fpu_version;
- env->nwindows = def->nwindows;
-#if !defined(TARGET_SPARC64)
- env->mmuregs[0] |= def->mmu_version;
- cpu_sparc_set_id(env, 0);
- env->mxccregs[7] |= def->mxcc_version;
-#else
- env->mmu_version = def->mmu_version;
- env->maxtl = def->maxtl;
- env->version |= def->maxtl << 8;
- env->version |= def->nwindows - 1;
-#endif
- return 0;
-}
-
-static void cpu_sparc_close(CPUSPARCState *env)
-{
- g_free(env->def);
- g_free(env);
-}
-
-CPUSPARCState *cpu_sparc_init(const char *cpu_model)
-{
- CPUSPARCState *env;
-
- env = g_new0(CPUSPARCState, 1);
- cpu_exec_init(env);
-
- gen_intermediate_code_init(env);
-
- if (cpu_sparc_register(env, cpu_model) < 0) {
- cpu_sparc_close(env);
- return NULL;
- }
- qemu_init_vcpu(env);
-
- return env;
-}
-
-void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
-{
-#if !defined(TARGET_SPARC64)
- env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
-#endif
-}
-
-static const sparc_def_t sparc_defs[] = {
-#ifdef TARGET_SPARC64
- {
- .name = "Fujitsu Sparc64",
- .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 4,
- .maxtl = 4,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Fujitsu Sparc64 III",
- .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 5,
- .maxtl = 4,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Fujitsu Sparc64 IV",
- .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Fujitsu Sparc64 V",
- .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI UltraSparc I",
- .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI UltraSparc II",
- .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI UltraSparc IIi",
- .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI UltraSparc IIe",
- .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Sun UltraSparc III",
- .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Sun UltraSparc III Cu",
- .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_3,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Sun UltraSparc IIIi",
- .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Sun UltraSparc IV",
- .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_4,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Sun UltraSparc IV+",
- .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
- },
- {
- .name = "Sun UltraSparc IIIi+",
- .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_3,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Sun UltraSparc T1",
- /* defined in sparc_ifu_fdp.v and ctu.h */
- .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_sun4v,
- .nwindows = 8,
- .maxtl = 6,
- .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
- | CPU_FEATURE_GL,
- },
- {
- .name = "Sun UltraSparc T2",
- /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
- .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_sun4v,
- .nwindows = 8,
- .maxtl = 6,
- .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
- | CPU_FEATURE_GL,
- },
- {
- .name = "NEC UltraSparc I",
- .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
- .fpu_version = 0x00000000,
- .mmu_version = mmu_us_12,
- .nwindows = 8,
- .maxtl = 5,
- .features = CPU_DEFAULT_FEATURES,
- },
-#else
- {
- .name = "Fujitsu MB86900",
- .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
- .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
- .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 7,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
- },
- {
- .name = "Fujitsu MB86904",
- .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
- .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
- .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x00ffffc0,
- .mmu_cxr_mask = 0x000000ff,
- .mmu_sfsr_mask = 0x00016fff,
- .mmu_trcr_mask = 0x00ffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Fujitsu MB86907",
- .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
- .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
- .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x000000ff,
- .mmu_sfsr_mask = 0x00016fff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "LSI L64811",
- .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
- .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
- .mmu_version = 0x10 << 24,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
- CPU_FEATURE_FSMULD,
- },
- {
- .name = "Cypress CY7C601",
- .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
- .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
- .mmu_version = 0x10 << 24,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
- CPU_FEATURE_FSMULD,
- },
- {
- .name = "Cypress CY7C611",
- .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
- .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
- .mmu_version = 0x10 << 24,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
- CPU_FEATURE_FSMULD,
- },
- {
- .name = "TI MicroSparc I",
- .iu_version = 0x41000000,
- .fpu_version = 4 << 17,
- .mmu_version = 0x41000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0x00016fff,
- .mmu_trcr_mask = 0x0000003f,
- .nwindows = 7,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
- CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
- CPU_FEATURE_FMUL,
- },
- {
- .name = "TI MicroSparc II",
- .iu_version = 0x42000000,
- .fpu_version = 4 << 17,
- .mmu_version = 0x02000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x00ffffc0,
- .mmu_cxr_mask = 0x000000ff,
- .mmu_sfsr_mask = 0x00016fff,
- .mmu_trcr_mask = 0x00ffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI MicroSparc IIep",
- .iu_version = 0x42000000,
- .fpu_version = 4 << 17,
- .mmu_version = 0x04000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x00ffffc0,
- .mmu_cxr_mask = 0x000000ff,
- .mmu_sfsr_mask = 0x00016bff,
- .mmu_trcr_mask = 0x00ffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI SuperSparc 40", /* STP1020NPGA */
- .iu_version = 0x41000000, /* SuperSPARC 2.x */
- .fpu_version = 0 << 17,
- .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
- .mmu_bm = 0x00002000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x0000ffff,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI SuperSparc 50", /* STP1020PGA */
- .iu_version = 0x40000000, /* SuperSPARC 3.x */
- .fpu_version = 0 << 17,
- .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
- .mmu_bm = 0x00002000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x0000ffff,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI SuperSparc 51",
- .iu_version = 0x40000000, /* SuperSPARC 3.x */
- .fpu_version = 0 << 17,
- .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
- .mmu_bm = 0x00002000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x0000ffff,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .mxcc_version = 0x00000104,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI SuperSparc 60", /* STP1020APGA */
- .iu_version = 0x40000000, /* SuperSPARC 3.x */
- .fpu_version = 0 << 17,
- .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
- .mmu_bm = 0x00002000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x0000ffff,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI SuperSparc 61",
- .iu_version = 0x44000000, /* SuperSPARC 3.x */
- .fpu_version = 0 << 17,
- .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
- .mmu_bm = 0x00002000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x0000ffff,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .mxcc_version = 0x00000104,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "TI SuperSparc II",
- .iu_version = 0x40000000, /* SuperSPARC II 1.x */
- .fpu_version = 0 << 17,
- .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
- .mmu_bm = 0x00002000,
- .mmu_ctpr_mask = 0xffffffc0,
- .mmu_cxr_mask = 0x0000ffff,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .mxcc_version = 0x00000104,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Ross RT625",
- .iu_version = 0x1e000000,
- .fpu_version = 1 << 17,
- .mmu_version = 0x1e000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "Ross RT620",
- .iu_version = 0x1f000000,
- .fpu_version = 1 << 17,
- .mmu_version = 0x1f000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "BIT B5010",
- .iu_version = 0x20000000,
- .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
- .mmu_version = 0x20000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
- CPU_FEATURE_FSMULD,
- },
- {
- .name = "Matsushita MN10501",
- .iu_version = 0x50000000,
- .fpu_version = 0 << 17,
- .mmu_version = 0x50000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
- CPU_FEATURE_FSMULD,
- },
- {
- .name = "Weitek W8601",
- .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
- .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
- .mmu_version = 0x10 << 24,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
- },
- {
- .name = "LEON2",
- .iu_version = 0xf2000000,
- .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
- .mmu_version = 0xf2000000,
- .mmu_bm = 0x00004000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
- },
- {
- .name = "LEON3",
- .iu_version = 0xf3000000,
- .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
- .mmu_version = 0xf3000000,
- .mmu_bm = 0x00000000,
- .mmu_ctpr_mask = 0x007ffff0,
- .mmu_cxr_mask = 0x0000003f,
- .mmu_sfsr_mask = 0xffffffff,
- .mmu_trcr_mask = 0xffffffff,
- .nwindows = 8,
- .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
- CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
- },
-#endif
-};
-
-static const char * const feature_name[] = {
- "float",
- "float128",
- "swap",
- "mul",
- "div",
- "flush",
- "fsqrt",
- "fmul",
- "vis1",
- "vis2",
- "fsmuld",
- "hypv",
- "cmt",
- "gl",
-};
-
-static void print_features(FILE *f, fprintf_function cpu_fprintf,
- uint32_t features, const char *prefix)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
- if (feature_name[i] && (features & (1 << i))) {
- if (prefix) {
- (*cpu_fprintf)(f, "%s", prefix);
- }
- (*cpu_fprintf)(f, "%s ", feature_name[i]);
- }
- }
-}
-
-static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
- if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
- *features |= 1 << i;
- return;
- }
- }
- fprintf(stderr, "CPU feature %s not found\n", flagname);
-}
-
-static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
-{
- unsigned int i;
- const sparc_def_t *def = NULL;
- char *s = strdup(cpu_model);
- char *featurestr, *name = strtok(s, ",");
- uint32_t plus_features = 0;
- uint32_t minus_features = 0;
- uint64_t iu_version;
- uint32_t fpu_version, mmu_version, nwindows;
-
- for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
- if (strcasecmp(name, sparc_defs[i].name) == 0) {
- def = &sparc_defs[i];
- }
- }
- if (!def) {
- goto error;
- }
- memcpy(cpu_def, def, sizeof(*def));
-
- featurestr = strtok(NULL, ",");
- while (featurestr) {
- char *val;
-
- if (featurestr[0] == '+') {
- add_flagname_to_bitmaps(featurestr + 1, &plus_features);
- } else if (featurestr[0] == '-') {
- add_flagname_to_bitmaps(featurestr + 1, &minus_features);
- } else if ((val = strchr(featurestr, '='))) {
- *val = 0; val++;
- if (!strcmp(featurestr, "iu_version")) {
- char *err;
-
- iu_version = strtoll(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- cpu_def->iu_version = iu_version;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
-#endif
- } else if (!strcmp(featurestr, "fpu_version")) {
- char *err;
-
- fpu_version = strtol(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- cpu_def->fpu_version = fpu_version;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "fpu_version %x\n", fpu_version);
-#endif
- } else if (!strcmp(featurestr, "mmu_version")) {
- char *err;
-
- mmu_version = strtol(val, &err, 0);
- if (!*val || *err) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- cpu_def->mmu_version = mmu_version;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "mmu_version %x\n", mmu_version);
-#endif
- } else if (!strcmp(featurestr, "nwindows")) {
- char *err;
-
- nwindows = strtol(val, &err, 0);
- if (!*val || *err || nwindows > MAX_NWINDOWS ||
- nwindows < MIN_NWINDOWS) {
- fprintf(stderr, "bad numerical value %s\n", val);
- goto error;
- }
- cpu_def->nwindows = nwindows;
-#ifdef DEBUG_FEATURES
- fprintf(stderr, "nwindows %d\n", nwindows);
-#endif
- } else {
- fprintf(stderr, "unrecognized feature %s\n", featurestr);
- goto error;
- }
- } else {
- fprintf(stderr, "feature string `%s' not in format "
- "(+feature|-feature|feature=xyz)\n", featurestr);
- goto error;
- }
- featurestr = strtok(NULL, ",");
- }
- cpu_def->features |= plus_features;
- cpu_def->features &= ~minus_features;
-#ifdef DEBUG_FEATURES
- print_features(stderr, fprintf, cpu_def->features, NULL);
-#endif
- free(s);
- return 0;
-
- error:
- free(s);
- return -1;
-}
-
-void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
- (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
- " FPU %08x MMU %08x NWINS %d ",
- sparc_defs[i].name,
- sparc_defs[i].iu_version,
- sparc_defs[i].fpu_version,
- sparc_defs[i].mmu_version,
- sparc_defs[i].nwindows);
- print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
- ~sparc_defs[i].features, "-");
- print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
- sparc_defs[i].features, "+");
- (*cpu_fprintf)(f, "\n");
- }
- (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
- print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
- (*cpu_fprintf)(f, "\n");
- (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
- print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
- (*cpu_fprintf)(f, "\n");
- (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
- "fpu_version mmu_version nwindows\n");
-}
-
-static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
- uint32_t cc)
-{
- cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
- cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
- cc & PSR_CARRY ? 'C' : '-');
-}
-
-#ifdef TARGET_SPARC64
-#define REGS_PER_LINE 4
-#else
-#define REGS_PER_LINE 8
-#endif
-
-void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
-{
- int i, x;
-
- cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
- env->npc);
- cpu_fprintf(f, "General Registers:\n");
-
- for (i = 0; i < 8; i++) {
- if (i % REGS_PER_LINE == 0) {
- cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
- }
- cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
- if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
- cpu_fprintf(f, "\n");
- }
- }
- cpu_fprintf(f, "\nCurrent Register Window:\n");
- for (x = 0; x < 3; x++) {
- for (i = 0; i < 8; i++) {
- if (i % REGS_PER_LINE == 0) {
- cpu_fprintf(f, "%%%c%d-%d: ",
- x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
- i, i + REGS_PER_LINE - 1);
- }
- cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
- if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
- cpu_fprintf(f, "\n");
- }
- }
- }
- cpu_fprintf(f, "\nFloating Point Registers:\n");
- for (i = 0; i < TARGET_DPREGS; i++) {
- if ((i & 3) == 0) {
- cpu_fprintf(f, "%%f%02d:", i * 2);
- }
- cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
- if ((i & 3) == 3) {
- cpu_fprintf(f, "\n");
- }
- }
-#ifdef TARGET_SPARC64
- cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
- (unsigned)cpu_get_ccr(env));
- cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
- cpu_fprintf(f, " xcc: ");
- cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
- cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
- env->psrpil);
- cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
- "cleanwin: %d cwp: %d\n",
- env->cansave, env->canrestore, env->otherwin, env->wstate,
- env->cleanwin, env->nwindows - 1 - env->cwp);
- cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
- TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
-#else
- cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
- cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
- cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
- env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
- env->wim);
- cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
- env->fsr, env->y);
-#endif
-}
diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
index 5e33d50..8d454ae 100644
--- a/target-sparc/int32_helper.c
+++ b/target-sparc/int32_helper.c
@@ -60,6 +60,9 @@ static const char * const excp_names[0x80] = {
void do_interrupt(CPUSPARCState *env)
{
+#if !defined(CONFIG_USER_ONLY)
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
+#endif
int cwp, intno = env->exception_index;
#ifdef DEBUG_PCALL
@@ -102,7 +105,7 @@ void do_interrupt(CPUSPARCState *env)
#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
if (env->exception_index == 0x80 &&
- env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
+ cpu->features & CPU_FEATURE_TA0_SHUTDOWN) {
qemu_system_shutdown_request();
} else {
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 48d433c..806f45c 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -438,6 +438,7 @@ static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
uint64_t ret = 0;
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_addr = addr;
@@ -450,7 +451,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ if (cpu->features & CPU_FEATURE_CACHE_CTRL) {
ret = leon3_cache_control_ld(addr, size);
}
break;
@@ -696,6 +697,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
+ SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
helper_check_align(addr, size - 1);
switch (asi) {
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
@@ -703,7 +706,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ if (cpu->features & CPU_FEATURE_CACHE_CTRL) {
leon3_cache_control_st(addr, val, size);
}
break;
@@ -853,16 +856,16 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
(val & 0x00ffffff);
/* Mappings generated during no-fault mode or MMU
disabled mode are invalid in normal mode */
- if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
- (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
+ if ((oldreg & (MMU_E | MMU_NF | klass->mmu_bm)) !=
+ (env->mmuregs[reg] & (MMU_E | MMU_NF | klass->mmu_bm))) {
tlb_flush(env, 1);
}
break;
case 1: /* Context Table Pointer Register */
- env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
+ env->mmuregs[reg] = val & klass->mmu_ctpr_mask;
break;
case 2: /* Context Register */
- env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
+ env->mmuregs[reg] = val & klass->mmu_cxr_mask;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
@@ -873,11 +876,11 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 4: /* Synchronous Fault Address Register */
break;
case 0x10: /* TLB Replacement Control Register */
- env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
+ env->mmuregs[reg] = val & klass->mmu_trcr_mask;
break;
case 0x13: /* Synchronous Fault Status Register with Read
and Clear */
- env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
+ env->mmuregs[3] = val & klass->mmu_sfsr_mask;
break;
case 0x14: /* Synchronous Fault Address Register */
env->mmuregs[4] = val;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 11fb9f5..83b050e 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -81,6 +81,8 @@ static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
+ SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
int access_perms = 0;
target_phys_addr_t pde_ptr;
uint32_t pde;
@@ -92,7 +94,7 @@ static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
*page_size = TARGET_PAGE_SIZE;
/* Boot mode: instruction fetches are taken from PROM */
- if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
+ if (rw == 2 && (env->mmuregs[0] & klass->mmu_bm)) {
*physical = env->prom_addr | (address & 0x7ffffULL);
*prot = PAGE_READ | PAGE_EXEC;
return 0;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ef176e9..a737279 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -81,7 +81,7 @@ typedef struct DisasContext {
int singlestep;
uint32_t cc_op; /* current CC operation */
struct TranslationBlock *tb;
- sparc_def_t *def;
+ SPARCCPU *def;
TCGv_i32 t32[3];
int n_t32;
} DisasContext;
@@ -5247,7 +5247,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = cpu_mmu_index(env);
- dc->def = env->def;
+ dc->def = sparc_env_get_cpu(env);
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (env->singlestep_enabled || singlestep);
diff --git a/target-sparc/win_helper.c b/target-sparc/win_helper.c
index 3e82eb7..02376fc 100644
--- a/target-sparc/win_helper.c
+++ b/target-sparc/win_helper.c
@@ -300,10 +300,11 @@ static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
uint32_t pstate_regs, new_pstate_regs;
uint64_t *src, *dst;
- if (env->def->features & CPU_FEATURE_GL) {
+ if (cpu->features & CPU_FEATURE_GL) {
/* PS_AG is not implemented in this case */
new_pstate &= ~PS_AG;
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* [Qemu-devel] [RFC 12/12] target-xtensa: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
` (10 preceding siblings ...)
2012-03-14 17:53 ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
@ 2012-03-14 17:53 ` Andreas Färber
2012-03-15 22:10 ` jcmvbkbc
11 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 17:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov, Andreas Färber
Let xtensa_cpu_list() enumerate CPU classes alphabetically.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
Makefile.target | 1 +
gdbstub.c | 19 +++--
hw/xtensa_pic.c | 51 ++++++++----
target-xtensa/core-dc232b.c | 5 +-
target-xtensa/core-fsf.c | 5 +-
target-xtensa/cpu-qom.h | 186 ++++++++++++++++++++++++++++++++++++++++++
target-xtensa/cpu.c | 87 ++++++++++++++++++++
target-xtensa/cpu.h | 125 ++++------------------------
target-xtensa/helper.c | 151 ++++++++++++++++++++--------------
target-xtensa/op_helper.c | 104 ++++++++++++++++--------
target-xtensa/overlay_tool.h | 28 +++++--
target-xtensa/translate.c | 9 ++-
12 files changed, 527 insertions(+), 244 deletions(-)
create mode 100644 target-xtensa/cpu-qom.h
create mode 100644 target-xtensa/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 1c6ed12..3edbdfc 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -105,6 +105,7 @@ endif
libobj-$(TARGET_SPARC) += int32_helper.o
libobj-$(TARGET_SPARC64) += int64_helper.o
libobj-$(TARGET_UNICORE32) += cpu.o
+libobj-$(TARGET_XTENSA) += cpu.o
libobj-y += disas.o
libobj-$(CONFIG_TCI_DIS) += tci-dis.o
diff --git a/gdbstub.c b/gdbstub.c
index f4e97f7..773e86f 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1570,14 +1570,17 @@ static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
* reset bit 0 in the 'flags' field of the registers definitions in the
* gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
*/
-#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
+#define NUM_CORE_REGS \
+ (XTENSA_CPU_GET_CLASS(xtensa_env_get_cpu(env))->gdb_regmap.num_regs)
#define num_g_regs NUM_CORE_REGS
static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
- const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ const XtensaGdbReg *reg = klass->gdb_regmap.reg + n;
- if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
+ if (n < 0 || n >= klass->gdb_regmap.num_regs) {
return 0;
}
@@ -1588,7 +1591,7 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
case 1: /*ar*/
xtensa_sync_phys_from_window(env);
- GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
+ GET_REG32(env->phys_regs[(reg->targno & 0xff) % klass->nareg]);
break;
case 2: /*SR*/
@@ -1613,9 +1616,11 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
- const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ const XtensaGdbReg *reg = klass->gdb_regmap.reg + n;
- if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
+ if (n < 0 || n >= klass->gdb_regmap.num_regs) {
return 0;
}
@@ -1627,7 +1632,7 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
break;
case 1: /*ar*/
- env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
+ env->phys_regs[(reg->targno & 0xff) % klass->nareg] = tmp;
xtensa_sync_window_from_phys(env);
break;
diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c
index 653ded6..3d398a1 100644
--- a/hw/xtensa_pic.c
+++ b/hw/xtensa_pic.c
@@ -31,13 +31,15 @@
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
uint32_t old_ccount = env->sregs[CCOUNT];
env->sregs[CCOUNT] += d;
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
+ if (xtensa_option_enabled(klass, XTENSA_OPTION_TIMER_INTERRUPT)) {
int i;
- for (i = 0; i < env->config->nccompare; ++i) {
+ for (i = 0; i < klass->nccompare; ++i) {
if (env->sregs[CCOMPARE + i] - old_ccount <= d) {
xtensa_timer_irq(env, i, 1);
}
@@ -47,7 +49,9 @@ void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
void check_interrupts(CPUXtensaState *env)
{
- int minlevel = xtensa_get_cintlevel(env);
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ int minlevel = xtensa_get_cintlevel(cpu);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
int level;
@@ -59,11 +63,11 @@ void check_interrupts(CPUXtensaState *env)
xtensa_advance_ccount(env,
muldiv64(now - env->halt_clock,
- env->config->clock_freq_khz, 1000000));
+ klass->clock_freq_khz, 1000000));
env->halt_clock = now;
}
- for (level = env->config->nlevel; level > minlevel; --level) {
- if (env->config->level_mask[level] & int_set_enabled) {
+ for (level = klass->nlevel; level > minlevel; --level) {
+ if (klass->level_mask[level] & int_set_enabled) {
env->pending_irq_level = level;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
qemu_log_mask(CPU_LOG_INT,
@@ -71,7 +75,7 @@ void check_interrupts(CPUXtensaState *env)
"pc = %08x, a0 = %08x, ps = %08x, "
"intset = %08x, intenable = %08x, "
"ccount = %08x\n",
- __func__, level, xtensa_get_cintlevel(env),
+ __func__, level, xtensa_get_cintlevel(cpu),
env->pc, env->regs[0], env->sregs[PS],
env->sregs[INTSET], env->sregs[INTENABLE],
env->sregs[CCOUNT]);
@@ -85,15 +89,17 @@ void check_interrupts(CPUXtensaState *env)
static void xtensa_set_irq(void *opaque, int irq, int active)
{
CPUXtensaState *env = opaque;
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
- if (irq >= env->config->ninterrupt) {
+ if (irq >= klass->ninterrupt) {
qemu_log("%s: bad IRQ %d\n", __func__, irq);
} else {
uint32_t irq_bit = 1 << irq;
if (active) {
env->sregs[INTSET] |= irq_bit;
- } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
+ } else if (klass->interrupt[irq].inttype == INTTYPE_LEVEL) {
env->sregs[INTSET] &= ~irq_bit;
}
@@ -103,15 +109,20 @@ static void xtensa_set_irq(void *opaque, int irq, int active)
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
{
- qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ qemu_set_irq(env->irq_inputs[klass->timerint[id]], active);
}
void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
int i;
uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
- for (i = 0; i < env->config->nccompare; ++i) {
+ for (i = 0; i < klass->nccompare; ++i) {
if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <
wake_ccount - env->sregs[CCOUNT]) {
wake_ccount = env->sregs[CCOMPARE + i];
@@ -120,7 +131,7 @@ void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
env->wake_ccount = wake_ccount;
qemu_mod_timer(env->ccompare_timer, env->halt_clock +
muldiv64(wake_ccount - env->sregs[CCOUNT],
- 1000000, env->config->clock_freq_khz));
+ 1000000, klass->clock_freq_khz));
}
static void xtensa_ccompare_cb(void *opaque)
@@ -139,10 +150,13 @@ static void xtensa_ccompare_cb(void *opaque)
void xtensa_irq_init(CPUXtensaState *env)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
env->irq_inputs = (void **)qemu_allocate_irqs(
- xtensa_set_irq, env, env->config->ninterrupt);
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
- env->config->nccompare > 0) {
+ xtensa_set_irq, env, klass->ninterrupt);
+ if (xtensa_option_enabled(klass, XTENSA_OPTION_TIMER_INTERRUPT) &&
+ klass->nccompare > 0) {
env->ccompare_timer =
qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, env);
}
@@ -150,8 +164,11 @@ void xtensa_irq_init(CPUXtensaState *env)
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
{
- if (extint < env->config->nextint) {
- unsigned irq = env->config->extint[extint];
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ if (extint < klass->nextint) {
+ unsigned irq = klass->extint[extint];
return env->irq_inputs[irq];
} else {
qemu_log("%s: trying to acquire invalid external interrupt %d\n",
diff --git a/target-xtensa/core-dc232b.c b/target-xtensa/core-dc232b.c
index 7c03835..a62ca6a 100644
--- a/target-xtensa/core-dc232b.c
+++ b/target-xtensa/core-dc232b.c
@@ -6,8 +6,7 @@
#include "core-dc232b/core-isa.h"
#include "overlay_tool.h"
-static const XtensaConfig dc232b = {
- .name = "dc232b",
+static const XtensaCPUClass dc232b = {
.options = XTENSA_OPTIONS,
.gdb_regmap = {
.num_regs = 120,
@@ -25,4 +24,4 @@ static const XtensaConfig dc232b = {
.clock_freq_khz = 10000,
};
-REGISTER_CORE(dc232b)
+REGISTER_CORE("dc232b", dc232b)
diff --git a/target-xtensa/core-fsf.c b/target-xtensa/core-fsf.c
index c11d970..bcda18b 100644
--- a/target-xtensa/core-fsf.c
+++ b/target-xtensa/core-fsf.c
@@ -6,8 +6,7 @@
#include "core-fsf/core-isa.h"
#include "overlay_tool.h"
-static const XtensaConfig fsf = {
- .name = "fsf",
+static const XtensaCPUClass fsf = {
.options = XTENSA_OPTIONS,
/* GDB for this core is not supported currently */
.nareg = XCHAL_NUM_AREGS,
@@ -19,4 +18,4 @@ static const XtensaConfig fsf = {
.clock_freq_khz = 10000,
};
-REGISTER_CORE(fsf)
+REGISTER_CORE("fsf", fsf)
diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
new file mode 100644
index 0000000..e286458
--- /dev/null
+++ b/target-xtensa/cpu-qom.h
@@ -0,0 +1,186 @@
+/*
+ * QEMU Xtensa CPU
+ *
+ * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef QEMU_XTENSA_CPU_QOM_H
+#define QEMU_XTENSA_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_XTENSA_CPU "xtensa-cpu"
+
+#define XTENSA_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XtensaCPUClass, (klass), TYPE_XTENSA_CPU)
+#define XTENSA_CPU(obj) \
+ OBJECT_CHECK(XtensaCPU, (obj), TYPE_XTENSA_CPU)
+#define XTENSA_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XtensaCPUClass, (obj), TYPE_XTENSA_CPU)
+
+typedef struct xtensa_tlb {
+ unsigned nways;
+ const unsigned way_size[10];
+ bool varway56;
+ unsigned nrefillentries;
+} xtensa_tlb;
+
+typedef struct XtensaGdbReg {
+ int targno;
+ int type;
+ int group;
+} XtensaGdbReg;
+
+typedef struct XtensaGdbRegmap {
+ int num_regs;
+ int num_core_regs;
+ /* PC + a + ar + sr + ur */
+ XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
+} XtensaGdbRegmap;
+
+/**
+ * XtensaCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An Xtensa CPU model.
+ */
+typedef struct XtensaCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint64_t options;
+ XtensaGdbRegmap gdb_regmap;
+ unsigned nareg;
+ int excm_level;
+ int ndepc;
+ uint32_t vecbase;
+ uint32_t exception_vector[EXC_MAX];
+ unsigned ninterrupt;
+ unsigned nlevel;
+ uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
+ uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
+ uint32_t inttype_mask[INTTYPE_MAX];
+ struct {
+ uint32_t level;
+ interrupt_type inttype;
+ } interrupt[MAX_NINTERRUPT];
+ unsigned nccompare;
+ uint32_t timerint[MAX_NCCOMPARE];
+ unsigned nextint;
+ unsigned extint[MAX_NINTERRUPT];
+
+ unsigned debug_level;
+ unsigned nibreak;
+ unsigned ndbreak;
+
+ uint32_t clock_freq_khz;
+
+ xtensa_tlb itlb;
+ xtensa_tlb dtlb;
+} XtensaCPUClass;
+
+/**
+ * XtensaCPU:
+ * @env: Legacy CPU state.
+ *
+ * An Xtensa CPU.
+ */
+typedef struct XtensaCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUXtensaState env;
+} XtensaCPU;
+
+static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
+{
+ return XTENSA_CPU(container_of(env, XtensaCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
+
+
+#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
+
+static inline bool xtensa_option_bits_enabled(XtensaCPUClass *klass,
+ uint64_t opt)
+{
+ return (klass->options & opt) != 0;
+}
+
+static inline bool xtensa_option_enabled(XtensaCPUClass *klass, int opt)
+{
+ return xtensa_option_bits_enabled(klass, XTENSA_OPTION_BIT(opt));
+}
+
+static inline bool xtensa_cpu_option_enabled(XtensaCPU *cpu, int opt)
+{
+ return xtensa_option_enabled(XTENSA_CPU_GET_CLASS(cpu), opt);
+}
+
+static inline int xtensa_get_cintlevel(XtensaCPU *cpu)
+{
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ CPUXtensaState *env = &cpu->env;
+ int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
+ if ((env->sregs[PS] & PS_EXCM) && klass->excm_level > level) {
+ level = klass->excm_level;
+ }
+ return level;
+}
+
+static inline int xtensa_get_debug_level(XtensaCPU *cpu)
+{
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ return klass->debug_level;
+}
+
+static inline int xtensa_get_ring(XtensaCPU *cpu)
+{
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
+ return (cpu->env.sregs[PS] & PS_RING) >> PS_RING_SHIFT;
+ } else {
+ return 0;
+ }
+}
+
+static inline int xtensa_get_cring(XtensaCPU *cpu)
+{
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU) &&
+ (cpu->env.sregs[PS] & PS_EXCM) == 0) {
+ return (cpu->env.sregs[PS] & PS_RING) >> PS_RING_SHIFT;
+ } else {
+ return 0;
+ }
+}
+
+
+#endif
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
new file mode 100644
index 0000000..54f4ffc
--- /dev/null
+++ b/target-xtensa/cpu.c
@@ -0,0 +1,87 @@
+/*
+ * QEMU Xtensa CPU
+ *
+ * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void xtensa_cpu_reset(CPUState *c)
+{
+ XtensaCPU *cpu = XTENSA_CPU(c);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ CPUXtensaState *env = &cpu->env;
+
+ klass->parent_reset(c);
+
+ env->exception_taken = 0;
+ env->pc = klass->exception_vector[EXC_RESET];
+ env->sregs[LITBASE] &= ~1;
+ env->sregs[PS] = xtensa_option_enabled(klass,
+ XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
+ env->sregs[VECBASE] = klass->vecbase;
+ env->sregs[IBREAKENABLE] = 0;
+
+ env->pending_irq_level = 0;
+ reset_mmu(cpu);
+}
+
+static void xtensa_cpu_initfn(Object *obj)
+{
+ XtensaCPU *cpu = XTENSA_CPU(obj);
+ CPUXtensaState *env = &cpu->env;
+
+ cpu_exec_init(env);
+ xtensa_irq_init(env);
+}
+
+static void xtensa_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ XtensaCPUClass *k = XTENSA_CPU_CLASS(klass);
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = xtensa_cpu_reset;
+}
+
+static const TypeInfo xtensa_cpu_info = {
+ .name = TYPE_XTENSA_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(XtensaCPU),
+ .instance_init = xtensa_cpu_initfn,
+ .abstract = true,
+ .class_size = sizeof(XtensaCPUClass),
+ .class_init = xtensa_cpu_class_init,
+};
+
+static void xtensa_cpu_register_types(void)
+{
+ type_register_static(&xtensa_cpu_info);
+}
+
+type_init(xtensa_cpu_register_types)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index a7bcf52..1191dcf 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -260,66 +260,7 @@ typedef struct xtensa_tlb_entry {
bool variable;
} xtensa_tlb_entry;
-typedef struct xtensa_tlb {
- unsigned nways;
- const unsigned way_size[10];
- bool varway56;
- unsigned nrefillentries;
-} xtensa_tlb;
-
-typedef struct XtensaGdbReg {
- int targno;
- int type;
- int group;
-} XtensaGdbReg;
-
-typedef struct XtensaGdbRegmap {
- int num_regs;
- int num_core_regs;
- /* PC + a + ar + sr + ur */
- XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
-} XtensaGdbRegmap;
-
-typedef struct XtensaConfig {
- const char *name;
- uint64_t options;
- XtensaGdbRegmap gdb_regmap;
- unsigned nareg;
- int excm_level;
- int ndepc;
- uint32_t vecbase;
- uint32_t exception_vector[EXC_MAX];
- unsigned ninterrupt;
- unsigned nlevel;
- uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
- uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
- uint32_t inttype_mask[INTTYPE_MAX];
- struct {
- uint32_t level;
- interrupt_type inttype;
- } interrupt[MAX_NINTERRUPT];
- unsigned nccompare;
- uint32_t timerint[MAX_NCCOMPARE];
- unsigned nextint;
- unsigned extint[MAX_NINTERRUPT];
-
- unsigned debug_level;
- unsigned nibreak;
- unsigned ndbreak;
-
- uint32_t clock_freq_khz;
-
- xtensa_tlb itlb;
- xtensa_tlb dtlb;
-} XtensaConfig;
-
-typedef struct XtensaConfigList {
- const XtensaConfig *config;
- struct XtensaConfigList *next;
-} XtensaConfigList;
-
typedef struct CPUXtensaState {
- const XtensaConfig *config;
uint32_t regs[16];
uint32_t pc;
uint32_t sregs[256];
@@ -350,10 +291,17 @@ typedef struct CPUXtensaState {
#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list
+typedef struct XtensaCPU XtensaCPU;
+static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env);
+static inline bool xtensa_cpu_option_enabled(XtensaCPU *klass, int opt);
+static inline int xtensa_get_cintlevel(XtensaCPU *cpu);
+static inline int xtensa_get_debug_level(XtensaCPU *cpu);
+static inline int xtensa_get_ring(XtensaCPU *cpu);
+static inline int xtensa_get_cring(XtensaCPU *cpu);
+
CPUXtensaState *cpu_xtensa_init(const char *cpu_model);
void xtensa_translate_init(void);
int cpu_xtensa_exec(CPUXtensaState *s);
-void xtensa_register_core(XtensaConfigList *node);
void do_interrupt(CPUXtensaState *s);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
@@ -377,49 +325,9 @@ int xtensa_get_physical_addr(CPUXtensaState *env,
uint32_t *paddr, uint32_t *page_size, unsigned *access);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
+void reset_mmu(XtensaCPU *cpu);
-#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
-
-static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
- uint64_t opt)
-{
- return (config->options & opt) != 0;
-}
-
-static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
-{
- return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
-}
-
-static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
-{
- int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
- if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
- level = env->config->excm_level;
- }
- return level;
-}
-
-static inline int xtensa_get_ring(const CPUXtensaState *env)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
- } else {
- return 0;
- }
-}
-
-static inline int xtensa_get_cring(const CPUXtensaState *env)
-{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
- (env->sregs[PS] & PS_EXCM) == 0) {
- return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
- } else {
- return 0;
- }
-}
-
static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
bool dtlb, unsigned wi, unsigned ei)
{
@@ -436,7 +344,7 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
static inline int cpu_mmu_index(CPUXtensaState *env)
{
- return xtensa_get_cring(env);
+ return xtensa_get_cring(xtensa_env_get_cpu(env));
}
#define XTENSA_TBFLAG_RING_MASK 0x3
@@ -448,28 +356,31 @@ static inline int cpu_mmu_index(CPUXtensaState *env)
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
*pc = env->pc;
*cs_base = 0;
*flags = 0;
- *flags |= xtensa_get_ring(env);
+ *flags |= xtensa_get_ring(cpu);
if (env->sregs[PS] & PS_EXCM) {
*flags |= XTENSA_TBFLAG_EXCM;
}
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_EXTENDED_L32R) &&
(env->sregs[LITBASE] & 1)) {
*flags |= XTENSA_TBFLAG_LITBASE;
}
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
- if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_DEBUG)) {
+ if (xtensa_get_cintlevel(cpu) < xtensa_get_debug_level(cpu)) {
*flags |= XTENSA_TBFLAG_DEBUG;
}
- if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+ if (xtensa_get_cintlevel(cpu) < env->sregs[ICOUNTLEVEL]) {
*flags |= XTENSA_TBFLAG_ICOUNT;
}
}
}
#include "cpu-all.h"
+#include "cpu-qom.h"
#include "exec-all.h"
static inline int cpu_has_work(CPUXtensaState *env)
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index dab135c..3433228 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -33,35 +33,18 @@
#include "hw/loader.h"
#endif
-static void reset_mmu(CPUXtensaState *env);
-
void cpu_state_reset(CPUXtensaState *env)
{
- env->exception_taken = 0;
- env->pc = env->config->exception_vector[EXC_RESET];
- env->sregs[LITBASE] &= ~1;
- env->sregs[PS] = xtensa_option_enabled(env->config,
- XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
- env->sregs[VECBASE] = env->config->vecbase;
- env->sregs[IBREAKENABLE] = 0;
-
- env->pending_irq_level = 0;
- reset_mmu(env);
+ cpu_reset(ENV_GET_CPU(env));
}
-static struct XtensaConfigList *xtensa_cores;
-
-void xtensa_register_core(XtensaConfigList *node)
-{
- node->next = xtensa_cores;
- xtensa_cores = node;
-}
-
-static uint32_t check_hw_breakpoints(CPUXtensaState *env)
+static uint32_t check_hw_breakpoints(XtensaCPU *cpu)
{
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ CPUXtensaState *env = &cpu->env;
unsigned i;
- for (i = 0; i < env->config->ndbreak; ++i) {
+ for (i = 0; i < klass->ndbreak; ++i) {
if (env->cpu_watchpoint[i] &&
env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
@@ -76,10 +59,11 @@ static void breakpoint_handler(CPUXtensaState *env)
{
if (env->watchpoint_hit) {
if (env->watchpoint_hit->flags & BP_CPU) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
uint32_t cause;
env->watchpoint_hit = NULL;
- cause = check_hw_breakpoints(env);
+ cause = check_hw_breakpoints(cpu);
if (cause) {
debug_exception_env(env, cause);
}
@@ -95,23 +79,14 @@ CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
{
static int tcg_inited;
static int debug_handler_inited;
+ XtensaCPU *cpu;
CPUXtensaState *env;
- const XtensaConfig *config = NULL;
- XtensaConfigList *core = xtensa_cores;
- for (; core; core = core->next)
- if (strcmp(core->config->name, cpu_model) == 0) {
- config = core->config;
- break;
- }
-
- if (config == NULL) {
+ if (object_class_by_name(cpu_model) == NULL) {
return NULL;
}
-
- env = g_malloc0(sizeof(*env));
- env->config = config;
- cpu_exec_init(env);
+ cpu = XTENSA_CPU(object_new(cpu_model));
+ env = &cpu->env;
if (!tcg_inited) {
tcg_inited = 1;
@@ -124,19 +99,48 @@ CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
cpu_set_debug_excp_handler(breakpoint_handler);
}
- xtensa_irq_init(env);
qemu_init_vcpu(env);
return env;
}
+typedef struct XtensaCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} XtensaCPUListState;
+
+/* Sort alphabetically. */
+static gint xtensa_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
+}
+
+static void xtensa_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *klass = data;
+ XtensaCPUListState *s = user_data;
+
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
+}
+
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
- XtensaConfigList *core = xtensa_cores;
+ XtensaCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_XTENSA_CPU, false);
+ list = g_slist_sort(list, xtensa_cpu_list_compare);
cpu_fprintf(f, "Available CPUs:\n");
- for (; core; core = core->next) {
- cpu_fprintf(f, " %s\n", core->config->name);
- }
+ g_slist_foreach(list, xtensa_cpu_list_entry, &s);
+ g_slist_free(list);
}
target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
@@ -158,9 +162,12 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong add
static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
{
- if (xtensa_option_enabled(env->config,
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ if (xtensa_option_enabled(klass,
XTENSA_OPTION_RELOCATABLE_VECTOR)) {
- return vector - env->config->vecbase + env->sregs[VECBASE];
+ return vector - klass->vecbase + env->sregs[VECBASE];
} else {
return vector;
}
@@ -174,11 +181,13 @@ static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
*/
static void handle_interrupt(CPUXtensaState *env)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
int level = env->pending_irq_level;
- if (level > xtensa_get_cintlevel(env) &&
- level <= env->config->nlevel &&
- (env->config->level_mask[level] &
+ if (level > xtensa_get_cintlevel(cpu) &&
+ level <= klass->nlevel &&
+ (klass->level_mask[level] &
env->sregs[INTSET] &
env->sregs[INTENABLE])) {
if (level > 1) {
@@ -187,12 +196,12 @@ static void handle_interrupt(CPUXtensaState *env)
env->sregs[PS] =
(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
env->pc = relocated_vector(env,
- env->config->interrupt_vector[level]);
+ klass->interrupt_vector[level]);
} else {
env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
if (env->sregs[PS] & PS_EXCM) {
- if (env->config->ndepc) {
+ if (klass->ndepc) {
env->sregs[DEPC] = env->pc;
} else {
env->sregs[EPC1] = env->pc;
@@ -211,13 +220,16 @@ static void handle_interrupt(CPUXtensaState *env)
void do_interrupt(CPUXtensaState *env)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
if (env->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
"%s(EXC_IRQ) level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
"intset = %08x, intenable = %08x, "
"ccount = %08x\n",
- __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
+ __func__, env->pending_irq_level, xtensa_get_cintlevel(cpu),
env->pc, env->regs[0], env->sregs[PS],
env->sregs[INTSET], env->sregs[INTENABLE],
env->sregs[CCOUNT]);
@@ -239,9 +251,9 @@ void do_interrupt(CPUXtensaState *env)
"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
__func__, env->exception_index,
env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
- if (env->config->exception_vector[env->exception_index]) {
+ if (klass->exception_vector[env->exception_index]) {
env->pc = relocated_vector(env,
- env->config->exception_vector[env->exception_index]);
+ klass->exception_vector[env->exception_index]);
env->exception_taken = 1;
} else {
qemu_log("%s(pc = %08x) bad exception_index: %d\n",
@@ -334,17 +346,20 @@ static void reset_tlb_region_way0(CPUXtensaState *env,
}
}
-static void reset_mmu(CPUXtensaState *env)
+void reset_mmu(XtensaCPU *cpu)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+ CPUXtensaState *env = &cpu->env;
+
+ if (xtensa_option_enabled(klass, XTENSA_OPTION_MMU)) {
env->sregs[RASID] = 0x04030201;
env->sregs[ITLBCFG] = 0;
env->sregs[DTLBCFG] = 0;
env->autorefill_idx = 0;
- reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
- reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
- reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
- reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
+ reset_tlb_mmu_all_ways(env, &klass->itlb, env->itlb);
+ reset_tlb_mmu_all_ways(env, &klass->dtlb, env->dtlb);
+ reset_tlb_mmu_ways56(env, &klass->itlb, env->itlb);
+ reset_tlb_mmu_ways56(env, &klass->dtlb, env->dtlb);
} else {
reset_tlb_region_way0(env, env->itlb);
reset_tlb_region_way0(env, env->dtlb);
@@ -374,8 +389,10 @@ static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
const xtensa_tlb *tlb = dtlb ?
- &env->config->dtlb : &env->config->itlb;
+ &klass->dtlb : &klass->itlb;
const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
env->dtlb : env->itlb;
@@ -567,10 +584,13 @@ int xtensa_get_physical_addr(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ if (xtensa_option_enabled(klass, XTENSA_OPTION_MMU)) {
return get_physical_addr_mmu(env, vaddr, is_write, mmu_idx,
paddr, page_size, access);
- } else if (xtensa_option_bits_enabled(env->config,
+ } else if (xtensa_option_bits_enabled(klass,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
@@ -586,11 +606,13 @@ int xtensa_get_physical_addr(CPUXtensaState *env,
static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
CPUXtensaState *env, bool dtlb)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
unsigned wi, ei;
const xtensa_tlb *conf =
- dtlb ? &env->config->dtlb : &env->config->itlb;
+ dtlb ? &klass->dtlb : &klass->itlb;
unsigned (*attr_to_access)(uint32_t) =
- xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
+ xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU) ?
mmu_attr_to_access : region_attr_to_access;
for (wi = 0; wi < conf->nways; ++wi) {
@@ -636,7 +658,10 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
{
- if (xtensa_option_bits_enabled(env->config,
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ if (xtensa_option_bits_enabled(klass,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cdef0db..96d293f 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -62,8 +62,10 @@ static void do_restore_state(void *pc_ptr)
static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
void *retaddr)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
- !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
+ !xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_HW_ALIGNMENT)) {
do_restore_state(retaddr);
HELPER(exception_cause_vaddr)(
env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
@@ -107,11 +109,13 @@ void HELPER(exception)(uint32_t excp)
void HELPER(exception_cause)(uint32_t pc, uint32_t cause)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
uint32_t vector;
env->pc = pc;
if (env->sregs[PS] & PS_EXCM) {
- if (env->config->ndepc) {
+ if (klass->ndepc) {
env->sregs[DEPC] = pc;
} else {
env->sregs[EPC1] = pc;
@@ -136,7 +140,9 @@ void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
void debug_exception_env(CPUXtensaState *new_env, uint32_t cause)
{
- if (xtensa_get_cintlevel(new_env) < new_env->config->debug_level) {
+ XtensaCPU *new_cpu = xtensa_env_get_cpu(new_env);
+
+ if (xtensa_get_cintlevel(new_cpu) < xtensa_get_debug_level(new_cpu)) {
env = new_env;
HELPER(debug_exception)(env->pc, cause);
}
@@ -144,7 +150,8 @@ void debug_exception_env(CPUXtensaState *new_env, uint32_t cause)
void HELPER(debug_exception)(uint32_t pc, uint32_t cause)
{
- unsigned level = env->config->debug_level;
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ unsigned level = xtensa_get_debug_level(cpu);
env->pc = pc;
env->sregs[DEBUGCAUSE] = cause;
@@ -171,12 +178,15 @@ uint32_t HELPER(nsau)(uint32_t v)
static void copy_window_from_phys(CPUXtensaState *env,
uint32_t window, uint32_t phys, uint32_t n)
{
- assert(phys < env->config->nareg);
- if (phys + n <= env->config->nareg) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ assert(phys < klass->nareg);
+ if (phys + n <= klass->nareg) {
memcpy(env->regs + window, env->phys_regs + phys,
n * sizeof(uint32_t));
} else {
- uint32_t n1 = env->config->nareg - phys;
+ uint32_t n1 = klass->nareg - phys;
memcpy(env->regs + window, env->phys_regs + phys,
n1 * sizeof(uint32_t));
memcpy(env->regs + window + n1, env->phys_regs,
@@ -187,12 +197,15 @@ static void copy_window_from_phys(CPUXtensaState *env,
static void copy_phys_from_window(CPUXtensaState *env,
uint32_t phys, uint32_t window, uint32_t n)
{
- assert(phys < env->config->nareg);
- if (phys + n <= env->config->nareg) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ assert(phys < klass->nareg);
+ if (phys + n <= klass->nareg) {
memcpy(env->phys_regs + phys, env->regs + window,
n * sizeof(uint32_t));
} else {
- uint32_t n1 = env->config->nareg - phys;
+ uint32_t n1 = klass->nareg - phys;
memcpy(env->phys_regs + phys, env->regs + window,
n1 * sizeof(uint32_t));
memcpy(env->phys_regs, env->regs + window + n1,
@@ -203,7 +216,10 @@ static void copy_phys_from_window(CPUXtensaState *env,
static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
{
- return a & (env->config->nareg / 4 - 1);
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ return a & (klass->nareg / 4 - 1);
}
static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
@@ -382,6 +398,8 @@ void HELPER(dump_state)(void)
void HELPER(waiti)(uint32_t pc, uint32_t intlevel)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
env->pc = pc;
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
(intlevel << PS_INTLEVEL_SHIFT);
@@ -393,7 +411,7 @@ void HELPER(waiti)(uint32_t pc, uint32_t intlevel)
env->halt_clock = qemu_get_clock_ns(vm_clock);
env->halted = 1;
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_TIMER_INTERRUPT)) {
xtensa_rearm_ccompare_timer(env);
}
HELPER(exception)(EXCP_HLT);
@@ -447,10 +465,13 @@ static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way
*/
uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
bool varway56 = dtlb ?
- env->config->dtlb.varway56 :
- env->config->itlb.varway56;
+ klass->dtlb.varway56 :
+ klass->itlb.varway56;
switch (way) {
case 4:
@@ -484,18 +505,21 @@ uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t
*/
static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
if (way < 4) {
bool is32 = (dtlb ?
- env->config->dtlb.nrefillentries :
- env->config->itlb.nrefillentries) == 32;
+ klass->dtlb.nrefillentries :
+ klass->itlb.nrefillentries) == 32;
return is32 ? 0xffff8000 : 0xffffc000;
} else if (way == 4) {
return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
} else if (way <= 6) {
uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
bool varway56 = dtlb ?
- env->config->dtlb.varway56 :
- env->config->itlb.varway56;
+ klass->dtlb.varway56 :
+ klass->itlb.varway56;
if (varway56) {
return mask << (way == 5 ? 2 : 3);
@@ -514,9 +538,12 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
+
bool varway56 = dtlb ?
- env->config->dtlb.varway56 :
- env->config->itlb.varway56;
+ klass->dtlb.varway56 :
+ klass->itlb.varway56;
if (!dtlb) {
wi &= 7;
@@ -524,8 +551,8 @@ void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
if (wi < 4) {
bool is32 = (dtlb ?
- env->config->dtlb.nrefillentries :
- env->config->itlb.nrefillentries) == 32;
+ klass->dtlb.nrefillentries :
+ klass->itlb.nrefillentries) == 32;
*ei = (v >> 12) & (is32 ? 0x7 : 0x3);
} else {
switch (wi) {
@@ -569,7 +596,9 @@ void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
static void split_tlb_entry_spec(uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t *wi, uint32_t *ei)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
*wi = v & (dtlb ? 0xf : 0x7);
split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
} else {
@@ -594,7 +623,9 @@ static xtensa_tlb_entry *get_tlb_entry(uint32_t v, bool dtlb, uint32_t *pwi)
uint32_t HELPER(rtlb0)(uint32_t v, uint32_t dtlb)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
@@ -611,7 +642,9 @@ uint32_t HELPER(rtlb1)(uint32_t v, uint32_t dtlb)
void HELPER(itlb)(uint32_t v, uint32_t dtlb)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
if (entry->variable && entry->asid) {
@@ -623,7 +656,9 @@ void HELPER(itlb)(uint32_t v, uint32_t dtlb)
uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
{
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
uint32_t wi;
uint32_t ei;
uint8_t ring;
@@ -631,7 +666,7 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
switch (res) {
case 0:
- if (ring >= xtensa_get_ring(env)) {
+ if (ring >= xtensa_get_ring(cpu)) {
return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
}
break;
@@ -650,9 +685,10 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
+ if (xtensa_cpu_option_enabled(cpu, XTENSA_OPTION_MMU)) {
if (entry->variable) {
if (entry->asid) {
tlb_flush_page(env, entry->vaddr);
@@ -667,7 +703,7 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
}
} else {
tlb_flush_page(env, entry->vaddr);
- if (xtensa_option_enabled(env->config,
+ if (xtensa_cpu_option_enabled(cpu,
XTENSA_OPTION_REGION_TRANSLATION)) {
entry->paddr = pte & REGION_PAGE_MASK;
}
@@ -687,16 +723,18 @@ void HELPER(wtlb)(uint32_t p, uint32_t v, uint32_t dtlb)
void HELPER(wsr_ibreakenable)(uint32_t v)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
uint32_t change = v ^ env->sregs[IBREAKENABLE];
unsigned i;
- for (i = 0; i < env->config->nibreak; ++i) {
+ for (i = 0; i < klass->nibreak; ++i) {
if (change & (1 << i)) {
tb_invalidate_phys_page_range(
env->sregs[IBREAKA + i], env->sregs[IBREAKA + i] + 1, 0);
}
}
- env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
+ env->sregs[IBREAKENABLE] = v & ((1 << klass->nibreak) - 1);
}
void HELPER(wsr_ibreaka)(uint32_t i, uint32_t v)
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index a3a5650..b46bca9 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@ -291,16 +291,28 @@
#endif
#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
-#define REGISTER_CORE(core) \
- static void __attribute__((constructor)) register_core(void) \
+#define REGISTER_CORE(typename, class) \
+ static void core_class_init(ObjectClass *klass, void *data) \
{ \
- static XtensaConfigList node = { \
- .config = &core, \
- }; \
- xtensa_register_core(&node); \
- }
+ /* XXX This is a really ugly but easy way to init the class... */ \
+ memcpy((void *)klass + offsetof(XtensaCPUClass, options), \
+ (void *)&(class) + offsetof(XtensaCPUClass, options), \
+ sizeof(XtensaCPUClass) - offsetof(XtensaCPUClass, options)); \
+ } \
+ static const TypeInfo core_info = { \
+ .name = (typename), \
+ .parent = TYPE_XTENSA_CPU, \
+ .instance_size = sizeof(XtensaCPU), \
+ .class_size = sizeof(XtensaCPUClass), \
+ .class_init = core_class_init, \
+ }; \
+ static void register_core_type(void) \
+ { \
+ type_register_static(&core_info); \
+ } \
+ type_init(register_core_type)
#else
-#define REGISTER_CORE(core)
+#define REGISTER_CORE(name, core)
#endif
#define DEBUG_SECTION \
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index e0ff72b..b05b83e 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -42,7 +42,7 @@
#include "helpers.h"
typedef struct DisasContext {
- const XtensaConfig *config;
+ XtensaCPUClass *config;
TranslationBlock *tb;
uint32_t pc;
uint32_t next_pc;
@@ -2524,6 +2524,7 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
static void gen_intermediate_code_internal(
CPUXtensaState *env, TranslationBlock *tb, int search_pc)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
DisasContext dc;
int insn_count = 0;
int j, lj = -1;
@@ -2537,7 +2538,7 @@ static void gen_intermediate_code_internal(
max_insns = CF_COUNT_MASK;
}
- dc.config = env->config;
+ dc.config = XTENSA_CPU_GET_CLASS(cpu);
dc.singlestep_enabled = env->singlestep_enabled;
dc.tb = tb;
dc.pc = pc_start;
@@ -2657,6 +2658,8 @@ void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
int i, j;
cpu_fprintf(f, "PC=%08x\n\n", env->pc);
@@ -2686,7 +2689,7 @@ void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n");
- for (i = 0; i < env->config->nareg; ++i) {
+ for (i = 0; i < klass->nareg; ++i) {
cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
(i % 4) == 3 ? '\n' : ' ');
}
--
1.7.7
^ permalink raw reply related [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 04/12] target-alpha: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
@ 2012-03-14 17:59 ` Richard Henderson
0 siblings, 0 replies; 175+ messages in thread
From: Richard Henderson @ 2012-03-14 17:59 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On 03/14/12 10:53, Andreas Färber wrote:
> Embed CPUAlphaState in AlphaCPU.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> Makefile.target | 1 +
> target-alpha/cpu-qom.h | 74 +++++++++++++++++++++++++++
> target-alpha/cpu.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++
> target-alpha/cpu.h | 1 +
> target-alpha/translate.c | 60 +++-------------------
> 5 files changed, 211 insertions(+), 52 deletions(-)
> create mode 100644 target-alpha/cpu-qom.h
> create mode 100644 target-alpha/cpu.c
Looks plausible. I admit to not having followed QOM at all...
Acked-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC
2012-03-14 16:06 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
@ 2012-03-14 18:25 ` Andreas Färber
0 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 18:25 UTC (permalink / raw)
To: Peter Maydell
Cc: Anthony Liguori, Paolo Bonzini, qemu-devel, Aurélien Jarno
Am 14.03.2012 17:06, schrieb Peter Maydell:
> On 14 March 2012 16:01, Andreas Färber <afaerber@suse.de> wrote:
>> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
>> the SuperH CPU to QOM.
>>
>> The SH7750 SoC code invited to do some cleanups, making use of the SuperHCPU,
>> so I've QOM'ified the SoC and added the CPU as a link<SuperHCPU> for now.
>>
>> I'm not so happy about the link construct, so it may need to be redone
>> as a SysBus device with qdev properties
>
> Shouldn't the CPU be a child of the SoC, not a link?
Exactly. Issue was twofold:
1) There is no object_property_set_child(), and using
object_property_add_child() in the machine for the SoC seemed wrong.
Setting the link target allowed to set the field in the state struct via
QOM without reintroducing qdev pointer properties.
2) The SH7750 SoC is expected to have one of three user-selectable CPU
cores (SH7750, SH7750R and SH7751 iirc) and this somewhat violates the
layering. Making it a SysBus device with a string property to tunnel
through the cpu_model is what I'm referring to below for v2.
>> - long-term I'd like to have a
>> "system-on-chip" type derived from TYPE_DEVICE. Deriving it from
>> TYPE_SYS_BUS_DEVICE might make for a better v2.
>
> I think TYPE_SYS_BUS_DEVICE should go away in favour of everything
> being a TYPE_DEVICE.
>
> What do you think a "system-on-chip" type would be needed for?
> I would have expected that SoCs would basically just be "containers"
> of devices and directly be TYPE_DEVICEs...
I was thinking that SoCs should have a fixed relation to particular CPU
core(s). -cpu exynos4210 would then select CPUs+x, we therefore need to
type-check it, and only features (NEON) etc. would be tweakable via QOM.
As opposed to having a fixed SoC like this one here and trying to fiddle
with its internals.
In particular I have decoupling of SoC from machine in mind: for Tegra2
I have tegra2.c defining a "tegra2-soc" type and am preparing an "ac100"
machine in tegra2_boards.c that trivially does an
object_new(TYPE_TEGRA2) that in turn instantiates all the SoC-level
SysBus devices in its initfn.
So, I think CPUs, and SoCs as CPU parent, are a special case of device.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 14/44] target-arm: Don't overuse CPUState
2012-03-14 14:39 ` Peter Maydell
@ 2012-03-14 18:33 ` Andreas Färber
0 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 18:33 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Am 14.03.2012 15:39, schrieb Peter Maydell:
> On 10 March 2012 02:27, Andreas Färber <afaerber@suse.de> wrote:
>> Scripted conversion:
>> sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc]
>> sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>
> Some of these automated changes in iwmmxt_helper.c break the
> neatly lined up '\' macro continuation characters...
> I'm not sure I care enough to suggest that we should manually fix
> this though, especially not for the ones which are full of hard
> coded tabs.
>
> Acked-by: Peter Maydell <peter.maydell@linaro.org>
I didn't check every line of these automated conversions - breaking
alignment, overflowing 80 chars and not fixing
whitespace/braces/indentation on the modified lines are therefore quite
possible.
I'd rather not hack such fixes into this patch wrt rebasing but would
suggest to allow trivial cleanup patches where sensible afterwards.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-14 20:37 ` Igor Mitsyanko
@ 2012-03-14 19:48 ` Anthony Liguori
2012-03-14 19:57 ` Andreas Färber
2012-03-14 20:37 ` Andreas Färber
1 sibling, 1 reply; 175+ messages in thread
From: Anthony Liguori @ 2012-03-14 19:48 UTC (permalink / raw)
To: i.mitsyanko
Cc: Igor Mitsyanko, qemu-devel, d.solodkiy, Paolo Bonzini,
Igor Mammedov, Andreas Färber
On 03/14/2012 03:37 PM, Igor Mitsyanko wrote:
> On 13.03.2012 3:13 PM, Andreas Färber wrote:
>
>> In SysBusDeviceClass etc. we use the specific object type, too.
>> Obviously my CPU is the first "new" QOM type, so we can go different
>> ways if we want to. As long as it's a CPU-specific mechanism, using the
>> specific type avoids some casts.
>>
>>> It will be easier to generalize later qdev code and not make special
>>> case when
>>> adding cpus.
>>
>> I never heard anyone wanting to generalize reset so far. I don't think
>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>>
>
> We can have a special object for this, let's call it ResetLine for example, with
> methods ResetLine::connect, ResetLine::assert or something like that. Different
> ResetLine objects could trigger reset of different sets of subdevices, just like
> real hardware can have several reset types (for example, STM32 has 3 different
> reset types).
I've explored a bunch of different models for this. My current thinking is a
realized:bool property that when set, would call a realize() virtual method and
when unset would call an unrealize() virtual method. The default implementation
of [un]realize() would propagate the change to all composition children.
At one point, I modeled this as a Vcc Pin with similar semantics except that
instead of relying on a property accessor, the realize function would connect to
the device's Vcc pin to the children's Vcc pins via a set of Wire objects (that
just propagate Pin state).
This later model is too low level IMHO. I think we should stick with the
functional realize property which covers 99% of devices. For the 1%, we can use
pins or just have additional properties as appropriate.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-14 19:48 ` Anthony Liguori
@ 2012-03-14 19:57 ` Andreas Färber
2012-03-14 20:01 ` Anthony Liguori
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 19:57 UTC (permalink / raw)
To: Anthony Liguori
Cc: i.mitsyanko, Igor Mitsyanko, qemu-devel, d.solodkiy,
Paolo Bonzini, Igor Mammedov
Am 14.03.2012 20:48, schrieb Anthony Liguori:
> On 03/14/2012 03:37 PM, Igor Mitsyanko wrote:
>> On 13.03.2012 3:13 PM, Andreas Färber wrote:
>>
>>> In SysBusDeviceClass etc. we use the specific object type, too.
>>> Obviously my CPU is the first "new" QOM type, so we can go different
>>> ways if we want to. As long as it's a CPU-specific mechanism, using the
>>> specific type avoids some casts.
>>>
>>>> It will be easier to generalize later qdev code and not make special
>>>> case when
>>>> adding cpus.
>>>
>>> I never heard anyone wanting to generalize reset so far. I don't think
>>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>>>
>>
>> We can have a special object for this, let's call it ResetLine for
>> example, with
>> methods ResetLine::connect, ResetLine::assert or something like that.
>> Different
>> ResetLine objects could trigger reset of different sets of subdevices,
>> just like
>> real hardware can have several reset types (for example, STM32 has 3
>> different
>> reset types).
>
> I've explored a bunch of different models for this. My current thinking
> is a realized:bool property that when set, would call a realize()
> virtual method and when unset would call an unrealize() virtual method.
> The default implementation of [un]realize() would propagate the change
> to all composition children.
I've found that model not to work with today's qdev remainders: We often
have a dependency tree of initfn and init a.k.a. realize functions, so
that we can't clearly separate between the two to do recursive
processing. Unless we do a three-stage initialization of Object::initfn,
what-is-now-DeviceState::init, Object::realize.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-14 19:57 ` Andreas Färber
@ 2012-03-14 20:01 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-14 20:01 UTC (permalink / raw)
To: Andreas Färber
Cc: i.mitsyanko, Igor Mitsyanko, qemu-devel, d.solodkiy,
Paolo Bonzini, Igor Mammedov
On 03/14/2012 02:57 PM, Andreas Färber wrote:
> Am 14.03.2012 20:48, schrieb Anthony Liguori:
>> On 03/14/2012 03:37 PM, Igor Mitsyanko wrote:
>>> On 13.03.2012 3:13 PM, Andreas Färber wrote:
>>>
>>>> In SysBusDeviceClass etc. we use the specific object type, too.
>>>> Obviously my CPU is the first "new" QOM type, so we can go different
>>>> ways if we want to. As long as it's a CPU-specific mechanism, using the
>>>> specific type avoids some casts.
>>>>
>>>>> It will be easier to generalize later qdev code and not make special
>>>>> case when
>>>>> adding cpus.
>>>>
>>>> I never heard anyone wanting to generalize reset so far. I don't think
>>>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>>>>
>>>
>>> We can have a special object for this, let's call it ResetLine for
>>> example, with
>>> methods ResetLine::connect, ResetLine::assert or something like that.
>>> Different
>>> ResetLine objects could trigger reset of different sets of subdevices,
>>> just like
>>> real hardware can have several reset types (for example, STM32 has 3
>>> different
>>> reset types).
>>
>> I've explored a bunch of different models for this. My current thinking
>> is a realized:bool property that when set, would call a realize()
>> virtual method and when unset would call an unrealize() virtual method.
>> The default implementation of [un]realize() would propagate the change
>> to all composition children.
>
> I've found that model not to work with today's qdev remainders: We often
> have a dependency tree of initfn and init a.k.a. realize functions, so
> that we can't clearly separate between the two to do recursive
> processing. Unless we do a three-stage initialization of Object::initfn,
> what-is-now-DeviceState::init, Object::realize.
Yes, there's quite a lot of refactoring to get to a two stage recursive init.
This is why realized isn't a part of QOM/qdev today.
Regards,
Anthony Liguori
>
> Andreas
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
` (7 preceding siblings ...)
2012-03-14 7:32 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
@ 2012-03-14 20:02 ` Blue Swirl
2012-03-14 23:23 ` Anthony Liguori
8 siblings, 1 reply; 175+ messages in thread
From: Blue Swirl @ 2012-03-14 20:02 UTC (permalink / raw)
To: Andreas Färber; +Cc: Guan Xue-tao, qemu-devel, Anthony Liguori
On Wed, Mar 14, 2012 at 01:39, Andreas Färber <afaerber@suse.de> wrote:
> Hello,
>
> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
> the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to
> target-arm and faces a similar issue of CPU-dependent init code, so let's
> tackle it next.
>
> Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS,
> so that the target-unicore32 author gets notified of patches against his code.
>
> Patch 2, based on feedback from Guan Xuetao, changes the license of most
> target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a
> qemu_malloc() -> g_malloc() substitution that he can't relicense at this time,
> so leave that as GPLv2 and declare my following patches explicitly as GPLv2+.
Perhaps g_malloc() patch could be partially reverted and a new GPLv2+
patch applied which uses g_new()?
> Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h header
> can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2 for now.
>
> Patches 4-7 move code out of the uc32_cpu_init() function and into classes.
>
> Regards,
> Andreas
>
> Cc: Guan Xue-tao <gxt@mprc.pku.edu.cn>
> Cc: Anthony Liguori <anthony@codemonkey.ws>
>
> Changes from former repo.or.cz qom-cpu[-wip] branch:
> * Drop duplicate .instance_init.
>
> Andreas Färber (7):
> MAINTAINERS: Add entry for UniCore32
> target-unicore32: Relicense to GPLv2+
> target-unicore32: QOM'ify CPU
> target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass
> target-unicore32: Store cp0 c1_sys in UniCore32CPUClass
> target-unicore32: Store feature flags in UniCore32CPUClass
> target-unicore32: Store ucf64 fpscr in UniCore32CPUClass
>
> MAINTAINERS | 5 ++
> Makefile.target | 1 +
> target-unicore32/cpu-qom.h | 81 ++++++++++++++++++++++++++++++
> target-unicore32/cpu.c | 112 ++++++++++++++++++++++++++++++++++++++++++
> target-unicore32/cpu.h | 10 +---
> target-unicore32/helper.c | 62 ++---------------------
> target-unicore32/helper.h | 5 +-
> target-unicore32/op_helper.c | 5 +-
> target-unicore32/translate.c | 5 +-
> 9 files changed, 213 insertions(+), 73 deletions(-)
> create mode 100644 target-unicore32/cpu-qom.h
> create mode 100644 target-unicore32/cpu.c
>
> --
> 1.7.7
>
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
2012-03-14 7:53 ` Guan Xuetao
@ 2012-03-14 20:03 ` Blue Swirl
2012-03-14 21:09 ` Stefan Weil
2 siblings, 0 replies; 175+ messages in thread
From: Blue Swirl @ 2012-03-14 20:03 UTC (permalink / raw)
To: Andreas Färber; +Cc: Stefan Weil, Guan Xuetao, Dor Laor, qemu-devel
On Wed, Mar 14, 2012 at 01:39, Andreas Färber <afaerber@suse.de> wrote:
> Adopt the license text suggested by Guan Xue-tao for all files except
> helper.c, to which Anthony Liguori (IBM) contributed a g_malloc() call.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Ack.
> Signed-off-by: Dor Laor <dlaor@redhat.com>
> ---
> target-unicore32/cpu.h | 5 ++---
> target-unicore32/helper.h | 5 ++---
> target-unicore32/op_helper.c | 5 ++---
> target-unicore32/translate.c | 5 ++---
> 4 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index a3f8589..9cbee7a 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -3,9 +3,8 @@
> *
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #ifndef __CPU_UC32_H__
> #define __CPU_UC32_H__
> diff --git a/target-unicore32/helper.h b/target-unicore32/helper.h
> index 615de2a..5aa7de8 100644
> --- a/target-unicore32/helper.h
> +++ b/target-unicore32/helper.h
> @@ -1,9 +1,8 @@
> /*
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #include "def-helper.h"
>
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 638a020..9fc2b1f 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -3,9 +3,8 @@
> *
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #include "cpu.h"
> #include "dyngen-exec.h"
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index 3b3ba16..c01e636 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -3,9 +3,8 @@
> *
> * Copyright (C) 2010-2011 GUAN Xue-tao
> *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * This program is licensed under the terms of the GNU GPL, version 2 or
> + * later. See the COPYING file in the top-level directory.
> */
> #include <stdarg.h>
> #include <stdlib.h>
> --
> 1.7.7
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 11/12] target-sparc: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
@ 2012-03-14 20:16 ` Blue Swirl
2012-03-23 17:27 ` Andreas Färber
0 siblings, 1 reply; 175+ messages in thread
From: Blue Swirl @ 2012-03-14 20:16 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On Wed, Mar 14, 2012 at 17:53, Andreas Färber <afaerber@suse.de> wrote:
> Let sparc_cpu_list() enumerate CPU classes alphabetically.
>
> Introduce sparc_env_get_features() to workaround a circular dependency.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> Makefile.target | 2 +-
> target-sparc/cpu-qom.h | 95 +++++
> target-sparc/cpu.c | 949 +++++++++++++++++++++++++++++++++++++++++++
> target-sparc/cpu.h | 29 +-
> target-sparc/cpu_init.c | 848 --------------------------------------
> target-sparc/int32_helper.c | 5 +-
> target-sparc/ldst_helper.c | 19 +-
> target-sparc/mmu_helper.c | 4 +-
> target-sparc/translate.c | 4 +-
> target-sparc/win_helper.c | 3 +-
> 10 files changed, 1075 insertions(+), 883 deletions(-)
> create mode 100644 target-sparc/cpu-qom.h
> create mode 100644 target-sparc/cpu.c
> delete mode 100644 target-sparc/cpu_init.c
>
> diff --git a/Makefile.target b/Makefile.target
> index 82171ca..1c6ed12 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -100,7 +100,7 @@ libobj-$(TARGET_S390X) += cpu.o
> libobj-$(TARGET_SH4) += cpu.o
> ifeq ($(TARGET_BASE_ARCH), sparc)
> libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
> -libobj-y += cpu_init.o
> +libobj-y += cpu.o
> endif
> libobj-$(TARGET_SPARC) += int32_helper.o
> libobj-$(TARGET_SPARC64) += int64_helper.o
> diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
> new file mode 100644
> index 0000000..15dcf84
> --- /dev/null
> +++ b/target-sparc/cpu-qom.h
> @@ -0,0 +1,95 @@
> +/*
> + * QEMU SPARC CPU
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +#ifndef QEMU_SPARC_CPU_QOM_H
> +#define QEMU_SPARC_CPU_QOM_H
> +
> +#include "qemu/cpu.h"
> +#include "cpu.h"
> +
> +#define TYPE_SPARC_CPU "sparc-cpu"
> +
> +#define SPARC_CPU_CLASS(klass) \
> + OBJECT_CLASS_CHECK(SPARCCPUClass, (klass), TYPE_SPARC_CPU)
> +#define SPARC_CPU(obj) \
> + OBJECT_CHECK(SPARCCPU, (obj), TYPE_SPARC_CPU)
> +#define SPARC_CPU_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU)
> +
> +/**
> + * SPARCCPUClass:
> + * @parent_reset: The parent class' reset handler.
> + *
> + * A SPARC CPU model.
> + */
> +typedef struct SPARCCPUClass {
> + /*< private >*/
> + CPUClass parent_class;
> + /*< public >*/
> +
> + void (*parent_reset)(CPUState *cpu);
> +
> + target_ulong iu_version;
> + uint32_t fpu_version;
> + uint32_t mmu_version;
> + uint32_t mmu_bm;
> + uint32_t mmu_ctpr_mask;
> + uint32_t mmu_cxr_mask;
> + uint32_t mmu_sfsr_mask;
> + uint32_t mmu_trcr_mask;
> + uint32_t mxcc_version;
> + uint32_t features;
> + uint32_t nwindows;
> + uint32_t maxtl;
> +} SPARCCPUClass;
> +
> +/**
> + * SPARCCPU:
> + * @env: Legacy CPU state.
> + *
> + * A SPARC CPU.
> + */
> +typedef struct SPARCCPU {
> + /*< private >*/
> + CPUState parent_obj;
> + /*< public >*/
> +
> + CPUSPARCState env;
> +
> + target_ulong iu_version;
> + uint32_t fpu_version;
> + uint32_t mmu_version;
> + uint32_t features;
> + uint32_t nwindows;
> +} SPARCCPU;
The fields do not look correct at all, the same fields are in both
structs. Moreover Sparc32 and Sparc64 fields are mixed. Maybe I don't
fully understand the conversion.
Would it be possible to make a common parent class which is then
specialized by Sparc32 and Sparc64 classes? There are many common
fields but also many 32/64 specific ones. Also cpu_common.c, cpu32.c
and cpu64.c to avoid #ifdeffery?
> +
> +static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
> +{
> + return SPARC_CPU(container_of(env, SPARCCPU, env));
> +}
> +
> +#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e))
> +
> +static inline uint32_t sparc_env_get_features(CPUSPARCState *env)
> +{
> + return sparc_env_get_cpu(env)->features;
> +}
> +
> +
> +#endif
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> new file mode 100644
> index 0000000..4c960a9
> --- /dev/null
> +++ b/target-sparc/cpu.c
> @@ -0,0 +1,949 @@
> +/*
> + * Sparc CPU init helpers
> + *
> + * Copyright (c) 2003-2005 Fabrice Bellard
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "cpu-qom.h"
> +
> +//#define DEBUG_FEATURES
> +
> +void cpu_state_reset(CPUSPARCState *env)
> +{
> + cpu_reset(ENV_GET_CPU(env));
> +}
> +
> +static void sparc_cpu_reset(CPUState *c)
> +{
> + SPARCCPU *cpu = SPARC_CPU(c);
> + SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
> + CPUSPARCState *env = &cpu->env;
> +
> + if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> + log_cpu_state(env, 0);
> + }
> +
> + klass->parent_reset(c);
> +
> + tlb_flush(env, 1);
> + env->cwp = 0;
> +#ifndef TARGET_SPARC64
> + env->wim = 1;
> +#endif
> + env->regwptr = env->regbase + (env->cwp * 16);
> + CC_OP = CC_OP_FLAGS;
> +#if defined(CONFIG_USER_ONLY)
> +#ifdef TARGET_SPARC64
> + env->cleanwin = env->nwindows - 2;
> + env->cansave = env->nwindows - 2;
> + env->pstate = PS_RMO | PS_PEF | PS_IE;
> + env->asi = 0x82; /* Primary no-fault */
> +#endif
> +#else
> +#if !defined(TARGET_SPARC64)
> + env->psret = 0;
> + env->psrs = 1;
> + env->psrps = 1;
> +#endif
> +#ifdef TARGET_SPARC64
> + env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
> + env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
> + env->tl = env->maxtl;
> + cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
> + env->lsu = 0;
> +#else
> + env->mmuregs[0] &= ~(MMU_E | MMU_NF);
> + env->mmuregs[0] |= klass->mmu_bm;
> +#endif
> + env->pc = 0;
> + env->npc = env->pc + 4;
> +#endif
> + env->cache_control = 0;
> +}
> +
> +static void sparc_cpu_initfn(Object *obj)
> +{
> + SPARCCPU *cpu = SPARC_CPU(obj);
> + SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
> + CPUSPARCState *env = &cpu->env;
> +
> + memset(env, 0, sizeof(*env));
> + cpu_exec_init(env);
> +
> +#if defined(CONFIG_USER_ONLY)
> + if ((cpu->features & CPU_FEATURE_FLOAT)) {
> + cpu->features |= CPU_FEATURE_FLOAT128;
> + }
> +#endif
> + env->version = cpu->iu_version;
> + env->fsr = cpu->fpu_version;
> + env->nwindows = cpu->nwindows;
> +#if !defined(TARGET_SPARC64)
> + env->mmuregs[0] |= cpu->mmu_version;
> + cpu_sparc_set_id(env, 0);
> + env->mxccregs[7] |= klass->mxcc_version;
> +#else
> + env->mmu_version = cpu->mmu_version;
> + env->maxtl = klass->maxtl;
> + env->version |= klass->maxtl << 8;
> + env->version |= cpu->nwindows - 1;
> +#endif
> +}
> +
> +void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
> +{
> +#if !defined(TARGET_SPARC64)
> + env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
> +#endif
> +}
> +
> +/* CPU models */
> +
> +typedef struct SPARCCPUInfo {
> + const char *name;
> + target_ulong iu_version;
> + uint32_t fpu_version;
> + uint32_t mmu_version;
> + uint32_t mmu_bm;
> + uint32_t mmu_ctpr_mask;
> + uint32_t mmu_cxr_mask;
> + uint32_t mmu_sfsr_mask;
> + uint32_t mmu_trcr_mask;
> + uint32_t mxcc_version;
> + uint32_t features;
> + uint32_t nwindows;
> + uint32_t maxtl;
> +} SPARCCPUInfo;
> +
> +static void sparc_cpu_class_init(ObjectClass *klass, void *data)
> +{
> + CPUClass *cpu_class = CPU_CLASS(klass);
> + SPARCCPUClass *k = SPARC_CPU_CLASS(klass);
> + const SPARCCPUInfo *info = data;
> +
> + k->parent_reset = cpu_class->reset;
> + cpu_class->reset = sparc_cpu_reset;
> +
> + k->iu_version = info->iu_version;
> + k->fpu_version = info->fpu_version;
> + k->mmu_version = info->mmu_version;
> + k->mmu_bm = info->mmu_bm;
> + k->mmu_ctpr_mask = info->mmu_ctpr_mask;
> + k->mmu_cxr_mask = info->mmu_cxr_mask;
> + k->mmu_sfsr_mask = info->mmu_sfsr_mask;
> + k->mmu_trcr_mask = info->mmu_trcr_mask;
> + k->mxcc_version = info->mxcc_version;
> + k->features = info->features;
> + k->nwindows = info->nwindows;
> + k->maxtl = info->maxtl;
> +}
> +
> +static const SPARCCPUInfo sparc_cpus[] = {
> +#ifdef TARGET_SPARC64
> + {
> + .name = "Fujitsu Sparc64",
> + .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 4,
> + .maxtl = 4,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Fujitsu Sparc64 III",
> + .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 5,
> + .maxtl = 4,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Fujitsu Sparc64 IV",
> + .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Fujitsu Sparc64 V",
> + .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI UltraSparc I",
> + .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI UltraSparc II",
> + .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI UltraSparc IIi",
> + .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI UltraSparc IIe",
> + .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Sun UltraSparc III",
> + .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Sun UltraSparc III Cu",
> + .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_3,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Sun UltraSparc IIIi",
> + .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Sun UltraSparc IV",
> + .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_4,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Sun UltraSparc IV+",
> + .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
> + },
> + {
> + .name = "Sun UltraSparc IIIi+",
> + .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_3,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Sun UltraSparc T1",
> + /* defined in sparc_ifu_fdp.v and ctu.h */
> + .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_sun4v,
> + .nwindows = 8,
> + .maxtl = 6,
> + .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
> + | CPU_FEATURE_GL,
> + },
> + {
> + .name = "Sun UltraSparc T2",
> + /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
> + .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_sun4v,
> + .nwindows = 8,
> + .maxtl = 6,
> + .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
> + | CPU_FEATURE_GL,
> + },
> + {
> + .name = "NEC UltraSparc I",
> + .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
> + .fpu_version = 0x00000000,
> + .mmu_version = mmu_us_12,
> + .nwindows = 8,
> + .maxtl = 5,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> +#else
> + {
> + .name = "Fujitsu MB86900",
> + .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
> + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> + .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 7,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
> + },
> + {
> + .name = "Fujitsu MB86904",
> + .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
> + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> + .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x00ffffc0,
> + .mmu_cxr_mask = 0x000000ff,
> + .mmu_sfsr_mask = 0x00016fff,
> + .mmu_trcr_mask = 0x00ffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Fujitsu MB86907",
> + .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
> + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> + .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x000000ff,
> + .mmu_sfsr_mask = 0x00016fff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "LSI L64811",
> + .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
> + .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
> + .mmu_version = 0x10 << 24,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> + CPU_FEATURE_FSMULD,
> + },
> + {
> + .name = "Cypress CY7C601",
> + .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
> + .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
> + .mmu_version = 0x10 << 24,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> + CPU_FEATURE_FSMULD,
> + },
> + {
> + .name = "Cypress CY7C611",
> + .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
> + .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
> + .mmu_version = 0x10 << 24,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> + CPU_FEATURE_FSMULD,
> + },
> + {
> + .name = "TI MicroSparc I",
> + .iu_version = 0x41000000,
> + .fpu_version = 4 << 17,
> + .mmu_version = 0x41000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0x00016fff,
> + .mmu_trcr_mask = 0x0000003f,
> + .nwindows = 7,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
> + CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
> + CPU_FEATURE_FMUL,
> + },
> + {
> + .name = "TI MicroSparc II",
> + .iu_version = 0x42000000,
> + .fpu_version = 4 << 17,
> + .mmu_version = 0x02000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x00ffffc0,
> + .mmu_cxr_mask = 0x000000ff,
> + .mmu_sfsr_mask = 0x00016fff,
> + .mmu_trcr_mask = 0x00ffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI MicroSparc IIep",
> + .iu_version = 0x42000000,
> + .fpu_version = 4 << 17,
> + .mmu_version = 0x04000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x00ffffc0,
> + .mmu_cxr_mask = 0x000000ff,
> + .mmu_sfsr_mask = 0x00016bff,
> + .mmu_trcr_mask = 0x00ffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI SuperSparc 40", /* STP1020NPGA */
> + .iu_version = 0x41000000, /* SuperSPARC 2.x */
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
> + .mmu_bm = 0x00002000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x0000ffff,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI SuperSparc 50", /* STP1020PGA */
> + .iu_version = 0x40000000, /* SuperSPARC 3.x */
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
> + .mmu_bm = 0x00002000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x0000ffff,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI SuperSparc 51",
> + .iu_version = 0x40000000, /* SuperSPARC 3.x */
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
> + .mmu_bm = 0x00002000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x0000ffff,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .mxcc_version = 0x00000104,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI SuperSparc 60", /* STP1020APGA */
> + .iu_version = 0x40000000, /* SuperSPARC 3.x */
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
> + .mmu_bm = 0x00002000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x0000ffff,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI SuperSparc 61",
> + .iu_version = 0x44000000, /* SuperSPARC 3.x */
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
> + .mmu_bm = 0x00002000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x0000ffff,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .mxcc_version = 0x00000104,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "TI SuperSparc II",
> + .iu_version = 0x40000000, /* SuperSPARC II 1.x */
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
> + .mmu_bm = 0x00002000,
> + .mmu_ctpr_mask = 0xffffffc0,
> + .mmu_cxr_mask = 0x0000ffff,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .mxcc_version = 0x00000104,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Ross RT625",
> + .iu_version = 0x1e000000,
> + .fpu_version = 1 << 17,
> + .mmu_version = 0x1e000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "Ross RT620",
> + .iu_version = 0x1f000000,
> + .fpu_version = 1 << 17,
> + .mmu_version = 0x1f000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "BIT B5010",
> + .iu_version = 0x20000000,
> + .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
> + .mmu_version = 0x20000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> + CPU_FEATURE_FSMULD,
> + },
> + {
> + .name = "Matsushita MN10501",
> + .iu_version = 0x50000000,
> + .fpu_version = 0 << 17,
> + .mmu_version = 0x50000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
> + CPU_FEATURE_FSMULD,
> + },
> + {
> + .name = "Weitek W8601",
> + .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
> + .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
> + .mmu_version = 0x10 << 24,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES,
> + },
> + {
> + .name = "LEON2",
> + .iu_version = 0xf2000000,
> + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> + .mmu_version = 0xf2000000,
> + .mmu_bm = 0x00004000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
> + },
> + {
> + .name = "LEON3",
> + .iu_version = 0xf3000000,
> + .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> + .mmu_version = 0xf3000000,
> + .mmu_bm = 0x00000000,
> + .mmu_ctpr_mask = 0x007ffff0,
> + .mmu_cxr_mask = 0x0000003f,
> + .mmu_sfsr_mask = 0xffffffff,
> + .mmu_trcr_mask = 0xffffffff,
> + .nwindows = 8,
> + .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
> + CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
> + },
> +#endif
> +};
> +
> +static const char * const feature_name[] = {
> + "float",
> + "float128",
> + "swap",
> + "mul",
> + "div",
> + "flush",
> + "fsqrt",
> + "fmul",
> + "vis1",
> + "vis2",
> + "fsmuld",
> + "hypv",
> + "cmt",
> + "gl",
> +};
> +
> +static void print_features(FILE *f, fprintf_function cpu_fprintf,
> + uint32_t features, const char *prefix)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
> + if (feature_name[i] && (features & (1 << i))) {
> + if (prefix) {
> + (*cpu_fprintf)(f, "%s", prefix);
> + }
> + (*cpu_fprintf)(f, "%s ", feature_name[i]);
> + }
> + }
> +}
> +
> +static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
> + if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
> + *features |= 1 << i;
> + return;
> + }
> + }
> + fprintf(stderr, "CPU feature %s not found\n", flagname);
> +}
> +
> +static SPARCCPU *cpu_sparc_find_by_name(const char *cpu_model)
> +{
> + SPARCCPU *cpu;
> + char *s = strdup(cpu_model);
> + char *featurestr, *name = strtok(s, ",");
> + uint32_t plus_features = 0;
> + uint32_t minus_features = 0;
> + uint64_t iu_version;
> + uint32_t fpu_version, mmu_version, nwindows;
> +
> + if (object_class_by_name(name) == NULL) {
> + goto error;
> + }
> + cpu = SPARC_CPU(object_new(name));
> +
> + featurestr = strtok(NULL, ",");
> + while (featurestr) {
> + char *val;
> +
> + if (featurestr[0] == '+') {
> + add_flagname_to_bitmaps(featurestr + 1, &plus_features);
> + } else if (featurestr[0] == '-') {
> + add_flagname_to_bitmaps(featurestr + 1, &minus_features);
> + } else if ((val = strchr(featurestr, '='))) {
> + *val = 0; val++;
> + if (!strcmp(featurestr, "iu_version")) {
> + char *err;
> +
> + iu_version = strtoll(val, &err, 0);
> + if (!*val || *err) {
> + fprintf(stderr, "bad numerical value %s\n", val);
> + goto error;
> + }
> + cpu->iu_version = iu_version;
> +#ifdef DEBUG_FEATURES
> + fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
> +#endif
> + } else if (!strcmp(featurestr, "fpu_version")) {
> + char *err;
> +
> + fpu_version = strtol(val, &err, 0);
> + if (!*val || *err) {
> + fprintf(stderr, "bad numerical value %s\n", val);
> + goto error;
> + }
> + cpu->fpu_version = fpu_version;
> +#ifdef DEBUG_FEATURES
> + fprintf(stderr, "fpu_version %x\n", fpu_version);
> +#endif
> + } else if (!strcmp(featurestr, "mmu_version")) {
> + char *err;
> +
> + mmu_version = strtol(val, &err, 0);
> + if (!*val || *err) {
> + fprintf(stderr, "bad numerical value %s\n", val);
> + goto error;
> + }
> + cpu->mmu_version = mmu_version;
> +#ifdef DEBUG_FEATURES
> + fprintf(stderr, "mmu_version %x\n", mmu_version);
> +#endif
> + } else if (!strcmp(featurestr, "nwindows")) {
> + char *err;
> +
> + nwindows = strtol(val, &err, 0);
> + if (!*val || *err || nwindows > MAX_NWINDOWS ||
> + nwindows < MIN_NWINDOWS) {
> + fprintf(stderr, "bad numerical value %s\n", val);
> + goto error;
> + }
> + cpu->nwindows = nwindows;
> +#ifdef DEBUG_FEATURES
> + fprintf(stderr, "nwindows %d\n", nwindows);
> +#endif
> + } else {
> + fprintf(stderr, "unrecognized feature %s\n", featurestr);
> + goto error;
> + }
> + } else {
> + fprintf(stderr, "feature string `%s' not in format "
> + "(+feature|-feature|feature=xyz)\n", featurestr);
> + goto error;
> + }
> + featurestr = strtok(NULL, ",");
> + }
> + cpu->features |= plus_features;
> + cpu->features &= ~minus_features;
> +#ifdef DEBUG_FEATURES
> + print_features(stderr, fprintf, cpu->features, NULL);
> +#endif
> + free(s);
> + return cpu;
> +
> + error:
> + free(s);
> + return NULL;
> +}
> +
> +CPUSPARCState *cpu_sparc_init(const char *cpu_model)
> +{
> + SPARCCPU *cpu;
> + CPUSPARCState *env;
> +
> + cpu = cpu_sparc_find_by_name(cpu_model);
> + if (cpu == NULL) {
> + return NULL;
> + }
> + env = &cpu->env;
> + env->cpu_model_str = cpu_model;
> +
> + gen_intermediate_code_init(env);
> +
> + qemu_init_vcpu(env);
> +
> + return env;
> +}
> +
> +typedef struct SPARCCPUListState {
> + fprintf_function cpu_fprintf;
> + FILE *file;
> +} SPARCCPUListState;
> +
> +/* Sort alphabetically. */
> +static gint sparc_cpu_list_compare(gconstpointer a, gconstpointer b)
> +{
> + ObjectClass *class_a = (ObjectClass *)a;
> + ObjectClass *class_b = (ObjectClass *)b;
> +
> + return strcasecmp(object_class_get_name(class_a),
> + object_class_get_name(class_b));
> +}
> +
> +static void sparc_cpu_list_entry(gpointer data, gpointer user_data)
> +{
> + ObjectClass *klass = data;
> + SPARCCPUClass *k = SPARC_CPU_CLASS(klass);
> + SPARCCPUListState *s = user_data;
> +
> + (*s->cpu_fprintf)(s->file, "Sparc %16s IU " TARGET_FMT_lx
> + " FPU %08x MMU %08x NWINS %d ",
> + object_class_get_name(klass),
> + k->iu_version,
> + k->fpu_version,
> + k->mmu_version,
> + k->nwindows);
> + print_features(s->file, s->cpu_fprintf, CPU_DEFAULT_FEATURES &
> + ~k->features, "-");
> + print_features(s->file, s->cpu_fprintf, ~CPU_DEFAULT_FEATURES &
> + k->features, "+");
> + (*s->cpu_fprintf)(s->file, "\n");
> +}
> +
> +void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
> +{
> + SPARCCPUListState s = {
> + .file = f,
> + .cpu_fprintf = cpu_fprintf,
> + };
> + GSList *list;
> +
> + list = object_class_get_list(TYPE_SPARC_CPU, false);
> + list = g_slist_sort(list, sparc_cpu_list_compare);
> + g_slist_foreach(list, sparc_cpu_list_entry, &s);
> + g_slist_free(list);
> + (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
> + print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
> + (*cpu_fprintf)(f, "\n");
> + (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
> + print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
> + (*cpu_fprintf)(f, "\n");
> + (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
> + "fpu_version mmu_version nwindows\n");
> +}
> +
> +static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
> + uint32_t cc)
> +{
> + cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
> + cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
> + cc & PSR_CARRY ? 'C' : '-');
> +}
> +
> +#ifdef TARGET_SPARC64
> +#define REGS_PER_LINE 4
> +#else
> +#define REGS_PER_LINE 8
> +#endif
> +
> +void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
> + int flags)
> +{
> + int i, x;
> +
> + cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
> + env->npc);
> + cpu_fprintf(f, "General Registers:\n");
> +
> + for (i = 0; i < 8; i++) {
> + if (i % REGS_PER_LINE == 0) {
> + cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
> + }
> + cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
> + if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
> + cpu_fprintf(f, "\n");
> + }
> + }
> + cpu_fprintf(f, "\nCurrent Register Window:\n");
> + for (x = 0; x < 3; x++) {
> + for (i = 0; i < 8; i++) {
> + if (i % REGS_PER_LINE == 0) {
> + cpu_fprintf(f, "%%%c%d-%d: ",
> + x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
> + i, i + REGS_PER_LINE - 1);
> + }
> + cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
> + if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
> + cpu_fprintf(f, "\n");
> + }
> + }
> + }
> + cpu_fprintf(f, "\nFloating Point Registers:\n");
> + for (i = 0; i < TARGET_DPREGS; i++) {
> + if ((i & 3) == 0) {
> + cpu_fprintf(f, "%%f%02d:", i * 2);
> + }
> + cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
> + if ((i & 3) == 3) {
> + cpu_fprintf(f, "\n");
> + }
> + }
> +#ifdef TARGET_SPARC64
> + cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
> + (unsigned)cpu_get_ccr(env));
> + cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
> + cpu_fprintf(f, " xcc: ");
> + cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
> + cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
> + env->psrpil);
> + cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
> + "cleanwin: %d cwp: %d\n",
> + env->cansave, env->canrestore, env->otherwin, env->wstate,
> + env->cleanwin, env->nwindows - 1 - env->cwp);
> + cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
> + TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
> +#else
> + cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
> + cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
> + cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
> + env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
> + env->wim);
> + cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
> + env->fsr, env->y);
> +#endif
> +}
> +
> +static void cpu_type_register(const SPARCCPUInfo *info)
> +{
> + TypeInfo type = {
> + .name = info->name,
> + .parent = TYPE_SPARC_CPU,
> + .instance_size = sizeof(SPARCCPU),
> + .instance_init = sparc_cpu_initfn,
> + .class_size = sizeof(SPARCCPUClass),
> + .class_init = sparc_cpu_class_init,
> + .class_data = (void *)info,
> + };
> +
> + type_register_static(&type);
> +}
> +
> +static const TypeInfo sparc_cpu_info = {
> + .name = TYPE_SPARC_CPU,
> + .parent = TYPE_CPU,
> + .instance_size = sizeof(SPARCCPU),
> + .abstract = true,
> + .class_size = sizeof(SPARCCPUClass),
> +};
> +
> +static void sparc_cpu_register_types(void)
> +{
> + int i;
> +
> + type_register_static(&sparc_cpu_info);
> + for (i = 0; i < ARRAY_SIZE(sparc_cpus); i++) {
> + cpu_type_register(&sparc_cpus[i]);
> + }
> +}
> +
> +type_init(sparc_cpu_register_types)
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 86f9de6..10b05ac 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -237,22 +237,6 @@ typedef struct trap_state {
> } trap_state;
> #endif
>
> -typedef struct sparc_def_t {
> - const char *name;
> - target_ulong iu_version;
> - uint32_t fpu_version;
> - uint32_t mmu_version;
> - uint32_t mmu_bm;
> - uint32_t mmu_ctpr_mask;
> - uint32_t mmu_cxr_mask;
> - uint32_t mmu_sfsr_mask;
> - uint32_t mmu_trcr_mask;
> - uint32_t mxcc_version;
> - uint32_t features;
> - uint32_t nwindows;
> - uint32_t maxtl;
> -} sparc_def_t;
> -
> #define CPU_FEATURE_FLOAT (1 << 0)
> #define CPU_FEATURE_FLOAT128 (1 << 1)
> #define CPU_FEATURE_SWAP (1 << 2)
> @@ -498,7 +482,6 @@ struct CPUSPARCState {
> #define SOFTINT_INTRMASK (0xFFFE)
> #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
> #endif
> - sparc_def_t *def;
>
> void *irq_manager;
> void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
> @@ -507,6 +490,7 @@ struct CPUSPARCState {
> uint32_t cache_control;
> };
>
> +
> #ifndef NO_CPU_IO_DEFS
> /* cpu_init.c */
> CPUSPARCState *cpu_sparc_init(const char *cpu_model);
> @@ -616,10 +600,12 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
> #define MMU_MODE1_SUFFIX _kernel
> #endif
>
> +static inline uint32_t sparc_env_get_features(CPUSPARCState *env);
> +
> #if defined (TARGET_SPARC64)
> static inline int cpu_has_hypervisor(CPUSPARCState *env1)
> {
> - return env1->def->features & CPU_FEATURE_HYPV;
> + return sparc_env_get_features(env1) & CPU_FEATURE_HYPV;
> }
>
> static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
> @@ -688,6 +674,7 @@ static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp)
> #endif
>
> #include "cpu-all.h"
> +#include "cpu-qom.h"
>
> #ifdef TARGET_SPARC64
> /* sun4u.c */
> @@ -714,14 +701,14 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
> if (env->pstate & PS_AM) {
> *flags |= TB_FLAG_AM_ENABLED;
> }
> - if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
> - && (env->fprs & FPRS_FEF)) {
> + if ((sparc_env_get_features(env) & CPU_FEATURE_FLOAT)
> + && (env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
> *flags |= TB_FLAG_FPU_ENABLED;
> }
> #else
> // FPU enable . Supervisor
> *flags = env->psrs;
> - if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
> + if ((sparc_env_get_features(env) & CPU_FEATURE_FLOAT) && env->psref) {
> *flags |= TB_FLAG_FPU_ENABLED;
> }
> #endif
> diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
> deleted file mode 100644
> index 29132fb..0000000
> --- a/target-sparc/cpu_init.c
> +++ /dev/null
> @@ -1,848 +0,0 @@
> -/*
> - * Sparc CPU init helpers
> - *
> - * Copyright (c) 2003-2005 Fabrice Bellard
> - *
> - * This library is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU Lesser General Public
> - * License as published by the Free Software Foundation; either
> - * version 2 of the License, or (at your option) any later version.
> - *
> - * This library is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> - * Lesser General Public License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public
> - * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -#include "cpu.h"
> -
> -//#define DEBUG_FEATURES
> -
> -static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
> -
> -void cpu_state_reset(CPUSPARCState *env)
> -{
> - if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
> - log_cpu_state(env, 0);
> - }
> -
> - tlb_flush(env, 1);
> - env->cwp = 0;
> -#ifndef TARGET_SPARC64
> - env->wim = 1;
> -#endif
> - env->regwptr = env->regbase + (env->cwp * 16);
> - CC_OP = CC_OP_FLAGS;
> -#if defined(CONFIG_USER_ONLY)
> -#ifdef TARGET_SPARC64
> - env->cleanwin = env->nwindows - 2;
> - env->cansave = env->nwindows - 2;
> - env->pstate = PS_RMO | PS_PEF | PS_IE;
> - env->asi = 0x82; /* Primary no-fault */
> -#endif
> -#else
> -#if !defined(TARGET_SPARC64)
> - env->psret = 0;
> - env->psrs = 1;
> - env->psrps = 1;
> -#endif
> -#ifdef TARGET_SPARC64
> - env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
> - env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
> - env->tl = env->maxtl;
> - cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
> - env->lsu = 0;
> -#else
> - env->mmuregs[0] &= ~(MMU_E | MMU_NF);
> - env->mmuregs[0] |= env->def->mmu_bm;
> -#endif
> - env->pc = 0;
> - env->npc = env->pc + 4;
> -#endif
> - env->cache_control = 0;
> -}
> -
> -static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
> -{
> - sparc_def_t def1, *def = &def1;
> -
> - if (cpu_sparc_find_by_name(def, cpu_model) < 0) {
> - return -1;
> - }
> -
> - env->def = g_new0(sparc_def_t, 1);
> - memcpy(env->def, def, sizeof(*def));
> -#if defined(CONFIG_USER_ONLY)
> - if ((env->def->features & CPU_FEATURE_FLOAT)) {
> - env->def->features |= CPU_FEATURE_FLOAT128;
> - }
> -#endif
> - env->cpu_model_str = cpu_model;
> - env->version = def->iu_version;
> - env->fsr = def->fpu_version;
> - env->nwindows = def->nwindows;
> -#if !defined(TARGET_SPARC64)
> - env->mmuregs[0] |= def->mmu_version;
> - cpu_sparc_set_id(env, 0);
> - env->mxccregs[7] |= def->mxcc_version;
> -#else
> - env->mmu_version = def->mmu_version;
> - env->maxtl = def->maxtl;
> - env->version |= def->maxtl << 8;
> - env->version |= def->nwindows - 1;
> -#endif
> - return 0;
> -}
> -
> -static void cpu_sparc_close(CPUSPARCState *env)
> -{
> - g_free(env->def);
> - g_free(env);
> -}
> -
> -CPUSPARCState *cpu_sparc_init(const char *cpu_model)
> -{
> - CPUSPARCState *env;
> -
> - env = g_new0(CPUSPARCState, 1);
> - cpu_exec_init(env);
> -
> - gen_intermediate_code_init(env);
> -
> - if (cpu_sparc_register(env, cpu_model) < 0) {
> - cpu_sparc_close(env);
> - return NULL;
> - }
> - qemu_init_vcpu(env);
> -
> - return env;
> -}
> -
> -void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
> -{
> -#if !defined(TARGET_SPARC64)
> - env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
> -#endif
> -}
> -
> -static const sparc_def_t sparc_defs[] = {
> -#ifdef TARGET_SPARC64
> - {
> - .name = "Fujitsu Sparc64",
> - .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 4,
> - .maxtl = 4,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Fujitsu Sparc64 III",
> - .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 5,
> - .maxtl = 4,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Fujitsu Sparc64 IV",
> - .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Fujitsu Sparc64 V",
> - .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI UltraSparc I",
> - .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI UltraSparc II",
> - .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI UltraSparc IIi",
> - .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI UltraSparc IIe",
> - .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Sun UltraSparc III",
> - .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Sun UltraSparc III Cu",
> - .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_3,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Sun UltraSparc IIIi",
> - .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Sun UltraSparc IV",
> - .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_4,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Sun UltraSparc IV+",
> - .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
> - },
> - {
> - .name = "Sun UltraSparc IIIi+",
> - .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_3,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Sun UltraSparc T1",
> - /* defined in sparc_ifu_fdp.v and ctu.h */
> - .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_sun4v,
> - .nwindows = 8,
> - .maxtl = 6,
> - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
> - | CPU_FEATURE_GL,
> - },
> - {
> - .name = "Sun UltraSparc T2",
> - /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
> - .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_sun4v,
> - .nwindows = 8,
> - .maxtl = 6,
> - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
> - | CPU_FEATURE_GL,
> - },
> - {
> - .name = "NEC UltraSparc I",
> - .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
> - .fpu_version = 0x00000000,
> - .mmu_version = mmu_us_12,
> - .nwindows = 8,
> - .maxtl = 5,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> -#else
> - {
> - .name = "Fujitsu MB86900",
> - .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
> - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> - .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 7,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
> - },
> - {
> - .name = "Fujitsu MB86904",
> - .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
> - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> - .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x00ffffc0,
> - .mmu_cxr_mask = 0x000000ff,
> - .mmu_sfsr_mask = 0x00016fff,
> - .mmu_trcr_mask = 0x00ffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Fujitsu MB86907",
> - .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
> - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> - .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x000000ff,
> - .mmu_sfsr_mask = 0x00016fff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "LSI L64811",
> - .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
> - .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
> - .mmu_version = 0x10 << 24,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> - CPU_FEATURE_FSMULD,
> - },
> - {
> - .name = "Cypress CY7C601",
> - .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
> - .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
> - .mmu_version = 0x10 << 24,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> - CPU_FEATURE_FSMULD,
> - },
> - {
> - .name = "Cypress CY7C611",
> - .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
> - .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
> - .mmu_version = 0x10 << 24,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> - CPU_FEATURE_FSMULD,
> - },
> - {
> - .name = "TI MicroSparc I",
> - .iu_version = 0x41000000,
> - .fpu_version = 4 << 17,
> - .mmu_version = 0x41000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0x00016fff,
> - .mmu_trcr_mask = 0x0000003f,
> - .nwindows = 7,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
> - CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
> - CPU_FEATURE_FMUL,
> - },
> - {
> - .name = "TI MicroSparc II",
> - .iu_version = 0x42000000,
> - .fpu_version = 4 << 17,
> - .mmu_version = 0x02000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x00ffffc0,
> - .mmu_cxr_mask = 0x000000ff,
> - .mmu_sfsr_mask = 0x00016fff,
> - .mmu_trcr_mask = 0x00ffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI MicroSparc IIep",
> - .iu_version = 0x42000000,
> - .fpu_version = 4 << 17,
> - .mmu_version = 0x04000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x00ffffc0,
> - .mmu_cxr_mask = 0x000000ff,
> - .mmu_sfsr_mask = 0x00016bff,
> - .mmu_trcr_mask = 0x00ffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI SuperSparc 40", /* STP1020NPGA */
> - .iu_version = 0x41000000, /* SuperSPARC 2.x */
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
> - .mmu_bm = 0x00002000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x0000ffff,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI SuperSparc 50", /* STP1020PGA */
> - .iu_version = 0x40000000, /* SuperSPARC 3.x */
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
> - .mmu_bm = 0x00002000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x0000ffff,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI SuperSparc 51",
> - .iu_version = 0x40000000, /* SuperSPARC 3.x */
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
> - .mmu_bm = 0x00002000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x0000ffff,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .mxcc_version = 0x00000104,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI SuperSparc 60", /* STP1020APGA */
> - .iu_version = 0x40000000, /* SuperSPARC 3.x */
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
> - .mmu_bm = 0x00002000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x0000ffff,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI SuperSparc 61",
> - .iu_version = 0x44000000, /* SuperSPARC 3.x */
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
> - .mmu_bm = 0x00002000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x0000ffff,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .mxcc_version = 0x00000104,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "TI SuperSparc II",
> - .iu_version = 0x40000000, /* SuperSPARC II 1.x */
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
> - .mmu_bm = 0x00002000,
> - .mmu_ctpr_mask = 0xffffffc0,
> - .mmu_cxr_mask = 0x0000ffff,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .mxcc_version = 0x00000104,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Ross RT625",
> - .iu_version = 0x1e000000,
> - .fpu_version = 1 << 17,
> - .mmu_version = 0x1e000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "Ross RT620",
> - .iu_version = 0x1f000000,
> - .fpu_version = 1 << 17,
> - .mmu_version = 0x1f000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "BIT B5010",
> - .iu_version = 0x20000000,
> - .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
> - .mmu_version = 0x20000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
> - CPU_FEATURE_FSMULD,
> - },
> - {
> - .name = "Matsushita MN10501",
> - .iu_version = 0x50000000,
> - .fpu_version = 0 << 17,
> - .mmu_version = 0x50000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
> - CPU_FEATURE_FSMULD,
> - },
> - {
> - .name = "Weitek W8601",
> - .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
> - .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
> - .mmu_version = 0x10 << 24,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES,
> - },
> - {
> - .name = "LEON2",
> - .iu_version = 0xf2000000,
> - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> - .mmu_version = 0xf2000000,
> - .mmu_bm = 0x00004000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
> - },
> - {
> - .name = "LEON3",
> - .iu_version = 0xf3000000,
> - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
> - .mmu_version = 0xf3000000,
> - .mmu_bm = 0x00000000,
> - .mmu_ctpr_mask = 0x007ffff0,
> - .mmu_cxr_mask = 0x0000003f,
> - .mmu_sfsr_mask = 0xffffffff,
> - .mmu_trcr_mask = 0xffffffff,
> - .nwindows = 8,
> - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
> - CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
> - },
> -#endif
> -};
> -
> -static const char * const feature_name[] = {
> - "float",
> - "float128",
> - "swap",
> - "mul",
> - "div",
> - "flush",
> - "fsqrt",
> - "fmul",
> - "vis1",
> - "vis2",
> - "fsmuld",
> - "hypv",
> - "cmt",
> - "gl",
> -};
> -
> -static void print_features(FILE *f, fprintf_function cpu_fprintf,
> - uint32_t features, const char *prefix)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
> - if (feature_name[i] && (features & (1 << i))) {
> - if (prefix) {
> - (*cpu_fprintf)(f, "%s", prefix);
> - }
> - (*cpu_fprintf)(f, "%s ", feature_name[i]);
> - }
> - }
> -}
> -
> -static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
> - if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
> - *features |= 1 << i;
> - return;
> - }
> - }
> - fprintf(stderr, "CPU feature %s not found\n", flagname);
> -}
> -
> -static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
> -{
> - unsigned int i;
> - const sparc_def_t *def = NULL;
> - char *s = strdup(cpu_model);
> - char *featurestr, *name = strtok(s, ",");
> - uint32_t plus_features = 0;
> - uint32_t minus_features = 0;
> - uint64_t iu_version;
> - uint32_t fpu_version, mmu_version, nwindows;
> -
> - for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
> - if (strcasecmp(name, sparc_defs[i].name) == 0) {
> - def = &sparc_defs[i];
> - }
> - }
> - if (!def) {
> - goto error;
> - }
> - memcpy(cpu_def, def, sizeof(*def));
> -
> - featurestr = strtok(NULL, ",");
> - while (featurestr) {
> - char *val;
> -
> - if (featurestr[0] == '+') {
> - add_flagname_to_bitmaps(featurestr + 1, &plus_features);
> - } else if (featurestr[0] == '-') {
> - add_flagname_to_bitmaps(featurestr + 1, &minus_features);
> - } else if ((val = strchr(featurestr, '='))) {
> - *val = 0; val++;
> - if (!strcmp(featurestr, "iu_version")) {
> - char *err;
> -
> - iu_version = strtoll(val, &err, 0);
> - if (!*val || *err) {
> - fprintf(stderr, "bad numerical value %s\n", val);
> - goto error;
> - }
> - cpu_def->iu_version = iu_version;
> -#ifdef DEBUG_FEATURES
> - fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
> -#endif
> - } else if (!strcmp(featurestr, "fpu_version")) {
> - char *err;
> -
> - fpu_version = strtol(val, &err, 0);
> - if (!*val || *err) {
> - fprintf(stderr, "bad numerical value %s\n", val);
> - goto error;
> - }
> - cpu_def->fpu_version = fpu_version;
> -#ifdef DEBUG_FEATURES
> - fprintf(stderr, "fpu_version %x\n", fpu_version);
> -#endif
> - } else if (!strcmp(featurestr, "mmu_version")) {
> - char *err;
> -
> - mmu_version = strtol(val, &err, 0);
> - if (!*val || *err) {
> - fprintf(stderr, "bad numerical value %s\n", val);
> - goto error;
> - }
> - cpu_def->mmu_version = mmu_version;
> -#ifdef DEBUG_FEATURES
> - fprintf(stderr, "mmu_version %x\n", mmu_version);
> -#endif
> - } else if (!strcmp(featurestr, "nwindows")) {
> - char *err;
> -
> - nwindows = strtol(val, &err, 0);
> - if (!*val || *err || nwindows > MAX_NWINDOWS ||
> - nwindows < MIN_NWINDOWS) {
> - fprintf(stderr, "bad numerical value %s\n", val);
> - goto error;
> - }
> - cpu_def->nwindows = nwindows;
> -#ifdef DEBUG_FEATURES
> - fprintf(stderr, "nwindows %d\n", nwindows);
> -#endif
> - } else {
> - fprintf(stderr, "unrecognized feature %s\n", featurestr);
> - goto error;
> - }
> - } else {
> - fprintf(stderr, "feature string `%s' not in format "
> - "(+feature|-feature|feature=xyz)\n", featurestr);
> - goto error;
> - }
> - featurestr = strtok(NULL, ",");
> - }
> - cpu_def->features |= plus_features;
> - cpu_def->features &= ~minus_features;
> -#ifdef DEBUG_FEATURES
> - print_features(stderr, fprintf, cpu_def->features, NULL);
> -#endif
> - free(s);
> - return 0;
> -
> - error:
> - free(s);
> - return -1;
> -}
> -
> -void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
> - (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
> - " FPU %08x MMU %08x NWINS %d ",
> - sparc_defs[i].name,
> - sparc_defs[i].iu_version,
> - sparc_defs[i].fpu_version,
> - sparc_defs[i].mmu_version,
> - sparc_defs[i].nwindows);
> - print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
> - ~sparc_defs[i].features, "-");
> - print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
> - sparc_defs[i].features, "+");
> - (*cpu_fprintf)(f, "\n");
> - }
> - (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
> - print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
> - (*cpu_fprintf)(f, "\n");
> - (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
> - print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
> - (*cpu_fprintf)(f, "\n");
> - (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
> - "fpu_version mmu_version nwindows\n");
> -}
> -
> -static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
> - uint32_t cc)
> -{
> - cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
> - cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
> - cc & PSR_CARRY ? 'C' : '-');
> -}
> -
> -#ifdef TARGET_SPARC64
> -#define REGS_PER_LINE 4
> -#else
> -#define REGS_PER_LINE 8
> -#endif
> -
> -void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf,
> - int flags)
> -{
> - int i, x;
> -
> - cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
> - env->npc);
> - cpu_fprintf(f, "General Registers:\n");
> -
> - for (i = 0; i < 8; i++) {
> - if (i % REGS_PER_LINE == 0) {
> - cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
> - }
> - cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
> - if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
> - cpu_fprintf(f, "\n");
> - }
> - }
> - cpu_fprintf(f, "\nCurrent Register Window:\n");
> - for (x = 0; x < 3; x++) {
> - for (i = 0; i < 8; i++) {
> - if (i % REGS_PER_LINE == 0) {
> - cpu_fprintf(f, "%%%c%d-%d: ",
> - x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
> - i, i + REGS_PER_LINE - 1);
> - }
> - cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
> - if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
> - cpu_fprintf(f, "\n");
> - }
> - }
> - }
> - cpu_fprintf(f, "\nFloating Point Registers:\n");
> - for (i = 0; i < TARGET_DPREGS; i++) {
> - if ((i & 3) == 0) {
> - cpu_fprintf(f, "%%f%02d:", i * 2);
> - }
> - cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
> - if ((i & 3) == 3) {
> - cpu_fprintf(f, "\n");
> - }
> - }
> -#ifdef TARGET_SPARC64
> - cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
> - (unsigned)cpu_get_ccr(env));
> - cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
> - cpu_fprintf(f, " xcc: ");
> - cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
> - cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
> - env->psrpil);
> - cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
> - "cleanwin: %d cwp: %d\n",
> - env->cansave, env->canrestore, env->otherwin, env->wstate,
> - env->cleanwin, env->nwindows - 1 - env->cwp);
> - cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
> - TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
> -#else
> - cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
> - cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
> - cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
> - env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
> - env->wim);
> - cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
> - env->fsr, env->y);
> -#endif
> -}
> diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
> index 5e33d50..8d454ae 100644
> --- a/target-sparc/int32_helper.c
> +++ b/target-sparc/int32_helper.c
> @@ -60,6 +60,9 @@ static const char * const excp_names[0x80] = {
>
> void do_interrupt(CPUSPARCState *env)
> {
> +#if !defined(CONFIG_USER_ONLY)
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> +#endif
> int cwp, intno = env->exception_index;
>
> #ifdef DEBUG_PCALL
> @@ -102,7 +105,7 @@ void do_interrupt(CPUSPARCState *env)
> #if !defined(CONFIG_USER_ONLY)
> if (env->psret == 0) {
> if (env->exception_index == 0x80 &&
> - env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
> + cpu->features & CPU_FEATURE_TA0_SHUTDOWN) {
> qemu_system_shutdown_request();
> } else {
> cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 48d433c..806f45c 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -438,6 +438,7 @@ static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
>
> uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> uint64_t ret = 0;
> #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
> uint32_t last_addr = addr;
> @@ -450,7 +451,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
> case 0x00: /* Leon3 Cache Control */
> case 0x08: /* Leon3 Instruction Cache config */
> case 0x0C: /* Leon3 Date Cache config */
> - if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
> + if (cpu->features & CPU_FEATURE_CACHE_CTRL) {
> ret = leon3_cache_control_ld(addr, size);
> }
> break;
> @@ -696,6 +697,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
>
> void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> + SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
> helper_check_align(addr, size - 1);
> switch (asi) {
> case 2: /* SuperSparc MXCC registers and Leon3 cache control */
> @@ -703,7 +706,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
> case 0x00: /* Leon3 Cache Control */
> case 0x08: /* Leon3 Instruction Cache config */
> case 0x0C: /* Leon3 Date Cache config */
> - if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
> + if (cpu->features & CPU_FEATURE_CACHE_CTRL) {
> leon3_cache_control_st(addr, val, size);
> }
> break;
> @@ -853,16 +856,16 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
> (val & 0x00ffffff);
> /* Mappings generated during no-fault mode or MMU
> disabled mode are invalid in normal mode */
> - if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
> - (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
> + if ((oldreg & (MMU_E | MMU_NF | klass->mmu_bm)) !=
> + (env->mmuregs[reg] & (MMU_E | MMU_NF | klass->mmu_bm))) {
> tlb_flush(env, 1);
> }
> break;
> case 1: /* Context Table Pointer Register */
> - env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
> + env->mmuregs[reg] = val & klass->mmu_ctpr_mask;
> break;
> case 2: /* Context Register */
> - env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
> + env->mmuregs[reg] = val & klass->mmu_cxr_mask;
> if (oldreg != env->mmuregs[reg]) {
> /* we flush when the MMU context changes because
> QEMU has no MMU context support */
> @@ -873,11 +876,11 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
> case 4: /* Synchronous Fault Address Register */
> break;
> case 0x10: /* TLB Replacement Control Register */
> - env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
> + env->mmuregs[reg] = val & klass->mmu_trcr_mask;
> break;
> case 0x13: /* Synchronous Fault Status Register with Read
> and Clear */
> - env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
> + env->mmuregs[3] = val & klass->mmu_sfsr_mask;
> break;
> case 0x14: /* Synchronous Fault Address Register */
> env->mmuregs[4] = val;
> diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index 11fb9f5..83b050e 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -81,6 +81,8 @@ static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical
> target_ulong address, int rw, int mmu_idx,
> target_ulong *page_size)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> + SPARCCPUClass *klass = SPARC_CPU_GET_CLASS(cpu);
> int access_perms = 0;
> target_phys_addr_t pde_ptr;
> uint32_t pde;
> @@ -92,7 +94,7 @@ static int get_physical_address(CPUSPARCState *env, target_phys_addr_t *physical
> if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
> *page_size = TARGET_PAGE_SIZE;
> /* Boot mode: instruction fetches are taken from PROM */
> - if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
> + if (rw == 2 && (env->mmuregs[0] & klass->mmu_bm)) {
> *physical = env->prom_addr | (address & 0x7ffffULL);
> *prot = PAGE_READ | PAGE_EXEC;
> return 0;
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index ef176e9..a737279 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -81,7 +81,7 @@ typedef struct DisasContext {
> int singlestep;
> uint32_t cc_op; /* current CC operation */
> struct TranslationBlock *tb;
> - sparc_def_t *def;
> + SPARCCPU *def;
> TCGv_i32 t32[3];
> int n_t32;
> } DisasContext;
> @@ -5247,7 +5247,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
> dc->npc = (target_ulong) tb->cs_base;
> dc->cc_op = CC_OP_DYNAMIC;
> dc->mem_idx = cpu_mmu_index(env);
> - dc->def = env->def;
> + dc->def = sparc_env_get_cpu(env);
> dc->fpu_enabled = tb_fpu_enabled(tb->flags);
> dc->address_mask_32bit = tb_am_enabled(tb->flags);
> dc->singlestep = (env->singlestep_enabled || singlestep);
> diff --git a/target-sparc/win_helper.c b/target-sparc/win_helper.c
> index 3e82eb7..02376fc 100644
> --- a/target-sparc/win_helper.c
> +++ b/target-sparc/win_helper.c
> @@ -300,10 +300,11 @@ static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
>
> void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> uint32_t pstate_regs, new_pstate_regs;
> uint64_t *src, *dst;
>
> - if (env->def->features & CPU_FEATURE_GL) {
> + if (cpu->features & CPU_FEATURE_GL) {
> /* PS_AG is not implemented in this case */
> new_pstate &= ~PS_AG;
> }
> --
> 1.7.7
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-14 20:37 ` Igor Mitsyanko
2012-03-14 19:48 ` Anthony Liguori
@ 2012-03-14 20:37 ` Andreas Färber
2012-03-14 20:40 ` Anthony Liguori
1 sibling, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 20:37 UTC (permalink / raw)
To: i.mitsyanko
Cc: Igor Mitsyanko, qemu-devel, d.solodkiy, Anthony Liguori,
Paolo Bonzini, Igor Mammedov
Am 14.03.2012 21:37, schrieb Igor Mitsyanko:
> On 13.03.2012 3:13 PM, Andreas Färber wrote:
>
>> I never heard anyone wanting to generalize reset so far. I don't think
>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>>
>
> We can have a special object for this, let's call it ResetLine for
> example, with methods ResetLine::connect, ResetLine::assert or something
> like that. Different ResetLine objects could trigger reset of different
> sets of subdevices, just like real hardware can have several reset types
> (for example, STM32 has 3 different reset types).
Anthony provided a Reviewed-by, and given that this is a direct
conversion of cpu_reset() -> cpu_state_reset() -> CPUState::reset(), I
am preparing a PULL for this series tonight. That does not mean that the
code must stay like this forever. :)
cpu_reset() only handles the full reset of one CPU, as I understand, and
is called both at startup and at machine-level reset.
Anthony's Pin object, as qemu_irq successor, was planned post-4th QOM
series, I believe. -- "Small steps, Allie."
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-13 12:13 ` Andreas Färber
2012-03-13 12:20 ` Paolo Bonzini
@ 2012-03-14 20:37 ` Igor Mitsyanko
2012-03-14 19:48 ` Anthony Liguori
2012-03-14 20:37 ` Andreas Färber
1 sibling, 2 replies; 175+ messages in thread
From: Igor Mitsyanko @ 2012-03-14 20:37 UTC (permalink / raw)
To: Andreas Färber
Cc: Igor Mammedov, d.solodkiy, qemu-devel, Anthony Liguori, Paolo Bonzini
On 13.03.2012 3:13 PM, Andreas Färber wrote:
> In SysBusDeviceClass etc. we use the specific object type, too.
> Obviously my CPU is the first "new" QOM type, so we can go different
> ways if we want to. As long as it's a CPU-specific mechanism, using the
> specific type avoids some casts.
>
>> It will be easier to generalize later qdev code and not make special
>> case when
>> adding cpus.
>
> I never heard anyone wanting to generalize reset so far. I don't think
> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>
We can have a special object for this, let's call it ResetLine for
example, with methods ResetLine::connect, ResetLine::assert or something
like that. Different ResetLine objects could trigger reset of different
sets of subdevices, just like real hardware can have several reset types
(for example, STM32 has 3 different reset types).
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class
2012-03-14 20:37 ` Andreas Färber
@ 2012-03-14 20:40 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-14 20:40 UTC (permalink / raw)
To: Andreas Färber
Cc: i.mitsyanko, Igor Mitsyanko, qemu-devel, d.solodkiy,
Paolo Bonzini, Igor Mammedov
On 03/14/2012 03:37 PM, Andreas Färber wrote:
> Am 14.03.2012 21:37, schrieb Igor Mitsyanko:
>> On 13.03.2012 3:13 PM, Andreas Färber wrote:
>>
>>> I never heard anyone wanting to generalize reset so far. I don't think
>>> it belongs into Object at least. Maybe DeviceState. Anthony? Paolo?
>>>
>>
>> We can have a special object for this, let's call it ResetLine for
>> example, with methods ResetLine::connect, ResetLine::assert or something
>> like that. Different ResetLine objects could trigger reset of different
>> sets of subdevices, just like real hardware can have several reset types
>> (for example, STM32 has 3 different reset types).
>
> Anthony provided a Reviewed-by, and given that this is a direct
> conversion of cpu_reset() -> cpu_state_reset() -> CPUState::reset(), I
> am preparing a PULL for this series tonight. That does not mean that the
> code must stay like this forever. :)
>
> cpu_reset() only handles the full reset of one CPU, as I understand, and
> is called both at startup and at machine-level reset.
>
> Anthony's Pin object, as qemu_irq successor, was planned post-4th QOM
> series, I believe. -- "Small steps, Allie."
Ack.
Regards,
Anthony Liguori
>
> Andreas
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: Don't overuse CPUState
2012-03-13 18:10 ` Anthony Liguori
@ 2012-03-14 20:50 ` Andreas Färber
2012-03-14 20:58 ` Peter Maydell
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 20:50 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Peter Maydell, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 672 bytes --]
Am 13.03.2012 19:10, schrieb Anthony Liguori:
> On 03/09/2012 08:27 PM, Andreas Färber wrote:
>> Scripted conversion:
>> sed -i "s/CPUState/CPUAlphaState/g" target-alpha/*.[hc]
>> sed -i "s/#define CPUAlphaState/#define CPUState/" target-alpha/cpu.h
>
> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
>
> For 13-42.
Thanks, I applied yours by modifying my script. Attached.
Peter's Acked-by was added manually, so if re-running the script due to
conflicts it would need to be re-added.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[-- Attachment #2: git-cpustate.sh --]
[-- Type: application/x-shellscript, Size: 7941 bytes --]
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: Don't overuse CPUState
2012-03-14 20:50 ` Andreas Färber
@ 2012-03-14 20:58 ` Peter Maydell
0 siblings, 0 replies; 175+ messages in thread
From: Peter Maydell @ 2012-03-14 20:58 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Anthony Liguori
On 14 March 2012 20:50, Andreas Färber <afaerber@suse.de> wrote:
> Peter's Acked-by was added manually, so if re-running the script due to
> conflicts it would need to be re-added.
Or you could just drop it, I don't pay that much attention :-)
-- PMM
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
2012-03-14 7:53 ` Guan Xuetao
2012-03-14 20:03 ` Blue Swirl
@ 2012-03-14 21:09 ` Stefan Weil
2012-03-14 21:20 ` Anthony Liguori
2 siblings, 1 reply; 175+ messages in thread
From: Stefan Weil @ 2012-03-14 21:09 UTC (permalink / raw)
To: Andreas Färber
Cc: Blue Swirl, Dor Laor, Anthony Liguori, Guan Xuetao, qemu-devel
Am 14.03.2012 02:39, schrieb Andreas Färber:
> Adopt the license text suggested by Guan Xue-tao for all files except
> helper.c, to which Anthony Liguori (IBM) contributed a g_malloc() call.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
> Signed-off-by: Dor Laor <dlaor@redhat.com>
> ---
> target-unicore32/cpu.h | 5 ++---
> target-unicore32/helper.h | 5 ++---
> target-unicore32/op_helper.c | 5 ++---
> target-unicore32/translate.c | 5 ++---
> 4 files changed, 8 insertions(+), 12 deletions(-)
Ack. I don't really think that my contribution here is large
enough that my "Acked-by" or "Signed-off-by" is needed,
but if it helps...
As far as I know, at least in German law trivial changes don't
result in a copyright claim. A global search-and-replace operation
which replaces qemu_mallocz by g_malloc0 is trivial and no
obstacle for a license change, so helper.c could be changed as
well(that's my personal opinion).
Regards,
Stefan W.
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+
2012-03-14 21:09 ` Stefan Weil
@ 2012-03-14 21:20 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-14 21:20 UTC (permalink / raw)
To: Stefan Weil
Cc: Blue Swirl, Dor Laor, Guan Xuetao, Andreas Färber, qemu-devel
On 03/14/2012 04:09 PM, Stefan Weil wrote:
> Am 14.03.2012 02:39, schrieb Andreas Färber:
>> Adopt the license text suggested by Guan Xue-tao for all files except
>> helper.c, to which Anthony Liguori (IBM) contributed a g_malloc() call.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>> Signed-off-by: Stefan Weil <sw@weilnetz.de>
>> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
>> Signed-off-by: Dor Laor <dlaor@redhat.com>
>> ---
>> target-unicore32/cpu.h | 5 ++---
>> target-unicore32/helper.h | 5 ++---
>> target-unicore32/op_helper.c | 5 ++---
>> target-unicore32/translate.c | 5 ++---
>> 4 files changed, 8 insertions(+), 12 deletions(-)
>
> Ack. I don't really think that my contribution here is large
> enough that my "Acked-by" or "Signed-off-by" is needed,
> but if it helps...
>
> As far as I know, at least in German law trivial changes don't
> result in a copyright claim. A global search-and-replace operation
> which replaces qemu_mallocz by g_malloc0 is trivial and no
> obstacle for a license change, so helper.c could be changed as
> well(that's my personal opinion).
Nack.
I don't really want to get into the business of splitting hairs here. We have
no pressing reason to relicense to GPLv2+ so let's do it right and get the
appropriate SoBs.
Regards,
Anthony Liguori
>
> Regards,
> Stefan W.
>
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU
2012-03-13 13:18 ` Paolo Bonzini
@ 2012-03-14 22:30 ` Andreas Färber
2012-03-15 9:43 ` Paolo Bonzini
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-14 22:30 UTC (permalink / raw)
To: Paolo Bonzini, Peter Maydell
Cc: Paul Brook, qemu-devel, Anthony Liguori, Richard Henderson
Am 13.03.2012 14:18, schrieb Paolo Bonzini:
> Il 10/03/2012 17:53, Andreas Färber ha scritto:
>> /**
>> * ARMCPU:
>> + * @env: Legacy CPU state.
>> *
>> * An ARM CPU core.
>> */
>> @@ -58,7 +60,17 @@ typedef struct ARMCPU {
>> /*< private >*/
>> CPUState parent_obj;
>> /*< public >*/
>> +
>> + /* TODO Inline this and split off common state */
>> + CPUARMState env;
>> } ARMCPU;
>>
>
> As usual I don't like "legacy". :)
Well, it refers to "former CPUState of which some or many fields are
going to be extracted". I wouldn't want to write it into documentation
as such.
" * @env: CPUARMState" is not telling either.
Better wordings anyone?
> A more interesting distinction is
> between state that is relevant to the emulation, and state that is
> relevant to the main loop or the machine. The former is reinitialized
> after reset and can remain in CPUFooState. The latter is not
> reinitialized after reset, can move to QOM, and in most cases that's
> what we access when we use CPUArchState.
Actually I was planning on keeping CPU*State only for TCG fields.
Whether a field is reset or not should be determined by the reset
callback, not by a semi-magic memset() up to a certain field name.
That's especially problematic for cp15.
The CPU*State struct stays around for two reasons,
1) allowing an incremental conversion of targets,
2) allowing offset calculations for TCG from the middle of the struct.
Mentioning this, we need to review all my *CPU structs to make sure env
is the *first* member and that any fields accessed by offset in its
parent CPUState are placed *last*, to minimize the immediates, as
previously pointed out by rth. Starts to matter once we move icount into
CPUState, as done on qom-cpu-wip branch.
> Also, I understand that the conversion is not fully mechanical, but
> perhaps it can be made "more" mechanical than this? Splitting this
> patch in two would be nice, but I can't say I read it fully.
Hm, this patch has been around since v1 and so far nobody requested a
particular split... it would be possible to move init and reset code in
separate patches if deemed necessary? Peter?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU
2012-03-14 20:02 ` Blue Swirl
@ 2012-03-14 23:23 ` Anthony Liguori
0 siblings, 0 replies; 175+ messages in thread
From: Anthony Liguori @ 2012-03-14 23:23 UTC (permalink / raw)
To: Blue Swirl; +Cc: Guan Xue-tao, Andreas Färber, qemu-devel
On 03/14/2012 03:02 PM, Blue Swirl wrote:
> On Wed, Mar 14, 2012 at 01:39, Andreas Färber<afaerber@suse.de> wrote:
>> Hello,
>>
>> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
>> the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to
>> target-arm and faces a similar issue of CPU-dependent init code, so let's
>> tackle it next.
>>
>> Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS,
>> so that the target-unicore32 author gets notified of patches against his code.
>>
>> Patch 2, based on feedback from Guan Xuetao, changes the license of most
>> target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a
>> qemu_malloc() -> g_malloc() substitution that he can't relicense at this time,
>> so leave that as GPLv2 and declare my following patches explicitly as GPLv2+.
>
> Perhaps g_malloc() patch could be partially reverted and a new GPLv2+
> patch applied which uses g_new()?
This is a bad idea IMHO. We need clear rules about changing licenses. I
personally will not sign off on anything involving reverting code that cannot be
relicensed.
Copyright law is just too complex when it comes to derivative works. Just have
some patience and let's collect the necessary SoBs.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU
2012-03-14 10:56 ` Andreas Färber
@ 2012-03-15 1:04 ` Guan Xuetao
0 siblings, 0 replies; 175+ messages in thread
From: Guan Xuetao @ 2012-03-15 1:04 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On Wed, 2012-03-14 at 11:56 +0100, Andreas Färber wrote:
> Am 14.03.2012 08:56, schrieb Guan Xuetao:
> > On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
> >> Embed CPUUniCore32State into UniCore32CPU.
> >>
> >> Contributed under GPLv2+.
> >>
> >> Signed-off-by: Andreas Färber <afaerber@suse.de>
> >> ---
> >> Makefile.target | 1 +
> >> target-unicore32/cpu-qom.h | 72 ++++++++++++++++++++++++++++++++++
> >> target-unicore32/cpu.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
> > I hope the gpl information for cpu.c and cpu-qom.h could be consistent
> > with other files.
>
> Copy&paste from other cpu-qom.h files. :) I can change it to match the
> rest of target-unicore32.
>
> But speaking of matching licenses, your previous text has "as published
> by the Free Software Foundation", which I think is a bit safer in theory
> (no company X can publish a "GPL" v4 of their own and change it to their
> liking) and would make the change smaller. For example:
>
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> + * published by the Free Software Foundation, or (at your option) any
> + * later version. See the COPYING file in the top-level directory.
>
> What do you think?
>
> Andreas
>
GPLv2+ is ok.
Thanks and Regards
Guan Xuetao
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU
2012-03-14 22:30 ` Andreas Färber
@ 2012-03-15 9:43 ` Paolo Bonzini
0 siblings, 0 replies; 175+ messages in thread
From: Paolo Bonzini @ 2012-03-15 9:43 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Paul Brook, qemu-devel, Anthony Liguori,
Richard Henderson
Il 14/03/2012 23:30, Andreas Färber ha scritto:
>> As usual I don't like "legacy". :)
>
> Well, it refers to "former CPUState of which some or many fields are
> going to be extracted". I wouldn't want to write it into documentation
> as such.
> " * @env: CPUARMState" is not telling either.
> Better wordings anyone?
>
>> A more interesting distinction is
>> between state that is relevant to the emulation, and state that is
>> relevant to the main loop or the machine. The former is reinitialized
>> after reset and can remain in CPUFooState. The latter is not
>> reinitialized after reset, can move to QOM, and in most cases that's
>> what we access when we use CPUArchState.
>
> Actually I was planning on keeping CPU*State only for TCG fields.
@env: CPUARMState structure (only TCG fields should remain there)
> Whether a field is reset or not should be determined by the reset
> callback, not by a semi-magic memset() up to a certain field name.
> That's especially problematic for cp15.
True. My idea was to leave all resettable fields in CPUARMState, and
move the others in ARMCPU. This is consistent with "machine state" in
CPUARMState and "machine settings + main-loop state" in ARMCPU.
However, it may make little sense to you. If so, ignore me. :)
>> Also, I understand that the conversion is not fully mechanical, but
>> perhaps it can be made "more" mechanical than this? Splitting this
>> patch in two would be nice, but I can't say I read it fully.
>
> Hm, this patch has been around since v1 and so far nobody requested a
> particular split... it would be possible to move init and reset code in
> separate patches if deemed necessary? Peter?
No problem, now that you posted conversion of everything.
Paolo
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
@ 2012-03-15 18:56 ` Paul Brook
0 siblings, 0 replies; 175+ messages in thread
From: Paul Brook @ 2012-03-15 18:56 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel
> The internal CPU feature flags were only ever set in
> cpu_reset_model_id(). Therefore move their initialization into
> ARMCPUClass. We might want to tweak them in the future though (e.g.,
> -cpu cortex-r4,+fpu), so keep a copy in ARMCPU. This in turn means we
> need to infer features for both ARMCPUClass and ARMCPU, so move feature
> inference to arm_infer_features() and use macros to simplify it.
>
> Since cpu.h defines ARMCPUState, which has been incorporated into
> ARMCPU, and tries to use arm_feature() in cpu_get_tb_cpu_state(),
> move arm_feature() to cpu-core.h and add a forward declaration.
I don't like how this has ended up. You've got a confusing mix of
decalarative and imperative code to set CPU features.
i.e. some cores set features in ARMCPU.class_init, others use ARMCPU.features.
I'd much prefer doing everything in the former, and removing the latter.
Also, you must not assume that the feature bits will fit in a single word.
The features code is deliberately structured so that everything outside
arm_feature and get_feature use the ARM_FEATURE_* enumeration. This means
underlying bitmap implementation can be easily changed/extended. Your patch
breaks that, making it inconvenient to expand beyond 32 features, and very
hard to go beyond 64. Even just considering currently available ARM variants,
we're likely to hit these limits very soon.
Infering of additional features should probably be done in set_feature.
Paul
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
@ 2012-03-15 19:08 ` Paul Brook
2012-03-15 19:20 ` Peter Maydell
0 siblings, 1 reply; 175+ messages in thread
From: Paul Brook @ 2012-03-15 19:08 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel
> For now set them in the reset function.
> + /* TODO Move these into arm_cpu_initfn() once no longer zeroed above.*/
> + memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
> + memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t)); +
Why bother copying them into the CPU state? These are readonly, so anything
that needs them should be able to use the value straight from the class
definitions.
Paul
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
2012-03-15 19:08 ` Paul Brook
@ 2012-03-15 19:20 ` Peter Maydell
2012-03-15 19:29 ` Alexey Starikovskiy
0 siblings, 1 reply; 175+ messages in thread
From: Peter Maydell @ 2012-03-15 19:20 UTC (permalink / raw)
To: Paul Brook; +Cc: Andreas Färber, qemu-devel
On 15 March 2012 19:08, Paul Brook <paul@codesourcery.com> wrote:
>> For now set them in the reset function.
>
>> + /* TODO Move these into arm_cpu_initfn() once no longer zeroed above.*/
>> + memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
>> + memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t)); +
>
> Why bother copying them into the CPU state? These are readonly, so anything
> that needs them should be able to use the value straight from the class
> definitions.
In my (hugely delayed) cp15 rework attempt these probably go away anyway
in favour of having each CPU register a pile of registers along the lines of
{ .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00001231 },
{ .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00000011 },
etc.
I'm not sure there's any need to retain the CPUState (or equivalent) fields
for them at that point.
-- PMM
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
2012-03-15 19:20 ` Peter Maydell
@ 2012-03-15 19:29 ` Alexey Starikovskiy
2012-03-15 19:42 ` Peter Maydell
0 siblings, 1 reply; 175+ messages in thread
From: Alexey Starikovskiy @ 2012-03-15 19:29 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Paul Brook, Andreas Färber
On Thu, Mar 15, 2012 at 11:20 PM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> On 15 March 2012 19:08, Paul Brook <paul@codesourcery.com> wrote:
>>> For now set them in the reset function.
>>
>>> + /* TODO Move these into arm_cpu_initfn() once no longer zeroed above.*/
>>> + memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
>>> + memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t)); +
>>
>> Why bother copying them into the CPU state? These are readonly, so anything
>> that needs them should be able to use the value straight from the class
>> definitions.
>
> In my (hugely delayed) cp15 rework attempt these probably go away anyway
> in favour of having each CPU register a pile of registers along the lines of
>
> { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00001231 },
> { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00000011 },
> etc.
>
> I'm not sure there's any need to retain the CPUState (or equivalent) fields
> for them at that point.
>
> -- PMM
>
Peter, with the reserved bits in most registers it might make sense to
have resetvalue in two
masks -- ones and zeros, so that you can prevent changing of those bits.
Alex.
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 05/12] target-i386: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 05/12] target-i386: " Andreas Färber
@ 2012-03-15 19:30 ` Eduardo Habkost
0 siblings, 0 replies; 175+ messages in thread
From: Eduardo Habkost @ 2012-03-15 19:30 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On Wed, Mar 14, 2012 at 06:53:29PM +0100, Andreas Färber wrote:
[...]
> +/**
> + * X86CPUClass:
> + * @parent_reset: The parent class' reset handler.
> + *
> + * An x86 CPU model or family.
> + */
> +typedef struct X86CPUClass {
> + /*< private >*/
> + CPUClass parent_class;
> + /*< public >*/
> +
> + void (*parent_reset)(CPUState *cpu);
> +
> + uint32_t level;
> + uint32_t vendor1, vendor2, vendor3;
> + int family;
> + int model;
> + int stepping;
> + int tsc_khz;
> + uint32_t features, ext_features, ext2_features, ext3_features;
> + uint32_t kvm_features, svm_features;
> + uint32_t xlevel;
> + char model_id[48];
> + int vendor_override;
> + uint32_t flags;
> + /* Store the results of Centaur's CPUID instructions */
> + uint32_t ext4_features;
> + uint32_t xlevel2;
> +} X86CPUClass;
[...]
> +typedef struct X86CPUInfo {
> + const char *name;
> + uint32_t level;
> + uint32_t vendor1, vendor2, vendor3;
> + int family;
> + int model;
> + int stepping;
> + int tsc_khz;
> + uint32_t features, ext_features, ext2_features, ext3_features;
> + uint32_t kvm_features, svm_features;
> + uint32_t xlevel;
> + char model_id[48];
> + int vendor_override;
> + uint32_t flags;
> + /* Store the results of Centaur's CPUID instructions */
> + uint32_t ext4_features;
> + uint32_t xlevel2;
> +} X86CPUInfo;
Have you considered eliminating this duplication and using a common
struct for both cases? (either by using X86CPUClass for everything, or
by embedding a common struct inside X86CPUClass)
This would simplify (or even make unnecessary) the field-by-field copy
on x86_cpu_class_init().
[...]
> +static void x86_cpu_class_init(ObjectClass *klass, void *data)
> +{
> + X86CPUClass *k = X86_CPU_CLASS(klass);
> + const X86CPUInfo *info = data;
> +
> + k->level = info->level;
> + k->vendor1 = info->vendor1;
> + k->vendor2 = info->vendor2;
> + k->vendor3 = info->vendor3;
> + k->family = info->family;
> + k->model = info->model;
> + k->stepping = info->stepping;
> + k->tsc_khz = info->tsc_khz;
> + k->features = info->features;
> + k->ext_features = info->ext_features;
> + k->ext2_features = info->ext2_features;
> + k->ext3_features = info->ext3_features;
> + k->kvm_features = info->kvm_features;
> + k->svm_features = info->svm_features;
> + k->xlevel = info->xlevel;
> + memcpy(k->model_id, info->model_id, 48);
> + k->vendor_override = info->vendor_override;
> + k->flags = info->flags;
> + k->ext4_features = info->ext4_features;
> + k->xlevel2 = info->xlevel2;
> +}
--
Eduardo
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass
2012-03-15 19:29 ` Alexey Starikovskiy
@ 2012-03-15 19:42 ` Peter Maydell
0 siblings, 0 replies; 175+ messages in thread
From: Peter Maydell @ 2012-03-15 19:42 UTC (permalink / raw)
To: Alexey Starikovskiy; +Cc: qemu-devel, Paul Brook, Andreas Färber
On 15 March 2012 19:29, Alexey Starikovskiy <aystarik@gmail.com> wrote:
> On Thu, Mar 15, 2012 at 11:20 PM, Peter Maydell
> <peter.maydell@linaro.org> wrote:
>> On 15 March 2012 19:08, Paul Brook <paul@codesourcery.com> wrote:
>>>> For now set them in the reset function.
>>>
>>>> + /* TODO Move these into arm_cpu_initfn() once no longer zeroed above.*/
>>>> + memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t));
>>>> + memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t)); +
>>>
>>> Why bother copying them into the CPU state? These are readonly, so anything
>>> that needs them should be able to use the value straight from the class
>>> definitions.
>>
>> In my (hugely delayed) cp15 rework attempt these probably go away anyway
>> in favour of having each CPU register a pile of registers along the lines of
>>
>> { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
>> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00001231 },
>> { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 1,
>> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0x00000011 },
>> etc.
>>
>> I'm not sure there's any need to retain the CPUState (or equivalent) fields
>> for them at that point.
>>
>> -- PMM
>>
> Peter, with the reserved bits in most registers it might make sense to
> have resetvalue in two
> masks -- ones and zeros, so that you can prevent changing of those bits.
Well, in this case it's totally read only. Mostly QEMU at the moment doesn't
enforce selectively read-only bits (we probably should!) so I haven't
put in read-only-masks in my conversion so far, but it's an obvious
possibility.
(Current status:
http://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/cp15-rework
still TODO:
cp15 crn=0 conversion ;
drop special case of mcrr in favour of explicitly implementing
block cache ops registers ;
reset handling of SCTLR still relies on cpu_reset_model_id ;
arrangement of define_arm_cp_regs() calls could probably be improved.
I'm also toying with the idea of just having each CPU we support go
through and register its own cp15 registers in a big long list (ie
no attempt at factoring out "these are registers all v7 cores have",
"these are registers for feature X", etc). That sounds kind of weird
but it might help in separating out changes to migration state for
CPU A from those for CPU B.)
-- PMM
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 12/12] target-xtensa: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
@ 2012-03-15 22:10 ` jcmvbkbc
2012-03-15 23:10 ` Max Filippov
0 siblings, 1 reply; 175+ messages in thread
From: jcmvbkbc @ 2012-03-15 22:10 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
> Let xtensa_cpu_list() enumerate CPU classes alphabetically.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> ---
[...]
> diff --git a/gdbstub.c b/gdbstub.c
> index f4e97f7..773e86f 100644
> --- a/gdbstub.c
> +++ b/gdbstub.c
> @@ -1570,14 +1570,17 @@ static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
> * reset bit 0 in the 'flags' field of the registers definitions in the
> * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
> */
> -#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
> +#define NUM_CORE_REGS \
> + (XTENSA_CPU_GET_CLASS(xtensa_env_get_cpu(env))->gdb_regmap.num_regs)
> #define num_g_regs NUM_CORE_REGS
>
> static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
> {
> - const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
> + XtensaCPU *cpu = xtensa_env_get_cpu(env);
> + XtensaCPUClass *klass = XTENSA_CPU_GET_CLASS(cpu);
*klass*
It's a bit strange to see patches that fix typos in comments and at the same time
to deliberately introduce this kind of misspelling. I'd suggest to call it what it is: cpu_class.
[...]
> diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
> index a3a5650..b46bca9 100644
> --- a/target-xtensa/overlay_tool.h
> +++ b/target-xtensa/overlay_tool.h
> @@ -291,16 +291,28 @@
> #endif
>
> #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
> -#define REGISTER_CORE(core) \
> - static void __attribute__((constructor)) register_core(void) \
> +#define REGISTER_CORE(typename, class) \
> + static void core_class_init(ObjectClass *klass, void *data) \
> { \
> - static XtensaConfigList node = { \
> - .config =&core, \
> - }; \
> - xtensa_register_core(&node); \
> - }
> + /* XXX This is a really ugly but easy way to init the class... */ \
> + memcpy((void *)klass + offsetof(XtensaCPUClass, options), \
> + (void *)&(class) + offsetof(XtensaCPUClass, options), \
> + sizeof(XtensaCPUClass) - offsetof(XtensaCPUClass, options)); \
> + } \
- void pointer arithmetic is non-standard;
- (void *)&(class) + offsetof(XtensaCPUClass, options) looks suspicious, I don't think
anything other than XtensaCPUClass instances should be passed here;
I'd suggest the following replacement:
memcpy(&((XtensaCPUClass *)klass)->options, \
&(class).options, \
sizeof(XtensaCPUClass) - offsetof(XtensaCPUClass, options)); \
[...]
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU
2012-03-14 17:53 ` [Qemu-devel] [RFC 09/12] target-lm32: " Andreas Färber
@ 2012-03-15 22:42 ` Michael Walle
0 siblings, 0 replies; 175+ messages in thread
From: Michael Walle @ 2012-03-15 22:42 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
Am Mittwoch 14 März 2012, 18:53:33 schrieb Andreas Färber:
> Let cpu_lm32_list() enumerate CPU classes sorted alphabetically.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> Makefile.target | 1 +
> target-lm32/cpu-qom.h | 77 ++++++++++++++++++++
> target-lm32/cpu.c | 188
> +++++++++++++++++++++++++++++++++++++++++++++++++ target-lm32/cpu.h |
> 1 +
> target-lm32/helper.c | 142 ++++++++-----------------------------
> 5 files changed, 297 insertions(+), 112 deletions(-)
> create mode 100644 target-lm32/cpu-qom.h
> create mode 100644 target-lm32/cpu.c
>
> diff --git a/Makefile.target b/Makefile.target
> index 3b7a4da..8c8f4a8 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -90,6 +90,7 @@ libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
> libobj-$(TARGET_ALPHA) += cpu.o
> libobj-$(TARGET_ARM) += cpu.o
> libobj-$(TARGET_CRIS) += cpu.o
> +libobj-$(TARGET_LM32) += cpu.o
> libobj-$(TARGET_M68K) += cpu.o
> ifeq ($(TARGET_BASE_ARCH), mips)
> libobj-y += cpu.o
> diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
> new file mode 100644
> index 0000000..dc3d434
> --- /dev/null
> +++ b/target-lm32/cpu-qom.h
> @@ -0,0 +1,77 @@
> +/*
> + * QEMU LatticeMico32 CPU
> + *
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +#ifndef QEMU_LM32_CPU_QOM_H
> +#define QEMU_LM32_CPU_QOM_H
> +
> +#include "qemu/cpu.h"
> +#include "cpu.h"
> +
> +#define TYPE_LM32_CPU "lm32-cpu"
> +
> +#define LM32_CPU_CLASS(klass) \
> + OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
> +#define LM32_CPU(obj) \
> + OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU)
> +#define LM32_CPU_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU)
> +
> +/**
> + * LM32CPUClass:
> + * @parent_reset: The parent class' reset handler.
> + *
> + * A LatticeMico32 CPU model.
> + */
> +typedef struct LM32CPUClass {
> + /*< private >*/
> + CPUClass parent_class;
> + /*< public >*/
> +
> + void (*parent_reset)(CPUState *cpu);
> +
> + uint32_t revision;
> + uint8_t num_interrupts;
> + uint8_t num_breakpoints;
> + uint8_t num_watchpoints;
> + uint32_t features;
> +} LM32CPUClass;
> +
> +/**
> + * LM32CPU:
> + * @env: Legacy CPU state.
> + *
> + * A LatticeMico32 CPU.
> + */
> +typedef struct LM32CPU {
> + /*< private >*/
> + CPUState parent_obj;
> + /*< public >*/
> +
> + CPULM32State env;
> +} LM32CPU;
> +
> +static inline LM32CPU *cris_env_get_cpu(CPULM32State *env)
cris? :)
> +{
> + return LM32_CPU(container_of(env, LM32CPU, env));
> +}
> +
> +#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
ditto
Apart from that:
Acked-by: Michael Walle <michael@walle.cc>
> +
> +
> +#endif
> diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
> new file mode 100644
> index 0000000..7f5308a
> --- /dev/null
> +++ b/target-lm32/cpu.c
> @@ -0,0 +1,188 @@
> +/*
> + * QEMU LatticeMico32 CPU
> + *
> + * Copyright (c) 2010 Michael Walle <michael@walle.cc>
> + * Copyright (c) 2012 SUSE LINUX Products GmbH
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#include "cpu-qom.h"
> +#include "qemu-common.h"
> +
> +static void lm32_cpu_reset(CPUState *c)
> +{
> +}
> +
> +/* CPU models */
> +
> +typedef struct LM32CPUInfo {
> + const char *name;
> + uint32_t revision;
> + uint8_t num_interrupts;
> + uint8_t num_breakpoints;
> + uint8_t num_watchpoints;
> + uint32_t features;
> +} LM32CPUInfo;
> +
> +static const LM32CPUInfo lm32_cpus[] = {
> + {
> + .name = "lm32-basic",
> + .revision = 3,
> + .num_interrupts = 32,
> + .num_breakpoints = 4,
> + .num_watchpoints = 4,
> + .features = (LM32_FEATURE_SHIFT
> + | LM32_FEATURE_SIGN_EXTEND
> + | LM32_FEATURE_CYCLE_COUNT),
> + },
> + {
> + .name = "lm32-standard",
> + .revision = 3,
> + .num_interrupts = 32,
> + .num_breakpoints = 4,
> + .num_watchpoints = 4,
> + .features = (LM32_FEATURE_MULTIPLY
> + | LM32_FEATURE_DIVIDE
> + | LM32_FEATURE_SHIFT
> + | LM32_FEATURE_SIGN_EXTEND
> + | LM32_FEATURE_I_CACHE
> + | LM32_FEATURE_CYCLE_COUNT),
> + },
> + {
> + .name = "lm32-full",
> + .revision = 3,
> + .num_interrupts = 32,
> + .num_breakpoints = 4,
> + .num_watchpoints = 4,
> + .features = (LM32_FEATURE_MULTIPLY
> + | LM32_FEATURE_DIVIDE
> + | LM32_FEATURE_SHIFT
> + | LM32_FEATURE_SIGN_EXTEND
> + | LM32_FEATURE_I_CACHE
> + | LM32_FEATURE_D_CACHE
> + | LM32_FEATURE_CYCLE_COUNT),
> + }
> +};
> +
> +static uint32_t cfg_by_class(LM32CPUClass *def)
> +{
> + uint32_t cfg = 0;
> +
> + if (def->features & LM32_FEATURE_MULTIPLY) {
> + cfg |= CFG_M;
> + }
> +
> + if (def->features & LM32_FEATURE_DIVIDE) {
> + cfg |= CFG_D;
> + }
> +
> + if (def->features & LM32_FEATURE_SHIFT) {
> + cfg |= CFG_S;
> + }
> +
> + if (def->features & LM32_FEATURE_SIGN_EXTEND) {
> + cfg |= CFG_X;
> + }
> +
> + if (def->features & LM32_FEATURE_I_CACHE) {
> + cfg |= CFG_IC;
> + }
> +
> + if (def->features & LM32_FEATURE_D_CACHE) {
> + cfg |= CFG_DC;
> + }
> +
> + if (def->features & LM32_FEATURE_CYCLE_COUNT) {
> + cfg |= CFG_CC;
> + }
> +
> + cfg |= (def->num_interrupts << CFG_INT_SHIFT);
> + cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
> + cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
> + cfg |= (def->revision << CFG_REV_SHIFT);
> +
> + return cfg;
> +}
> +
> +static void lm32_cpu_initfn(Object *obj)
> +{
> + LM32CPU *cpu = LM32_CPU(obj);
> + LM32CPUClass *klass = LM32_CPU_GET_CLASS(cpu);
> + CPULM32State *env = &cpu->env;
> +
> + memset(env, 0, sizeof(*env));
> + cpu_exec_init(env);
> + env->cpu_model_str = object_get_typename(obj);
> +
> + env->features = klass->features;
> + env->num_bps = klass->num_breakpoints;
> + env->num_wps = klass->num_watchpoints;
> + env->cfg = cfg_by_class(klass);
> + env->flags = 0;
> +
> + cpu_reset(CPU(cpu));
> +}
> +
> +static void lm32_cpu_class_init(ObjectClass *klass, void *data)
> +{
> + CPUClass *cpu_class = CPU_CLASS(klass);
> + LM32CPUClass *k = LM32_CPU_CLASS(klass);
> + const LM32CPUInfo *info = data;
> +
> + k->parent_reset = cpu_class->reset;
> + cpu_class->reset = lm32_cpu_reset;
> +
> + k->revision = info->revision;
> + k->num_interrupts = info->num_interrupts;
> + k->num_breakpoints = info->num_breakpoints;
> + k->num_watchpoints = info->num_watchpoints;
> + k->features = info->features;
> +}
> +
> +static void cpu_register(const LM32CPUInfo *info)
> +{
> + TypeInfo type = {
> + .name = info->name,
> + .parent = TYPE_LM32_CPU,
> + .instance_size = sizeof(LM32CPU),
> + .instance_init = lm32_cpu_initfn,
> + .class_size = sizeof(LM32CPUClass),
> + .class_init = lm32_cpu_class_init,
> + .class_data = (void *)info,
> + };
> +
> + type_register_static(&type);
> +}
> +
> +static const TypeInfo lm32_cpu_type_info = {
> + .name = TYPE_LM32_CPU,
> + .parent = TYPE_CPU,
> + .instance_size = sizeof(LM32CPU),
> + .abstract = true,
> + .class_size = sizeof(LM32CPUClass),
> +};
> +
> +static void lm32_cpu_register_types(void)
> +{
> + int i;
> +
> + type_register_static(&lm32_cpu_type_info);
> + for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
> + cpu_register(&lm32_cpus[i]);
> + }
> +}
> +
> +type_init(lm32_cpu_register_types)
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index 0902a24..c1be305 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -184,6 +184,7 @@ typedef struct CPULM32State {
>
> } CPULM32State;
>
> +#include "cpu-qom.h"
>
> CPULM32State *cpu_lm32_init(const char *cpu_model);
> void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index 5db8f8d..e89cc0e 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -80,139 +80,57 @@ void do_interrupt(CPULM32State *env)
> }
> }
>
> -typedef struct {
> - const char *name;
> - uint32_t revision;
> - uint8_t num_interrupts;
> - uint8_t num_breakpoints;
> - uint8_t num_watchpoints;
> - uint32_t features;
> -} LM32Def;
> +typedef struct LM32CPUListState {
> + fprintf_function cpu_fprintf;
> + FILE *file;
> +} LM32CPUListState;
>
> -static const LM32Def lm32_defs[] = {
> - {
> - .name = "lm32-basic",
> - .revision = 3,
> - .num_interrupts = 32,
> - .num_breakpoints = 4,
> - .num_watchpoints = 4,
> - .features = (LM32_FEATURE_SHIFT
> - | LM32_FEATURE_SIGN_EXTEND
> - | LM32_FEATURE_CYCLE_COUNT),
> - },
> - {
> - .name = "lm32-standard",
> - .revision = 3,
> - .num_interrupts = 32,
> - .num_breakpoints = 4,
> - .num_watchpoints = 4,
> - .features = (LM32_FEATURE_MULTIPLY
> - | LM32_FEATURE_DIVIDE
> - | LM32_FEATURE_SHIFT
> - | LM32_FEATURE_SIGN_EXTEND
> - | LM32_FEATURE_I_CACHE
> - | LM32_FEATURE_CYCLE_COUNT),
> - },
> - {
> - .name = "lm32-full",
> - .revision = 3,
> - .num_interrupts = 32,
> - .num_breakpoints = 4,
> - .num_watchpoints = 4,
> - .features = (LM32_FEATURE_MULTIPLY
> - | LM32_FEATURE_DIVIDE
> - | LM32_FEATURE_SHIFT
> - | LM32_FEATURE_SIGN_EXTEND
> - | LM32_FEATURE_I_CACHE
> - | LM32_FEATURE_D_CACHE
> - | LM32_FEATURE_CYCLE_COUNT),
> - }
> -};
> -
> -void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
> +/* Sort alphabetically. */
> +static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
> {
> - int i;
> + ObjectClass *class_a = OBJECT_CLASS(a);
> + ObjectClass *class_b = OBJECT_CLASS(b);
>
> - cpu_fprintf(f, "Available CPUs:\n");
> - for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
> - cpu_fprintf(f, " %s\n", lm32_defs[i].name);
> - }
> + return strcasecmp(object_class_get_name(class_a),
> + object_class_get_name(class_b));
> }
>
> -static const LM32Def *cpu_lm32_find_by_name(const char *name)
> +static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
> {
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
> - if (strcasecmp(name, lm32_defs[i].name) == 0) {
> - return &lm32_defs[i];
> - }
> - }
> + ObjectClass *klass = data;
> + LM32CPUListState *s = user_data;
>
> - return NULL;
> + (*s->cpu_fprintf)(s->file, " %s\n",
> + object_class_get_name(klass));
> }
>
> -static uint32_t cfg_by_def(const LM32Def *def)
> +void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
> {
> - uint32_t cfg = 0;
> -
> - if (def->features & LM32_FEATURE_MULTIPLY) {
> - cfg |= CFG_M;
> - }
> + LM32CPUListState s = {
> + .file = f,
> + .cpu_fprintf = cpu_fprintf,
> + };
> + GSList *list;
>
> - if (def->features & LM32_FEATURE_DIVIDE) {
> - cfg |= CFG_D;
> - }
> -
> - if (def->features & LM32_FEATURE_SHIFT) {
> - cfg |= CFG_S;
> - }
> -
> - if (def->features & LM32_FEATURE_SIGN_EXTEND) {
> - cfg |= CFG_X;
> - }
> -
> - if (def->features & LM32_FEATURE_I_CACHE) {
> - cfg |= CFG_IC;
> - }
> -
> - if (def->features & LM32_FEATURE_D_CACHE) {
> - cfg |= CFG_DC;
> - }
> -
> - if (def->features & LM32_FEATURE_CYCLE_COUNT) {
> - cfg |= CFG_CC;
> - }
> -
> - cfg |= (def->num_interrupts << CFG_INT_SHIFT);
> - cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
> - cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
> - cfg |= (def->revision << CFG_REV_SHIFT);
> -
> - return cfg;
> + list = object_class_get_list(TYPE_LM32_CPU, false);
> + list = g_slist_sort(list, lm32_cpu_list_compare);
> + cpu_fprintf(f, "Available CPUs:\n");
> + g_slist_foreach(list, lm32_cpu_list_entry, &s);
> + g_slist_free(list);
> }
>
> CPULM32State *cpu_lm32_init(const char *cpu_model)
> {
> + LM32CPU *cpu;
> CPULM32State *env;
> - const LM32Def *def;
> static int tcg_initialized;
>
> - def = cpu_lm32_find_by_name(cpu_model);
> - if (!def) {
> + if (object_class_by_name(cpu_model) == NULL) {
> return NULL;
> }
> + cpu = LM32_CPU(object_new(cpu_model));
> + env = &cpu->env;
>
> - env = g_malloc0(sizeof(CPULM32State));
> -
> - env->features = def->features;
> - env->num_bps = def->num_breakpoints;
> - env->num_wps = def->num_watchpoints;
> - env->cfg = cfg_by_def(def);
> - env->flags = 0;
> -
> - cpu_exec_init(env);
> - cpu_state_reset(env);
> qemu_init_vcpu(env);
>
> if (!tcg_initialized) {
--
Michael
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 12/12] target-xtensa: QOM'ify CPU
2012-03-15 22:10 ` jcmvbkbc
@ 2012-03-15 23:10 ` Max Filippov
0 siblings, 0 replies; 175+ messages in thread
From: Max Filippov @ 2012-03-15 23:10 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
>> Let xtensa_cpu_list() enumerate CPU classes alphabetically.
>>
>> Signed-off-by: Andreas Färber<afaerber@suse.de>
>> ---
With this patch applied qemu aborts on unit tests with the following message:
qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel ./test_b.tst
**
ERROR:/home/dumb/ws/m/awt/emu/xtensa/qemu/qom/object.c:156:type_get_parent: assertion failed: (type->parent_type != NULL)
make: *** [run-test_b.tst] Aborted
(gdb) bt
#0 0x00007ffff5f57285 in raise () from /lib64/libc.so.6
#1 0x00007ffff5f58b9b in abort () from /lib64/libc.so.6
#2 0x00007ffff771641d in g_assertion_message () from /lib64/libglib-2.0.so.0
#3 0x00007ffff7716942 in g_assertion_message_expr () from /lib64/libglib-2.0.so.0
#4 0x000055555565f23e in type_get_parent (type=0x55555625c8b0) at /home/dumb/ws/m/awt/emu/xtensa/qemu/qom/object.c:156
#5 0x000055555565f4ec in type_initialize (ti=0x55555625c8b0) at /home/dumb/ws/m/awt/emu/xtensa/qemu/qom/object.c:225
#6 0x00005555556602f4 in object_class_by_name (typename=0x7fffffffdc15 "dc232b") at
/home/dumb/ws/m/awt/emu/xtensa/qemu/qom/object.c:543
#7 0x00005555556dd27b in cpu_xtensa_init (cpu_model=0x7fffffffdc15 "dc232b") at
/home/dumb/ws/m/awt/emu/xtensa/qemu/target-xtensa/helper.c:85
#8 0x0000555555716703 in sim_init (ram_size=134217728, boot_device=0x7fffffffd6d0 "cad", kernel_filename=0x555556256060
"./test_b.tst", kernel_cmdline=0x55555572aeb2 "", initrd_filename=0x0, cpu_model=
0x7fffffffdc15 "dc232b") at /home/dumb/ws/m/awt/emu/xtensa/qemu/hw/xtensa_sim.c:55
#9 0x00005555557168e5 in xtensa_sim_init (ram_size=134217728, boot_device=0x7fffffffd6d0 "cad",
kernel_filename=0x555556256060 "./test_b.tst", kernel_cmdline=0x55555572aeb2 "", initrd_filename=0x0, cpu_model=
0x7fffffffdc15 "dc232b") at /home/dumb/ws/m/awt/emu/xtensa/qemu/hw/xtensa_sim.c:102
#10 0x000055555561f0bb in main (argc=9, argv=0x7fffffffd7f8, envp=0x7fffffffd848) at
/home/dumb/ws/m/awt/emu/xtensa/qemu/vl.c:3496
(gdb) frame 4
#4 0x000055555565f23e in type_get_parent (type=0x55555625c8b0) at /home/dumb/ws/m/awt/emu/xtensa/qemu/qom/object.c:156
156 g_assert(type->parent_type != NULL);
(gdb) p *type
$6 = {name = 0x555556255fa0 "dc232b", class_size = 7848, instance_size = 75232, class_init = 0x5555556b4a6c
<core_class_init>, class_finalize = 0, class_data = 0x0, instance_init = 0, instance_finalize = 0, abstract =
false, parent = 0x555556255fc0 "xtensa-cpu", parent_type = 0x0, class = 0x555556264a90, num_interfaces = 0,
interfaces = {{parent = 0x0, interface_initfn = 0, type = 0x0} <repeats 32 times>}}
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU
2012-03-14 7:32 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
@ 2012-03-23 16:53 ` Andreas Färber
0 siblings, 0 replies; 175+ messages in thread
From: Andreas Färber @ 2012-03-23 16:53 UTC (permalink / raw)
To: gxt; +Cc: qemu-devel, Anthony Liguori
Am 14.03.2012 08:32, schrieb Guan Xuetao:
> On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
>> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
>> the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to
>> target-arm and faces a similar issue of CPU-dependent init code, so let's
>> tackle it next.
>>
>> Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS,
>> so that the target-unicore32 author gets notified of patches against his code.
>>
>> Patch 2, based on feedback from Guan Xuetao, changes the license of most
>> target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a
>> qemu_malloc() -> g_malloc() substitution that he can't relicense at this time,
>> so leave that as GPLv2 and declare my following patches explicitly as GPLv2+.
>>
>> Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h header
>> can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2 for now.
>>
>> Patches 4-7 move code out of the uc32_cpu_init() function and into classes.
>
> I pulled the latest qemu code, but these patches seems to rely on the
> former qom-cpu v4 series.
That series has been applied in the meantime, so unicore32 should no
longer depend on other series.
> Could you tell me where I can pull the testable branch/tree?
Sorry, repo.or.cz was having problems at the time of posting, this v1
series is now available at:
git://repo.or.cz/qemu/afaerber.git qom-cpu-unicore32.v1
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu-unicore32.v1
I've added links to the Wiki for my work-in-progress branches on GitHub:
http://wiki.qemu.org/Features/QOM/CPU
Today I've reworked the preceding ARM series and rebased onto v5; I
still need to revisit the table-driven class initialization before
sending out a v2. MAINTAINERS and licenses are already adjusted.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 11/12] target-sparc: QOM'ify CPU
2012-03-14 20:16 ` Blue Swirl
@ 2012-03-23 17:27 ` Andreas Färber
2012-03-24 13:19 ` Blue Swirl
0 siblings, 1 reply; 175+ messages in thread
From: Andreas Färber @ 2012-03-23 17:27 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel
Am 14.03.2012 21:16, schrieb Blue Swirl:
> On Wed, Mar 14, 2012 at 17:53, Andreas Färber <afaerber@suse.de> wrote:
>> diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
>> new file mode 100644
>> index 0000000..15dcf84
>> --- /dev/null
>> +++ b/target-sparc/cpu-qom.h
[...]
>> +/**
>> + * SPARCCPUClass:
>> + * @parent_reset: The parent class' reset handler.
>> + *
>> + * A SPARC CPU model.
>> + */
>> +typedef struct SPARCCPUClass {
>> + /*< private >*/
>> + CPUClass parent_class;
>> + /*< public >*/
>> +
>> + void (*parent_reset)(CPUState *cpu);
>> +
>> + target_ulong iu_version;
>> + uint32_t fpu_version;
>> + uint32_t mmu_version;
>> + uint32_t mmu_bm;
>> + uint32_t mmu_ctpr_mask;
>> + uint32_t mmu_cxr_mask;
>> + uint32_t mmu_sfsr_mask;
>> + uint32_t mmu_trcr_mask;
>> + uint32_t mxcc_version;
>> + uint32_t features;
>> + uint32_t nwindows;
>> + uint32_t maxtl;
>> +} SPARCCPUClass;
>> +
>> +/**
>> + * SPARCCPU:
>> + * @env: Legacy CPU state.
>> + *
>> + * A SPARC CPU.
>> + */
>> +typedef struct SPARCCPU {
>> + /*< private >*/
>> + CPUState parent_obj;
>> + /*< public >*/
>> +
>> + CPUSPARCState env;
>> +
>> + target_ulong iu_version;
>> + uint32_t fpu_version;
>> + uint32_t mmu_version;
>> + uint32_t features;
>> + uint32_t nwindows;
>> +} SPARCCPU;
>
> The fields do not look correct at all, the same fields are in both
> structs.
Formerly you had the model of an array of sparc_def_t structs, which you
would duplicate and then associate with CPUSPARCState, modifying the
duplicate.
SPARCCPUClass exists only once though. Therefore we cannot modify
classes based on command line parameters and must do so on the instance
instead. I have therefore duplicated some fields from class to instance
as you have noticed, initialized the object's value from the class' and
let any -cpu options modify the latter.
The same pattern has been used for arm and i386. On arm my v5 postpones
this by doing a bare-bones conversion for now; on x86 the only request
so far was to set the values via QOM properties.
> Moreover Sparc32 and Sparc64 fields are mixed. Maybe I don't
> fully understand the conversion.
Mixed fields likely means they were mixed in your original code. It is a
mostly mechanical conversion.
> Would it be possible to make a common parent class which is then
> specialized by Sparc32 and Sparc64 classes? There are many common
> fields but also many 32/64 specific ones. Also cpu_common.c, cpu32.c
> and cpu64.c to avoid #ifdeffery?
That is possible, but I would ask that you do such split-ups later.
Discussions for arm and ppc have shown that the structure of subclasses
in lack of multi-inheritence can be a tricky and controversial issue and
requires a lot of target knowledge that I do not posses for sparc.
Also, restructuring target code, e.g., into multiple files is orthogonal
to the goal of QOM'ifying all target CPUs and doing cleanups in common code.
If you think this is heading into a totally wrong direction due to some
in-progress work of yours, we could strip it down like target-arm v5,
but ATM I don't believe so. ;)
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
* Re: [Qemu-devel] [RFC 11/12] target-sparc: QOM'ify CPU
2012-03-23 17:27 ` Andreas Färber
@ 2012-03-24 13:19 ` Blue Swirl
0 siblings, 0 replies; 175+ messages in thread
From: Blue Swirl @ 2012-03-24 13:19 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
On Fri, Mar 23, 2012 at 17:27, Andreas Färber <afaerber@suse.de> wrote:
> Am 14.03.2012 21:16, schrieb Blue Swirl:
>> On Wed, Mar 14, 2012 at 17:53, Andreas Färber <afaerber@suse.de> wrote:
>>> diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
>>> new file mode 100644
>>> index 0000000..15dcf84
>>> --- /dev/null
>>> +++ b/target-sparc/cpu-qom.h
> [...]
>>> +/**
>>> + * SPARCCPUClass:
>>> + * @parent_reset: The parent class' reset handler.
>>> + *
>>> + * A SPARC CPU model.
>>> + */
>>> +typedef struct SPARCCPUClass {
>>> + /*< private >*/
>>> + CPUClass parent_class;
>>> + /*< public >*/
>>> +
>>> + void (*parent_reset)(CPUState *cpu);
>>> +
>>> + target_ulong iu_version;
>>> + uint32_t fpu_version;
>>> + uint32_t mmu_version;
>>> + uint32_t mmu_bm;
>>> + uint32_t mmu_ctpr_mask;
>>> + uint32_t mmu_cxr_mask;
>>> + uint32_t mmu_sfsr_mask;
>>> + uint32_t mmu_trcr_mask;
>>> + uint32_t mxcc_version;
>>> + uint32_t features;
>>> + uint32_t nwindows;
>>> + uint32_t maxtl;
>>> +} SPARCCPUClass;
>>> +
>>> +/**
>>> + * SPARCCPU:
>>> + * @env: Legacy CPU state.
>>> + *
>>> + * A SPARC CPU.
>>> + */
>>> +typedef struct SPARCCPU {
>>> + /*< private >*/
>>> + CPUState parent_obj;
>>> + /*< public >*/
>>> +
>>> + CPUSPARCState env;
>>> +
>>> + target_ulong iu_version;
>>> + uint32_t fpu_version;
>>> + uint32_t mmu_version;
>>> + uint32_t features;
>>> + uint32_t nwindows;
>>> +} SPARCCPU;
>>
>> The fields do not look correct at all, the same fields are in both
>> structs.
>
> Formerly you had the model of an array of sparc_def_t structs, which you
> would duplicate and then associate with CPUSPARCState, modifying the
> duplicate.
> SPARCCPUClass exists only once though. Therefore we cannot modify
> classes based on command line parameters and must do so on the instance
> instead. I have therefore duplicated some fields from class to instance
> as you have noticed, initialized the object's value from the class' and
> let any -cpu options modify the latter.
> The same pattern has been used for arm and i386. On arm my v5 postpones
> this by doing a bare-bones conversion for now; on x86 the only request
> so far was to set the values via QOM properties.
>
>> Moreover Sparc32 and Sparc64 fields are mixed. Maybe I don't
>> fully understand the conversion.
>
> Mixed fields likely means they were mixed in your original code. It is a
> mostly mechanical conversion.
I see, this is only for the sparc_def_t structure.
>> Would it be possible to make a common parent class which is then
>> specialized by Sparc32 and Sparc64 classes? There are many common
>> fields but also many 32/64 specific ones. Also cpu_common.c, cpu32.c
>> and cpu64.c to avoid #ifdeffery?
>
> That is possible, but I would ask that you do such split-ups later.
> Discussions for arm and ppc have shown that the structure of subclasses
> in lack of multi-inheritence can be a tricky and controversial issue and
> requires a lot of target knowledge that I do not posses for sparc.
> Also, restructuring target code, e.g., into multiple files is orthogonal
> to the goal of QOM'ifying all target CPUs and doing cleanups in common code.
>
> If you think this is heading into a totally wrong direction due to some
> in-progress work of yours, we could strip it down like target-arm v5,
> but ATM I don't believe so. ;)
No, the patch is fine as is.
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 175+ messages in thread
end of thread, other threads:[~2012-03-24 13:19 UTC | newest]
Thread overview: 175+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-03-04 20:32 [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 1/3] kvmclock: Always register type Andreas Färber
2012-03-05 9:23 ` Avi Kivity
2012-03-10 1:35 ` Andreas Färber
2012-03-12 10:36 ` Avi Kivity
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 2/3] qom: Register QOM infrastructure early Andreas Färber
2012-03-04 20:32 ` [Qemu-devel] [PATCH v4 3/3] qom: Add QOM support to user emulators Andreas Färber
2012-03-07 14:11 ` Luiz Capitulino
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 00/44] Introduce QOM CPU Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 01/44] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH v4 02/44] Rename cpu_reset() to cpu_state_reset() Andreas Färber
2012-03-13 18:02 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 03/44] monitor: Don't access registers through CPUState Andreas Färber
2012-03-13 18:02 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions Andreas Färber
2012-03-13 18:03 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 05/44] target-lm32: Typedef struct CPULM32State Andreas Färber
2012-03-13 18:04 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 06/44] target-microblaze: Typedef struct CPUMBState Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 07/44] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State Andreas Färber
2012-03-13 18:05 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 09/44] hw/mc146818: Drop unneeded #includes Andreas Färber
2012-03-13 18:07 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 10/44] linux-user: Don't overuse CPUState Andreas Färber
2012-03-13 18:08 ` Anthony Liguori
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 11/44] darwin-user: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 12/44] bsd-user: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: " Andreas Färber
2012-03-13 18:10 ` Anthony Liguori
2012-03-14 20:50 ` Andreas Färber
2012-03-14 20:58 ` Peter Maydell
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 14/44] target-arm: " Andreas Färber
2012-03-14 14:39 ` Peter Maydell
2012-03-14 18:33 ` Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 15/44] target-cris: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 16/44] target-i386: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 17/44] target-lm32: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 18/44] target-m68k: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 19/44] target-microblaze: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 20/44] target-mips: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 21/44] target-ppc: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 22/44] target-s390x: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 23/44] target-sh4: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 24/44] target-sparc: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 25/44] target-unicore32: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 26/44] target-xtensa: " Andreas Färber
2012-03-10 2:27 ` [Qemu-devel] [PATCH RFC v4 27/44] arm-semi: Don't use CPUState Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 28/44] m68k-semi: " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 29/44] xtensa-semi: " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 30/44] alpha hw/: " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 31/44] arm " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 32/44] cris " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 33/44] i386 " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 34/44] lm32 " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 35/44] m68k " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 36/44] microblaze " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 37/44] mips " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 38/44] ppc " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 39/44] s390x " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 40/44] sh4 " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 41/44] sparc " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 42/44] xtensa " Andreas Färber
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 43/44] Rename CPUState -> CPUArchState Andreas Färber
2012-03-13 18:06 ` Andreas Färber
2012-03-13 18:11 ` Anthony Liguori
2012-03-10 2:28 ` [Qemu-devel] [PATCH RFC v4 44/44] qom: Introduce CPU class Andreas Färber
2012-03-12 9:38 ` Igor Mammedov
2012-03-13 12:13 ` Andreas Färber
2012-03-13 12:20 ` Paolo Bonzini
2012-03-13 12:53 ` Andreas Färber
2012-03-13 13:03 ` Paolo Bonzini
2012-03-13 18:16 ` Anthony Liguori
2012-03-14 20:37 ` Igor Mitsyanko
2012-03-14 19:48 ` Anthony Liguori
2012-03-14 19:57 ` Andreas Färber
2012-03-14 20:01 ` Anthony Liguori
2012-03-14 20:37 ` Andreas Färber
2012-03-14 20:40 ` Anthony Liguori
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 00/20] QOM'ify ARM CPU Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH v2 RESEND 01/20] qom: Introduce object_class_get_list() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 02/20] target-arm: Introduce QOM ARMCPUClass Andreas Färber
2012-03-13 12:31 ` Igor Mitsyanko
2012-03-13 17:58 ` Andreas Färber
2012-03-13 18:04 ` Eric Blake
2012-03-13 18:09 ` Eric Blake
2012-03-13 18:05 ` Paolo Bonzini
2012-03-13 18:12 ` Peter Maydell
2012-03-14 8:58 ` Igor Mitsyanko
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 03/20] target-arm: Embed CPUARMState in QOM ARMCPU Andreas Färber
2012-03-13 13:18 ` Paolo Bonzini
2012-03-14 22:30 ` Andreas Färber
2012-03-15 9:43 ` Paolo Bonzini
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 04/20] target-arm: Prepare model-specific class_init function Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 05/20] target-arm: Overwrite reset handler for ti925t Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 06/20] target-arm: Move CPU feature flags out of CPUState Andreas Färber
2012-03-15 18:56 ` Paul Brook
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 07/20] target-arm: No longer abort on unhandled CPUIDs on reset Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1 and c0_c2 in ARMCPUClass Andreas Färber
2012-03-15 19:08 ` Paul Brook
2012-03-15 19:20 ` Peter Maydell
2012-03-15 19:29 ` Alexey Starikovskiy
2012-03-15 19:42 ` Peter Maydell
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 09/20] target-arm: Store CTR " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 10/20] target-arm: Store SCTLR " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 11/20] target-arm: Drop JTAG_ID documentation Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 12/20] target-arm: Move the PXA270's iwMMXt reset to pxa270_reset() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 13/20] target-arm: Store VFP FPSID register in ARMCPUClass Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 14/20] target-arm: Store VFP MVFR0 and MVFR1 " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 15/20] target-arm: Store CLIDR " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 16/20] target-arm: Store CCSIDRs " Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 17/20] target-arm: Kill off cpu_reset_model_id() Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 18/20] target-arm: Add cpuid-{variant, revision} properties to CPU Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 19/20] target-arm: Simplify pxa270 CPU classes Andreas Färber
2012-03-10 16:53 ` [Qemu-devel] [PATCH RFC v4 20/20] hw/integratorcp: Add child property for CPU Andreas Färber
2012-03-13 19:52 ` [Qemu-devel] [PATCH v4 0/3] Prepare QOM support for machines and CPU Anthony Liguori
2012-03-14 1:39 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32 Andreas Färber
2012-03-14 7:44 ` Guan Xuetao
2012-03-14 1:39 ` [Qemu-devel] [PATCH 2/7] target-unicore32: Relicense to GPLv2+ Andreas Färber
2012-03-14 7:53 ` Guan Xuetao
2012-03-14 10:46 ` Andreas Färber
2012-03-14 20:03 ` Blue Swirl
2012-03-14 21:09 ` Stefan Weil
2012-03-14 21:20 ` Anthony Liguori
2012-03-14 1:39 ` [Qemu-devel] [PATCH 3/7] target-unicore32: QOM'ify CPU Andreas Färber
2012-03-14 7:56 ` Guan Xuetao
2012-03-14 10:56 ` Andreas Färber
2012-03-15 1:04 ` Guan Xuetao
2012-03-14 1:39 ` [Qemu-devel] [PATCH 4/7] target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys " Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags " Andreas Färber
2012-03-14 1:39 ` [Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr " Andreas Färber
2012-03-14 7:32 ` [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU Guan Xuetao
2012-03-23 16:53 ` Andreas Färber
2012-03-14 20:02 ` Blue Swirl
2012-03-14 23:23 ` Anthony Liguori
2012-03-14 16:01 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 01/12] target-sh4: QOM'ify CPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 03/12] hw/sh7750: Use SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 05/12] target-sh4: Make increment_urc() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 06/12] target-sh4: Make find_*tlb_entry() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() " Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU Andreas Färber
2012-03-14 16:01 ` [Qemu-devel] [PATCH RFC 12/12] hw/sh7750: QOM'ify SH7750 SoC Andreas Färber
2012-03-14 16:06 ` [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and " Peter Maydell
2012-03-14 18:25 ` Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 02/12] target-mips: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 03/12] target-m68k: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 04/12] target-alpha: " Andreas Färber
2012-03-14 17:59 ` Richard Henderson
2012-03-14 17:53 ` [Qemu-devel] [RFC 05/12] target-i386: " Andreas Färber
2012-03-15 19:30 ` Eduardo Habkost
2012-03-14 17:53 ` [RFC 06/12] target-ppc: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] " Andreas Färber
2012-03-14 17:53 ` [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 09/12] target-lm32: " Andreas Färber
2012-03-15 22:42 ` Michael Walle
2012-03-14 17:53 ` [Qemu-devel] [RFC 10/12] target-microblaze: " Andreas Färber
2012-03-14 17:53 ` [Qemu-devel] [RFC 11/12] target-sparc: " Andreas Färber
2012-03-14 20:16 ` Blue Swirl
2012-03-23 17:27 ` Andreas Färber
2012-03-24 13:19 ` Blue Swirl
2012-03-14 17:53 ` [Qemu-devel] [RFC 12/12] target-xtensa: " Andreas Färber
2012-03-15 22:10 ` jcmvbkbc
2012-03-15 23:10 ` Max Filippov
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